diff --git a/Hardware/CRC.vhd b/Hardware/CRC.vhd deleted file mode 100644 index 5ef9fd0..0000000 --- a/Hardware/CRC.vhd +++ /dev/null @@ -1,63 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity crc is - generic ( - CRC_WIDTH : positive; - DWIDTH : positive - ); - port ( - clk : in std_logic; - -- Kontrollsignale - reset : in std_logic; - enable : in std_logic; - initial_value : in std_logic_vector(CRC_WIDTH-1 downto 0); - polynomial : in std_logic_vector(CRC_WIDTH-1 downto 0); - -- Datensignale - data : in std_logic_vector(DWIDTH-1 downto 0); - checksum : out std_logic_vector(CRC_WIDTH-1 downto 0) - ); -end crc; - -architecture rtl of crc is - - -- Interne Signale fuer CRC Pruefsumme - signal checksum_i : std_logic_vector(CRC_WIDTH-1 downto 0); - signal nextChecksum : std_logic_vector(CRC_WIDTH-1 downto 0); - -begin - -- Kombinatorik fuer CRC-Berechnung - ProcNextCRC: process (data, checksum_i) - variable mix: std_logic_vector(CRC_WIDTH-1 downto 0); - variable MSB : std_logic; - begin - mix := checksum_i; - for i in data'range loop - -- Pruefen ob MSB gesetzt ist - MSB := mix(mix'length-1); - -- neues Bit reinschieben - mix := mix(mix'length-2 downto 0) & data(i); - -- XOR Verknuepfung - if MSB = '1' then - mix := mix XOR polynomial; - end if; - end loop; - nextChecksum <= mix; - end process; - - -- Register zum Speichern der CRC-Pruefsumme - Reg: process (clk) - begin - if rising_edge(clk) then - if reset = '1' then - checksum_i <= initial_value; - elsif enable = '1' then - checksum_i <= nextChecksum; - end if; - end if; - end process; - - checksum <= checksum_i; - -end architecture; diff --git a/Hardware/aci_crc_dma/.gitignore b/Hardware/aci_crc_dma/.gitignore index 67f001d..ff42ea2 100644 --- a/Hardware/aci_crc_dma/.gitignore +++ b/Hardware/aci_crc_dma/.gitignore @@ -86,4 +86,7 @@ vivado_pid*.str # DO NOT ignore images as bitmap files -!*.bmp \ No newline at end of file +!*.bmp + +# do not ignore stimuli file for axil_master_with_rom IP +!*.stm \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml index 3dd4783..c6eade9 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml @@ -2,10 +2,55 @@ Composite Fileset - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1_ooc.xdc b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1_ooc.xdc new file mode 100644 index 0000000..7fac2b2 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1_ooc.xdc @@ -0,0 +1,10 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ + +################################################################################ \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/hdl/axis_master_test_wrapper.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd similarity index 60% rename from Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/hdl/axis_master_test_wrapper.vhd rename to Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd index e854fda..711c981 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/hdl/axis_master_test_wrapper.vhd +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd @@ -2,23 +2,23 @@ --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Sat Feb 1 17:34:52 2025 +--Date : Sun Feb 2 01:00:12 2025 --Host : BiermannSurface running 64-bit major release (build 9200) ---Command : generate_target axis_master_test_wrapper.bd ---Design : axis_master_test_wrapper +--Command : generate_target axi_crc_dma_sim_1_wrapper.bd +--Design : axi_crc_dma_sim_1_wrapper --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity axis_master_test_wrapper is -end axis_master_test_wrapper; +entity axi_crc_dma_sim_1_wrapper is +end axi_crc_dma_sim_1_wrapper; -architecture STRUCTURE of axis_master_test_wrapper is - component axis_master_test is - end component axis_master_test; +architecture STRUCTURE of axi_crc_dma_sim_1_wrapper is + component axi_crc_dma_sim_1 is + end component axi_crc_dma_sim_1; begin -axis_master_test_i: component axis_master_test +axi_crc_dma_sim_1_i: component axi_crc_dma_sim_1 ; end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xml new file mode 100644 index 0000000..3982670 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xml @@ -0,0 +1,1256 @@ + + + xilinx.com + customized_ip + axi_crc_dma_sim_1_axi3_slave_verif_0_0 + 1.0 + + + S_AXI + + + + + + + + + AWADDR + + + S_AXI_AWADDR + + + + + AWLEN + + + S_AXI_AWLEN + + + + + AWSIZE + + + S_AXI_AWSIZE + + + + + AWBURST + + + S_AXI_AWBURST + + + + + AWVALID + + + S_AXI_AWVALID + + + + + AWREADY + + + S_AXI_AWREADY + + + + + WDATA + + + S_AXI_WDATA + + + + + WSTRB + + + S_AXI_WSTRB + + + + + WLAST + + + S_AXI_WLAST + + + + + WVALID + + + S_AXI_WVALID + + + + + WREADY + + + S_AXI_WREADY + + + + + BRESP + + + S_AXI_BRESP + + + + + BVALID + + + S_AXI_BVALID + + + + + BREADY + + + S_AXI_BREADY + + + + + ARID + + + S_AXI_ARID + + + + + ARADDR + + + S_AXI_ARADDR + + + + + ARLEN + + + S_AXI_ARLEN + + + + + ARSIZE + + + S_AXI_ARSIZE + + + + + ARBURST + + + S_AXI_ARBURST + + + + + ARVALID + + + S_AXI_ARVALID + + + + + ARREADY + + + S_AXI_ARREADY + + + + + RID + + + S_AXI_RID + + + + + RDATA + + + S_AXI_RDATA + + + + + RRESP + + + S_AXI_RRESP + + + + + RLAST + + + S_AXI_RLAST + + + + + RVALID + + + S_AXI_RVALID + + + + + RREADY + + + S_AXI_RREADY + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI3 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 1 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 2 + + + none + + + + + NUM_WRITE_OUTSTANDING + 2 + + + none + + + + + MAX_BURST_LENGTH + 16 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RESETN + + + + + + + RST + + + RESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK + + + + + + + CLK + + + CLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + RESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + S_AXI + S_AXI + + reg0 + reg0 + 0x0 + 0x100000000 + 32 + register + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axi3_slave_verif + + + outputProductCRC + 9:9592e3e6 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axi_crc_dma_sim_1_axi3_slave_verif_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:9592e3e6 + + + + + + + CLK + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + RESETN + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_ARVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARID + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_ARBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + S_AXI_RVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_RREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RLAST + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_AWVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_AWREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_AWLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_AWSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_AWBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + S_AXI_WVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_WREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + S_AXI_WLAST + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_BVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_BREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + + + DWIDTH + Dwidth + 32 + + + IDWIDTH + Idwidth + 1 + + + MAX_BURSTLEN + Max Burstlen + 16 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axi_crc_dma_sim_1_axi3_slave_verif_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx.com:module_ref:axi3_slave_verif:1.0 + + + DWIDTH + Dwidth + 32 + + + IDWIDTH + Idwidth + 1 + + + MAX_BURSTLEN + Max Burstlen + 16 + + + Component_Name + axi_crc_dma_sim_1_axi3_slave_verif_0_0 + + + + + axi3_slave_verif_v1_0 + module_ref + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/sim/axi_crc_dma_sim_1_axi3_slave_verif_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/sim/axi_crc_dma_sim_1_axi3_slave_verif_0_0.vhd new file mode 100644 index 0000000..b88bcc7 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/sim/axi_crc_dma_sim_1_axi3_slave_verif_0_0.vhd @@ -0,0 +1,204 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:axi3_slave_verif:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axi_crc_dma_sim_1_axi3_slave_verif_0_0 IS + PORT ( + CLK : IN STD_LOGIC; + RESETN : IN STD_LOGIC; + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); +END axi_crc_dma_sim_1_axi3_slave_verif_0_0; + +ARCHITECTURE axi_crc_dma_sim_1_axi3_slave_verif_0_0_arch OF axi_crc_dma_sim_1_axi3_slave_verif_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axi3_slave_verif_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axi3_slave_verif IS + GENERIC ( + DWIDTH : INTEGER; + IDWIDTH : INTEGER; + MAX_BURSTLEN : INTEGER + ); + PORT ( + CLK : IN STD_LOGIC; + RESETN : IN STD_LOGIC; + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT axi3_slave_verif; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXI_ARVALID: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS" & +"_PER_BYTE 0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; +BEGIN + U0 : axi3_slave_verif + GENERIC MAP ( + DWIDTH => 32, + IDWIDTH => 1, + MAX_BURSTLEN => 16 + ) + PORT MAP ( + CLK => CLK, + RESETN => RESETN, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARID => S_AXI_ARID, + S_AXI_ARLEN => S_AXI_ARLEN, + S_AXI_ARSIZE => S_AXI_ARSIZE, + S_AXI_ARBURST => S_AXI_ARBURST, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RID => S_AXI_RID, + S_AXI_RLAST => S_AXI_RLAST, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWLEN => S_AXI_AWLEN, + S_AXI_AWSIZE => S_AXI_AWSIZE, + S_AXI_AWBURST => S_AXI_AWBURST, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WLAST => S_AXI_WLAST, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_BRESP => S_AXI_BRESP + ); +END axi_crc_dma_sim_1_axi3_slave_verif_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml index 47c3720..e5b9a3a 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml @@ -187,7 +187,7 @@ FREQ_HZ - 100000000 + none @@ -565,6 +565,47 @@ + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axil_master_with_rom + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:8286588d + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axi_crc_dma_sim_1_axil_master_with_rom_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:8286588d + + + + interrupt_in @@ -573,7 +614,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -595,7 +636,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -614,7 +655,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -626,7 +667,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -641,7 +682,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -656,7 +697,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -672,7 +713,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -688,7 +729,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -700,7 +741,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -712,7 +753,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -731,7 +772,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -750,7 +791,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -765,7 +806,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -780,7 +821,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -796,7 +837,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -812,7 +853,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -824,7 +865,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -839,7 +880,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -855,7 +896,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -871,7 +912,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -883,7 +924,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -895,7 +936,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -914,7 +955,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -927,7 +968,7 @@ STIM_FILENAME Stim Filename - ../../stimuli.mem + ../../axi_crc_dma_sim.mem HAS_FINISHED_OUT @@ -953,12 +994,33 @@ ACTIVE_LOW + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/85f6/sources_1/new/axilm_rom.vhd + vhdlSource + + + ../../ipshared/85f6/sources_1/new/axil_master_with_rom.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd + vhdlSource + xil_defaultlib + + + axil_master_with_rom STIM_FILENAME Stim Filename - ../../stimuli.mem + ../../axi_crc_dma_sim.mem Component_Name @@ -992,7 +1054,7 @@ - + @@ -1024,6 +1086,7 @@ + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd new file mode 100644 index 0000000..2622482 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd @@ -0,0 +1,178 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: wg:user:axil_master_with_rom:1.0 +-- IP Revision: 19 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axi_crc_dma_sim_1_axil_master_with_rom_0_0 IS + PORT ( + interrupt_in : IN STD_LOGIC; + M_AXIL_ACLK : IN STD_LOGIC; + M_AXIL_ARESETN : IN STD_LOGIC; + M_AXIL_ARREADY : IN STD_LOGIC; + M_AXIL_ARVALID : OUT STD_LOGIC; + M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXIL_RREADY : OUT STD_LOGIC; + M_AXIL_RVALID : IN STD_LOGIC; + M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXIL_AWREADY : IN STD_LOGIC; + M_AXIL_AWVALID : OUT STD_LOGIC; + M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXIL_WREADY : IN STD_LOGIC; + M_AXIL_WVALID : OUT STD_LOGIC; + M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXIL_BREADY : OUT STD_LOGIC; + M_AXIL_BVALID : IN STD_LOGIC; + M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0) + ); +END axi_crc_dma_sim_1_axil_master_with_rom_0_0; + +ARCHITECTURE axi_crc_dma_sim_1_axil_master_with_rom_0_0_arch OF axi_crc_dma_sim_1_axil_master_with_rom_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axil_master_with_rom IS + GENERIC ( + STIM_FILENAME : STRING; + HAS_FINISHED_OUT : BOOLEAN; + HAS_INTERRUPT_IN : BOOLEAN; + REVISION_NO : INTEGER + ); + PORT ( + interrupt_in : IN STD_LOGIC; + finished_o : OUT STD_LOGIC; + M_AXIL_ACLK : IN STD_LOGIC; + M_AXIL_ARESETN : IN STD_LOGIC; + M_AXIL_ARREADY : IN STD_LOGIC; + M_AXIL_ARVALID : OUT STD_LOGIC; + M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXIL_RREADY : OUT STD_LOGIC; + M_AXIL_RVALID : IN STD_LOGIC; + M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXIL_AWREADY : IN STD_LOGIC; + M_AXIL_AWVALID : OUT STD_LOGIC; + M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXIL_WREADY : IN STD_LOGIC; + M_AXIL_WVALID : OUT STD_LOGIC; + M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXIL_BREADY : OUT STD_LOGIC; + M_AXIL_BVALID : IN STD_LOGIC; + M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT axil_master_with_rom; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" & +"SERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID"; +BEGIN + U0 : axil_master_with_rom + GENERIC MAP ( + STIM_FILENAME => "../../axi_crc_dma_sim.mem", + HAS_FINISHED_OUT => false, + HAS_INTERRUPT_IN => true, + REVISION_NO => 1 + ) + PORT MAP ( + interrupt_in => interrupt_in, + M_AXIL_ACLK => M_AXIL_ACLK, + M_AXIL_ARESETN => M_AXIL_ARESETN, + M_AXIL_ARREADY => M_AXIL_ARREADY, + M_AXIL_ARVALID => M_AXIL_ARVALID, + M_AXIL_ARADDR => M_AXIL_ARADDR, + M_AXIL_ARPROT => M_AXIL_ARPROT, + M_AXIL_RREADY => M_AXIL_RREADY, + M_AXIL_RVALID => M_AXIL_RVALID, + M_AXIL_RDATA => M_AXIL_RDATA, + M_AXIL_RRESP => M_AXIL_RRESP, + M_AXIL_AWREADY => M_AXIL_AWREADY, + M_AXIL_AWVALID => M_AXIL_AWVALID, + M_AXIL_AWADDR => M_AXIL_AWADDR, + M_AXIL_AWPROT => M_AXIL_AWPROT, + M_AXIL_WREADY => M_AXIL_WREADY, + M_AXIL_WVALID => M_AXIL_WVALID, + M_AXIL_WDATA => M_AXIL_WDATA, + M_AXIL_WSTRB => M_AXIL_WSTRB, + M_AXIL_BREADY => M_AXIL_BREADY, + M_AXIL_BVALID => M_AXIL_BVALID, + M_AXIL_BRESP => M_AXIL_BRESP + ); +END axi_crc_dma_sim_1_axil_master_with_rom_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml index 7ee223a..3b7be1e 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml @@ -436,6 +436,40 @@ + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_crc + + + outputProductCRC + 9:f02b2d15 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axi_crc_dma_sim_1_axis_crc_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:f02b2d15 + + + + CLK @@ -444,7 +478,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -456,7 +490,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -472,7 +506,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -488,7 +522,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -500,7 +534,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -516,7 +550,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -531,7 +565,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -546,7 +580,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -558,7 +592,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -574,7 +608,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -586,7 +620,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -598,7 +632,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -615,6 +649,16 @@ ACTIVE_LOW + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd + vhdlSource + xil_defaultlib + + + xilinx.com:module_ref:axis_crc:1.0 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0/sim/test_1_axis_crc_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd similarity index 90% rename from Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0/sim/test_1_axis_crc_0_0.vhd rename to Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd index e734694..ef33404 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0/sim/test_1_axis_crc_0_0.vhd +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd @@ -53,7 +53,7 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -ENTITY test_1_axis_crc_0_0 IS +ENTITY axi_crc_dma_sim_1_axis_crc_0_0 IS PORT ( CLK : IN STD_LOGIC; RESETN : IN STD_LOGIC; @@ -68,11 +68,11 @@ ENTITY test_1_axis_crc_0_0 IS M_AXIS_TLAST : OUT STD_LOGIC; M_AXIS_TREADY : IN STD_LOGIC ); -END test_1_axis_crc_0_0; +END axi_crc_dma_sim_1_axis_crc_0_0; -ARCHITECTURE test_1_axis_crc_0_0_arch OF test_1_axis_crc_0_0 IS +ARCHITECTURE axi_crc_dma_sim_1_axis_crc_0_0_arch OF axi_crc_dma_sim_1_axis_crc_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; - ATTRIBUTE DowngradeIPIdentifiedWarnings OF test_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes"; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axis_crc IS PORT ( CLK : IN STD_LOGIC; @@ -91,19 +91,19 @@ ARCHITECTURE test_1_axis_crc_0_0_arch OF test_1_axis_crc_0_0 IS END COMPONENT axis_crc; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; BEGIN U0 : axis_crc @@ -121,4 +121,4 @@ BEGIN M_AXIS_TLAST => M_AXIS_TLAST, M_AXIS_TREADY => M_AXIS_TREADY ); -END test_1_axis_crc_0_0_arch; +END axi_crc_dma_sim_1_axis_crc_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml index 7c4e2cf..aee8713 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml @@ -1448,6 +1448,40 @@ + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_dma + + + outputProductCRC + 9:e65ec1c3 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axi_crc_dma_sim_1_axis_dma_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:59:43 UTC 2025 + + + outputProductCRC + 9:e65ec1c3 + + + + CLK @@ -1456,7 +1490,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1468,7 +1502,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1484,7 +1518,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1500,7 +1534,39 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation + + + + + + FIFO_NUM_FREE + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + FIFO_NUM_AVAIL + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation @@ -1516,7 +1582,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1531,7 +1597,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1546,7 +1612,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1562,7 +1628,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1577,7 +1643,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1592,7 +1658,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1608,7 +1674,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1623,7 +1689,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1635,7 +1701,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1654,7 +1720,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1670,7 +1736,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1685,7 +1751,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1700,7 +1766,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1716,7 +1782,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1728,7 +1794,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1740,7 +1806,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1759,7 +1825,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1771,7 +1837,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1786,7 +1852,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1805,7 +1871,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1821,7 +1887,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1837,7 +1903,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1853,7 +1919,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1869,7 +1935,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1885,7 +1951,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1901,7 +1967,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1913,7 +1979,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1925,7 +1991,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1944,7 +2010,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1963,7 +2029,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1982,7 +2048,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -1997,7 +2063,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2012,7 +2078,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2027,7 +2093,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2046,7 +2112,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2062,7 +2128,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2078,7 +2144,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2094,7 +2160,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2110,7 +2176,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2126,7 +2192,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2142,7 +2208,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2154,7 +2220,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2169,7 +2235,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2188,7 +2254,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2204,7 +2270,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2216,7 +2282,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2232,7 +2298,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2244,7 +2310,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2256,7 +2322,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2275,7 +2341,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2294,7 +2360,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2309,7 +2375,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2325,7 +2391,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2340,7 +2406,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2355,7 +2421,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2367,7 +2433,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2383,7 +2449,7 @@ std_logic_vector - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2395,7 +2461,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2407,7 +2473,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -2432,6 +2498,21 @@ Max Burstlen 16 + + FIFO_AWIDTH + Fifo Awidth + 8 + + + polynomial_default + Polynomial Default + 0x04C11DB7 + + + initial_value_default + Initial Value Default + 0x00000000 + @@ -2441,6 +2522,16 @@ ACTIVE_LOW + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd + vhdlSource + xil_defaultlib + + + xilinx.com:module_ref:axis_dma:1.0 @@ -2458,6 +2549,21 @@ Max Burstlen 16 + + FIFO_AWIDTH + Fifo Awidth + 8 + + + polynomial_default + Polynomial Default + 0x04C11DB7 + + + initial_value_default + Initial Value Default + 0x00000000 + Component_Name axi_crc_dma_sim_1_axis_dma_0_0 @@ -2476,22 +2582,22 @@ - - - - + + + + - - - - - - - - - + + + + + + + + + @@ -2499,13 +2605,13 @@ - - + + - + - + @@ -2519,36 +2625,36 @@ - - - - + + + + - + - - - - - - - - - - + + + + + + + + + + - - + + - + - + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd new file mode 100644 index 0000000..45c5779 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd @@ -0,0 +1,354 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:axis_dma:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axi_crc_dma_sim_1_axis_dma_0_0 IS + PORT ( + CLK : IN STD_LOGIC; + RESETN : IN STD_LOGIC; + initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXIL_AWVALID : IN STD_LOGIC; + S_AXIL_AWREADY : OUT STD_LOGIC; + S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIL_WVALID : IN STD_LOGIC; + S_AXIL_WREADY : OUT STD_LOGIC; + S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXIL_BVALID : OUT STD_LOGIC; + S_AXIL_BREADY : IN STD_LOGIC; + S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXIL_ARVALID : IN STD_LOGIC; + S_AXIL_ARREADY : OUT STD_LOGIC; + S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIL_RVALID : OUT STD_LOGIC; + S_AXIL_RREADY : IN STD_LOGIC; + S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXI_ARREADY : IN STD_LOGIC; + M_AXI_ARVALID : OUT STD_LOGIC; + M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_RREADY : OUT STD_LOGIC; + M_AXI_RVALID : IN STD_LOGIC; + M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + M_AXI_RLAST : IN STD_LOGIC; + M_AXI_AWREADY : IN STD_LOGIC; + M_AXI_AWVALID : OUT STD_LOGIC; + M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_WREADY : IN STD_LOGIC; + M_AXI_WVALID : OUT STD_LOGIC; + M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_WLAST : OUT STD_LOGIC; + M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_BREADY : OUT STD_LOGIC; + M_AXI_BVALID : IN STD_LOGIC; + M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC + ); +END axi_crc_dma_sim_1_axis_dma_0_0; + +ARCHITECTURE axi_crc_dma_sim_1_axis_dma_0_0_arch OF axi_crc_dma_sim_1_axis_dma_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axis_dma_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_dma IS + GENERIC ( + DWIDTH : INTEGER; + IDWIDTH : INTEGER; + MAX_BURSTLEN : INTEGER; + FIFO_AWIDTH : INTEGER; + polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0); + initial_value_default : STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + PORT ( + CLK : IN STD_LOGIC; + RESETN : IN STD_LOGIC; + initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXIL_AWVALID : IN STD_LOGIC; + S_AXIL_AWREADY : OUT STD_LOGIC; + S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIL_WVALID : IN STD_LOGIC; + S_AXIL_WREADY : OUT STD_LOGIC; + S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXIL_BVALID : OUT STD_LOGIC; + S_AXIL_BREADY : IN STD_LOGIC; + S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXIL_ARVALID : IN STD_LOGIC; + S_AXIL_ARREADY : OUT STD_LOGIC; + S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIL_RVALID : OUT STD_LOGIC; + S_AXIL_RREADY : IN STD_LOGIC; + S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXI_ARREADY : IN STD_LOGIC; + M_AXI_ARVALID : OUT STD_LOGIC; + M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_RREADY : OUT STD_LOGIC; + M_AXI_RVALID : IN STD_LOGIC; + M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + M_AXI_RLAST : IN STD_LOGIC; + M_AXI_AWREADY : IN STD_LOGIC; + M_AXI_AWVALID : OUT STD_LOGIC; + M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_WREADY : IN STD_LOGIC; + M_AXI_WVALID : OUT STD_LOGIC; + M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXI_WLAST : OUT STD_LOGIC; + M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_BREADY : OUT STD_LOGIC; + M_AXI_BVALID : IN STD_LOGIC; + M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC + ); + END COMPONENT axis_dma; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS" & +"_PER_BYTE 0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" & +"ITS_PER_BYTE 0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_dma + GENERIC MAP ( + DWIDTH => 32, + IDWIDTH => 1, + MAX_BURSTLEN => 16, + FIFO_AWIDTH => 8, + polynomial_default => X"04C11DB7", + initial_value_default => X"00000000" + ) + PORT MAP ( + CLK => CLK, + RESETN => RESETN, + initial_value => initial_value, + polynomial => polynomial, + FIFO_NUM_FREE => FIFO_NUM_FREE, + FIFO_NUM_AVAIL => FIFO_NUM_AVAIL, + S_AXIL_AWADDR => S_AXIL_AWADDR, + S_AXIL_AWVALID => S_AXIL_AWVALID, + S_AXIL_AWREADY => S_AXIL_AWREADY, + S_AXIL_WDATA => S_AXIL_WDATA, + S_AXIL_WVALID => S_AXIL_WVALID, + S_AXIL_WREADY => S_AXIL_WREADY, + S_AXIL_WSTRB => S_AXIL_WSTRB, + S_AXIL_BVALID => S_AXIL_BVALID, + S_AXIL_BREADY => S_AXIL_BREADY, + S_AXIL_BRESP => S_AXIL_BRESP, + S_AXIL_ARADDR => S_AXIL_ARADDR, + S_AXIL_ARVALID => S_AXIL_ARVALID, + S_AXIL_ARREADY => S_AXIL_ARREADY, + S_AXIL_RDATA => S_AXIL_RDATA, + S_AXIL_RVALID => S_AXIL_RVALID, + S_AXIL_RREADY => S_AXIL_RREADY, + S_AXIL_RRESP => S_AXIL_RRESP, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_RREADY => M_AXI_RREADY, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RID => M_AXI_RID, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WID => M_AXI_WID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY + ); +END axi_crc_dma_sim_1_axis_dma_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_downsizer_0_0/axi_crc_dma_sim_1_axis_downsizer_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_downsizer_0_0/axi_crc_dma_sim_1_axis_downsizer_0_0.xml deleted file mode 100644 index a5b82ce..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_downsizer_0_0/axi_crc_dma_sim_1_axis_downsizer_0_0.xml +++ /dev/null @@ -1,721 +0,0 @@ - - - xilinx.com - customized_ip - axi_crc_dma_sim_1_axis_downsizer_0_0 - 1.0 - - - M_AXIS - - - - - - - TDATA - - - M_AXIS_TDATA - - - - - TLAST - - - M_AXIS_TLAST - - - - - TUSER - - - M_AXIS_TUSER - - - - - TVALID - - - M_AXIS_TVALID - - - - - TREADY - - - M_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 2 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 1 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXIS - - - - - - - TDATA - - - S_AXIS_TDATA - - - - - TLAST - - - S_AXIS_TLAST - - - - - TUSER - - - S_AXIS_TUSER - - - - - TVALID - - - S_AXIS_TVALID - - - - - TREADY - - - S_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 1 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - AXIS_ARESETN - - - - - - - RST - - - AXIS_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - AXIS_ACLK - - - - - - - CLK - - - AXIS_ACLK - - - - - - ASSOCIATED_BUSIF - M_AXIS:S_AXIS - - - ASSOCIATED_RESET - AXIS_ARESETN - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - AXIS_ACLK - - in - - - std_logic - dummy_view - - - - - - AXIS_ARESETN - - in - - - std_logic - dummy_view - - - - - - S_AXIS_TVALID - - in - - - std_logic - dummy_view - - - - - - S_AXIS_TDATA - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - S_AXIS_TLAST - - in - - - std_logic - dummy_view - - - - 0 - - - - - S_AXIS_TREADY - - out - - - std_logic - dummy_view - - - - - - S_AXIS_TUSER - - in - - - std_logic - dummy_view - - - - 0 - - - - - M_AXIS_TVALID - - out - - - std_logic - dummy_view - - - - - - M_AXIS_TDATA - - out - - 15 - 0 - - - - std_logic_vector - dummy_view - - - - - - M_AXIS_TLAST - - out - - - std_logic - dummy_view - - - - - - M_AXIS_TREADY - - in - - - std_logic - dummy_view - - - - 1 - - - - - M_AXIS_TUSER - - out - - - std_logic - dummy_view - - - - - - - - WIDTH_OUT - Width Out - 16 - - - SIZE_FACTOR - Size Factor - 2 - - - BIG_ENDIAN - Big Endian - false - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - axis_downsizer_v1_0 - - - WIDTH_OUT - Width Out - 16 - - - SIZE_FACTOR - Size Factor - 2 - - - BIG_ENDIAN - Big Endian - false - - - Component_Name - axi_crc_dma_sim_1_axis_downsizer_0_0 - - - - - axis_downsizer_v1_0 - package_project - 2 - - d:/projekte/edvs/vivado/vivado/ip_projects/axis_downsizer/axis_downsizer.srcs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2017.4 - - - - - - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xml index 3095768..c6dc207 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xml @@ -1134,6 +1134,48 @@ + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_fifo + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:bc9b0f83 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axi_crc_dma_sim_1_axis_fifo_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:bc9b0f83 + + + + S_AXI_ACLK @@ -1142,7 +1184,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1164,7 +1206,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1190,7 +1232,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1212,7 +1254,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1238,7 +1280,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1264,7 +1306,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1286,7 +1328,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1308,7 +1350,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1334,7 +1376,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1356,7 +1398,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1378,7 +1420,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1400,7 +1442,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1423,7 +1465,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1446,7 +1488,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1465,7 +1507,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1484,7 +1526,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1507,7 +1549,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1526,7 +1568,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1545,7 +1587,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1564,7 +1606,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1576,7 +1618,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1588,7 +1630,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1604,7 +1646,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1616,7 +1658,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1628,7 +1670,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1644,7 +1686,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1654,13 +1696,13 @@ out - 10 + 7 0 std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1672,7 +1714,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1684,7 +1726,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1696,7 +1738,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1712,7 +1754,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1724,7 +1766,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1736,7 +1778,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1752,7 +1794,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1762,13 +1804,13 @@ out - 10 + 7 0 std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1788,7 +1830,7 @@ FIFO_AWIDTH Fifo Awidth - 11 + 8 FIFO_DWIDTH @@ -1809,6 +1851,39 @@ ACTIVE_LOW + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/91a4/dmem_dp.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/91a4/bmem_dp.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/91a4/generic_fifo.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/91a4/axis_fifo.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axi_crc_dma_sim_1_axis_fifo_0_0.vhd + vhdlSource + xil_defaultlib + + + axis_fifo_v1_0 @@ -1824,7 +1899,7 @@ FIFO_AWIDTH Fifo Awidth - 11 + 8 FIFO_USE_BLOCKRAM @@ -1892,6 +1967,7 @@ + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/sim/axi_crc_dma_sim_1_axis_fifo_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/sim/axi_crc_dma_sim_1_axis_fifo_0_0.vhd new file mode 100644 index 0000000..f21e407 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/sim/axi_crc_dma_sim_1_axis_fifo_0_0.vhd @@ -0,0 +1,186 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: Gehrke:user:axis_fifo:1.0 +-- IP Revision: 15 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axi_crc_dma_sim_1_axis_fifo_0_0 IS + PORT ( + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + M_AXIS_ACLK : IN STD_LOGIC; + M_AXIS_ARESETN : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END axi_crc_dma_sim_1_axis_fifo_0_0; + +ARCHITECTURE axi_crc_dma_sim_1_axis_fifo_0_0_arch OF axi_crc_dma_sim_1_axis_fifo_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axis_fifo_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_fifo IS + GENERIC ( + FIFO_HAS_AXIL_IF : BOOLEAN; + FIFO_USE_BLOCKRAM : BOOLEAN; + FIFO_AWIDTH : INTEGER; + FIFO_DWIDTH : INTEGER; + FIFO_TUSERWIDTH : INTEGER + ); + PORT ( + S_AXI_ACLK : IN STD_LOGIC; + S_AXI_ARESETN : IN STD_LOGIC; + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + M_AXIS_ACLK : IN STD_LOGIC; + M_AXIS_ARESETN : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT axis_fifo; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_fifo + GENERIC MAP ( + FIFO_HAS_AXIL_IF => false, + FIFO_USE_BLOCKRAM => true, + FIFO_AWIDTH => 8, + FIFO_DWIDTH => 32, + FIFO_TUSERWIDTH => 1 + ) + PORT MAP ( + S_AXI_ACLK => '0', + S_AXI_ARESETN => '0', + S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), + S_AXI_AWVALID => '0', + S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), + S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), + S_AXI_WVALID => '0', + S_AXI_BREADY => '0', + S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), + S_AXI_ARVALID => '0', + S_AXI_RREADY => '0', + S_AXIS_ACLK => S_AXIS_ACLK, + S_AXIS_ARESETN => S_AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TUSER => S_AXIS_TUSER, + S_NUM_FREE => S_NUM_FREE, + M_AXIS_ACLK => M_AXIS_ACLK, + M_AXIS_ARESETN => M_AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TUSER => M_AXIS_TUSER, + M_NUM_AVAIL => M_NUM_AVAIL + ); +END axi_crc_dma_sim_1_axis_fifo_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml index fdc7415..919f82a 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml @@ -1134,6 +1134,48 @@ + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_fifo + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:d953da0f + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axi_crc_dma_sim_1_axis_fifo_1_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:d953da0f + + + + S_AXI_ACLK @@ -1142,7 +1184,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1164,7 +1206,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1190,7 +1232,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1212,7 +1254,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1238,7 +1280,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1264,7 +1306,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1286,7 +1328,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1308,7 +1350,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1334,7 +1376,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1356,7 +1398,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1378,7 +1420,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1400,7 +1442,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1423,7 +1465,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1446,7 +1488,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1465,7 +1507,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1484,7 +1526,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1507,7 +1549,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1526,7 +1568,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1545,7 +1587,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1564,7 +1606,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1576,7 +1618,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1588,7 +1630,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1604,7 +1646,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1616,7 +1658,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1628,7 +1670,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1644,7 +1686,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1654,13 +1696,13 @@ out - 10 + 7 0 std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1672,7 +1714,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1684,7 +1726,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1696,7 +1738,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1712,7 +1754,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1724,7 +1766,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1736,7 +1778,7 @@ std_logic - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1752,7 +1794,7 @@ std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1762,13 +1804,13 @@ out - 10 + 7 0 std_logic_vector - dummy_view + xilinx_vhdlbehavioralsimulation @@ -1788,7 +1830,7 @@ FIFO_AWIDTH Fifo Awidth - 11 + 8 FIFO_DWIDTH @@ -1809,6 +1851,39 @@ ACTIVE_LOW + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/91a4/dmem_dp.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/91a4/bmem_dp.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/91a4/generic_fifo.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/91a4/axis_fifo.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axi_crc_dma_sim_1_axis_fifo_1_0.vhd + vhdlSource + xil_defaultlib + + + axis_fifo_v1_0 @@ -1824,7 +1899,7 @@ FIFO_AWIDTH Fifo Awidth - 11 + 8 FIFO_USE_BLOCKRAM @@ -1892,6 +1967,7 @@ + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/sim/axi_crc_dma_sim_1_axis_fifo_1_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/sim/axi_crc_dma_sim_1_axis_fifo_1_0.vhd new file mode 100644 index 0000000..d0b0a73 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/sim/axi_crc_dma_sim_1_axis_fifo_1_0.vhd @@ -0,0 +1,186 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: Gehrke:user:axis_fifo:1.0 +-- IP Revision: 15 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axi_crc_dma_sim_1_axis_fifo_1_0 IS + PORT ( + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + M_AXIS_ACLK : IN STD_LOGIC; + M_AXIS_ARESETN : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END axi_crc_dma_sim_1_axis_fifo_1_0; + +ARCHITECTURE axi_crc_dma_sim_1_axis_fifo_1_0_arch OF axi_crc_dma_sim_1_axis_fifo_1_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axis_fifo_1_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_fifo IS + GENERIC ( + FIFO_HAS_AXIL_IF : BOOLEAN; + FIFO_USE_BLOCKRAM : BOOLEAN; + FIFO_AWIDTH : INTEGER; + FIFO_DWIDTH : INTEGER; + FIFO_TUSERWIDTH : INTEGER + ); + PORT ( + S_AXI_ACLK : IN STD_LOGIC; + S_AXI_ARESETN : IN STD_LOGIC; + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + M_AXIS_ACLK : IN STD_LOGIC; + M_AXIS_ARESETN : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT axis_fifo; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_fifo + GENERIC MAP ( + FIFO_HAS_AXIL_IF => false, + FIFO_USE_BLOCKRAM => true, + FIFO_AWIDTH => 8, + FIFO_DWIDTH => 32, + FIFO_TUSERWIDTH => 1 + ) + PORT MAP ( + S_AXI_ACLK => '0', + S_AXI_ARESETN => '0', + S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), + S_AXI_AWVALID => '0', + S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), + S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), + S_AXI_WVALID => '0', + S_AXI_BREADY => '0', + S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), + S_AXI_ARVALID => '0', + S_AXI_RREADY => '0', + S_AXIS_ACLK => S_AXIS_ACLK, + S_AXIS_ARESETN => S_AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TUSER => S_AXIS_TUSER, + S_NUM_FREE => S_NUM_FREE, + M_AXIS_ACLK => M_AXIS_ACLK, + M_AXIS_ARESETN => M_AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TUSER => M_AXIS_TUSER, + M_NUM_AVAIL => M_NUM_AVAIL + ); +END axi_crc_dma_sim_1_axis_fifo_1_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_upsizer_0_0/axi_crc_dma_sim_1_axis_upsizer_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_upsizer_0_0/axi_crc_dma_sim_1_axis_upsizer_0_0.xml deleted file mode 100644 index 215912d..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_upsizer_0_0/axi_crc_dma_sim_1_axis_upsizer_0_0.xml +++ /dev/null @@ -1,737 +0,0 @@ - - - xilinx.com - customized_ip - axi_crc_dma_sim_1_axis_upsizer_0_0 - 1.0 - - - M_AXIS - - - - - - - TDATA - - - M_AXIS_TDATA - - - - - TLAST - - - M_AXIS_TLAST - - - - - TUSER - - - M_AXIS_TUSER - - - - - TVALID - - - M_AXIS_TVALID - - - - - TREADY - - - M_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 1 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXIS - - - - - - - TDATA - - - S_AXIS_TDATA - - - - - TLAST - - - S_AXIS_TLAST - - - - - TUSER - - - S_AXIS_TUSER - - - - - TVALID - - - S_AXIS_TVALID - - - - - TREADY - - - S_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 2 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 1 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - AXIS_ARESETN - - - - - - - RST - - - AXIS_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - AXIS_ACLK - - - - - - - CLK - - - AXIS_ACLK - - - - - - ASSOCIATED_BUSIF - M_AXIS:S_AXIS - - - ASSOCIATED_RESET - AXIS_ARESETN - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - AXIS_ACLK - - in - - - std_logic - dummy_view - - - - - - AXIS_ARESETN - - in - - - std_logic - dummy_view - - - - - - S_AXIS_TVALID - - in - - - std_logic - dummy_view - - - - - - S_AXIS_TDATA - - in - - 15 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - S_AXIS_TLAST - - in - - - std_logic - dummy_view - - - - 0 - - - - - S_AXIS_TREADY - - out - - - std_logic - dummy_view - - - - - - S_AXIS_TUSER - - in - - - std_logic - dummy_view - - - - 0 - - - - - M_AXIS_TVALID - - out - - - std_logic - dummy_view - - - - - - M_AXIS_TDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - M_AXIS_TLAST - - out - - - std_logic - dummy_view - - - - - - M_AXIS_TREADY - - in - - - std_logic - dummy_view - - - - 1 - - - - - M_AXIS_TUSER - - out - - - std_logic - dummy_view - - - - - - - - WIDTH_IN - Width In - 16 - - - SIZE_FACTOR - Size Factor - 2 - - - BIG_ENDIAN - Big Endian - false - - - - - - choice_list_552a89ba - 2 - 4 - 8 - 16 - - - choice_list_5f2cf65b - 1 - 8 - 16 - 32 - 64 - 128 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - axis_upsizer_v1_0 - - - WIDTH_IN - Width In - 16 - - - SIZE_FACTOR - Size Factor - 2 - - - BIG_ENDIAN - Big Endian - false - - - Component_Name - axi_crc_dma_sim_1_axis_upsizer_0_0 - - - - - axis_upsizer_v1_0 - package_project - 3 - - d:/Projekte/edvs/vivado/vivado/ip_projects/axis_upsizer/axis_upsizer.srcs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2017.4 - - - - - - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xml index 53aa449..66ed36c 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xml @@ -5,6 +5,47 @@ axi_crc_dma_sim_1_clk_rst_generator_0_0 1.0 + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + clk_rst_generator + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:47ca4f62 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axi_crc_dma_sim_1_clk_rst_generator_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:19:22 UTC 2025 + + + outputProductCRC + 9:47ca4f62 + + + + clk_in @@ -13,7 +54,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -35,7 +76,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -57,7 +98,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -69,7 +110,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -81,7 +122,7 @@ std_logic - dummy_view + xilinx_anylanguagebehavioralsimulation @@ -120,6 +161,23 @@ + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axi_crc_dma_sim_1_clk_rst_generator_0_0.vhd + vhdlSource + xil_defaultlib + + + clk_rst_generator diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/sim/axi_crc_dma_sim_1_clk_rst_generator_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/sim/axi_crc_dma_sim_1_clk_rst_generator_0_0.vhd new file mode 100644 index 0000000..5c1f941 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/sim/axi_crc_dma_sim_1_clk_rst_generator_0_0.vhd @@ -0,0 +1,99 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: wg:user:clk_rst_generator:1.0 +-- IP Revision: 7 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axi_crc_dma_sim_1_clk_rst_generator_0_0 IS + PORT ( + clk_in : IN STD_LOGIC; + rst_in : IN STD_LOGIC; + clk : OUT STD_LOGIC; + rst_n : OUT STD_LOGIC; + stop_simulation : IN STD_LOGIC + ); +END axi_crc_dma_sim_1_clk_rst_generator_0_0; + +ARCHITECTURE axi_crc_dma_sim_1_clk_rst_generator_0_0_arch OF axi_crc_dma_sim_1_clk_rst_generator_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT clk_rst_generator IS + GENERIC ( + CLOCK_PERIOD : INTEGER; + HAS_CLK_INPUT : BOOLEAN; + HAS_RESET_INPUT : BOOLEAN; + HAS_STOP_INPUT : BOOLEAN + ); + PORT ( + clk_in : IN STD_LOGIC; + rst_in : IN STD_LOGIC; + clk : OUT STD_LOGIC; + rst_n : OUT STD_LOGIC; + stop_simulation : IN STD_LOGIC + ); + END COMPONENT clk_rst_generator; +BEGIN + U0 : clk_rst_generator + GENERIC MAP ( + CLOCK_PERIOD => 10000, + HAS_CLK_INPUT => true, + HAS_RESET_INPUT => true, + HAS_STOP_INPUT => true + ) + PORT MAP ( + clk_in => clk_in, + rst_in => rst_in, + clk => clk, + rst_n => rst_n, + stop_simulation => stop_simulation + ); +END axi_crc_dma_sim_1_clk_rst_generator_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/85f6/sources_1/new/axil_master_with_rom.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/85f6/sources_1/new/axil_master_with_rom.vhd new file mode 100644 index 0000000..e4b30a0 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/85f6/sources_1/new/axil_master_with_rom.vhd @@ -0,0 +1,285 @@ +------------------------------------------------------------------------------ +-- axil_master_with_rom.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2024 +---------------------------------------------------------- + +-- AXIL-Master +-- +-- Transactions des Masters werden durch ein ladbares ROM definiert +-- Die Inhalte des ROMs werden aus einer Datei geladen und bei Synthese und Simulation verwendet +-- Das ROM besitzt eine Wortbreite von 40 bit +-- Für einen Befehl werden 1 bis 2 Worte verwendet +-- Nur 'wal' verwendet 2 40 - Bit - Worte +-- +-- Die Codierung ist nachfolgend dargestellt : +-- command wal : <39 : 8> Adresse <3 : 0> Befehl(wal = 1) +-- <39 : 8> Daten <3 : 0> Befehl WStrobe +-- command ral : <39 : 8> Adresse <3 : 0> Befehl(ral = 2) +-- command wfi : Befehl(wfi = 6) +-- command ral : <15 : 8> Wartezyklen <3 : 0> Befehl(slp = 7) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity axil_master_with_rom is + generic + ( + HAS_INTERRUPT_IN : boolean := true; + HAS_FINISHED_OUT : boolean := false; + REVISION_NO : integer := 1; + STIM_FILENAME : string := "../../stimuli.mem" + ); + port + ( + interrupt_in : in std_logic:='0'; + finished_o : out std_logic; + + M_AXIL_ACLK : in std_logic; + M_AXIL_ARESETN : in std_logic; + + M_AXIL_ARREADY : in std_logic; + M_AXIL_ARVALID : out std_logic; + M_AXIL_ARADDR : out std_logic_vector(31 downto 0); + M_AXIL_ARPROT : out std_logic_vector(2 downto 0); + M_AXIL_RREADY : out std_logic; + M_AXIL_RVALID : in std_logic; + M_AXIL_RDATA : in std_logic_vector(31 downto 0); + M_AXIL_RRESP : in std_logic_vector(1 downto 0); + M_AXIL_AWREADY : in std_logic; + M_AXIL_AWVALID : out std_logic; + M_AXIL_AWADDR : out std_logic_vector(31 downto 0); + M_AXIL_AWPROT : out std_logic_vector(2 downto 0); + M_AXIL_WREADY : in std_logic; + M_AXIL_WVALID : out std_logic; + M_AXIL_WDATA : out std_logic_vector(31 downto 0); + M_AXIL_WSTRB : out std_logic_vector(3 downto 0); + M_AXIL_BREADY : out std_logic; + M_AXIL_BVALID : in std_logic; + M_AXIL_BRESP : in std_logic_vector(1 downto 0) + ); + +end; + + +architecture rtl of axil_master_with_rom is + + + type TSTATE is (INIT,INIT_WAIT, + GET_COMMAND, + WR_ADDR,WR_ADDR_WAIT1,WR_ADDR_WAIT2,WR_DATA,WR_DATA_WAIT,WR_RESP, + RD_ADDR,RD_DATA, + WAIT_FOR_INT, + SLEEP,SLEEP_WAIT, + FINISHED + ); + + signal state : TSTATE := INIT; + + constant ADDR_WIDTH_CMD_ROM : integer := 12; + + signal mdata : std_logic_vector(39 downto 0); + signal maddr : std_logic_vector(ADDR_WIDTH_CMD_ROM-1 downto 0); + +begin + +cmdrom : entity work.axilm_rom + generic map ( + FILENAME => STIM_FILENAME, + DW => 40, + AW => ADDR_WIDTH_CMD_ROM + ) + port map ( + clk => M_AXIL_ACLK, + a => maddr, + q => mdata + ); + + +process + variable cnt8 : unsigned( 7 downto 0); + variable cnt32 : unsigned(31 downto 0); + variable addr_accepted : boolean; + variable data_accepted : boolean; + + begin + wait until rising_edge(M_AXIL_ACLK); + + if M_AXIL_ARESETN = '0' then + state <= INIT; + M_AXIL_ARVALID <= '0'; + M_AXIL_ARADDR <= (others=>'X'); + M_AXIL_ARPROT <= (others=>'0'); + M_AXIL_RREADY <= '0'; + M_AXIL_AWVALID <= '0'; + M_AXIL_AWADDR <= (others=>'X'); + M_AXIL_AWPROT <= (others=>'0'); + M_AXIL_WVALID <= '0'; + M_AXIL_WDATA <= (others=>'X'); + M_AXIL_WSTRB <= (others=>'X'); + M_AXIL_BREADY <= '0'; + finished_o <= '0'; + else + case state is + + ---- + -- Init + ---- + when INIT => + finished_o <= '0'; + cnt8 := x"10"; + maddr <= (others=>'0'); + M_AXIL_ARVALID <= '0'; + M_AXIL_ARADDR <= (others=>'X'); + M_AXIL_ARPROT <= (others=>'0'); + M_AXIL_RREADY <= '0'; + M_AXIL_AWVALID <= '0'; + M_AXIL_AWADDR <= (others=>'X'); + M_AXIL_AWPROT <= (others=>'0'); + M_AXIL_WVALID <= '0'; + M_AXIL_WDATA <= (others=>'X'); + M_AXIL_WSTRB <= (others=>'X'); + M_AXIL_BREADY <= '0'; + state <= INIT_WAIT; + + when INIT_WAIT => + cnt8 := cnt8 - 1; + if cnt8 = 0 then + state <= GET_COMMAND; + end if; + + when GET_COMMAND => + case (mdata(3 downto 0)) is + when x"0" => state <= FINISHED; + when x"1" => state <= WR_ADDR; + when x"2" => state <= RD_ADDR; + when x"6" => state <= WAIT_FOR_INT; + when x"7" => state <= SLEEP; + when others => maddr <= std_logic_vector(unsigned(maddr) + 1); + end case; + + + ---- + -- Write + ---- + when WR_ADDR => + M_AXIL_AWVALID <= '1'; + M_AXIL_AWADDR <= mdata(39 downto 8); + M_AXIL_ARVALID <= '0'; + M_AXIL_ARADDR <= (others => 'X'); + maddr <= std_logic_vector(unsigned(maddr) + 1); + addr_accepted := false; + data_accepted := false; + state <= WR_ADDR_WAIT1; + when WR_ADDR_WAIT1 => + if (M_AXIL_AWREADY = '1') then + M_AXIL_AWVALID <= '0'; + addr_accepted := true; + end if; + state <= WR_ADDR_WAIT2; + when WR_ADDR_WAIT2 => + if (M_AXIL_AWREADY = '1') then + M_AXIL_AWVALID <= '0'; + addr_accepted := true; + end if; + state <= WR_DATA; + when WR_DATA => + if (M_AXIL_AWREADY = '1') then + M_AXIL_AWVALID <= '0'; + addr_accepted := true; + end if; + M_AXIL_WSTRB <= mdata( 3 downto 0); + M_AXIL_WDATA <= mdata(39 downto 8); + M_AXIL_WVALID <= '1'; + state <= WR_DATA_WAIT; + when WR_DATA_WAIT => + if (M_AXIL_AWREADY = '1') then + M_AXIL_AWVALID <= '0'; + addr_accepted := true; + end if; + if (M_AXIL_WREADY = '1') then + M_AXIL_WVALID <= '0'; + data_accepted := true; + end if; + + if (addr_accepted and data_accepted) then + maddr <= std_logic_vector(unsigned(maddr) + 1); + M_AXIL_AWVALID <= '0'; + M_AXIL_WSTRB <= (others=>'X'); + M_AXIL_WDATA <= (others=>'X'); + M_AXIL_WVALID <= '0'; + M_AXIL_BREADY <= '1'; + state <= WR_RESP; + end if; + when WR_RESP => + if M_AXIL_BVALID = '1' then + M_AXIL_BREADY <= '0'; + state <= GET_COMMAND; + end if; + + + ---- + -- Read + ---- + when RD_ADDR => + M_AXIL_ARVALID <= '1'; + M_AXIL_ARADDR <= mdata(39 downto 8); + M_AXIL_AWVALID <= 'X'; + M_AXIL_AWADDR <= (others => 'X'); + M_AXIL_RREADY <= '1'; + addr_accepted := false; + state <= RD_DATA; + when RD_DATA => + if (M_AXIL_ARREADY = '1') then + M_AXIL_ARVALID <= '0'; + addr_accepted := true; + end if; + if (M_AXIL_RVALID = '1') then + M_AXIL_RREADY <= '0'; + data_accepted := true; + end if; + if (addr_accepted and data_accepted) then + maddr <= std_logic_vector(unsigned(maddr) + 1); + M_AXIL_ARVALID <= '0'; + M_AXIL_RREADY <= '0'; + M_AXIL_ARADDR <= (others => 'X'); + state <= GET_COMMAND; + end if; + + when WAIT_FOR_INT => + if (interrupt_in = '1') then + maddr <= std_logic_vector(unsigned(maddr) + 1); + state <= GET_COMMAND; + end if; + + when SLEEP => + cnt32 := unsigned(mdata(39 downto 8)); + -- synthesis translate_off + cnt32 := x"0000"&unsigned(mdata(39 downto 24)); -- fuer Simulation Wartezeit um 65536 verringern + -- synthesis translate_on + maddr <= std_logic_vector(unsigned(maddr) + 1); + state <= SLEEP_WAIT; + + when SLEEP_WAIT => + if (cnt32 /= 0) then + cnt32 := cnt32 - 1; + else + state <= GET_COMMAND; + end if; + + when FINISHED => + finished_o <= '1'; + + + end case; + + end if; + +end process; + + +end; \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/85f6/sources_1/new/axilm_rom.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/85f6/sources_1/new/axilm_rom.vhd new file mode 100644 index 0000000..7693edd --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/85f6/sources_1/new/axilm_rom.vhd @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------ +-- axilm_rom.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2024 +---------------------------------------------------------- + +-- ref. https://docs.amd.com/r/en-US/ug901-vivado-synthesis/VHDL-Code-Example + +use std.textio.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; + +entity axilm_rom is + + generic ( + FILENAME : string; + DW : integer; -- Data Width + AW : integer -- Address Width + ); + port ( + clk : in std_logic; -- Clock + a : in std_logic_vector(AW-1 downto 0); -- Address + q : out std_logic_vector(DW-1 downto 0) -- Data out port +); +end; + + +architecture rtl of axilm_rom is + type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0); + + impure function InitMemFromFile(MemFileName : in string) return tmem is + FILE MemFile : text is in MemFileName; + variable MemFileLine : line; + variable mem : tmem; + begin + for i in tmem'range loop + readline(MemFile, MemFileLine); + read(MemFileLine, mem(i)); + end loop; + return mem; + end function; + + constant mem : tmem := InitMemFromFile( + -- synthesis translate_off + "../../" & + -- synthesis translate_on + FILENAME); + +begin + process + begin + wait until rising_edge(clk); + q <= mem(to_integer(unsigned(a))); + end process; +end; + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/axis_fifo.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/axis_fifo.vhd new file mode 100644 index 0000000..21876ec --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/axis_fifo.vhd @@ -0,0 +1,230 @@ +-------------------------------------------------------------------------- +-- +-- AXI Stream FIFO +-- +-- Prof. Dr.-Ing. W. Gehrke (c) 2013 +-- +-------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity axis_fifo is + generic + ( + FIFO_HAS_AXIL_IF : boolean := false; + FIFO_USE_BLOCKRAM : boolean := true; + FIFO_AWIDTH : integer := 11; + FIFO_DWIDTH : integer := 32; + FIFO_TUSERWIDTH : integer := 1 + ); + port + ( + -- AXI-L Slave Port + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(7 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(7 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_RREADY : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_AWREADY : out std_logic; + + -- AXI Streaming Target Port + S_AXIS_ACLK : in std_logic; + S_AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TUSER : in std_logic_vector(FIFO_TUSERWIDTH-1 downto 0); + S_NUM_FREE : out std_logic_vector(FIFO_AWIDTH-1 downto 0); -- Free Entries + + -- AXI Streaming Initiator Port + M_AXIS_ACLK : in std_logic; + M_AXIS_ARESETN : in std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TUSER : out std_logic_vector(FIFO_TUSERWIDTH-1 downto 0); + M_NUM_AVAIL : out std_logic_vector(FIFO_AWIDTH-1 downto 0) -- Allocated Entries + + ); +end; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture rtl of axis_fifo is + + type T_AXIL_STATE is (IDLE,WAIT_BREADY,WAIT_RREADY); + signal axil_state : T_AXIL_STATE := IDLE; + + signal fifo_wrclk : std_logic; + signal fifo_wrrst : std_logic; + signal fifo_wren : std_logic; + signal fifo_wrfull : std_logic; + signal fifo_wrdat : std_logic_vector(FIFO_DWIDTH+FIFO_TUSERWIDTH downto 0); + signal fifo_wrnum : std_logic_vector(FIFO_AWIDTH-1 downto 0); + + signal fifo_rdclk : std_logic; + signal fifo_rdrst : std_logic := '0'; + signal fifo_rden : std_logic; + signal fifo_rdempty : std_logic; + signal fifo_rddat : std_logic_vector(FIFO_DWIDTH+FIFO_TUSERWIDTH downto 0); + signal fifo_rdnum : std_logic_vector(FIFO_AWIDTH-1 downto 0); + + signal fifo_reset_req : std_logic; + signal fifo_reset_req_sync : std_logic; + signal status_reg : std_logic_vector (31 downto 0):= (others=>'0'); + +begin + fifo_wrclk <= S_AXIS_ACLK; + fifo_wrrst <= not S_AXIS_ARESETN; + fifo_wren <= S_AXIS_TVALID; + S_AXIS_TREADY <= not fifo_wrfull; + fifo_wrdat <= S_AXIS_TUSER & S_AXIS_TLAST & S_AXIS_TDATA; + S_NUM_FREE <= fifo_wrnum; + + fifo_rdclk <= M_AXIS_ACLK; + fifo_rdrst <= (not M_AXIS_ARESETN) or fifo_reset_req_sync; + fifo_rden <= M_AXIS_TREADY; + M_AXIS_TVALID <= not fifo_rdempty; + M_AXIS_TDATA <= fifo_rddat(FIFO_DWIDTH-1 downto 0); + M_AXIS_TUSER <= fifo_rddat(FIFO_DWIDTH+FIFO_TUSERWIDTH downto FIFO_DWIDTH+1); + M_AXIS_TLAST <= fifo_rddat(FIFO_DWIDTH); + M_NUM_AVAIL <= fifo_rdnum; + + status_gen1: if FIFO_AWIDTH <= 14 generate + status_reg(2*FIFO_AWIDTH+3 downto 0) <= fifo_wrnum & fifo_rdnum & '0' & fifo_wrfull & fifo_rdempty & fifo_reset_req; + end generate; + + status_gen2: if FIFO_AWIDTH > 14 generate + status_reg <= fifo_wrnum(13 downto 0) & fifo_rdnum(13 downto 0) & '0' & fifo_wrfull & fifo_rdempty & fifo_reset_req; + end generate; + + + fifo : entity work.generic_fifo + + generic map ( + USE_BLOCKRAM=> FIFO_USE_BLOCKRAM, -- Block RAM (1) or Distributed Memory (0) + DW => FIFO_DWIDTH+FIFO_TUSERWIDTH+1, -- Data Width + AW => FIFO_AWIDTH -- Address Width + ) + port map ( + -- Write Port + wrclk => fifo_wrclk, -- Clock + wrrst => fifo_wrrst, -- Reset + wrdat => fifo_wrdat, -- Data in + wren => fifo_wren, -- Write enable + wrfull => fifo_wrfull, -- Full indicator + wrnum => fifo_wrnum, + + -- Read Port + rdclk => fifo_rdclk, -- Clock + rdrst => fifo_rdrst, -- Reset + rden => fifo_rden, -- Read enable + rddat => fifo_rddat, -- Data out port + rdempty => fifo_rdempty, -- Empty indicator + rdnum => fifo_rdnum + ); + + + process begin + wait until rising_edge (fifo_rdclk); + fifo_reset_req_sync <= fifo_reset_req; + end process; + + +axil_ngen: if not FIFO_HAS_AXIL_IF generate + S_AXI_ARREADY <= '0'; + S_AXI_RDATA <= (others=>'0'); + S_AXI_RRESP <= (others=>'0'); + S_AXI_RVALID <= '0'; + S_AXI_WREADY <= '0'; + S_AXI_BRESP <= (others=>'0'); + S_AXI_BVALID <= '0'; + S_AXI_AWREADY <= '0'; + fifo_reset_req <= '0'; +end generate; + +axil_gen: if FIFO_HAS_AXIL_IF generate + axil_if : process + variable reg_num : integer; + begin + wait until rising_edge (S_AXI_ACLK); + if S_AXI_ARESETN = '0' then + S_AXI_AWREADY <= '0'; + S_AXI_ARREADY <= '0'; + S_AXI_BVALID <= '0'; + S_AXI_WREADY <= '0'; + S_AXI_RVALID <= '0'; + S_AXI_RDATA <= (others=>'0'); + + fifo_reset_req <= '0'; + else + case axil_state is + when IDLE => + S_AXI_AWREADY <= '1'; + S_AXI_WREADY <= '1'; + S_AXI_ARREADY <= '1'; + S_AXI_BVALID <= '0'; + S_AXI_RVALID <= '0'; + + if S_AXI_AWVALID = '1' then + if S_AXI_WVALID = '1' then + fifo_reset_req <= S_AXI_WDATA(0); + S_AXI_AWREADY <= '0'; + S_AXI_WREADY <= '0'; + S_AXI_ARREADY <= '0'; + S_AXI_BVALID <= '1'; + axil_state <= WAIT_BREADY; + end if; + elsif S_AXI_ARVALID = '1' then + S_AXI_RDATA <= status_reg; + S_AXI_AWREADY <= '0'; + S_AXI_WREADY <= '0'; + S_AXI_ARREADY <= '0'; + S_AXI_RVALID <= '1'; + axil_state <= WAIT_RREADY; + end if; + + when WAIT_BREADY => + if S_AXI_BREADY = '1' then + S_AXI_AWREADY <= '1'; + S_AXI_WREADY <= '1'; + S_AXI_ARREADY <= '1'; + S_AXI_BVALID <= '0'; + axil_state <= IDLE; + end if; + + when WAIT_RREADY => + if S_AXI_RREADY = '1' then + S_AXI_AWREADY <= '1'; + S_AXI_WREADY <= '1'; + S_AXI_ARREADY <= '1'; + S_AXI_RVALID <= '0'; + axil_state <= IDLE; + end if; + end case; + + end if; + end process; +end generate; + + + end; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/bmem_dp.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/bmem_dp.vhd new file mode 100644 index 0000000..37f4156 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/bmem_dp.vhd @@ -0,0 +1,78 @@ +-------------------------------------------------------------------------- +-- +-- Dual-ported Synchronous Memory (Block Memory) +-- +-- Prof. Dr.-Ing. W. Gehrke (c) 2011 +-- +-------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity bmem_dp is + + generic ( + DW : integer := 16; -- Data Width + AW : integer := 10 -- Address Width + ); + port ( + -- Port 1 + clk1 : in std_logic; -- Clock + en1 : in std_logic; -- Enable + a1 : in std_logic_vector(AW-1 downto 0); -- Address + d1 : in std_logic_vector(DW-1 downto 0); -- Data in + we1 : in std_logic; -- Write enable + q1 : out std_logic_vector(DW-1 downto 0); -- Data out port + + -- Port 2 + clk2 : in std_logic; -- Clock + en2 : in std_logic; -- Enable + a2 : in std_logic_vector(AW-1 downto 0); -- Address + d2 : in std_logic_vector(DW-1 downto 0); -- Data in + we2 : in std_logic; -- Write enable + q2 : out std_logic_vector(DW-1 downto 0) -- Data out port + + ); +end; + + +architecture rtl of bmem_dp is + + type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0); + shared variable mem : tmem := ((others=> (others=>'0'))); + + signal q1_sig : std_logic_vector(DW-1 downto 0) := (others=>'0'); + signal q2_sig : std_logic_vector(DW-1 downto 0) := (others=>'0'); + +begin + q1 <= q1_sig; + q2 <= q2_sig; + + -- Port 1 + process (clk1) + begin + if (clk1'event and clk1 = '1') then + if (en1 = '1') then + if (we1 = '1') then + mem(to_integer(unsigned(a1))) := d1; + end if; + q1_sig <= mem(to_integer(unsigned(a1))); + end if; + end if; + end process; + + -- Port 2 + process (clk2) + begin + if (clk2'event and clk2 = '1') then + if (en2 = '1') then + if (we2 = '1') then + mem(to_integer(unsigned(a2))) := d2; + end if; + q2_sig <= mem(to_integer(unsigned(a2))); + end if; + end if; + end process; + +end; \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/dmem_dp.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/dmem_dp.vhd new file mode 100644 index 0000000..f8e2475 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/dmem_dp.vhd @@ -0,0 +1,74 @@ +-------------------------------------------------------------------------- +-- +-- Dual-ported Asynchronous-Read Synchronous-Write Memory (Distributed Memory) +-- +-- Prof. Dr.-Ing. W. Gehrke (c) 2011 +-- +-------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dmem_dp is + + generic ( + DW : integer := 16; -- Data Width + AW : integer := 10 -- Address Width + ); + port ( + -- Port 1 + clk1 : in std_logic; -- Clock + en1 : in std_logic; -- Enable + a1 : in std_logic_vector(AW-1 downto 0); -- Address + d1 : in std_logic_vector(DW-1 downto 0); -- Data in + we1 : in std_logic; -- Write enable + q1 : out std_logic_vector(DW-1 downto 0); -- Data out port + + -- Port 2 + clk2 : in std_logic; -- Clock + en2 : in std_logic; -- Enable + a2 : in std_logic_vector(AW-1 downto 0); -- Address + d2 : in std_logic_vector(DW-1 downto 0); -- Data in + we2 : in std_logic; -- Write enable + q2 : out std_logic_vector(DW-1 downto 0) -- Data out port + + ); +end; + + +architecture rtl of dmem_dp is + + type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0); + shared variable mem : tmem; + + +begin + + -- Port 1 + process (clk1,a1) + begin + q1 <= mem(to_integer(unsigned(a1))); + if (clk1'event and clk1 = '1') then + if (en1 = '1') then + if (we1 = '1') then + mem(to_integer(unsigned(a1))) := d1; + end if; + end if; + end if; + end process; + + -- Port 2 + process (clk2,a2) + begin + q2 <= mem(to_integer(unsigned(a2))); + if (clk2'event and clk2 = '1') then + if (en2 = '1') then + if (we2 = '1') then + mem(to_integer(unsigned(a2))) := d2; + end if; + end if; + end if; + end process; + +end; \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/generic_fifo.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/generic_fifo.vhd new file mode 100644 index 0000000..7f6e78d --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/generic_fifo.vhd @@ -0,0 +1,222 @@ +-------------------------------------------------------------------------- +-- +-- FIFO incl. Clock Domain Crossing +-- +-- +-- Prof. Dr.-Ing. W. Gehrke (c) 2013 +-- +-------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity generic_fifo is + + generic ( + USE_BLOCKRAM: boolean := true; + DW : integer := 32; -- Data Width + AW : integer := 10 -- Address Width + ); + port ( + -- Write Port + wrclk : in std_logic; -- Clock + wrrst : in std_logic; -- Reset + wrdat : in std_logic_vector(DW-1 downto 0); -- Data in + wren : in std_logic; -- Write enable + wrfull : out std_logic; -- Full indicator + wrnum : out std_logic_vector(AW-1 downto 0); -- Free Entries + + -- Read Port + rdclk : in std_logic; -- Clock + rdrst : in std_logic; -- Reset + rden : in std_logic; -- Read enable + rddat : out std_logic_vector(DW-1 downto 0); -- Data out port + rdempty : out std_logic; -- Empty indicator + rdnum : out std_logic_vector(AW-1 downto 0) -- Allocated Entries + ); +end; + + +architecture rtl of generic_fifo is + + + constant zero : std_logic_vector (DW-1 downto 0) := (others=>'0'); + + signal full : std_logic := '0'; + signal empty : std_logic := '1'; + + signal mem_wren : std_logic := '0'; + + signal wrrst_sync : std_logic := '0'; + signal rdrst_sync : std_logic := '0'; + + signal wp_bin : std_logic_vector (AW downto 0) := (others=>'0'); + signal wp_bin_next : std_logic_vector (AW downto 0) := (others=>'0'); + signal wp_gray : std_logic_vector (AW downto 0) := (others=>'0'); + signal wp_gray_sync : std_logic_vector (AW downto 0) := (others=>'0'); + signal wp_bin_sync : std_logic_vector (AW downto 0) := (others=>'0'); + signal w_num_free : std_logic_vector (AW-1 downto 0) := (others=>'1'); + + signal rp_bin : std_logic_vector (AW downto 0) := (others=>'0'); + signal rp_bin_reg : std_logic_vector (AW downto 0) := (others=>'0'); + signal rp_bin_next : std_logic_vector (AW downto 0) := (others=>'0'); + signal rp_gray : std_logic_vector (AW downto 0) := (others=>'0'); + signal rp_gray_sync : std_logic_vector (AW downto 0) := (others=>'0'); + signal rp_bin_sync : std_logic_vector (AW downto 0) := (others=>'0'); + signal r_num_avail : std_logic_vector (AW-1 downto 0) := (others=>'0'); + + signal rddat_dm : std_logic_vector(DW-1 downto 0); + +begin + +bl_gen: if USE_BLOCKRAM generate + fifomem : entity work.bmem_dp + generic map( + DW => DW, -- Data Width + AW => AW -- Address Width + ) + port map( + -- Port 1 + clk1 => wrclk, -- Clock + en1 => '1', -- Enable + a1 => wp_bin(AW-1 downto 0), -- Address + d1 => wrdat, -- Data in + we1 => mem_wren, -- Write enable + q1 => open, -- Data out port + -- Port 2 + clk2 => rdclk, -- Clock + en2 => '1', -- Enable + a2 => rp_bin(AW-1 downto 0), -- Address + d2 => zero, -- Data in + we2 => '0', -- Write enable + q2 => rddat -- Data out port + ); + end generate; + +dm_gen: if not USE_BLOCKRAM generate + fifomem : entity work.dmem_dp + generic map( + DW => DW, -- Data Width + AW => AW -- Address Width + ) + port map( + -- Port 1 + clk1 => wrclk, -- Clock + en1 => '1', -- Enable + a1 => wp_bin(AW-1 downto 0), -- Address + d1 => wrdat, -- Data in + we1 => mem_wren, -- Write enable + q1 => open, -- Data out port + -- Port 2 + clk2 => rdclk, -- Clock + en2 => '1', -- Enable + a2 => rp_bin(AW-1 downto 0), -- Address + d2 => zero, -- Data in + we2 => '0', -- Write enable + q2 => rddat_dm -- Data out port + ); + + process begin + wait until rising_edge(rdclk); + rddat <= rddat_dm; + end process; + end generate; + ---------------------------------------------- + -- FIFO Write Logic + ---------------------------------------------- + wp_gray <= '0' & wp_bin(AW downto 1) xor wp_bin; -- Gray Code conversion + full <= '1' when (wp_bin(AW-1 downto 0) = rp_bin_sync(AW-1 downto 0)) and (wp_bin(AW) /= rp_bin_sync(AW)) else '0'; + wrfull <= full; + wrnum <= w_num_free; + mem_wren <= wren and (not full); + + sync_wr : process begin + wait until rising_edge(wrclk); + rp_gray_sync <= rp_gray; + rdrst_sync <= rdrst; + end process; + + fifo_fulln_wr : process begin + wait until rising_edge(wrclk); + if wp_bin = rp_bin_sync then + w_num_free <= (others=>'1'); + else + w_num_free <= std_logic_vector(unsigned(rp_bin_sync(AW-1 downto 0)) - unsigned(wp_bin(AW-1 downto 0))); + end if; + end process; + + fifo_wr : process begin + wait until rising_edge(wrclk); + if wrrst = '1' or rdrst_sync = '1' then + wp_bin <= (others=>'0'); + wp_bin_next <= std_logic_vector(to_unsigned(1,AW+1)); + else + if wren = '1' and full = '0' then + wp_bin <= wp_bin_next; + wp_bin_next <= std_logic_vector(unsigned(wp_bin_next)+1); + end if; + end if; + end process; + + gray2bin_rp: process (rp_gray_sync) + variable temp : std_logic_vector(AW downto 0); + begin + temp := rp_gray_sync; + for i in AW-1 downto 0 loop + temp(i) := rp_gray_sync(i) xor temp(i+1); + end loop; + rp_bin_sync <= temp; + end process; + + ---------------------------------------------- + -- FIFO Read Logic + ---------------------------------------------- + rp_gray <= '0' & rp_bin(AW downto 1) xor rp_bin; -- Gray Code conversion + empty <= '1' when rp_bin_reg = wp_bin_sync else '0'; + rdempty <= empty; + rp_bin <= rp_bin_next when rden = '1' and empty = '0' else rp_bin_reg; + rdnum <= r_num_avail; + + + sync_rd : process begin + wait until rising_edge(rdclk); + wp_gray_sync <= wp_gray; + wrrst_sync <= wrrst; + end process; + + fifo_fulln_rd : process begin + wait until rising_edge(rdclk); + if rp_bin_reg = wp_bin_sync then -- empty check -- changed rp_bin to rp_bin_reg for timing improvement, WG 07.11.16 + r_num_avail <= (others=>'0'); + elsif wp_bin_sync = (not rp_bin_reg(AW)) & rp_bin_reg(AW-1 downto 0) then --full check -- changed rp_bin to rp_bin_reg for timing improvement, WG 07.11.16 + r_num_avail <= (others=>'1'); + else + r_num_avail <= std_logic_vector(unsigned(wp_bin_sync(AW-1 downto 0)) - unsigned(rp_bin_reg(AW-1 downto 0))); -- changed rp_bin to rp_bin_reg for timing improvement, WG 07.11.16 + end if; + end process; + + fifo_rd : process begin + wait until rising_edge(rdclk); + if rdrst = '1' or wrrst_sync = '1' then + rp_bin_reg <= (others=>'0'); + rp_bin_next <= std_logic_vector(to_unsigned(1,AW+1)); + else + rp_bin_reg <= rp_bin; + if rden = '1' and empty = '0' then + rp_bin_next <= std_logic_vector(unsigned(rp_bin_next)+1); + end if; + end if; + end process; + + gray2bin_wp: process (wp_gray_sync) + variable temp : std_logic_vector(AW downto 0); + begin + temp := wp_gray_sync; + for i in AW-1 downto 0 loop + temp(i) := wp_gray_sync(i) xor temp(i+1); + end loop; + wp_bin_sync <= temp; + end process; + +end; \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd new file mode 100644 index 0000000..5a4bb56 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd @@ -0,0 +1,114 @@ +------------------------------------------------------------------------------ +-- clk_rst_generator.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2024 +---------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity clk_rst_generator is + generic + ( + CLOCK_PERIOD : integer := 10000; + HAS_CLK_INPUT : boolean := true; + HAS_RESET_INPUT : boolean := true; + HAS_STOP_INPUT : boolean := true + ); + port + ( + clk_in : in std_logic := '1'; + rst_in : in std_logic := '0'; + + clk : out std_logic; + rst_n : out std_logic; + + stop_simulation : in std_logic := '0' + ); + +end; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture rtl of clk_rst_generator is + + signal clk_sim : std_logic := '1'; + signal clk_in_sig : std_logic := '1'; + signal clk_sig : std_logic := '1'; + signal rst_sig : std_logic := '0'; + signal rst_in_sync : std_logic := '0'; + +begin + clk <= clk_sig; + rst_n <= not rst_sig; + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- CLOCK GENERATION + --------------------------------------------------------------- + --------------------------------------------------------------- + + clk_sig <= clk_in_sig and clk_sim; + -- Dies ist kein gated Clock! + -- Fuer die Synthese ist clk_sim konstant '1' + -- somit wird die UND-Verknuepfung 'wegoptimiert' + -- und was übrig bleibt, ist ein 'Draht' + + -- synthesis translate_off + clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2; + assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note; + assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note; + assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note; + -- synthesis translate_on + + process (clk_in) begin + clk_in_sig <= clk_in; + -- synthesis translate_off + clk_in_sig <= '1'; + -- synthesis translate_on + end process; + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- RESET GENERATION + --------------------------------------------------------------- + --------------------------------------------------------------- + + process + variable rescnt : unsigned (6 downto 0) := (others=>'1'); + begin + wait until rising_edge(clk_sig); + + rst_in_sync <= rst_in; + if rst_in_sync = '1' then + rescnt := (others=>'1'); + end if; + + if rescnt = 0 then + rst_sig <= '0'; + else + rescnt := rescnt - 1; + rst_sig <= '1'; + end if; + end process; + + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- STOP SIMULATION INPUT (simulation only) + --------------------------------------------------------------- + --------------------------------------------------------------- + + -- synthesis translate_off + process (stop_simulation) begin + if stop_simulation = '1' then + assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure; + end if; + end process; + -- synthesis translate_on + +end rtl; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd new file mode 100644 index 0000000..5747598 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd @@ -0,0 +1,680 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Sun Feb 2 01:00:12 2025 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target axi_crc_dma_sim_1.bd +--Design : axi_crc_dma_sim_1 +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity axi_crc_dma_imp_1PQG7GB is + port ( + CLK : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + RESETN : in STD_LOGIC; + S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_arready : out STD_LOGIC; + S_AXIL_arvalid : in STD_LOGIC; + S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_awready : out STD_LOGIC; + S_AXIL_awvalid : in STD_LOGIC; + S_AXIL_bready : in STD_LOGIC; + S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_bvalid : out STD_LOGIC; + S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_rready : in STD_LOGIC; + S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_rvalid : out STD_LOGIC; + S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_wready : out STD_LOGIC; + S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_wvalid : in STD_LOGIC + ); +end axi_crc_dma_imp_1PQG7GB; + +architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is + component axi_crc_dma_sim_1_axis_fifo_0_0 is + port ( + S_AXIS_ACLK : in STD_LOGIC; + S_AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXIS_ACLK : in STD_LOGIC; + M_AXIS_ARESETN : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + end component axi_crc_dma_sim_1_axis_fifo_0_0; + component axi_crc_dma_sim_1_axis_fifo_1_0 is + port ( + S_AXIS_ACLK : in STD_LOGIC; + S_AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXIS_ACLK : in STD_LOGIC; + M_AXIS_ARESETN : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + end component axi_crc_dma_sim_1_axis_fifo_1_0; + component axi_crc_dma_sim_1_axis_crc_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 ); + polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC + ); + end component axi_crc_dma_sim_1_axis_crc_0_0; + component axi_crc_dma_sim_1_axis_dma_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 ); + polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 ); + FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 ); + FIFO_NUM_AVAIL : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXIL_AWVALID : in STD_LOGIC; + S_AXIL_AWREADY : out STD_LOGIC; + S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_WVALID : in STD_LOGIC; + S_AXIL_WREADY : out STD_LOGIC; + S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_BVALID : out STD_LOGIC; + S_AXIL_BREADY : in STD_LOGIC; + S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXIL_ARVALID : in STD_LOGIC; + S_AXIL_ARREADY : out STD_LOGIC; + S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_RVALID : out STD_LOGIC; + S_AXIL_RREADY : in STD_LOGIC; + S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_ARREADY : in STD_LOGIC; + M_AXI_ARVALID : out STD_LOGIC; + M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_RREADY : out STD_LOGIC; + M_AXI_RVALID : in STD_LOGIC; + M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_RLAST : in STD_LOGIC; + M_AXI_AWREADY : in STD_LOGIC; + M_AXI_AWVALID : out STD_LOGIC; + M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WREADY : in STD_LOGIC; + M_AXI_WVALID : out STD_LOGIC; + M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WLAST : out STD_LOGIC; + M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_BREADY : out STD_LOGIC; + M_AXI_BVALID : in STD_LOGIC; + M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC + ); + end component axi_crc_dma_sim_1_axis_dma_0_0; + signal CLK_1 : STD_LOGIC; + signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_ARREADY : STD_LOGIC; + signal Conn1_ARVALID : STD_LOGIC; + signal Conn1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_AWREADY : STD_LOGIC; + signal Conn1_AWVALID : STD_LOGIC; + signal Conn1_BREADY : STD_LOGIC; + signal Conn1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn1_BVALID : STD_LOGIC; + signal Conn1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_RREADY : STD_LOGIC; + signal Conn1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn1_RVALID : STD_LOGIC; + signal Conn1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_WREADY : STD_LOGIC; + signal Conn1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn1_WVALID : STD_LOGIC; + signal Conn2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal Conn2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn2_ARREADY : STD_LOGIC; + signal Conn2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal Conn2_ARVALID : STD_LOGIC; + signal Conn2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn2_AWREADY : STD_LOGIC; + signal Conn2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal Conn2_AWVALID : STD_LOGIC; + signal Conn2_BREADY : STD_LOGIC; + signal Conn2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_BVALID : STD_LOGIC; + signal Conn2_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal Conn2_RLAST : STD_LOGIC; + signal Conn2_RREADY : STD_LOGIC; + signal Conn2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_RVALID : STD_LOGIC; + signal Conn2_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_WLAST : STD_LOGIC; + signal Conn2_WREADY : STD_LOGIC; + signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn2_WVALID : STD_LOGIC; + signal RESETN_1 : STD_LOGIC; + signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_dma_0_initial_value : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_fifo_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_fifo_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_fifo_0_S_NUM_FREE : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axis_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_fifo_1_M_AXIS_TLAST : STD_LOGIC; + signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC; + signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC; + signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; + signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_axis_dma_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); +begin + CLK_1 <= CLK; + Conn1_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0); + Conn1_ARVALID <= S_AXIL_arvalid; + Conn1_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0); + Conn1_AWVALID <= S_AXIL_awvalid; + Conn1_BREADY <= S_AXIL_bready; + Conn1_RREADY <= S_AXIL_rready; + Conn1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0); + Conn1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0); + Conn1_WVALID <= S_AXIL_wvalid; + Conn2_ARREADY <= M_AXI_arready; + Conn2_AWREADY <= M_AXI_awready; + Conn2_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + Conn2_BVALID <= M_AXI_bvalid; + Conn2_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + Conn2_RID(0) <= M_AXI_rid(0); + Conn2_RLAST <= M_AXI_rlast; + Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + Conn2_RVALID <= M_AXI_rvalid; + Conn2_WREADY <= M_AXI_wready; + M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0); + M_AXI_arid(0) <= Conn2_ARID(0); + M_AXI_arlen(3 downto 0) <= Conn2_ARLEN(3 downto 0); + M_AXI_arsize(2 downto 0) <= Conn2_ARSIZE(2 downto 0); + M_AXI_arvalid <= Conn2_ARVALID; + M_AXI_awaddr(31 downto 0) <= Conn2_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= Conn2_AWBURST(1 downto 0); + M_AXI_awlen(3 downto 0) <= Conn2_AWLEN(3 downto 0); + M_AXI_awsize(2 downto 0) <= Conn2_AWSIZE(2 downto 0); + M_AXI_awvalid <= Conn2_AWVALID; + M_AXI_bready <= Conn2_BREADY; + M_AXI_rready <= Conn2_RREADY; + M_AXI_wdata(31 downto 0) <= Conn2_WDATA(31 downto 0); + M_AXI_wlast <= Conn2_WLAST; + M_AXI_wstrb(3 downto 0) <= Conn2_WSTRB(3 downto 0); + M_AXI_wvalid <= Conn2_WVALID; + RESETN_1 <= RESETN; + S_AXIL_arready <= Conn1_ARREADY; + S_AXIL_awready <= Conn1_AWREADY; + S_AXIL_bresp(1 downto 0) <= Conn1_BRESP(1 downto 0); + S_AXIL_bvalid <= Conn1_BVALID; + S_AXIL_rdata(31 downto 0) <= Conn1_RDATA(31 downto 0); + S_AXIL_rresp(1 downto 0) <= Conn1_RRESP(1 downto 0); + S_AXIL_rvalid <= Conn1_RVALID; + S_AXIL_wready <= Conn1_WREADY; +axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0 + port map ( + CLK => CLK_1, + M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + RESETN => RESETN_1, + S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY, + S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID, + initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0), + polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0) + ); +axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0 + port map ( + CLK => CLK_1, + FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0), + FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0), + M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY, + M_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID, + M_AXI_ARADDR(31 downto 0) => Conn2_ARADDR(31 downto 0), + M_AXI_ARBURST(1 downto 0) => Conn2_ARBURST(1 downto 0), + M_AXI_ARCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0), + M_AXI_ARID(0) => Conn2_ARID(0), + M_AXI_ARLEN(3 downto 0) => Conn2_ARLEN(3 downto 0), + M_AXI_ARPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0), + M_AXI_ARREADY => Conn2_ARREADY, + M_AXI_ARSIZE(2 downto 0) => Conn2_ARSIZE(2 downto 0), + M_AXI_ARVALID => Conn2_ARVALID, + M_AXI_AWADDR(31 downto 0) => Conn2_AWADDR(31 downto 0), + M_AXI_AWBURST(1 downto 0) => Conn2_AWBURST(1 downto 0), + M_AXI_AWCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0), + M_AXI_AWID(0) => NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED(0), + M_AXI_AWLEN(3 downto 0) => Conn2_AWLEN(3 downto 0), + M_AXI_AWPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0), + M_AXI_AWREADY => Conn2_AWREADY, + M_AXI_AWSIZE(2 downto 0) => Conn2_AWSIZE(2 downto 0), + M_AXI_AWVALID => Conn2_AWVALID, + M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000", + M_AXI_BREADY => Conn2_BREADY, + M_AXI_BRESP(1 downto 0) => Conn2_BRESP(1 downto 0), + M_AXI_BVALID => Conn2_BVALID, + M_AXI_RDATA(31 downto 0) => Conn2_RDATA(31 downto 0), + M_AXI_RID(0) => Conn2_RID(0), + M_AXI_RLAST => Conn2_RLAST, + M_AXI_RREADY => Conn2_RREADY, + M_AXI_RRESP(1 downto 0) => Conn2_RRESP(1 downto 0), + M_AXI_RVALID => Conn2_RVALID, + M_AXI_WDATA(31 downto 0) => Conn2_WDATA(31 downto 0), + M_AXI_WID(31 downto 0) => NLW_axis_dma_0_M_AXI_WID_UNCONNECTED(31 downto 0), + M_AXI_WLAST => Conn2_WLAST, + M_AXI_WREADY => Conn2_WREADY, + M_AXI_WSTRB(3 downto 0) => Conn2_WSTRB(3 downto 0), + M_AXI_WVALID => Conn2_WVALID, + RESETN => RESETN_1, + S_AXIL_ARADDR(7 downto 0) => Conn1_ARADDR(7 downto 0), + S_AXIL_ARREADY => Conn1_ARREADY, + S_AXIL_ARVALID => Conn1_ARVALID, + S_AXIL_AWADDR(7 downto 0) => Conn1_AWADDR(7 downto 0), + S_AXIL_AWREADY => Conn1_AWREADY, + S_AXIL_AWVALID => Conn1_AWVALID, + S_AXIL_BREADY => Conn1_BREADY, + S_AXIL_BRESP(1 downto 0) => Conn1_BRESP(1 downto 0), + S_AXIL_BVALID => Conn1_BVALID, + S_AXIL_RDATA(31 downto 0) => Conn1_RDATA(31 downto 0), + S_AXIL_RREADY => Conn1_RREADY, + S_AXIL_RRESP(1 downto 0) => Conn1_RRESP(1 downto 0), + S_AXIL_RVALID => Conn1_RVALID, + S_AXIL_WDATA(31 downto 0) => Conn1_WDATA(31 downto 0), + S_AXIL_WREADY => Conn1_WREADY, + S_AXIL_WSTRB(3 downto 0) => Conn1_WSTRB(3 downto 0), + S_AXIL_WVALID => Conn1_WVALID, + S_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST, + S_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY, + S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID, + initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0), + polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0) + ); +axis_fifo_0: component axi_crc_dma_sim_1_axis_fifo_0_0 + port map ( + M_AXIS_ACLK => CLK_1, + M_AXIS_ARESETN => RESETN_1, + M_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY, + M_AXIS_TUSER(0) => NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED(0), + M_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID, + M_NUM_AVAIL(7 downto 0) => NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED(7 downto 0), + S_AXIS_ACLK => CLK_1, + S_AXIS_ARESETN => RESETN_1, + S_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY, + S_AXIS_TUSER(0) => '0', + S_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID, + S_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0) + ); +axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0 + port map ( + M_AXIS_ACLK => CLK_1, + M_AXIS_ARESETN => RESETN_1, + M_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST, + M_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY, + M_AXIS_TUSER(0) => NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED(0), + M_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID, + M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0), + S_AXIS_ACLK => CLK_1, + S_AXIS_ARESETN => RESETN_1, + S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + S_AXIS_TUSER(0) => '0', + S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity axi_crc_dma_sim_1 is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axi_crc_dma_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=8,numReposBlks=7,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,da_clkrst_cnt=6,synth_mode=OOC_per_IP}"; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1.hwdef"; +end axi_crc_dma_sim_1; + +architecture STRUCTURE of axi_crc_dma_sim_1 is + component axi_crc_dma_sim_1_axil_master_with_rom_0_0 is + port ( + interrupt_in : in STD_LOGIC; + M_AXIL_ACLK : in STD_LOGIC; + M_AXIL_ARESETN : in STD_LOGIC; + M_AXIL_ARREADY : in STD_LOGIC; + M_AXIL_ARVALID : out STD_LOGIC; + M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXIL_RREADY : out STD_LOGIC; + M_AXIL_RVALID : in STD_LOGIC; + M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXIL_AWREADY : in STD_LOGIC; + M_AXIL_AWVALID : out STD_LOGIC; + M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXIL_WREADY : in STD_LOGIC; + M_AXIL_WVALID : out STD_LOGIC; + M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXIL_BREADY : out STD_LOGIC; + M_AXIL_BVALID : in STD_LOGIC; + M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component axi_crc_dma_sim_1_axil_master_with_rom_0_0; + component axi_crc_dma_sim_1_clk_rst_generator_0_0 is + port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + clk : out STD_LOGIC; + rst_n : out STD_LOGIC; + stop_simulation : in STD_LOGIC + ); + end component axi_crc_dma_sim_1_clk_rst_generator_0_0; + component axi_crc_dma_sim_1_axi3_slave_verif_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + S_AXI_ARVALID : in STD_LOGIC; + S_AXI_ARREADY : out STD_LOGIC; + S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_RVALID : out STD_LOGIC; + S_AXI_RREADY : in STD_LOGIC; + S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_RLAST : out STD_LOGIC; + S_AXI_AWVALID : in STD_LOGIC; + S_AXI_AWREADY : out STD_LOGIC; + S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_WVALID : in STD_LOGIC; + S_AXI_WREADY : out STD_LOGIC; + S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_WLAST : in STD_LOGIC; + S_AXI_BVALID : out STD_LOGIC; + S_AXI_BREADY : in STD_LOGIC; + S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component axi_crc_dma_sim_1_axi3_slave_verif_0_0; + signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_crc_dma_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_crc_dma_M_AXI_ARREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_crc_dma_M_AXI_ARVALID : STD_LOGIC; + signal axi_crc_dma_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_crc_dma_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_crc_dma_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_crc_dma_M_AXI_AWREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_crc_dma_M_AXI_AWVALID : STD_LOGIC; + signal axi_crc_dma_M_AXI_BREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_crc_dma_M_AXI_BVALID : STD_LOGIC; + signal axi_crc_dma_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_crc_dma_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_crc_dma_M_AXI_RLAST : STD_LOGIC; + signal axi_crc_dma_M_AXI_RREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_crc_dma_M_AXI_RVALID : STD_LOGIC; + signal axi_crc_dma_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_crc_dma_M_AXI_WLAST : STD_LOGIC; + signal axi_crc_dma_M_AXI_WREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_crc_dma_M_AXI_WVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC; + signal clk_rst_generator_0_clk : STD_LOGIC; + signal clk_rst_generator_0_rst_n : STD_LOGIC; + signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); +begin +axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0 + port map ( + CLK => clk_rst_generator_0_clk, + RESETN => clk_rst_generator_0_rst_n, + S_AXI_ARADDR(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0), + S_AXI_ARBURST(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0), + S_AXI_ARID(0) => axi_crc_dma_M_AXI_ARID(0), + S_AXI_ARLEN(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0), + S_AXI_ARREADY => axi_crc_dma_M_AXI_ARREADY, + S_AXI_ARSIZE(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0), + S_AXI_ARVALID => axi_crc_dma_M_AXI_ARVALID, + S_AXI_AWADDR(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0), + S_AXI_AWBURST(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0), + S_AXI_AWLEN(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0), + S_AXI_AWREADY => axi_crc_dma_M_AXI_AWREADY, + S_AXI_AWSIZE(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0), + S_AXI_AWVALID => axi_crc_dma_M_AXI_AWVALID, + S_AXI_BREADY => axi_crc_dma_M_AXI_BREADY, + S_AXI_BRESP(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0), + S_AXI_BVALID => axi_crc_dma_M_AXI_BVALID, + S_AXI_RDATA(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0), + S_AXI_RID(0) => axi_crc_dma_M_AXI_RID(0), + S_AXI_RLAST => axi_crc_dma_M_AXI_RLAST, + S_AXI_RREADY => axi_crc_dma_M_AXI_RREADY, + S_AXI_RRESP(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0), + S_AXI_RVALID => axi_crc_dma_M_AXI_RVALID, + S_AXI_WDATA(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0), + S_AXI_WLAST => axi_crc_dma_M_AXI_WLAST, + S_AXI_WREADY => axi_crc_dma_M_AXI_WREADY, + S_AXI_WSTRB(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0), + S_AXI_WVALID => axi_crc_dma_M_AXI_WVALID + ); +axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB + port map ( + CLK => clk_rst_generator_0_clk, + M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0), + M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0), + M_AXI_arlen(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0), + M_AXI_arready => axi_crc_dma_M_AXI_ARREADY, + M_AXI_arsize(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0), + M_AXI_arvalid => axi_crc_dma_M_AXI_ARVALID, + M_AXI_awaddr(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0), + M_AXI_awlen(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0), + M_AXI_awready => axi_crc_dma_M_AXI_AWREADY, + M_AXI_awsize(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0), + M_AXI_awvalid => axi_crc_dma_M_AXI_AWVALID, + M_AXI_bready => axi_crc_dma_M_AXI_BREADY, + M_AXI_bresp(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0), + M_AXI_bvalid => axi_crc_dma_M_AXI_BVALID, + M_AXI_rdata(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0), + M_AXI_rid(0) => axi_crc_dma_M_AXI_RID(0), + M_AXI_rlast => axi_crc_dma_M_AXI_RLAST, + M_AXI_rready => axi_crc_dma_M_AXI_RREADY, + M_AXI_rresp(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0), + M_AXI_rvalid => axi_crc_dma_M_AXI_RVALID, + M_AXI_wdata(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0), + M_AXI_wlast => axi_crc_dma_M_AXI_WLAST, + M_AXI_wready => axi_crc_dma_M_AXI_WREADY, + M_AXI_wstrb(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0), + M_AXI_wvalid => axi_crc_dma_M_AXI_WVALID, + RESETN => clk_rst_generator_0_rst_n, + S_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0), + S_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY, + S_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID, + S_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0), + S_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY, + S_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID, + S_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY, + S_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), + S_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID, + S_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), + S_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY, + S_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), + S_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID, + S_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), + S_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY, + S_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), + S_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID + ); +axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0 + port map ( + M_AXIL_ACLK => clk_rst_generator_0_clk, + M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0), + M_AXIL_ARESETN => clk_rst_generator_0_rst_n, + M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0), + M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY, + M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID, + M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0), + M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0), + M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY, + M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID, + M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY, + M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), + M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID, + M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), + M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY, + M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), + M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID, + M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), + M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY, + M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), + M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID, + interrupt_in => '0' + ); +clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0 + port map ( + clk => clk_rst_generator_0_clk, + clk_in => '1', + rst_in => '0', + rst_n => clk_rst_generator_0_rst_n, + stop_simulation => '0' + ); +end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd new file mode 100644 index 0000000..5747598 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd @@ -0,0 +1,680 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Sun Feb 2 01:00:12 2025 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target axi_crc_dma_sim_1.bd +--Design : axi_crc_dma_sim_1 +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity axi_crc_dma_imp_1PQG7GB is + port ( + CLK : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + RESETN : in STD_LOGIC; + S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_arready : out STD_LOGIC; + S_AXIL_arvalid : in STD_LOGIC; + S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_awready : out STD_LOGIC; + S_AXIL_awvalid : in STD_LOGIC; + S_AXIL_bready : in STD_LOGIC; + S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_bvalid : out STD_LOGIC; + S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_rready : in STD_LOGIC; + S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_rvalid : out STD_LOGIC; + S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_wready : out STD_LOGIC; + S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_wvalid : in STD_LOGIC + ); +end axi_crc_dma_imp_1PQG7GB; + +architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is + component axi_crc_dma_sim_1_axis_fifo_0_0 is + port ( + S_AXIS_ACLK : in STD_LOGIC; + S_AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXIS_ACLK : in STD_LOGIC; + M_AXIS_ARESETN : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + end component axi_crc_dma_sim_1_axis_fifo_0_0; + component axi_crc_dma_sim_1_axis_fifo_1_0 is + port ( + S_AXIS_ACLK : in STD_LOGIC; + S_AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXIS_ACLK : in STD_LOGIC; + M_AXIS_ARESETN : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + end component axi_crc_dma_sim_1_axis_fifo_1_0; + component axi_crc_dma_sim_1_axis_crc_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 ); + polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC + ); + end component axi_crc_dma_sim_1_axis_crc_0_0; + component axi_crc_dma_sim_1_axis_dma_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 ); + polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 ); + FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 ); + FIFO_NUM_AVAIL : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXIL_AWVALID : in STD_LOGIC; + S_AXIL_AWREADY : out STD_LOGIC; + S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_WVALID : in STD_LOGIC; + S_AXIL_WREADY : out STD_LOGIC; + S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_BVALID : out STD_LOGIC; + S_AXIL_BREADY : in STD_LOGIC; + S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXIL_ARVALID : in STD_LOGIC; + S_AXIL_ARREADY : out STD_LOGIC; + S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_RVALID : out STD_LOGIC; + S_AXIL_RREADY : in STD_LOGIC; + S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_ARREADY : in STD_LOGIC; + M_AXI_ARVALID : out STD_LOGIC; + M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_RREADY : out STD_LOGIC; + M_AXI_RVALID : in STD_LOGIC; + M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_RLAST : in STD_LOGIC; + M_AXI_AWREADY : in STD_LOGIC; + M_AXI_AWVALID : out STD_LOGIC; + M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WREADY : in STD_LOGIC; + M_AXI_WVALID : out STD_LOGIC; + M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WLAST : out STD_LOGIC; + M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_BREADY : out STD_LOGIC; + M_AXI_BVALID : in STD_LOGIC; + M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC + ); + end component axi_crc_dma_sim_1_axis_dma_0_0; + signal CLK_1 : STD_LOGIC; + signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_ARREADY : STD_LOGIC; + signal Conn1_ARVALID : STD_LOGIC; + signal Conn1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_AWREADY : STD_LOGIC; + signal Conn1_AWVALID : STD_LOGIC; + signal Conn1_BREADY : STD_LOGIC; + signal Conn1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn1_BVALID : STD_LOGIC; + signal Conn1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_RREADY : STD_LOGIC; + signal Conn1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn1_RVALID : STD_LOGIC; + signal Conn1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_WREADY : STD_LOGIC; + signal Conn1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn1_WVALID : STD_LOGIC; + signal Conn2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal Conn2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn2_ARREADY : STD_LOGIC; + signal Conn2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal Conn2_ARVALID : STD_LOGIC; + signal Conn2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn2_AWREADY : STD_LOGIC; + signal Conn2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal Conn2_AWVALID : STD_LOGIC; + signal Conn2_BREADY : STD_LOGIC; + signal Conn2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_BVALID : STD_LOGIC; + signal Conn2_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal Conn2_RLAST : STD_LOGIC; + signal Conn2_RREADY : STD_LOGIC; + signal Conn2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_RVALID : STD_LOGIC; + signal Conn2_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_WLAST : STD_LOGIC; + signal Conn2_WREADY : STD_LOGIC; + signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn2_WVALID : STD_LOGIC; + signal RESETN_1 : STD_LOGIC; + signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_dma_0_initial_value : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_fifo_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_fifo_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_fifo_0_S_NUM_FREE : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axis_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_fifo_1_M_AXIS_TLAST : STD_LOGIC; + signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC; + signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC; + signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; + signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_axis_dma_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); +begin + CLK_1 <= CLK; + Conn1_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0); + Conn1_ARVALID <= S_AXIL_arvalid; + Conn1_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0); + Conn1_AWVALID <= S_AXIL_awvalid; + Conn1_BREADY <= S_AXIL_bready; + Conn1_RREADY <= S_AXIL_rready; + Conn1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0); + Conn1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0); + Conn1_WVALID <= S_AXIL_wvalid; + Conn2_ARREADY <= M_AXI_arready; + Conn2_AWREADY <= M_AXI_awready; + Conn2_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + Conn2_BVALID <= M_AXI_bvalid; + Conn2_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + Conn2_RID(0) <= M_AXI_rid(0); + Conn2_RLAST <= M_AXI_rlast; + Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + Conn2_RVALID <= M_AXI_rvalid; + Conn2_WREADY <= M_AXI_wready; + M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0); + M_AXI_arid(0) <= Conn2_ARID(0); + M_AXI_arlen(3 downto 0) <= Conn2_ARLEN(3 downto 0); + M_AXI_arsize(2 downto 0) <= Conn2_ARSIZE(2 downto 0); + M_AXI_arvalid <= Conn2_ARVALID; + M_AXI_awaddr(31 downto 0) <= Conn2_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= Conn2_AWBURST(1 downto 0); + M_AXI_awlen(3 downto 0) <= Conn2_AWLEN(3 downto 0); + M_AXI_awsize(2 downto 0) <= Conn2_AWSIZE(2 downto 0); + M_AXI_awvalid <= Conn2_AWVALID; + M_AXI_bready <= Conn2_BREADY; + M_AXI_rready <= Conn2_RREADY; + M_AXI_wdata(31 downto 0) <= Conn2_WDATA(31 downto 0); + M_AXI_wlast <= Conn2_WLAST; + M_AXI_wstrb(3 downto 0) <= Conn2_WSTRB(3 downto 0); + M_AXI_wvalid <= Conn2_WVALID; + RESETN_1 <= RESETN; + S_AXIL_arready <= Conn1_ARREADY; + S_AXIL_awready <= Conn1_AWREADY; + S_AXIL_bresp(1 downto 0) <= Conn1_BRESP(1 downto 0); + S_AXIL_bvalid <= Conn1_BVALID; + S_AXIL_rdata(31 downto 0) <= Conn1_RDATA(31 downto 0); + S_AXIL_rresp(1 downto 0) <= Conn1_RRESP(1 downto 0); + S_AXIL_rvalid <= Conn1_RVALID; + S_AXIL_wready <= Conn1_WREADY; +axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0 + port map ( + CLK => CLK_1, + M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + RESETN => RESETN_1, + S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY, + S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID, + initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0), + polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0) + ); +axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0 + port map ( + CLK => CLK_1, + FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0), + FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0), + M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY, + M_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID, + M_AXI_ARADDR(31 downto 0) => Conn2_ARADDR(31 downto 0), + M_AXI_ARBURST(1 downto 0) => Conn2_ARBURST(1 downto 0), + M_AXI_ARCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0), + M_AXI_ARID(0) => Conn2_ARID(0), + M_AXI_ARLEN(3 downto 0) => Conn2_ARLEN(3 downto 0), + M_AXI_ARPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0), + M_AXI_ARREADY => Conn2_ARREADY, + M_AXI_ARSIZE(2 downto 0) => Conn2_ARSIZE(2 downto 0), + M_AXI_ARVALID => Conn2_ARVALID, + M_AXI_AWADDR(31 downto 0) => Conn2_AWADDR(31 downto 0), + M_AXI_AWBURST(1 downto 0) => Conn2_AWBURST(1 downto 0), + M_AXI_AWCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0), + M_AXI_AWID(0) => NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED(0), + M_AXI_AWLEN(3 downto 0) => Conn2_AWLEN(3 downto 0), + M_AXI_AWPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0), + M_AXI_AWREADY => Conn2_AWREADY, + M_AXI_AWSIZE(2 downto 0) => Conn2_AWSIZE(2 downto 0), + M_AXI_AWVALID => Conn2_AWVALID, + M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000", + M_AXI_BREADY => Conn2_BREADY, + M_AXI_BRESP(1 downto 0) => Conn2_BRESP(1 downto 0), + M_AXI_BVALID => Conn2_BVALID, + M_AXI_RDATA(31 downto 0) => Conn2_RDATA(31 downto 0), + M_AXI_RID(0) => Conn2_RID(0), + M_AXI_RLAST => Conn2_RLAST, + M_AXI_RREADY => Conn2_RREADY, + M_AXI_RRESP(1 downto 0) => Conn2_RRESP(1 downto 0), + M_AXI_RVALID => Conn2_RVALID, + M_AXI_WDATA(31 downto 0) => Conn2_WDATA(31 downto 0), + M_AXI_WID(31 downto 0) => NLW_axis_dma_0_M_AXI_WID_UNCONNECTED(31 downto 0), + M_AXI_WLAST => Conn2_WLAST, + M_AXI_WREADY => Conn2_WREADY, + M_AXI_WSTRB(3 downto 0) => Conn2_WSTRB(3 downto 0), + M_AXI_WVALID => Conn2_WVALID, + RESETN => RESETN_1, + S_AXIL_ARADDR(7 downto 0) => Conn1_ARADDR(7 downto 0), + S_AXIL_ARREADY => Conn1_ARREADY, + S_AXIL_ARVALID => Conn1_ARVALID, + S_AXIL_AWADDR(7 downto 0) => Conn1_AWADDR(7 downto 0), + S_AXIL_AWREADY => Conn1_AWREADY, + S_AXIL_AWVALID => Conn1_AWVALID, + S_AXIL_BREADY => Conn1_BREADY, + S_AXIL_BRESP(1 downto 0) => Conn1_BRESP(1 downto 0), + S_AXIL_BVALID => Conn1_BVALID, + S_AXIL_RDATA(31 downto 0) => Conn1_RDATA(31 downto 0), + S_AXIL_RREADY => Conn1_RREADY, + S_AXIL_RRESP(1 downto 0) => Conn1_RRESP(1 downto 0), + S_AXIL_RVALID => Conn1_RVALID, + S_AXIL_WDATA(31 downto 0) => Conn1_WDATA(31 downto 0), + S_AXIL_WREADY => Conn1_WREADY, + S_AXIL_WSTRB(3 downto 0) => Conn1_WSTRB(3 downto 0), + S_AXIL_WVALID => Conn1_WVALID, + S_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST, + S_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY, + S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID, + initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0), + polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0) + ); +axis_fifo_0: component axi_crc_dma_sim_1_axis_fifo_0_0 + port map ( + M_AXIS_ACLK => CLK_1, + M_AXIS_ARESETN => RESETN_1, + M_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY, + M_AXIS_TUSER(0) => NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED(0), + M_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID, + M_NUM_AVAIL(7 downto 0) => NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED(7 downto 0), + S_AXIS_ACLK => CLK_1, + S_AXIS_ARESETN => RESETN_1, + S_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY, + S_AXIS_TUSER(0) => '0', + S_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID, + S_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0) + ); +axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0 + port map ( + M_AXIS_ACLK => CLK_1, + M_AXIS_ARESETN => RESETN_1, + M_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST, + M_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY, + M_AXIS_TUSER(0) => NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED(0), + M_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID, + M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0), + S_AXIS_ACLK => CLK_1, + S_AXIS_ARESETN => RESETN_1, + S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + S_AXIS_TUSER(0) => '0', + S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity axi_crc_dma_sim_1 is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axi_crc_dma_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=8,numReposBlks=7,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,da_clkrst_cnt=6,synth_mode=OOC_per_IP}"; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1.hwdef"; +end axi_crc_dma_sim_1; + +architecture STRUCTURE of axi_crc_dma_sim_1 is + component axi_crc_dma_sim_1_axil_master_with_rom_0_0 is + port ( + interrupt_in : in STD_LOGIC; + M_AXIL_ACLK : in STD_LOGIC; + M_AXIL_ARESETN : in STD_LOGIC; + M_AXIL_ARREADY : in STD_LOGIC; + M_AXIL_ARVALID : out STD_LOGIC; + M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXIL_RREADY : out STD_LOGIC; + M_AXIL_RVALID : in STD_LOGIC; + M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXIL_AWREADY : in STD_LOGIC; + M_AXIL_AWVALID : out STD_LOGIC; + M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXIL_WREADY : in STD_LOGIC; + M_AXIL_WVALID : out STD_LOGIC; + M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXIL_BREADY : out STD_LOGIC; + M_AXIL_BVALID : in STD_LOGIC; + M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component axi_crc_dma_sim_1_axil_master_with_rom_0_0; + component axi_crc_dma_sim_1_clk_rst_generator_0_0 is + port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + clk : out STD_LOGIC; + rst_n : out STD_LOGIC; + stop_simulation : in STD_LOGIC + ); + end component axi_crc_dma_sim_1_clk_rst_generator_0_0; + component axi_crc_dma_sim_1_axi3_slave_verif_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + S_AXI_ARVALID : in STD_LOGIC; + S_AXI_ARREADY : out STD_LOGIC; + S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_RVALID : out STD_LOGIC; + S_AXI_RREADY : in STD_LOGIC; + S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_RLAST : out STD_LOGIC; + S_AXI_AWVALID : in STD_LOGIC; + S_AXI_AWREADY : out STD_LOGIC; + S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_WVALID : in STD_LOGIC; + S_AXI_WREADY : out STD_LOGIC; + S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_WLAST : in STD_LOGIC; + S_AXI_BVALID : out STD_LOGIC; + S_AXI_BREADY : in STD_LOGIC; + S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component axi_crc_dma_sim_1_axi3_slave_verif_0_0; + signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_crc_dma_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_crc_dma_M_AXI_ARREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_crc_dma_M_AXI_ARVALID : STD_LOGIC; + signal axi_crc_dma_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_crc_dma_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_crc_dma_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_crc_dma_M_AXI_AWREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_crc_dma_M_AXI_AWVALID : STD_LOGIC; + signal axi_crc_dma_M_AXI_BREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_crc_dma_M_AXI_BVALID : STD_LOGIC; + signal axi_crc_dma_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_crc_dma_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_crc_dma_M_AXI_RLAST : STD_LOGIC; + signal axi_crc_dma_M_AXI_RREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_crc_dma_M_AXI_RVALID : STD_LOGIC; + signal axi_crc_dma_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_crc_dma_M_AXI_WLAST : STD_LOGIC; + signal axi_crc_dma_M_AXI_WREADY : STD_LOGIC; + signal axi_crc_dma_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_crc_dma_M_AXI_WVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC; + signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC; + signal clk_rst_generator_0_clk : STD_LOGIC; + signal clk_rst_generator_0_rst_n : STD_LOGIC; + signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); +begin +axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0 + port map ( + CLK => clk_rst_generator_0_clk, + RESETN => clk_rst_generator_0_rst_n, + S_AXI_ARADDR(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0), + S_AXI_ARBURST(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0), + S_AXI_ARID(0) => axi_crc_dma_M_AXI_ARID(0), + S_AXI_ARLEN(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0), + S_AXI_ARREADY => axi_crc_dma_M_AXI_ARREADY, + S_AXI_ARSIZE(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0), + S_AXI_ARVALID => axi_crc_dma_M_AXI_ARVALID, + S_AXI_AWADDR(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0), + S_AXI_AWBURST(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0), + S_AXI_AWLEN(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0), + S_AXI_AWREADY => axi_crc_dma_M_AXI_AWREADY, + S_AXI_AWSIZE(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0), + S_AXI_AWVALID => axi_crc_dma_M_AXI_AWVALID, + S_AXI_BREADY => axi_crc_dma_M_AXI_BREADY, + S_AXI_BRESP(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0), + S_AXI_BVALID => axi_crc_dma_M_AXI_BVALID, + S_AXI_RDATA(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0), + S_AXI_RID(0) => axi_crc_dma_M_AXI_RID(0), + S_AXI_RLAST => axi_crc_dma_M_AXI_RLAST, + S_AXI_RREADY => axi_crc_dma_M_AXI_RREADY, + S_AXI_RRESP(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0), + S_AXI_RVALID => axi_crc_dma_M_AXI_RVALID, + S_AXI_WDATA(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0), + S_AXI_WLAST => axi_crc_dma_M_AXI_WLAST, + S_AXI_WREADY => axi_crc_dma_M_AXI_WREADY, + S_AXI_WSTRB(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0), + S_AXI_WVALID => axi_crc_dma_M_AXI_WVALID + ); +axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB + port map ( + CLK => clk_rst_generator_0_clk, + M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0), + M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0), + M_AXI_arlen(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0), + M_AXI_arready => axi_crc_dma_M_AXI_ARREADY, + M_AXI_arsize(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0), + M_AXI_arvalid => axi_crc_dma_M_AXI_ARVALID, + M_AXI_awaddr(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0), + M_AXI_awlen(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0), + M_AXI_awready => axi_crc_dma_M_AXI_AWREADY, + M_AXI_awsize(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0), + M_AXI_awvalid => axi_crc_dma_M_AXI_AWVALID, + M_AXI_bready => axi_crc_dma_M_AXI_BREADY, + M_AXI_bresp(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0), + M_AXI_bvalid => axi_crc_dma_M_AXI_BVALID, + M_AXI_rdata(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0), + M_AXI_rid(0) => axi_crc_dma_M_AXI_RID(0), + M_AXI_rlast => axi_crc_dma_M_AXI_RLAST, + M_AXI_rready => axi_crc_dma_M_AXI_RREADY, + M_AXI_rresp(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0), + M_AXI_rvalid => axi_crc_dma_M_AXI_RVALID, + M_AXI_wdata(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0), + M_AXI_wlast => axi_crc_dma_M_AXI_WLAST, + M_AXI_wready => axi_crc_dma_M_AXI_WREADY, + M_AXI_wstrb(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0), + M_AXI_wvalid => axi_crc_dma_M_AXI_WVALID, + RESETN => clk_rst_generator_0_rst_n, + S_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0), + S_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY, + S_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID, + S_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0), + S_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY, + S_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID, + S_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY, + S_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), + S_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID, + S_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), + S_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY, + S_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), + S_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID, + S_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), + S_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY, + S_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), + S_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID + ); +axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0 + port map ( + M_AXIL_ACLK => clk_rst_generator_0_clk, + M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0), + M_AXIL_ARESETN => clk_rst_generator_0_rst_n, + M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0), + M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY, + M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID, + M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0), + M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0), + M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY, + M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID, + M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY, + M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), + M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID, + M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), + M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY, + M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), + M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID, + M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), + M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY, + M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), + M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID, + interrupt_in => '0' + ); +clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0 + port map ( + clk => clk_rst_generator_0_clk, + clk_in => '1', + rst_in => '0', + rst_n => clk_rst_generator_0_rst_n, + stop_simulation => '0' + ); +end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml index ac3ad88..30d9736 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml @@ -2,10 +2,55 @@ Composite Fileset - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc new file mode 100644 index 0000000..7fac2b2 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc @@ -0,0 +1,10 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ + +################################################################################ \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd index 58aab11..f3624fd 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd @@ -2,7 +2,7 @@ --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Sat Feb 1 17:06:13 2025 +--Date : Sun Feb 2 00:16:45 2025 --Host : BiermannSurface running 64-bit major release (build 9200) --Command : generate_target axis_crc_sim_1_wrapper.bd --Design : axis_crc_sim_1_wrapper diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml index 8b11386..4071b75 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml @@ -436,6 +436,83 @@ + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_crc + + + outputProductCRC + 9:7d52f37a + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + axis_crc + + + outputProductCRC + 9:3fed59a8 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:3fed59a8 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axis_crc_sim_1_axis_crc_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:16:45 UTC 2025 + + + outputProductCRC + 9:7d52f37a + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + axis_crc_sim_1_axis_crc_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:59:37 UTC 2025 + + + outputProductCRC + 9:3fed59a8 + + + + CLK @@ -444,7 +521,8 @@ std_logic - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -456,7 +534,8 @@ std_logic - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -472,7 +551,8 @@ std_logic_vector - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -488,7 +568,8 @@ std_logic_vector - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -500,7 +581,8 @@ std_logic - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -516,7 +598,8 @@ std_logic_vector - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -531,7 +614,8 @@ std_logic - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -546,7 +630,8 @@ std_logic - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -558,7 +643,8 @@ std_logic - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -574,7 +660,8 @@ std_logic_vector - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -586,7 +673,8 @@ std_logic - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -598,7 +686,8 @@ std_logic - dummy_view + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -615,6 +704,24 @@ ACTIVE_LOW + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_axis_crc_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/axis_crc_sim_1_axis_crc_0_0.vhd + vhdlSource + xil_defaultlib + + + xilinx.com:module_ref:axis_crc:1.0 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/synth/axis_crc_sim_1_axis_crc_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/synth/axis_crc_sim_1_axis_crc_0_0.vhd new file mode 100644 index 0000000..3007447 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/synth/axis_crc_sim_1_axis_crc_0_0.vhd @@ -0,0 +1,132 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:axis_crc:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_axis_crc_0_0 IS + PORT ( + CLK : IN STD_LOGIC; + RESETN : IN STD_LOGIC; + initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC + ); +END axis_crc_sim_1_axis_crc_0_0; + +ARCHITECTURE axis_crc_sim_1_axis_crc_0_0_arch OF axis_crc_sim_1_axis_crc_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_crc IS + PORT ( + CLK : IN STD_LOGIC; + RESETN : IN STD_LOGIC; + initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC + ); + END COMPONENT axis_crc; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc,Vivado 2023.1"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_axis_crc_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_axis_crc_0_0,axis_crc,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc_sim_1_axis_crc_0_0,axis_crc,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_crc,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_crc + PORT MAP ( + CLK => CLK, + RESETN => RESETN, + initial_value => initial_value, + polynomial => polynomial, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY + ); +END axis_crc_sim_1_axis_crc_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xml index 7e90f66..e00d054 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xml @@ -286,6 +286,17 @@ + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:7759c31b + + + xilinx_vhdlbehavioralsimulation VHDL Simulation @@ -326,6 +337,46 @@ + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_master_simmodel + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:7759c31b + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + axis_crc_sim_1_axis_master_simmodel_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:59:36 UTC 2025 + + + outputProductCRC + 9:7759c31b + + + @@ -335,6 +386,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -347,6 +399,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -359,6 +412,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -371,6 +425,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -387,6 +442,7 @@ std_logic_vector + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -399,6 +455,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -411,6 +468,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -427,6 +485,7 @@ std_logic_vector + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -443,6 +502,7 @@ std_logic_vector + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -591,6 +651,25 @@ xil_defaultlib + + xilinx_vhdlsynthesis_view_fileset + + ../../ipshared/d44d/bmp_pkg.vhd + vhdlSource + + + ../../ipshared/d44d/axis_master_simmodel.vhd + vhdlSource + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/axis_crc_sim_1_axis_master_simmodel_0_0.vhd + vhdlSource + xil_defaultlib + + axis_master_simmodel diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/synth/axis_crc_sim_1_axis_master_simmodel_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/synth/axis_crc_sim_1_axis_master_simmodel_0_0.vhd new file mode 100644 index 0000000..f2a8b3a --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/synth/axis_crc_sim_1_axis_master_simmodel_0_0.vhd @@ -0,0 +1,156 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: Gehrke:user:axis_master_simmodel:1.0 +-- IP Revision: 10 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_axis_master_simmodel_0_0 IS + PORT ( + ACLK : IN STD_LOGIC; + ARESETN : IN STD_LOGIC; + FINISHED : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END axis_crc_sim_1_axis_master_simmodel_0_0; + +ARCHITECTURE axis_crc_sim_1_axis_master_simmodel_0_0_arch OF axis_crc_sim_1_axis_master_simmodel_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_master_simmodel_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_master_simmodel IS + GENERIC ( + DATA_WIDTH : INTEGER; + HAS_FIFO_INTERFACE : BOOLEAN; + FIFO_AWIDTH : INTEGER; + FIFO_REQUEST_TRESHOLD : INTEGER; + TUSERWIDTH : INTEGER; + FILE_NAME : STRING; + FILE_EXTENSION : STRING; + FILE_AUTONUMBERING : BOOLEAN; + NUM_PIX_PER_LINE : INTEGER; + NUM_LINES : INTEGER; + NUM_FRAMES_PER_FILE : INTEGER; + RANDOM_TVALID : BOOLEAN; + PIXEL_FORMAT : INTEGER; + ALPHA_VALUE : INTEGER; + FRAMING_PIXELS : INTEGER; + FRAMING_LINES : INTEGER; + FRAMING_VAL_R_V : INTEGER; + FRAMING_VAL_G_Y : INTEGER; + FRAMING_VAL_B_U : INTEGER + ); + PORT ( + ACLK : IN STD_LOGIC; + ARESETN : IN STD_LOGIC; + FINISHED : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_AXIS_NUM_FREE : IN STD_LOGIC_VECTOR(10 DOWNTO 0) + ); + END COMPONENT axis_master_simmodel; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_axis_master_simmodel_0_0_arch: ARCHITECTURE IS "axis_master_simmodel,Vivado 2023.1"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_axis_master_simmodel_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_axis_master_simmodel_0_0,axis_master_simmodel,{}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; +BEGIN + U0 : axis_master_simmodel + GENERIC MAP ( + DATA_WIDTH => 32, + HAS_FIFO_INTERFACE => false, + FIFO_AWIDTH => 11, + FIFO_REQUEST_TRESHOLD => 32, + TUSERWIDTH => 1, + FILE_NAME => "../../../../tst", + FILE_EXTENSION => "raw", + FILE_AUTONUMBERING => false, + NUM_PIX_PER_LINE => 3, + NUM_LINES => 1, + NUM_FRAMES_PER_FILE => 1, + RANDOM_TVALID => true, + PIXEL_FORMAT => 1, + ALPHA_VALUE => 255, + FRAMING_PIXELS => 0, + FRAMING_LINES => 0, + FRAMING_VAL_R_V => 128, + FRAMING_VAL_G_Y => 128, + FRAMING_VAL_B_U => 128 + ) + PORT MAP ( + ACLK => ACLK, + ARESETN => ARESETN, + FINISHED => FINISHED, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_NUM_FREE => STD_LOGIC_VECTOR(TO_UNSIGNED(1, 11)) + ); +END axis_crc_sim_1_axis_master_simmodel_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xml index 519c740..2be957d 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xml @@ -281,6 +281,17 @@ + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:69398033 + + + xilinx_vhdlbehavioralsimulation VHDL Simulation @@ -321,6 +332,46 @@ + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_slave_simmodel + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:69398033 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + axis_crc_sim_1_axis_slave_simmodel_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:59:36 UTC 2025 + + + outputProductCRC + 9:69398033 + + + @@ -330,6 +381,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -342,6 +394,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -354,6 +407,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -366,6 +420,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -382,6 +437,7 @@ std_logic_vector + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -394,6 +450,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -406,6 +463,7 @@ std_logic + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -422,6 +480,7 @@ std_logic_vector + xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation @@ -525,6 +584,25 @@ xil_defaultlib + + xilinx_vhdlsynthesis_view_fileset + + ../../ipshared/c453/bmp_pkg.vhd + vhdlSource + + + ../../ipshared/c453/axis_slave_simmodel.vhd + vhdlSource + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd + vhdlSource + xil_defaultlib + + axis_slave_simmodel_v1_0 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/synth/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/synth/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd new file mode 100644 index 0000000..5618983 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/synth/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd @@ -0,0 +1,140 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: Gehrke:user:axis_slave_simmodel:1.0 +-- IP Revision: 4 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_axis_slave_simmodel_0_0 IS + PORT ( + FINISHED : OUT STD_LOGIC; + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END axis_crc_sim_1_axis_slave_simmodel_0_0; + +ARCHITECTURE axis_crc_sim_1_axis_slave_simmodel_0_0_arch OF axis_crc_sim_1_axis_slave_simmodel_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_slave_simmodel_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_slave_simmodel IS + GENERIC ( + TUSERWIDTH : INTEGER; + FILE_NAME : STRING; + FILE_EXTENSION : STRING; + FILE_AUTONUMBERING : BOOLEAN; + PIXEL_FORMAT : INTEGER; + NUM_PIX_PER_LINE : INTEGER; + NUM_LINES : INTEGER; + NUM_FRAMES_PER_FILE : INTEGER; + NUM_FILES : INTEGER; + FRAMING_PIXELS : INTEGER; + FRAMING_LINES : INTEGER; + RANDOM_TREADY : BOOLEAN + ); + PORT ( + FINISHED : OUT STD_LOGIC; + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT axis_slave_simmodel; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_axis_slave_simmodel_0_0_arch: ARCHITECTURE IS "axis_slave_simmodel,Vivado 2023.1"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_axis_slave_simmodel_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_axis_slave_simmodel_0_0,axis_slave_simmodel,{}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_slave_simmodel + GENERIC MAP ( + TUSERWIDTH => 1, + FILE_NAME => "../../../../tst_out", + FILE_EXTENSION => "raw", + FILE_AUTONUMBERING => false, + PIXEL_FORMAT => 1, + NUM_PIX_PER_LINE => 3, + NUM_LINES => 1, + NUM_FRAMES_PER_FILE => 1, + NUM_FILES => 1, + FRAMING_PIXELS => 0, + FRAMING_LINES => 0, + RANDOM_TREADY => true + ) + PORT MAP ( + FINISHED => FINISHED, + S_AXIS_ACLK => S_AXIS_ACLK, + S_AXIS_ARESETN => S_AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TUSER => S_AXIS_TUSER + ); +END axis_crc_sim_1_axis_slave_simmodel_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xml index 6e3b10f..acf6c3e 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xml @@ -25,6 +25,36 @@ + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + clk_rst_generator + + xilinx_anylanguagesynthesis_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:bbae1481 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:bbae1481 + + + xilinx_vhdlsimulationwrapper VHDL Simulation Wrapper @@ -45,6 +75,26 @@ + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + axis_crc_sim_1_clk_rst_generator_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:59:36 UTC 2025 + + + outputProductCRC + 9:bbae1481 + + + @@ -54,6 +104,7 @@ std_logic + xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation @@ -76,6 +127,7 @@ std_logic + xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation @@ -98,6 +150,7 @@ std_logic + xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation @@ -110,6 +163,7 @@ std_logic + xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation @@ -122,6 +176,7 @@ std_logic + xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation @@ -169,6 +224,25 @@ vhdlSource + + xilinx_anylanguagesynthesis_view_fileset + + constrs_1/new/clk_rst_generator.xdc + xdc + + + constrs_1/new/clk_rst_generator_ooc.xdc + xdc + + + constrs_1/new/clk_rst_generator_clocks.xdc + xdc + + + ../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd + vhdlSource + + xilinx_vhdlsimulationwrapper_view_fileset @@ -177,6 +251,14 @@ xil_defaultlib + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/axis_crc_sim_1_clk_rst_generator_0_0.vhd + vhdlSource + xil_defaultlib + + clk_rst_generator diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator.xdc b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator.xdc new file mode 100644 index 0000000..e69de29 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_clocks.xdc b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_clocks.xdc new file mode 100644 index 0000000..e69de29 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_ooc.xdc b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_ooc.xdc new file mode 100644 index 0000000..8b930e8 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_ooc.xdc @@ -0,0 +1 @@ +create_clock -period 10.000 -name clk_in -waveform {0.000 5.000} [get_ports clk_in] \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/synth/axis_crc_sim_1_clk_rst_generator_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/synth/axis_crc_sim_1_clk_rst_generator_0_0.vhd new file mode 100644 index 0000000..26677fb --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/synth/axis_crc_sim_1_clk_rst_generator_0_0.vhd @@ -0,0 +1,105 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: wg:user:clk_rst_generator:1.0 +-- IP Revision: 7 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_clk_rst_generator_0_0 IS + PORT ( + clk_in : IN STD_LOGIC; + rst_in : IN STD_LOGIC; + clk : OUT STD_LOGIC; + rst_n : OUT STD_LOGIC; + stop_simulation : IN STD_LOGIC + ); +END axis_crc_sim_1_clk_rst_generator_0_0; + +ARCHITECTURE axis_crc_sim_1_clk_rst_generator_0_0_arch OF axis_crc_sim_1_clk_rst_generator_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT clk_rst_generator IS + GENERIC ( + CLOCK_PERIOD : INTEGER; + HAS_CLK_INPUT : BOOLEAN; + HAS_RESET_INPUT : BOOLEAN; + HAS_STOP_INPUT : BOOLEAN + ); + PORT ( + clk_in : IN STD_LOGIC; + rst_in : IN STD_LOGIC; + clk : OUT STD_LOGIC; + rst_n : OUT STD_LOGIC; + stop_simulation : IN STD_LOGIC + ); + END COMPONENT clk_rst_generator; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "clk_rst_generator,Vivado 2023.1"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_clk_rst_generator_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_clk_rst_generator_0_0,clk_rst_generator,{}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF axis_crc_sim_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "package_project"; +BEGIN + U0 : clk_rst_generator + GENERIC MAP ( + CLOCK_PERIOD => 10000, + HAS_CLK_INPUT => true, + HAS_RESET_INPUT => true, + HAS_STOP_INPUT => true + ) + PORT MAP ( + clk_in => clk_in, + rst_in => rst_in, + clk => clk, + rst_n => rst_n, + stop_simulation => stop_simulation + ); +END axis_crc_sim_1_clk_rst_generator_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xml index 6a9522f..4fac904 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xml @@ -6,6 +6,17 @@ 1.0 + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:e2c6de17 + + + xilinx_systemcsimulation SystemC Simulation @@ -94,6 +105,46 @@ + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:e2c6de17 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + axis_crc_sim_1_xlconstant_0_0 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:59:36 UTC 2025 + + + outputProductCRC + 9:e2c6de17 + + + @@ -107,7 +158,8 @@ std_logic_vector - xilinx_verilogbehavioralsimulation + xilinx_verilogsynthesis + xilinx_systemcsimulation @@ -168,6 +220,22 @@ xil_defaultlib + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + xlconstant_v1_1_7 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axis_crc_sim_1_xlconstant_0_0.v + verilogSource + xil_defaultlib + + Gives a constant signed value. diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/synth/axis_crc_sim_1_xlconstant_0_0.v similarity index 83% rename from Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0.v rename to Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/synth/axis_crc_sim_1_xlconstant_0_0.v index e4c704b..7ccfd1b 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0.v +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/synth/axis_crc_sim_1_xlconstant_0_0.v @@ -50,10 +50,11 @@ // IP VLNV: xilinx.com:ip:xlconstant:1.1 // IP Revision: 7 -`timescale 1ns/1ps - +(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2023.1" *) +(* CHECK_LICENSE_TYPE = "axis_crc_sim_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{}" *) +(* CORE_GENERATION_INFO = "axis_crc_sim_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=32,CONST_VAL=0x00000001}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) -module test_1_xlconstant_1_0 ( +module axis_crc_sim_1_xlconstant_0_0 ( dout ); @@ -61,7 +62,7 @@ output wire [31 : 0] dout; xlconstant_v1_1_7_xlconstant #( .CONST_WIDTH(32), - .CONST_VAL(32'H00000000) + .CONST_VAL(32'H00000001) ) inst ( .dout(dout) ); diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xml index 7481c11..9e7df1d 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xml @@ -6,6 +6,17 @@ 1.0 + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:fe058b70 + + + xilinx_systemcsimulation SystemC Simulation @@ -94,6 +105,46 @@ + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:fe058b70 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + axis_crc_sim_1_xlconstant_1_0 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 23:59:36 UTC 2025 + + + outputProductCRC + 9:fe058b70 + + + @@ -107,7 +158,8 @@ std_logic_vector - xilinx_verilogbehavioralsimulation + xilinx_verilogsynthesis + xilinx_systemcsimulation @@ -168,6 +220,22 @@ xil_defaultlib + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + xlconstant_v1_1_7 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axis_crc_sim_1_xlconstant_1_0.v + verilogSource + xil_defaultlib + + Gives a constant signed value. diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/synth/axis_crc_sim_1_xlconstant_1_0.v similarity index 83% rename from Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0.v rename to Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/synth/axis_crc_sim_1_xlconstant_1_0.v index 460bc8f..0a4d40d 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0.v +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/synth/axis_crc_sim_1_xlconstant_1_0.v @@ -50,10 +50,11 @@ // IP VLNV: xilinx.com:ip:xlconstant:1.1 // IP Revision: 7 -`timescale 1ns/1ps - +(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2023.1" *) +(* CHECK_LICENSE_TYPE = "axis_crc_sim_1_xlconstant_1_0,xlconstant_v1_1_7_xlconstant,{}" *) +(* CORE_GENERATION_INFO = "axis_crc_sim_1_xlconstant_1_0,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=32,CONST_VAL=0x00000001}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) -module test_1_xlconstant_0_0 ( +module axis_crc_sim_1_xlconstant_1_0 ( dout ); @@ -61,7 +62,7 @@ output wire [31 : 0] dout; xlconstant_v1_1_7_xlconstant #( .CONST_WIDTH(32), - .CONST_VAL(32'H00000000) + .CONST_VAL(32'H00000001) ) inst ( .dout(dout) ); diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd new file mode 100644 index 0000000..32cbc36 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd @@ -0,0 +1,151 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Sun Feb 2 00:16:45 2025 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target axis_crc_sim_1.bd +--Design : axis_crc_sim_1 +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity axis_crc_sim_1 is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef"; +end axis_crc_sim_1; + +architecture STRUCTURE of axis_crc_sim_1 is + component axis_crc_sim_1_clk_rst_generator_0_0 is + port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + clk : out STD_LOGIC; + rst_n : out STD_LOGIC; + stop_simulation : in STD_LOGIC + ); + end component axis_crc_sim_1_clk_rst_generator_0_0; + component axis_crc_sim_1_axis_slave_simmodel_0_0 is + port ( + FINISHED : out STD_LOGIC; + S_AXIS_ACLK : in STD_LOGIC; + S_AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component axis_crc_sim_1_axis_slave_simmodel_0_0; + component axis_crc_sim_1_axis_master_simmodel_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + FINISHED : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component axis_crc_sim_1_axis_master_simmodel_0_0; + component axis_crc_sim_1_xlconstant_1_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + end component axis_crc_sim_1_xlconstant_1_0; + component axis_crc_sim_1_xlconstant_0_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + end component axis_crc_sim_1_xlconstant_0_0; + component axis_crc_sim_1_axis_crc_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 ); + polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC + ); + end component axis_crc_sim_1_axis_crc_0_0; + signal AXIS_ARESETN_1 : STD_LOGIC; + signal axis_master_simmodel_0_FINISHED : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; + signal clk_rst_generator_0_clk : STD_LOGIC; + signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal crc_M_AXIS_TLAST : STD_LOGIC; + signal crc_M_AXIS_TREADY : STD_LOGIC; + signal crc_M_AXIS_TVALID : STD_LOGIC; + signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC; +begin +axis_crc_0: component axis_crc_sim_1_axis_crc_0_0 + port map ( + CLK => clk_rst_generator_0_clk, + M_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => crc_M_AXIS_TLAST, + M_AXIS_TREADY => crc_M_AXIS_TREADY, + M_AXIS_TVALID => crc_M_AXIS_TVALID, + RESETN => AXIS_ARESETN_1, + S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, + S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID, + initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0), + polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0) + ); +axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0 + port map ( + ACLK => clk_rst_generator_0_clk, + ARESETN => AXIS_ARESETN_1, + FINISHED => axis_master_simmodel_0_FINISHED, + M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, + M_AXIS_TUSER(0) => NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED(0), + M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID + ); +axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0 + port map ( + FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED, + S_AXIS_ACLK => clk_rst_generator_0_clk, + S_AXIS_ARESETN => AXIS_ARESETN_1, + S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => crc_M_AXIS_TLAST, + S_AXIS_TREADY => crc_M_AXIS_TREADY, + S_AXIS_TUSER(0) => '0', + S_AXIS_TVALID => crc_M_AXIS_TVALID + ); +clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0 + port map ( + clk => clk_rst_generator_0_clk, + clk_in => '1', + rst_in => '0', + rst_n => AXIS_ARESETN_1, + stop_simulation => axis_master_simmodel_0_FINISHED + ); +xlconstant_0: component axis_crc_sim_1_xlconstant_0_0 + port map ( + dout(31 downto 0) => xlconstant_0_dout(31 downto 0) + ); +xlconstant_1: component axis_crc_sim_1_xlconstant_1_0 + port map ( + dout(31 downto 0) => xlconstant_1_dout(31 downto 0) + ); +end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd new file mode 100644 index 0000000..32cbc36 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd @@ -0,0 +1,151 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Sun Feb 2 00:16:45 2025 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target axis_crc_sim_1.bd +--Design : axis_crc_sim_1 +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity axis_crc_sim_1 is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef"; +end axis_crc_sim_1; + +architecture STRUCTURE of axis_crc_sim_1 is + component axis_crc_sim_1_clk_rst_generator_0_0 is + port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + clk : out STD_LOGIC; + rst_n : out STD_LOGIC; + stop_simulation : in STD_LOGIC + ); + end component axis_crc_sim_1_clk_rst_generator_0_0; + component axis_crc_sim_1_axis_slave_simmodel_0_0 is + port ( + FINISHED : out STD_LOGIC; + S_AXIS_ACLK : in STD_LOGIC; + S_AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component axis_crc_sim_1_axis_slave_simmodel_0_0; + component axis_crc_sim_1_axis_master_simmodel_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + FINISHED : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component axis_crc_sim_1_axis_master_simmodel_0_0; + component axis_crc_sim_1_xlconstant_1_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + end component axis_crc_sim_1_xlconstant_1_0; + component axis_crc_sim_1_xlconstant_0_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + end component axis_crc_sim_1_xlconstant_0_0; + component axis_crc_sim_1_axis_crc_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 ); + polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC + ); + end component axis_crc_sim_1_axis_crc_0_0; + signal AXIS_ARESETN_1 : STD_LOGIC; + signal axis_master_simmodel_0_FINISHED : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; + signal clk_rst_generator_0_clk : STD_LOGIC; + signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal crc_M_AXIS_TLAST : STD_LOGIC; + signal crc_M_AXIS_TREADY : STD_LOGIC; + signal crc_M_AXIS_TVALID : STD_LOGIC; + signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC; +begin +axis_crc_0: component axis_crc_sim_1_axis_crc_0_0 + port map ( + CLK => clk_rst_generator_0_clk, + M_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => crc_M_AXIS_TLAST, + M_AXIS_TREADY => crc_M_AXIS_TREADY, + M_AXIS_TVALID => crc_M_AXIS_TVALID, + RESETN => AXIS_ARESETN_1, + S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, + S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID, + initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0), + polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0) + ); +axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0 + port map ( + ACLK => clk_rst_generator_0_clk, + ARESETN => AXIS_ARESETN_1, + FINISHED => axis_master_simmodel_0_FINISHED, + M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, + M_AXIS_TUSER(0) => NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED(0), + M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID + ); +axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0 + port map ( + FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED, + S_AXIS_ACLK => clk_rst_generator_0_clk, + S_AXIS_ARESETN => AXIS_ARESETN_1, + S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => crc_M_AXIS_TLAST, + S_AXIS_TREADY => crc_M_AXIS_TREADY, + S_AXIS_TUSER(0) => '0', + S_AXIS_TVALID => crc_M_AXIS_TVALID + ); +clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0 + port map ( + clk => clk_rst_generator_0_clk, + clk_in => '1', + rst_in => '0', + rst_n => AXIS_ARESETN_1, + stop_simulation => axis_master_simmodel_0_FINISHED + ); +xlconstant_0: component axis_crc_sim_1_xlconstant_0_0 + port map ( + dout(31 downto 0) => xlconstant_0_dout(31 downto 0) + ); +xlconstant_1: component axis_crc_sim_1_xlconstant_1_0 + port map ( + dout(31 downto 0) => xlconstant_1_dout(31 downto 0) + ); +end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/axis_master_test.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/axis_master_test.bxml deleted file mode 100644 index c191261..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/axis_master_test.bxml +++ /dev/null @@ -1,11 +0,0 @@ - - - - Composite Fileset - - - - - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/axis_master_test_axis_mixer_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/axis_master_test_axis_mixer_0_0.xml deleted file mode 100644 index 6ee3bda..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/axis_master_test_axis_mixer_0_0.xml +++ /dev/null @@ -1,1911 +0,0 @@ - - - xilinx.com - customized_ip - axis_master_test_axis_mixer_0_0 - 1.0 - - - M_AXIS - - - - - - - TDATA - - - M_AXIS_TDATA - - - - - TVALID - - - M_AXIS_TVALID - - - - - TREADY - - - M_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - axis_master_test_axis_numeric_master_0_0_CLK - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXIS_1 - - - - - - - TDATA - - - S_AXIS_1_TDATA - - - - - TVALID - - - S_AXIS_1_TVALID - - - - - TREADY - - - S_AXIS_1_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - axis_master_test_axis_numeric_master_0_0_CLK - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXIS_2 - - - - - - - TDATA - - - S_AXIS_2_TDATA - - - - - TVALID - - - S_AXIS_2_TVALID - - - - - TREADY - - - S_AXIS_2_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - axis_master_test_axis_numeric_master_0_0_CLK - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - ARESETN - - - - - - - RST - - - ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - ACLK - - - - - - - CLK - - - ACLK - - - - - - ASSOCIATED_RESET - ARESETN - - - ASSOCIATED_BUSIF - S_AXIL:S_AXIS_2:S_AXIS_1:M_AXIS - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - axis_master_test_axis_numeric_master_0_0_CLK - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXIL - - - - - - - - - BVALID - - - S_AXIL_BVALID - - - - - RREADY - - - S_AXIL_RREADY - - - - - BREADY - - - S_AXIL_BREADY - - - - - AWVALID - - - S_AXIL_AWVALID - - - - - AWREADY - - - S_AXIL_AWREADY - - - - - WDATA - - - S_AXIL_WDATA - - - - - RRESP - - - S_AXIL_RRESP - - - - - RVALID - - - S_AXIL_RVALID - - - - - ARADDR - - - S_AXIL_ARADDR - - - - - AWADDR - - - S_AXIL_AWADDR - - - - - ARREADY - - - S_AXIL_ARREADY - - - - - WVALID - - - S_AXIL_WVALID - - - - - WREADY - - - S_AXIL_WREADY - - - - - ARVALID - - - S_AXIL_ARVALID - - - - - WSTRB - - - S_AXIL_WSTRB - - - - - BRESP - - - S_AXIL_BRESP - - - - - RDATA - - - S_AXIL_RDATA - - - - - - NUM_READ_OUTSTANDING - - - - NUM_WRITE_OUTSTANDING - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 32 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 1 - - - none - - - - - HAS_LOCK - 1 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 1 - - - none - - - - - HAS_QOS - 1 - - - none - - - - - HAS_REGION - 1 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 1 - - - none - - - - - MAX_BURST_LENGTH - 256 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - - - S_AXIL - - reg0 - 0 - 65536 - 32 - register - - - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - axis_mixer - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Feb 01 16:34:52 UTC 2025 - - - outputProductCRC - 9:cf998957 - - - - - xilinx_vhdlsimulationwrapper - VHDL Simulation Wrapper - vhdlSource:vivado.xilinx.com:simulation.wrapper - vhdl - axis_master_test_axis_mixer_0_0 - - xilinx_vhdlsimulationwrapper_view_fileset - - - - GENtimestamp - Sat Feb 01 16:34:52 UTC 2025 - - - outputProductCRC - 9:cf998957 - - - - - - - ACLK - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - ARESETN - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - M_AXIS_TVALID - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - M_AXIS_TDATA - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - - - M_AXIS_TREADY - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x1 - - - - - S_AXIS_1_TVALID - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x1 - - - - - S_AXIS_1_TDATA - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - S_AXIS_1_TREADY - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - S_AXIS_2_TVALID - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x1 - - - - - S_AXIS_2_TDATA - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - S_AXIS_2_TREADY - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - S_AXIL_AWADDR - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - S_AXIL_AWVALID - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - S_AXIL_AWREADY - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - S_AXIL_WDATA - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - S_AXIL_WVALID - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - S_AXIL_WREADY - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - S_AXIL_WSTRB - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - S_AXIL_BVALID - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - S_AXIL_BREADY - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - S_AXIL_BRESP - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - S_AXIL_ARADDR - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - S_AXIL_ARVALID - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - S_AXIL_ARREADY - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - S_AXIL_RDATA - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - S_AXIL_RVALID - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - S_AXIL_RREADY - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - S_AXIL_RRESP - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - - - WEIGHT_1 - Weight 1 - 1 - - - DATA_WIDTH - Data Width - 32 - - - HAS_AXI_LITE_IF - Has Axi Lite If - false - - - WEIGHT_2 - Weight 2 - 1 - - - FORCE_01_INPUT - Force 01 Input - false - - - SHIFT_DEF - Shift Def - 0 - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - ../../ipshared/c104/sources_1/new/axis_mixer.vhd - vhdlSource - - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/axis_master_test_axis_mixer_0_0.vhd - vhdlSource - xil_defaultlib - - - - axis_mixer_v1_0 - - - WEIGHT_1 - Weight 1 - 1 - - - DATA_WIDTH - AXI-Stream Data Width - 32 - - - Component_Name - axis_master_test_axis_mixer_0_0 - - - HAS_AXI_LITE_IF - AXI-Lite Interface present - false - - - WEIGHT_2 - Weight 2 - 1 - - - FORCE_01_INPUT - Force AXIS Input Data to 0 or 1 - false - - - SHIFT_DEF - Shift Amount - 0 - - - - - axis_mixer_v1_0 - package_project - 14 - - d:/es-ip/ip/axis_mixer/axis_mixer.srcs - d:/es-ip/ip/axis_mixer/axis_mixer.srcs - d:/es-ip/ip/axis_mixer/axis_mixer.srcs - d:/es-ip/ip/axis_mixer/axis_mixer.srcs - d:/es-ip/ip/axis_mixer/axis_mixer.srcs - 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d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - d:/Projekte/GIP/axis_mixer/axis_mixer.srcs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/sim/axis_master_test_axis_mixer_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/sim/axis_master_test_axis_mixer_0_0.vhd deleted file mode 100644 index caab631..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/sim/axis_master_test_axis_mixer_0_0.vhd +++ /dev/null @@ -1,165 +0,0 @@ --- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of AMD and is protected under U.S. and international copyright --- and other intellectual property laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- AMD, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) AMD shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or AMD had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- AMD products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of AMD products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:user:axis_mixer:1.0 --- IP Revision: 14 - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY axis_master_test_axis_mixer_0_0 IS - PORT ( - ACLK : IN STD_LOGIC; - ARESETN : IN STD_LOGIC; - M_AXIS_TVALID : OUT STD_LOGIC; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M_AXIS_TREADY : IN STD_LOGIC; - S_AXIS_1_TVALID : IN STD_LOGIC; - S_AXIS_1_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_1_TREADY : OUT STD_LOGIC; - S_AXIS_2_TVALID : IN STD_LOGIC; - S_AXIS_2_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_2_TREADY : OUT STD_LOGIC - ); -END axis_master_test_axis_mixer_0_0; - -ARCHITECTURE axis_master_test_axis_mixer_0_0_arch OF axis_master_test_axis_mixer_0_0 IS - ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; - ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_master_test_axis_mixer_0_0_arch: ARCHITECTURE IS "yes"; - COMPONENT axis_mixer IS - GENERIC ( - WEIGHT_1 : INTEGER; - DATA_WIDTH : INTEGER; - HAS_AXI_LITE_IF : BOOLEAN; - WEIGHT_2 : INTEGER; - FORCE_01_INPUT : BOOLEAN; - SHIFT_DEF : INTEGER - ); - PORT ( - ACLK : IN STD_LOGIC; - ARESETN : IN STD_LOGIC; - M_AXIS_TVALID : OUT STD_LOGIC; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M_AXIS_TREADY : IN STD_LOGIC; - S_AXIS_1_TVALID : IN STD_LOGIC; - S_AXIS_1_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_1_TREADY : OUT STD_LOGIC; - S_AXIS_2_TVALID : IN STD_LOGIC; - S_AXIS_2_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_2_TREADY : OUT STD_LOGIC; - S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - S_AXIL_AWVALID : IN STD_LOGIC; - S_AXIL_AWREADY : OUT STD_LOGIC; - S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIL_WVALID : IN STD_LOGIC; - S_AXIL_WREADY : OUT STD_LOGIC; - S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - S_AXIL_BVALID : OUT STD_LOGIC; - S_AXIL_BREADY : IN STD_LOGIC; - S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - S_AXIL_ARVALID : IN STD_LOGIC; - S_AXIL_ARREADY : OUT STD_LOGIC; - S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIL_RVALID : OUT STD_LOGIC; - S_AXIL_RREADY : IN STD_LOGIC; - S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) - ); - END COMPONENT axis_mixer; - ATTRIBUTE X_INTERFACE_INFO : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_RESET ARESETN, ASSOCIATED_BUSIF S_AXIL:S_AXIS_2:S_AXIS_1:M_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK"; - ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST"; - ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_1_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_1 TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_1_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_1 TREADY"; - ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_1_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS_1, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_1_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_1 TVALID"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_2_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_2 TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_2_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_2 TREADY"; - ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_2_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS_2, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_2_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_2 TVALID"; -BEGIN - U0 : axis_mixer - GENERIC MAP ( - WEIGHT_1 => 1, - DATA_WIDTH => 32, - HAS_AXI_LITE_IF => false, - WEIGHT_2 => 1, - FORCE_01_INPUT => false, - SHIFT_DEF => 0 - ) - PORT MAP ( - ACLK => ACLK, - ARESETN => ARESETN, - M_AXIS_TVALID => M_AXIS_TVALID, - M_AXIS_TDATA => M_AXIS_TDATA, - M_AXIS_TREADY => M_AXIS_TREADY, - S_AXIS_1_TVALID => S_AXIS_1_TVALID, - S_AXIS_1_TDATA => S_AXIS_1_TDATA, - S_AXIS_1_TREADY => S_AXIS_1_TREADY, - S_AXIS_2_TVALID => S_AXIS_2_TVALID, - S_AXIS_2_TDATA => S_AXIS_2_TDATA, - S_AXIS_2_TREADY => S_AXIS_2_TREADY, - S_AXIL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)), - S_AXIL_AWVALID => '0', - S_AXIL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), - S_AXIL_WVALID => '0', - S_AXIL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), - S_AXIL_BREADY => '1', - S_AXIL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)), - S_AXIL_ARVALID => '0', - S_AXIL_RREADY => '1' - ); -END axis_master_test_axis_mixer_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0/axis_master_test_axis_numeric_master_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0/axis_master_test_axis_numeric_master_0_0.xml deleted file mode 100644 index 0cd496e..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0/axis_master_test_axis_numeric_master_0_0.xml +++ /dev/null @@ -1,1754 +0,0 @@ - - - xilinx.com - customized_ip - axis_master_test_axis_numeric_master_0_0 - 1.0 - - - M1_AXIS - - - - - - - TDATA - - - M1_AXIS_TDATA - - - - - TLAST - - - M1_AXIS_TLAST - - - - - TUSER - - - M1_AXIS_TUSER - - - - - TVALID - - - M1_AXIS_TVALID - - - - - TREADY - - - M1_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 1 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - M2_AXIS - - - - - - - TDATA - - - M2_AXIS_TDATA - - - - - TLAST - - - M2_AXIS_TLAST - - - - - TUSER - - - M2_AXIS_TUSER - - - - - TVALID - - - M2_AXIS_TVALID - - - - - TREADY - - - M2_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 1 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - S_AXIS - - - - - - - TDATA - - - S_AXIS_TDATA - - - - - TLAST - - - S_AXIS_TLAST - - - - - TUSER - - - S_AXIS_TUSER - - - - - TVALID - - - S_AXIS_TVALID - - - - - TREADY - - - S_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 1 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - ARESETN - - - - - - - RST - - - ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RESETN - - - - - - - RST - - - RESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - ACLK - - - - - - - CLK - - - ACLK - - - - - - ASSOCIATED_BUSIF - M1_AXIS:M2_AXIS:S_AXIS - - - ASSOCIATED_RESET - RESETN - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - CLK - - - - - - - CLK - - - CLK - - - - - - ASSOCIATED_RESET - RESETN - - - ASSOCIATED_BUSIF - S_AXIS:M2_AXIS:M1_AXIS - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - axis_master_test_axis_numeric_master_0_0_CLK - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - - - - CLK - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - RESETN - - out - - - std_logic - dummy_view - - - - 0x1 - - - - - ACLK - - in - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - ARESETN - - in - - - std_logic - dummy_view - - - - 0x1 - - - - - - false - - - - - - M1_AXIS_TVALID - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - M1_AXIS_TDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - M1_AXIS_TREADY - - in - - - std_logic - dummy_view - - - - 0x1 - - - - - M1_AXIS_TLAST - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - M1_AXIS_TUSER - - out - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - M2_AXIS_TVALID - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - M2_AXIS_TDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - M2_AXIS_TREADY - - in - - - std_logic - dummy_view - - - - 0x1 - - - - - M2_AXIS_TLAST - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - M2_AXIS_TUSER - - out - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - S_AXIS_TVALID - - in - - - std_logic - dummy_view - - - - 0x0 - - - - - S_AXIS_TDATA - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - S_AXIS_TREADY - - out - - - std_logic - dummy_view - - - - - - S_AXIS_TLAST - - in - - - std_logic - dummy_view - - - - 0x0 - - - - - S_AXIS_TUSER - - in - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - - HAS_CLOCK_GENERATOR - Has Clock Generator - true - - - CLOCK_PERIOD_NS - Clock Period Ns - 10 - - - HAS_RESET_GENERATOR - Has Reset Generator - true - - - RESET_ACTIVE_CYCLES - Reset Active Cycles - 100 - - - HAS_MASTER1 - Has Master1 - true - - - MASTER1_DATA_WIDTH - Master1 Data Width - 32 - - - MASTER1_RANDOM_VALID - Master1 Random Valid - true - - - MASTER1_HAS_LAST - Master1 Has Last - false - - - MASTER1_LAST_PERIOD - Master1 Last Period - 100 - - - MASTER1_HAS_USER - Master1 Has User - false - - - MASTER1_USER_PERIOD - Master1 User Period - 1000 - - - HAS_MASTER2 - Has Master2 - true - - - MASTER2_DATA_WIDTH - Master2 Data Width - 32 - - - MASTER2_RANDOM_VALID - Master2 Random Valid - true - - - MASTER2_HAS_LAST - Master2 Has Last - false - - - MASTER2_LAST_PERIOD - Master2 Last Period - 100 - - - MASTER2_HAS_USER - Master2 Has User - false - - - MASTER2_USER_PERIOD - Master2 User Period - 1000 - - - HAS_SLAVE - Has Slave - true - - - SLAVE_DATA_WIDTH - Slave Data Width - 32 - - - SLAVE_RANDOM_READY - Slave Random Ready - true - - - SLAVE_HAS_LAST - Slave Has Last - false - - - SLAVE_HAS_USER - Slave Has User - false - - - SLAVE_WAIT_FOR_SOF - Slave Wait For Sof - false - - - FILE_NAME_M1 - File Name M1 - ../../../../mstr1.txt - - - FILE_NAME_M2 - File Name M2 - ../../../../mstr2.txt - - - FILE_NAME_S - File Name S - ../../../../slv.txt - - - HAS_RESETN_INPUT - Has Resetn Input - false - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - axis_numeric_master_slave_simmodel_v1_0 - - - HAS_CLOCK_GENERATOR - Clock Generator - true - - - CLOCK_PERIOD_NS - Clock Period (ns) - 10 - - - HAS_RESET_GENERATOR - Reset Generator - true - - - RESET_ACTIVE_CYCLES - Reset Active Cycles at Startup - 100 - - - HAS_MASTER1 - AXIS Master 1 - true - - - MASTER1_DATA_WIDTH - Data Width - 32 - - - MASTER1_RANDOM_VALID - Random Valid - true - - - MASTER1_HAS_LAST - TLAST present - false - - - MASTER1_LAST_PERIOD - TLAST Period - 100 - - - MASTER1_HAS_USER - TUSER present - false - - - MASTER1_USER_PERIOD - TUSER Period - 1000 - - - HAS_MASTER2 - AXIS Master 2 - true - - - MASTER2_DATA_WIDTH - Data Width - 32 - - - MASTER2_RANDOM_VALID - Random Valid - true - - - MASTER2_HAS_LAST - TLAST present - false - - - MASTER2_LAST_PERIOD - TLAST Period - 100 - - - MASTER2_HAS_USER - TUSER present - false - - - MASTER2_USER_PERIOD - TUSER Period - 1000 - - - HAS_SLAVE - AXIS Slave - true - - - SLAVE_DATA_WIDTH - Data Width - 32 - - - SLAVE_RANDOM_READY - Random Ready - true - - - SLAVE_HAS_LAST - TLAST present - false - - - SLAVE_HAS_USER - TUSER present - false - - - SLAVE_WAIT_FOR_SOF - Wait For SOF - false - - - FILE_NAME_M1 - Stimuli File - ../../../../mstr1.txt - - - FILE_NAME_M2 - Stimuli File - ../../../../mstr2.txt - - - FILE_NAME_S - Verification Data File - ../../../../slv.txt - - - Component_Name - axis_master_test_axis_numeric_master_0_0 - - - HAS_RESETN_INPUT - ARESETN Input present - false - - - - - axis_numeric_master_slave_simmodel_v1_0 - package_project - 18 - - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - 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d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0/sim/axis_master_test_axis_numeric_master_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0/sim/axis_master_test_axis_numeric_master_0_0.vhd deleted file mode 100644 index 2721453..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0/sim/axis_master_test_axis_numeric_master_0_0.vhd +++ /dev/null @@ -1,211 +0,0 @@ --- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of AMD and is protected under U.S. and international copyright --- and other intellectual property laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- AMD, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) AMD shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or AMD had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- AMD products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of AMD products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:user:axis_numeric_master_slave_simmodel:1.0 --- IP Revision: 18 - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY axis_master_test_axis_numeric_master_0_0 IS - PORT ( - CLK : OUT STD_LOGIC; - RESETN : OUT STD_LOGIC; - M1_AXIS_TVALID : OUT STD_LOGIC; - M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M1_AXIS_TREADY : IN STD_LOGIC; - M1_AXIS_TLAST : OUT STD_LOGIC; - M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - M2_AXIS_TVALID : OUT STD_LOGIC; - M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M2_AXIS_TREADY : IN STD_LOGIC; - M2_AXIS_TLAST : OUT STD_LOGIC; - M2_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - S_AXIS_TVALID : IN STD_LOGIC; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_TREADY : OUT STD_LOGIC; - S_AXIS_TLAST : IN STD_LOGIC; - S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) - ); -END axis_master_test_axis_numeric_master_0_0; - -ARCHITECTURE axis_master_test_axis_numeric_master_0_0_arch OF axis_master_test_axis_numeric_master_0_0 IS - ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; - ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_master_test_axis_numeric_master_0_0_arch: ARCHITECTURE IS "yes"; - COMPONENT axis_numeric_master_slave_simmodel IS - GENERIC ( - HAS_CLOCK_GENERATOR : BOOLEAN; - CLOCK_PERIOD_NS : INTEGER; - HAS_RESET_GENERATOR : BOOLEAN; - RESET_ACTIVE_CYCLES : INTEGER; - HAS_MASTER1 : BOOLEAN; - MASTER1_DATA_WIDTH : INTEGER; - MASTER1_RANDOM_VALID : BOOLEAN; - MASTER1_HAS_LAST : BOOLEAN; - MASTER1_LAST_PERIOD : INTEGER; - MASTER1_HAS_USER : BOOLEAN; - MASTER1_USER_PERIOD : INTEGER; - HAS_MASTER2 : BOOLEAN; - MASTER2_DATA_WIDTH : INTEGER; - MASTER2_RANDOM_VALID : BOOLEAN; - MASTER2_HAS_LAST : BOOLEAN; - MASTER2_LAST_PERIOD : INTEGER; - MASTER2_HAS_USER : BOOLEAN; - MASTER2_USER_PERIOD : INTEGER; - HAS_SLAVE : BOOLEAN; - SLAVE_DATA_WIDTH : INTEGER; - SLAVE_RANDOM_READY : BOOLEAN; - SLAVE_HAS_LAST : BOOLEAN; - SLAVE_HAS_USER : BOOLEAN; - SLAVE_WAIT_FOR_SOF : BOOLEAN; - FILE_NAME_M1 : STRING; - FILE_NAME_M2 : STRING; - FILE_NAME_S : STRING; - HAS_RESETN_INPUT : BOOLEAN - ); - PORT ( - CLK : OUT STD_LOGIC; - RESETN : OUT STD_LOGIC; - ACLK : IN STD_LOGIC; - ARESETN : IN STD_LOGIC; - M1_AXIS_TVALID : OUT STD_LOGIC; - M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M1_AXIS_TREADY : IN STD_LOGIC; - M1_AXIS_TLAST : OUT STD_LOGIC; - M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - M2_AXIS_TVALID : OUT STD_LOGIC; - M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M2_AXIS_TREADY : IN STD_LOGIC; - M2_AXIS_TLAST : OUT STD_LOGIC; - M2_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - S_AXIS_TVALID : IN STD_LOGIC; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_TREADY : OUT STD_LOGIC; - S_AXIS_TLAST : IN STD_LOGIC; - S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) - ); - END COMPONENT axis_numeric_master_slave_simmodel; - ATTRIBUTE X_INTERFACE_INFO : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_RESET RESETN, ASSOCIATED_BUSIF S_AXIS:M2_AXIS:M1_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TLAST"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TUSER"; - ATTRIBUTE X_INTERFACE_PARAMETER OF M1_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M1_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TVALID"; - ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TLAST"; - ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TUSER"; - ATTRIBUTE X_INTERFACE_PARAMETER OF M2_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M2_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TVALID"; - ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; - ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; -BEGIN - U0 : axis_numeric_master_slave_simmodel - GENERIC MAP ( - HAS_CLOCK_GENERATOR => true, - CLOCK_PERIOD_NS => 10, - HAS_RESET_GENERATOR => true, - RESET_ACTIVE_CYCLES => 100, - HAS_MASTER1 => true, - MASTER1_DATA_WIDTH => 32, - MASTER1_RANDOM_VALID => true, - MASTER1_HAS_LAST => false, - MASTER1_LAST_PERIOD => 100, - MASTER1_HAS_USER => false, - MASTER1_USER_PERIOD => 1000, - HAS_MASTER2 => true, - MASTER2_DATA_WIDTH => 32, - MASTER2_RANDOM_VALID => true, - MASTER2_HAS_LAST => false, - MASTER2_LAST_PERIOD => 100, - MASTER2_HAS_USER => false, - MASTER2_USER_PERIOD => 1000, - HAS_SLAVE => true, - SLAVE_DATA_WIDTH => 32, - SLAVE_RANDOM_READY => true, - SLAVE_HAS_LAST => false, - SLAVE_HAS_USER => false, - SLAVE_WAIT_FOR_SOF => false, - FILE_NAME_M1 => "../../../../mstr1.txt", - FILE_NAME_M2 => "../../../../mstr2.txt", - FILE_NAME_S => "../../../../slv.txt", - HAS_RESETN_INPUT => false - ) - PORT MAP ( - CLK => CLK, - RESETN => RESETN, - ACLK => '0', - ARESETN => '1', - M1_AXIS_TVALID => M1_AXIS_TVALID, - M1_AXIS_TDATA => M1_AXIS_TDATA, - M1_AXIS_TREADY => M1_AXIS_TREADY, - M1_AXIS_TLAST => M1_AXIS_TLAST, - M1_AXIS_TUSER => M1_AXIS_TUSER, - M2_AXIS_TVALID => M2_AXIS_TVALID, - M2_AXIS_TDATA => M2_AXIS_TDATA, - M2_AXIS_TREADY => M2_AXIS_TREADY, - M2_AXIS_TLAST => M2_AXIS_TLAST, - M2_AXIS_TUSER => M2_AXIS_TUSER, - S_AXIS_TVALID => S_AXIS_TVALID, - S_AXIS_TDATA => S_AXIS_TDATA, - S_AXIS_TREADY => S_AXIS_TREADY, - S_AXIS_TLAST => S_AXIS_TLAST, - S_AXIS_TUSER => S_AXIS_TUSER - ); -END axis_master_test_axis_numeric_master_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c104/sources_1/new/axis_mixer.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c104/sources_1/new/axis_mixer.vhd deleted file mode 100644 index cff4e95..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c104/sources_1/new/axis_mixer.vhd +++ /dev/null @@ -1,240 +0,0 @@ ------------------------------------------------------------------------------- --- axis_mixer.vhd - entity/architecture pair ------------------------------------------------------------------------------- ----------------------------------------------------------- --- Prof. Dr.-Ing. W. Gehrke (c) 2020, update 2022 ----------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axis_mixer is - generic - ( - HAS_AXI_LITE_IF : boolean := false; - FORCE_01_INPUT : boolean := false; - WEIGHT_1 : positive := 1; - WEIGHT_2 : positive := 1; - SHIFT_DEF : integer := 0; - DATA_WIDTH : integer := 16 - ); - - port - ( - ACLK : in std_logic; - ARESETN : in std_logic; - - -- AXIS Master - M_AXIS_TVALID : out std_logic; - M_AXIS_TDATA : out std_logic_vector(DATA_WIDTH-1 downto 0); - M_AXIS_TREADY : in std_logic := '1'; - - -- AXIS Slave 1 - S_AXIS_1_TVALID : in std_logic := '1'; - S_AXIS_1_TDATA : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0'); - S_AXIS_1_TREADY : out std_logic; - - -- AXIS Slave 2 - S_AXIS_2_TVALID : in std_logic := '1'; - S_AXIS_2_TDATA : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0'); - S_AXIS_2_TREADY : out std_logic; - - -- AXIL Interface - S_AXIL_AWADDR : in std_logic_vector(15 downto 0) := (others=>'0'); - S_AXIL_AWVALID : in std_logic := '0'; - S_AXIL_AWREADY : out std_logic; - S_AXIL_WDATA : in std_logic_vector(31 downto 0) := (others=>'0'); - S_AXIL_WVALID : in std_logic := '0'; - S_AXIL_WREADY : out std_logic; - S_AXIL_WSTRB : in std_logic_vector( 3 downto 0) := (others=>'0'); - S_AXIL_BVALID : out std_logic; - S_AXIL_BREADY : in std_logic := '1'; - S_AXIL_BRESP : out std_logic_vector( 1 downto 0); - S_AXIL_ARADDR : in std_logic_vector(15 downto 0) := (others=>'0'); - S_AXIL_ARVALID : in std_logic := '0'; - S_AXIL_ARREADY : out std_logic; - S_AXIL_RDATA : out std_logic_vector(31 downto 0); - S_AXIL_RVALID : out std_logic; - S_AXIL_RREADY : in std_logic := '1'; - S_AXIL_RRESP : out std_logic_vector( 1 downto 0) - - ); - -end entity; - - ------------------------------------------------------------------------------- --- Architecture section ------------------------------------------------------------------------------- - -architecture rtl of axis_mixer is - - signal weight1 : signed(8 downto 0) := to_signed(WEIGHT_1,9); - signal weight2 : signed(8 downto 0) := to_signed(WEIGHT_2,9); - signal shift : unsigned(3 downto 0) := to_unsigned(SHIFT_DEF,4); - -begin - - process - variable datain1 : signed(DATA_WIDTH-1 downto 0); - variable datain2 : signed(DATA_WIDTH-1 downto 0); - variable tmp2 : signed(DATA_WIDTH-1+9 downto 0); - variable tmp1 : signed(DATA_WIDTH-1+9 downto 0); - variable res : signed(DATA_WIDTH-1+10 downto 0); - variable shift_i : integer; - variable tmp1_valid : boolean := false; - variable tmp2_valid : boolean := false; - variable out_valid : boolean := false; - - begin - wait until rising_edge(ACLK); - - if ARESETN = '0' then - - M_AXIS_TVALID <= '0'; - S_AXIS_1_TREADY <= '0'; - S_AXIS_2_TREADY <= '0'; - tmp1 := to_signed(0,DATA_WIDTH+9); - tmp2 := to_signed(0,DATA_WIDTH+9); - tmp1_valid := false; - tmp2_valid := false; - out_valid := false; - - else - -- nur für Simulation: Falls U,X etc am Eingang, 0 weitergeben - -- synthesis translate_off - if FORCE_01_INPUT then - for i in DATA_WIDTH-1 downto 0 loop - if S_AXIS_1_TDATA(i) = '1' then - datain1(i) := '1'; - else - datain1(i) := '0'; - end if; - if S_AXIS_2_TDATA(i) = '1' then - datain2(i) := '1'; - else - datain2(i) := '0'; - end if; - end loop; - end if; - -- synthesis translate_on - - -- Datenpuffer tmp1 frei? Dann: ready = 1 und ggf. Daten übernehmen - if not tmp1_valid then - S_AXIS_1_TREADY <= '1'; - if S_AXIS_1_TVALID = '1' then - tmp1 := signed(S_AXIS_1_TDATA)*weight1; - tmp1_valid := true; - -- Datenpuffer gefüllt, weitere Daten können nicht übernommen werden - -- Falls die Daten konsumiert werden, wird ready unten wieder auf 1 gesetzt - S_AXIS_1_TREADY <= '0'; - end if; - end if; - - -- Datenpuffer tmp2 frei? Dann: ready = 1 und ggf. Daten übernehmen - if not tmp2_valid then - S_AXIS_2_TREADY <= '1'; - if S_AXIS_2_TVALID = '1' then - tmp2 := signed(S_AXIS_2_TDATA)*weight2; - tmp2_valid := true; - -- Datenpuffer gefüllt, weitere Daten können nicht übernommen werden - -- Falls die Daten konsumiert werden, wird ready unten wieder auf 1 gesetzt - S_AXIS_2_TREADY <= '0'; - end if; - end if; - - -- Ausgangsdaten übernommen? Dann: keine neuen Daten verfügbar (valid=0) - -- Falls in diesem Taktzyklus neue Ausgangsdaten produziert werden, - -- wird valid unten wieder auf 1 gesetzt - if M_AXIS_TREADY = '1' then - M_AXIS_TVALID <= '0'; - out_valid := false; - end if; - - -- Datenpuffer tmp1 UND tmp2 haben gültige Daten UND Ausgangspuffer ist frei? - -- Dann: neue Ausgangsdaten produzieren - if tmp1_valid and tmp2_valid and (not out_valid) then - - -- Daten aus Eingangspuffer sind konsumiert - -- Daher: Pufferinhalt als ungültig markieren UND Epmfangsbereitschaft signalisieren - tmp1_valid := false; - tmp2_valid := false; - S_AXIS_1_TREADY <= '1'; - S_AXIS_2_TREADY <= '1'; - - -- Neue Ausgangsdaten bereitstellen und als gültig markieren - res := (tmp1(DATA_WIDTH-1+9)&tmp1)+(tmp2(DATA_WIDTH-1+9)&tmp2); - shift_i := to_integer(shift); - if shift_i > 10 then shift_i := 10; end if; - M_AXIS_TDATA <= std_logic_vector(res(DATA_WIDTH-1+shift_i downto shift_i)); - M_AXIS_TVALID <= '1'; - out_valid := true; - end if; - end if; - - end process; --------------------------------------------------------------------------------------------------- --- AXIL --------------------------------------------------------------------------------------------------- - - S_AXIL_BRESP <= (others=>'0'); -- No write errors - S_AXIL_RRESP <= (others=>'0'); -- No read errors - S_AXIL_ARREADY <= '1'; -- IP is always ready - S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID; - S_AXIL_WREADY <= S_AXIL_AWVALID and S_AXIL_WVALID; - -axilgen: if HAS_AXI_LITE_IF generate -process begin - wait until rising_edge (ACLK); - - if ARESETN = '0' then - S_AXIL_BVALID <= '0'; - S_AXIL_RVALID <= '0'; - weight1 <= to_signed(WEIGHT_1,9); - weight2 <= to_signed(WEIGHT_2,9); - shift <= to_unsigned(8,4); - else - if S_AXIL_RREADY = '1' then - S_AXIL_RVALID <= '0'; - end if; - - if S_AXIL_ARVALID = '1' then - S_AXIL_RDATA <= (others=>'0'); - case S_AXIL_ARADDR(3 downto 2) is - when "00" => S_AXIL_RDATA(7 downto 0) <= std_logic_vector(weight1(7 downto 0)); - when "01" => S_AXIL_RDATA(7 downto 0) <= std_logic_vector(weight2(7 downto 0)); - when "10" => S_AXIL_RDATA(3 downto 0) <= std_logic_vector(shift); - when others => null; - end case; - S_AXIL_RVALID <= '1'; - end if; - - if S_AXIL_BREADY = '1' then - S_AXIL_BVALID <= '0'; - end if; - - if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then - S_AXIL_BVALID <= '1'; - case S_AXIL_ARADDR(3 downto 2) is - when "00" => - if S_AXIL_WSTRB(0) = '1' then - weight1(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); - end if; - when "01" => - if S_AXIL_WSTRB(0) = '1' then - weight2(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); - end if; - when "11" => - if S_AXIL_WSTRB(0) = '1' then - shift(3 downto 0) <= unsigned(S_AXIL_WDATA(3 downto 0)); - end if; - when others => null; - end case; - end if; - end if; -end process; -end generate; - -end; - \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c6f6/axis_numeric_master_slave_simmodel.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c6f6/axis_numeric_master_slave_simmodel.vhd deleted file mode 100644 index e40cd22..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c6f6/axis_numeric_master_slave_simmodel.vhd +++ /dev/null @@ -1,362 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.vhdl_c_pkg_tb.all; - -entity axis_numeric_master_slave_simmodel is - generic - ( - HAS_CLOCK_GENERATOR : boolean := true; - CLOCK_PERIOD_NS : integer := 10; - - HAS_RESET_GENERATOR : boolean := true; - HAS_RESETN_INPUT : boolean := false; - RESET_ACTIVE_CYCLES : integer := 100; - - HAS_MASTER1 : boolean := true; - FILE_NAME_M1 : string := string'("../../../../m1.txt"); - MASTER1_DATA_WIDTH : integer := 32; - MASTER1_RANDOM_VALID : boolean := true; - MASTER1_HAS_LAST : boolean := true; - MASTER1_LAST_PERIOD : integer := 100; - MASTER1_HAS_USER : boolean := true; - MASTER1_USER_PERIOD : integer := 1000; - - HAS_MASTER2 : boolean := true; - FILE_NAME_M2 : string := string'("../../../../m1.txt"); - MASTER2_DATA_WIDTH : integer := 32; - MASTER2_RANDOM_VALID : boolean := true; - MASTER2_HAS_LAST : boolean := true; - MASTER2_LAST_PERIOD : integer := 100; - MASTER2_HAS_USER : boolean := true; - MASTER2_USER_PERIOD : integer := 1000; - - HAS_SLAVE : boolean := true; - FILE_NAME_S : string := string'("../../../../m1.txt"); - SLAVE_DATA_WIDTH : integer := 32; - SLAVE_RANDOM_READY : boolean := true; - SLAVE_HAS_LAST : boolean := true; - SLAVE_HAS_USER : boolean := true; - SLAVE_WAIT_FOR_SOF : boolean := true - ); - - port - ( - CLK : out std_logic := '0'; - RESETN : out std_logic := '1'; - - ACLK : in std_logic := '0'; - ARESETN : in std_logic := '1'; - - M1_AXIS_TVALID : out std_logic := '0'; - M1_AXIS_TDATA : out std_logic_vector(MASTER1_DATA_WIDTH-1 downto 0):= (others=>'0'); - M1_AXIS_TREADY : in std_logic := '1'; - M1_AXIS_TLAST : out std_logic := '0'; - M1_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0'); - - M2_AXIS_TVALID : out std_logic := '0'; - M2_AXIS_TDATA : out std_logic_vector(MASTER2_DATA_WIDTH-1 downto 0) := (others=>'0'); - M2_AXIS_TREADY : in std_logic := '1'; - M2_AXIS_TLAST : out std_logic := '0'; - M2_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0'); - - S_AXIS_TVALID : in std_logic := '0'; - S_AXIS_TDATA : in std_logic_vector(SLAVE_DATA_WIDTH-1 downto 0); - S_AXIS_TREADY : out std_logic; - S_AXIS_TLAST : in std_logic := '0'; - S_AXIS_TUSER : in std_logic_vector(0 downto 0):= (others=>'0') - ); - -end; - - - -architecture sim of axis_numeric_master_slave_simmodel is - - signal rnd_m1 : unsigned (31 downto 0) := x"ABBAABBA"; - signal rnd_m2 : unsigned (31 downto 0) := x"DEADBEEF"; - signal rnd_s : unsigned (31 downto 0) := x"12345678"; - signal lclk : std_logic := '0'; - signal local_clk : std_logic := ACLK; - signal local_resetn : std_logic := '1'; - - signal DBG_M1_FILERELOAD : std_logic := '0'; - signal DBG_M2_FILERELOAD : std_logic := '0'; - signal DBG_S_FILERELOAD : std_logic := '0'; - -begin - --- synthesis translate_off --- translate off - ---------------------------------------- - -- Clock Generator - ---------------------------------------- - genclk: if HAS_CLOCK_GENERATOR generate - lclk <= not lclk after CLOCK_PERIOD_NS * 0.5 ns; - CLK <= lclk; - local_clk <= lclk; - end generate; - - no_genclk: if not HAS_CLOCK_GENERATOR generate - local_clk <= ACLK; - end generate; - - ---------------------------------------- - -- Reset Generator - ---------------------------------------- - genreset: if HAS_RESET_GENERATOR generate - process begin - RESETN <= '0'; - local_resetn <= '0'; - for i in 1 to RESET_ACTIVE_CYCLES loop - wait until rising_edge(local_clk); - end loop; - RESETN <= '1'; - local_resetn <= '1'; - wait; - end process; - end generate; - - no_genreset: if HAS_RESETN_INPUT and (not HAS_RESET_GENERATOR) generate - local_resetn <= ARESETN; - end generate; - - - ---------------------------------------- - -- Random Number Generator - ---------------------------------------- - -- uint32_t xorshift32() { - -- static uint32_t x = 314159265; - -- x ^= x << 13; - -- x ^= x >> 17; - -- x ^= x << 5; - -- return x; - -- } - rnd: process - variable r : unsigned (31 downto 0); - begin - wait until rising_edge(local_clk); - r := rnd_m1; - r := r xor (r(18 downto 0)& x"000"&"0"); - r := r xor (x"0000"&"0"&r(31 downto 17)); - r := r xor (r(26 downto 0)& "00000"); - rnd_m1 <= r; - r := rnd_m2; - r := r xor (r(18 downto 0)& x"000"&"0"); - r := r xor (x"0000"&"0"&r(31 downto 17)); - r := r xor (r(26 downto 0)& "00000"); - rnd_m2 <= r; - r := rnd_s; - r := r xor (r(18 downto 0)& x"000"&"0"); - r := r xor (x"0000"&"0"&r(31 downto 17)); - r := r xor (r(26 downto 0)& "00000"); - rnd_s <= r; - end process; - - ---------------------------------------- - -- Master 1 - ---------------------------------------- - genmaster1: if HAS_MASTER1 generate - m1: process - variable fp : CFILE := 0; - variable data : std_logic_vector(31 downto 0); - variable rnd : integer; - variable data_cnt_last : integer := 1; - variable data_cnt_user : integer := 1; - variable valid_out : std_logic := '0'; - - begin - wait until rising_edge (local_clk); - DBG_M1_FILERELOAD <= '0'; - if (local_resetn = '0') then - valid_out := '0'; - M1_AXIS_TVALID <= '0'; - M1_AXIS_TDATA <= (others=>'0'); - if fp > 0 then - fclose(fp); - end if; - else - if fp > 0 then - fclose(fp); - fp := 0; - end if; - fp := fopen(FILE_NAME_M1, "r"); - if fp = 0 then - printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master1 (%s).\n",FILE_NAME_M1); - wait; - end if; - - while not feof(fp) loop - valid_out := '1'; - fscanf(fp, string'("%x"), data); - M1_AXIS_TVALID <= '1'; - M1_AXIS_TDATA <= data(MASTER1_DATA_WIDTH-1 downto 0); - M1_AXIS_TLAST <= '0'; - M1_AXIS_TUSER(0) <= '0'; - if data_cnt_last >= MASTER1_LAST_PERIOD then - M1_AXIS_TLAST <= '1'; - data_cnt_last := 0; - end if; - if data_cnt_user >= MASTER1_USER_PERIOD then - M1_AXIS_TUSER(0) <= '1'; - data_cnt_user := 0; - end if; - data_cnt_last := data_cnt_last + 1; - data_cnt_user := data_cnt_user + 1; - - wait until rising_edge (local_clk); - while M1_AXIS_TREADY /= '1' loop - wait until rising_edge (local_clk); - end loop; - - rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length)); - if (rnd>0 and MASTER1_RANDOM_VALID) then - M1_AXIS_TVALID <= '0'; - for i in 0 to rnd loop - wait until rising_edge (local_clk); - end loop; - end if; - end loop; - M1_AXIS_TVALID <= '0'; - DBG_M1_FILERELOAD <= '1'; - end if; - end process; - end generate; - - ---------------------------------------- - -- Master 2 - ---------------------------------------- - genmaster2: if HAS_MASTER2 generate - m2: process - variable fp : CFILE := 0; - variable data : std_logic_vector(31 downto 0); - variable rnd : integer; - variable data_cnt_last : integer := 1; - variable data_cnt_user : integer := 1; - variable valid_out : std_logic := '0'; - - begin - - wait until rising_edge (local_clk); - DBG_M1_FILERELOAD <= '0'; - if (local_resetn = '0') then - valid_out := '0'; - M2_AXIS_TVALID <= '0'; - M2_AXIS_TDATA <= (others=>'0'); - if fp > 0 then - fclose(fp); - end if; - else - if fp > 0 then - fclose(fp); - fp := 0; - end if; - fp := fopen(FILE_NAME_M2, "r"); - if fp = 0 then - printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master2 (%s).\n",FILE_NAME_M2); - wait; - end if; - - while not feof(fp) loop - valid_out := '1'; - fscanf(fp, string'("%x"), data); - M2_AXIS_TVALID <= '1'; - M2_AXIS_TDATA <= data(MASTER2_DATA_WIDTH-1 downto 0); - M2_AXIS_TLAST <= '0'; - M2_AXIS_TUSER(0) <= '0'; - if data_cnt_last >= MASTER2_LAST_PERIOD then - M2_AXIS_TLAST <= '1'; - data_cnt_last := 0; - end if; - if data_cnt_user >= MASTER1_USER_PERIOD then - M2_AXIS_TUSER(0) <= '1'; - data_cnt_user := 0; - end if; - data_cnt_last := data_cnt_last + 1; - data_cnt_user := data_cnt_user + 1; - - wait until rising_edge (local_clk); - while M2_AXIS_TREADY /= '1' loop - wait until rising_edge (local_clk); - end loop; - - rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length)); - if (rnd>0 and MASTER2_RANDOM_VALID) then - M2_AXIS_TVALID <= '0'; - for i in 0 to rnd loop - wait until rising_edge (local_clk); - end loop; - end if; - end loop; - M2_AXIS_TVALID <= '0'; - DBG_M2_FILERELOAD <= '1'; - end if; - end process; - end generate; - - ---------------------------------------- - -- SLAVE - ---------------------------------------- - genslave: if HAS_SLAVE generate - s: process - variable fp : CFILE := 0; - variable data : std_logic_vector(31 downto 0) := (others=>'0'); - variable rnd : integer; - variable wait_sof : boolean := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER; - begin - - wait until rising_edge (local_clk); - DBG_S_FILERELOAD <= '0'; - if (local_resetn = '0') then - S_AXIS_TREADY <= '0'; - if fp > 0 then - fclose(fp); - end if; - wait_sof := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER; - elsif wait_sof then - if S_AXIS_TVALID = '1' and S_AXIS_TUSER(0) = '1' then - wait_sof := false; - end if; - else - if fp > 0 then - fclose(fp); - fp := 0; - end if; - fp := fopen(FILE_NAME_S, "r"); - if fp = 0 then - printf("*** Simulation Info *** => Cannot open stimuli file for AXIS-Slave (%s).\n",FILE_NAME_S); - end if; - - while not feof(fp) and fp /= 0 loop - S_AXIS_TREADY <= '1'; - wait until rising_edge (local_clk); - while S_AXIS_TVALID /= '1' loop - wait until rising_edge (local_clk); - end loop; - - if fp > 0 then - fscanf(fp, string'("%x"), data); - if data(SLAVE_DATA_WIDTH-1 downto 0) /= S_AXIS_TDATA then - printf("*** Verification Error *** => expected %x - received %x\n",data(SLAVE_DATA_WIDTH-1 downto 0),S_AXIS_TDATA); - end if; - end if; - - rnd := to_integer(rnd_s and to_unsigned(3,rnd_s'length)); - if (rnd>0 and SLAVE_RANDOM_READY) then - S_AXIS_TREADY <= '0'; - for i in 0 to rnd loop - wait until rising_edge (local_clk); - end loop; - end if; - end loop; - S_AXIS_TREADY <= '0'; - DBG_S_FILERELOAD <= '1'; - end if; - end process; - end generate; - --- synthesis translate_on --- translate on - -end; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c6f6/vhdl_c_pkg_tb.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c6f6/vhdl_c_pkg_tb.vhd deleted file mode 100644 index a277d78..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c6f6/vhdl_c_pkg_tb.vhd +++ /dev/null @@ -1,2604 +0,0 @@ --- Files: stdlib_h.vhd et.al. --- Version: 3.0 (June 6, 2004) --- Source: http://bear.ces.cwru.edu/vhdl --- Date: June 6, 2004 (Copyright) --- Author: Francis G. Wolff Email: fxw12@po.cwru.edu --- Author: Michael J. Knieser Email: mjknieser@knieser.com --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 1, or (at your option) --- any later version: http://www.gnu.org/licenses/gpl.html --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. --- -library STD; -use STD.textio.all; -library IEEE; -use IEEE.std_logic_1164.all; - -PACKAGE vhdl_c_pkg_tb IS --------------------------------------------------------------------------------------------- --- Package: endian_h --------------------------------------------------------------------------------------------- --- PACKAGE endian_h IS - --to_bigendian(x=any endian) return only big endian (HIGH DOWNTO LOW); - --to_littleendian(x=any endian) return only little endian (LOW TO HIGH); - - FUNCTION to_bigendian_bit_vector( x: IN BIT_VECTOR) RETURN BIT_VECTOR; - FUNCTION to_littleendian_bit_vector(x: IN BIT_VECTOR) RETURN BIT_VECTOR; - FUNCTION to_bigendian_bit_vector( x: IN INTEGER; n: IN INTEGER:=32) RETURN BIT_VECTOR; --n bits - FUNCTION to_littleendian_bit_vector( x: IN INTEGER; n: IN INTEGER:=32) RETURN BIT_VECTOR; --n bits - - FUNCTION to_bigendian_std_logic_vector( x: IN BIT_VECTOR) RETURN STD_LOGIC_VECTOR; - FUNCTION to_littleendian_std_logic_vector(x: IN BIT_VECTOR) RETURN STD_LOGIC_VECTOR; - FUNCTION to_bigendian_std_logic_vector( x: IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; - FUNCTION to_littleendian_std_logic_vector(x: IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; - FUNCTION to_bigendian_std_logic_vector( x: IN INTEGER; n: IN INTEGER:=32) RETURN std_logic_vector; - FUNCTION to_littleendian_std_logic_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN std_logic_vector; - - --This must be a seperate case because VHDL cannot distinguish between typeless STRING and BIT_VECTOR string - FUNCTION to_bigendian_bit_vector_string(x: IN STRING) RETURN BIT_VECTOR; --"0101",o"05",x"5" - FUNCTION to_littleendian_bit_vector_string(x: IN STRING) RETURN BIT_VECTOR; --"0101",o"05",x"5" - FUNCTION to_bigendian_std_logic_vector_string(x: IN STRING) RETURN std_logic_vector; - FUNCTION to_littleendian_std_logic_vector_string(x: IN STRING) RETURN std_logic_vector; - ---------------------------------------------------------------------------------------------------------- --- END endian_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package ctype_h is ---------------------------------------------------------------------------------------------------------- - function isalpha(c: character) return boolean; - function isupper(c: character) return boolean; - function islower(c: character) return boolean; - function isdigit(c: character) return boolean; - function isxdigit(c: character) return boolean; - function isalnum(c: character) return boolean; - function isspace(c: character) return boolean; - function ispunct(c: character) return boolean; - function isprint(c: character) return boolean; - function isgraph(c: character) return boolean; - function iscntrl(c: character) return boolean; - function isascii(c: character) return boolean; - function tolower(c: character) return character; - function toupper(c: character) return character; - - - --This implementation was done to use the VHDL simulator efficiently - --and minimize number of boolean type arrays - - type tarray is array(0 to 255) of integer; - constant t: tarray:=( - 2, 2, 2, 2, 2, 2, 2, 2, 2,11*2,11*2,11*2,11*2,11*2, 2, 2, --0x00 - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, --0x10 - 11, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, --0x20 - 13*3,13*3,13*3,13*3,13*3,13*3,13*3,13*3,13*3,13*3, 17, 17, 17, 17, 17, 17, --0x30 - 17, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5, 5, 5, 5, 5, --0x40 - 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 17, 17, 17, 17, 17, --0x50 - 17, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7, 7, 7, 7, 7, --0x60 - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 17, 17, 17, 17, 2, --0x70 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0x80 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0x90 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xa0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xb0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xc0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xd0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xe0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);--0xf0 - ---------------------------------------------------------------------------------------------------------- --- end ctype_h; ---------------------------------------------------------------------------------------------------------- - - ---------------------------------------------------------------------------------------------------------- --- package strings_h is ---------------------------------------------------------------------------------------------------------- - ---c/c++ string is an array of integers and are variable in length ---cannot contain a zero byte, concession to computers with fast zero compare ---also no need to save length size ---cannot protect overwriting allocated size ---mixed endian, little endian string but big endian bytes - ---vhdl string is an array of enumerated types and are fixed in length ---..this makes it difficult to embed numeric characters ---..like in C (i.e. \0x0d ) - - --C language addressing: strlen(s+si); - function strlen(s: IN string) return integer; - function strlen(s: IN string; si: IN integer) return integer; ---function strlen(s: INOUT line) return integer; --use instead: strlen(s.all); - - --array constant still works "s": strcpy(s, ""); - --strcpy(d, s); strcpy(d, s+si); strcpy(d+di, s); strcpy(d+di, s+si); - procedure strcpy(d: OUT string; s: IN string); - procedure strcpy(d: OUT string; s: IN string; si: IN integer); - procedure strcpy(d: INOUT string; di: IN integer; s: IN string); - procedure strcpy(d: INOUT string; di: IN integer; s: IN string; si: IN integer); - - --element constant still works 'c': strcpy(s, '#'); - procedure strcpy(d: OUT string; s: IN character); - - procedure strcat(d: INOUT line; s: IN string); --Due to ModelSim - procedure strcat(d: INOUT string; s: IN string); - procedure strcat(d: INOUT string; s: IN string; si: IN integer); - procedure strcat(d: INOUT string; di: IN integer; s: IN string); - procedure strcat(d: INOUT string; di: IN integer; s: IN string; si: IN integer); - - procedure strcat(d: INOUT string; s: IN character); - - function strcmp(d: IN string; s: IN string) return integer; - - procedure strcpyij(d: OUT string; s: IN string; i, j: IN integer); - ---------------------------------------------------------------------------------------------------------- --- end strings_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package stdlib_h is ---------------------------------------------------------------------------------------------------------- - procedure strtoul(result: OUT integer; --natural - s: IN string; si: IN integer; - endptr: INOUT integer; base:IN integer); - - procedure strtoul(result: OUT integer; --natural - s: IN string; - endptr: INOUT integer; base:IN integer); - - procedure strtol(result: OUT integer; --natural - s: IN string; si: IN integer; - endptr: INOUT integer; base:IN integer); - - procedure strtol(result: OUT integer; --natural - s: IN string; - endptr: INOUT integer; base:IN integer); - - function atoi(s: IN string) return integer; - - function atol(s: IN string) return integer; - ---------------------------------------------------------------------------------------------------------- --- end stdlib_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package regexp_h is ---------------------------------------------------------------------------------------------------------- - --AVOID: since shared variables will cause problems with multiple processes - - --INPUT si = initial index into the string - --INPUT s = scan string terminated by NUL or length - --INPUT f = pattern matching format string (i.e. perl style, less typing than sed) - - --OUTPUT ai = 0 none, alternate match number = 1|2|3|4|... - --OUTPUT si = next unmatch character - --OUTPUT m1 = matched (string) =\1 - --OUTPUT m2 = matched (string) =\2 - - --NOTES: . = match any character except NUL - -- (differs from perl which is newline - -- since pattern matching is limited to a line) - -- ^$ = match an empty string (i.e. length=0 or first character=NUL) - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; f: IN string); - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1: OUT string); - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1,m2: OUT string); - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1,m2,m3: OUT string); - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1,m2,m3,m4: OUT string); - - function sedscanf(s: IN string) return string; - ---------------------------------------------------------------------------------------------------------- --- end regexp_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- PACKAGE stdio_h IS ---------------------------------------------------------------------------------------------------------- - FILE streamfile4, streamfile5, streamfile6: TEXT; - FILE streamfile7, streamfile8, streamfile9: TEXT; - CONSTANT streamNFILE: INTEGER:=9; - - TYPE streamflags IS ARRAY(0 TO streamNFILE) OF BOOLEAN; - SHARED VARIABLE streambusy: streamflags := (TRUE,TRUE,TRUE,TRUE,OTHERS=>FALSE); - SHARED VARIABLE streamlock: BOOLEAN:=FALSE; - SHARED VARIABLE streamnulbuf: LINE; --should allows be null - - TYPE STREAMIOBUF IS - RECORD - fstat: FILE_OPEN_STATUS; - fmode: FILE_OPEN_KIND; --READ_MODE, WRITE_MODE, APPEND_MODE; - buf: LINE; - END RECORD; - - TYPE STREAMIOBUFS IS ARRAY(0 TO streamNFILE) OF STREAMIOBUF; - SHARED VARIABLE streamiob: STREAMIOBUFS := - ((STATUS_ERROR,READ_MODE,NULL), --null fid - (OPEN_OK,WRITE_MODE,NULL), --stdout - (OPEN_OK,READ_MODE,NULL), --stdin - OTHERS=>(STATUS_ERROR,READ_MODE,NULL)); - - SUBTYPE CFILE IS INTEGER; - CONSTANT stdin: CFILE :=2; --UNIX filename "/dev/tty", DOS filename "CON" - CONSTANT stdout: CFILE :=1; --UNIX filename "/dev/tty", DOS filename "CON" - CONSTANT stdnul: CFILE :=3; --UNIX filename "/dev/null", DOS filename "NUL" - CONSTANT stderr: CFILE :=1; --Not support by VHDL 93 - - FUNCTION pf(x: IN BIT) RETURN STRING; - FUNCTION pf(x: IN BOOLEAN) RETURN STRING; - FUNCTION pf(x: IN CHARACTER) RETURN STRING; - FUNCTION pf(x: IN STD_ULOGIC) RETURN STRING; - FUNCTION pf(x: IN STRING) RETURN STRING; - FUNCTION pf(x: IN INTEGER) RETURN STRING; - FUNCTION pf(x: IN BIT_VECTOR) RETURN STRING; - FUNCTION pf(x: IN STD_ULOGIC_VECTOR) RETURN STRING; - FUNCTION pf(x: IN STD_LOGIC_VECTOR) RETURN STRING; - FUNCTION pf(x: IN TIME) RETURN STRING; - FUNCTION pf(x: IN REAL) RETURN STRING; - - -- FILE *fopen(const char *filename, const char *mode); - IMPURE FUNCTION fopen(filename: IN STRING; mode: IN STRING) RETURN CFILE; - -- int fflush(FILE *stream); - PROCEDURE fflush(stream: IN CFILE); - -- int fclose(FILE *stream); - PROCEDURE fclose(stream: IN CFILE); - - -- int fputc(int c, FILE *stream); - PROCEDURE fputc(c: IN character; stream: IN CFILE); - -- int fputs(const char *s, FILE *stream); - PROCEDURE fputs(s: IN STRING; stream: IN CFILE); - PROCEDURE fputs(s: INOUT LINE; stream: IN CFILE); --will deallocate(s) - -- int putc(int c, FILE *stream); - PROCEDURE putc(c: IN character; stream: IN CFILE); - -- int putchar(int c); - PROCEDURE putchar(c: IN character); - -- int puts(const char *s); - PROCEDURE puts(s: IN STRING); - PROCEDURE puts(s: INOUT LINE); --will deallocate(s) - - -- int feof(FILE *stream); - IMPURE FUNCTION feof(stream: IN CFILE) RETURN BOOLEAN; - -- int fgetc(FILE *stream); - IMPURE FUNCTION fgetc(stream: IN CFILE) RETURN CHARACTER; - -- char *fgets(char *s, int size, FILE *stream); - PROCEDURE fgets(s: OUT STRING; n: IN INTEGER; stream: IN CFILE); - -- int getc(FILE *stream); - IMPURE FUNCTION getc(stream: IN CFILE) RETURN CHARACTER; - -- int getchar(void); - IMPURE FUNCTION getchar RETURN CHARACTER; - -- char *gets(char *s); - PROCEDURE gets(s: OUT STRING); - -- int ungetc(int c, FILE *stream); - PROCEDURE ungetc(c: IN character; stream: IN CFILE); - - PROCEDURE sbufprintf(fi: INOUT INTEGER; sbuf: INOUT LINE; stream: IN CFILE; - fmt: IN STRING; s: IN STRING); --used only for testing package - - PROCEDURE sbufscanf(fi: INOUT INTEGER; sbuf: INOUT LINE; stream: IN CFILE; - fmt: IN STRING; s: INOUT LINE); --used only for testing package - - PROCEDURE fprintf(stream: IN CFILE; format: IN STRING; a1: INOUT LINE); - PROCEDURE printf( format: IN STRING; a1: INOUT LINE); - PROCEDURE fscanf( stream: IN CFILE; format: IN string; a1: INOUT LINE); - PROCEDURE scanf( format: IN string; a1: INOUT LINE); - PROCEDURE sscanf( s: IN string; format: IN string; a1: INOUT LINE); - - - PROCEDURE fprintf(stream: IN CFILE; - format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " "); - - PROCEDURE fprintf(stream: IN CFILE; - format: IN STRING; - a1: IN STD_LOGIC_VECTOR; - a2, a3, a4, a5, a6, a7, a8 : IN STD_LOGIC_VECTOR := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN STD_LOGIC_VECTOR := "U"); - - PROCEDURE printf( format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " "); - - PROCEDURE printf( format: IN STRING; - a1: IN STD_LOGIC_VECTOR; - a2, a3, a4, a5, a6, a7, a8 : IN STD_LOGIC_VECTOR := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN STD_LOGIC_VECTOR := "U"); - - PROCEDURE sprintf(s: INOUT LINE; format: IN STRING; --Append to variable s - a1, a2, a3, a4, a5, a6, a7, a8 : IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " "); - - PROCEDURE sprintf(s: INOUT STRING; format: IN STRING; --Overwrite variable s - a1, a2, a3, a4, a5, a6, a7, a8 : IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " "); - - PROCEDURE sprintf(s: INOUT STRING; format: IN STRING; - a1: IN STD_LOGIC_VECTOR; - a2, a3, a4, a5, a6, a7, a8 : IN STD_LOGIC_VECTOR := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN STD_LOGIC_VECTOR := "U"); - - - PROCEDURE printf(format: IN string; a1: integer); - - PROCEDURE printf(format: IN string; a1: std_logic); - - PROCEDURE printf(format: IN string; a1: boolean); - - PROCEDURE printf(format: IN string; a1: bit); - - PROCEDURE printf(format: IN string; a1: bit_vector); - - PROCEDURE printf(format: IN string; a1: time); - - PROCEDURE printf(format: IN string; a1: real); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: integer); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: std_logic); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: boolean); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: bit); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: bit_vector); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: time); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: real); - - PROCEDURE scanf(format: IN string; a1: INOUT string); - - PROCEDURE scanf(format: IN string; a1: INOUT integer); - - PROCEDURE scanf(format: IN string; a1: INOUT std_logic); - - PROCEDURE scanf(format: IN string; a1: INOUT std_logic_vector); - - PROCEDURE scanf(format: IN string; a1: INOUT boolean); - - PROCEDURE scanf(format: IN string; a1: INOUT bit); - - PROCEDURE scanf(format: IN string; a1: INOUT bit_vector); - - PROCEDURE scanf(format: IN string; a1: INOUT time); - - PROCEDURE scanf(format: IN string; a1: INOUT real); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT string); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT integer); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT std_logic); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT std_logic_vector); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT boolean); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT bit); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT bit_vector); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT time); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT real); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT string); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT integer); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT std_logic); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT std_logic_vector); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT boolean); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT bit); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT bit_vector); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT time); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT real); - ---------------------------------------------------------------------------------------------------------- --- end stdio_h; ---------------------------------------------------------------------------------------------------------- - -end vhdl_c_pkg_tb; - - - -PACKAGE BODY vhdl_c_pkg_tb IS - ---------------------------------------------------------------------------------------------------------- ---PACKAGE BODY endian_h IS ---------------------------------------------------------------------------------------------------------- - - FUNCTION to_bigendian_bit_vector(x: IN BIT_VECTOR) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(x'HIGH DOWNTO x'LOW); --big endian: HIGH DOWNTO LOW - BEGIN - FOR i IN x'RANGE LOOP y(i) := x(i); END LOOP; - RETURN y; - END to_bigendian_bit_vector; - - FUNCTION to_littleendian_bit_vector(x: IN BIT_VECTOR) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(x'LOW TO x'HIGH); --little endian: LOW TO HIGH - BEGIN - FOR i IN x'RANGE LOOP y(i) := x(i); END LOOP; - RETURN y; - END to_littleendian_bit_vector; - - FUNCTION to_littleendian_bit_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(0 TO n-1); VARIABLE c: bit:='0'; --carry - VARIABLE ax, j: INTEGER; - BEGIN - ax:=x; IF ax<0 THEN ax:=-ax; c:='1'; END IF; - FOR i IN y'LOW TO y'HIGH LOOP - j:=ax MOD 2; ax:=ax/2; - IF x<0 THEN - IF j=0 THEN y(i):='1'; ELSE y(i):=c; c:='0'; END IF; - ELSE - IF j=0 THEN y(i):='0'; ELSE y(i):='1'; END IF; - END IF; - END LOOP; - ASSERT ax=0 AND c='0' - REPORT "bit_vector_bigendian(x, n) bit length too small" - SEVERITY WARNING; - RETURN y; - END to_littleendian_bit_vector; - - FUNCTION to_bigendian_bit_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN BIT_VECTOR IS - VARIABLE v: BIT_VECTOR(0 TO n-1); VARIABLE y: BIT_VECTOR(n-1 DOWNTO 0); - BEGIN - v := to_littleendian_bit_vector(x, n); - y := to_bigendian_bit_vector(v); - RETURN y; - END to_bigendian_bit_vector; - - FUNCTION to_bigendian_std_logic_vector(x: IN BIT_VECTOR) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'HIGH DOWNTO x'LOW); --big endian: HIGH DOWNTO LOW - BEGIN - FOR i IN x'RANGE LOOP IF x(i)='1' THEN y(i):='1'; ELSE y(i):='0'; END IF; END LOOP; - RETURN y; - END to_bigendian_std_logic_vector; - - FUNCTION to_littleendian_std_logic_vector(x: IN BIT_VECTOR) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'LOW TO x'HIGH); --little endian: LOW TO HIGH - BEGIN - FOR i IN x'RANGE LOOP IF x(i)='1' THEN y(i):='1'; ELSE y(i):='0'; END IF; END LOOP; - RETURN y; - END to_littleendian_std_logic_vector; - - FUNCTION to_bigendian_std_logic_vector(x: IN std_logic_vector) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'HIGH DOWNTO x'LOW); --big endian: HIGH DOWNTO LOW - BEGIN - FOR i IN x'RANGE LOOP y(i) := x(i); END LOOP; - RETURN y; - END to_bigendian_std_logic_vector; - - FUNCTION to_littleendian_std_logic_vector(x: IN std_logic_vector) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'LOW TO x'HIGH); --little endian: LOW TO HIGH - BEGIN - FOR i IN x'RANGE LOOP y(i) := x(i); END LOOP; - RETURN y; - END to_littleendian_std_logic_vector; - - FUNCTION to_littleendian_std_logic_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN STD_LOGIC_VECTOR IS - VARIABLE v: BIT_VECTOR(0 TO n-1); VARIABLE y: STD_LOGIC_VECTOR(n-1 DOWNTO 0); - BEGIN - v := to_littleendian_bit_vector(x, n); - y := to_littleendian_std_logic_vector(v); - RETURN y; - END to_littleendian_std_logic_vector; - - FUNCTION to_bigendian_std_logic_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN STD_LOGIC_VECTOR IS - VARIABLE v: BIT_VECTOR(0 TO n-1); VARIABLE y: STD_LOGIC_VECTOR(n-1 DOWNTO 0); - BEGIN - v := to_littleendian_bit_vector(x, n); - y := to_bigendian_std_logic_vector(v); - RETURN y; - END to_bigendian_std_logic_vector; - - - - FUNCTION to_bigendian_bit_vector_string(x: IN STRING) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(x'LENGTH-1 DOWNTO 0); --big endian: HIGH DOWNTO LOW - BEGIN - FOR i IN x'RANGE LOOP - IF x(i)='1' THEN y(x'LENGTH-i):='1'; ELSE y(x'LENGTH-i):='0'; END IF; - END LOOP; - RETURN y; - END to_bigendian_bit_vector_string; - - FUNCTION to_littleendian_bit_vector_string(x: IN STRING) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(0 TO x'LENGTH-1); --little endian: LOW TO HIGH - BEGIN - FOR i IN x'RANGE LOOP - IF x(i)='1' THEN y(x'LENGTH-i):='1'; ELSE y(x'LENGTH-i):='0'; END IF; - END LOOP; - RETURN y; - END to_littleendian_bit_vector_string; - - FUNCTION to_bigendian_std_logic_vector_string(x: IN STRING) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'LENGTH-1 DOWNTO 0); VARIABLE s: std_logic; - BEGIN - FOR i IN x'RANGE LOOP - CASE x(i) IS - WHEN '1' => s:='1'; WHEN '0' => s:='0'; - WHEN 'X'|'x'=> s:='X'; - WHEN 'Z'|'z'=> s:='Z'; WHEN 'W'|'w'=> s:='W'; - WHEN 'H'|'h'=> s:='H'; WHEN 'L'|'l'=> s:='L'; - WHEN '-' => s:='-'; WHEN others => s:='U'; - END CASE; - y(x'LENGTH-i):=s; - END LOOP; - RETURN y; - END to_bigendian_std_logic_vector_string; - - FUNCTION to_littleendian_std_logic_vector_string(x: IN STRING) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(0 TO x'LENGTH-1); VARIABLE s: std_logic; - BEGIN - FOR i IN x'RANGE LOOP - CASE x(i) IS - WHEN '1' => s:='1'; WHEN '0' => s:='0'; - WHEN 'X'|'x'=> s:='X'; - WHEN 'Z'|'z'=> s:='Z'; WHEN 'W'|'w'=> s:='W'; - WHEN 'H'|'h'=> s:='H'; WHEN 'L'|'l'=> s:='L'; - WHEN '-' => s:='-'; WHEN others => s:='U'; - END CASE; - y(x'LENGTH-i):=s; - END LOOP; - RETURN y; - END to_littleendian_std_logic_vector_string; - ---------------------------------------------------------------------------------------------------------- ---END endian_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package body ctype_h is ---------------------------------------------------------------------------------------------------------- - - function isalpha(c: character) return boolean is - begin - return t(character'pos(c)) mod 5 = 0 OR t(character'pos(c)) mod 7 = 0; - end isalpha; - - function isupper(c: character) return boolean is - begin - return t(character'pos(c)) mod 5 = 0; - end isupper; - - function islower(c: character) return boolean is - begin - return t(character'pos(c)) mod 7 = 0; - end islower; - - function isdigit(c: character) return boolean is - begin - return t(character'pos(c)) mod 13 = 0; - end isdigit; - - function isxdigit(c: character) return boolean is - begin - return t(character'pos(c)) mod 3 = 0; - end isxdigit; - - function isalnum(c: character) return boolean is - begin - return t(character'pos(c)) mod 3 = 0 - OR t(character'pos(c)) mod 5 = 0 - OR t(character'pos(c)) mod 7 = 0; - end isalnum; - - function isspace(c: character) return boolean is - begin - return t(character'pos(c)) mod 11 = 0; - end isspace; - - function ispunct(c: character) return boolean is - begin - return t(character'pos(c)) mod 17 = 0; - end ispunct; - - function isprint(c: character) return boolean is - begin - return t(character'pos(c)) mod 3 = 0 - OR t(character'pos(c)) mod 5 = 0 - OR t(character'pos(c)) mod 7 = 0 - OR t(character'pos(c)) mod 17 = 0 - OR c=' '; - end isprint; - - function isgraph(c: character) return boolean is - begin - return t(character'pos(c)) mod 3 = 0 - OR t(character'pos(c)) mod 5 = 0 - OR t(character'pos(c)) mod 7 = 0 - OR t(character'pos(c)) mod 17 = 0; - end isgraph; - - function iscntrl(c: character) return boolean is - begin - return t(character'pos(c)) mod 2 = 0; - end iscntrl; - - function isascii(c: character) return boolean is - begin - return character'pos(c) >= 0 and character'pos(c)<=127; - end isascii; - - function tolower(c: character) return character is - begin - if character'pos(c)>=65 AND character'pos(c)<=90 then - return character'val(character'pos(c)+32); - else - return c; - end if; - end tolower; - - function toupper(c: character) return character is - begin - if character'pos(c)>=97 AND character'pos(c)<=122 then - return character'val(character'pos(c)-32); - else - return c; - end if; - end toupper; - ---------------------------------------------------------------------------------------------------------- --- end ctype_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package body strings_h is ---------------------------------------------------------------------------------------------------------- - - --Added Because ModelSim write(buf, s); will copy beyond NUL until s'length - procedure strcat(d: INOUT line; s: IN string) is - variable sj: integer:=s'left; - begin - if s'length>0 then - loop - if s(sj)=NUL then exit; end if; - write(d, s(sj)); - - if ( s'left > s'right ) then - if sj<=s'right then exit; end if; - sj:=sj-1; - else - if sj>=s'right then exit; end if; - sj:=sj+1; - end if; - end loop; - end if; - end strcat; - - procedure strcpy(d: OUT string; s: IN string) is - variable dj: integer:=d'left; - variable sj: integer:=s'left; - --variable W : line; - begin - --write(W,string'("strcpy: ")); - --write(W,string'(" s=")); write(W,s); - --write(W,string'(" s'left=")); write(W,s'left); - --write(W,string'(" s'right=")); write(W,s'right); - --write(W,string'(" s'length=")); write(W,s'length); - --write(W,string'(" d'left=")); write(W,d'left); - --write(W,string'(" d'right=")); write(W,d'right); - --write(W,string'(" d'length=")); write(W,d'length); - --writeline(output, W); - - if s'length<=0 then - if d'length>=1 then d(d'left):=NUL; end if; - else - loop - --write(W,string'(" s(")); write(W,sj); - --write(W,string'(")=")); write(W,s(sj)); - --write(W,string'(" dj=")); write(W,dj); - --writeline(output,W); - - if s(sj)=NUL then d(dj):=NUL; exit; end if; - d(dj):=s(sj); - if ( d'left > d'right ) then - if dj<=d'right then exit; end if; - dj:=dj-1; - else - if dj>=d'right then exit; end if; - dj:=dj+1; - end if; - if ( s'left > s'right ) then - if sj<=s'right then d(dj):=NUL; exit; end if; - sj:=sj-1; - else - if sj>=s'right then d(dj):=NUL; exit; end if; - sj:=sj+1; - end if; - end loop; - end if; - end strcpy; - - procedure strcpy(d: OUT string; s: IN string; si: IN integer) is - variable dj: integer:=d'left; - variable sj: integer:=si; --Synopsys does not support BUFFER (pass by value) - begin - loop - if dj>d'right then d(d'right):=NUL; exit; end if; - if sj>s'right then d(dj):=NUL; exit; end if; - if s(sj)=NUL then d(dj):=NUL; exit; end if; - d(dj):=s(sj); dj:=dj+1; sj:=sj+1; - end loop; - end strcpy; -- procedure; johan - - - procedure strcpy(d: INOUT string; di: IN integer; s: IN string) is - begin strcpy(d, di, s, 1); end strcpy; -- procedure; johan - - --Make it easy to translate back to C: strcpy(d+di, s+si) - procedure strcpy(d: INOUT string; di: IN integer; s: IN string; si: IN integer) is - variable dj: integer:=di; --Synopsys does not support BUFFER - variable sj: integer:=si; --Synopsys does not support BUFFER (pass by value) - begin - loop - if dj>d'right then d(d'right):=NUL; exit; end if; - if sj>s'right then d(dj):=NUL; exit; end if; - if s(sj)=NUL then d(dj):=NUL; exit; end if; - d(dj):=s(sj); dj:=dj+1; sj:=sj+1; - end loop; - end strcpy; -- procedure; johan - - - procedure strcat(d: INOUT string; di: IN integer; s: IN string; si: IN integer) is - variable dj: integer:=di; - variable sj: integer:=si; - begin - --strcpy(d, strlen(d)+1, s, si); - loop - if dj>d'right then d(d'right):=NUL; exit; end if; - if d(dj)=NUL then exit; end if; - dj:=dj+1; - end loop; - - loop - if dj>d'right then d(d'right):=NUL; exit; end if; - if sj>s'right then d(dj):=NUL; exit; end if; - if s(sj)=NUL then d(dj):=NUL; exit; end if; - d(dj):=s(sj); dj:=dj+1; sj:=sj+1; - end loop; - end strcat; -- procedure; johan - - procedure strcat(d: INOUT string; di: IN integer; s: IN string) is - begin strcat(d, di, s, 1); end strcat; - - procedure strcat(d: INOUT string; s: IN string; si: IN integer) is - begin strcat(d, 1, s, si); end strcat; - - procedure strcat(d: INOUT string; s: IN string) is - begin strcat(d, 1, s, 1); end strcat; - - - function strcmp(d: IN string; s: IN string) return integer is - variable i: integer:=1; variable dc, sc: character; - begin - loop - if i<=d'right then dc:=d(i); else dc:=NUL; end if; - if i<=s'right then sc:=s(i); else sc:=NUL; end if; - - - if dc/=sc or dc=NUL then - return character'pos(dc) - character'pos(sc); - else - i:=i+1; - end if; - end loop; - end strcmp; - - function strlen(s: IN string) return integer is - variable n: integer:=0; variable sj: integer:=s'left; - begin - loop - if sj>s'right then exit; - elsif s(sj)=NUL then exit; --sequential if protects sj > length - else sj:=sj+1; n:=n+1; - end if; - end loop; - return n; - end strlen; - - function strlen(s: IN string; si: IN integer) return integer is - variable n: integer:=0; variable sj: integer:=si; - begin - loop - if sj>s'right then exit; - elsif s(sj)=NUL then exit; --sequential if protects sj > length - else sj:=sj+1; n:=n+1; - end if; - end loop; - return n; - end strlen; - - procedure strcpy( d: OUT string; s: IN character) is - variable cs: string(1 to 2); - begin - cs(1):=s; cs(2):=NUL; strcpy(d, cs); - end strcpy; -- johan - - procedure strcat( d: INOUT string; s: IN character) is - variable cs: string(1 to 2); - begin - cs(1):=s; cs(2):=NUL; strcat(d, cs); - end strcat; -- strcat - - -- d(1 to j-i+1):=s(i to j) - -- strcpy(d, s(i to j)); - procedure strcpyij(d: OUT string; s: IN string; i, j: IN integer) is - variable di: integer:=1; - variable si: integer:=i; - begin - loop - if di>d'right then d(d'right):=NUL; exit; end if; - if si>s'right then d(di):=NUL; exit; end if; - if s(si)=NUL then d(di):=NUL; exit; end if; - if si>j then d(di):=NUL; exit; end if; --added on to strcpy - d(di):=s(si); di:=di+1; si:=si+1; - end loop; - end strcpyij; -- procedure; johan - ---------------------------------------------------------------------------------------------------------- --- end strings_h; -- johan ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package body stdlib_h is ---------------------------------------------------------------------------------------------------------- - procedure strtoul(result: OUT integer; --natural - s: IN string; si: IN integer; - endptr: INOUT integer; base:IN integer) IS - - variable p: integer:=si; - variable f: integer:=0; --actual digits flag hit - variable d: integer; - variable b: integer:=base; - variable r: integer; - begin - r:=0; - while p<=s'length loop - if isspace(s(p)) then p:=p+1; else exit; end if; - end loop; - - if b=0 then --auto detect base - if p<=s'length then - if s(p)='0' then - p:=p+1; - if p<=s'length then - if s(p)='x' OR s(p)='X' then - p:=p+1; b:=16; - else - f:=1; b:=8; - end if; - end if; - else - b:=10; - end if; - end if; - elsif b=16 then - if p=b then exit; end if; - r:=(b*r)+d; f:=1; p:=p+1; - end loop; - - if f=0 then p:=si; end if; - - if endptr/=0 then endptr:=p; end if; - - result:=r; - end strtoul; - - procedure strtoul(result: OUT integer; --natural - s: IN string; - endptr: INOUT integer; base:IN integer) IS - begin - strtoul(result, s, 1, endptr, base); - end strtoul; - - procedure strtol(result: OUT integer; --natural - s: IN string; si: IN integer; - endptr: INOUT integer; base:IN integer) IS - variable r: integer:=0; - variable p: integer:=si; - begin - while p<=s'length loop - if isspace(s(p)) then p:=p+1; else exit; end if; - end loop; - - if p<=s'length then - if s(p)='-' then - p:=p+1; strtoul(r, s, p, endptr, base); result:= -r; - - else - if s(p)='+' then p:=p+1; end if; - strtoul(r, s, p, endptr, base); result:=r; - end if; - end if; - - if r=0 AND endptr/=0 AND endptr=p then endptr:=si; end if; - end strtol; - - procedure strtol(result: OUT integer; --natural - s: IN string; - endptr: INOUT integer; base:IN integer) IS - begin - strtol(result, s, 1, endptr, base); - end strtol; - - function atoi(s: IN string) return integer is - variable result, p: integer:=0; - begin - strtol(result, s, 1, p, 10); return result; - end atoi; - - function atol(s: IN string) return integer is - variable result, p: integer:=0; - begin - strtol(result, s, 1, p, 10); return result; - end atol; - ---------------------------------------------------------------------------------------------------------- --- end stdlib_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package body regexp_h is ---------------------------------------------------------------------------------------------------------- --- For instance, `[^]0-9-]' means the set `everything except close --- bracket, zero through nine, and hyphen'. - - function mfalse(m: integer) return integer is - begin - if m=1 then return 0; elsif m=0 then return -2; else return m; end if; - end; - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1,m2,m3,m4: OUT string) is - - variable debug: boolean:=false; --TRUE; - - type tarray is array(integer range <>) of bit; - variable t: tarray(0 to 256); - variable tset: bit; - - type iarray is array(integer range <>) of integer; - variable fstack: iarray(1 to 15); --stack of format pointer - variable mstack: iarray(1 to 15); --stack of match flags - variable mistack: iarray(1 to 15); --stack of mi match left parenthesis - variable sstack: iarray(1 to 15); --stack of string pointers - variable sp: integer; - - variable aii: integer:=0; - variable si_in: integer; - variable simax: integer:=1; --debugging information - variable fi: integer; - variable m: integer; --=0 false, 1=true, -1=skip true, -2=skip false - variable mi: integer:=0; - variable ms: string(1 to 80); - variable fb,mc,j: integer; - variable mr,mm,mn: integer; - variable mlast: integer; - variable b, c: character; - variable bi, ci: integer; - variable W: line; - begin - if debug then - write(W, string'("------------------------------------------")); - write(W, string'(" string=")); write(W, s); - write(W, string'(" si=")); write(W, si); - write(W, string'(" string'length=")); write(W, s'length); - write(W, string'(" format=")); write(W, f); - writeline(output, W); - end if; - - si_in:=si; --si:=1; - fi:=0; sp:=1; m:=1; - sstack(1):=si; fstack(1):=1; mstack(1):=1; mistack(1):=0; - sstack(2):=si; fstack(2):=1; mstack(2):=1; mistack(2):=0; - loop - fi:=fi+1; if fi>f'length then exit; end if; - mc:=0; mr:=0; tset:='1'; t:=(others=>'0'); - - if debug then - write(W, string'(" loop:ai=")); write(W, aii); - write(W, string'(" m=")); write(W, m); - write(W, string'(" f(")); write(W, fi); write(W, string'(")=")); - write(W, f(fi)); - writeline(output, W); - write(W, string'(" s(")); write(W, si); write(W, string'(")=")); - if si<=s'length then write(W, s(si)); else write(W, string'("UUU")); end if; - write(W, string'(" mstack(")); write(W, sp); write(W, string'(")=")); write(W, mstack(sp)); - write(W, string'(" sstack(")); write(W, sp); write(W, string'(")=")); write(W, sstack(sp)); - writeline(output, W); - end if; - - case f(fi) is - when '^' => --Match beginning of line - if si/=si_in then m:=mfalse(m); end if; - - when '$' => --Match end of line - if si<=s'length then if s(si)/=NUL then m:=mfalse(m); end if; - elsif si/=(s'length+1) then m:=mfalse(m); end if; - - when '*' => --Match last expression 0 or more times - if m=1 then fi:=fstack(sp+1)-1; - elsif m=0 then - m:=mstack(sp+1); si:=sstack(sp+1); - if si>simax then simax:=si; end if; - end if; - - when '?' => --Match last expression 0 or 1 times - if m= 0 then - m:=mstack(sp+1); si:=sstack(sp+1); --ab?c\(def?g?h\)? - if si>simax then simax:=si; end if; --- elsif m=-1 then m:=-1; --looking for right parenthesis --- elsif m=-2 then m:=-2; --looking for alternate-bar or right - end if; - - --[character pattern] - --Examples: [abc], []], [^abc], [0-9-], [^]], [^]abc], [^^] - when '[' => - mc:=1; if m=1 then fstack(sp+1):=fi; end if; --needed for 0 or more operator - fb:=fi; - loop - fi:=fi+1; if fi>f'length then exit; end if; - - if debug then - write(W, string'(" [char pattern]:f(")); write(W, fi); - write(W, string'(")=")); write(W, f(fi)); - writeline(output, W); - end if; - - b:=c; c:=f(fi); - - --To include a close bracket in the set, - --make it the first character after the open bracket - --or the circumflex; any other position will end the set. - --Examples: []] or the NOT cases: [^]] or [^]abc] or [^^] - - if c='\' then - fi:=fi+1; if fi>f'length then exit; end if; - - case f(fi) is - when 'a' => t(character'pos(BEL)):=tset; - when 'b' => t(character'pos(BS)):=tset; - when 'f' => t(character'pos(FF)):=tset; - when 'n' => t(character'pos(LF)):=tset; - when 'r' => t(character'pos(CR)):=tset; - when 't' => t(character'pos(HT)):=tset; - when 'v' => t(character'pos(VT)):=tset; - when '\' => t(character'pos('\')):=tset; - when others => t(character'pos(f(fi))):=tset; - end case; - - elsif c='^' then - if fb+1=fi then tset:='0'; t:=(others=>'1'); - else t(character'pos(c)):=tset; end if; - - elsif c=']' then - if (fb+1=fi and tset='1') or (fb+2=fi and tset='0') then - t(character'pos(c)):=tset; - else - exit; - end if; - - elsif c='-' then - fi:=fi+1; if fi>f'length then exit; end if; --lookahead - - -- To include a hyphen, make it the last character - -- before the final close bracket: [9-] or [---] or [-9]. - if f(fi)=']' then - t(character'pos(c)):=tset; fi:=fi-1; - else - bi:=character'pos(b); ci:=character'pos(f(fi)); - for ti in bi to ci loop t(ti):=tset; end loop; - end if; - else - t(character'pos(c)):=tset; - end if; - end loop; - - when NUL => aii:=aii+1; exit; - - when '(' => sp:=sp+1; - sstack(sp):=si; fstack(sp):=fi-1; mstack(sp):=m; - mi:=mi+1; mistack(sp):=mi; - - when ')' => - if m=1 then - strcpyij(ms, s, sstack(sp), si-1); - case mistack(sp) is - when 1 => strcpy(m1, ms); - when 2 => strcpy(m2, ms); - when 3 => strcpy(m3, ms); - when 4 => strcpy(m4, ms); - when others => - end case; - end if; - - if debug then - write(W, string'(" (Right):store: m=")); write(W, m); - write(W, string'(" ms=")); write(W, ms); - write(W, string'(" mistack(sp)=")); write(W, mistack(sp)); - write(W, string'(" sstack(")); write(W, sp); - write(W, string'(")=")); write(W, sstack(sp)); - write(W, string'(" si=")); write(W, si); - writeline(output, W); - end if; - - sp:=sp-1; - if m=-1 then m:=1; --implies an alternate-bar was encountered - elsif m=0 or m=-2 then - m:=0; si:=sstack(sp); - if si>simax then simax:=si; end if; - end if; - - when '{' => - when '}' => - when '|' => if m=1 then - strcpyij(ms, s, sstack(sp), si-1); - case mistack(sp) is - when 1 => strcpy(m1, ms); - when 2 => strcpy(m2, ms); - when 3 => strcpy(m3, ms); - when 4 => strcpy(m4, ms); - when others => - end case; - end if; - - if debug then - write(W, string'(" Bar|:store: m=")); write(W, m); - write(W, string'(" ms=")); write(W, ms); - write(W, string'(" mistack(sp)=")); write(W, mistack(sp)); - write(W, string'(" sstack(")); write(W, sp); - write(W, string'(")=")); write(W, sstack(sp)); - write(W, string'(" si=")); write(W, si); - writeline(output, W); - end if; - - if sp=1 then - mi:=0; aii:=aii+1; if m=1 then exit; end if; --break out early - end if; - - if m=1 then m:=-1; --looking for next grouping parenthesis - elsif m=0 or m=-2 then - m:=mstack(sp); si:=sstack(sp); - if si>simax then simax:=si; end if; - end if; - - when '\' => - fi:=fi+1; if fi>f'length then exit; end if; - - if debug then - write(W, string'(" f(")); write(W, fi); - write(W, string'(")=")); write(W, f(fi)); - writeline(output, W); - end if; - - case f(fi) is - when others => - t(character'pos(f(fi))):='1'; - mc:=1; if m=1 then fstack(sp+1):=fi; end if; - end case; - - when '.' => --match any character except NUL - t:=(others=>'1'); --t(character'pos(LF)):='0'; --differ from sed - mc:=1; if m=1 then fstack(sp+1):=fi; end if; - - when others => - t(character'pos(f(fi))):='1'; - mc:=1; if m=1 then fstack(sp+1):=fi; end if; - - end case; - - if mc=1 then - if m=0 then m:=-2; --skip characters - elsif m=1 then - sstack(sp+1):=si; mstack(sp+1):=m; - - t(character'pos(NUL)):='0'; - if si<=s'length then - if debug then - write(W, string'("match: s(")); write(W, si); - write(W, string'(")=")); write(W, s(si)); - write(W, string'(" with t(s(si))=")); write(W, t(character'pos(s(si)))); - writeline(output, W); - end if; - - if t(character'pos(s(si)))='1' then si:=si+1; else m:=0; end if; - if si>simax then simax:=si; end if; - else - m:=0; - end if; - end if; - end if; - end loop; - - --next unmatched character: si - if m=1 or m=-1 then ai:=aii; else ai:=0; si:=si_in; end if; --- --- si:=-simatch; --last good character before it went bad --- if si>simax then simatch:=-si; else simatch:=-simax; end if; --- - end; - - procedure regmatch(ai: OUT integer; si: INOUT integer; s: IN string; f: IN string) is - variable m1,m2,m3,m4: string(1 to 80); - begin - regmatch(ai, si, s, f, m1, m2, m3, m4); - end; - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; f: IN string; m1: OUT string) is - variable m2,m3,m4: string(1 to 80); - begin - regmatch(ai, si, s, f, m1, m2, m3, m4); - end; - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; f: IN string; m1,m2: OUT string) is - variable m3,m4: string(1 to 80); - begin - regmatch(ai, si, s, f, m1, m2, m3, m4); - end; - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; f: IN string; m1,m2,m3: OUT string) is - variable m4: string(1 to 80); - begin - regmatch(ai, si, s, f, m1, m2, m3, m4); - end; - - --conversion of scanf to sed - function sedscanf(s: IN string) return string is - variable i: integer:=0; - variable white: string(1 to 8):= "[ \t\n]*"; --zero or more white space - variable r: string(1 to 256); - begin - strcpy(r, NUL); - loop - i:=i+1; - if i>s'length then exit; end if; - if s(i)=NUL then exit; end if; - - if s(i)='%' then - i:=i+1; - if i>s'length then exit; end if; - if s(i)=NUL then exit; end if; - - case s(i) is - when 'x' => - strcat(r, white); strcat(r, "\(0[xX][0-9A-Fa-f][0-9A-Fa-f]*\|[0-9A-Fa-f][0-9A-Fa-f]*\)"); - when 'o' => - strcat(r, white); strcat(r, "\(0[0-7][0-7]*\)"); - when 'd' => - strcat(r, white); strcat(r, "\([0-9][0-9]*\)"); - when 's' => - strcat(r, white); strcat(r, "\([^ \t\n]*\)"); - when '%' => - strcat(r, "%"); - when others => - end case; - - elsif s(i)=' ' then strcat(r, white); - else - strcat(r, s(i)); - end if; - end loop; - return r; - end; ---------------------------------------------------------------------------------------------------------- --- end regexp_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- PACKAGE BODY stdio_h IS ---------------------------------------------------------------------------------------------------------- - TYPE pf_std_logic_vector_type IS array(std_ulogic) OF CHARACTER; - CONSTANT pf_std_logic_vector: pf_std_logic_vector_type - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - TYPE pf_hex_type IS array(0 to 15) OF CHARACTER; - CONSTANT pf_hex: pf_hex_type - := ('0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f'); - CONSTANT pf_hexx: pf_hex_type - := ('0','1','2','3','4','5','6','7','8','9','A','B','C','C','E','F'); - - TYPE pf_hex2_type IS array(0 to 15) of STRING(1 to 4); - CONSTANT pf_hex2: pf_hex2_type - := ("0000","0001","0010","0011","0100","0101","0110","0111", --fix 20030425 - "1000","1001","1010","1011","1100","1101","1110","1111"); --fix 20030425 - - - FUNCTION pf(x: IN bit) RETURN STRING IS - VARIABLE s: STRING(1 TO 1); - BEGIN - IF x='1' THEN s(1):='1'; ELSE s(1):='0'; END IF; RETURN s; - END pf; - - FUNCTION pf(x: IN BOOLEAN) RETURN STRING IS - VARIABLE s: STRING(1 TO 1); - BEGIN - IF x THEN s(1):='1'; ELSE s(1):='0'; END IF; RETURN s; - END pf; - - FUNCTION pf(x: IN CHARACTER) RETURN STRING IS - VARIABLE s: STRING(1 TO 1); - BEGIN - s(1):=x; RETURN s; - END pf; - - FUNCTION pf(x: IN std_ulogic) RETURN STRING IS - VARIABLE s: STRING(1 TO 1); - BEGIN - s(1):=pf_std_logic_vector(x); RETURN s; - END pf; - - FUNCTION pf(x: IN STRING) RETURN STRING IS - BEGIN - RETURN x; - END pf; - - FUNCTION pf(x: IN INTEGER) RETURN STRING IS - VARIABLE y: STRING(1 TO 128); - VARIABLE c: CHARACTER:='0'; --carry - VARIABLE a, b, i, n: INTEGER; --n:=bit length+sign bit - BEGIN - a:=x; IF a<0 THEN a:=-a; c:='1'; END IF; - n:=1; WHILE a/=0 LOOP a:=a/2; n:=n+1; END LOOP; - a:=x; IF n>y'HIGH THEN n:=y'HIGH; END IF; - FOR i IN n DOWNTO 1 LOOP --big endian - b:=a MOD 2; a:=a/2; - IF x<0 THEN --2's complement - IF b=0 THEN y(i):='1'; ELSE y(i):=c; c:='0'; END IF; - ELSE - IF b=0 THEN y(i):='0'; ELSE y(i):='1'; END IF; - END IF; - END LOOP; - ASSERT a=0 AND c='0' - REPORT "pf(x: IN INTEGER) bit length too small" SEVERITY WARNING; - RETURN y(1 TO n); --return minimum number of bits to descibe integer - END pf; - - FUNCTION sf(s: IN STRING) RETURN INTEGER IS - VARIABLE i, ax, n, p: INTEGER; VARIABLE nflag: BOOLEAN:=FALSE; - BEGIN - ax:=0; n:=0; p:=1; --IF f='u' THEN p:=0; ELSE p:=1; END IF; - FOR i IN 1 TO s'LENGTH LOOP - CASE s(i) IS - WHEN NUL => EXIT; WHEN ' '|HT => --ignore blanks - WHEN '1' => IF p=1 THEN p:=0; nflag:=TRUE; --begin 2's complement - ELSE - IF nflag THEN ax:=2*ax; ELSE ax:=2*ax+1; END IF; - END IF; - WHEN OTHERS => IF p=1 THEN p:=0; - ELSE - IF nflag THEN ax:=2*ax+1; ELSE ax:=2*ax; END IF; - END IF; - END CASE; - END LOOP; - IF nflag THEN ax:=ax+1; END IF; --2's complement ax:=(NOT ax)+1; - RETURN ax; - END sf; - - FUNCTION pf(x: IN REAL) RETURN STRING IS - VARIABLE s: LINE; VARIABLE i, n: INTEGER; VARIABLE y: STRING(1 TO 128); - BEGIN - y(1):='0'; n:=1; --assume default - write(s, x); --use internal function - IF s/=NULL THEN - IF s'LENGTH>0 THEN - i:=1; WHILE i<=s'LENGTH LOOP - IF i<=y'LENGTH THEN y(i):=s(i); n:=i; END IF; i:=i+1; - END LOOP; - END IF; - END IF; - DEALLOCATE(s); RETURN y(1 TO n); --wish list: return ieee bit string - END pf; - - FUNCTION pf(x: IN bit_vector) RETURN STRING IS - VARIABLE y: STRING(1 TO x'LENGTH); VARIABLE j: INTEGER:=1; - BEGIN - FOR i IN x'HIGH DOWNTO x'LOW LOOP - IF x(i)='1' THEN y(j):='1'; ELSE y(j):='0'; END IF; j:=j+1; - END LOOP; - RETURN y; - END pf; - - FUNCTION pf(x: IN std_ulogic_vector) RETURN STRING IS - VARIABLE y: STRING(1 TO x'LENGTH); VARIABLE j: INTEGER:=1; - BEGIN - FOR i IN x'HIGH DOWNTO x'LOW LOOP - y(j) := pf_std_logic_vector(x(i)); j:=j+1; - END LOOP; - RETURN y; - END pf; - - FUNCTION pf(x: IN std_logic_vector) RETURN STRING IS - VARIABLE y: STRING(1 TO x'LENGTH); VARIABLE j: INTEGER:=1; - BEGIN - FOR i IN x'HIGH DOWNTO x'LOW LOOP - y(j) := pf_std_logic_vector(x(i)); j:=j+1; - END LOOP; - RETURN y; - END pf; - - FUNCTION pf(x: IN time) RETURN STRING IS - BEGIN - RETURN pf(INTEGER(x / 1 ns)); - END pf; - - IMPURE FUNCTION fopen(filename: IN STRING; mode: IN STRING) RETURN CFILE IS - VARIABLE buf: LINE; - VARIABLE m: INTEGER:=0; - VARIABLE fid: CFILE:=0; - VARIABLE fmode: FILE_OPEN_KIND; --READ_MODE, WRITE_MODE, APPEND_MODE; - VARIABLE fstat: FILE_OPEN_STATUS:=NAME_ERROR; --OPEN_OK, STATUS_ERROR, NAME_ERROR, MODE_ERROR; - BEGIN - IF streamlock THEN --handle concurrent calls to fopen - write(buf, STRING'("fopen: streamlock")); writeline(OUTPUT, buf); - WHILE streamlock LOOP m:=0; END LOOP; --symphonyeda has bug, cannot have empty loop - END IF; - streamlock:=TRUE; - - FOR i IN mode'RANGE LOOP - CASE mode(i) IS - WHEN 'r' => fmode:=READ_MODE; m:=m+1; - WHEN 'w' => fmode:=WRITE_MODE; m:=m+1; - WHEN 'a' => fmode:=APPEND_MODE; m:=m+1; - WHEN NUL => EXIT; - WHEN OTHERS => m:=-1; EXIT; - END CASE; - END LOOP; - - IF m=1 THEN - IF strcmp(filename,"/dev/tty")=0 OR strcmp(filename,"CON")=0 THEN - CASE fmode IS --unix shell commands also use the dash, "-" - WHEN READ_MODE => fid:=stdin; fstat:=OPEN_OK; - WHEN WRITE_MODE => fid:=stdout;fstat:=OPEN_OK; - WHEN APPEND_MODE => fid:=stdout;fstat:=OPEN_OK; - WHEN OTHERS => fstat:=NAME_ERROR; - END CASE; - ELSIF strcmp(filename,"/dev/null")=0 OR strcmp(filename,"NUL")=0 THEN - fid:=stdnul; fstat:=OPEN_OK; - ELSE - fid:=0; m:=strlen(filename); - FOR i IN streambusy'RANGE LOOP - IF NOT streambusy(i) THEN fid:=i; EXIT; END IF; - END LOOP; - CASE fid IS - WHEN 4 => file_open(fstat, streamfile4, filename(1 TO m), fmode); - WHEN 5 => file_open(fstat, streamfile5, filename(1 TO m), fmode); - WHEN 6 => file_open(fstat, streamfile6, filename(1 TO m), fmode); - WHEN 7 => file_open(fstat, streamfile7, filename(1 TO m), fmode); - WHEN 8 => file_open(fstat, streamfile8, filename(1 TO m), fmode); - WHEN 9 => file_open(fstat, streamfile9, filename(1 TO m), fmode); - WHEN OTHERS => fstat:=NAME_ERROR; - END CASE; - END IF; - ELSE - fstat:=MODE_ERROR; - END IF; - - IF fstat=OPEN_OK THEN - streambusy(fid):=TRUE; - ELSE - CASE fid IS --totally unexpected: must do for fstat error - WHEN 4 => file_close(streamfile4); - WHEN 5 => file_close(streamfile5); - WHEN 6 => file_close(streamfile6); - WHEN 7 => file_close(streamfile7); - WHEN 8 => file_close(streamfile8); - WHEN 9 => file_close(streamfile9); - WHEN OTHERS => - END CASE; - fid:=0; - END IF; - streamiob(fid).fstat:=fstat; streamiob(fid).fmode:=fmode; - - streamlock:=FALSE; - --write(buf, STRING'("fopen: file=")); write(buf, filename); - --write(buf, STRING'(" fid=")); write(buf, fid); writeline(OUTPUT, buf); - RETURN fid; - END fopen; - - PROCEDURE fflush(stream: IN CFILE) IS - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fflush()/fclose(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF streamiob(stream).fstat=OPEN_OK AND streamiob(stream).buf/=NULL THEN - IF (streamiob(stream).fmode=WRITE_MODE - OR streamiob(stream).fmode=APPEND_MODE) THEN - CASE stream IS --buf'LENGTH==0 is a newline - WHEN stdout => writeline(output, streamiob(stream).buf); - WHEN 3 => --/dev/null - WHEN 4 => writeline(streamfile4, streamiob(stream).buf); - WHEN 5 => writeline(streamfile5, streamiob(stream).buf); - WHEN 6 => writeline(streamfile6, streamiob(stream).buf); - WHEN 7 => writeline(streamfile7, streamiob(stream).buf); - WHEN 8 => writeline(streamfile8, streamiob(stream).buf); - WHEN 9 => writeline(streamfile9, streamiob(stream).buf); - WHEN OTHERS => - END CASE; - DEALLOCATE(streamiob(stream).buf); - END IF; - END IF; - END fflush; - - PROCEDURE fclose(stream: IN CFILE) IS - BEGIN - fflush(stream); - ASSERT streamiob(stream).fstat=OPEN_OK AND streambusy(stream)=TRUE - REPORT "fclose(): CFILE stream id is already closed" SEVERITY FAILURE; - CASE stream IS - WHEN 4 => file_close(streamfile4); streambusy(stream):=FALSE; - WHEN 5 => file_close(streamfile5); streambusy(stream):=FALSE; - WHEN 6 => file_close(streamfile6); streambusy(stream):=FALSE; - WHEN 7 => file_close(streamfile7); streambusy(stream):=FALSE; - WHEN 8 => file_close(streamfile8); streambusy(stream):=FALSE; - WHEN 9 => file_close(streamfile9); streambusy(stream):=FALSE; - WHEN OTHERS => - END CASE; - END fclose; - - PROCEDURE fputc(c: IN CHARACTER; stream: IN CFILE) IS - VARIABLE fid: INTEGER; - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fputc(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF stream/=stdnul THEN - IF c=LF THEN fflush(stream); ELSE write(streamiob(stream).buf, c); END IF; - END IF; - END fputc; - - PROCEDURE fputs(s: IN STRING; stream: IN CFILE) IS - VARIABLE i: INTEGER; VARIABLE n: INTEGER:=strlen(s); - BEGIN --inline fputc code FOR simulator efficiency - IF stream/=stdnul THEN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fputs(): passed in bad CFILE stream id" SEVERITY FAILURE; - FOR i IN 1 TO n LOOP - IF s(i)=LF THEN write(streamiob(stream).buf, string'("")); fflush(stream); - ELSE write(streamiob(stream).buf, s(i)); END IF; - END LOOP; - END IF; - END fputs; - - PROCEDURE fputs(s: INOUT LINE; stream: IN CFILE) IS - VARIABLE i: INTEGER; VARIABLE n: INTEGER:=0; - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fputs(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF stream/=stdnul THEN - IF s/=NULL THEN n:=strlen(s.all); END IF; --avoids Null access value dereferenced - FOR i IN 1 TO n LOOP - IF s(i)=LF THEN write(streamiob(stream).buf, string'("")); fflush(stream); - ELSE write(streamiob(stream).buf, s(i)); - END IF; - END LOOP; - END IF; - DEALLOCATE(s); --same behavior as write(FILE, LINE); - END fputs; - - PROCEDURE putc(c: IN CHARACTER; stream: IN CFILE) IS - BEGIN - fputc(c, stream); - END putc; - - PROCEDURE putchar(c: IN CHARACTER) IS - BEGIN - fputc(c, stdout); - END putchar; - - PROCEDURE puts(s: IN STRING) IS - BEGIN - fputs(s, stdout); fputc(LF, stdout); - END puts; - - PROCEDURE puts(s: INOUT LINE) IS - BEGIN - fputs(s, stdout); fputc(LF, stdout); - END puts; - - IMPURE FUNCTION feof(stream: IN CFILE) RETURN BOOLEAN IS - VARIABLE eof: BOOLEAN:=TRUE; - BEGIN - IF stream>0 AND stream<=streamNFILE THEN - IF streamiob(stream).fstat=OPEN_OK THEN - CASE stream IS - WHEN stdin => eof:=ENDFILE(INPUT); - WHEN 4 => eof:=ENDFILE(streamfile4); - WHEN 5 => eof:=ENDFILE(streamfile5); - WHEN 6 => eof:=ENDFILE(streamfile6); - WHEN 7 => eof:=ENDFILE(streamfile7); - WHEN 8 => eof:=ENDFILE(streamfile8); - WHEN 9 => eof:=ENDFILE(streamfile9); - WHEN OTHERS => eof:=TRUE; - END CASE; - END IF; - END IF; - RETURN eof; - END feof; - - IMPURE FUNCTION fgetc(stream: IN CFILE) RETURN CHARACTER IS - VARIABLE more: BOOLEAN:=FALSE; VARIABLE c: CHARACTER:=NUL; - VARIABLE b: LINE; --workaround for SymphonyEDA 2.3#8 - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fgetc(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF stream>0 AND stream<=streamNFILE THEN - IF streamiob(stream).buf=NULL THEN more:=TRUE; - ELSE - b:=streamiob(stream).buf; IF b'LENGTH<=0 THEN more:=TRUE; END IF; - END IF; - IF more AND streamiob(stream).fstat=OPEN_OK THEN - more:=feof(stream); - IF NOT more THEN - CASE stream IS - WHEN stdin => readline(input, streamiob(stream).buf); - WHEN 4 => readline(streamfile4, streamiob(stream).buf); - WHEN 5 => readline(streamfile5, streamiob(stream).buf); - WHEN 6 => readline(streamfile6, streamiob(stream).buf); - WHEN 7 => readline(streamfile7, streamiob(stream).buf); - WHEN 8 => readline(streamfile8, streamiob(stream).buf); - WHEN 9 => readline(streamfile9, streamiob(stream).buf); - WHEN OTHERS => - END CASE; - write(streamiob(stream).buf, LF); - END IF; - END IF; - - IF streamiob(stream).buf/=NULL THEN - b:=streamiob(stream).buf; - IF b'LENGTH>0 THEN read(streamiob(stream).buf, c); END IF; - END IF; - END IF; - RETURN c; - END fgetc; - - --The fgets() function reads CHARACTERs from the stream into the STRING s, - -- until n-1 bytes are read, - -- or a newline CHARACTER IS read and transferred to s, - -- or an end-of-file condition IS encountered. - -- The STRING IS then terminated with a NULL byte. - -- - PROCEDURE fgets(s: OUT STRING; n: IN INTEGER; stream: IN CFILE) IS - VARIABLE i: INTEGER:=1; VARIABLE c: CHARACTER; - BEGIN - WHILE i0 AND stream<=streamNFILE - REPORT "ungetc(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF stream/=stdnul THEN - write(t, c); - IF streamiob(stream).buf/=NULL THEN - b:=streamiob(stream).buf; - IF b'LENGTH>0 THEN write(t, streamiob(stream).buf.all); END IF; - END IF; - DEALLOCATE(streamiob(stream).buf); - streamiob(stream).buf:=t; --copy pointer - END IF; - END ungetc; - - PROCEDURE sbufprintf(fi: INOUT INTEGER; sbuf: INOUT LINE; stream: IN CFILE; - fmt: IN STRING; s: IN STRING) IS - - CONSTANT zero: CHARACTER:='0'; - VARIABLE c, d, f: CHARACTER; - VARIABLE sn, n, m, p, z: INTEGER; - VARIABLE ai, i, j, ax: INTEGER; - VARIABLE fj: INTEGER:=1; - VARIABLE lflag, aflag, zflag: BOOLEAN; - VARIABLE nflag, pflag, sflag: BOOLEAN; - VARIABLE fmtflag: BOOLEAN:=FALSE; - VARIABLE m1, m2, m3, m4: STRING(1 to 256); - VARIABLE w, buf, wbuf: LINE; - VARIABLE wflag: BOOLEAN:=FALSE; - BEGIN - IF stream/=stdnul THEN - ASSERT stream=-1 OR (sbuf=NULL AND stream>0 AND stream<=streamNFILE) - REPORT "fprintf/printf/sprintf error: passed in bad CFILE stream id or string" - SEVERITY FAILURE; - LOOP - fj:=fi; - regmatch(ai, fi, fmt, - "^$|\\n|([^%\\][^%\\]*)|%([^scdioxXufeEgGpn%\\]*)(.)|\\0(\\[0-7][0-7]?[0-7]?)|\\(.)", - m1, m2); - - - CASE ai IS --preprocess STRING - WHEN 5 => ai:=3; - ax:=0; - FOR i in 1 to m1'LENGTH LOOP - ax:=ax*8; - CASE m1(i) IS - WHEN '0'=> ax:=ax+0; when '1'=> ax:=ax+1; - WHEN '2'=> ax:=ax+2; when '3'=> ax:=ax+3; - WHEN '4'=> ax:=ax+4; when '5'=> ax:=ax+5; - WHEN '6'=> ax:=ax+6; when '7'=> ax:=ax+7; - WHEN others => - END CASE; - END LOOP; - m1(1):=CHARACTER'val(ax); - - WHEN 6 => ai:=3; - CASE m1(1) IS - WHEN 'a'=> m1(1):=BEL; when 'b'=> m1(1):=BS; - WHEN 'f'=> m1(1):=FF; when 'n'=> m1(1):=LF; - WHEN 'r'=> m1(1):=CR; when 't'=> m1(1):=HT; - WHEN 'v'=> m1(1):=VT; when others => - END CASE; - WHEN others => - END CASE; - - CASE ai IS - WHEN 1 => EXIT; - WHEN 2 => write(buf, LF); IF stream>0 THEN fputs(buf, stream); END IF; - WHEN 3 => write(buf, m1(1 to strlen(m1))); - WHEN 4 => - if fmtflag then fi:=fj; EXIT; end if; - f:=m2(1); m1(1):=NUL; m2(1):=NUL; m3(1):=NUL; m4(1):=NUL; - regmatch(ai, fj, fmt, - "%([ 0#+-]*)([0-9]*)\.?([0-9]*).", m1, m2, m3, m4); - - --. - lflag:=FALSE; aflag:=FALSE; - nflag:=FALSE; pflag:=FALSE; sflag:=FALSE; zflag:=FALSE; - - FOR i in 1 to m1'LENGTH LOOP - if m1(i)='-' then lflag:=TRUE; end if; - if m1(i)='+' then pflag:=TRUE; end if; - if m1(i)=' ' then sflag:=TRUE; end if; - if m1(i)='0' then zflag:=TRUE; end if; - if m1(i)='#' then aflag:=TRUE; end if; --ignored in decimal - if m1(i)=NUL then EXIT; end if; - END LOOP; - if m2(1)=NUL then m:=0; else m:=atoi(m2); end if; - - - IF f='x' OR f='o' OR f='X' THEN --unlimited STRING LENGTH - z:=0; sn:=s'LENGTH; ax:=0; j:=1; n:=0; - FOR i IN 1 TO s'LENGTH LOOP --skip leading zeros - IF z=0 AND s(i)='1' THEN z:=i; END IF; - IF s(i)=NUL THEN EXIT; END IF; sn:=i; - END LOOP; - IF z/=0 THEN - IF f='o' THEN p:=8; ELSE p:=16; END IF; --fix 20030425 - FOR i IN sn DOWNTO z LOOP --fix 20040528 big endian - CASE s(i) IS - WHEN ' '|HT => --ignore white space - WHEN '1' => ax:=j+ax; j:=2*j; - WHEN OTHERS => j:=2*j; --0, X, H, L, U, ... - END CASE; - IF j=p THEN - IF f='x' THEN write(w, pf_hex(ax)); - ELSE write(w, pf_hexx(ax)); END IF; --fix 20040528 - ax:=0; j:=1; n:=n+1; - END IF; - END LOOP; - END IF; - IF ax>0 OR n=0 THEN --residue - IF f='x' THEN write(w, pf_hex(ax)); ELSE write(w, pf_hexx(ax)); END IF; - n:=n+1; - END IF; - - IF zflag AND NOT lflag THEN - p:=0; IF aflag THEN IF f='o' THEN p:=1; ELSE p:=2; END IF; END IF; - WHILE n EXIT; WHEN ' '|HT => --ignore blanks - WHEN '1' => IF p=1 THEN p:=0; nflag:=TRUE; --begin 2's complement - ELSE - IF nflag THEN ax:=2*ax; ELSE ax:=2*ax+1; END IF; - END IF; - WHEN OTHERS => IF p=1 THEN p:=0; - ELSE - IF nflag THEN ax:=2*ax+1; ELSE ax:=2*ax; END IF; - END IF; - END CASE; - END LOOP; - IF nflag THEN ax:=ax+1; END IF; --2's complement ax:=(NOT ax)+1; - - LOOP --convert to base 10 - j:=ax MOD 10; write(w, pf_hex(j)); n:=n+1; - ax:=ax/10; IF ax=0 THEN EXIT; END IF; - END LOOP; - - IF zflag AND NOT lflag THEN - WHILE n - END CASE; - DEALLOCATE(w); wflag:=FALSE; - END LOOP; - IF stream<0 THEN sbuf:=buf; - ELSE - fputs(buf, stream); DEALLOCATE(buf); DEALLOCATE(sbuf); - END IF; - END IF; --NOT stdnul - END sbufprintf; - - PROCEDURE fprintf2(buf: INOUT LINE; - stream: IN CFILE; - format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : in STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: in STRING := " " - ) IS - VARIABLE fi: INTEGER:=1; - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "sprintf/fprintf: passed in bad CFILE stream id" SEVERITY FAILURE; - if stream/=stdnul THEN - sbufprintf(fi, buf, stream, format, a1); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a2); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a3); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a4); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a5); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a6); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a7); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a8); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a9); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a10); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a11); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a12); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a13); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a14); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a15); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a16); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; - END IF; - END fprintf2; - - PROCEDURE fprintf(stream: IN CFILE; - format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : in STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: in STRING := " " - ) IS - BEGIN - fprintf2(streamnulbuf, stream, format, a1, a2, a3, a4, a5, a6, a7, a8, - a9, a10, a11, a12, a13, a14, a15, a16); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; - format: IN STRING; - a1: IN std_logic_vector; - a2, a3, a4, a5, a6, a7, a8: IN std_logic_vector := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN std_logic_vector := "U" - ) IS - BEGIN - fprintf2(streamnulbuf, stream, format, pf(a1),pf(a2),pf(a3),pf(a4),pf(a5),pf(a6),pf(a7),pf(a8), - pf(a9),pf(a10),pf(a11),pf(a12),pf(a13),pf(a14),pf(a15),pf(a16)); - END fprintf; - - PROCEDURE printf( format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8: IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " " - ) IS - begin - fprintf2(streamnulbuf, stdout, format, a1,a2,a3,a4,a5,a6,a7,a8, - a9,a10,a11,a12,a13,a14,a15,a16); - END printf; - - PROCEDURE printf( format: IN STRING; - a1: IN std_logic_vector; - a2, a3, a4, a5, a6, a7, a8: IN std_logic_vector := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN std_logic_vector := "U" - ) IS - begin - fprintf2(streamnulbuf, stdout, format, pf(a1),pf(a2),pf(a3),pf(a4),pf(a5),pf(a6),pf(a7),pf(a8), - pf(a9),pf(a10),pf(a11),pf(a12),pf(a13),pf(a14),pf(a15),pf(a16)); - END printf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN STRING; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; - BEGIN - IF a1/=NULL THEN sbufprintf(fi, streamnulbuf, stream, format, a1.all); - ELSE sbufprintf(fi, streamnulbuf, stream, format, STRING'("")); END IF; - END fprintf; - - PROCEDURE printf( format: IN STRING; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; - BEGIN - IF a1/=NULL THEN sbufprintf(fi, streamnulbuf, stdout, format, a1.all); - ELSE sbufprintf(fi, streamnulbuf, stdout, format, STRING'("")); END IF; - END printf; - - PROCEDURE sprintf(s: INOUT LINE; format: IN STRING; --Appends to LINE variable s by default - a1, a2, a3, a4, a5, a6, a7, a8 : in STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: in STRING := " " - ) IS - BEGIN - fprintf2(s, -1, format, a1, a2, a3, a4, a5, a6, a7, a8, - a9, a10, a11, a12, a13, a14, a15, a16); - END sprintf; - - PROCEDURE sprintf(s: INOUT STRING; format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : in STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: in STRING := " " - ) IS - variable W: LINE; variable i: INTEGER; - BEGIN - fprintf2(W, -1, format, a1, a2, a3, a4, a5, a6, a7, a8, - a9, a10, a11, a12, a13, a14, a15, a16); - - i:=1; WHILE i<=w'LENGTH LOOP - if i=0 THEN c:=fgetc(stream); - ELSIF buf=NULL THEN c:=NUL; - ELSIF buf'LENGTH<=0 THEN c:=NUL; - ELSE read(buf, c); - END IF; - END sfgetc; - - PROCEDURE sbufscanf(fi: INOUT INTEGER; sbuf: INOUT LINE; stream: IN CFILE; - fmt: IN STRING; s: INOUT LINE) IS - VARIABLE xbuf: LINE; - VARIABLE c, d, f: CHARACTER; - VARIABLE n, m, ms: INTEGER; - VARIABLE ai, i, j, ax: INTEGER; - VARIABLE fj: INTEGER:=1; - VARIABLE sflag, mflag: BOOLEAN; - VARIABLE fmtflag: BOOLEAN:=FALSE; - VARIABLE m1, m2, m3, m4:STRING(1 to 256); - BEGIN - IF stream/=stdnul THEN - ASSERT stream=-1 OR (sbuf=NULL AND stream>0 AND stream<=streamNFILE) - REPORT "fscanf/scanf/sscanf error: passed in bad CFILE stream id or string" - SEVERITY FAILURE; - sfgetc(c, stream, sbuf); - LOOP - fj:=fi; m1(1):=NUL; m2(1):=NUL; - regmatch(ai, fi, fmt, - "^$|%%|([^%\\])|%([^scdioxXufeEgGpn%\\]*)(.)|\\0(\\[0-7][0-7]?[0-7]?)|\\(.)", - m1, m2); - - - CASE ai IS - WHEN 2 => ai:=2; m1(1):='%'; m1(2):=NUL; - - WHEN 5 => ai:=2; - ax:=0; - FOR i in 1 to m1'LENGTH LOOP - ax:=ax*8; - CASE m1(i) IS - WHEN '0'=> ax:=ax+0; when '1'=> ax:=ax+1; - WHEN '2'=> ax:=ax+2; when '3'=> ax:=ax+3; - WHEN '4'=> ax:=ax+4; when '5'=> ax:=ax+5; - WHEN '6'=> ax:=ax+6; when '7'=> ax:=ax+7; - WHEN others => - END CASE; - END LOOP; - m1(1):=CHARACTER'val(ax); m1(2):=NUL; - - WHEN 6 => ai:=2; - CASE m1(1) IS - WHEN 'a'=> m1(1):=BEL; when 'b'=> m1(1):=BS; - WHEN 'f'=> m1(1):=FF; when 'n'=> m1(1):=LF; - WHEN 'r'=> m1(1):=CR; when 't'=> m1(1):=HT; - WHEN 'v'=> m1(1):=VT; when others => - END CASE; - m1(2):=NUL; - WHEN others => - END CASE; - - CASE ai IS - WHEN 1 => EXIT; - WHEN 3 => - if c/=m1(1) then EXIT; end if; - WHILE c=' ' LOOP - sfgetc(c, stream, sbuf); - END LOOP; - WHEN 4 => - if fmtflag then fi:=fj; EXIT; end if; - - f:=m2(1); m1(1):=NUL; m2(1):=NUL; m3(1):=NUL; m4(1):=NUL; - regmatch(ai, fj, fmt, "%([*]*)([0-9]*)([lLh]).", m1, m2, m3, m4); - - -- - sflag:=FALSE; - FOR i in 1 to m1'LENGTH LOOP - if m1(i)='*' then sflag:=TRUE; end if; --assignment suppression - if m1(i)=NUL then EXIT; end if; - END LOOP; - if m2(1)=NUL then m:=0; else m:=atoi(m2); end if; - - - if f/='c' then - WHILE c=' ' OR c=LF OR c=HT OR c=CR OR c=VT LOOP - sfgetc(c, stream, sbuf); - END LOOP; - end if; - - IF f='x' OR f='o' OR f='d' THEN - if f='x' or f='o' then write(s, STRING'("0")); end if; --20040529, sign bit - - i:=0; ax:=0; ms:=1; - LOOP - if m/=0 AND i>=m then EXIT; end if; - if i=0 and c='+' then ms:=1; - elsif i=0 and c='-' then ms:=-1; - else - CASE c IS - WHEN '0' => n:=0; when '1' => n:=1; - WHEN '2' => n:=2; when '3' => n:=3; - WHEN '4' => n:=4; when '5' => n:=5; - WHEN '6' => n:=6; when '7' => n:=7; - WHEN '8' => n:=8; when '9' => n:=9; - WHEN 'a'|'A'=> n:=10; when 'b'|'B'=> n:=11; - WHEN 'c'|'C'=> n:=12; when 'd'|'D'=> n:=13; - WHEN 'e'|'E'=> n:=14; when 'f'|'F'=> n:=15; - WHEN others => EXIT; - END CASE; - if f='d' then - if n>9 then EXIT; else ax:=ax*10+n; end if; - else - m1(1 to 4):=pf_hex2(n); - if f='o' and n>7 then EXIT; end if; - if f='o' and not sflag then write(s, m1(2 to 4)); end if; - if f='x' and not sflag then write(s, m1(1 to 4)); end if; - end if; - end if; - i:=i+1; sfgetc(c, stream, sbuf); - END LOOP; - - IF f='d' THEN - strcat(s, pf(ms*ax)); - --m1:=pf(ms*ax); n:=strlen(m1); write(s, m1(1 to n)); - --m1'LENGTH /= pf()'LENGTH - --mismatched array sizes are a problem in vhdl - --strcat, strcpy solves the mismatched array size problem - END IF; - END IF; - - --if f='%' then write(buf, '%'); end if; - - IF f='s' OR f='f' THEN - i:=0; - WHILE c/=' ' AND c/=LF AND c/=HT AND c/=CR AND c/=VT AND c/=NUL LOOP - if m/=0 AND i>=m then EXIT; end if; - if not sflag then write(s, c); end if; - i:=i+1; sfgetc(c, stream, sbuf); - END LOOP; - - END IF; - if c/='%' AND not sflag then fmtflag:=TRUE; end if; - WHEN others => - END CASE; - END LOOP; - IF stream=-1 THEN --put CHARACTER back into stream - write(xbuf, c); write(xbuf, sbuf.all); - DEALLOCATE(sbuf); sbuf:=xbuf; - ELSE - ungetc(c, stream); - END IF; - END IF; --NOT stdnul - END sbufscanf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT REAL) IS - BEGIN - if buf/=NULL then if buf'LENGTH>0 then read(buf, s); end if; end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT INTEGER) IS - BEGIN - if buf/=NULL then if buf'LENGTH>0 then s:=sf(buf.all); end if; end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT time) IS - BEGIN - if buf/=NULL then if buf'LENGTH>0 then s:=sf(buf.all)*1 ns; end if; end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT CHARACTER) IS - BEGIN - if buf/=NULL then if buf'LENGTH>0 then s:=buf(1); end if; end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT STRING) IS - VARIABLE i: INTEGER:=1; - BEGIN - IF buf/=NULL THEN - WHILE i<=buf'LENGTH LOOP - IF i0 then if buf(1)='1' then s:='1'; else s:='0'; end if; end if; - end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT BOOLEAN) IS - BEGIN - IF buf/=NULL THEN - IF buf'LENGTH>0 THEN IF buf(1)='1' THEN s:=TRUE; ELSE s:=FALSE; END IF; END IF; - END IF; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT bit_vector) IS - VARIABLE i, j: INTEGER; VARIABLE b: BIT:='0'; - BEGIN - IF buf/=NULL THEN --scanf will not alter unread variables - j:=buf'HIGH; - FOR i IN s'LOW TO s'HIGH LOOP - IF j>=buf'LOW THEN IF buf(j)='1' THEN b:='1'; END IF; j:=j-1; END IF; - s(i):=b; --last b will be for signed extention - END LOOP; - DEALLOCATE(buf); - END IF; - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT std_logic) IS - BEGIN - IF buf/=NULL THEN - IF buf'LENGTH>0 THEN - CASE buf(1) IS - WHEN '1' => s:='1'; - WHEN '0' => s:='0'; - WHEN '-' => s:='-'; - WHEN 'X'|'x'=> s:='X'; - WHEN 'Z'|'z'=> s:='Z'; - WHEN 'H'|'h'=> s:='H'; - WHEN 'L'|'l'=> s:='L'; - WHEN 'W'|'w'=> s:='W'; - WHEN others => s:='U'; - END CASE; - END IF; - END IF; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT std_logic_vector) IS - VARIABLE i, j: INTEGER; VARIABLE b: CHARACTER:='0'; --signed extention bit - BEGIN - IF buf/=NULL THEN --scanf will not alter unread variables - j:=buf'HIGH; - FOR i IN s'LOW TO s'HIGH LOOP - IF j>=buf'LOW THEN b:=buf(j); j:=j-1; END IF; - CASE b IS - WHEN '1' => s(i):='1'; - WHEN '0' => s(i):='0'; - WHEN '-' => s(i):='-'; - WHEN 'X'|'x'=> s(i):='X'; - WHEN 'Z'|'z'=> s(i):='Z'; - WHEN 'H'|'h'=> s(i):='H'; - WHEN 'L'|'l'=> s(i):='L'; - WHEN 'W'|'w'=> s(i):='W'; - WHEN others => s(i):='U'; - END CASE; - END LOOP; - DEALLOCATE(buf); - END IF; - END pf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, a1); - END fscanf; - - PROCEDURE scanf(format: IN string; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, a1); - END scanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, a1); deallocate(w); - END sscanf; - - PROCEDURE printf(format: IN string; a1: string) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: integer) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: std_logic) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: std_logic_vector) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: boolean) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: bit) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: bit_vector) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: time) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: real) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: integer) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: std_logic) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: boolean) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: bit) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: bit_vector) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: time) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: real) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE scanf(format: IN string; a1: INOUT string) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT integer) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT std_logic) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT std_logic_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT boolean) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT bit) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT bit_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT time) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT real) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT string) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT integer) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT std_logic) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT std_logic_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT boolean) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT bit) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT bit_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT time) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT real) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT string) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT integer) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT std_logic) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT std_logic_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT boolean) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT bit) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT bit_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT time) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT real) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; ---------------------------------------------------------------------------------------------------------- --- end stdio_h; ---------------------------------------------------------------------------------------------------------- - -end vhdl_c_pkg_tb; \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/component.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/component.xml new file mode 100644 index 0000000..23e8113 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/component.xml @@ -0,0 +1,915 @@ + + + xilinx.com + module_ref + axi3_slave_verif + 1.0 + + + S_AXI + + + + + + + + + AWADDR + + + S_AXI_AWADDR + + + + + AWLEN + + + S_AXI_AWLEN + + + + + AWSIZE + + + S_AXI_AWSIZE + + + + + AWBURST + + + S_AXI_AWBURST + + + + + AWVALID + + + S_AXI_AWVALID + + + + + AWREADY + + + S_AXI_AWREADY + + + + + WDATA + + + S_AXI_WDATA + + + + + WSTRB + + + S_AXI_WSTRB + + + + + WLAST + + + S_AXI_WLAST + + + + + WVALID + + + S_AXI_WVALID + + + + + WREADY + + + S_AXI_WREADY + + + + + BRESP + + + S_AXI_BRESP + + + + + BVALID + + + S_AXI_BVALID + + + + + BREADY + + + S_AXI_BREADY + + + + + ARID + + + S_AXI_ARID + + + + + ARADDR + + + S_AXI_ARADDR + + + + + ARLEN + + + S_AXI_ARLEN + + + + + ARSIZE + + + S_AXI_ARSIZE + + + + + ARBURST + + + S_AXI_ARBURST + + + + + ARVALID + + + S_AXI_ARVALID + + + + + ARREADY + + + S_AXI_ARREADY + + + + + RID + + + S_AXI_RID + + + + + RDATA + + + S_AXI_RDATA + + + + + RRESP + + + S_AXI_RRESP + + + + + RLAST + + + S_AXI_RLAST + + + + + RVALID + + + S_AXI_RVALID + + + + + RREADY + + + S_AXI_RREADY + + + + + + RESETN + + + + + + + RST + + + RESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + CLK + + + + + + + CLK + + + CLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + RESETN + + + + + + + S_AXI + S_AXI + + reg0 + reg0 + 0x0 + 0x100000000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axi3_slave_verif + + + viewChecksum + 6d6387c1 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axi3_slave_verif + + + viewChecksum + 6d6387c1 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + + + CLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + RESETN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARID + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_ARBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + S_AXI_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_AWLEN + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_AWSIZE + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_AWBURST + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + S_AXI_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + S_AXI_WLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXI_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DWIDTH + Dwidth + 32 + + + IDWIDTH + Idwidth + 1 + + + MAX_BURSTLEN + Max Burstlen + 16 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_xpgui_view_fileset + + xgui/axi3_slave_verif_v1_0.tcl + tclSource + CHECKSUM_dc83b24a + XGUI_VERSION_2 + + + + xilinx.com:module_ref:axi3_slave_verif:1.0 + + + DWIDTH + Dwidth + 32 + + + IDWIDTH + Idwidth + 1 + + + MAX_BURSTLEN + Max Burstlen + 16 + + + Component_Name + axi3_slave_verif_v1_0 + + + + + + zynq + + + /UserIP + + axi3_slave_verif_v1_0 + level_1 + module_ref + + IPI + + 1 + 2025-02-01T20:40:20Z + + + 2023.1 + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/xgui/axi3_slave_verif_v1_0.tcl b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/xgui/axi3_slave_verif_v1_0.tcl new file mode 100644 index 0000000..3f2fcb6 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/xgui/axi3_slave_verif_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "IDWIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "MAX_BURSTLEN" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } { + # Procedure called to update DWIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } { + # Procedure called to validate DWIDTH + return true +} + +proc update_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } { + # Procedure called to update IDWIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } { + # Procedure called to validate IDWIDTH + return true +} + +proc update_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } { + # Procedure called to update MAX_BURSTLEN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } { + # Procedure called to validate MAX_BURSTLEN + return true +} + + +proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH} +} + +proc update_MODELPARAM_VALUE.IDWIDTH { MODELPARAM_VALUE.IDWIDTH PARAM_VALUE.IDWIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IDWIDTH}] ${MODELPARAM_VALUE.IDWIDTH} +} + +proc update_MODELPARAM_VALUE.MAX_BURSTLEN { MODELPARAM_VALUE.MAX_BURSTLEN PARAM_VALUE.MAX_BURSTLEN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MAX_BURSTLEN}] ${MODELPARAM_VALUE.MAX_BURSTLEN} +} + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml index 6a54aca..22d0c8d 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml @@ -145,7 +145,7 @@ viewChecksum - 14047e48 + b45c4280 @@ -158,7 +158,7 @@ viewChecksum - 14047e48 + b45c4280 @@ -395,7 +395,7 @@ IPI 1 - 2025-02-01T18:35:25Z + 2025-02-01T19:31:07Z 2023.1 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml index e88bcb5..711340c 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml @@ -595,7 +595,7 @@ viewChecksum - f22c6690 + ba1cd223 @@ -608,7 +608,7 @@ viewChecksum - f22c6690 + ba1cd223 @@ -682,6 +682,40 @@ + + FIFO_NUM_FREE + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + FIFO_NUM_AVAIL + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + S_AXIL_AWADDR @@ -1668,6 +1702,21 @@ Max Burstlen 16 + + FIFO_AWIDTH + Fifo Awidth + 8 + + + polynomial_default + Polynomial Default + 0x04C11DB7 + + + initial_value_default + Initial Value Default + 0x00000000 + @@ -1683,7 +1732,7 @@ xgui/axis_dma_v1_0.tcl tclSource - CHECKSUM_dc83b24a + CHECKSUM_47a147b5 XGUI_VERSION_2 @@ -1705,6 +1754,21 @@ Max Burstlen 16 + + FIFO_AWIDTH + Fifo Awidth + 8 + + + polynomial_default + Polynomial Default + 0x04C11DB7 + + + initial_value_default + Initial Value Default + 0x00000000 + Component_Name axis_dma_v1_0 @@ -1725,7 +1789,7 @@ IPI 1 - 2025-01-31T17:03:28Z + 2025-02-01T23:59:34Z 2023.1 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl index 3f2fcb6..fabd8c1 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl @@ -4,8 +4,11 @@ proc init_gui { IPINST } { #Adding Page set Page_0 [ipgui::add_page $IPINST -name "Page 0"] ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "FIFO_AWIDTH" -parent ${Page_0} ipgui::add_param $IPINST -name "IDWIDTH" -parent ${Page_0} ipgui::add_param $IPINST -name "MAX_BURSTLEN" -parent ${Page_0} + ipgui::add_param $IPINST -name "initial_value_default" -parent ${Page_0} + ipgui::add_param $IPINST -name "polynomial_default" -parent ${Page_0} } @@ -19,6 +22,15 @@ proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } { return true } +proc update_PARAM_VALUE.FIFO_AWIDTH { PARAM_VALUE.FIFO_AWIDTH } { + # Procedure called to update FIFO_AWIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FIFO_AWIDTH { PARAM_VALUE.FIFO_AWIDTH } { + # Procedure called to validate FIFO_AWIDTH + return true +} + proc update_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } { # Procedure called to update IDWIDTH when any of the dependent parameters in the arguments change } @@ -37,6 +49,24 @@ proc validate_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } { return true } +proc update_PARAM_VALUE.initial_value_default { PARAM_VALUE.initial_value_default } { + # Procedure called to update initial_value_default when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.initial_value_default { PARAM_VALUE.initial_value_default } { + # Procedure called to validate initial_value_default + return true +} + +proc update_PARAM_VALUE.polynomial_default { PARAM_VALUE.polynomial_default } { + # Procedure called to update polynomial_default when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.polynomial_default { PARAM_VALUE.polynomial_default } { + # Procedure called to validate polynomial_default + return true +} + proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } { # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value @@ -53,3 +83,18 @@ proc update_MODELPARAM_VALUE.MAX_BURSTLEN { MODELPARAM_VALUE.MAX_BURSTLEN PARAM_ set_property value [get_property value ${PARAM_VALUE.MAX_BURSTLEN}] ${MODELPARAM_VALUE.MAX_BURSTLEN} } +proc update_MODELPARAM_VALUE.FIFO_AWIDTH { MODELPARAM_VALUE.FIFO_AWIDTH PARAM_VALUE.FIFO_AWIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FIFO_AWIDTH}] ${MODELPARAM_VALUE.FIFO_AWIDTH} +} + +proc update_MODELPARAM_VALUE.polynomial_default { MODELPARAM_VALUE.polynomial_default PARAM_VALUE.polynomial_default } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.polynomial_default}] ${MODELPARAM_VALUE.polynomial_default} +} + +proc update_MODELPARAM_VALUE.initial_value_default { MODELPARAM_VALUE.initial_value_default PARAM_VALUE.initial_value_default } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.initial_value_default}] ${MODELPARAM_VALUE.initial_value_default} +} + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/hdl/test_1_wrapper.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/hdl/test_1_wrapper.vhd deleted file mode 100644 index 55b181c..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/hdl/test_1_wrapper.vhd +++ /dev/null @@ -1,24 +0,0 @@ ---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- ---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Sat Feb 1 18:39:19 2025 ---Host : BiermannSurface running 64-bit major release (build 9200) ---Command : generate_target test_1_wrapper.bd ---Design : test_1_wrapper ---Purpose : IP block netlist ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity test_1_wrapper is -end test_1_wrapper; - -architecture STRUCTURE of test_1_wrapper is - component test_1 is - end component test_1; -begin -test_1_i: component test_1 - ; -end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0/test_1_axis_crc_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0/test_1_axis_crc_0_0.xml deleted file mode 100644 index b40326a..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0/test_1_axis_crc_0_0.xml +++ /dev/null @@ -1,669 +0,0 @@ - - - xilinx.com - customized_ip - test_1_axis_crc_0_0 - 1.0 - - - M_AXIS - - - - - - - TDATA - - - M_AXIS_TDATA - - - - - TLAST - - - M_AXIS_TLAST - - - - - TVALID - - - M_AXIS_TVALID - - - - - TREADY - - - M_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXIS - - - - - - - TDATA - - - S_AXIS_TDATA - - - - - TLAST - - - S_AXIS_TLAST - - - - - TVALID - - - S_AXIS_TVALID - - - - - TREADY - - - S_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - RESETN - - - - - - - RST - - - RESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - CLK - - - - - - - CLK - - - CLK - - - - - - ASSOCIATED_BUSIF - M_AXIS:S_AXIS - - - ASSOCIATED_RESET - RESETN - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - CLK - - in - - - std_logic - dummy_view - - - - - - RESETN - - in - - - std_logic - dummy_view - - - - - - initial_value - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - polynomial - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - S_AXIS_TVALID - - in - - - std_logic - dummy_view - - - - - - S_AXIS_TDATA - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - S_AXIS_TLAST - - in - - - std_logic - dummy_view - - - - 0x0 - - - - - S_AXIS_TREADY - - out - - - std_logic - dummy_view - - - - - - M_AXIS_TVALID - - out - - - std_logic - dummy_view - - - - - - M_AXIS_TDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - M_AXIS_TLAST - - out - - - std_logic - dummy_view - - - - - - M_AXIS_TREADY - - in - - - std_logic - dummy_view - - - - 1 - - - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - xilinx.com:module_ref:axis_crc:1.0 - - - Component_Name - test_1_axis_crc_0_0 - - - - - axis_crc_v1_0 - module_ref - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2023.1 - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0/sim/test_1_axis_numeric_master_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0/sim/test_1_axis_numeric_master_0_0.vhd deleted file mode 100644 index c2e834f..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0/sim/test_1_axis_numeric_master_0_0.vhd +++ /dev/null @@ -1,196 +0,0 @@ --- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of AMD and is protected under U.S. and international copyright --- and other intellectual property laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- AMD, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) AMD shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or AMD had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- AMD products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of AMD products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:user:axis_numeric_master_slave_simmodel:1.0 --- IP Revision: 18 - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY test_1_axis_numeric_master_0_0 IS - PORT ( - CLK : OUT STD_LOGIC; - RESETN : OUT STD_LOGIC; - M1_AXIS_TVALID : OUT STD_LOGIC; - M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M1_AXIS_TREADY : IN STD_LOGIC; - M1_AXIS_TLAST : OUT STD_LOGIC; - M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - S_AXIS_TVALID : IN STD_LOGIC; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_TREADY : OUT STD_LOGIC; - S_AXIS_TLAST : IN STD_LOGIC; - S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) - ); -END test_1_axis_numeric_master_0_0; - -ARCHITECTURE test_1_axis_numeric_master_0_0_arch OF test_1_axis_numeric_master_0_0 IS - ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; - ATTRIBUTE DowngradeIPIdentifiedWarnings OF test_1_axis_numeric_master_0_0_arch: ARCHITECTURE IS "yes"; - COMPONENT axis_numeric_master_slave_simmodel IS - GENERIC ( - HAS_CLOCK_GENERATOR : BOOLEAN; - CLOCK_PERIOD_NS : INTEGER; - HAS_RESET_GENERATOR : BOOLEAN; - RESET_ACTIVE_CYCLES : INTEGER; - HAS_MASTER1 : BOOLEAN; - MASTER1_DATA_WIDTH : INTEGER; - MASTER1_RANDOM_VALID : BOOLEAN; - MASTER1_HAS_LAST : BOOLEAN; - MASTER1_LAST_PERIOD : INTEGER; - MASTER1_HAS_USER : BOOLEAN; - MASTER1_USER_PERIOD : INTEGER; - HAS_MASTER2 : BOOLEAN; - MASTER2_DATA_WIDTH : INTEGER; - MASTER2_RANDOM_VALID : BOOLEAN; - MASTER2_HAS_LAST : BOOLEAN; - MASTER2_LAST_PERIOD : INTEGER; - MASTER2_HAS_USER : BOOLEAN; - MASTER2_USER_PERIOD : INTEGER; - HAS_SLAVE : BOOLEAN; - SLAVE_DATA_WIDTH : INTEGER; - SLAVE_RANDOM_READY : BOOLEAN; - SLAVE_HAS_LAST : BOOLEAN; - SLAVE_HAS_USER : BOOLEAN; - SLAVE_WAIT_FOR_SOF : BOOLEAN; - FILE_NAME_M1 : STRING; - FILE_NAME_M2 : STRING; - FILE_NAME_S : STRING; - HAS_RESETN_INPUT : BOOLEAN - ); - PORT ( - CLK : OUT STD_LOGIC; - RESETN : OUT STD_LOGIC; - ACLK : IN STD_LOGIC; - ARESETN : IN STD_LOGIC; - M1_AXIS_TVALID : OUT STD_LOGIC; - M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M1_AXIS_TREADY : IN STD_LOGIC; - M1_AXIS_TLAST : OUT STD_LOGIC; - M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - M2_AXIS_TVALID : OUT STD_LOGIC; - M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M2_AXIS_TREADY : IN STD_LOGIC; - M2_AXIS_TLAST : OUT STD_LOGIC; - M2_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - S_AXIS_TVALID : IN STD_LOGIC; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_TREADY : OUT STD_LOGIC; - S_AXIS_TLAST : IN STD_LOGIC; - S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) - ); - END COMPONENT axis_numeric_master_slave_simmodel; - ATTRIBUTE X_INTERFACE_INFO : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_RESET RESETN, ASSOCIATED_BUSIF S_AXIS:M2_AXIS:M1_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TLAST"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TUSER"; - ATTRIBUTE X_INTERFACE_PARAMETER OF M1_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M1_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TVALID"; - ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; - ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; -BEGIN - U0 : axis_numeric_master_slave_simmodel - GENERIC MAP ( - HAS_CLOCK_GENERATOR => true, - CLOCK_PERIOD_NS => 10, - HAS_RESET_GENERATOR => true, - RESET_ACTIVE_CYCLES => 100, - HAS_MASTER1 => true, - MASTER1_DATA_WIDTH => 32, - MASTER1_RANDOM_VALID => true, - MASTER1_HAS_LAST => true, - MASTER1_LAST_PERIOD => 100, - MASTER1_HAS_USER => false, - MASTER1_USER_PERIOD => 1000, - HAS_MASTER2 => false, - MASTER2_DATA_WIDTH => 32, - MASTER2_RANDOM_VALID => true, - MASTER2_HAS_LAST => false, - MASTER2_LAST_PERIOD => 100, - MASTER2_HAS_USER => false, - MASTER2_USER_PERIOD => 1000, - HAS_SLAVE => true, - SLAVE_DATA_WIDTH => 32, - SLAVE_RANDOM_READY => true, - SLAVE_HAS_LAST => true, - SLAVE_HAS_USER => false, - SLAVE_WAIT_FOR_SOF => false, - FILE_NAME_M1 => "../../../../m1.txt", - FILE_NAME_M2 => "../../../../m1.txt", - FILE_NAME_S => "../../../../m1.txt", - HAS_RESETN_INPUT => false - ) - PORT MAP ( - CLK => CLK, - RESETN => RESETN, - ACLK => '0', - ARESETN => '1', - M1_AXIS_TVALID => M1_AXIS_TVALID, - M1_AXIS_TDATA => M1_AXIS_TDATA, - M1_AXIS_TREADY => M1_AXIS_TREADY, - M1_AXIS_TLAST => M1_AXIS_TLAST, - M1_AXIS_TUSER => M1_AXIS_TUSER, - M2_AXIS_TREADY => '1', - S_AXIS_TVALID => S_AXIS_TVALID, - S_AXIS_TDATA => S_AXIS_TDATA, - S_AXIS_TREADY => S_AXIS_TREADY, - S_AXIS_TLAST => S_AXIS_TLAST, - S_AXIS_TUSER => S_AXIS_TUSER - ); -END test_1_axis_numeric_master_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0/test_1_axis_numeric_master_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0/test_1_axis_numeric_master_0_0.xml deleted file mode 100644 index c91ac6c..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0/test_1_axis_numeric_master_0_0.xml +++ /dev/null @@ -1,1838 +0,0 @@ - - - xilinx.com - customized_ip - test_1_axis_numeric_master_0_0 - 1.0 - - - M1_AXIS - - - - - - - TDATA - - - M1_AXIS_TDATA - - - - - TLAST - - - M1_AXIS_TLAST - - - - - TUSER - - - M1_AXIS_TUSER - - - - - TVALID - - - M1_AXIS_TVALID - - - - - TREADY - - - M1_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 1 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - test_1_axis_numeric_master_0_0_CLK - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - M2_AXIS - - - - - - - TDATA - - - M2_AXIS_TDATA - - - - - TLAST - - - M2_AXIS_TLAST - - - - - TUSER - - - M2_AXIS_TUSER - - - - - TVALID - - - M2_AXIS_TVALID - - - - - TREADY - - - M2_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXIS - - - - - - - TDATA - - - S_AXIS_TDATA - - - - - TLAST - - - S_AXIS_TLAST - - - - - TUSER - - - S_AXIS_TUSER - - - - - TVALID - - - S_AXIS_TVALID - - - - - TREADY - - - S_AXIS_TREADY - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 1 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 1 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - test_1_axis_numeric_master_0_0_CLK - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - ARESETN - - - - - - - RST - - - ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RESETN - - - - - - - RST - - - RESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - ACLK - - - - - - - CLK - - - ACLK - - - - - - ASSOCIATED_BUSIF - M1_AXIS:M2_AXIS:S_AXIS - - - ASSOCIATED_RESET - RESETN - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - CLK - - - - - - - CLK - - - CLK - - - - - - ASSOCIATED_RESET - RESETN - - - ASSOCIATED_BUSIF - S_AXIS:M2_AXIS:M1_AXIS - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - test_1_axis_numeric_master_0_0_CLK - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - axis_numeric_master_slave_simmodel - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Feb 01 16:12:36 UTC 2025 - - - outputProductCRC - 9:cae3de6e - - - - - xilinx_vhdlsimulationwrapper - VHDL Simulation Wrapper - vhdlSource:vivado.xilinx.com:simulation.wrapper - vhdl - test_1_axis_numeric_master_0_0 - - xilinx_vhdlsimulationwrapper_view_fileset - - - - GENtimestamp - Sat Feb 01 17:39:19 UTC 2025 - - - outputProductCRC - 9:cae3de6e - - - - - - - CLK - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - RESETN - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x1 - - - - - ACLK - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - ARESETN - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - M1_AXIS_TVALID - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - M1_AXIS_TDATA - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - M1_AXIS_TREADY - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x1 - - - - - M1_AXIS_TLAST - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - M1_AXIS_TUSER - - out - - 0 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - M2_AXIS_TVALID - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - M2_AXIS_TDATA - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - M2_AXIS_TREADY - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - M2_AXIS_TLAST - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - M2_AXIS_TUSER - - out - - 0 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - S_AXIS_TVALID - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - S_AXIS_TDATA - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - S_AXIS_TREADY - - out - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - - - S_AXIS_TLAST - - in - - - std_logic - xilinx_anylanguagebehavioralsimulation - - - - 0x0 - - - - - S_AXIS_TUSER - - in - - 0 - 0 - - - - std_logic_vector - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - - HAS_CLOCK_GENERATOR - Has Clock Generator - true - - - CLOCK_PERIOD_NS - Clock Period Ns - 10 - - - HAS_RESET_GENERATOR - Has Reset Generator - true - - - RESET_ACTIVE_CYCLES - Reset Active Cycles - 100 - - - HAS_MASTER1 - Has Master1 - true - - - MASTER1_DATA_WIDTH - Master1 Data Width - 32 - - - MASTER1_RANDOM_VALID - Master1 Random Valid - true - - - MASTER1_HAS_LAST - Master1 Has Last - true - - - MASTER1_LAST_PERIOD - Master1 Last Period - 100 - - - MASTER1_HAS_USER - Master1 Has User - false - - - MASTER1_USER_PERIOD - Master1 User Period - 1000 - - - HAS_MASTER2 - Has Master2 - false - - - MASTER2_DATA_WIDTH - Master2 Data Width - 32 - - - MASTER2_RANDOM_VALID - Master2 Random Valid - true - - - MASTER2_HAS_LAST - Master2 Has Last - false - - - MASTER2_LAST_PERIOD - Master2 Last Period - 100 - - - MASTER2_HAS_USER - Master2 Has User - false - - - MASTER2_USER_PERIOD - Master2 User Period - 1000 - - - HAS_SLAVE - Has Slave - true - - - SLAVE_DATA_WIDTH - Slave Data Width - 32 - - - SLAVE_RANDOM_READY - Slave Random Ready - true - - - SLAVE_HAS_LAST - Slave Has Last - true - - - SLAVE_HAS_USER - Slave Has User - false - - - SLAVE_WAIT_FOR_SOF - Slave Wait For Sof - false - - - FILE_NAME_M1 - File Name M1 - ../../../../m1.txt - - - FILE_NAME_M2 - File Name M2 - ../../../../m1.txt - - - FILE_NAME_S - File Name S - ../../../../m1.txt - - - HAS_RESETN_INPUT - Has Resetn Input - false - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - ../../ipshared/c6f6/vhdl_c_pkg_tb.vhd - vhdlSource - - - ../../ipshared/c6f6/axis_numeric_master_slave_simmodel.vhd - vhdlSource - - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/test_1_axis_numeric_master_0_0.vhd - vhdlSource - xil_defaultlib - - - - axis_numeric_master_slave_simmodel_v1_0 - - - HAS_CLOCK_GENERATOR - Clock Generator - true - - - CLOCK_PERIOD_NS - Clock Period (ns) - 10 - - - HAS_RESET_GENERATOR - Reset Generator - true - - - RESET_ACTIVE_CYCLES - Reset Active Cycles at Startup - 100 - - - HAS_MASTER1 - AXIS Master 1 - true - - - MASTER1_DATA_WIDTH - Data Width - 32 - - - MASTER1_RANDOM_VALID - Random Valid - true - - - MASTER1_HAS_LAST - TLAST present - true - - - MASTER1_LAST_PERIOD - TLAST Period - 100 - - - MASTER1_HAS_USER - TUSER present - false - - - MASTER1_USER_PERIOD - TUSER Period - 1000 - - - HAS_MASTER2 - AXIS Master 2 - false - - - MASTER2_DATA_WIDTH - Data Width - 32 - - - MASTER2_RANDOM_VALID - Random Valid - true - - - MASTER2_HAS_LAST - TLAST present - false - - - MASTER2_LAST_PERIOD - TLAST Period - 100 - - - MASTER2_HAS_USER - TUSER present - false - - - MASTER2_USER_PERIOD - TUSER Period - 1000 - - - HAS_SLAVE - AXIS Slave - true - - - SLAVE_DATA_WIDTH - Data Width - 32 - - - SLAVE_RANDOM_READY - Random Ready - true - - - SLAVE_HAS_LAST - TLAST present - true - - - SLAVE_HAS_USER - TUSER present - false - - - SLAVE_WAIT_FOR_SOF - Wait For SOF - false - - - FILE_NAME_M1 - Stimuli File - ../../../../m1.txt - - - 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d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - d:/Projekte/GIP/axis_numeric_master_slave_simmodel/axis_numeric_master_slave_simmodel.srcs/sources_1/new - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0.h b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0.h deleted file mode 100644 index c02b8e7..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0.h +++ /dev/null @@ -1,65 +0,0 @@ -// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: xilinx.com:ip:xlconstant:1.1 -// IP Revision: 1 - -#ifndef _test_1_xlconstant_0_0_H_ -#define _test_1_xlconstant_0_0_H_ - -#include "xlconstant_v1_1_7.h" -#include "systemc.h" -class test_1_xlconstant_0_0 : public sc_module { - public: -xlconstant_v1_1_7<32,0> mod; - sc_out< sc_bv<32> > dout; -test_1_xlconstant_0_0 (sc_core::sc_module_name name); - }; - -#endif diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0_stub.sv b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0_stub.sv deleted file mode 100644 index 66d4a5e..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0_stub.sv +++ /dev/null @@ -1,79 +0,0 @@ -// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -//------------------------------------------------------------------------------------ -// Filename: xl_Constant_stub.sv -// Description: This HDL file is intended to be used with following simulators only: -// -// Vivado Simulator (XSim) -// Cadence Xcelium Simulator -// -//------------------------------------------------------------------------------------ -`ifdef XILINX_SIMULATOR -`ifndef XILINX_SIMULATOR_BITASBOOL -`define XILINX_SIMULATOR_BITASBOOL -typedef bit bit_as_bool; -`endif - -(* SC_MODULE_EXPORT *) -module test_1_xlconstant_0_0 ( - output bit [31 : 0 ] dout -); -endmodule -`endif - -`ifdef XCELIUM -(* XMSC_MODULE_EXPORT *) -module test_1_xlconstant_0_0 (dout) -(* integer foreign = "SystemC"; -*); - output wire [31 : 0 ] dout; -endmodule -`endif - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h deleted file mode 100644 index 653886b..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: xilinx.com:ip:xlconstant:1.1 -// IP Revision: 1 - -#ifndef _xlconstant_v1_1_7_H_ -#define _xlconstant_v1_1_7_H_ - -#include "systemc.h" -template -SC_MODULE(xlconstant_v1_1_7) { - public: - sc_out< sc_bv > dout; - void init() { - dout.write(CONST_VAL); - } - SC_CTOR(xlconstant_v1_1_7) { - SC_METHOD(init); - } -}; - -#endif diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/test_1_xlconstant_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/test_1_xlconstant_0_0.xml deleted file mode 100644 index 93ece8e..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/test_1_xlconstant_0_0.xml +++ /dev/null @@ -1,206 +0,0 @@ - - - xilinx.com - customized_ip - test_1_xlconstant_0_0 - 1.0 - - - - xilinx_systemcsimulation - SystemC Simulation - systemCSource:vivado.xilinx.com:simulation - systemc - xlconstant_v1_1_7 - - xilinx_systemcsimulation_view_fileset - - - - GENtimestamp - Sat Feb 01 16:15:06 UTC 2025 - - - outputProductCRC - 9:bb996ab6 - - - sim_type - tlm - - - - - xilinx_systemcsimulationwrapper - SystemC Simulation Wrapper - systemCSource:vivado.xilinx.com:simulation.wrapper - systemc - test_1_xlconstant_0_0 - - xilinx_systemcsimulationwrapper_view_fileset - - - - GENtimestamp - Sat Feb 01 16:15:06 UTC 2025 - - - outputProductCRC - 9:bb996ab6 - - - sim_type - tlm - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - xlconstant_v1_1_7_xlconstant - - xilinx_verilogbehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Feb 01 16:15:06 UTC 2025 - - - outputProductCRC - 9:bb996ab6 - - - - - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper - verilog - test_1_xlconstant_0_0 - - xilinx_verilogsimulationwrapper_view_fileset - - - - GENtimestamp - Sat Feb 01 16:15:06 UTC 2025 - - - outputProductCRC - 9:bb996ab6 - - - - - - - dout - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogbehavioralsimulation - - - - - - - - CONST_WIDTH - Const Width - 32 - - - CONST_VAL - Const Val - 0x00000000 - - - - - - xilinx_systemcsimulation_view_fileset - - sim/xlconstant_v1_1_7.h - systemCSource - true - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/test_1_xlconstant_0_0.h - systemCSource - true - - - sim/test_1_xlconstant_0_0.cpp - systemCSource - - - sim/test_1_xlconstant_0_0_stub.sv - systemVerilogSource - - - - xilinx_verilogbehavioralsimulation_view_fileset - - ../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - xlconstant_v1_1_7 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/test_1_xlconstant_0_0.v - verilogSource - xil_defaultlib - - - - Gives a constant signed value. - - - Component_Name - test_1_xlconstant_0_0 - - - CONST_WIDTH - Const Width - 32 - - - CONST_VAL - Const Val - 0 - - - - - Constant - 7 - - - - - - - 2023.1 - - - - - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0.h b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0.h deleted file mode 100644 index 6e9bb57..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0.h +++ /dev/null @@ -1,65 +0,0 @@ -// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: xilinx.com:ip:xlconstant:1.1 -// IP Revision: 1 - -#ifndef _test_1_xlconstant_1_0_H_ -#define _test_1_xlconstant_1_0_H_ - -#include "xlconstant_v1_1_7.h" -#include "systemc.h" -class test_1_xlconstant_1_0 : public sc_module { - public: -xlconstant_v1_1_7<32,0> mod; - sc_out< sc_bv<32> > dout; -test_1_xlconstant_1_0 (sc_core::sc_module_name name); - }; - -#endif diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0_stub.sv b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0_stub.sv deleted file mode 100644 index 7a2af74..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0_stub.sv +++ /dev/null @@ -1,79 +0,0 @@ -// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -//------------------------------------------------------------------------------------ -// Filename: xl_Constant_stub.sv -// Description: This HDL file is intended to be used with following simulators only: -// -// Vivado Simulator (XSim) -// Cadence Xcelium Simulator -// -//------------------------------------------------------------------------------------ -`ifdef XILINX_SIMULATOR -`ifndef XILINX_SIMULATOR_BITASBOOL -`define XILINX_SIMULATOR_BITASBOOL -typedef bit bit_as_bool; -`endif - -(* SC_MODULE_EXPORT *) -module test_1_xlconstant_1_0 ( - output bit [31 : 0 ] dout -); -endmodule -`endif - -`ifdef XCELIUM -(* XMSC_MODULE_EXPORT *) -module test_1_xlconstant_1_0 (dout) -(* integer foreign = "SystemC"; -*); - output wire [31 : 0 ] dout; -endmodule -`endif - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/xlconstant_v1_1_7.h b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/xlconstant_v1_1_7.h deleted file mode 100644 index 653886b..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/xlconstant_v1_1_7.h +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: xilinx.com:ip:xlconstant:1.1 -// IP Revision: 1 - -#ifndef _xlconstant_v1_1_7_H_ -#define _xlconstant_v1_1_7_H_ - -#include "systemc.h" -template -SC_MODULE(xlconstant_v1_1_7) { - public: - sc_out< sc_bv > dout; - void init() { - dout.write(CONST_VAL); - } - SC_CTOR(xlconstant_v1_1_7) { - SC_METHOD(init); - } -}; - -#endif diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/test_1_xlconstant_1_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/test_1_xlconstant_1_0.xml deleted file mode 100644 index 46c3b53..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/test_1_xlconstant_1_0.xml +++ /dev/null @@ -1,206 +0,0 @@ - - - xilinx.com - customized_ip - test_1_xlconstant_1_0 - 1.0 - - - - xilinx_systemcsimulation - SystemC Simulation - systemCSource:vivado.xilinx.com:simulation - systemc - xlconstant_v1_1_7 - - xilinx_systemcsimulation_view_fileset - - - - GENtimestamp - Sat Feb 01 17:07:49 UTC 2025 - - - outputProductCRC - 9:8609d079 - - - sim_type - tlm - - - - - xilinx_systemcsimulationwrapper - SystemC Simulation Wrapper - systemCSource:vivado.xilinx.com:simulation.wrapper - systemc - test_1_xlconstant_1_0 - - xilinx_systemcsimulationwrapper_view_fileset - - - - GENtimestamp - Sat Feb 01 17:07:49 UTC 2025 - - - outputProductCRC - 9:8609d079 - - - sim_type - tlm - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - xlconstant_v1_1_7_xlconstant - - xilinx_verilogbehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Feb 01 16:15:06 UTC 2025 - - - outputProductCRC - 9:8609d079 - - - - - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper - verilog - test_1_xlconstant_1_0 - - xilinx_verilogsimulationwrapper_view_fileset - - - - GENtimestamp - Sat Feb 01 17:07:49 UTC 2025 - - - outputProductCRC - 9:8609d079 - - - - - - - dout - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogbehavioralsimulation - - - - - - - - CONST_WIDTH - Const Width - 32 - - - CONST_VAL - Const Val - 0x00000000 - - - - - - xilinx_systemcsimulation_view_fileset - - sim/xlconstant_v1_1_7.h - systemCSource - true - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/test_1_xlconstant_1_0.h - systemCSource - true - - - sim/test_1_xlconstant_1_0.cpp - systemCSource - - - sim/test_1_xlconstant_1_0_stub.sv - systemVerilogSource - - - - xilinx_verilogbehavioralsimulation_view_fileset - - ../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - xlconstant_v1_1_7 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/test_1_xlconstant_1_0.v - verilogSource - xil_defaultlib - - - - Gives a constant signed value. - - - Component_Name - test_1_xlconstant_1_0 - - - CONST_WIDTH - Const Width - 32 - - - CONST_VAL - Const Val - 0 - - - - - Constant - 7 - - - - - - - 2023.1 - - - - - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v deleted file mode 100644 index 51977ac..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v +++ /dev/null @@ -1,31 +0,0 @@ -//------------------------------------------------------------------------ -//-- -//-- Filename : xlconstant.v -//-- -//-- Date : 06/05/12 -//-- -//-- Description : VERILOG description of a constant block. This -//-- block does not use a core. -//-- -//------------------------------------------------------------------------ - - -//------------------------------------------------------------------------ -//-- -//-- Module : xlconstant -//-- -//-- Architecture : behavior -//-- -//-- Description : Top level VERILOG description of constant block -//-- -//------------------------------------------------------------------------ -`timescale 1ps/1ps -module xlconstant_v1_1_7_xlconstant (dout); - parameter CONST_VAL = 1; - parameter CONST_WIDTH = 1; - output [CONST_WIDTH-1:0] dout; - - assign dout = CONST_VAL; -endmodule - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/c6f6/axis_numeric_master_slave_simmodel.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/c6f6/axis_numeric_master_slave_simmodel.vhd deleted file mode 100644 index e40cd22..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/c6f6/axis_numeric_master_slave_simmodel.vhd +++ /dev/null @@ -1,362 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.vhdl_c_pkg_tb.all; - -entity axis_numeric_master_slave_simmodel is - generic - ( - HAS_CLOCK_GENERATOR : boolean := true; - CLOCK_PERIOD_NS : integer := 10; - - HAS_RESET_GENERATOR : boolean := true; - HAS_RESETN_INPUT : boolean := false; - RESET_ACTIVE_CYCLES : integer := 100; - - HAS_MASTER1 : boolean := true; - FILE_NAME_M1 : string := string'("../../../../m1.txt"); - MASTER1_DATA_WIDTH : integer := 32; - MASTER1_RANDOM_VALID : boolean := true; - MASTER1_HAS_LAST : boolean := true; - MASTER1_LAST_PERIOD : integer := 100; - MASTER1_HAS_USER : boolean := true; - MASTER1_USER_PERIOD : integer := 1000; - - HAS_MASTER2 : boolean := true; - FILE_NAME_M2 : string := string'("../../../../m1.txt"); - MASTER2_DATA_WIDTH : integer := 32; - MASTER2_RANDOM_VALID : boolean := true; - MASTER2_HAS_LAST : boolean := true; - MASTER2_LAST_PERIOD : integer := 100; - MASTER2_HAS_USER : boolean := true; - MASTER2_USER_PERIOD : integer := 1000; - - HAS_SLAVE : boolean := true; - FILE_NAME_S : string := string'("../../../../m1.txt"); - SLAVE_DATA_WIDTH : integer := 32; - SLAVE_RANDOM_READY : boolean := true; - SLAVE_HAS_LAST : boolean := true; - SLAVE_HAS_USER : boolean := true; - SLAVE_WAIT_FOR_SOF : boolean := true - ); - - port - ( - CLK : out std_logic := '0'; - RESETN : out std_logic := '1'; - - ACLK : in std_logic := '0'; - ARESETN : in std_logic := '1'; - - M1_AXIS_TVALID : out std_logic := '0'; - M1_AXIS_TDATA : out std_logic_vector(MASTER1_DATA_WIDTH-1 downto 0):= (others=>'0'); - M1_AXIS_TREADY : in std_logic := '1'; - M1_AXIS_TLAST : out std_logic := '0'; - M1_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0'); - - M2_AXIS_TVALID : out std_logic := '0'; - M2_AXIS_TDATA : out std_logic_vector(MASTER2_DATA_WIDTH-1 downto 0) := (others=>'0'); - M2_AXIS_TREADY : in std_logic := '1'; - M2_AXIS_TLAST : out std_logic := '0'; - M2_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0'); - - S_AXIS_TVALID : in std_logic := '0'; - S_AXIS_TDATA : in std_logic_vector(SLAVE_DATA_WIDTH-1 downto 0); - S_AXIS_TREADY : out std_logic; - S_AXIS_TLAST : in std_logic := '0'; - S_AXIS_TUSER : in std_logic_vector(0 downto 0):= (others=>'0') - ); - -end; - - - -architecture sim of axis_numeric_master_slave_simmodel is - - signal rnd_m1 : unsigned (31 downto 0) := x"ABBAABBA"; - signal rnd_m2 : unsigned (31 downto 0) := x"DEADBEEF"; - signal rnd_s : unsigned (31 downto 0) := x"12345678"; - signal lclk : std_logic := '0'; - signal local_clk : std_logic := ACLK; - signal local_resetn : std_logic := '1'; - - signal DBG_M1_FILERELOAD : std_logic := '0'; - signal DBG_M2_FILERELOAD : std_logic := '0'; - signal DBG_S_FILERELOAD : std_logic := '0'; - -begin - --- synthesis translate_off --- translate off - ---------------------------------------- - -- Clock Generator - ---------------------------------------- - genclk: if HAS_CLOCK_GENERATOR generate - lclk <= not lclk after CLOCK_PERIOD_NS * 0.5 ns; - CLK <= lclk; - local_clk <= lclk; - end generate; - - no_genclk: if not HAS_CLOCK_GENERATOR generate - local_clk <= ACLK; - end generate; - - ---------------------------------------- - -- Reset Generator - ---------------------------------------- - genreset: if HAS_RESET_GENERATOR generate - process begin - RESETN <= '0'; - local_resetn <= '0'; - for i in 1 to RESET_ACTIVE_CYCLES loop - wait until rising_edge(local_clk); - end loop; - RESETN <= '1'; - local_resetn <= '1'; - wait; - end process; - end generate; - - no_genreset: if HAS_RESETN_INPUT and (not HAS_RESET_GENERATOR) generate - local_resetn <= ARESETN; - end generate; - - - ---------------------------------------- - -- Random Number Generator - ---------------------------------------- - -- uint32_t xorshift32() { - -- static uint32_t x = 314159265; - -- x ^= x << 13; - -- x ^= x >> 17; - -- x ^= x << 5; - -- return x; - -- } - rnd: process - variable r : unsigned (31 downto 0); - begin - wait until rising_edge(local_clk); - r := rnd_m1; - r := r xor (r(18 downto 0)& x"000"&"0"); - r := r xor (x"0000"&"0"&r(31 downto 17)); - r := r xor (r(26 downto 0)& "00000"); - rnd_m1 <= r; - r := rnd_m2; - r := r xor (r(18 downto 0)& x"000"&"0"); - r := r xor (x"0000"&"0"&r(31 downto 17)); - r := r xor (r(26 downto 0)& "00000"); - rnd_m2 <= r; - r := rnd_s; - r := r xor (r(18 downto 0)& x"000"&"0"); - r := r xor (x"0000"&"0"&r(31 downto 17)); - r := r xor (r(26 downto 0)& "00000"); - rnd_s <= r; - end process; - - ---------------------------------------- - -- Master 1 - ---------------------------------------- - genmaster1: if HAS_MASTER1 generate - m1: process - variable fp : CFILE := 0; - variable data : std_logic_vector(31 downto 0); - variable rnd : integer; - variable data_cnt_last : integer := 1; - variable data_cnt_user : integer := 1; - variable valid_out : std_logic := '0'; - - begin - wait until rising_edge (local_clk); - DBG_M1_FILERELOAD <= '0'; - if (local_resetn = '0') then - valid_out := '0'; - M1_AXIS_TVALID <= '0'; - M1_AXIS_TDATA <= (others=>'0'); - if fp > 0 then - fclose(fp); - end if; - else - if fp > 0 then - fclose(fp); - fp := 0; - end if; - fp := fopen(FILE_NAME_M1, "r"); - if fp = 0 then - printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master1 (%s).\n",FILE_NAME_M1); - wait; - end if; - - while not feof(fp) loop - valid_out := '1'; - fscanf(fp, string'("%x"), data); - M1_AXIS_TVALID <= '1'; - M1_AXIS_TDATA <= data(MASTER1_DATA_WIDTH-1 downto 0); - M1_AXIS_TLAST <= '0'; - M1_AXIS_TUSER(0) <= '0'; - if data_cnt_last >= MASTER1_LAST_PERIOD then - M1_AXIS_TLAST <= '1'; - data_cnt_last := 0; - end if; - if data_cnt_user >= MASTER1_USER_PERIOD then - M1_AXIS_TUSER(0) <= '1'; - data_cnt_user := 0; - end if; - data_cnt_last := data_cnt_last + 1; - data_cnt_user := data_cnt_user + 1; - - wait until rising_edge (local_clk); - while M1_AXIS_TREADY /= '1' loop - wait until rising_edge (local_clk); - end loop; - - rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length)); - if (rnd>0 and MASTER1_RANDOM_VALID) then - M1_AXIS_TVALID <= '0'; - for i in 0 to rnd loop - wait until rising_edge (local_clk); - end loop; - end if; - end loop; - M1_AXIS_TVALID <= '0'; - DBG_M1_FILERELOAD <= '1'; - end if; - end process; - end generate; - - ---------------------------------------- - -- Master 2 - ---------------------------------------- - genmaster2: if HAS_MASTER2 generate - m2: process - variable fp : CFILE := 0; - variable data : std_logic_vector(31 downto 0); - variable rnd : integer; - variable data_cnt_last : integer := 1; - variable data_cnt_user : integer := 1; - variable valid_out : std_logic := '0'; - - begin - - wait until rising_edge (local_clk); - DBG_M1_FILERELOAD <= '0'; - if (local_resetn = '0') then - valid_out := '0'; - M2_AXIS_TVALID <= '0'; - M2_AXIS_TDATA <= (others=>'0'); - if fp > 0 then - fclose(fp); - end if; - else - if fp > 0 then - fclose(fp); - fp := 0; - end if; - fp := fopen(FILE_NAME_M2, "r"); - if fp = 0 then - printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master2 (%s).\n",FILE_NAME_M2); - wait; - end if; - - while not feof(fp) loop - valid_out := '1'; - fscanf(fp, string'("%x"), data); - M2_AXIS_TVALID <= '1'; - M2_AXIS_TDATA <= data(MASTER2_DATA_WIDTH-1 downto 0); - M2_AXIS_TLAST <= '0'; - M2_AXIS_TUSER(0) <= '0'; - if data_cnt_last >= MASTER2_LAST_PERIOD then - M2_AXIS_TLAST <= '1'; - data_cnt_last := 0; - end if; - if data_cnt_user >= MASTER1_USER_PERIOD then - M2_AXIS_TUSER(0) <= '1'; - data_cnt_user := 0; - end if; - data_cnt_last := data_cnt_last + 1; - data_cnt_user := data_cnt_user + 1; - - wait until rising_edge (local_clk); - while M2_AXIS_TREADY /= '1' loop - wait until rising_edge (local_clk); - end loop; - - rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length)); - if (rnd>0 and MASTER2_RANDOM_VALID) then - M2_AXIS_TVALID <= '0'; - for i in 0 to rnd loop - wait until rising_edge (local_clk); - end loop; - end if; - end loop; - M2_AXIS_TVALID <= '0'; - DBG_M2_FILERELOAD <= '1'; - end if; - end process; - end generate; - - ---------------------------------------- - -- SLAVE - ---------------------------------------- - genslave: if HAS_SLAVE generate - s: process - variable fp : CFILE := 0; - variable data : std_logic_vector(31 downto 0) := (others=>'0'); - variable rnd : integer; - variable wait_sof : boolean := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER; - begin - - wait until rising_edge (local_clk); - DBG_S_FILERELOAD <= '0'; - if (local_resetn = '0') then - S_AXIS_TREADY <= '0'; - if fp > 0 then - fclose(fp); - end if; - wait_sof := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER; - elsif wait_sof then - if S_AXIS_TVALID = '1' and S_AXIS_TUSER(0) = '1' then - wait_sof := false; - end if; - else - if fp > 0 then - fclose(fp); - fp := 0; - end if; - fp := fopen(FILE_NAME_S, "r"); - if fp = 0 then - printf("*** Simulation Info *** => Cannot open stimuli file for AXIS-Slave (%s).\n",FILE_NAME_S); - end if; - - while not feof(fp) and fp /= 0 loop - S_AXIS_TREADY <= '1'; - wait until rising_edge (local_clk); - while S_AXIS_TVALID /= '1' loop - wait until rising_edge (local_clk); - end loop; - - if fp > 0 then - fscanf(fp, string'("%x"), data); - if data(SLAVE_DATA_WIDTH-1 downto 0) /= S_AXIS_TDATA then - printf("*** Verification Error *** => expected %x - received %x\n",data(SLAVE_DATA_WIDTH-1 downto 0),S_AXIS_TDATA); - end if; - end if; - - rnd := to_integer(rnd_s and to_unsigned(3,rnd_s'length)); - if (rnd>0 and SLAVE_RANDOM_READY) then - S_AXIS_TREADY <= '0'; - for i in 0 to rnd loop - wait until rising_edge (local_clk); - end loop; - end if; - end loop; - S_AXIS_TREADY <= '0'; - DBG_S_FILERELOAD <= '1'; - end if; - end process; - end generate; - --- synthesis translate_on --- translate on - -end; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/c6f6/vhdl_c_pkg_tb.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/c6f6/vhdl_c_pkg_tb.vhd deleted file mode 100644 index a277d78..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/c6f6/vhdl_c_pkg_tb.vhd +++ /dev/null @@ -1,2604 +0,0 @@ --- Files: stdlib_h.vhd et.al. --- Version: 3.0 (June 6, 2004) --- Source: http://bear.ces.cwru.edu/vhdl --- Date: June 6, 2004 (Copyright) --- Author: Francis G. Wolff Email: fxw12@po.cwru.edu --- Author: Michael J. Knieser Email: mjknieser@knieser.com --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 1, or (at your option) --- any later version: http://www.gnu.org/licenses/gpl.html --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. --- -library STD; -use STD.textio.all; -library IEEE; -use IEEE.std_logic_1164.all; - -PACKAGE vhdl_c_pkg_tb IS --------------------------------------------------------------------------------------------- --- Package: endian_h --------------------------------------------------------------------------------------------- --- PACKAGE endian_h IS - --to_bigendian(x=any endian) return only big endian (HIGH DOWNTO LOW); - --to_littleendian(x=any endian) return only little endian (LOW TO HIGH); - - FUNCTION to_bigendian_bit_vector( x: IN BIT_VECTOR) RETURN BIT_VECTOR; - FUNCTION to_littleendian_bit_vector(x: IN BIT_VECTOR) RETURN BIT_VECTOR; - FUNCTION to_bigendian_bit_vector( x: IN INTEGER; n: IN INTEGER:=32) RETURN BIT_VECTOR; --n bits - FUNCTION to_littleendian_bit_vector( x: IN INTEGER; n: IN INTEGER:=32) RETURN BIT_VECTOR; --n bits - - FUNCTION to_bigendian_std_logic_vector( x: IN BIT_VECTOR) RETURN STD_LOGIC_VECTOR; - FUNCTION to_littleendian_std_logic_vector(x: IN BIT_VECTOR) RETURN STD_LOGIC_VECTOR; - FUNCTION to_bigendian_std_logic_vector( x: IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; - FUNCTION to_littleendian_std_logic_vector(x: IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; - FUNCTION to_bigendian_std_logic_vector( x: IN INTEGER; n: IN INTEGER:=32) RETURN std_logic_vector; - FUNCTION to_littleendian_std_logic_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN std_logic_vector; - - --This must be a seperate case because VHDL cannot distinguish between typeless STRING and BIT_VECTOR string - FUNCTION to_bigendian_bit_vector_string(x: IN STRING) RETURN BIT_VECTOR; --"0101",o"05",x"5" - FUNCTION to_littleendian_bit_vector_string(x: IN STRING) RETURN BIT_VECTOR; --"0101",o"05",x"5" - FUNCTION to_bigendian_std_logic_vector_string(x: IN STRING) RETURN std_logic_vector; - FUNCTION to_littleendian_std_logic_vector_string(x: IN STRING) RETURN std_logic_vector; - ---------------------------------------------------------------------------------------------------------- --- END endian_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package ctype_h is ---------------------------------------------------------------------------------------------------------- - function isalpha(c: character) return boolean; - function isupper(c: character) return boolean; - function islower(c: character) return boolean; - function isdigit(c: character) return boolean; - function isxdigit(c: character) return boolean; - function isalnum(c: character) return boolean; - function isspace(c: character) return boolean; - function ispunct(c: character) return boolean; - function isprint(c: character) return boolean; - function isgraph(c: character) return boolean; - function iscntrl(c: character) return boolean; - function isascii(c: character) return boolean; - function tolower(c: character) return character; - function toupper(c: character) return character; - - - --This implementation was done to use the VHDL simulator efficiently - --and minimize number of boolean type arrays - - type tarray is array(0 to 255) of integer; - constant t: tarray:=( - 2, 2, 2, 2, 2, 2, 2, 2, 2,11*2,11*2,11*2,11*2,11*2, 2, 2, --0x00 - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, --0x10 - 11, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, --0x20 - 13*3,13*3,13*3,13*3,13*3,13*3,13*3,13*3,13*3,13*3, 17, 17, 17, 17, 17, 17, --0x30 - 17, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5*3, 5, 5, 5, 5, 5, --0x40 - 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 17, 17, 17, 17, 17, --0x50 - 17, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7*3, 7, 7, 7, 7, 7, --0x60 - 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 17, 17, 17, 17, 2, --0x70 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0x80 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0x90 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xa0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xb0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xc0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xd0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, --0xe0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);--0xf0 - ---------------------------------------------------------------------------------------------------------- --- end ctype_h; ---------------------------------------------------------------------------------------------------------- - - ---------------------------------------------------------------------------------------------------------- --- package strings_h is ---------------------------------------------------------------------------------------------------------- - ---c/c++ string is an array of integers and are variable in length ---cannot contain a zero byte, concession to computers with fast zero compare ---also no need to save length size ---cannot protect overwriting allocated size ---mixed endian, little endian string but big endian bytes - ---vhdl string is an array of enumerated types and are fixed in length ---..this makes it difficult to embed numeric characters ---..like in C (i.e. \0x0d ) - - --C language addressing: strlen(s+si); - function strlen(s: IN string) return integer; - function strlen(s: IN string; si: IN integer) return integer; ---function strlen(s: INOUT line) return integer; --use instead: strlen(s.all); - - --array constant still works "s": strcpy(s, ""); - --strcpy(d, s); strcpy(d, s+si); strcpy(d+di, s); strcpy(d+di, s+si); - procedure strcpy(d: OUT string; s: IN string); - procedure strcpy(d: OUT string; s: IN string; si: IN integer); - procedure strcpy(d: INOUT string; di: IN integer; s: IN string); - procedure strcpy(d: INOUT string; di: IN integer; s: IN string; si: IN integer); - - --element constant still works 'c': strcpy(s, '#'); - procedure strcpy(d: OUT string; s: IN character); - - procedure strcat(d: INOUT line; s: IN string); --Due to ModelSim - procedure strcat(d: INOUT string; s: IN string); - procedure strcat(d: INOUT string; s: IN string; si: IN integer); - procedure strcat(d: INOUT string; di: IN integer; s: IN string); - procedure strcat(d: INOUT string; di: IN integer; s: IN string; si: IN integer); - - procedure strcat(d: INOUT string; s: IN character); - - function strcmp(d: IN string; s: IN string) return integer; - - procedure strcpyij(d: OUT string; s: IN string; i, j: IN integer); - ---------------------------------------------------------------------------------------------------------- --- end strings_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package stdlib_h is ---------------------------------------------------------------------------------------------------------- - procedure strtoul(result: OUT integer; --natural - s: IN string; si: IN integer; - endptr: INOUT integer; base:IN integer); - - procedure strtoul(result: OUT integer; --natural - s: IN string; - endptr: INOUT integer; base:IN integer); - - procedure strtol(result: OUT integer; --natural - s: IN string; si: IN integer; - endptr: INOUT integer; base:IN integer); - - procedure strtol(result: OUT integer; --natural - s: IN string; - endptr: INOUT integer; base:IN integer); - - function atoi(s: IN string) return integer; - - function atol(s: IN string) return integer; - ---------------------------------------------------------------------------------------------------------- --- end stdlib_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package regexp_h is ---------------------------------------------------------------------------------------------------------- - --AVOID: since shared variables will cause problems with multiple processes - - --INPUT si = initial index into the string - --INPUT s = scan string terminated by NUL or length - --INPUT f = pattern matching format string (i.e. perl style, less typing than sed) - - --OUTPUT ai = 0 none, alternate match number = 1|2|3|4|... - --OUTPUT si = next unmatch character - --OUTPUT m1 = matched (string) =\1 - --OUTPUT m2 = matched (string) =\2 - - --NOTES: . = match any character except NUL - -- (differs from perl which is newline - -- since pattern matching is limited to a line) - -- ^$ = match an empty string (i.e. length=0 or first character=NUL) - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; f: IN string); - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1: OUT string); - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1,m2: OUT string); - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1,m2,m3: OUT string); - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1,m2,m3,m4: OUT string); - - function sedscanf(s: IN string) return string; - ---------------------------------------------------------------------------------------------------------- --- end regexp_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- PACKAGE stdio_h IS ---------------------------------------------------------------------------------------------------------- - FILE streamfile4, streamfile5, streamfile6: TEXT; - FILE streamfile7, streamfile8, streamfile9: TEXT; - CONSTANT streamNFILE: INTEGER:=9; - - TYPE streamflags IS ARRAY(0 TO streamNFILE) OF BOOLEAN; - SHARED VARIABLE streambusy: streamflags := (TRUE,TRUE,TRUE,TRUE,OTHERS=>FALSE); - SHARED VARIABLE streamlock: BOOLEAN:=FALSE; - SHARED VARIABLE streamnulbuf: LINE; --should allows be null - - TYPE STREAMIOBUF IS - RECORD - fstat: FILE_OPEN_STATUS; - fmode: FILE_OPEN_KIND; --READ_MODE, WRITE_MODE, APPEND_MODE; - buf: LINE; - END RECORD; - - TYPE STREAMIOBUFS IS ARRAY(0 TO streamNFILE) OF STREAMIOBUF; - SHARED VARIABLE streamiob: STREAMIOBUFS := - ((STATUS_ERROR,READ_MODE,NULL), --null fid - (OPEN_OK,WRITE_MODE,NULL), --stdout - (OPEN_OK,READ_MODE,NULL), --stdin - OTHERS=>(STATUS_ERROR,READ_MODE,NULL)); - - SUBTYPE CFILE IS INTEGER; - CONSTANT stdin: CFILE :=2; --UNIX filename "/dev/tty", DOS filename "CON" - CONSTANT stdout: CFILE :=1; --UNIX filename "/dev/tty", DOS filename "CON" - CONSTANT stdnul: CFILE :=3; --UNIX filename "/dev/null", DOS filename "NUL" - CONSTANT stderr: CFILE :=1; --Not support by VHDL 93 - - FUNCTION pf(x: IN BIT) RETURN STRING; - FUNCTION pf(x: IN BOOLEAN) RETURN STRING; - FUNCTION pf(x: IN CHARACTER) RETURN STRING; - FUNCTION pf(x: IN STD_ULOGIC) RETURN STRING; - FUNCTION pf(x: IN STRING) RETURN STRING; - FUNCTION pf(x: IN INTEGER) RETURN STRING; - FUNCTION pf(x: IN BIT_VECTOR) RETURN STRING; - FUNCTION pf(x: IN STD_ULOGIC_VECTOR) RETURN STRING; - FUNCTION pf(x: IN STD_LOGIC_VECTOR) RETURN STRING; - FUNCTION pf(x: IN TIME) RETURN STRING; - FUNCTION pf(x: IN REAL) RETURN STRING; - - -- FILE *fopen(const char *filename, const char *mode); - IMPURE FUNCTION fopen(filename: IN STRING; mode: IN STRING) RETURN CFILE; - -- int fflush(FILE *stream); - PROCEDURE fflush(stream: IN CFILE); - -- int fclose(FILE *stream); - PROCEDURE fclose(stream: IN CFILE); - - -- int fputc(int c, FILE *stream); - PROCEDURE fputc(c: IN character; stream: IN CFILE); - -- int fputs(const char *s, FILE *stream); - PROCEDURE fputs(s: IN STRING; stream: IN CFILE); - PROCEDURE fputs(s: INOUT LINE; stream: IN CFILE); --will deallocate(s) - -- int putc(int c, FILE *stream); - PROCEDURE putc(c: IN character; stream: IN CFILE); - -- int putchar(int c); - PROCEDURE putchar(c: IN character); - -- int puts(const char *s); - PROCEDURE puts(s: IN STRING); - PROCEDURE puts(s: INOUT LINE); --will deallocate(s) - - -- int feof(FILE *stream); - IMPURE FUNCTION feof(stream: IN CFILE) RETURN BOOLEAN; - -- int fgetc(FILE *stream); - IMPURE FUNCTION fgetc(stream: IN CFILE) RETURN CHARACTER; - -- char *fgets(char *s, int size, FILE *stream); - PROCEDURE fgets(s: OUT STRING; n: IN INTEGER; stream: IN CFILE); - -- int getc(FILE *stream); - IMPURE FUNCTION getc(stream: IN CFILE) RETURN CHARACTER; - -- int getchar(void); - IMPURE FUNCTION getchar RETURN CHARACTER; - -- char *gets(char *s); - PROCEDURE gets(s: OUT STRING); - -- int ungetc(int c, FILE *stream); - PROCEDURE ungetc(c: IN character; stream: IN CFILE); - - PROCEDURE sbufprintf(fi: INOUT INTEGER; sbuf: INOUT LINE; stream: IN CFILE; - fmt: IN STRING; s: IN STRING); --used only for testing package - - PROCEDURE sbufscanf(fi: INOUT INTEGER; sbuf: INOUT LINE; stream: IN CFILE; - fmt: IN STRING; s: INOUT LINE); --used only for testing package - - PROCEDURE fprintf(stream: IN CFILE; format: IN STRING; a1: INOUT LINE); - PROCEDURE printf( format: IN STRING; a1: INOUT LINE); - PROCEDURE fscanf( stream: IN CFILE; format: IN string; a1: INOUT LINE); - PROCEDURE scanf( format: IN string; a1: INOUT LINE); - PROCEDURE sscanf( s: IN string; format: IN string; a1: INOUT LINE); - - - PROCEDURE fprintf(stream: IN CFILE; - format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " "); - - PROCEDURE fprintf(stream: IN CFILE; - format: IN STRING; - a1: IN STD_LOGIC_VECTOR; - a2, a3, a4, a5, a6, a7, a8 : IN STD_LOGIC_VECTOR := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN STD_LOGIC_VECTOR := "U"); - - PROCEDURE printf( format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " "); - - PROCEDURE printf( format: IN STRING; - a1: IN STD_LOGIC_VECTOR; - a2, a3, a4, a5, a6, a7, a8 : IN STD_LOGIC_VECTOR := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN STD_LOGIC_VECTOR := "U"); - - PROCEDURE sprintf(s: INOUT LINE; format: IN STRING; --Append to variable s - a1, a2, a3, a4, a5, a6, a7, a8 : IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " "); - - PROCEDURE sprintf(s: INOUT STRING; format: IN STRING; --Overwrite variable s - a1, a2, a3, a4, a5, a6, a7, a8 : IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " "); - - PROCEDURE sprintf(s: INOUT STRING; format: IN STRING; - a1: IN STD_LOGIC_VECTOR; - a2, a3, a4, a5, a6, a7, a8 : IN STD_LOGIC_VECTOR := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN STD_LOGIC_VECTOR := "U"); - - - PROCEDURE printf(format: IN string; a1: integer); - - PROCEDURE printf(format: IN string; a1: std_logic); - - PROCEDURE printf(format: IN string; a1: boolean); - - PROCEDURE printf(format: IN string; a1: bit); - - PROCEDURE printf(format: IN string; a1: bit_vector); - - PROCEDURE printf(format: IN string; a1: time); - - PROCEDURE printf(format: IN string; a1: real); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: integer); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: std_logic); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: boolean); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: bit); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: bit_vector); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: time); - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: real); - - PROCEDURE scanf(format: IN string; a1: INOUT string); - - PROCEDURE scanf(format: IN string; a1: INOUT integer); - - PROCEDURE scanf(format: IN string; a1: INOUT std_logic); - - PROCEDURE scanf(format: IN string; a1: INOUT std_logic_vector); - - PROCEDURE scanf(format: IN string; a1: INOUT boolean); - - PROCEDURE scanf(format: IN string; a1: INOUT bit); - - PROCEDURE scanf(format: IN string; a1: INOUT bit_vector); - - PROCEDURE scanf(format: IN string; a1: INOUT time); - - PROCEDURE scanf(format: IN string; a1: INOUT real); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT string); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT integer); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT std_logic); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT std_logic_vector); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT boolean); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT bit); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT bit_vector); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT time); - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT real); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT string); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT integer); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT std_logic); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT std_logic_vector); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT boolean); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT bit); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT bit_vector); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT time); - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT real); - ---------------------------------------------------------------------------------------------------------- --- end stdio_h; ---------------------------------------------------------------------------------------------------------- - -end vhdl_c_pkg_tb; - - - -PACKAGE BODY vhdl_c_pkg_tb IS - ---------------------------------------------------------------------------------------------------------- ---PACKAGE BODY endian_h IS ---------------------------------------------------------------------------------------------------------- - - FUNCTION to_bigendian_bit_vector(x: IN BIT_VECTOR) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(x'HIGH DOWNTO x'LOW); --big endian: HIGH DOWNTO LOW - BEGIN - FOR i IN x'RANGE LOOP y(i) := x(i); END LOOP; - RETURN y; - END to_bigendian_bit_vector; - - FUNCTION to_littleendian_bit_vector(x: IN BIT_VECTOR) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(x'LOW TO x'HIGH); --little endian: LOW TO HIGH - BEGIN - FOR i IN x'RANGE LOOP y(i) := x(i); END LOOP; - RETURN y; - END to_littleendian_bit_vector; - - FUNCTION to_littleendian_bit_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(0 TO n-1); VARIABLE c: bit:='0'; --carry - VARIABLE ax, j: INTEGER; - BEGIN - ax:=x; IF ax<0 THEN ax:=-ax; c:='1'; END IF; - FOR i IN y'LOW TO y'HIGH LOOP - j:=ax MOD 2; ax:=ax/2; - IF x<0 THEN - IF j=0 THEN y(i):='1'; ELSE y(i):=c; c:='0'; END IF; - ELSE - IF j=0 THEN y(i):='0'; ELSE y(i):='1'; END IF; - END IF; - END LOOP; - ASSERT ax=0 AND c='0' - REPORT "bit_vector_bigendian(x, n) bit length too small" - SEVERITY WARNING; - RETURN y; - END to_littleendian_bit_vector; - - FUNCTION to_bigendian_bit_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN BIT_VECTOR IS - VARIABLE v: BIT_VECTOR(0 TO n-1); VARIABLE y: BIT_VECTOR(n-1 DOWNTO 0); - BEGIN - v := to_littleendian_bit_vector(x, n); - y := to_bigendian_bit_vector(v); - RETURN y; - END to_bigendian_bit_vector; - - FUNCTION to_bigendian_std_logic_vector(x: IN BIT_VECTOR) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'HIGH DOWNTO x'LOW); --big endian: HIGH DOWNTO LOW - BEGIN - FOR i IN x'RANGE LOOP IF x(i)='1' THEN y(i):='1'; ELSE y(i):='0'; END IF; END LOOP; - RETURN y; - END to_bigendian_std_logic_vector; - - FUNCTION to_littleendian_std_logic_vector(x: IN BIT_VECTOR) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'LOW TO x'HIGH); --little endian: LOW TO HIGH - BEGIN - FOR i IN x'RANGE LOOP IF x(i)='1' THEN y(i):='1'; ELSE y(i):='0'; END IF; END LOOP; - RETURN y; - END to_littleendian_std_logic_vector; - - FUNCTION to_bigendian_std_logic_vector(x: IN std_logic_vector) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'HIGH DOWNTO x'LOW); --big endian: HIGH DOWNTO LOW - BEGIN - FOR i IN x'RANGE LOOP y(i) := x(i); END LOOP; - RETURN y; - END to_bigendian_std_logic_vector; - - FUNCTION to_littleendian_std_logic_vector(x: IN std_logic_vector) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'LOW TO x'HIGH); --little endian: LOW TO HIGH - BEGIN - FOR i IN x'RANGE LOOP y(i) := x(i); END LOOP; - RETURN y; - END to_littleendian_std_logic_vector; - - FUNCTION to_littleendian_std_logic_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN STD_LOGIC_VECTOR IS - VARIABLE v: BIT_VECTOR(0 TO n-1); VARIABLE y: STD_LOGIC_VECTOR(n-1 DOWNTO 0); - BEGIN - v := to_littleendian_bit_vector(x, n); - y := to_littleendian_std_logic_vector(v); - RETURN y; - END to_littleendian_std_logic_vector; - - FUNCTION to_bigendian_std_logic_vector(x: IN INTEGER; n: IN INTEGER:=32) RETURN STD_LOGIC_VECTOR IS - VARIABLE v: BIT_VECTOR(0 TO n-1); VARIABLE y: STD_LOGIC_VECTOR(n-1 DOWNTO 0); - BEGIN - v := to_littleendian_bit_vector(x, n); - y := to_bigendian_std_logic_vector(v); - RETURN y; - END to_bigendian_std_logic_vector; - - - - FUNCTION to_bigendian_bit_vector_string(x: IN STRING) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(x'LENGTH-1 DOWNTO 0); --big endian: HIGH DOWNTO LOW - BEGIN - FOR i IN x'RANGE LOOP - IF x(i)='1' THEN y(x'LENGTH-i):='1'; ELSE y(x'LENGTH-i):='0'; END IF; - END LOOP; - RETURN y; - END to_bigendian_bit_vector_string; - - FUNCTION to_littleendian_bit_vector_string(x: IN STRING) RETURN BIT_VECTOR IS - VARIABLE y: BIT_VECTOR(0 TO x'LENGTH-1); --little endian: LOW TO HIGH - BEGIN - FOR i IN x'RANGE LOOP - IF x(i)='1' THEN y(x'LENGTH-i):='1'; ELSE y(x'LENGTH-i):='0'; END IF; - END LOOP; - RETURN y; - END to_littleendian_bit_vector_string; - - FUNCTION to_bigendian_std_logic_vector_string(x: IN STRING) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(x'LENGTH-1 DOWNTO 0); VARIABLE s: std_logic; - BEGIN - FOR i IN x'RANGE LOOP - CASE x(i) IS - WHEN '1' => s:='1'; WHEN '0' => s:='0'; - WHEN 'X'|'x'=> s:='X'; - WHEN 'Z'|'z'=> s:='Z'; WHEN 'W'|'w'=> s:='W'; - WHEN 'H'|'h'=> s:='H'; WHEN 'L'|'l'=> s:='L'; - WHEN '-' => s:='-'; WHEN others => s:='U'; - END CASE; - y(x'LENGTH-i):=s; - END LOOP; - RETURN y; - END to_bigendian_std_logic_vector_string; - - FUNCTION to_littleendian_std_logic_vector_string(x: IN STRING) RETURN std_logic_vector IS - VARIABLE y: std_logic_vector(0 TO x'LENGTH-1); VARIABLE s: std_logic; - BEGIN - FOR i IN x'RANGE LOOP - CASE x(i) IS - WHEN '1' => s:='1'; WHEN '0' => s:='0'; - WHEN 'X'|'x'=> s:='X'; - WHEN 'Z'|'z'=> s:='Z'; WHEN 'W'|'w'=> s:='W'; - WHEN 'H'|'h'=> s:='H'; WHEN 'L'|'l'=> s:='L'; - WHEN '-' => s:='-'; WHEN others => s:='U'; - END CASE; - y(x'LENGTH-i):=s; - END LOOP; - RETURN y; - END to_littleendian_std_logic_vector_string; - ---------------------------------------------------------------------------------------------------------- ---END endian_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package body ctype_h is ---------------------------------------------------------------------------------------------------------- - - function isalpha(c: character) return boolean is - begin - return t(character'pos(c)) mod 5 = 0 OR t(character'pos(c)) mod 7 = 0; - end isalpha; - - function isupper(c: character) return boolean is - begin - return t(character'pos(c)) mod 5 = 0; - end isupper; - - function islower(c: character) return boolean is - begin - return t(character'pos(c)) mod 7 = 0; - end islower; - - function isdigit(c: character) return boolean is - begin - return t(character'pos(c)) mod 13 = 0; - end isdigit; - - function isxdigit(c: character) return boolean is - begin - return t(character'pos(c)) mod 3 = 0; - end isxdigit; - - function isalnum(c: character) return boolean is - begin - return t(character'pos(c)) mod 3 = 0 - OR t(character'pos(c)) mod 5 = 0 - OR t(character'pos(c)) mod 7 = 0; - end isalnum; - - function isspace(c: character) return boolean is - begin - return t(character'pos(c)) mod 11 = 0; - end isspace; - - function ispunct(c: character) return boolean is - begin - return t(character'pos(c)) mod 17 = 0; - end ispunct; - - function isprint(c: character) return boolean is - begin - return t(character'pos(c)) mod 3 = 0 - OR t(character'pos(c)) mod 5 = 0 - OR t(character'pos(c)) mod 7 = 0 - OR t(character'pos(c)) mod 17 = 0 - OR c=' '; - end isprint; - - function isgraph(c: character) return boolean is - begin - return t(character'pos(c)) mod 3 = 0 - OR t(character'pos(c)) mod 5 = 0 - OR t(character'pos(c)) mod 7 = 0 - OR t(character'pos(c)) mod 17 = 0; - end isgraph; - - function iscntrl(c: character) return boolean is - begin - return t(character'pos(c)) mod 2 = 0; - end iscntrl; - - function isascii(c: character) return boolean is - begin - return character'pos(c) >= 0 and character'pos(c)<=127; - end isascii; - - function tolower(c: character) return character is - begin - if character'pos(c)>=65 AND character'pos(c)<=90 then - return character'val(character'pos(c)+32); - else - return c; - end if; - end tolower; - - function toupper(c: character) return character is - begin - if character'pos(c)>=97 AND character'pos(c)<=122 then - return character'val(character'pos(c)-32); - else - return c; - end if; - end toupper; - ---------------------------------------------------------------------------------------------------------- --- end ctype_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package body strings_h is ---------------------------------------------------------------------------------------------------------- - - --Added Because ModelSim write(buf, s); will copy beyond NUL until s'length - procedure strcat(d: INOUT line; s: IN string) is - variable sj: integer:=s'left; - begin - if s'length>0 then - loop - if s(sj)=NUL then exit; end if; - write(d, s(sj)); - - if ( s'left > s'right ) then - if sj<=s'right then exit; end if; - sj:=sj-1; - else - if sj>=s'right then exit; end if; - sj:=sj+1; - end if; - end loop; - end if; - end strcat; - - procedure strcpy(d: OUT string; s: IN string) is - variable dj: integer:=d'left; - variable sj: integer:=s'left; - --variable W : line; - begin - --write(W,string'("strcpy: ")); - --write(W,string'(" s=")); write(W,s); - --write(W,string'(" s'left=")); write(W,s'left); - --write(W,string'(" s'right=")); write(W,s'right); - --write(W,string'(" s'length=")); write(W,s'length); - --write(W,string'(" d'left=")); write(W,d'left); - --write(W,string'(" d'right=")); write(W,d'right); - --write(W,string'(" d'length=")); write(W,d'length); - --writeline(output, W); - - if s'length<=0 then - if d'length>=1 then d(d'left):=NUL; end if; - else - loop - --write(W,string'(" s(")); write(W,sj); - --write(W,string'(")=")); write(W,s(sj)); - --write(W,string'(" dj=")); write(W,dj); - --writeline(output,W); - - if s(sj)=NUL then d(dj):=NUL; exit; end if; - d(dj):=s(sj); - if ( d'left > d'right ) then - if dj<=d'right then exit; end if; - dj:=dj-1; - else - if dj>=d'right then exit; end if; - dj:=dj+1; - end if; - if ( s'left > s'right ) then - if sj<=s'right then d(dj):=NUL; exit; end if; - sj:=sj-1; - else - if sj>=s'right then d(dj):=NUL; exit; end if; - sj:=sj+1; - end if; - end loop; - end if; - end strcpy; - - procedure strcpy(d: OUT string; s: IN string; si: IN integer) is - variable dj: integer:=d'left; - variable sj: integer:=si; --Synopsys does not support BUFFER (pass by value) - begin - loop - if dj>d'right then d(d'right):=NUL; exit; end if; - if sj>s'right then d(dj):=NUL; exit; end if; - if s(sj)=NUL then d(dj):=NUL; exit; end if; - d(dj):=s(sj); dj:=dj+1; sj:=sj+1; - end loop; - end strcpy; -- procedure; johan - - - procedure strcpy(d: INOUT string; di: IN integer; s: IN string) is - begin strcpy(d, di, s, 1); end strcpy; -- procedure; johan - - --Make it easy to translate back to C: strcpy(d+di, s+si) - procedure strcpy(d: INOUT string; di: IN integer; s: IN string; si: IN integer) is - variable dj: integer:=di; --Synopsys does not support BUFFER - variable sj: integer:=si; --Synopsys does not support BUFFER (pass by value) - begin - loop - if dj>d'right then d(d'right):=NUL; exit; end if; - if sj>s'right then d(dj):=NUL; exit; end if; - if s(sj)=NUL then d(dj):=NUL; exit; end if; - d(dj):=s(sj); dj:=dj+1; sj:=sj+1; - end loop; - end strcpy; -- procedure; johan - - - procedure strcat(d: INOUT string; di: IN integer; s: IN string; si: IN integer) is - variable dj: integer:=di; - variable sj: integer:=si; - begin - --strcpy(d, strlen(d)+1, s, si); - loop - if dj>d'right then d(d'right):=NUL; exit; end if; - if d(dj)=NUL then exit; end if; - dj:=dj+1; - end loop; - - loop - if dj>d'right then d(d'right):=NUL; exit; end if; - if sj>s'right then d(dj):=NUL; exit; end if; - if s(sj)=NUL then d(dj):=NUL; exit; end if; - d(dj):=s(sj); dj:=dj+1; sj:=sj+1; - end loop; - end strcat; -- procedure; johan - - procedure strcat(d: INOUT string; di: IN integer; s: IN string) is - begin strcat(d, di, s, 1); end strcat; - - procedure strcat(d: INOUT string; s: IN string; si: IN integer) is - begin strcat(d, 1, s, si); end strcat; - - procedure strcat(d: INOUT string; s: IN string) is - begin strcat(d, 1, s, 1); end strcat; - - - function strcmp(d: IN string; s: IN string) return integer is - variable i: integer:=1; variable dc, sc: character; - begin - loop - if i<=d'right then dc:=d(i); else dc:=NUL; end if; - if i<=s'right then sc:=s(i); else sc:=NUL; end if; - - - if dc/=sc or dc=NUL then - return character'pos(dc) - character'pos(sc); - else - i:=i+1; - end if; - end loop; - end strcmp; - - function strlen(s: IN string) return integer is - variable n: integer:=0; variable sj: integer:=s'left; - begin - loop - if sj>s'right then exit; - elsif s(sj)=NUL then exit; --sequential if protects sj > length - else sj:=sj+1; n:=n+1; - end if; - end loop; - return n; - end strlen; - - function strlen(s: IN string; si: IN integer) return integer is - variable n: integer:=0; variable sj: integer:=si; - begin - loop - if sj>s'right then exit; - elsif s(sj)=NUL then exit; --sequential if protects sj > length - else sj:=sj+1; n:=n+1; - end if; - end loop; - return n; - end strlen; - - procedure strcpy( d: OUT string; s: IN character) is - variable cs: string(1 to 2); - begin - cs(1):=s; cs(2):=NUL; strcpy(d, cs); - end strcpy; -- johan - - procedure strcat( d: INOUT string; s: IN character) is - variable cs: string(1 to 2); - begin - cs(1):=s; cs(2):=NUL; strcat(d, cs); - end strcat; -- strcat - - -- d(1 to j-i+1):=s(i to j) - -- strcpy(d, s(i to j)); - procedure strcpyij(d: OUT string; s: IN string; i, j: IN integer) is - variable di: integer:=1; - variable si: integer:=i; - begin - loop - if di>d'right then d(d'right):=NUL; exit; end if; - if si>s'right then d(di):=NUL; exit; end if; - if s(si)=NUL then d(di):=NUL; exit; end if; - if si>j then d(di):=NUL; exit; end if; --added on to strcpy - d(di):=s(si); di:=di+1; si:=si+1; - end loop; - end strcpyij; -- procedure; johan - ---------------------------------------------------------------------------------------------------------- --- end strings_h; -- johan ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package body stdlib_h is ---------------------------------------------------------------------------------------------------------- - procedure strtoul(result: OUT integer; --natural - s: IN string; si: IN integer; - endptr: INOUT integer; base:IN integer) IS - - variable p: integer:=si; - variable f: integer:=0; --actual digits flag hit - variable d: integer; - variable b: integer:=base; - variable r: integer; - begin - r:=0; - while p<=s'length loop - if isspace(s(p)) then p:=p+1; else exit; end if; - end loop; - - if b=0 then --auto detect base - if p<=s'length then - if s(p)='0' then - p:=p+1; - if p<=s'length then - if s(p)='x' OR s(p)='X' then - p:=p+1; b:=16; - else - f:=1; b:=8; - end if; - end if; - else - b:=10; - end if; - end if; - elsif b=16 then - if p=b then exit; end if; - r:=(b*r)+d; f:=1; p:=p+1; - end loop; - - if f=0 then p:=si; end if; - - if endptr/=0 then endptr:=p; end if; - - result:=r; - end strtoul; - - procedure strtoul(result: OUT integer; --natural - s: IN string; - endptr: INOUT integer; base:IN integer) IS - begin - strtoul(result, s, 1, endptr, base); - end strtoul; - - procedure strtol(result: OUT integer; --natural - s: IN string; si: IN integer; - endptr: INOUT integer; base:IN integer) IS - variable r: integer:=0; - variable p: integer:=si; - begin - while p<=s'length loop - if isspace(s(p)) then p:=p+1; else exit; end if; - end loop; - - if p<=s'length then - if s(p)='-' then - p:=p+1; strtoul(r, s, p, endptr, base); result:= -r; - - else - if s(p)='+' then p:=p+1; end if; - strtoul(r, s, p, endptr, base); result:=r; - end if; - end if; - - if r=0 AND endptr/=0 AND endptr=p then endptr:=si; end if; - end strtol; - - procedure strtol(result: OUT integer; --natural - s: IN string; - endptr: INOUT integer; base:IN integer) IS - begin - strtol(result, s, 1, endptr, base); - end strtol; - - function atoi(s: IN string) return integer is - variable result, p: integer:=0; - begin - strtol(result, s, 1, p, 10); return result; - end atoi; - - function atol(s: IN string) return integer is - variable result, p: integer:=0; - begin - strtol(result, s, 1, p, 10); return result; - end atol; - ---------------------------------------------------------------------------------------------------------- --- end stdlib_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- package body regexp_h is ---------------------------------------------------------------------------------------------------------- --- For instance, `[^]0-9-]' means the set `everything except close --- bracket, zero through nine, and hyphen'. - - function mfalse(m: integer) return integer is - begin - if m=1 then return 0; elsif m=0 then return -2; else return m; end if; - end; - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; - f: IN string; m1,m2,m3,m4: OUT string) is - - variable debug: boolean:=false; --TRUE; - - type tarray is array(integer range <>) of bit; - variable t: tarray(0 to 256); - variable tset: bit; - - type iarray is array(integer range <>) of integer; - variable fstack: iarray(1 to 15); --stack of format pointer - variable mstack: iarray(1 to 15); --stack of match flags - variable mistack: iarray(1 to 15); --stack of mi match left parenthesis - variable sstack: iarray(1 to 15); --stack of string pointers - variable sp: integer; - - variable aii: integer:=0; - variable si_in: integer; - variable simax: integer:=1; --debugging information - variable fi: integer; - variable m: integer; --=0 false, 1=true, -1=skip true, -2=skip false - variable mi: integer:=0; - variable ms: string(1 to 80); - variable fb,mc,j: integer; - variable mr,mm,mn: integer; - variable mlast: integer; - variable b, c: character; - variable bi, ci: integer; - variable W: line; - begin - if debug then - write(W, string'("------------------------------------------")); - write(W, string'(" string=")); write(W, s); - write(W, string'(" si=")); write(W, si); - write(W, string'(" string'length=")); write(W, s'length); - write(W, string'(" format=")); write(W, f); - writeline(output, W); - end if; - - si_in:=si; --si:=1; - fi:=0; sp:=1; m:=1; - sstack(1):=si; fstack(1):=1; mstack(1):=1; mistack(1):=0; - sstack(2):=si; fstack(2):=1; mstack(2):=1; mistack(2):=0; - loop - fi:=fi+1; if fi>f'length then exit; end if; - mc:=0; mr:=0; tset:='1'; t:=(others=>'0'); - - if debug then - write(W, string'(" loop:ai=")); write(W, aii); - write(W, string'(" m=")); write(W, m); - write(W, string'(" f(")); write(W, fi); write(W, string'(")=")); - write(W, f(fi)); - writeline(output, W); - write(W, string'(" s(")); write(W, si); write(W, string'(")=")); - if si<=s'length then write(W, s(si)); else write(W, string'("UUU")); end if; - write(W, string'(" mstack(")); write(W, sp); write(W, string'(")=")); write(W, mstack(sp)); - write(W, string'(" sstack(")); write(W, sp); write(W, string'(")=")); write(W, sstack(sp)); - writeline(output, W); - end if; - - case f(fi) is - when '^' => --Match beginning of line - if si/=si_in then m:=mfalse(m); end if; - - when '$' => --Match end of line - if si<=s'length then if s(si)/=NUL then m:=mfalse(m); end if; - elsif si/=(s'length+1) then m:=mfalse(m); end if; - - when '*' => --Match last expression 0 or more times - if m=1 then fi:=fstack(sp+1)-1; - elsif m=0 then - m:=mstack(sp+1); si:=sstack(sp+1); - if si>simax then simax:=si; end if; - end if; - - when '?' => --Match last expression 0 or 1 times - if m= 0 then - m:=mstack(sp+1); si:=sstack(sp+1); --ab?c\(def?g?h\)? - if si>simax then simax:=si; end if; --- elsif m=-1 then m:=-1; --looking for right parenthesis --- elsif m=-2 then m:=-2; --looking for alternate-bar or right - end if; - - --[character pattern] - --Examples: [abc], []], [^abc], [0-9-], [^]], [^]abc], [^^] - when '[' => - mc:=1; if m=1 then fstack(sp+1):=fi; end if; --needed for 0 or more operator - fb:=fi; - loop - fi:=fi+1; if fi>f'length then exit; end if; - - if debug then - write(W, string'(" [char pattern]:f(")); write(W, fi); - write(W, string'(")=")); write(W, f(fi)); - writeline(output, W); - end if; - - b:=c; c:=f(fi); - - --To include a close bracket in the set, - --make it the first character after the open bracket - --or the circumflex; any other position will end the set. - --Examples: []] or the NOT cases: [^]] or [^]abc] or [^^] - - if c='\' then - fi:=fi+1; if fi>f'length then exit; end if; - - case f(fi) is - when 'a' => t(character'pos(BEL)):=tset; - when 'b' => t(character'pos(BS)):=tset; - when 'f' => t(character'pos(FF)):=tset; - when 'n' => t(character'pos(LF)):=tset; - when 'r' => t(character'pos(CR)):=tset; - when 't' => t(character'pos(HT)):=tset; - when 'v' => t(character'pos(VT)):=tset; - when '\' => t(character'pos('\')):=tset; - when others => t(character'pos(f(fi))):=tset; - end case; - - elsif c='^' then - if fb+1=fi then tset:='0'; t:=(others=>'1'); - else t(character'pos(c)):=tset; end if; - - elsif c=']' then - if (fb+1=fi and tset='1') or (fb+2=fi and tset='0') then - t(character'pos(c)):=tset; - else - exit; - end if; - - elsif c='-' then - fi:=fi+1; if fi>f'length then exit; end if; --lookahead - - -- To include a hyphen, make it the last character - -- before the final close bracket: [9-] or [---] or [-9]. - if f(fi)=']' then - t(character'pos(c)):=tset; fi:=fi-1; - else - bi:=character'pos(b); ci:=character'pos(f(fi)); - for ti in bi to ci loop t(ti):=tset; end loop; - end if; - else - t(character'pos(c)):=tset; - end if; - end loop; - - when NUL => aii:=aii+1; exit; - - when '(' => sp:=sp+1; - sstack(sp):=si; fstack(sp):=fi-1; mstack(sp):=m; - mi:=mi+1; mistack(sp):=mi; - - when ')' => - if m=1 then - strcpyij(ms, s, sstack(sp), si-1); - case mistack(sp) is - when 1 => strcpy(m1, ms); - when 2 => strcpy(m2, ms); - when 3 => strcpy(m3, ms); - when 4 => strcpy(m4, ms); - when others => - end case; - end if; - - if debug then - write(W, string'(" (Right):store: m=")); write(W, m); - write(W, string'(" ms=")); write(W, ms); - write(W, string'(" mistack(sp)=")); write(W, mistack(sp)); - write(W, string'(" sstack(")); write(W, sp); - write(W, string'(")=")); write(W, sstack(sp)); - write(W, string'(" si=")); write(W, si); - writeline(output, W); - end if; - - sp:=sp-1; - if m=-1 then m:=1; --implies an alternate-bar was encountered - elsif m=0 or m=-2 then - m:=0; si:=sstack(sp); - if si>simax then simax:=si; end if; - end if; - - when '{' => - when '}' => - when '|' => if m=1 then - strcpyij(ms, s, sstack(sp), si-1); - case mistack(sp) is - when 1 => strcpy(m1, ms); - when 2 => strcpy(m2, ms); - when 3 => strcpy(m3, ms); - when 4 => strcpy(m4, ms); - when others => - end case; - end if; - - if debug then - write(W, string'(" Bar|:store: m=")); write(W, m); - write(W, string'(" ms=")); write(W, ms); - write(W, string'(" mistack(sp)=")); write(W, mistack(sp)); - write(W, string'(" sstack(")); write(W, sp); - write(W, string'(")=")); write(W, sstack(sp)); - write(W, string'(" si=")); write(W, si); - writeline(output, W); - end if; - - if sp=1 then - mi:=0; aii:=aii+1; if m=1 then exit; end if; --break out early - end if; - - if m=1 then m:=-1; --looking for next grouping parenthesis - elsif m=0 or m=-2 then - m:=mstack(sp); si:=sstack(sp); - if si>simax then simax:=si; end if; - end if; - - when '\' => - fi:=fi+1; if fi>f'length then exit; end if; - - if debug then - write(W, string'(" f(")); write(W, fi); - write(W, string'(")=")); write(W, f(fi)); - writeline(output, W); - end if; - - case f(fi) is - when others => - t(character'pos(f(fi))):='1'; - mc:=1; if m=1 then fstack(sp+1):=fi; end if; - end case; - - when '.' => --match any character except NUL - t:=(others=>'1'); --t(character'pos(LF)):='0'; --differ from sed - mc:=1; if m=1 then fstack(sp+1):=fi; end if; - - when others => - t(character'pos(f(fi))):='1'; - mc:=1; if m=1 then fstack(sp+1):=fi; end if; - - end case; - - if mc=1 then - if m=0 then m:=-2; --skip characters - elsif m=1 then - sstack(sp+1):=si; mstack(sp+1):=m; - - t(character'pos(NUL)):='0'; - if si<=s'length then - if debug then - write(W, string'("match: s(")); write(W, si); - write(W, string'(")=")); write(W, s(si)); - write(W, string'(" with t(s(si))=")); write(W, t(character'pos(s(si)))); - writeline(output, W); - end if; - - if t(character'pos(s(si)))='1' then si:=si+1; else m:=0; end if; - if si>simax then simax:=si; end if; - else - m:=0; - end if; - end if; - end if; - end loop; - - --next unmatched character: si - if m=1 or m=-1 then ai:=aii; else ai:=0; si:=si_in; end if; --- --- si:=-simatch; --last good character before it went bad --- if si>simax then simatch:=-si; else simatch:=-simax; end if; --- - end; - - procedure regmatch(ai: OUT integer; si: INOUT integer; s: IN string; f: IN string) is - variable m1,m2,m3,m4: string(1 to 80); - begin - regmatch(ai, si, s, f, m1, m2, m3, m4); - end; - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; f: IN string; m1: OUT string) is - variable m2,m3,m4: string(1 to 80); - begin - regmatch(ai, si, s, f, m1, m2, m3, m4); - end; - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; f: IN string; m1,m2: OUT string) is - variable m3,m4: string(1 to 80); - begin - regmatch(ai, si, s, f, m1, m2, m3, m4); - end; - - procedure regmatch(ai: OUT integer; - si: INOUT integer; s: IN string; f: IN string; m1,m2,m3: OUT string) is - variable m4: string(1 to 80); - begin - regmatch(ai, si, s, f, m1, m2, m3, m4); - end; - - --conversion of scanf to sed - function sedscanf(s: IN string) return string is - variable i: integer:=0; - variable white: string(1 to 8):= "[ \t\n]*"; --zero or more white space - variable r: string(1 to 256); - begin - strcpy(r, NUL); - loop - i:=i+1; - if i>s'length then exit; end if; - if s(i)=NUL then exit; end if; - - if s(i)='%' then - i:=i+1; - if i>s'length then exit; end if; - if s(i)=NUL then exit; end if; - - case s(i) is - when 'x' => - strcat(r, white); strcat(r, "\(0[xX][0-9A-Fa-f][0-9A-Fa-f]*\|[0-9A-Fa-f][0-9A-Fa-f]*\)"); - when 'o' => - strcat(r, white); strcat(r, "\(0[0-7][0-7]*\)"); - when 'd' => - strcat(r, white); strcat(r, "\([0-9][0-9]*\)"); - when 's' => - strcat(r, white); strcat(r, "\([^ \t\n]*\)"); - when '%' => - strcat(r, "%"); - when others => - end case; - - elsif s(i)=' ' then strcat(r, white); - else - strcat(r, s(i)); - end if; - end loop; - return r; - end; ---------------------------------------------------------------------------------------------------------- --- end regexp_h; ---------------------------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- --- PACKAGE BODY stdio_h IS ---------------------------------------------------------------------------------------------------------- - TYPE pf_std_logic_vector_type IS array(std_ulogic) OF CHARACTER; - CONSTANT pf_std_logic_vector: pf_std_logic_vector_type - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - TYPE pf_hex_type IS array(0 to 15) OF CHARACTER; - CONSTANT pf_hex: pf_hex_type - := ('0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f'); - CONSTANT pf_hexx: pf_hex_type - := ('0','1','2','3','4','5','6','7','8','9','A','B','C','C','E','F'); - - TYPE pf_hex2_type IS array(0 to 15) of STRING(1 to 4); - CONSTANT pf_hex2: pf_hex2_type - := ("0000","0001","0010","0011","0100","0101","0110","0111", --fix 20030425 - "1000","1001","1010","1011","1100","1101","1110","1111"); --fix 20030425 - - - FUNCTION pf(x: IN bit) RETURN STRING IS - VARIABLE s: STRING(1 TO 1); - BEGIN - IF x='1' THEN s(1):='1'; ELSE s(1):='0'; END IF; RETURN s; - END pf; - - FUNCTION pf(x: IN BOOLEAN) RETURN STRING IS - VARIABLE s: STRING(1 TO 1); - BEGIN - IF x THEN s(1):='1'; ELSE s(1):='0'; END IF; RETURN s; - END pf; - - FUNCTION pf(x: IN CHARACTER) RETURN STRING IS - VARIABLE s: STRING(1 TO 1); - BEGIN - s(1):=x; RETURN s; - END pf; - - FUNCTION pf(x: IN std_ulogic) RETURN STRING IS - VARIABLE s: STRING(1 TO 1); - BEGIN - s(1):=pf_std_logic_vector(x); RETURN s; - END pf; - - FUNCTION pf(x: IN STRING) RETURN STRING IS - BEGIN - RETURN x; - END pf; - - FUNCTION pf(x: IN INTEGER) RETURN STRING IS - VARIABLE y: STRING(1 TO 128); - VARIABLE c: CHARACTER:='0'; --carry - VARIABLE a, b, i, n: INTEGER; --n:=bit length+sign bit - BEGIN - a:=x; IF a<0 THEN a:=-a; c:='1'; END IF; - n:=1; WHILE a/=0 LOOP a:=a/2; n:=n+1; END LOOP; - a:=x; IF n>y'HIGH THEN n:=y'HIGH; END IF; - FOR i IN n DOWNTO 1 LOOP --big endian - b:=a MOD 2; a:=a/2; - IF x<0 THEN --2's complement - IF b=0 THEN y(i):='1'; ELSE y(i):=c; c:='0'; END IF; - ELSE - IF b=0 THEN y(i):='0'; ELSE y(i):='1'; END IF; - END IF; - END LOOP; - ASSERT a=0 AND c='0' - REPORT "pf(x: IN INTEGER) bit length too small" SEVERITY WARNING; - RETURN y(1 TO n); --return minimum number of bits to descibe integer - END pf; - - FUNCTION sf(s: IN STRING) RETURN INTEGER IS - VARIABLE i, ax, n, p: INTEGER; VARIABLE nflag: BOOLEAN:=FALSE; - BEGIN - ax:=0; n:=0; p:=1; --IF f='u' THEN p:=0; ELSE p:=1; END IF; - FOR i IN 1 TO s'LENGTH LOOP - CASE s(i) IS - WHEN NUL => EXIT; WHEN ' '|HT => --ignore blanks - WHEN '1' => IF p=1 THEN p:=0; nflag:=TRUE; --begin 2's complement - ELSE - IF nflag THEN ax:=2*ax; ELSE ax:=2*ax+1; END IF; - END IF; - WHEN OTHERS => IF p=1 THEN p:=0; - ELSE - IF nflag THEN ax:=2*ax+1; ELSE ax:=2*ax; END IF; - END IF; - END CASE; - END LOOP; - IF nflag THEN ax:=ax+1; END IF; --2's complement ax:=(NOT ax)+1; - RETURN ax; - END sf; - - FUNCTION pf(x: IN REAL) RETURN STRING IS - VARIABLE s: LINE; VARIABLE i, n: INTEGER; VARIABLE y: STRING(1 TO 128); - BEGIN - y(1):='0'; n:=1; --assume default - write(s, x); --use internal function - IF s/=NULL THEN - IF s'LENGTH>0 THEN - i:=1; WHILE i<=s'LENGTH LOOP - IF i<=y'LENGTH THEN y(i):=s(i); n:=i; END IF; i:=i+1; - END LOOP; - END IF; - END IF; - DEALLOCATE(s); RETURN y(1 TO n); --wish list: return ieee bit string - END pf; - - FUNCTION pf(x: IN bit_vector) RETURN STRING IS - VARIABLE y: STRING(1 TO x'LENGTH); VARIABLE j: INTEGER:=1; - BEGIN - FOR i IN x'HIGH DOWNTO x'LOW LOOP - IF x(i)='1' THEN y(j):='1'; ELSE y(j):='0'; END IF; j:=j+1; - END LOOP; - RETURN y; - END pf; - - FUNCTION pf(x: IN std_ulogic_vector) RETURN STRING IS - VARIABLE y: STRING(1 TO x'LENGTH); VARIABLE j: INTEGER:=1; - BEGIN - FOR i IN x'HIGH DOWNTO x'LOW LOOP - y(j) := pf_std_logic_vector(x(i)); j:=j+1; - END LOOP; - RETURN y; - END pf; - - FUNCTION pf(x: IN std_logic_vector) RETURN STRING IS - VARIABLE y: STRING(1 TO x'LENGTH); VARIABLE j: INTEGER:=1; - BEGIN - FOR i IN x'HIGH DOWNTO x'LOW LOOP - y(j) := pf_std_logic_vector(x(i)); j:=j+1; - END LOOP; - RETURN y; - END pf; - - FUNCTION pf(x: IN time) RETURN STRING IS - BEGIN - RETURN pf(INTEGER(x / 1 ns)); - END pf; - - IMPURE FUNCTION fopen(filename: IN STRING; mode: IN STRING) RETURN CFILE IS - VARIABLE buf: LINE; - VARIABLE m: INTEGER:=0; - VARIABLE fid: CFILE:=0; - VARIABLE fmode: FILE_OPEN_KIND; --READ_MODE, WRITE_MODE, APPEND_MODE; - VARIABLE fstat: FILE_OPEN_STATUS:=NAME_ERROR; --OPEN_OK, STATUS_ERROR, NAME_ERROR, MODE_ERROR; - BEGIN - IF streamlock THEN --handle concurrent calls to fopen - write(buf, STRING'("fopen: streamlock")); writeline(OUTPUT, buf); - WHILE streamlock LOOP m:=0; END LOOP; --symphonyeda has bug, cannot have empty loop - END IF; - streamlock:=TRUE; - - FOR i IN mode'RANGE LOOP - CASE mode(i) IS - WHEN 'r' => fmode:=READ_MODE; m:=m+1; - WHEN 'w' => fmode:=WRITE_MODE; m:=m+1; - WHEN 'a' => fmode:=APPEND_MODE; m:=m+1; - WHEN NUL => EXIT; - WHEN OTHERS => m:=-1; EXIT; - END CASE; - END LOOP; - - IF m=1 THEN - IF strcmp(filename,"/dev/tty")=0 OR strcmp(filename,"CON")=0 THEN - CASE fmode IS --unix shell commands also use the dash, "-" - WHEN READ_MODE => fid:=stdin; fstat:=OPEN_OK; - WHEN WRITE_MODE => fid:=stdout;fstat:=OPEN_OK; - WHEN APPEND_MODE => fid:=stdout;fstat:=OPEN_OK; - WHEN OTHERS => fstat:=NAME_ERROR; - END CASE; - ELSIF strcmp(filename,"/dev/null")=0 OR strcmp(filename,"NUL")=0 THEN - fid:=stdnul; fstat:=OPEN_OK; - ELSE - fid:=0; m:=strlen(filename); - FOR i IN streambusy'RANGE LOOP - IF NOT streambusy(i) THEN fid:=i; EXIT; END IF; - END LOOP; - CASE fid IS - WHEN 4 => file_open(fstat, streamfile4, filename(1 TO m), fmode); - WHEN 5 => file_open(fstat, streamfile5, filename(1 TO m), fmode); - WHEN 6 => file_open(fstat, streamfile6, filename(1 TO m), fmode); - WHEN 7 => file_open(fstat, streamfile7, filename(1 TO m), fmode); - WHEN 8 => file_open(fstat, streamfile8, filename(1 TO m), fmode); - WHEN 9 => file_open(fstat, streamfile9, filename(1 TO m), fmode); - WHEN OTHERS => fstat:=NAME_ERROR; - END CASE; - END IF; - ELSE - fstat:=MODE_ERROR; - END IF; - - IF fstat=OPEN_OK THEN - streambusy(fid):=TRUE; - ELSE - CASE fid IS --totally unexpected: must do for fstat error - WHEN 4 => file_close(streamfile4); - WHEN 5 => file_close(streamfile5); - WHEN 6 => file_close(streamfile6); - WHEN 7 => file_close(streamfile7); - WHEN 8 => file_close(streamfile8); - WHEN 9 => file_close(streamfile9); - WHEN OTHERS => - END CASE; - fid:=0; - END IF; - streamiob(fid).fstat:=fstat; streamiob(fid).fmode:=fmode; - - streamlock:=FALSE; - --write(buf, STRING'("fopen: file=")); write(buf, filename); - --write(buf, STRING'(" fid=")); write(buf, fid); writeline(OUTPUT, buf); - RETURN fid; - END fopen; - - PROCEDURE fflush(stream: IN CFILE) IS - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fflush()/fclose(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF streamiob(stream).fstat=OPEN_OK AND streamiob(stream).buf/=NULL THEN - IF (streamiob(stream).fmode=WRITE_MODE - OR streamiob(stream).fmode=APPEND_MODE) THEN - CASE stream IS --buf'LENGTH==0 is a newline - WHEN stdout => writeline(output, streamiob(stream).buf); - WHEN 3 => --/dev/null - WHEN 4 => writeline(streamfile4, streamiob(stream).buf); - WHEN 5 => writeline(streamfile5, streamiob(stream).buf); - WHEN 6 => writeline(streamfile6, streamiob(stream).buf); - WHEN 7 => writeline(streamfile7, streamiob(stream).buf); - WHEN 8 => writeline(streamfile8, streamiob(stream).buf); - WHEN 9 => writeline(streamfile9, streamiob(stream).buf); - WHEN OTHERS => - END CASE; - DEALLOCATE(streamiob(stream).buf); - END IF; - END IF; - END fflush; - - PROCEDURE fclose(stream: IN CFILE) IS - BEGIN - fflush(stream); - ASSERT streamiob(stream).fstat=OPEN_OK AND streambusy(stream)=TRUE - REPORT "fclose(): CFILE stream id is already closed" SEVERITY FAILURE; - CASE stream IS - WHEN 4 => file_close(streamfile4); streambusy(stream):=FALSE; - WHEN 5 => file_close(streamfile5); streambusy(stream):=FALSE; - WHEN 6 => file_close(streamfile6); streambusy(stream):=FALSE; - WHEN 7 => file_close(streamfile7); streambusy(stream):=FALSE; - WHEN 8 => file_close(streamfile8); streambusy(stream):=FALSE; - WHEN 9 => file_close(streamfile9); streambusy(stream):=FALSE; - WHEN OTHERS => - END CASE; - END fclose; - - PROCEDURE fputc(c: IN CHARACTER; stream: IN CFILE) IS - VARIABLE fid: INTEGER; - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fputc(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF stream/=stdnul THEN - IF c=LF THEN fflush(stream); ELSE write(streamiob(stream).buf, c); END IF; - END IF; - END fputc; - - PROCEDURE fputs(s: IN STRING; stream: IN CFILE) IS - VARIABLE i: INTEGER; VARIABLE n: INTEGER:=strlen(s); - BEGIN --inline fputc code FOR simulator efficiency - IF stream/=stdnul THEN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fputs(): passed in bad CFILE stream id" SEVERITY FAILURE; - FOR i IN 1 TO n LOOP - IF s(i)=LF THEN write(streamiob(stream).buf, string'("")); fflush(stream); - ELSE write(streamiob(stream).buf, s(i)); END IF; - END LOOP; - END IF; - END fputs; - - PROCEDURE fputs(s: INOUT LINE; stream: IN CFILE) IS - VARIABLE i: INTEGER; VARIABLE n: INTEGER:=0; - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fputs(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF stream/=stdnul THEN - IF s/=NULL THEN n:=strlen(s.all); END IF; --avoids Null access value dereferenced - FOR i IN 1 TO n LOOP - IF s(i)=LF THEN write(streamiob(stream).buf, string'("")); fflush(stream); - ELSE write(streamiob(stream).buf, s(i)); - END IF; - END LOOP; - END IF; - DEALLOCATE(s); --same behavior as write(FILE, LINE); - END fputs; - - PROCEDURE putc(c: IN CHARACTER; stream: IN CFILE) IS - BEGIN - fputc(c, stream); - END putc; - - PROCEDURE putchar(c: IN CHARACTER) IS - BEGIN - fputc(c, stdout); - END putchar; - - PROCEDURE puts(s: IN STRING) IS - BEGIN - fputs(s, stdout); fputc(LF, stdout); - END puts; - - PROCEDURE puts(s: INOUT LINE) IS - BEGIN - fputs(s, stdout); fputc(LF, stdout); - END puts; - - IMPURE FUNCTION feof(stream: IN CFILE) RETURN BOOLEAN IS - VARIABLE eof: BOOLEAN:=TRUE; - BEGIN - IF stream>0 AND stream<=streamNFILE THEN - IF streamiob(stream).fstat=OPEN_OK THEN - CASE stream IS - WHEN stdin => eof:=ENDFILE(INPUT); - WHEN 4 => eof:=ENDFILE(streamfile4); - WHEN 5 => eof:=ENDFILE(streamfile5); - WHEN 6 => eof:=ENDFILE(streamfile6); - WHEN 7 => eof:=ENDFILE(streamfile7); - WHEN 8 => eof:=ENDFILE(streamfile8); - WHEN 9 => eof:=ENDFILE(streamfile9); - WHEN OTHERS => eof:=TRUE; - END CASE; - END IF; - END IF; - RETURN eof; - END feof; - - IMPURE FUNCTION fgetc(stream: IN CFILE) RETURN CHARACTER IS - VARIABLE more: BOOLEAN:=FALSE; VARIABLE c: CHARACTER:=NUL; - VARIABLE b: LINE; --workaround for SymphonyEDA 2.3#8 - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "fgetc(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF stream>0 AND stream<=streamNFILE THEN - IF streamiob(stream).buf=NULL THEN more:=TRUE; - ELSE - b:=streamiob(stream).buf; IF b'LENGTH<=0 THEN more:=TRUE; END IF; - END IF; - IF more AND streamiob(stream).fstat=OPEN_OK THEN - more:=feof(stream); - IF NOT more THEN - CASE stream IS - WHEN stdin => readline(input, streamiob(stream).buf); - WHEN 4 => readline(streamfile4, streamiob(stream).buf); - WHEN 5 => readline(streamfile5, streamiob(stream).buf); - WHEN 6 => readline(streamfile6, streamiob(stream).buf); - WHEN 7 => readline(streamfile7, streamiob(stream).buf); - WHEN 8 => readline(streamfile8, streamiob(stream).buf); - WHEN 9 => readline(streamfile9, streamiob(stream).buf); - WHEN OTHERS => - END CASE; - write(streamiob(stream).buf, LF); - END IF; - END IF; - - IF streamiob(stream).buf/=NULL THEN - b:=streamiob(stream).buf; - IF b'LENGTH>0 THEN read(streamiob(stream).buf, c); END IF; - END IF; - END IF; - RETURN c; - END fgetc; - - --The fgets() function reads CHARACTERs from the stream into the STRING s, - -- until n-1 bytes are read, - -- or a newline CHARACTER IS read and transferred to s, - -- or an end-of-file condition IS encountered. - -- The STRING IS then terminated with a NULL byte. - -- - PROCEDURE fgets(s: OUT STRING; n: IN INTEGER; stream: IN CFILE) IS - VARIABLE i: INTEGER:=1; VARIABLE c: CHARACTER; - BEGIN - WHILE i0 AND stream<=streamNFILE - REPORT "ungetc(): passed in bad CFILE stream id" SEVERITY FAILURE; - IF stream/=stdnul THEN - write(t, c); - IF streamiob(stream).buf/=NULL THEN - b:=streamiob(stream).buf; - IF b'LENGTH>0 THEN write(t, streamiob(stream).buf.all); END IF; - END IF; - DEALLOCATE(streamiob(stream).buf); - streamiob(stream).buf:=t; --copy pointer - END IF; - END ungetc; - - PROCEDURE sbufprintf(fi: INOUT INTEGER; sbuf: INOUT LINE; stream: IN CFILE; - fmt: IN STRING; s: IN STRING) IS - - CONSTANT zero: CHARACTER:='0'; - VARIABLE c, d, f: CHARACTER; - VARIABLE sn, n, m, p, z: INTEGER; - VARIABLE ai, i, j, ax: INTEGER; - VARIABLE fj: INTEGER:=1; - VARIABLE lflag, aflag, zflag: BOOLEAN; - VARIABLE nflag, pflag, sflag: BOOLEAN; - VARIABLE fmtflag: BOOLEAN:=FALSE; - VARIABLE m1, m2, m3, m4: STRING(1 to 256); - VARIABLE w, buf, wbuf: LINE; - VARIABLE wflag: BOOLEAN:=FALSE; - BEGIN - IF stream/=stdnul THEN - ASSERT stream=-1 OR (sbuf=NULL AND stream>0 AND stream<=streamNFILE) - REPORT "fprintf/printf/sprintf error: passed in bad CFILE stream id or string" - SEVERITY FAILURE; - LOOP - fj:=fi; - regmatch(ai, fi, fmt, - "^$|\\n|([^%\\][^%\\]*)|%([^scdioxXufeEgGpn%\\]*)(.)|\\0(\\[0-7][0-7]?[0-7]?)|\\(.)", - m1, m2); - - - CASE ai IS --preprocess STRING - WHEN 5 => ai:=3; - ax:=0; - FOR i in 1 to m1'LENGTH LOOP - ax:=ax*8; - CASE m1(i) IS - WHEN '0'=> ax:=ax+0; when '1'=> ax:=ax+1; - WHEN '2'=> ax:=ax+2; when '3'=> ax:=ax+3; - WHEN '4'=> ax:=ax+4; when '5'=> ax:=ax+5; - WHEN '6'=> ax:=ax+6; when '7'=> ax:=ax+7; - WHEN others => - END CASE; - END LOOP; - m1(1):=CHARACTER'val(ax); - - WHEN 6 => ai:=3; - CASE m1(1) IS - WHEN 'a'=> m1(1):=BEL; when 'b'=> m1(1):=BS; - WHEN 'f'=> m1(1):=FF; when 'n'=> m1(1):=LF; - WHEN 'r'=> m1(1):=CR; when 't'=> m1(1):=HT; - WHEN 'v'=> m1(1):=VT; when others => - END CASE; - WHEN others => - END CASE; - - CASE ai IS - WHEN 1 => EXIT; - WHEN 2 => write(buf, LF); IF stream>0 THEN fputs(buf, stream); END IF; - WHEN 3 => write(buf, m1(1 to strlen(m1))); - WHEN 4 => - if fmtflag then fi:=fj; EXIT; end if; - f:=m2(1); m1(1):=NUL; m2(1):=NUL; m3(1):=NUL; m4(1):=NUL; - regmatch(ai, fj, fmt, - "%([ 0#+-]*)([0-9]*)\.?([0-9]*).", m1, m2, m3, m4); - - --. - lflag:=FALSE; aflag:=FALSE; - nflag:=FALSE; pflag:=FALSE; sflag:=FALSE; zflag:=FALSE; - - FOR i in 1 to m1'LENGTH LOOP - if m1(i)='-' then lflag:=TRUE; end if; - if m1(i)='+' then pflag:=TRUE; end if; - if m1(i)=' ' then sflag:=TRUE; end if; - if m1(i)='0' then zflag:=TRUE; end if; - if m1(i)='#' then aflag:=TRUE; end if; --ignored in decimal - if m1(i)=NUL then EXIT; end if; - END LOOP; - if m2(1)=NUL then m:=0; else m:=atoi(m2); end if; - - - IF f='x' OR f='o' OR f='X' THEN --unlimited STRING LENGTH - z:=0; sn:=s'LENGTH; ax:=0; j:=1; n:=0; - FOR i IN 1 TO s'LENGTH LOOP --skip leading zeros - IF z=0 AND s(i)='1' THEN z:=i; END IF; - IF s(i)=NUL THEN EXIT; END IF; sn:=i; - END LOOP; - IF z/=0 THEN - IF f='o' THEN p:=8; ELSE p:=16; END IF; --fix 20030425 - FOR i IN sn DOWNTO z LOOP --fix 20040528 big endian - CASE s(i) IS - WHEN ' '|HT => --ignore white space - WHEN '1' => ax:=j+ax; j:=2*j; - WHEN OTHERS => j:=2*j; --0, X, H, L, U, ... - END CASE; - IF j=p THEN - IF f='x' THEN write(w, pf_hex(ax)); - ELSE write(w, pf_hexx(ax)); END IF; --fix 20040528 - ax:=0; j:=1; n:=n+1; - END IF; - END LOOP; - END IF; - IF ax>0 OR n=0 THEN --residue - IF f='x' THEN write(w, pf_hex(ax)); ELSE write(w, pf_hexx(ax)); END IF; - n:=n+1; - END IF; - - IF zflag AND NOT lflag THEN - p:=0; IF aflag THEN IF f='o' THEN p:=1; ELSE p:=2; END IF; END IF; - WHILE n EXIT; WHEN ' '|HT => --ignore blanks - WHEN '1' => IF p=1 THEN p:=0; nflag:=TRUE; --begin 2's complement - ELSE - IF nflag THEN ax:=2*ax; ELSE ax:=2*ax+1; END IF; - END IF; - WHEN OTHERS => IF p=1 THEN p:=0; - ELSE - IF nflag THEN ax:=2*ax+1; ELSE ax:=2*ax; END IF; - END IF; - END CASE; - END LOOP; - IF nflag THEN ax:=ax+1; END IF; --2's complement ax:=(NOT ax)+1; - - LOOP --convert to base 10 - j:=ax MOD 10; write(w, pf_hex(j)); n:=n+1; - ax:=ax/10; IF ax=0 THEN EXIT; END IF; - END LOOP; - - IF zflag AND NOT lflag THEN - WHILE n - END CASE; - DEALLOCATE(w); wflag:=FALSE; - END LOOP; - IF stream<0 THEN sbuf:=buf; - ELSE - fputs(buf, stream); DEALLOCATE(buf); DEALLOCATE(sbuf); - END IF; - END IF; --NOT stdnul - END sbufprintf; - - PROCEDURE fprintf2(buf: INOUT LINE; - stream: IN CFILE; - format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : in STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: in STRING := " " - ) IS - VARIABLE fi: INTEGER:=1; - BEGIN - ASSERT stream>0 AND stream<=streamNFILE - REPORT "sprintf/fprintf: passed in bad CFILE stream id" SEVERITY FAILURE; - if stream/=stdnul THEN - sbufprintf(fi, buf, stream, format, a1); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a2); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a3); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a4); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a5); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a6); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a7); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a8); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a9); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a10); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a11); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a12); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a13); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a14); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a15); - if fi<=format'LENGTH then sbufprintf(fi, buf, stream, format, a16); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; - END IF; - END fprintf2; - - PROCEDURE fprintf(stream: IN CFILE; - format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : in STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: in STRING := " " - ) IS - BEGIN - fprintf2(streamnulbuf, stream, format, a1, a2, a3, a4, a5, a6, a7, a8, - a9, a10, a11, a12, a13, a14, a15, a16); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; - format: IN STRING; - a1: IN std_logic_vector; - a2, a3, a4, a5, a6, a7, a8: IN std_logic_vector := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN std_logic_vector := "U" - ) IS - BEGIN - fprintf2(streamnulbuf, stream, format, pf(a1),pf(a2),pf(a3),pf(a4),pf(a5),pf(a6),pf(a7),pf(a8), - pf(a9),pf(a10),pf(a11),pf(a12),pf(a13),pf(a14),pf(a15),pf(a16)); - END fprintf; - - PROCEDURE printf( format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8: IN STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: IN STRING := " " - ) IS - begin - fprintf2(streamnulbuf, stdout, format, a1,a2,a3,a4,a5,a6,a7,a8, - a9,a10,a11,a12,a13,a14,a15,a16); - END printf; - - PROCEDURE printf( format: IN STRING; - a1: IN std_logic_vector; - a2, a3, a4, a5, a6, a7, a8: IN std_logic_vector := "U"; - a9, a10, a11, a12, a13, a14, a15, a16: IN std_logic_vector := "U" - ) IS - begin - fprintf2(streamnulbuf, stdout, format, pf(a1),pf(a2),pf(a3),pf(a4),pf(a5),pf(a6),pf(a7),pf(a8), - pf(a9),pf(a10),pf(a11),pf(a12),pf(a13),pf(a14),pf(a15),pf(a16)); - END printf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN STRING; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; - BEGIN - IF a1/=NULL THEN sbufprintf(fi, streamnulbuf, stream, format, a1.all); - ELSE sbufprintf(fi, streamnulbuf, stream, format, STRING'("")); END IF; - END fprintf; - - PROCEDURE printf( format: IN STRING; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; - BEGIN - IF a1/=NULL THEN sbufprintf(fi, streamnulbuf, stdout, format, a1.all); - ELSE sbufprintf(fi, streamnulbuf, stdout, format, STRING'("")); END IF; - END printf; - - PROCEDURE sprintf(s: INOUT LINE; format: IN STRING; --Appends to LINE variable s by default - a1, a2, a3, a4, a5, a6, a7, a8 : in STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: in STRING := " " - ) IS - BEGIN - fprintf2(s, -1, format, a1, a2, a3, a4, a5, a6, a7, a8, - a9, a10, a11, a12, a13, a14, a15, a16); - END sprintf; - - PROCEDURE sprintf(s: INOUT STRING; format: IN STRING; - a1, a2, a3, a4, a5, a6, a7, a8 : in STRING := " "; - a9, a10, a11, a12, a13, a14, a15, a16: in STRING := " " - ) IS - variable W: LINE; variable i: INTEGER; - BEGIN - fprintf2(W, -1, format, a1, a2, a3, a4, a5, a6, a7, a8, - a9, a10, a11, a12, a13, a14, a15, a16); - - i:=1; WHILE i<=w'LENGTH LOOP - if i=0 THEN c:=fgetc(stream); - ELSIF buf=NULL THEN c:=NUL; - ELSIF buf'LENGTH<=0 THEN c:=NUL; - ELSE read(buf, c); - END IF; - END sfgetc; - - PROCEDURE sbufscanf(fi: INOUT INTEGER; sbuf: INOUT LINE; stream: IN CFILE; - fmt: IN STRING; s: INOUT LINE) IS - VARIABLE xbuf: LINE; - VARIABLE c, d, f: CHARACTER; - VARIABLE n, m, ms: INTEGER; - VARIABLE ai, i, j, ax: INTEGER; - VARIABLE fj: INTEGER:=1; - VARIABLE sflag, mflag: BOOLEAN; - VARIABLE fmtflag: BOOLEAN:=FALSE; - VARIABLE m1, m2, m3, m4:STRING(1 to 256); - BEGIN - IF stream/=stdnul THEN - ASSERT stream=-1 OR (sbuf=NULL AND stream>0 AND stream<=streamNFILE) - REPORT "fscanf/scanf/sscanf error: passed in bad CFILE stream id or string" - SEVERITY FAILURE; - sfgetc(c, stream, sbuf); - LOOP - fj:=fi; m1(1):=NUL; m2(1):=NUL; - regmatch(ai, fi, fmt, - "^$|%%|([^%\\])|%([^scdioxXufeEgGpn%\\]*)(.)|\\0(\\[0-7][0-7]?[0-7]?)|\\(.)", - m1, m2); - - - CASE ai IS - WHEN 2 => ai:=2; m1(1):='%'; m1(2):=NUL; - - WHEN 5 => ai:=2; - ax:=0; - FOR i in 1 to m1'LENGTH LOOP - ax:=ax*8; - CASE m1(i) IS - WHEN '0'=> ax:=ax+0; when '1'=> ax:=ax+1; - WHEN '2'=> ax:=ax+2; when '3'=> ax:=ax+3; - WHEN '4'=> ax:=ax+4; when '5'=> ax:=ax+5; - WHEN '6'=> ax:=ax+6; when '7'=> ax:=ax+7; - WHEN others => - END CASE; - END LOOP; - m1(1):=CHARACTER'val(ax); m1(2):=NUL; - - WHEN 6 => ai:=2; - CASE m1(1) IS - WHEN 'a'=> m1(1):=BEL; when 'b'=> m1(1):=BS; - WHEN 'f'=> m1(1):=FF; when 'n'=> m1(1):=LF; - WHEN 'r'=> m1(1):=CR; when 't'=> m1(1):=HT; - WHEN 'v'=> m1(1):=VT; when others => - END CASE; - m1(2):=NUL; - WHEN others => - END CASE; - - CASE ai IS - WHEN 1 => EXIT; - WHEN 3 => - if c/=m1(1) then EXIT; end if; - WHILE c=' ' LOOP - sfgetc(c, stream, sbuf); - END LOOP; - WHEN 4 => - if fmtflag then fi:=fj; EXIT; end if; - - f:=m2(1); m1(1):=NUL; m2(1):=NUL; m3(1):=NUL; m4(1):=NUL; - regmatch(ai, fj, fmt, "%([*]*)([0-9]*)([lLh]).", m1, m2, m3, m4); - - -- - sflag:=FALSE; - FOR i in 1 to m1'LENGTH LOOP - if m1(i)='*' then sflag:=TRUE; end if; --assignment suppression - if m1(i)=NUL then EXIT; end if; - END LOOP; - if m2(1)=NUL then m:=0; else m:=atoi(m2); end if; - - - if f/='c' then - WHILE c=' ' OR c=LF OR c=HT OR c=CR OR c=VT LOOP - sfgetc(c, stream, sbuf); - END LOOP; - end if; - - IF f='x' OR f='o' OR f='d' THEN - if f='x' or f='o' then write(s, STRING'("0")); end if; --20040529, sign bit - - i:=0; ax:=0; ms:=1; - LOOP - if m/=0 AND i>=m then EXIT; end if; - if i=0 and c='+' then ms:=1; - elsif i=0 and c='-' then ms:=-1; - else - CASE c IS - WHEN '0' => n:=0; when '1' => n:=1; - WHEN '2' => n:=2; when '3' => n:=3; - WHEN '4' => n:=4; when '5' => n:=5; - WHEN '6' => n:=6; when '7' => n:=7; - WHEN '8' => n:=8; when '9' => n:=9; - WHEN 'a'|'A'=> n:=10; when 'b'|'B'=> n:=11; - WHEN 'c'|'C'=> n:=12; when 'd'|'D'=> n:=13; - WHEN 'e'|'E'=> n:=14; when 'f'|'F'=> n:=15; - WHEN others => EXIT; - END CASE; - if f='d' then - if n>9 then EXIT; else ax:=ax*10+n; end if; - else - m1(1 to 4):=pf_hex2(n); - if f='o' and n>7 then EXIT; end if; - if f='o' and not sflag then write(s, m1(2 to 4)); end if; - if f='x' and not sflag then write(s, m1(1 to 4)); end if; - end if; - end if; - i:=i+1; sfgetc(c, stream, sbuf); - END LOOP; - - IF f='d' THEN - strcat(s, pf(ms*ax)); - --m1:=pf(ms*ax); n:=strlen(m1); write(s, m1(1 to n)); - --m1'LENGTH /= pf()'LENGTH - --mismatched array sizes are a problem in vhdl - --strcat, strcpy solves the mismatched array size problem - END IF; - END IF; - - --if f='%' then write(buf, '%'); end if; - - IF f='s' OR f='f' THEN - i:=0; - WHILE c/=' ' AND c/=LF AND c/=HT AND c/=CR AND c/=VT AND c/=NUL LOOP - if m/=0 AND i>=m then EXIT; end if; - if not sflag then write(s, c); end if; - i:=i+1; sfgetc(c, stream, sbuf); - END LOOP; - - END IF; - if c/='%' AND not sflag then fmtflag:=TRUE; end if; - WHEN others => - END CASE; - END LOOP; - IF stream=-1 THEN --put CHARACTER back into stream - write(xbuf, c); write(xbuf, sbuf.all); - DEALLOCATE(sbuf); sbuf:=xbuf; - ELSE - ungetc(c, stream); - END IF; - END IF; --NOT stdnul - END sbufscanf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT REAL) IS - BEGIN - if buf/=NULL then if buf'LENGTH>0 then read(buf, s); end if; end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT INTEGER) IS - BEGIN - if buf/=NULL then if buf'LENGTH>0 then s:=sf(buf.all); end if; end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT time) IS - BEGIN - if buf/=NULL then if buf'LENGTH>0 then s:=sf(buf.all)*1 ns; end if; end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT CHARACTER) IS - BEGIN - if buf/=NULL then if buf'LENGTH>0 then s:=buf(1); end if; end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT STRING) IS - VARIABLE i: INTEGER:=1; - BEGIN - IF buf/=NULL THEN - WHILE i<=buf'LENGTH LOOP - IF i0 then if buf(1)='1' then s:='1'; else s:='0'; end if; end if; - end if; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT BOOLEAN) IS - BEGIN - IF buf/=NULL THEN - IF buf'LENGTH>0 THEN IF buf(1)='1' THEN s:=TRUE; ELSE s:=FALSE; END IF; END IF; - END IF; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT bit_vector) IS - VARIABLE i, j: INTEGER; VARIABLE b: BIT:='0'; - BEGIN - IF buf/=NULL THEN --scanf will not alter unread variables - j:=buf'HIGH; - FOR i IN s'LOW TO s'HIGH LOOP - IF j>=buf'LOW THEN IF buf(j)='1' THEN b:='1'; END IF; j:=j-1; END IF; - s(i):=b; --last b will be for signed extention - END LOOP; - DEALLOCATE(buf); - END IF; - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT std_logic) IS - BEGIN - IF buf/=NULL THEN - IF buf'LENGTH>0 THEN - CASE buf(1) IS - WHEN '1' => s:='1'; - WHEN '0' => s:='0'; - WHEN '-' => s:='-'; - WHEN 'X'|'x'=> s:='X'; - WHEN 'Z'|'z'=> s:='Z'; - WHEN 'H'|'h'=> s:='H'; - WHEN 'L'|'l'=> s:='L'; - WHEN 'W'|'w'=> s:='W'; - WHEN others => s:='U'; - END CASE; - END IF; - END IF; - DEALLOCATE(buf); - END pf; - - PROCEDURE pf(buf: INOUT LINE; s: INOUT std_logic_vector) IS - VARIABLE i, j: INTEGER; VARIABLE b: CHARACTER:='0'; --signed extention bit - BEGIN - IF buf/=NULL THEN --scanf will not alter unread variables - j:=buf'HIGH; - FOR i IN s'LOW TO s'HIGH LOOP - IF j>=buf'LOW THEN b:=buf(j); j:=j-1; END IF; - CASE b IS - WHEN '1' => s(i):='1'; - WHEN '0' => s(i):='0'; - WHEN '-' => s(i):='-'; - WHEN 'X'|'x'=> s(i):='X'; - WHEN 'Z'|'z'=> s(i):='Z'; - WHEN 'H'|'h'=> s(i):='H'; - WHEN 'L'|'l'=> s(i):='L'; - WHEN 'W'|'w'=> s(i):='W'; - WHEN others => s(i):='U'; - END CASE; - END LOOP; - DEALLOCATE(buf); - END IF; - END pf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, a1); - END fscanf; - - PROCEDURE scanf(format: IN string; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, a1); - END scanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT LINE) IS - VARIABLE fi: INTEGER:=1; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, a1); deallocate(w); - END sscanf; - - PROCEDURE printf(format: IN string; a1: string) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: integer) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: std_logic) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: std_logic_vector) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: boolean) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: bit) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: bit_vector) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: time) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE printf(format: IN string; a1: real) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stdout, format, pf(a1)); - END printf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: integer) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: std_logic) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: boolean) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: bit) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: bit_vector) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: time) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE fprintf(stream: IN CFILE; format: IN string; a1: real) IS - VARIABLE fi: INTEGER:=1; - BEGIN - sbufprintf(fi, streamnulbuf, stream, format, pf(a1)); - END fprintf; - - PROCEDURE scanf(format: IN string; a1: INOUT string) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT integer) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT std_logic) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT std_logic_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT boolean) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT bit) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT bit_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT time) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE scanf(format: IN string; a1: INOUT real) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stdin, format, t); pf(t, a1); - END scanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT string) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT integer) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT std_logic) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT std_logic_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT boolean) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT bit) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT bit_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT time) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE fscanf(stream: IN CFILE; format: IN string; a1: INOUT real) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: LINE; - BEGIN - sbufscanf(fi, streamnulbuf, stream, format, t); pf(t, a1); - END fscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT string) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT integer) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT std_logic) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT std_logic_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT boolean) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT bit) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT bit_vector) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT time) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; - - PROCEDURE sscanf(s: IN string; format: IN string; a1: INOUT real) IS - VARIABLE fi: INTEGER:=1; VARIABLE t: line; VARIABLE w: line:=NEW string'(s); - BEGIN - sbufscanf(fi, w, -1, format, t); pf(t, a1); - deallocate(w); - END sscanf; ---------------------------------------------------------------------------------------------------------- --- end stdio_h; ---------------------------------------------------------------------------------------------------------- - -end vhdl_c_pkg_tb; \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/test_1.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/test_1.bxml deleted file mode 100644 index 1f0000c..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/test_1.bxml +++ /dev/null @@ -1,11 +0,0 @@ - - - - Composite Fileset - - - - - - - diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd index 58dd27a..81f763b 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd @@ -7,21 +7,19 @@ "name": "axi_crc_dma_sim_1", "rev_ctrl_bd_flag": "RevCtrlBdOff", "synth_flow_mode": "Hierarchical", - "tool_version": "2023.1" + "tool_version": "2023.1", + "validated": "true" }, "design_tree": { "axi_crc_dma": { - "axis_dma_0": "", "axis_fifo_0": "", "axis_fifo_1": "", - "crc": { - "axis_downsizer_0": "", - "axis_upsizer_0": "", - "axis_crc_0": "" - } + "axis_crc_0": "", + "axis_dma_0": "" }, "axil_master_with_rom_0": "", - "clk_rst_generator_0": "" + "clk_rst_generator_0": "", + "axi3_slave_verif_0": "" }, "components": { "axi_crc_dma": { @@ -30,6 +28,11 @@ "mode": "Slave", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { @@ -43,6 +46,195 @@ } }, "components": { + "axis_fifo_0": { + "vlnv": "Gehrke:user:axis_fifo:1.0", + "xci_name": "axi_crc_dma_sim_1_axis_fifo_0_0", + "xci_path": "ip\\axi_crc_dma_sim_1_axis_fifo_0_0\\axi_crc_dma_sim_1_axis_fifo_0_0.xci", + "inst_hier_path": "axi_crc_dma/axis_fifo_0", + "parameters": { + "FIFO_AWIDTH": { + "value": "8" + } + } + }, + "axis_fifo_1": { + "vlnv": "Gehrke:user:axis_fifo:1.0", + "xci_name": "axi_crc_dma_sim_1_axis_fifo_1_0", + "xci_path": "ip\\axi_crc_dma_sim_1_axis_fifo_1_0\\axi_crc_dma_sim_1_axis_fifo_1_0.xci", + "inst_hier_path": "axi_crc_dma/axis_fifo_1", + "parameters": { + "FIFO_AWIDTH": { + "value": "8" + } + } + }, + "axis_crc_0": { + "vlnv": "xilinx.com:module_ref:axis_crc:1.0", + "xci_name": "axi_crc_dma_sim_1_axis_crc_0_0", + "xci_path": "ip\\axi_crc_dma_sim_1_axis_crc_0_0\\axi_crc_dma_sim_1_axis_crc_0_0.xci", + "inst_hier_path": "axi_crc_dma/axis_crc_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "axis_crc", + "boundary_crc": "0x0" + }, + "interface_ports": { + "M_AXIS": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "4", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "M_AXIS_TDATA", + "direction": "O", + "left": "31", + "right": "0" + }, + "TLAST": { + "physical_name": "M_AXIS_TLAST", + "direction": "O" + }, + "TVALID": { + "physical_name": "M_AXIS_TVALID", + "direction": "O" + }, + "TREADY": { + "physical_name": "M_AXIS_TREADY", + "direction": "I" + } + } + }, + "S_AXIS": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "4", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "S_AXIS_TDATA", + "direction": "I", + "left": "31", + "right": "0" + }, + "TLAST": { + "physical_name": "S_AXIS_TLAST", + "direction": "I" + }, + "TVALID": { + "physical_name": "S_AXIS_TVALID", + "direction": "I" + }, + "TREADY": { + "physical_name": "S_AXIS_TREADY", + "direction": "O" + } + } + } + }, + "ports": { + "CLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXIS:S_AXIS", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "RESETN", + "value_src": "constant" + } + } + }, + "RESETN": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "initial_value": { + "direction": "I", + "left": "31", + "right": "0" + }, + "polynomial": { + "direction": "I", + "left": "31", + "right": "0" + } + } + }, "axis_dma_0": { "vlnv": "xilinx.com:module_ref:axis_dma:1.0", "xci_name": "axi_crc_dma_sim_1_axis_dma_0_0", @@ -678,6 +870,16 @@ "direction": "O", "left": "31", "right": "0" + }, + "FIFO_NUM_FREE": { + "direction": "I", + "left": "7", + "right": "0" + }, + "FIFO_NUM_AVAIL": { + "direction": "I", + "left": "7", + "right": "0" } }, "addressing": { @@ -688,299 +890,6 @@ } } } - }, - "axis_fifo_0": { - "vlnv": "Gehrke:user:axis_fifo:1.0", - "xci_name": "axi_crc_dma_sim_1_axis_fifo_0_0", - "xci_path": "ip\\axi_crc_dma_sim_1_axis_fifo_0_0\\axi_crc_dma_sim_1_axis_fifo_0_0.xci", - "inst_hier_path": "axi_crc_dma/axis_fifo_0" - }, - "axis_fifo_1": { - "vlnv": "Gehrke:user:axis_fifo:1.0", - "xci_name": "axi_crc_dma_sim_1_axis_fifo_1_0", - "xci_path": "ip\\axi_crc_dma_sim_1_axis_fifo_1_0\\axi_crc_dma_sim_1_axis_fifo_1_0.xci", - "inst_hier_path": "axi_crc_dma/axis_fifo_1" - }, - "crc": { - "interface_ports": { - "S_AXIS": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0" - }, - "M_AXIS": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0" - } - }, - "ports": { - "CLK": { - "type": "clk", - "direction": "I" - }, - "RESETN": { - "type": "rst", - "direction": "I" - }, - "initial_value": { - "direction": "I", - "left": "31", - "right": "0" - }, - "polynomial": { - "direction": "I", - "left": "31", - "right": "0" - } - }, - "components": { - "axis_downsizer_0": { - "vlnv": "xilinx.com:user:axis_downsizer:1.0", - "xci_name": "axi_crc_dma_sim_1_axis_downsizer_0_0", - "xci_path": "ip\\axi_crc_dma_sim_1_axis_downsizer_0_0\\axi_crc_dma_sim_1_axis_downsizer_0_0.xci", - "inst_hier_path": "axi_crc_dma/crc/axis_downsizer_0", - "parameters": { - "WIDTH_OUT": { - "value": "16" - } - } - }, - "axis_upsizer_0": { - "vlnv": "xilinx.com:user:axis_upsizer:1.0", - "xci_name": "axi_crc_dma_sim_1_axis_upsizer_0_0", - "xci_path": "ip\\axi_crc_dma_sim_1_axis_upsizer_0_0\\axi_crc_dma_sim_1_axis_upsizer_0_0.xci", - "inst_hier_path": "axi_crc_dma/crc/axis_upsizer_0", - "parameters": { - "WIDTH_IN": { - "value": "16" - } - } - }, - "axis_crc_0": { - "vlnv": "xilinx.com:module_ref:axis_crc:1.0", - "xci_name": "axi_crc_dma_sim_1_axis_crc_0_0", - "xci_path": "ip\\axi_crc_dma_sim_1_axis_crc_0_0\\axi_crc_dma_sim_1_axis_crc_0_0.xci", - "inst_hier_path": "axi_crc_dma/crc/axis_crc_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "axis_crc", - "boundary_crc": "0x0" - }, - "interface_ports": { - "M_AXIS": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "4", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "M_AXIS_TDATA", - "direction": "O", - "left": "31", - "right": "0" - }, - "TLAST": { - "physical_name": "M_AXIS_TLAST", - "direction": "O" - }, - "TVALID": { - "physical_name": "M_AXIS_TVALID", - "direction": "O" - }, - "TREADY": { - "physical_name": "M_AXIS_TREADY", - "direction": "I" - } - } - }, - "S_AXIS": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "4", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "S_AXIS_TDATA", - "direction": "I", - "left": "31", - "right": "0" - }, - "TLAST": { - "physical_name": "S_AXIS_TLAST", - "direction": "I" - }, - "TVALID": { - "physical_name": "S_AXIS_TVALID", - "direction": "I" - }, - "TREADY": { - "physical_name": "S_AXIS_TREADY", - "direction": "O" - } - } - } - }, - "ports": { - "CLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXIS:S_AXIS", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "RESETN", - "value_src": "constant" - } - } - }, - "RESETN": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - }, - "initial_value": { - "direction": "I", - "left": "31", - "right": "0" - }, - "polynomial": { - "direction": "I", - "left": "31", - "right": "0" - } - } - } - }, - "interface_nets": { - "axis_crc_0_M_AXIS": { - "interface_ports": [ - "axis_crc_0/M_AXIS", - "axis_upsizer_0/S_AXIS" - ] - }, - "axis_downsizer_0_M_AXIS": { - "interface_ports": [ - "axis_downsizer_0/M_AXIS", - "axis_crc_0/S_AXIS" - ] - }, - "axis_fifo_0_M_AXIS": { - "interface_ports": [ - "S_AXIS", - "axis_downsizer_0/S_AXIS" - ] - }, - "axis_upsizer_0_M_AXIS": { - "interface_ports": [ - "M_AXIS", - "axis_upsizer_0/M_AXIS" - ] - } - }, - "nets": { - "CLK_1": { - "ports": [ - "CLK", - "axis_upsizer_0/AXIS_ACLK", - "axis_downsizer_0/AXIS_ACLK", - "axis_crc_0/CLK" - ] - }, - "RESETN_1": { - "ports": [ - "RESETN", - "axis_upsizer_0/AXIS_ARESETN", - "axis_downsizer_0/AXIS_ARESETN", - "axis_crc_0/RESETN" - ] - }, - "axis_dma_0_initial_value": { - "ports": [ - "initial_value", - "axis_crc_0/initial_value" - ] - }, - "axis_dma_0_polynomial": { - "ports": [ - "polynomial", - "axis_crc_0/polynomial" - ] - } - } } }, "interface_nets": { @@ -990,6 +899,12 @@ "S_AXIL" ] }, + "Conn2": { + "interface_ports": [ + "axis_dma_0/M_AXI", + "M_AXI" + ] + }, "axis_dma_0_M_AXIS": { "interface_ports": [ "axis_dma_0/M_AXIS", @@ -999,7 +914,7 @@ "axis_fifo_0_M_AXIS": { "interface_ports": [ "axis_fifo_0/M_AXIS", - "crc/S_AXIS" + "axis_crc_0/S_AXIS" ] }, "axis_fifo_1_M_AXIS": { @@ -1010,7 +925,7 @@ }, "axis_upsizer_0_M_AXIS": { "interface_ports": [ - "crc/M_AXIS", + "axis_crc_0/M_AXIS", "axis_fifo_1/S_AXIS" ] } @@ -1019,34 +934,47 @@ "CLK_1": { "ports": [ "CLK", - "axis_dma_0/CLK", "axis_fifo_0/M_AXIS_ACLK", "axis_fifo_0/S_AXIS_ACLK", "axis_fifo_1/S_AXIS_ACLK", "axis_fifo_1/M_AXIS_ACLK", - "crc/CLK" + "axis_crc_0/CLK", + "axis_dma_0/CLK" ] }, "RESETN_1": { "ports": [ "RESETN", - "axis_dma_0/RESETN", "axis_fifo_0/M_AXIS_ARESETN", "axis_fifo_1/S_AXIS_ARESETN", "axis_fifo_1/M_AXIS_ARESETN", - "crc/RESETN" + "axis_crc_0/RESETN", + "axis_fifo_0/S_AXIS_ARESETN", + "axis_dma_0/RESETN" ] }, "axis_dma_0_initial_value": { "ports": [ "axis_dma_0/initial_value", - "crc/initial_value" + "axis_crc_0/initial_value" ] }, "axis_dma_0_polynomial": { "ports": [ "axis_dma_0/polynomial", - "crc/polynomial" + "axis_crc_0/polynomial" + ] + }, + "axis_fifo_0_S_NUM_FREE": { + "ports": [ + "axis_fifo_0/S_NUM_FREE", + "axis_dma_0/FIFO_NUM_FREE" + ] + }, + "axis_fifo_1_M_NUM_AVAIL": { + "ports": [ + "axis_fifo_1/M_NUM_AVAIL", + "axis_dma_0/FIFO_NUM_AVAIL" ] } } @@ -1056,6 +984,11 @@ "xci_name": "axi_crc_dma_sim_1_axil_master_with_rom_0_0", "xci_path": "ip\\axi_crc_dma_sim_1_axil_master_with_rom_0_0\\axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci", "inst_hier_path": "axil_master_with_rom_0", + "parameters": { + "STIM_FILENAME": { + "value": "../../axi_crc_dma_sim.mem" + } + }, "interface_ports": { "M_AXIL": { "vlnv": "xilinx.com:interface:aximm_rtl:1.0", @@ -1082,9 +1015,294 @@ "xci_name": "axi_crc_dma_sim_1_clk_rst_generator_0_0", "xci_path": "ip\\axi_crc_dma_sim_1_clk_rst_generator_0_0\\axi_crc_dma_sim_1_clk_rst_generator_0_0.xci", "inst_hier_path": "clk_rst_generator_0" + }, + "axi3_slave_verif_0": { + "vlnv": "xilinx.com:module_ref:axi3_slave_verif:1.0", + "xci_name": "axi_crc_dma_sim_1_axi3_slave_verif_0_0", + "xci_path": "ip\\axi_crc_dma_sim_1_axi3_slave_verif_0_0\\axi_crc_dma_sim_1_axi3_slave_verif_0_0.xci", + "inst_hier_path": "axi3_slave_verif_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "axi3_slave_verif", + "boundary_crc": "0x0" + }, + "interface_ports": { + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "DATA_WIDTH": { + "value": "32", + "value_src": "auto" + }, + "PROTOCOL": { + "value": "AXI3", + "value_src": "constant" + }, + "ID_WIDTH": { + "value": "1", + "value_src": "auto" + }, + "ADDR_WIDTH": { + "value": "32", + "value_src": "constant" + }, + "AWUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "ARUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "WUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "RUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "BUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE", + "value_src": "constant" + }, + "HAS_BURST": { + "value": "1", + "value_src": "constant" + }, + "HAS_LOCK": { + "value": "0", + "value_src": "constant" + }, + "HAS_PROT": { + "value": "0", + "value_src": "constant" + }, + "HAS_CACHE": { + "value": "0", + "value_src": "constant" + }, + "HAS_QOS": { + "value": "0", + "value_src": "constant" + }, + "HAS_REGION": { + "value": "0", + "value_src": "constant" + }, + "HAS_WSTRB": { + "value": "1", + "value_src": "constant" + }, + "HAS_BRESP": { + "value": "1", + "value_src": "constant" + }, + "HAS_RRESP": { + "value": "1", + "value_src": "constant" + }, + "SUPPORTS_NARROW_BURST": { + "value": "1", + "value_src": "auto" + }, + "NUM_READ_OUTSTANDING": { + "value": "2", + "value_src": "auto" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "2", + "value_src": "auto" + }, + "MAX_BURST_LENGTH": { + "value": "16", + "value_src": "auto" + } + }, + "memory_map_ref": "S_AXI", + "port_maps": { + "AWADDR": { + "physical_name": "S_AXI_AWADDR", + "direction": "I", + "left": "31", + "right": "0" + }, + "AWLEN": { + "physical_name": "S_AXI_AWLEN", + "direction": "I", + "left": "3", + "right": "0" + }, + "AWSIZE": { + "physical_name": "S_AXI_AWSIZE", + "direction": "I", + "left": "2", + "right": "0" + }, + "AWBURST": { + "physical_name": "S_AXI_AWBURST", + "direction": "I", + "left": "1", + "right": "0" + }, + "AWVALID": { + "physical_name": "S_AXI_AWVALID", + "direction": "I" + }, + "AWREADY": { + "physical_name": "S_AXI_AWREADY", + "direction": "O" + }, + "WDATA": { + "physical_name": "S_AXI_WDATA", + "direction": "I", + "left": "31", + "right": "0" + }, + "WSTRB": { + "physical_name": "S_AXI_WSTRB", + "direction": "I", + "left": "3", + "right": "0" + }, + "WLAST": { + "physical_name": "S_AXI_WLAST", + "direction": "I" + }, + "WVALID": { + "physical_name": "S_AXI_WVALID", + "direction": "I" + }, + "WREADY": { + "physical_name": "S_AXI_WREADY", + "direction": "O" + }, + "BRESP": { + "physical_name": "S_AXI_BRESP", + "direction": "O", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "S_AXI_BVALID", + "direction": "O" + }, + "BREADY": { + "physical_name": "S_AXI_BREADY", + "direction": "I" + }, + "ARID": { + "physical_name": "S_AXI_ARID", + "direction": "I", + "left": "0", + "right": "0" + }, + "ARADDR": { + "physical_name": "S_AXI_ARADDR", + "direction": "I", + "left": "31", + "right": "0" + }, + "ARLEN": { + "physical_name": "S_AXI_ARLEN", + "direction": "I", + "left": "3", + "right": "0" + }, + "ARSIZE": { + "physical_name": "S_AXI_ARSIZE", + "direction": "I", + "left": "2", + "right": "0" + }, + "ARBURST": { + "physical_name": "S_AXI_ARBURST", + "direction": "I", + "left": "1", + "right": "0" + }, + "ARVALID": { + "physical_name": "S_AXI_ARVALID", + "direction": "I" + }, + "ARREADY": { + "physical_name": "S_AXI_ARREADY", + "direction": "O" + }, + "RID": { + "physical_name": "S_AXI_RID", + "direction": "O", + "left": "0", + "right": "0" + }, + "RDATA": { + "physical_name": "S_AXI_RDATA", + "direction": "O", + "left": "31", + "right": "0" + }, + "RRESP": { + "physical_name": "S_AXI_RRESP", + "direction": "O", + "left": "1", + "right": "0" + }, + "RLAST": { + "physical_name": "S_AXI_RLAST", + "direction": "O" + }, + "RVALID": { + "physical_name": "S_AXI_RVALID", + "direction": "O" + }, + "RREADY": { + "physical_name": "S_AXI_RREADY", + "direction": "I" + } + } + } + }, + "ports": { + "CLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "RESETN", + "value_src": "constant" + } + } + }, + "RESETN": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } } }, "interface_nets": { + "axi_crc_dma_M_AXI": { + "interface_ports": [ + "axi3_slave_verif_0/S_AXI", + "axi_crc_dma/M_AXI" + ] + }, "axil_master_with_rom_0_M_AXIL": { "interface_ports": [ "axil_master_with_rom_0/M_AXIL", @@ -1097,14 +1315,16 @@ "ports": [ "clk_rst_generator_0/clk", "axil_master_with_rom_0/M_AXIL_ACLK", - "axi_crc_dma/CLK" + "axi_crc_dma/CLK", + "axi3_slave_verif_0/CLK" ] }, "clk_rst_generator_0_rst_n": { "ports": [ "clk_rst_generator_0/rst_n", "axil_master_with_rom_0/M_AXIL_ARESETN", - "axi_crc_dma/RESETN" + "axi_crc_dma/RESETN", + "axi3_slave_verif_0/RESETN" ] } } diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xci new file mode 100644 index 0000000..f8b7e43 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xci @@ -0,0 +1,192 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_crc_dma_sim_1_axi3_slave_verif_0_0", + "cell_name": "axi3_slave_verif_0", + "component_reference": "xilinx.com:module_ref:axi3_slave_verif:1.0", + "ip_revision": "1", + "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0", + "parameters": { + "component_parameters": { + "DWIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "IDWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MAX_BURSTLEN": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "axi_crc_dma_sim_1_axi3_slave_verif_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "IDWIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "MAX_BURSTLEN": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VHDL" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "1" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ] + } + }, + "boundary": { + "ports": { + "CLK": [ { "direction": "in" } ], + "RESETN": [ { "direction": "in" } ], + "S_AXI_ARVALID": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_ARREADY": [ { "direction": "out", "driver_value": "0x0" } ], + "S_AXI_ARADDR": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "S_AXI_ARID": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "S_AXI_ARLEN": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "S_AXI_ARSIZE": [ { "direction": "in", "size_left": "2", "size_right": "0" } ], + "S_AXI_ARBURST": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ], + "S_AXI_RVALID": [ { "direction": "out", "driver_value": "0x0" } ], + "S_AXI_RREADY": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "S_AXI_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "S_AXI_RID": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], + "S_AXI_RLAST": [ { "direction": "out", "driver_value": "0x0" } ], + "S_AXI_AWVALID": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_AWREADY": [ { "direction": "out", "driver_value": "0x0" } ], + "S_AXI_AWADDR": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "S_AXI_AWLEN": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "S_AXI_AWSIZE": [ { "direction": "in", "size_left": "2", "size_right": "0" } ], + "S_AXI_AWBURST": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ], + "S_AXI_WVALID": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_WREADY": [ { "direction": "out", "driver_value": "0x0" } ], + "S_AXI_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "S_AXI_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ], + "S_AXI_WLAST": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_BVALID": [ { "direction": "out", "driver_value": "0x0" } ], + "S_AXI_BREADY": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ] + }, + "interfaces": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "memory_map_ref": "S_AXI", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "S_AXI_AWADDR" } ], + "AWLEN": [ { "physical_name": "S_AXI_AWLEN" } ], + "AWSIZE": [ { "physical_name": "S_AXI_AWSIZE" } ], + "AWBURST": [ { "physical_name": "S_AXI_AWBURST" } ], + "AWVALID": [ { "physical_name": "S_AXI_AWVALID" } ], + "AWREADY": [ { "physical_name": "S_AXI_AWREADY" } ], + "WDATA": [ { "physical_name": "S_AXI_WDATA" } ], + "WSTRB": [ { "physical_name": "S_AXI_WSTRB" } ], + "WLAST": [ { "physical_name": "S_AXI_WLAST" } ], + "WVALID": [ { "physical_name": "S_AXI_WVALID" } ], + "WREADY": [ { "physical_name": "S_AXI_WREADY" } ], + "BRESP": [ { "physical_name": "S_AXI_BRESP" } ], + "BVALID": [ { "physical_name": "S_AXI_BVALID" } ], + "BREADY": [ { "physical_name": "S_AXI_BREADY" } ], + "ARID": [ { "physical_name": "S_AXI_ARID" } ], + "ARADDR": [ { "physical_name": "S_AXI_ARADDR" } ], + "ARLEN": [ { "physical_name": "S_AXI_ARLEN" } ], + "ARSIZE": [ { "physical_name": "S_AXI_ARSIZE" } ], + "ARBURST": [ { "physical_name": "S_AXI_ARBURST" } ], + "ARVALID": [ { "physical_name": "S_AXI_ARVALID" } ], + "ARREADY": [ { "physical_name": "S_AXI_ARREADY" } ], + "RID": [ { "physical_name": "S_AXI_RID" } ], + "RDATA": [ { "physical_name": "S_AXI_RDATA" } ], + "RRESP": [ { "physical_name": "S_AXI_RRESP" } ], + "RLAST": [ { "physical_name": "S_AXI_RLAST" } ], + "RVALID": [ { "physical_name": "S_AXI_RVALID" } ], + "RREADY": [ { "physical_name": "S_AXI_RREADY" } ] + } + }, + "RESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "RESETN" } ] + } + }, + "CLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "CLK" } ] + } + } + }, + "memory_maps": { + "S_AXI": { + "display_name": "S_AXI", + "address_blocks": { + "reg0": { + "base_address": "0x0", + "range": "0x100000000", + "display_name": "reg0", + "usage": "register" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci index 56e8770..ff83833 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci @@ -8,14 +8,14 @@ "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0", "parameters": { "component_parameters": { - "STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "user", "usage": "all" } ], + "STIM_FILENAME": [ { "value": "../../axi_crc_dma_sim.mem", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Component_Name": [ { "value": "axi_crc_dma_sim_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ], "HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "REVISION_NO": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ] }, "model_parameters": { - "STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "generated", "usage": "all" } ], + "STIM_FILENAME": [ { "value": "../../axi_crc_dma_sim.mem", "resolve_type": "generated", "usage": "all" } ], "HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "REVISION_NO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] @@ -78,7 +78,7 @@ "parameters": { "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci index 78a628e..841e5b2 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci @@ -2,7 +2,7 @@ "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { "xci_name": "axi_crc_dma_sim_1_axis_crc_0_0", - "cell_name": "axis_crc_0", + "cell_name": "axi_crc_dma/axis_crc_0", "component_reference": "xilinx.com:module_ref:axis_crc:1.0", "ip_revision": "1", "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0", diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci index 67d7be8..807e84b 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci @@ -2,7 +2,7 @@ "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { "xci_name": "axi_crc_dma_sim_1_axis_dma_0_0", - "cell_name": "axi_crc_dma/axis_dma_0", + "cell_name": "axis_dma_0", "component_reference": "xilinx.com:module_ref:axis_dma:1.0", "ip_revision": "1", "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0", @@ -11,12 +11,18 @@ "DWIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], "IDWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "MAX_BURSTLEN": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FIFO_AWIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], + "polynomial_default": [ { "value": "0x04C11DB7", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "initial_value_default": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "Component_Name": [ { "value": "axi_crc_dma_sim_1_axis_dma_0_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { "DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "IDWIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "MAX_BURSTLEN": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ] + "MAX_BURSTLEN": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FIFO_AWIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "polynomial_default": [ { "value": "0x04C11DB7", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "initial_value_default": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ] }, "project_parameters": { "ARCHITECTURE": [ { "value": "zynq" } ], @@ -48,6 +54,8 @@ "RESETN": [ { "direction": "in" } ], "initial_value": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], "polynomial": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "FIFO_NUM_FREE": [ { "direction": "in", "size_left": "7", "size_right": "0" } ], + "FIFO_NUM_AVAIL": [ { "direction": "in", "size_left": "7", "size_right": "0" } ], "S_AXIL_AWADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], "S_AXIL_AWVALID": [ { "direction": "in", "driver_value": "0" } ], "S_AXIL_AWREADY": [ { "direction": "out" } ], @@ -168,25 +176,25 @@ "address_space_ref": "M_AXI", "parameters": { "DATA_WIDTH": [ { "value": "32", "value_src": "auto", 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"is_static_object": false } ] - }, - "port_maps": { - "CLK": [ { "physical_name": "AXIS_ACLK" } ] - } - } - } - } - } -} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xci index d8fac44..f501bf6 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xci +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xci @@ -10,7 +10,7 @@ "component_parameters": { "FIFO_TUSERWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "FIFO_DWIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FIFO_AWIDTH": [ { "value": "11", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FIFO_AWIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "FIFO_USE_BLOCKRAM": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "FIFO_HAS_AXIL_IF": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Component_Name": [ { "value": "axi_crc_dma_sim_1_axis_fifo_0_0", "resolve_type": "user", "usage": "all" } ] @@ -18,7 +18,7 @@ "model_parameters": { "FIFO_HAS_AXIL_IF": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "FIFO_USE_BLOCKRAM": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], - "FIFO_AWIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FIFO_AWIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], "FIFO_DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "FIFO_TUSERWIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, @@ -55,7 +55,7 @@ "S_AXIS_TLAST": [ { "direction": "in" } ], "S_AXIS_TREADY": [ { "direction": "out" } ], "S_AXIS_TUSER": [ { "direction": "in", "size_left": "0", "size_right": "0" } ], - "S_NUM_FREE": [ { "direction": "out", "size_left": "10", "size_right": "0" } ], + "S_NUM_FREE": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], "M_AXIS_ACLK": [ { "direction": "in" } ], "M_AXIS_ARESETN": [ { "direction": "in" } ], "M_AXIS_TVALID": [ { "direction": "out" } ], @@ -63,7 +63,7 @@ "M_AXIS_TLAST": [ { "direction": "out" } ], "M_AXIS_TREADY": [ { "direction": "in" } ], "M_AXIS_TUSER": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], - "M_NUM_AVAIL": [ { "direction": "out", "size_left": "10", "size_right": "0" } ] + "M_NUM_AVAIL": [ { "direction": "out", "size_left": "7", "size_right": "0" } ] }, "interfaces": { "M_AXIS": { diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xci index a70dee8..ed78575 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xci +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xci @@ -10,7 +10,7 @@ "component_parameters": { "FIFO_TUSERWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "FIFO_DWIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FIFO_AWIDTH": [ { "value": "11", "resolve_type": "user", "format": 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"is_ips_inferred": true, "is_static_object": false } ], - "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "TDATA": [ { "physical_name": "M_AXIS_TDATA" } ], - "TLAST": [ { "physical_name": "M_AXIS_TLAST" } ], - "TUSER": [ { "physical_name": "M_AXIS_TUSER" } ], - "TVALID": [ { "physical_name": "M_AXIS_TVALID" } ], - "TREADY": [ { "physical_name": "M_AXIS_TREADY" } ] - } - }, - "S_AXIS": { - "vlnv": "xilinx.com:interface:axis:1.0", - "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", - "mode": "slave", - "parameters": { - "TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "TDATA": [ { "physical_name": "S_AXIS_TDATA" } ], - "TLAST": [ { "physical_name": "S_AXIS_TLAST" } ], - "TUSER": [ { "physical_name": "S_AXIS_TUSER" } ], - "TVALID": [ { "physical_name": "S_AXIS_TVALID" } ], - "TREADY": [ { "physical_name": "S_AXIS_TREADY" } ] - } - }, - "AXIS_ARESETN": { - "vlnv": "xilinx.com:signal:reset:1.0", - "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", - "mode": "slave", - "parameters": { - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "RST": [ { "physical_name": "AXIS_ARESETN" } ] - } - }, - "AXIS_ACLK": { - "vlnv": "xilinx.com:signal:clock:1.0", - "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", - "mode": "slave", - "parameters": { - "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], - "ASSOCIATED_RESET": [ { "value": "AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], - "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "CLK": [ { "physical_name": "AXIS_ACLK" } ] - } - } - } - } - } -} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui index 3cd95b7..b3691c0 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui @@ -1,7 +1,7 @@ { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"2.0", - "Default View_TopLeft":"1191,-40", + "Default View_ScaleFactor":"1.25", + "Default View_TopLeft":"-146,-50", "Display-PortTypeOthers":"true", "ExpandedHierarchyInLayout":"", "Interfaces View_ExpandedHierarchyInLayout":"", @@ -19,14 +19,16 @@ pagesize -pg 1 -db -bbox -sgen 0 0 1990 480 "Interfaces View_TopLeft":"-199,-369", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD -preplace inst axi_crc_dma -pg 1 -lvl 3 -x 600 -y 78 -defaultsOSRD -preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 350 -y 110 -defaultsOSRD -preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 120 -defaultsOSRD -preplace netloc clk_rst_generator_0_clk 1 1 2 220 20 490J -preplace netloc clk_rst_generator_0_rst_n 1 1 2 230 30 470J -preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 480 58n -levelinfo -pg 1 0 110 350 600 680 -pagesize -pg 1 -db -bbox -sgen 0 -10 2700 420 +preplace inst axi_crc_dma -pg 1 -lvl 3 -x 620 -y 240 -defaultsOSRD +preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 350 -y 210 -defaultsOSRD +preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 130 -defaultsOSRD +preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 850 -y 260 -defaultsOSRD +preplace netloc clk_rst_generator_0_clk 1 1 3 230 290 510 310 720J +preplace netloc clk_rst_generator_0_rst_n 1 1 3 220 300 520 320 730J +preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 470 210n +preplace netloc axi_crc_dma_M_AXI 1 3 1 N 240 +levelinfo -pg 1 0 110 350 620 850 940 +pagesize -pg 1 -db -bbox -sgen 0 0 940 340 " } { diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd index 2809374..02f0bd1 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd @@ -7,7 +7,8 @@ "name": "axis_crc_sim_1", "rev_ctrl_bd_flag": "RevCtrlBdOff", "synth_flow_mode": "Hierarchical", - "tool_version": "2023.1" + "tool_version": "2023.1", + "validated": "true" }, "design_tree": { "clk_rst_generator_0": "", diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui index 5c8ac70..df0f237 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui @@ -1,7 +1,7 @@ { "ActiveEmotionalView":"Default View", "Default View_ScaleFactor":"2.0", - "Default View_TopLeft":"-180,-69", + "Default View_TopLeft":"187,103", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/axis_master_test.bd b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/axis_master_test.bd deleted file mode 100644 index 287922a..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/axis_master_test.bd +++ /dev/null @@ -1,117 +0,0 @@ -{ - "design": { - "design_info": { - "boundary_crc": "0x0", - "device": "xc7z020clg400-1", - "gen_directory": "../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test", - "name": "axis_master_test", - "rev_ctrl_bd_flag": "RevCtrlBdOff", - "synth_flow_mode": "Hierarchical", - "tool_version": "2023.1" - }, - "design_tree": { - "axis_mixer_0": "", - "axis_numeric_master_0": "" - }, - "components": { - "axis_mixer_0": { - "vlnv": "xilinx.com:user:axis_mixer:1.0", - "xci_name": "axis_master_test_axis_mixer_0_0", - "xci_path": "ip\\axis_master_test_axis_mixer_0_0\\axis_master_test_axis_mixer_0_0.xci", - "inst_hier_path": "axis_mixer_0", - "parameters": { - "DATA_WIDTH": { - "value": "32" - }, - "WEIGHT_1": { - "value": "1" - }, - "WEIGHT_2": { - "value": "1" - } - } - }, - "axis_numeric_master_0": { - "vlnv": "xilinx.com:user:axis_numeric_master_slave_simmodel:1.0", - "xci_name": "axis_master_test_axis_numeric_master_0_0", - "xci_path": "ip\\axis_master_test_axis_numeric_master_0_0\\axis_master_test_axis_numeric_master_0_0.xci", - "inst_hier_path": "axis_numeric_master_0", - "parameters": { - "FILE_NAME_M1": { - "value": "../../../../mstr1.txt" - }, - "FILE_NAME_M2": { - "value": "../../../../mstr2.txt" - }, - "FILE_NAME_S": { - "value": "../../../../slv.txt" - }, - "MASTER1_HAS_LAST": { - "value": "false" - }, - "MASTER1_HAS_USER": { - "value": "false" - }, - "MASTER1_RANDOM_VALID": { - "value": "true" - }, - "MASTER2_HAS_LAST": { - "value": "false" - }, - "MASTER2_HAS_USER": { - "value": "false" - }, - "MASTER2_RANDOM_VALID": { - "value": "true" - }, - "SLAVE_HAS_LAST": { - "value": "false" - }, - "SLAVE_HAS_USER": { - "value": "false" - }, - "SLAVE_RANDOM_READY": { - "value": "true" - }, - "SLAVE_WAIT_FOR_SOF": { - "value": "false" - } - } - } - }, - "interface_nets": { - "axis_mixer_0_M_AXIS": { - "interface_ports": [ - "axis_mixer_0/M_AXIS", - "axis_numeric_master_0/S_AXIS" - ] - }, - "axis_numeric_master_0_M1_AXIS": { - "interface_ports": [ - "axis_mixer_0/S_AXIS_1", - "axis_numeric_master_0/M1_AXIS" - ] - }, - "axis_numeric_master_0_M2_AXIS": { - "interface_ports": [ - "axis_mixer_0/S_AXIS_2", - "axis_numeric_master_0/M2_AXIS" - ] - } - }, - "nets": { - "axis_numeric_master_0_CLK": { - "ports": [ - "axis_numeric_master_0/CLK", - "axis_mixer_0/ACLK" - ] - }, - "axis_numeric_master_0_RESETN": { - "ports": [ - "axis_numeric_master_0/RESETN", - "axis_mixer_0/ARESETN" - ] - } - } - } -} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/axis_master_test_axis_mixer_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/axis_master_test_axis_mixer_0_0.xci deleted file mode 100644 index e0dfd68..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/axis_master_test_axis_mixer_0_0.xci +++ /dev/null @@ -1,185 +0,0 @@ -{ - "schema": "xilinx.com:schema:json_instance:1.0", - "ip_inst": { - "xci_name": "axis_master_test_axis_mixer_0_0", - "cell_name": "axis_mixer_0", - "component_reference": "xilinx.com:user:axis_mixer:1.0", - "ip_revision": "14", - "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0", - "parameters": { - "component_parameters": { - "WEIGHT_1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Component_Name": [ { "value": "axis_master_test_axis_mixer_0_0", "resolve_type": "user", "usage": "all" } ], - "HAS_AXI_LITE_IF": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "WEIGHT_2": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FORCE_01_INPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "SHIFT_DEF": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ] - }, - "model_parameters": { - "WEIGHT_1": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "HAS_AXI_LITE_IF": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], - "WEIGHT_2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "FORCE_01_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], - "SHIFT_DEF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] - }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "zynq" } ], - "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7z020" } ], - "PACKAGE": [ { "value": "clg400" } ], - "PREFHDL": [ { "value": "VHDL" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-1" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "" } ] - }, - "runtime_parameters": { - "IPCONTEXT": [ { "value": "IP_Integrator" } ], - "IPREVISION": [ { "value": "14" } ], - "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0" } ], - "SELECTEDSIMMODEL": [ { "value": "" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], - "SWVERSION": [ { "value": "2023.1" } ], - "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] 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"generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "test_1_axis_numeric_master_0_0_CLK", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "CLK": [ { "physical_name": "CLK" } ] - } - } - } - } - } -} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/test_1_xlconstant_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/test_1_xlconstant_0_0.xci deleted file mode 100644 index a111668..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/test_1_xlconstant_0_0.xci +++ /dev/null @@ -1,49 +0,0 @@ -{ - "schema": "xilinx.com:schema:json_instance:1.0", - "ip_inst": { - "xci_name": "test_1_xlconstant_0_0", - "cell_name": "xlconstant_0", - "component_reference": "xilinx.com:ip:xlconstant:1.1", - "ip_revision": "7", - "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0", - "parameters": { - "component_parameters": { - "Component_Name": [ { "value": "test_1_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ], - "CONST_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ] - }, - "model_parameters": { - "CONST_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "CONST_VAL": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ] - }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "zynq" } ], - "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7z020" } ], - "PACKAGE": [ { "value": "clg400" } ], - "PREFHDL": [ { "value": "VHDL" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-1" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "" } ] - }, - "runtime_parameters": { - "IPCONTEXT": [ { "value": "IP_Integrator" } ], - "IPREVISION": [ { "value": "7" } ], - "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0" } ], - "SELECTEDSIMMODEL": [ { "value": "" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], - "SWVERSION": [ { "value": "2023.1" } ], - "SYNTHESISFLOW": [ { "value": "GLOBAL" } ] - } - }, - "boundary": { - "ports": { - "dout": [ { "direction": "out", "size_left": "31", "size_right": "0" } ] - } - } - } -} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/test_1_xlconstant_1_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/test_1_xlconstant_1_0.xci deleted file mode 100644 index f00017d..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/test_1_xlconstant_1_0.xci +++ /dev/null @@ -1,49 +0,0 @@ -{ - "schema": "xilinx.com:schema:json_instance:1.0", - "ip_inst": { - "xci_name": "test_1_xlconstant_1_0", - "cell_name": "xlconstant_1", - "component_reference": "xilinx.com:ip:xlconstant:1.1", - "ip_revision": "7", - "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0", - "parameters": { - "component_parameters": { - "Component_Name": [ { "value": "test_1_xlconstant_1_0", "resolve_type": "user", "usage": "all" } ], - "CONST_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ] - }, - "model_parameters": { - "CONST_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "CONST_VAL": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ] - }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "zynq" } ], - "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7z020" } ], - "PACKAGE": [ { "value": "clg400" } ], - "PREFHDL": [ { "value": "VHDL" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-1" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "" } ] - }, - "runtime_parameters": { - "IPCONTEXT": [ { "value": "IP_Integrator" } ], - "IPREVISION": [ { "value": "7" } ], - "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0" } ], - "SELECTEDSIMMODEL": [ { "value": "" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], - "SWVERSION": [ { "value": "2023.1" } ], - "SYNTHESISFLOW": [ { "value": "GLOBAL" } ] - } - }, - "boundary": { - "ports": { - "dout": [ { "direction": "out", "size_left": "31", "size_right": "0" } ] - } - } - } -} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/test_1.bd b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/test_1.bd deleted file mode 100644 index 46af2bc..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/test_1.bd +++ /dev/null @@ -1,300 +0,0 @@ -{ - "design": { - "design_info": { - "boundary_crc": "0x0", - "device": "xc7z020clg400-1", - "gen_directory": "../../../../aci_crc_dma.gen/sources_1/bd/test_1", - "name": "test_1", - "rev_ctrl_bd_flag": "RevCtrlBdOff", - "synth_flow_mode": "Hierarchical", - "tool_version": "2023.1" - }, - "design_tree": { - "xlconstant_0": "", - "xlconstant_1": "", - "axis_numeric_master_0": "", - "axis_crc_0": "" - }, - "components": { - "xlconstant_0": { - "vlnv": "xilinx.com:ip:xlconstant:1.1", - "xci_name": "test_1_xlconstant_0_0", - "xci_path": "ip\\test_1_xlconstant_0_0\\test_1_xlconstant_0_0.xci", - "inst_hier_path": "xlconstant_0", - "parameters": { - "CONST_VAL": { - "value": "0" - }, - "CONST_WIDTH": { - "value": "32" - } - } - }, - "xlconstant_1": { - "vlnv": "xilinx.com:ip:xlconstant:1.1", - "xci_name": "test_1_xlconstant_1_0", - "xci_path": "ip\\test_1_xlconstant_1_0\\test_1_xlconstant_1_0.xci", - "inst_hier_path": "xlconstant_1", - "parameters": { - "CONST_VAL": { - "value": "0" - }, - "CONST_WIDTH": { - "value": "32" - } - } - }, - "axis_numeric_master_0": { - "vlnv": "xilinx.com:user:axis_numeric_master_slave_simmodel:1.0", - "xci_name": "test_1_axis_numeric_master_0_0", - "xci_path": "ip\\test_1_axis_numeric_master_0_0\\test_1_axis_numeric_master_0_0.xci", - "inst_hier_path": "axis_numeric_master_0", - "parameters": { - "CLOCK_PERIOD_NS": { - "value": "10" - }, - "FILE_NAME_M1": { - "value": "../../../../m1.txt" - }, - "FILE_NAME_M2": { - "value": "../../../../m1.txt" - }, - "FILE_NAME_S": { - "value": "../../../../m1.txt" - }, - "HAS_MASTER2": { - "value": "false" - }, - "MASTER1_HAS_LAST": { - "value": "true" - }, - "MASTER1_HAS_USER": { - "value": "false" - }, - "MASTER2_HAS_LAST": { - "value": "false" - }, - "MASTER2_HAS_USER": { - "value": "false" - }, - "SLAVE_HAS_LAST": { - "value": "true" - }, - "SLAVE_HAS_USER": { - "value": "false" - }, - "SLAVE_WAIT_FOR_SOF": { - "value": "false" - } - } - }, - "axis_crc_0": { - "vlnv": "xilinx.com:module_ref:axis_crc:1.0", - "xci_name": "test_1_axis_crc_0_0", - "xci_path": "ip\\test_1_axis_crc_0_0\\test_1_axis_crc_0_0.xci", - "inst_hier_path": "axis_crc_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "axis_crc", - "boundary_crc": "0x0" - }, - "interface_ports": { - "M_AXIS": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "4", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "M_AXIS_TDATA", - "direction": "O", - "left": "31", - "right": "0" - }, - "TLAST": { - "physical_name": "M_AXIS_TLAST", - "direction": "O" - }, - "TVALID": { - "physical_name": "M_AXIS_TVALID", - "direction": "O" - }, - "TREADY": { - "physical_name": "M_AXIS_TREADY", - "direction": "I" - } - } - }, - "S_AXIS": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "4", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "S_AXIS_TDATA", - "direction": "I", - "left": "31", - "right": "0" - }, - "TLAST": { - "physical_name": "S_AXIS_TLAST", - "direction": "I" - }, - "TVALID": { - "physical_name": "S_AXIS_TVALID", - "direction": "I" - }, - "TREADY": { - "physical_name": "S_AXIS_TREADY", - "direction": "O" - } - } - } - }, - "ports": { - "CLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXIS:S_AXIS", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "RESETN", - "value_src": "constant" - } - } - }, - "RESETN": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - }, - "initial_value": { - "direction": "I", - "left": "31", - "right": "0" - }, - "polynomial": { - "direction": "I", - "left": "31", - "right": "0" - } - } - } - }, - "interface_nets": { - "axis_crc_0_M_AXIS": { - "interface_ports": [ - "axis_crc_0/M_AXIS", - "axis_numeric_master_0/S_AXIS" - ] - }, - "axis_numeric_master_0_M1_AXIS": { - "interface_ports": [ - "axis_numeric_master_0/M1_AXIS", - "axis_crc_0/S_AXIS" - ] - } - }, - "nets": { - "axis_numeric_master_0_CLK": { - "ports": [ - "axis_numeric_master_0/CLK", - "axis_crc_0/CLK" - ] - }, - "axis_numeric_master_0_RESETN": { - "ports": [ - "axis_numeric_master_0/RESETN", - "axis_crc_0/RESETN" - ] - }, - "xlconstant_0_dout": { - "ports": [ - "xlconstant_0/dout", - "axis_crc_0/initial_value" - ] - }, - "xlconstant_1_dout": { - "ports": [ - "xlconstant_1/dout", - "axis_crc_0/polynomial" - ] - } - } - } -} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ui/bd_7c56d984.ui b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ui/bd_7c56d984.ui deleted file mode 100644 index 93dfca2..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ui/bd_7c56d984.ui +++ /dev/null @@ -1,22 +0,0 @@ -{ - "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"2.0", - "Default View_TopLeft":"-85,-16", - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 -# -string -flagsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 1 -x 130 -y 260 -defaultsOSRD -preplace inst xlconstant_1 -pg 1 -lvl 1 -x 130 -y 360 -defaultsOSRD -preplace inst axis_numeric_master_0 -pg 1 -lvl 1 -x 130 -y 80 -defaultsOSRD -preplace inst axis_crc_0 -pg 1 -lvl 2 -x 400 -y 100 -defaultsOSRD -preplace netloc axis_numeric_master_0_CLK 1 1 1 N 80 -preplace netloc axis_numeric_master_0_RESETN 1 1 1 N 100 -preplace netloc xlconstant_0_dout 1 1 1 240J 120n -preplace netloc xlconstant_1_dout 1 1 1 250J 140n -preplace netloc axis_crc_0_M_AXIS 1 0 3 20 200 NJ 200 540 -preplace netloc axis_numeric_master_0_M1_AXIS 1 1 1 N 60 -levelinfo -pg 1 0 130 400 570 -pagesize -pg 1 -db -bbox -sgen 0 0 570 420 -" -} -0 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.xpr b/Hardware/aci_crc_dma/aci_crc_dma.xpr index d05f203..5945467 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.xpr +++ b/Hardware/aci_crc_dma/aci_crc_dma.xpr @@ -45,7 +45,7 @@