From 529f1a10d234bcdf1ccc53d821fac017b84cc2b6 Mon Sep 17 00:00:00 2001 From: Matthias Biermann Date: Sun, 2 Feb 2025 05:17:10 +0100 Subject: [PATCH] axis_crc Fehler gefixt --- .../axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml | 8 +- .../hdl/axi_crc_dma_sim_1_wrapper.vhd | 2 +- ...axi_crc_dma_sim_1_axi3_slave_verif_0_0.xml | 2 +- ...crc_dma_sim_1_axil_master_with_rom_0_0.xml | 11 +- ...crc_dma_sim_1_axil_master_with_rom_0_0.vhd | 2 +- .../axi_crc_dma_sim_1_axis_crc_0_0.xml | 2 +- .../axi_crc_dma_sim_1_axis_dma_0_0.xml | 61 ++++++- .../sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd | 5 + .../axi_crc_dma_sim_1_axis_fifo_1_0.xml | 2 +- .../sim/axi_crc_dma_sim_1.vhd | 35 ++-- .../synth/axi_crc_dma_sim_1.vhd | 35 ++-- .../bd/axis_crc_sim_1/axis_crc_sim_1.bxml | 55 +------ .../bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc | 10 -- .../hdl/axis_crc_sim_1_wrapper.vhd | 2 +- .../axis_crc_sim_1_axis_crc_0_0.xml | 131 ++------------- .../synth/axis_crc_sim_1_axis_crc_0_0.vhd | 132 --------------- .../bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd | 151 ------------------ .../axis_crc_sim_1/synth/axis_crc_sim_1.vhd | 151 ------------------ .../bd/mref/axi3_slave_verif/component.xml | 6 +- .../sources_1/bd/mref/axis_crc/component.xml | 6 +- .../sources_1/bd/mref/axis_dma/component.xml | 51 +++++- .../bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd | 47 +++++- ...crc_dma_sim_1_axil_master_with_rom_0_0.xci | 4 +- .../axi_crc_dma_sim_1_axis_crc_0_0.xci | 2 +- .../axi_crc_dma_sim_1_axis_dma_0_0.xci | 13 ++ .../bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui | 44 +++-- .../bd/axis_crc_sim_1/axis_crc_sim_1.bd | 3 +- .../bd/axis_crc_sim_1/ui/bd_9f9006c0.ui | 4 +- Hardware/aci_crc_dma/aci_crc_dma.xpr | 57 +------ Hardware/aci_crc_dma/axi_crc_dma_sim.mem | 17 +- .../axi_crc_dma_sim_1_wrapper_behav.wcfg | 89 ++++++++++- Hardware/axi3_slave_verif.vhd | 4 +- Hardware/axis_crc.vhd | 52 +++--- Hardware/axis_crc_16.vhd | 78 +++++++++ Hardware/axis_dma.vhd | 137 +++++++++++++--- Support/stm2mem/axi_crc_dma_sim.mem | 17 +- Support/stm2mem/axi_crc_dma_sim.stm | 13 +- 37 files changed, 630 insertions(+), 811 deletions(-) delete mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc delete mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/synth/axis_crc_sim_1_axis_crc_0_0.vhd delete mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd delete mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd create mode 100644 Hardware/axis_crc_16.vhd diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml index c6eade9..725bae8 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd index 711c981..25a376b 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd @@ -2,7 +2,7 @@ --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Sun Feb 2 01:00:12 2025 +--Date : Sun Feb 2 05:15:42 2025 --Host : BiermannSurface running 64-bit major release (build 9200) --Command : generate_target axi_crc_dma_sim_1_wrapper.bd --Design : axi_crc_dma_sim_1_wrapper diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xml index 3982670..13289ea 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xml @@ -664,7 +664,7 @@ GENtimestamp - Sat Feb 01 23:19:22 UTC 2025 + Sun Feb 02 02:02:02 UTC 2025 outputProductCRC diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml index e5b9a3a..60a8a9c 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml @@ -581,7 +581,7 @@ outputProductCRC - 9:8286588d + 9:be22c7e7 @@ -597,11 +597,11 @@ GENtimestamp - Sat Feb 01 23:19:22 UTC 2025 + Sun Feb 02 02:12:31 UTC 2025 outputProductCRC - 9:8286588d + 9:be22c7e7 @@ -983,7 +983,7 @@ REVISION_NO Revision No - 1 + 8 @@ -1039,7 +1039,7 @@ REVISION_NO Revision No - 1 + 8 @@ -1086,6 +1086,7 @@ + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd index 2622482..4179956 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd @@ -149,7 +149,7 @@ BEGIN STIM_FILENAME => "../../axi_crc_dma_sim.mem", HAS_FINISHED_OUT => false, HAS_INTERRUPT_IN => true, - REVISION_NO => 1 + REVISION_NO => 8 ) PORT MAP ( interrupt_in => interrupt_in, diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml index 3b7be1e..0bc43cb 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml @@ -461,7 +461,7 @@ GENtimestamp - Sat Feb 01 23:19:22 UTC 2025 + Sun Feb 02 04:07:29 UTC 2025 outputProductCRC diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml index aee8713..25c6d05 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml @@ -1424,6 +1424,37 @@ + + INTERRUPT + + + + + + + INTERRUPT + + + INTERRUPT + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + @@ -1457,7 +1488,7 @@ outputProductCRC - 9:e65ec1c3 + 9:91ac5338 @@ -1473,11 +1504,11 @@ GENtimestamp - Sat Feb 01 23:59:43 UTC 2025 + Sun Feb 02 04:15:43 UTC 2025 outputProductCRC - 9:e65ec1c3 + 9:91ac5338 @@ -1507,6 +1538,21 @@ + + INTERRUPT + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + initial_value @@ -2516,6 +2562,13 @@ + + choice_list_99a1d2b9 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + choice_list_9d8b0d81 ACTIVE_HIGH @@ -2582,6 +2635,8 @@ + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd index 45c5779..80b8db0 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd @@ -57,6 +57,7 @@ ENTITY axi_crc_dma_sim_1_axis_dma_0_0 IS PORT ( CLK : IN STD_LOGIC; RESETN : IN STD_LOGIC; + INTERRUPT : OUT STD_LOGIC; initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0); @@ -138,6 +139,7 @@ ARCHITECTURE axi_crc_dma_sim_1_axis_dma_0_0_arch OF axi_crc_dma_sim_1_axis_dma_0 PORT ( CLK : IN STD_LOGIC; RESETN : IN STD_LOGIC; + INTERRUPT : OUT STD_LOGIC; initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0); @@ -207,6 +209,8 @@ ARCHITECTURE axi_crc_dma_sim_1_axis_dma_0_0_arch OF axi_crc_dma_sim_1_axis_dma_0 ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1"; + ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; @@ -287,6 +291,7 @@ BEGIN PORT MAP ( CLK => CLK, RESETN => RESETN, + INTERRUPT => INTERRUPT, initial_value => initial_value, polynomial => polynomial, FIFO_NUM_FREE => FIFO_NUM_FREE, diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml index 919f82a..b030051 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml @@ -1167,7 +1167,7 @@ GENtimestamp - Sat Feb 01 23:19:22 UTC 2025 + Sun Feb 02 01:19:48 UTC 2025 outputProductCRC diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd index 5747598..e9d0d70 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd @@ -2,7 +2,7 @@ --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Sun Feb 2 01:00:12 2025 +--Date : Sun Feb 2 05:15:42 2025 --Host : BiermannSurface running 64-bit major release (build 9200) --Command : generate_target axi_crc_dma_sim_1.bd --Design : axi_crc_dma_sim_1 @@ -15,6 +15,7 @@ use UNISIM.VCOMPONENTS.ALL; entity axi_crc_dma_imp_1PQG7GB is port ( CLK : in STD_LOGIC; + INTERRUPT : out STD_LOGIC; M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); @@ -124,6 +125,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is port ( CLK : in STD_LOGIC; RESETN : in STD_LOGIC; + INTERRUPT : out STD_LOGIC; initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 ); polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 ); FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 ); @@ -235,6 +237,11 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Conn2_WVALID : STD_LOGIC; signal RESETN_1 : STD_LOGIC; + signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_dma_0_INTERRUPT : STD_LOGIC; signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC; signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC; @@ -251,10 +258,6 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC; signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC; signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -286,6 +289,7 @@ begin Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); Conn2_RVALID <= M_AXI_rvalid; Conn2_WREADY <= M_AXI_wready; + INTERRUPT <= axis_dma_0_INTERRUPT; M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0); M_AXI_arid(0) <= Conn2_ARID(0); @@ -315,10 +319,10 @@ begin axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0 port map ( CLK => CLK_1, - M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + M_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY, + M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID, RESETN => RESETN_1, S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0), S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST, @@ -332,6 +336,7 @@ axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0 CLK => CLK_1, FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0), FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0), + INTERRUPT => axis_dma_0_INTERRUPT, M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0), M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST, M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY, @@ -426,11 +431,11 @@ axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0 M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0), S_AXIS_ACLK => CLK_1, S_AXIS_ARESETN => RESETN_1, - S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, - S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + S_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY, S_AXIS_TUSER(0) => '0', - S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID, S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0) ); end STRUCTURE; @@ -514,6 +519,7 @@ architecture STRUCTURE of axi_crc_dma_sim_1 is S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ) ); end component axi_crc_dma_sim_1_axi3_slave_verif_0_0; + signal axi_crc_dma_INTERRUPT : STD_LOGIC; signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); @@ -598,6 +604,7 @@ axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0 axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB port map ( CLK => clk_rst_generator_0_clk, + INTERRUPT => axi_crc_dma_INTERRUPT, M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0), M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0), M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0), @@ -667,7 +674,7 @@ axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0 M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY, M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID, - interrupt_in => '0' + interrupt_in => axi_crc_dma_INTERRUPT ); clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0 port map ( diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd index 5747598..e9d0d70 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd @@ -2,7 +2,7 @@ --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Sun Feb 2 01:00:12 2025 +--Date : Sun Feb 2 05:15:42 2025 --Host : BiermannSurface running 64-bit major release (build 9200) --Command : generate_target axi_crc_dma_sim_1.bd --Design : axi_crc_dma_sim_1 @@ -15,6 +15,7 @@ use UNISIM.VCOMPONENTS.ALL; entity axi_crc_dma_imp_1PQG7GB is port ( CLK : in STD_LOGIC; + INTERRUPT : out STD_LOGIC; M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); @@ -124,6 +125,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is port ( CLK : in STD_LOGIC; RESETN : in STD_LOGIC; + INTERRUPT : out STD_LOGIC; initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 ); polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 ); FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 ); @@ -235,6 +237,11 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Conn2_WVALID : STD_LOGIC; signal RESETN_1 : STD_LOGIC; + signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_dma_0_INTERRUPT : STD_LOGIC; signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC; signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC; @@ -251,10 +258,6 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC; signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC; signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -286,6 +289,7 @@ begin Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); Conn2_RVALID <= M_AXI_rvalid; Conn2_WREADY <= M_AXI_wready; + INTERRUPT <= axis_dma_0_INTERRUPT; M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0); M_AXI_arid(0) <= Conn2_ARID(0); @@ -315,10 +319,10 @@ begin axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0 port map ( CLK => CLK_1, - M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + M_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY, + M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID, RESETN => RESETN_1, S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0), S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST, @@ -332,6 +336,7 @@ axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0 CLK => CLK_1, FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0), FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0), + INTERRUPT => axis_dma_0_INTERRUPT, M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0), M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST, M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY, @@ -426,11 +431,11 @@ axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0 M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0), S_AXIS_ACLK => CLK_1, S_AXIS_ARESETN => RESETN_1, - S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, - S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + S_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY, S_AXIS_TUSER(0) => '0', - S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID, S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0) ); end STRUCTURE; @@ -514,6 +519,7 @@ architecture STRUCTURE of axi_crc_dma_sim_1 is S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ) ); end component axi_crc_dma_sim_1_axi3_slave_verif_0_0; + signal axi_crc_dma_INTERRUPT : STD_LOGIC; signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); @@ -598,6 +604,7 @@ axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0 axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB port map ( CLK => clk_rst_generator_0_clk, + INTERRUPT => axi_crc_dma_INTERRUPT, M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0), M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0), M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0), @@ -667,7 +674,7 @@ axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0 M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY, M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID, - interrupt_in => '0' + interrupt_in => axi_crc_dma_INTERRUPT ); clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0 port map ( diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml index 30d9736..41a9673 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml @@ -2,55 +2,10 @@ Composite Fileset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc deleted file mode 100644 index 7fac2b2..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc +++ /dev/null @@ -1,10 +0,0 @@ -################################################################################ - -# This XDC is used only for OOC mode of synthesis, implementation -# This constraints file contains default clock frequencies to be used during -# out-of-context flows such as OOC Synthesis and Hierarchical Designs. -# This constraints file is not used in normal top-down synthesis (default flow -# of Vivado) -################################################################################ - -################################################################################ \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd index f3624fd..f554e70 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd @@ -2,7 +2,7 @@ --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Sun Feb 2 00:16:45 2025 +--Date : Sun Feb 2 04:32:07 2025 --Host : BiermannSurface running 64-bit major release (build 9200) --Command : generate_target axis_crc_sim_1_wrapper.bd --Design : axis_crc_sim_1_wrapper diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml index 4071b75..8b11386 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml @@ -436,83 +436,6 @@ - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - axis_crc - - - outputProductCRC - 9:7d52f37a - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - axis_crc - - - outputProductCRC - 9:3fed59a8 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:3fed59a8 - - - - - xilinx_vhdlsimulationwrapper - VHDL Simulation Wrapper - vhdlSource:vivado.xilinx.com:simulation.wrapper - vhdl - axis_crc_sim_1_axis_crc_0_0 - - xilinx_vhdlsimulationwrapper_view_fileset - - - - GENtimestamp - Sat Feb 01 23:16:45 UTC 2025 - - - outputProductCRC - 9:7d52f37a - - - - - xilinx_vhdlsynthesiswrapper - VHDL Synthesis Wrapper - vhdlSource:vivado.xilinx.com:synthesis.wrapper - vhdl - axis_crc_sim_1_axis_crc_0_0 - - xilinx_vhdlsynthesiswrapper_view_fileset - - - - GENtimestamp - Sat Feb 01 23:59:37 UTC 2025 - - - outputProductCRC - 9:3fed59a8 - - - - CLK @@ -521,8 +444,7 @@ std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -534,8 +456,7 @@ std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -551,8 +472,7 @@ std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -568,8 +488,7 @@ std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -581,8 +500,7 @@ std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -598,8 +516,7 @@ std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -614,8 +531,7 @@ std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -630,8 +546,7 @@ std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -643,8 +558,7 @@ std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -660,8 +574,7 @@ std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -673,8 +586,7 @@ std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -686,8 +598,7 @@ std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -704,24 +615,6 @@ ACTIVE_LOW - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/axis_crc_sim_1_axis_crc_0_0.vhd - vhdlSource - xil_defaultlib - - - - xilinx_vhdlsynthesiswrapper_view_fileset - - synth/axis_crc_sim_1_axis_crc_0_0.vhd - vhdlSource - xil_defaultlib - - - xilinx.com:module_ref:axis_crc:1.0 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/synth/axis_crc_sim_1_axis_crc_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/synth/axis_crc_sim_1_axis_crc_0_0.vhd deleted file mode 100644 index 3007447..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/synth/axis_crc_sim_1_axis_crc_0_0.vhd +++ /dev/null @@ -1,132 +0,0 @@ --- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of AMD and is protected under U.S. and international copyright --- and other intellectual property laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- AMD, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) AMD shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or AMD had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- AMD products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of AMD products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:module_ref:axis_crc:1.0 --- IP Revision: 1 - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY axis_crc_sim_1_axis_crc_0_0 IS - PORT ( - CLK : IN STD_LOGIC; - RESETN : IN STD_LOGIC; - initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_TVALID : IN STD_LOGIC; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_TLAST : IN STD_LOGIC; - S_AXIS_TREADY : OUT STD_LOGIC; - M_AXIS_TVALID : OUT STD_LOGIC; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M_AXIS_TLAST : OUT STD_LOGIC; - M_AXIS_TREADY : IN STD_LOGIC - ); -END axis_crc_sim_1_axis_crc_0_0; - -ARCHITECTURE axis_crc_sim_1_axis_crc_0_0_arch OF axis_crc_sim_1_axis_crc_0_0 IS - ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; - ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes"; - COMPONENT axis_crc IS - PORT ( - CLK : IN STD_LOGIC; - RESETN : IN STD_LOGIC; - initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_TVALID : IN STD_LOGIC; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - S_AXIS_TLAST : IN STD_LOGIC; - S_AXIS_TREADY : OUT STD_LOGIC; - M_AXIS_TVALID : OUT STD_LOGIC; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - M_AXIS_TLAST : OUT STD_LOGIC; - M_AXIS_TREADY : IN STD_LOGIC - ); - END COMPONENT axis_crc; - ATTRIBUTE X_CORE_INFO : STRING; - ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc,Vivado 2023.1"; - ATTRIBUTE CHECK_LICENSE_TYPE : STRING; - ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_axis_crc_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_axis_crc_0_0,axis_crc,{}"; - ATTRIBUTE CORE_GENERATION_INFO : STRING; - ATTRIBUTE CORE_GENERATION_INFO OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc_sim_1_axis_crc_0_0,axis_crc,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_crc,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; - ATTRIBUTE IP_DEFINITION_SOURCE : STRING; - ATTRIBUTE IP_DEFINITION_SOURCE OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "module_ref"; - ATTRIBUTE X_INTERFACE_INFO : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; - ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; - ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; - ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; - ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; -BEGIN - U0 : axis_crc - PORT MAP ( - CLK => CLK, - RESETN => RESETN, - initial_value => initial_value, - polynomial => polynomial, - S_AXIS_TVALID => S_AXIS_TVALID, - S_AXIS_TDATA => S_AXIS_TDATA, - S_AXIS_TLAST => S_AXIS_TLAST, - S_AXIS_TREADY => S_AXIS_TREADY, - M_AXIS_TVALID => M_AXIS_TVALID, - M_AXIS_TDATA => M_AXIS_TDATA, - M_AXIS_TLAST => M_AXIS_TLAST, - M_AXIS_TREADY => M_AXIS_TREADY - ); -END axis_crc_sim_1_axis_crc_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd deleted file mode 100644 index 32cbc36..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd +++ /dev/null @@ -1,151 +0,0 @@ ---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- ---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Sun Feb 2 00:16:45 2025 ---Host : BiermannSurface running 64-bit major release (build 9200) ---Command : generate_target axis_crc_sim_1.bd ---Design : axis_crc_sim_1 ---Purpose : IP block netlist ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity axis_crc_sim_1 is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; - attribute HW_HANDOFF : string; - attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef"; -end axis_crc_sim_1; - -architecture STRUCTURE of axis_crc_sim_1 is - component axis_crc_sim_1_clk_rst_generator_0_0 is - port ( - clk_in : in STD_LOGIC; - rst_in : in STD_LOGIC; - clk : out STD_LOGIC; - rst_n : out STD_LOGIC; - stop_simulation : in STD_LOGIC - ); - end component axis_crc_sim_1_clk_rst_generator_0_0; - component axis_crc_sim_1_axis_slave_simmodel_0_0 is - port ( - FINISHED : out STD_LOGIC; - S_AXIS_ACLK : in STD_LOGIC; - S_AXIS_ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - end component axis_crc_sim_1_axis_slave_simmodel_0_0; - component axis_crc_sim_1_axis_master_simmodel_0_0 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - FINISHED : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - end component axis_crc_sim_1_axis_master_simmodel_0_0; - component axis_crc_sim_1_xlconstant_1_0 is - port ( - dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - end component axis_crc_sim_1_xlconstant_1_0; - component axis_crc_sim_1_xlconstant_0_0 is - port ( - dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - end component axis_crc_sim_1_xlconstant_0_0; - component axis_crc_sim_1_axis_crc_0_0 is - port ( - CLK : in STD_LOGIC; - RESETN : in STD_LOGIC; - initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 ); - polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC - ); - end component axis_crc_sim_1_axis_crc_0_0; - signal AXIS_ARESETN_1 : STD_LOGIC; - signal axis_master_simmodel_0_FINISHED : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; - signal clk_rst_generator_0_clk : STD_LOGIC; - signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal crc_M_AXIS_TLAST : STD_LOGIC; - signal crc_M_AXIS_TREADY : STD_LOGIC; - signal crc_M_AXIS_TVALID : STD_LOGIC; - signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC; -begin -axis_crc_0: component axis_crc_sim_1_axis_crc_0_0 - port map ( - CLK => clk_rst_generator_0_clk, - M_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => crc_M_AXIS_TLAST, - M_AXIS_TREADY => crc_M_AXIS_TREADY, - M_AXIS_TVALID => crc_M_AXIS_TVALID, - RESETN => AXIS_ARESETN_1, - S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, - S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID, - initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0), - polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0) - ); -axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0 - port map ( - ACLK => clk_rst_generator_0_clk, - ARESETN => AXIS_ARESETN_1, - FINISHED => axis_master_simmodel_0_FINISHED, - M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, - M_AXIS_TUSER(0) => NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED(0), - M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID - ); -axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0 - port map ( - FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED, - S_AXIS_ACLK => clk_rst_generator_0_clk, - S_AXIS_ARESETN => AXIS_ARESETN_1, - S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => crc_M_AXIS_TLAST, - S_AXIS_TREADY => crc_M_AXIS_TREADY, - S_AXIS_TUSER(0) => '0', - S_AXIS_TVALID => crc_M_AXIS_TVALID - ); -clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0 - port map ( - clk => clk_rst_generator_0_clk, - clk_in => '1', - rst_in => '0', - rst_n => AXIS_ARESETN_1, - stop_simulation => axis_master_simmodel_0_FINISHED - ); -xlconstant_0: component axis_crc_sim_1_xlconstant_0_0 - port map ( - dout(31 downto 0) => xlconstant_0_dout(31 downto 0) - ); -xlconstant_1: component axis_crc_sim_1_xlconstant_1_0 - port map ( - dout(31 downto 0) => xlconstant_1_dout(31 downto 0) - ); -end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd deleted file mode 100644 index 32cbc36..0000000 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd +++ /dev/null @@ -1,151 +0,0 @@ ---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- ---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Sun Feb 2 00:16:45 2025 ---Host : BiermannSurface running 64-bit major release (build 9200) ---Command : generate_target axis_crc_sim_1.bd ---Design : axis_crc_sim_1 ---Purpose : IP block netlist ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity axis_crc_sim_1 is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; - attribute HW_HANDOFF : string; - attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef"; -end axis_crc_sim_1; - -architecture STRUCTURE of axis_crc_sim_1 is - component axis_crc_sim_1_clk_rst_generator_0_0 is - port ( - clk_in : in STD_LOGIC; - rst_in : in STD_LOGIC; - clk : out STD_LOGIC; - rst_n : out STD_LOGIC; - stop_simulation : in STD_LOGIC - ); - end component axis_crc_sim_1_clk_rst_generator_0_0; - component axis_crc_sim_1_axis_slave_simmodel_0_0 is - port ( - FINISHED : out STD_LOGIC; - S_AXIS_ACLK : in STD_LOGIC; - S_AXIS_ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - end component axis_crc_sim_1_axis_slave_simmodel_0_0; - component axis_crc_sim_1_axis_master_simmodel_0_0 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - FINISHED : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - end component axis_crc_sim_1_axis_master_simmodel_0_0; - component axis_crc_sim_1_xlconstant_1_0 is - port ( - dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - end component axis_crc_sim_1_xlconstant_1_0; - component axis_crc_sim_1_xlconstant_0_0 is - port ( - dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - end component axis_crc_sim_1_xlconstant_0_0; - component axis_crc_sim_1_axis_crc_0_0 is - port ( - CLK : in STD_LOGIC; - RESETN : in STD_LOGIC; - initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 ); - polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC - ); - end component axis_crc_sim_1_axis_crc_0_0; - signal AXIS_ARESETN_1 : STD_LOGIC; - signal axis_master_simmodel_0_FINISHED : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; - signal clk_rst_generator_0_clk : STD_LOGIC; - signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal crc_M_AXIS_TLAST : STD_LOGIC; - signal crc_M_AXIS_TREADY : STD_LOGIC; - signal crc_M_AXIS_TVALID : STD_LOGIC; - signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC; -begin -axis_crc_0: component axis_crc_sim_1_axis_crc_0_0 - port map ( - CLK => clk_rst_generator_0_clk, - M_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => crc_M_AXIS_TLAST, - M_AXIS_TREADY => crc_M_AXIS_TREADY, - M_AXIS_TVALID => crc_M_AXIS_TVALID, - RESETN => AXIS_ARESETN_1, - S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, - S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID, - initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0), - polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0) - ); -axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0 - port map ( - ACLK => clk_rst_generator_0_clk, - ARESETN => AXIS_ARESETN_1, - FINISHED => axis_master_simmodel_0_FINISHED, - M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, - M_AXIS_TUSER(0) => NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED(0), - M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID - ); -axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0 - port map ( - FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED, - S_AXIS_ACLK => clk_rst_generator_0_clk, - S_AXIS_ARESETN => AXIS_ARESETN_1, - S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => crc_M_AXIS_TLAST, - S_AXIS_TREADY => crc_M_AXIS_TREADY, - S_AXIS_TUSER(0) => '0', - S_AXIS_TVALID => crc_M_AXIS_TVALID - ); -clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0 - port map ( - clk => clk_rst_generator_0_clk, - clk_in => '1', - rst_in => '0', - rst_n => AXIS_ARESETN_1, - stop_simulation => axis_master_simmodel_0_FINISHED - ); -xlconstant_0: component axis_crc_sim_1_xlconstant_0_0 - port map ( - dout(31 downto 0) => xlconstant_0_dout(31 downto 0) - ); -xlconstant_1: component axis_crc_sim_1_xlconstant_1_0 - port map ( - dout(31 downto 0) => xlconstant_1_dout(31 downto 0) - ); -end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/component.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/component.xml index 23e8113..fe31bb5 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/component.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/component.xml @@ -305,7 +305,7 @@ viewChecksum - 6d6387c1 + 4b08b998 @@ -318,7 +318,7 @@ viewChecksum - 6d6387c1 + 4b08b998 @@ -906,7 +906,7 @@ IPI 1 - 2025-02-01T20:40:20Z + 2025-02-02T02:01:58Z 2023.1 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml index 22d0c8d..40c9f16 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml @@ -145,7 +145,7 @@ viewChecksum - b45c4280 + 8ca8a756 @@ -158,7 +158,7 @@ viewChecksum - b45c4280 + 8ca8a756 @@ -395,7 +395,7 @@ IPI 1 - 2025-02-01T19:31:07Z + 2025-02-02T04:07:21Z 2023.1 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml index 711340c..ae59454 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml @@ -561,6 +561,28 @@ + + INTERRUPT + + + + + + + INTERRUPT + + + INTERRUPT + + + + + + SENSITIVITY + LEVEL_HIGH + + + @@ -595,7 +617,7 @@ viewChecksum - ba1cd223 + 2b97c8af @@ -608,7 +630,7 @@ viewChecksum - ba1cd223 + 2b97c8af @@ -648,6 +670,22 @@ + + INTERRUPT + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + initial_value @@ -1725,6 +1763,13 @@ ACTIVE_HIGH ACTIVE_LOW + + choice_list_9ca20931 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + @@ -1789,7 +1834,7 @@ IPI 1 - 2025-02-01T23:59:34Z + 2025-02-02T04:15:37Z 2023.1 diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd index 81f763b..7dfa5c8 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd @@ -43,6 +43,10 @@ "RESETN": { "type": "rst", "direction": "I" + }, + "INTERRUPT": { + "type": "intr", + "direction": "O" } }, "components": { @@ -861,6 +865,20 @@ } } }, + "INTERRUPT": { + "type": "intr", + "direction": "O", + "parameters": { + "SENSITIVITY": { + "value": "LEVEL_HIGH", + "value_src": "constant" + }, + "PortWidth": { + "value": "1", + "value_src": "default_prop" + } + } + }, "initial_value": { "direction": "O", "left": "31", @@ -905,6 +923,12 @@ "M_AXI" ] }, + "axis_crc_0_M_AXIS": { + "interface_ports": [ + "axis_crc_0/M_AXIS", + "axis_fifo_1/S_AXIS" + ] + }, "axis_dma_0_M_AXIS": { "interface_ports": [ "axis_dma_0/M_AXIS", @@ -922,12 +946,6 @@ "axis_fifo_1/M_AXIS", "axis_dma_0/S_AXIS" ] - }, - "axis_upsizer_0_M_AXIS": { - "interface_ports": [ - "axis_crc_0/M_AXIS", - "axis_fifo_1/S_AXIS" - ] } }, "nets": { @@ -948,11 +966,17 @@ "axis_fifo_0/M_AXIS_ARESETN", "axis_fifo_1/S_AXIS_ARESETN", "axis_fifo_1/M_AXIS_ARESETN", - "axis_crc_0/RESETN", "axis_fifo_0/S_AXIS_ARESETN", + "axis_crc_0/RESETN", "axis_dma_0/RESETN" ] }, + "axis_dma_0_INTERRUPT": { + "ports": [ + "axis_dma_0/INTERRUPT", + "INTERRUPT" + ] + }, "axis_dma_0_initial_value": { "ports": [ "axis_dma_0/initial_value", @@ -985,6 +1009,9 @@ "xci_path": "ip\\axi_crc_dma_sim_1_axil_master_with_rom_0_0\\axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci", "inst_hier_path": "axil_master_with_rom_0", "parameters": { + "REVISION_NO": { + "value": "8" + }, "STIM_FILENAME": { "value": "../../axi_crc_dma_sim.mem" } @@ -1311,6 +1338,12 @@ } }, "nets": { + "axi_crc_dma_INTERRUPT": { + "ports": [ + "axi_crc_dma/INTERRUPT", + "axil_master_with_rom_0/interrupt_in" + ] + }, "clk_rst_generator_0_clk": { "ports": [ "clk_rst_generator_0/clk", diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci index ff83833..4762fb4 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci @@ -12,13 +12,13 @@ "Component_Name": [ { "value": "axi_crc_dma_sim_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ], "HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "REVISION_NO": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ] + "REVISION_NO": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ] }, "model_parameters": { "STIM_FILENAME": [ { "value": "../../axi_crc_dma_sim.mem", "resolve_type": "generated", "usage": "all" } ], "HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], - "REVISION_NO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] + "REVISION_NO": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { "ARCHITECTURE": [ { "value": "zynq" } ], diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci index 841e5b2..78a628e 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci @@ -2,7 +2,7 @@ "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { "xci_name": "axi_crc_dma_sim_1_axis_crc_0_0", - "cell_name": "axi_crc_dma/axis_crc_0", + "cell_name": "axis_crc_0", "component_reference": "xilinx.com:module_ref:axis_crc:1.0", "ip_revision": "1", "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0", diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci index 807e84b..68f3ac8 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci @@ -52,6 +52,7 @@ "ports": { "CLK": [ { "direction": "in" } ], "RESETN": [ { "direction": "in" } ], + "INTERRUPT": [ { "direction": "out", "driver_value": "0x0" } ], "initial_value": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], "polynomial": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], "FIFO_NUM_FREE": [ { "direction": "in", "size_left": "7", "size_right": "0" } ], @@ -331,6 +332,18 @@ "port_maps": { "CLK": [ { "physical_name": "CLK" } ] } + }, + "INTERRUPT": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "INTERRUPT": [ { "physical_name": "INTERRUPT" } ] + } } }, "address_spaces": { diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui index b3691c0..3b10a8f 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui @@ -1,7 +1,7 @@ { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"1.25", - "Default View_TopLeft":"-146,-50", + "Default View_ScaleFactor":"0.947325", + "Default View_TopLeft":"333,-198", "Display-PortTypeOthers":"true", "ExpandedHierarchyInLayout":"", "Interfaces View_ExpandedHierarchyInLayout":"", @@ -19,16 +19,36 @@ pagesize -pg 1 -db -bbox -sgen 0 0 1990 480 "Interfaces View_TopLeft":"-199,-369", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD -preplace inst axi_crc_dma -pg 1 -lvl 3 -x 620 -y 240 -defaultsOSRD -preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 350 -y 210 -defaultsOSRD -preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 130 -defaultsOSRD -preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 850 -y 260 -defaultsOSRD -preplace netloc clk_rst_generator_0_clk 1 1 3 230 290 510 310 720J -preplace netloc clk_rst_generator_0_rst_n 1 1 3 220 300 520 320 730J -preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 470 210n -preplace netloc axi_crc_dma_M_AXI 1 3 1 N 240 -levelinfo -pg 1 0 110 350 620 850 940 -pagesize -pg 1 -db -bbox -sgen 0 0 940 340 +preplace inst axi_crc_dma -pg 1 -lvl 3 -x 660 -y -60 -defaultsOSRD +preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 360 -y 310 -defaultsOSRD +preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 220 -defaultsOSRD +preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 2220 -y 340 -defaultsOSRD +preplace inst axi_crc_dma|axis_fifo_0 -pg 1 -lvl 1 -x 790 -y 0 -defaultsOSRD +preplace inst axi_crc_dma|axis_fifo_1 -pg 1 -lvl 3 -x 1450 -y 60 -defaultsOSRD +preplace inst axi_crc_dma|axis_crc_0 -pg 1 -lvl 2 -x 1120 -y 300 -defaultsOSRD +preplace inst axi_crc_dma|axis_dma_0 -pg 1 -lvl 4 -x 1800 -y 200 -defaultsOSRD +preplace netloc clk_rst_generator_0_clk 1 1 3 230 190 480 -140 2130J +preplace netloc clk_rst_generator_0_rst_n 1 1 3 220 390 500 420 2130J +preplace netloc axi_crc_dma_INTERRUPT 1 1 3 240 430 NJ 430 2110 +preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 490 170n +preplace netloc axi_crc_dma_M_AXI 1 3 1 2120 180n +preplace netloc axi_crc_dma|CLK_1 1 0 4 630 180 950 180 1290 190 NJ +preplace netloc axi_crc_dma|RESETN_1 1 0 4 640 160 960 160 1300 180 1610J +preplace netloc axi_crc_dma|axis_fifo_0_S_NUM_FREE 1 1 3 980 -40 N -40 1620J +preplace netloc axi_crc_dma|axis_fifo_1_M_NUM_AVAIL 1 3 1 1600 80n +preplace netloc axi_crc_dma|axis_dma_0_INTERRUPT 1 4 1 N 200 +preplace netloc axi_crc_dma|axis_dma_0_initial_value 1 1 4 970 190 1280J 310 NJ 310 1980 +preplace netloc axi_crc_dma|axis_dma_0_polynomial 1 1 4 980 200 1260J 320 NJ 320 1970 +preplace netloc axi_crc_dma|Conn1 1 0 4 NJ 170 NJ 170 N 170 NJ +preplace netloc axi_crc_dma|axis_dma_0_M_AXIS 1 0 5 640 -100 NJ -100 N -100 NJ -100 1970 +preplace netloc axi_crc_dma|axis_fifo_1_M_AXIS 1 3 1 1630 40n +preplace netloc axi_crc_dma|Conn2 1 4 1 N 180 +preplace netloc axi_crc_dma|axis_fifo_0_M_AXIS 1 1 1 940 -20n +preplace netloc axi_crc_dma|axis_crc_0_M_AXIS 1 2 1 1270 20n +levelinfo -pg 1 0 110 360 660 2220 2310 +levelinfo -hier axi_crc_dma * 790 1120 1450 1800 * +pagesize -pg 1 -db -bbox -sgen 0 -150 2340 690 +pagesize -hier axi_crc_dma -db -bbox -sgen 580 -110 2010 400 " } { diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd index 02f0bd1..2809374 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd @@ -7,8 +7,7 @@ "name": "axis_crc_sim_1", "rev_ctrl_bd_flag": "RevCtrlBdOff", "synth_flow_mode": "Hierarchical", - "tool_version": "2023.1", - "validated": "true" + "tool_version": "2023.1" }, "design_tree": { "clk_rst_generator_0": "", diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui index df0f237..aa23bc6 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui @@ -1,7 +1,7 @@ { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"2.0", - "Default View_TopLeft":"187,103", + "Default View_ScaleFactor":"1.25", + "Default View_TopLeft":"-162,-36", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD diff --git a/Hardware/aci_crc_dma/aci_crc_dma.xpr b/Hardware/aci_crc_dma/aci_crc_dma.xpr index 5945467..37ae552 100644 --- a/Hardware/aci_crc_dma/aci_crc_dma.xpr +++ b/Hardware/aci_crc_dma/aci_crc_dma.xpr @@ -61,20 +61,20 @@