diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip.bxml
index 9111212..d3a9f7a 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip.bxml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip.bxml
@@ -2,10 +2,10 @@
Composite Fileset
-
-
-
-
+
+
+
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_crc_0_0/axi_crc_dma_ip_axis_crc_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_crc_0_0/axi_crc_dma_ip_axis_crc_0_0.xml
index 95f56ca..0a5dd87 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_crc_0_0/axi_crc_dma_ip_axis_crc_0_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_crc_0_0/axi_crc_dma_ip_axis_crc_0_0.xml
@@ -462,7 +462,7 @@
- initial_value
+ initialValue
in
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0.xml
index adf1f89..894fbc7 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0.xml
@@ -1520,7 +1520,7 @@
- initial_value
+ initialValue
out
@@ -2555,11 +2555,6 @@
Polynomial Default
0x04C11DB7
-
- initial_value_default
- Initial Value Default
- 0x00000000
-
@@ -2603,11 +2598,6 @@
Polynomial Default
0x04C11DB7
-
- initial_value_default
- Initial Value Default
- 0x00000000
-
Component_Name
axi_crc_dma_ip_axis_dma_0_0
@@ -2628,22 +2618,22 @@
-
-
-
-
+
+
+
+
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
@@ -2651,13 +2641,13 @@
-
-
+
+
-
+
-
+
@@ -2671,36 +2661,36 @@
-
-
-
-
+
+
+
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
-
+
-
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml
index 0ae34fe..0ad0869 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml
@@ -2,10 +2,10 @@
Composite Fileset
-
-
-
-
+
+
+
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd
index caadb4c..a7c9acb 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
---Date : Tue Feb 11 20:14:47 2025
+--Date : Wed Feb 12 11:55:39 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_sim_1_wrapper.bd
--Design : axi_crc_dma_sim_1_wrapper
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml
index fe8a6a5..a798e8f 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml
@@ -445,7 +445,7 @@
outputProductCRC
- 9:bba2692b
+ 9:0784c673
@@ -461,11 +461,11 @@
GENtimestamp
- Tue Feb 11 19:14:47 UTC 2025
+ Wed Feb 12 10:55:39 UTC 2025
outputProductCRC
- 9:bba2692b
+ 9:0784c673
@@ -496,7 +496,7 @@
- initial_value
+ initialValue
in
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd
index 351865f..5de5bf8 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd
@@ -57,7 +57,7 @@ ENTITY axi_crc_dma_sim_1_axis_crc_0_0 IS
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
- initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ initialValue : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -79,7 +79,7 @@ ARCHITECTURE axi_crc_dma_sim_1_axis_crc_0_0_arch OF axi_crc_dma_sim_1_axis_crc_0
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
- initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ initialValue : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -114,7 +114,7 @@ BEGIN
PORT MAP (
CLK => CLK,
RESETN => RESETN,
- initial_value => initial_value,
+ initialValue => initialValue,
polynomial => polynomial,
finalXOR => finalXOR,
inOutReflected => inOutReflected,
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml
index ea6d95b..9dabba3 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml
@@ -1488,7 +1488,7 @@
outputProductCRC
- 9:a1417149
+ 9:f9e4e24a
@@ -1504,11 +1504,11 @@
GENtimestamp
- Mon Feb 10 22:24:31 UTC 2025
+ Wed Feb 12 10:55:39 UTC 2025
outputProductCRC
- 9:a1417149
+ 9:f9e4e24a
@@ -1554,7 +1554,7 @@
- initial_value
+ initialValue
out
@@ -2589,11 +2589,6 @@
Polynomial Default
0x04C11DB7
-
- initial_value_default
- Initial Value Default
- 0x00000000
-
@@ -2647,11 +2642,6 @@
Polynomial Default
0x04C11DB7
-
- initial_value_default
- Initial Value Default
- 0x00000000
-
Component_Name
axi_crc_dma_sim_1_axis_dma_0_0
@@ -2672,22 +2662,22 @@
-
-
-
-
+
+
+
+
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
@@ -2695,13 +2685,13 @@
-
-
+
+
-
+
-
+
@@ -2715,36 +2705,36 @@
-
-
-
-
+
+
+
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
-
+
-
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd
index 4051875..77ccfe7 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd
@@ -58,7 +58,7 @@ ENTITY axi_crc_dma_sim_1_axis_dma_0_0 IS
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
- initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ initialValue : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -135,14 +135,13 @@ ARCHITECTURE axi_crc_dma_sim_1_axis_dma_0_0_arch OF axi_crc_dma_sim_1_axis_dma_0
IDWIDTH : INTEGER;
MAX_BURSTLEN : INTEGER;
FIFO_AWIDTH : INTEGER;
- polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0);
- initial_value_default : STD_LOGIC_VECTOR(31 DOWNTO 0)
+ polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
- initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ initialValue : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -289,14 +288,13 @@ BEGIN
IDWIDTH => 1,
MAX_BURSTLEN => 16,
FIFO_AWIDTH => 8,
- polynomial_default => X"04C11DB7",
- initial_value_default => X"00000000"
+ polynomial_default => X"04C11DB7"
)
PORT MAP (
CLK => CLK,
RESETN => RESETN,
INTERRUPT => INTERRUPT,
- initial_value => initial_value,
+ initialValue => initialValue,
polynomial => polynomial,
finalXOR => finalXOR,
inOutReflected => inOutReflected,
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd
index ab723dd..56b6031 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
---Date : Tue Feb 11 20:14:47 2025
+--Date : Wed Feb 12 11:55:39 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_sim_1.bd
--Design : axi_crc_dma_sim_1
@@ -110,7 +110,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
INTERRUPT : out STD_LOGIC;
- initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ initialValue : out STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : out STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : out STD_LOGIC_VECTOR ( 1 downto 0 );
@@ -181,7 +181,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
- initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ initialValue : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
@@ -252,7 +252,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_dma_0_finalXOR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_inOutReflected : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axis_dma_0_initial_value : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axis_dma_0_initialValue : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC;
@@ -336,7 +336,7 @@ axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0
S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
- initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
+ initialValue(31 downto 0) => axis_dma_0_initialValue(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
@@ -407,7 +407,7 @@ axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
- initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
+ initialValue(31 downto 0) => axis_dma_0_initialValue(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_fifo_0: component axi_crc_dma_sim_1_axis_fifo_0_0
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd
index ab723dd..56b6031 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
---Date : Tue Feb 11 20:14:47 2025
+--Date : Wed Feb 12 11:55:39 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_sim_1.bd
--Design : axi_crc_dma_sim_1
@@ -110,7 +110,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
INTERRUPT : out STD_LOGIC;
- initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ initialValue : out STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : out STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : out STD_LOGIC_VECTOR ( 1 downto 0 );
@@ -181,7 +181,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
- initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ initialValue : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
@@ -252,7 +252,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_dma_0_finalXOR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_inOutReflected : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axis_dma_0_initial_value : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axis_dma_0_initialValue : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC;
@@ -336,7 +336,7 @@ axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0
S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
- initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
+ initialValue(31 downto 0) => axis_dma_0_initialValue(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
@@ -407,7 +407,7 @@ axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
- initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
+ initialValue(31 downto 0) => axis_dma_0_initialValue(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_fifo_0: component axi_crc_dma_sim_1_axis_fifo_0_0
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml
index ea3d8dd..cd6acb6 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml
@@ -2,55 +2,10 @@
Composite Fileset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1_ooc.xdc b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1_ooc.xdc
deleted file mode 100644
index 5ee9a4d..0000000
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1_ooc.xdc
+++ /dev/null
@@ -1,14 +0,0 @@
-################################################################################
-
-# This XDC is used only for OOC mode of synthesis, implementation
-# This constraints file contains default clock frequencies to be used during
-# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
-# This constraints file is not used in normal top-down synthesis (default flow
-# of Vivado)
-################################################################################
-create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 10 [get_pins PS/processing_system7_0/FCLK_CLK0]
-create_clock -name PS_processing_system7_0_FCLK_CLK1 -period 8 [get_pins PS/processing_system7_0/FCLK_CLK1]
-create_clock -name PS_processing_system7_0_FCLK_CLK2 -period 5 [get_pins PS/processing_system7_0/FCLK_CLK2]
-create_clock -name PS_processing_system7_0_FCLK_CLK3 -period 15 [get_pins PS/processing_system7_0/FCLK_CLK3]
-
-################################################################################
\ No newline at end of file
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/hdl/axi_crc_dma_syn_1_wrapper.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/hdl/axi_crc_dma_syn_1_wrapper.vhd
index 7a30f7c..a3ce277 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/hdl/axi_crc_dma_syn_1_wrapper.vhd
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/hdl/axi_crc_dma_syn_1_wrapper.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
---Date : Tue Feb 11 19:46:02 2025
+--Date : Tue Feb 11 21:11:13 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_syn_1_wrapper.bd
--Design : axi_crc_dma_syn_1_wrapper
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml
index ea7f801..865be98 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml
@@ -1500,7 +1500,7 @@
GENtimestamp
- Tue Feb 11 18:46:10 UTC 2025
+ Tue Feb 11 20:11:27 UTC 2025
outputProductCRC
@@ -1518,7 +1518,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:26 UTC 2025
outputProductCRC
@@ -1538,7 +1538,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:26 UTC 2025
outputProductCRC
@@ -1566,7 +1566,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:26 UTC 2025
outputProductCRC
@@ -1605,7 +1605,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:24 UTC 2025
outputProductCRC
@@ -1625,7 +1625,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:26 UTC 2025
outputProductCRC
@@ -1663,7 +1663,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:26 UTC 2025
outputProductCRC
@@ -1683,7 +1683,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:26 UTC 2025
outputProductCRC
@@ -1701,7 +1701,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1714,7 +1714,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1731,7 +1731,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1758,7 +1758,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1785,7 +1785,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1812,7 +1812,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1839,7 +1839,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1866,7 +1866,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1893,7 +1893,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1920,7 +1920,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1947,7 +1947,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1974,7 +1974,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2001,7 +2001,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2024,7 +2024,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2047,7 +2047,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2071,7 +2071,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2098,7 +2098,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2125,7 +2125,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2148,7 +2148,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2175,7 +2175,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2198,7 +2198,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2221,7 +2221,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2245,7 +2245,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2269,7 +2269,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2293,7 +2293,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2313,7 +2313,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2333,7 +2333,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2360,7 +2360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2387,7 +2387,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2414,7 +2414,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2441,7 +2441,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2468,7 +2468,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2495,7 +2495,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2522,7 +2522,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2549,7 +2549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2576,7 +2576,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2603,7 +2603,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2630,7 +2630,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2653,7 +2653,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2676,7 +2676,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2700,7 +2700,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2724,7 +2724,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2748,7 +2748,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2768,7 +2768,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2792,7 +2792,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2812,7 +2812,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2832,7 +2832,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2859,7 +2859,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2883,7 +2883,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2907,7 +2907,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2931,7 +2931,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2955,7 +2955,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2979,7 +2979,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3003,7 +3003,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3027,7 +3027,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3051,7 +3051,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3075,7 +3075,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3099,7 +3099,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3119,7 +3119,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3139,7 +3139,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3166,7 +3166,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3190,7 +3190,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3214,7 +3214,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3234,7 +3234,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3258,7 +3258,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3278,7 +3278,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3298,7 +3298,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3325,7 +3325,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3352,7 +3352,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3379,7 +3379,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3402,7 +3402,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3425,7 +3425,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3449,7 +3449,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3473,7 +3473,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3497,7 +3497,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3521,7 +3521,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3545,7 +3545,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3569,7 +3569,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3593,7 +3593,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3617,7 +3617,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3641,7 +3641,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3665,7 +3665,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3689,7 +3689,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3709,7 +3709,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3729,7 +3729,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3756,7 +3756,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3783,7 +3783,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3810,7 +3810,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3833,7 +3833,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3860,7 +3860,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3883,7 +3883,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3906,7 +3906,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -4552,67 +4552,68 @@
-
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
-
-
-
-
+
+
+
+
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
-
+
-
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml
index 6178221..f161e69 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml
@@ -1511,7 +1511,7 @@
GENtimestamp
- Tue Feb 11 18:46:10 UTC 2025
+ Tue Feb 11 20:11:27 UTC 2025
outputProductCRC
@@ -1530,7 +1530,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1548,7 +1548,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1568,7 +1568,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1596,7 +1596,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1644,7 +1644,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1664,7 +1664,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1708,7 +1708,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1728,7 +1728,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1746,7 +1746,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1762,7 +1762,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1782,7 +1782,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1809,7 +1809,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1836,7 +1836,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1863,7 +1863,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1890,7 +1890,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1917,7 +1917,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1944,7 +1944,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1971,7 +1971,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1998,7 +1998,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2025,7 +2025,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2048,7 +2048,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2071,7 +2071,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2095,7 +2095,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2122,7 +2122,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2145,7 +2145,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2168,7 +2168,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2191,7 +2191,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2215,7 +2215,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2239,7 +2239,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2259,7 +2259,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2279,7 +2279,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2306,7 +2306,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2333,7 +2333,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2360,7 +2360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2387,7 +2387,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2414,7 +2414,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2441,7 +2441,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2468,7 +2468,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2495,7 +2495,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2522,7 +2522,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2549,7 +2549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2572,7 +2572,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2595,7 +2595,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2619,7 +2619,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2643,7 +2643,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2667,7 +2667,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2687,7 +2687,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2707,7 +2707,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2727,7 +2727,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2750,7 +2750,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2773,7 +2773,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2800,7 +2800,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2824,7 +2824,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2848,7 +2848,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2872,7 +2872,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2896,7 +2896,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2920,7 +2920,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2944,7 +2944,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2968,7 +2968,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2992,7 +2992,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3012,7 +3012,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3032,7 +3032,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3059,7 +3059,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3083,7 +3083,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3103,7 +3103,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3123,7 +3123,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3143,7 +3143,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3170,7 +3170,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3193,7 +3193,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3216,7 +3216,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3240,7 +3240,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3264,7 +3264,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3288,7 +3288,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3312,7 +3312,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3336,7 +3336,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3360,7 +3360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3384,7 +3384,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3408,7 +3408,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3432,7 +3432,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3452,7 +3452,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3472,7 +3472,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3499,7 +3499,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3526,7 +3526,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3549,7 +3549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3572,7 +3572,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3595,7 +3595,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -4387,7 +4387,7 @@
-
+
@@ -4396,7 +4396,7 @@
-
+
@@ -4420,31 +4420,32 @@
-
+
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/axi_crc_dma_syn_1_auto_us_1.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/axi_crc_dma_syn_1_auto_us_1.xml
index 764c079..727fb2d 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/axi_crc_dma_syn_1_auto_us_1.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/axi_crc_dma_syn_1_auto_us_1.xml
@@ -1511,7 +1511,7 @@
GENtimestamp
- Tue Feb 11 18:46:10 UTC 2025
+ Tue Feb 11 20:11:27 UTC 2025
outputProductCRC
@@ -1530,7 +1530,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1548,7 +1548,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1568,7 +1568,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1596,7 +1596,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1644,7 +1644,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1664,7 +1664,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1708,7 +1708,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1728,7 +1728,7 @@
GENtimestamp
- Tue Feb 11 18:46:09 UTC 2025
+ Tue Feb 11 20:11:25 UTC 2025
outputProductCRC
@@ -1746,7 +1746,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1762,7 +1762,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1782,7 +1782,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1809,7 +1809,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1836,7 +1836,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1863,7 +1863,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1890,7 +1890,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1917,7 +1917,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1944,7 +1944,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1971,7 +1971,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1998,7 +1998,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2025,7 +2025,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2048,7 +2048,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2071,7 +2071,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2095,7 +2095,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2122,7 +2122,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2145,7 +2145,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2168,7 +2168,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2191,7 +2191,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2215,7 +2215,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2239,7 +2239,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2259,7 +2259,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2279,7 +2279,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2306,7 +2306,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2333,7 +2333,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2360,7 +2360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2387,7 +2387,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2414,7 +2414,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2441,7 +2441,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2468,7 +2468,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2495,7 +2495,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2522,7 +2522,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2549,7 +2549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2572,7 +2572,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2595,7 +2595,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2619,7 +2619,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2643,7 +2643,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2667,7 +2667,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2687,7 +2687,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2707,7 +2707,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2727,7 +2727,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2750,7 +2750,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2773,7 +2773,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2800,7 +2800,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2824,7 +2824,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2848,7 +2848,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2872,7 +2872,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2896,7 +2896,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2920,7 +2920,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2944,7 +2944,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2968,7 +2968,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2992,7 +2992,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3012,7 +3012,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3032,7 +3032,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3059,7 +3059,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3083,7 +3083,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3103,7 +3103,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3123,7 +3123,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3143,7 +3143,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3170,7 +3170,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3193,7 +3193,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3216,7 +3216,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3240,7 +3240,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3264,7 +3264,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3288,7 +3288,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3312,7 +3312,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3336,7 +3336,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3360,7 +3360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3384,7 +3384,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3408,7 +3408,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3432,7 +3432,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3452,7 +3452,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3472,7 +3472,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3499,7 +3499,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3526,7 +3526,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3549,7 +3549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3572,7 +3572,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3595,7 +3595,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -4387,7 +4387,7 @@
-
+
@@ -4396,7 +4396,7 @@
-
+
@@ -4420,31 +4420,32 @@
-
+
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0.xml
index b4dae52..d4e1e68 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0.xml
@@ -119,7 +119,7 @@
FREQ_HZ
- 1e+08
+ 100000000
none
@@ -137,7 +137,7 @@
CLK_DOMAIN
- axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0
+
none
@@ -278,7 +278,7 @@
FREQ_HZ
- 1e+08
+ 100000000
none
@@ -296,7 +296,7 @@
CLK_DOMAIN
- axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0
+
none
@@ -380,7 +380,7 @@
FREQ_HZ
- 1e+08
+ 100000000
none
@@ -407,7 +407,7 @@
CLK_DOMAIN
- axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0
+
none
@@ -436,101 +436,6 @@
-
-
- xilinx_anylanguagebehavioralsimulation
- Simulation
- :vivado.xilinx.com:simulation
- axis_crc
-
-
- outputProductCRC
- 9:15667cfd
-
-
-
-
- xilinx_anylanguagesynthesis
- Synthesis
- :vivado.xilinx.com:synthesis
- axis_crc
-
-
- outputProductCRC
- 9:67c4611f
-
-
-
-
- xilinx_externalfiles
- External Files
- :vivado.xilinx.com:external.files
-
- xilinx_externalfiles_view_fileset
-
-
-
- GENtimestamp
- Tue Feb 11 18:47:38 UTC 2025
-
-
- outputProductCRC
- 9:67c4611f
-
-
-
-
- xilinx_synthesisconstraints
- Synthesis Constraints
- :vivado.xilinx.com:synthesis.constraints
-
-
- outputProductCRC
- 9:67c4611f
-
-
-
-
- xilinx_vhdlsimulationwrapper
- VHDL Simulation Wrapper
- vhdlSource:vivado.xilinx.com:simulation.wrapper
- vhdl
- axi_crc_dma_syn_1_axis_crc_0_0
-
- xilinx_vhdlsimulationwrapper_view_fileset
-
-
-
- GENtimestamp
- Tue Feb 11 18:46:03 UTC 2025
-
-
- outputProductCRC
- 9:15667cfd
-
-
-
-
- xilinx_vhdlsynthesiswrapper
- VHDL Synthesis Wrapper
- vhdlSource:vivado.xilinx.com:synthesis.wrapper
- vhdl
- axi_crc_dma_syn_1_axis_crc_0_0
-
- xilinx_vhdlsynthesiswrapper_view_fileset
-
-
-
- GENtimestamp
- Tue Feb 11 18:46:03 UTC 2025
-
-
- outputProductCRC
- 9:67c4611f
-
-
-
-
CLK
@@ -539,8 +444,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -552,14 +456,13 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
- initial_value
+ initialValue
in
@@ -569,8 +472,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -586,8 +488,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -603,8 +504,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -620,8 +520,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -633,8 +532,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -650,8 +548,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -666,8 +563,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -682,8 +578,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -695,8 +590,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -712,8 +606,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -725,8 +618,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -738,8 +630,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -756,60 +647,6 @@
ACTIVE_LOW
-
-
- xilinx_externalfiles_view_fileset
-
- axi_crc_dma_syn_1_axis_crc_0_0.dcp
- dcp
- USED_IN_implementation
- USED_IN_synthesis
- xil_defaultlib
-
-
- axi_crc_dma_syn_1_axis_crc_0_0_stub.v
- verilogSource
- USED_IN_synth_blackbox_stub
- xil_defaultlib
-
-
- axi_crc_dma_syn_1_axis_crc_0_0_stub.vhdl
- vhdlSource
- USED_IN_synth_blackbox_stub
- xil_defaultlib
-
-
- axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.v
- verilogSource
- USED_IN_simulation
- USED_IN_single_language
- xil_defaultlib
-
-
- axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.vhdl
- vhdlSource
- USED_IN_simulation
- USED_IN_single_language
- xil_defaultlib
-
-
-
- xilinx_vhdlsimulationwrapper_view_fileset
-
- sim/axi_crc_dma_syn_1_axis_crc_0_0.vhd
- vhdlSource
- xil_defaultlib
-
-
-
- xilinx_vhdlsynthesiswrapper_view_fileset
-
- synth/axi_crc_dma_syn_1_axis_crc_0_0.vhd
- vhdlSource
- xil_defaultlib
-
-
-
xilinx.com:module_ref:axis_crc:1.0
@@ -826,12 +663,12 @@
-
-
+
+
-
-
+
+
@@ -843,8 +680,8 @@
-
-
+
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.v
deleted file mode 100644
index a989172..0000000
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.v
+++ /dev/null
@@ -1,7543 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-// Date : Tue Feb 11 19:47:38 2025
-// Host : BiermannSurface running 64-bit major release (build 9200)
-// Command : write_verilog -force -mode funcsim
-// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.v
-// Design : axi_crc_dma_syn_1_axis_crc_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z020clg400-1
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "axi_crc_dma_syn_1_axis_crc_0_0,axis_crc,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *)
-(* x_core_info = "axis_crc,Vivado 2023.1" *)
-(* NotValidForBitStream *)
-module axi_crc_dma_syn_1_axis_crc_0_0
- (CLK,
- RESETN,
- initial_value,
- polynomial,
- finalXOR,
- inOutReflected,
- S_AXIS_TVALID,
- S_AXIS_TDATA,
- S_AXIS_TLAST,
- S_AXIS_TREADY,
- M_AXIS_TVALID,
- M_AXIS_TDATA,
- M_AXIS_TLAST,
- M_AXIS_TREADY);
- (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input CLK;
- (* x_interface_info = "xilinx.com:signal:reset:1.0 RESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input RESETN;
- input [31:0]initial_value;
- input [31:0]polynomial;
- input [31:0]finalXOR;
- input [1:0]inOutReflected;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [31:0]S_AXIS_TDATA;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input S_AXIS_TLAST;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [31:0]M_AXIS_TDATA;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) output M_AXIS_TLAST;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
-
- wire CLK;
- wire [31:0]M_AXIS_TDATA;
- wire M_AXIS_TLAST;
- wire M_AXIS_TREADY;
- wire M_AXIS_TVALID;
- wire RESETN;
- wire [31:0]S_AXIS_TDATA;
- wire S_AXIS_TLAST;
- wire S_AXIS_TREADY;
- wire S_AXIS_TVALID;
- wire [31:0]finalXOR;
- wire [31:0]initial_value;
- wire [31:0]polynomial;
-
- axi_crc_dma_syn_1_axis_crc_0_0_axis_crc U0
- (.CLK(CLK),
- .M_AXIS_TDATA(M_AXIS_TDATA),
- .M_AXIS_TLAST(M_AXIS_TLAST),
- .M_AXIS_TREADY(M_AXIS_TREADY),
- .M_AXIS_TVALID(M_AXIS_TVALID),
- .RESETN(RESETN),
- .S_AXIS_TDATA(S_AXIS_TDATA),
- .S_AXIS_TLAST(S_AXIS_TLAST),
- .S_AXIS_TREADY(S_AXIS_TREADY),
- .S_AXIS_TVALID(S_AXIS_TVALID),
- .finalXOR(finalXOR),
- .initial_value(initial_value),
- .polynomial(polynomial));
-endmodule
-
-(* ORIG_REF_NAME = "axis_crc" *)
-module axi_crc_dma_syn_1_axis_crc_0_0_axis_crc
- (M_AXIS_TDATA,
- S_AXIS_TREADY,
- M_AXIS_TVALID,
- M_AXIS_TLAST,
- finalXOR,
- M_AXIS_TREADY,
- S_AXIS_TVALID,
- CLK,
- S_AXIS_TDATA,
- polynomial,
- RESETN,
- initial_value,
- S_AXIS_TLAST);
- output [31:0]M_AXIS_TDATA;
- output S_AXIS_TREADY;
- output M_AXIS_TVALID;
- output M_AXIS_TLAST;
- input [31:0]finalXOR;
- input M_AXIS_TREADY;
- input S_AXIS_TVALID;
- input CLK;
- input [31:0]S_AXIS_TDATA;
- input [31:0]polynomial;
- input RESETN;
- input [31:0]initial_value;
- input S_AXIS_TLAST;
-
- wire CLK;
- wire [1:0]CRC064_out;
- wire [31:2]CRC63_in;
- wire \CRC[0]_i_2_n_0 ;
- wire \CRC[0]_i_4_n_0 ;
- wire \CRC[10]_i_13_n_0 ;
- wire \CRC[10]_i_3_n_0 ;
- wire \CRC[10]_i_4_n_0 ;
- wire \CRC[11]_i_3_n_0 ;
- wire \CRC[11]_i_4_n_0 ;
- wire \CRC[12]_i_14_n_0 ;
- wire \CRC[12]_i_3_n_0 ;
- wire \CRC[12]_i_4_n_0 ;
- wire \CRC[13]_i_3_n_0 ;
- wire \CRC[13]_i_4_n_0 ;
- wire \CRC[14]_i_3_n_0 ;
- wire \CRC[14]_i_4_n_0 ;
- wire \CRC[15]_i_3_n_0 ;
- wire \CRC[15]_i_4_n_0 ;
- wire \CRC[16]_i_3_n_0 ;
- wire \CRC[16]_i_4_n_0 ;
- wire \CRC[17]_i_3_n_0 ;
- wire \CRC[17]_i_4_n_0 ;
- wire \CRC[18]_i_3_n_0 ;
- wire \CRC[18]_i_4_n_0 ;
- wire \CRC[19]_i_3_n_0 ;
- wire \CRC[19]_i_4_n_0 ;
- wire \CRC[1]_i_3_n_0 ;
- wire \CRC[1]_i_4_n_0 ;
- wire \CRC[1]_i_5_n_0 ;
- wire \CRC[20]_i_3_n_0 ;
- wire \CRC[20]_i_4_n_0 ;
- wire \CRC[21]_i_3_n_0 ;
- wire \CRC[21]_i_4_n_0 ;
- wire \CRC[22]_i_3_n_0 ;
- wire \CRC[22]_i_4_n_0 ;
- wire \CRC[23]_i_3_n_0 ;
- wire \CRC[23]_i_4_n_0 ;
- wire \CRC[24]_i_3_n_0 ;
- wire \CRC[24]_i_4_n_0 ;
- wire \CRC[25]_i_3_n_0 ;
- wire \CRC[25]_i_4_n_0 ;
- wire \CRC[26]_i_3_n_0 ;
- wire \CRC[26]_i_4_n_0 ;
- wire \CRC[27]_i_3_n_0 ;
- wire \CRC[27]_i_4_n_0 ;
- wire \CRC[28]_i_3_n_0 ;
- wire \CRC[28]_i_4_n_0 ;
- wire \CRC[29]_i_4_n_0 ;
- wire \CRC[29]_i_5_n_0 ;
- wire \CRC[2]_i_3_n_0 ;
- wire \CRC[2]_i_4_n_0 ;
- wire \CRC[2]_i_5_n_0 ;
- wire \CRC[30]_i_2_n_0 ;
- wire \CRC[30]_i_4_n_0 ;
- wire \CRC[30]_i_5_n_0 ;
- wire \CRC[30]_i_6_n_0 ;
- wire \CRC[31]_i_14_n_0 ;
- wire \CRC[31]_i_15_n_0 ;
- wire \CRC[31]_i_1_n_0 ;
- wire \CRC[31]_i_3_n_0 ;
- wire \CRC[31]_i_4_n_0 ;
- wire \CRC[31]_i_6_n_0 ;
- wire \CRC[31]_i_7_n_0 ;
- wire \CRC[31]_i_8_n_0 ;
- wire \CRC[31]_i_98_n_0 ;
- wire \CRC[3]_i_3_n_0 ;
- wire \CRC[3]_i_4_n_0 ;
- wire \CRC[4]_i_3_n_0 ;
- wire \CRC[4]_i_4_n_0 ;
- wire \CRC[4]_i_7_n_0 ;
- wire \CRC[5]_i_3_n_0 ;
- wire \CRC[5]_i_4_n_0 ;
- wire \CRC[6]_i_3_n_0 ;
- wire \CRC[6]_i_4_n_0 ;
- wire \CRC[6]_i_9_n_0 ;
- wire \CRC[7]_i_11_n_0 ;
- wire \CRC[7]_i_3_n_0 ;
- wire \CRC[7]_i_4_n_0 ;
- wire \CRC[8]_i_11_n_0 ;
- wire \CRC[8]_i_3_n_0 ;
- wire \CRC[8]_i_4_n_0 ;
- wire \CRC[9]_i_3_n_0 ;
- wire \CRC[9]_i_4_n_0 ;
- wire [31:31]CRC__0__0;
- wire [31:31]CRC__10__0;
- wire [31:31]CRC__11__0;
- wire [31:31]CRC__12__0;
- wire [31:31]CRC__13__0;
- wire [31:31]CRC__14__0;
- wire [31:31]CRC__15__0;
- wire [31:31]CRC__16__0;
- wire [31:31]CRC__17__0;
- wire [31:31]CRC__18__0;
- wire [31:31]CRC__1__0;
- wire [31:31]CRC__20__0;
- wire [31:31]CRC__21__0;
- wire [31:31]CRC__22__0;
- wire [31:31]CRC__23__0;
- wire [31:31]CRC__24__0;
- wire [31:31]CRC__25__0;
- wire [31:31]CRC__26__0;
- wire [31:31]CRC__27__0;
- wire [31:0]CRC__28;
- wire [31:31]CRC__2__0;
- wire [31:31]CRC__31;
- wire [31:31]CRC__3__0;
- wire [31:31]CRC__4__0;
- wire [31:31]CRC__5__0;
- wire [31:31]CRC__6__0;
- wire [31:31]CRC__7__0;
- wire [31:31]CRC__8__0;
- wire [31:31]CRC__9__0;
- wire \CRC_reg_n_0_[0] ;
- wire \CRC_reg_n_0_[10] ;
- wire \CRC_reg_n_0_[11] ;
- wire \CRC_reg_n_0_[12] ;
- wire \CRC_reg_n_0_[13] ;
- wire \CRC_reg_n_0_[14] ;
- wire \CRC_reg_n_0_[15] ;
- wire \CRC_reg_n_0_[16] ;
- wire \CRC_reg_n_0_[17] ;
- wire \CRC_reg_n_0_[18] ;
- wire \CRC_reg_n_0_[19] ;
- wire \CRC_reg_n_0_[1] ;
- wire \CRC_reg_n_0_[20] ;
- wire \CRC_reg_n_0_[21] ;
- wire \CRC_reg_n_0_[22] ;
- wire \CRC_reg_n_0_[23] ;
- wire \CRC_reg_n_0_[24] ;
- wire \CRC_reg_n_0_[25] ;
- wire \CRC_reg_n_0_[26] ;
- wire \CRC_reg_n_0_[27] ;
- wire \CRC_reg_n_0_[28] ;
- wire \CRC_reg_n_0_[29] ;
- wire \CRC_reg_n_0_[2] ;
- wire \CRC_reg_n_0_[30] ;
- wire \CRC_reg_n_0_[31] ;
- wire \CRC_reg_n_0_[3] ;
- wire \CRC_reg_n_0_[4] ;
- wire \CRC_reg_n_0_[5] ;
- wire \CRC_reg_n_0_[6] ;
- wire \CRC_reg_n_0_[7] ;
- wire \CRC_reg_n_0_[8] ;
- wire \CRC_reg_n_0_[9] ;
- wire \FSM_sequential_state[0]_i_1_n_0 ;
- wire \FSM_sequential_state[1]_i_1_n_0 ;
- wire [31:0]M_AXIS_TDATA;
- wire [31:0]M_AXIS_TDATA0_in;
- wire \M_AXIS_TDATA[0]_i_10_n_0 ;
- wire \M_AXIS_TDATA[31]_i_1_n_0 ;
- wire M_AXIS_TLAST;
- wire M_AXIS_TLAST_i_1_n_0;
- wire M_AXIS_TREADY;
- wire M_AXIS_TVALID;
- wire M_AXIS_TVALID_i_1_n_0;
- wire RESETN;
- wire [31:0]S_AXIS_TDATA;
- wire S_AXIS_TLAST;
- wire S_AXIS_TREADY;
- wire S_AXIS_TREADY_i_1_n_0;
- wire S_AXIS_TREADY_i_2_n_0;
- wire S_AXIS_TVALID;
- wire [7:0]byte_0__0;
- wire [31:0]finalXOR;
- wire firstWord_i_1_n_0;
- wire firstWord_reg_n_0;
- wire [31:0]initial_value;
- wire last3_out;
- wire last_reg_n_0;
- wire [30:2]p_0_in0_in;
- wire [30:26]p_0_in10_in;
- wire [29:1]p_0_in14_in;
- wire [30:29]p_0_in16_in;
- wire [31:1]p_0_in18_in;
- wire [30:27]p_0_in20_in;
- wire [31:1]p_0_in22_in;
- wire [30:25]p_0_in24_in;
- wire [31:1]p_0_in26_in;
- wire [30:23]p_0_in28_in;
- wire [30:3]p_0_in2_in;
- wire [31:1]p_0_in30_in;
- wire [30:21]p_0_in32_in;
- wire [31:1]p_0_in34_in;
- wire [30:19]p_0_in36_in;
- wire [31:1]p_0_in38_in;
- wire [30:17]p_0_in40_in;
- wire [31:1]p_0_in42_in;
- wire [31:2]p_0_in46_in;
- wire [30:3]p_0_in4_in;
- wire [30:2]p_0_in50_in;
- wire [30:3]p_0_in52_in;
- wire [31:3]p_0_in54_in;
- wire [31:2]p_0_in58_in;
- wire [31:24]p_0_in62_in;
- wire [31:16]p_0_in65_in;
- wire [30:28]p_0_in6_in;
- wire [30:2]p_0_in8_in;
- wire [31:0]polynomial;
- wire [1:0]state;
-
- LUT6 #(
- .INIT(64'hFFFFFFFFFF808080))
- \CRC[0]_i_1
- (.I0(polynomial[0]),
- .I1(\CRC[31]_i_3_n_0 ),
- .I2(CRC__20__0),
- .I3(\CRC[0]_i_2_n_0 ),
- .I4(CRC064_out[0]),
- .I5(\CRC[0]_i_4_n_0 ),
- .O(CRC__28[0]));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT2 #(
- .INIT(4'h8))
- \CRC[0]_i_2
- (.I0(last_reg_n_0),
- .I1(state[1]),
- .O(\CRC[0]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT3 #(
- .INIT(8'h6A))
- \CRC[0]_i_3
- (.I0(finalXOR[0]),
- .I1(polynomial[0]),
- .I2(CRC__27__0),
- .O(CRC064_out[0]));
- LUT6 #(
- .INIT(64'h220022000000F000))
- \CRC[0]_i_4
- (.I0(CRC__27__0),
- .I1(last_reg_n_0),
- .I2(CRC__5__0),
- .I3(polynomial[0]),
- .I4(state[0]),
- .I5(state[1]),
- .O(\CRC[0]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[10]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[10]),
- .I2(polynomial[10]),
- .I3(CRC__20__0),
- .I4(\CRC[10]_i_3_n_0 ),
- .I5(\CRC[10]_i_4_n_0 ),
- .O(CRC__28[10]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[10]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[5]),
- .I2(p_0_in58_in[4]),
- .I3(polynomial[4]),
- .I4(CRC__31),
- .O(p_0_in54_in[6]));
- LUT6 #(
- .INIT(64'h96FF6900C300C300))
- \CRC[10]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in36_in[30]),
- .I2(\CRC[10]_i_13_n_0 ),
- .I3(polynomial[1]),
- .I4(polynomial[0]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[2]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[10]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[3]),
- .I2(\CRC_reg_n_0_[2] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[2]),
- .O(p_0_in58_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT5 #(
- .INIT(32'h6999FFFF))
- \CRC[10]_i_13
- (.I0(CRC__7__0),
- .I1(p_0_in40_in[30]),
- .I2(CRC__8__0),
- .I3(polynomial[31]),
- .I4(polynomial[30]),
- .O(\CRC[10]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[10]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[9]),
- .I3(p_0_in18_in[8]),
- .I4(polynomial[8]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[10]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[10]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[10]),
- .I3(finalXOR[10]),
- .O(\CRC[10]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[10]_i_4
- (.I0(CRC63_in[10]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[10]),
- .I5(p_0_in46_in[10]),
- .O(\CRC[10]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[10]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[7]),
- .I3(p_0_in22_in[6]),
- .I4(polynomial[6]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[8]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[10]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[9]),
- .I2(p_0_in50_in[8]),
- .I3(polynomial[8]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[10]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[10]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[5]),
- .I3(p_0_in26_in[4]),
- .I4(polynomial[4]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[6]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[10]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[7]),
- .I2(p_0_in54_in[6]),
- .I3(polynomial[6]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[8]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[10]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[3]),
- .I3(p_0_in30_in[2]),
- .I4(polynomial[2]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[4]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[11]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[11]),
- .I2(polynomial[11]),
- .I3(CRC__20__0),
- .I4(\CRC[11]_i_3_n_0 ),
- .I5(\CRC[11]_i_4_n_0 ),
- .O(CRC__28[11]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[11]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[6]),
- .I2(p_0_in58_in[5]),
- .I3(polynomial[5]),
- .I4(CRC__31),
- .O(p_0_in54_in[7]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[11]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[2]),
- .I3(p_0_in34_in[1]),
- .I4(polynomial[1]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[3]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[11]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[4]),
- .I2(\CRC_reg_n_0_[3] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[3]),
- .O(p_0_in58_in[5]));
- LUT6 #(
- .INIT(64'h8778787800000000))
- \CRC[11]_i_13
- (.I0(polynomial[30]),
- .I1(CRC__7__0),
- .I2(p_0_in40_in[30]),
- .I3(CRC__8__0),
- .I4(polynomial[31]),
- .I5(polynomial[0]),
- .O(p_0_in34_in[1]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[11]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[10]),
- .I3(p_0_in18_in[9]),
- .I4(polynomial[9]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[11]));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[11]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[11]),
- .I3(finalXOR[11]),
- .O(\CRC[11]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[11]_i_4
- (.I0(CRC63_in[11]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[11]),
- .I5(p_0_in46_in[11]),
- .O(\CRC[11]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[11]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[8]),
- .I3(p_0_in22_in[7]),
- .I4(polynomial[7]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[9]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[11]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[10]),
- .I2(p_0_in50_in[9]),
- .I3(polynomial[9]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[11]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[11]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[6]),
- .I3(p_0_in26_in[5]),
- .I4(polynomial[5]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[7]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[11]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[8]),
- .I2(p_0_in54_in[7]),
- .I3(polynomial[7]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[9]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[11]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[4]),
- .I3(p_0_in30_in[3]),
- .I4(polynomial[3]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[5]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[12]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[12]),
- .I2(polynomial[12]),
- .I3(CRC__20__0),
- .I4(\CRC[12]_i_3_n_0 ),
- .I5(\CRC[12]_i_4_n_0 ),
- .O(CRC__28[12]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[12]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[7]),
- .I2(p_0_in58_in[6]),
- .I3(polynomial[6]),
- .I4(CRC__31),
- .O(p_0_in54_in[8]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[12]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[3]),
- .I3(p_0_in34_in[2]),
- .I4(polynomial[2]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[4]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[12]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[5]),
- .I2(\CRC_reg_n_0_[4] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[4]),
- .O(p_0_in58_in[6]));
- LUT6 #(
- .INIT(64'h96FF6900C300C300))
- \CRC[12]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in40_in[30]),
- .I2(\CRC[12]_i_14_n_0 ),
- .I3(polynomial[1]),
- .I4(polynomial[0]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[2]));
- LUT6 #(
- .INIT(64'h96696969FFFFFFFF))
- \CRC[12]_i_14
- (.I0(\CRC[31]_i_98_n_0 ),
- .I1(\CRC_reg_n_0_[29] ),
- .I2(p_0_in65_in[29]),
- .I3(CRC__6__0),
- .I4(polynomial[31]),
- .I5(polynomial[30]),
- .O(\CRC[12]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[12]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[11]),
- .I3(p_0_in18_in[10]),
- .I4(polynomial[10]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[12]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[12]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[12]),
- .I3(finalXOR[12]),
- .O(\CRC[12]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[12]_i_4
- (.I0(CRC63_in[12]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[12]),
- .I5(p_0_in46_in[12]),
- .O(\CRC[12]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[12]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[9]),
- .I3(p_0_in22_in[8]),
- .I4(polynomial[8]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[10]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[12]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[11]),
- .I2(p_0_in50_in[10]),
- .I3(polynomial[10]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[12]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[12]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[7]),
- .I3(p_0_in26_in[6]),
- .I4(polynomial[6]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[8]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[12]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[9]),
- .I2(p_0_in54_in[8]),
- .I3(polynomial[8]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[10]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[12]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[5]),
- .I3(p_0_in30_in[4]),
- .I4(polynomial[4]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[6]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[13]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[13]),
- .I2(polynomial[13]),
- .I3(CRC__20__0),
- .I4(\CRC[13]_i_3_n_0 ),
- .I5(\CRC[13]_i_4_n_0 ),
- .O(CRC__28[13]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[13]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[8]),
- .I2(p_0_in58_in[7]),
- .I3(polynomial[7]),
- .I4(CRC__31),
- .O(p_0_in54_in[9]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[13]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[4]),
- .I3(p_0_in34_in[3]),
- .I4(polynomial[3]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[5]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[13]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[6]),
- .I2(\CRC_reg_n_0_[5] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[5]),
- .O(p_0_in58_in[7]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[13]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[2]),
- .I3(p_0_in38_in[1]),
- .I4(polynomial[1]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT4 #(
- .INIT(16'h6A00))
- \CRC[13]_i_14
- (.I0(p_0_in42_in[31]),
- .I1(CRC__6__0),
- .I2(polynomial[31]),
- .I3(polynomial[0]),
- .O(p_0_in38_in[1]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[13]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[12]),
- .I3(p_0_in18_in[11]),
- .I4(polynomial[11]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[13]));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[13]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[13]),
- .I3(finalXOR[13]),
- .O(\CRC[13]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[13]_i_4
- (.I0(CRC63_in[13]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[13]),
- .I5(p_0_in46_in[13]),
- .O(\CRC[13]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[13]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[10]),
- .I3(p_0_in22_in[9]),
- .I4(polynomial[9]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[11]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[13]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[12]),
- .I2(p_0_in50_in[11]),
- .I3(polynomial[11]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[13]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[13]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[8]),
- .I3(p_0_in26_in[7]),
- .I4(polynomial[7]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[9]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[13]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[10]),
- .I2(p_0_in54_in[9]),
- .I3(polynomial[9]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[11]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[13]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[6]),
- .I3(p_0_in30_in[5]),
- .I4(polynomial[5]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[7]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[14]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[14]),
- .I2(polynomial[14]),
- .I3(CRC__20__0),
- .I4(\CRC[14]_i_3_n_0 ),
- .I5(\CRC[14]_i_4_n_0 ),
- .O(CRC__28[14]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[14]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[9]),
- .I2(p_0_in58_in[8]),
- .I3(polynomial[8]),
- .I4(CRC__31),
- .O(p_0_in54_in[10]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[14]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[5]),
- .I3(p_0_in34_in[4]),
- .I4(polynomial[4]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[6]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[14]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[7]),
- .I2(\CRC_reg_n_0_[6] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[6]),
- .O(p_0_in58_in[8]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[14]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[3]),
- .I3(p_0_in38_in[2]),
- .I4(polynomial[2]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT5 #(
- .INIT(32'h9F60C0C0))
- \CRC[14]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[1]),
- .I3(polynomial[0]),
- .I4(CRC__6__0),
- .O(p_0_in38_in[2]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[14]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[13]),
- .I3(p_0_in18_in[12]),
- .I4(polynomial[12]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[14]));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[14]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[14]),
- .I3(finalXOR[14]),
- .O(\CRC[14]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[14]_i_4
- (.I0(CRC63_in[14]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[14]),
- .I5(p_0_in46_in[14]),
- .O(\CRC[14]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[14]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[11]),
- .I3(p_0_in22_in[10]),
- .I4(polynomial[10]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[12]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[14]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[13]),
- .I2(p_0_in50_in[12]),
- .I3(polynomial[12]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[14]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[14]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[9]),
- .I3(p_0_in26_in[8]),
- .I4(polynomial[8]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[10]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[14]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[11]),
- .I2(p_0_in54_in[10]),
- .I3(polynomial[10]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[12]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[14]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[7]),
- .I3(p_0_in30_in[6]),
- .I4(polynomial[6]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[8]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[15]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[15]),
- .I2(polynomial[15]),
- .I3(CRC__20__0),
- .I4(\CRC[15]_i_3_n_0 ),
- .I5(\CRC[15]_i_4_n_0 ),
- .O(CRC__28[15]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[15]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[10]),
- .I2(p_0_in58_in[9]),
- .I3(polynomial[9]),
- .I4(CRC__31),
- .O(p_0_in54_in[11]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[15]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[6]),
- .I3(p_0_in34_in[5]),
- .I4(polynomial[5]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[7]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[15]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[8]),
- .I2(\CRC_reg_n_0_[7] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[7]),
- .O(p_0_in58_in[9]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[15]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[4]),
- .I3(p_0_in38_in[3]),
- .I4(polynomial[3]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[5]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[15]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[2]),
- .I3(p_0_in42_in[1]),
- .I4(polynomial[1]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT3 #(
- .INIT(8'h60))
- \CRC[15]_i_15
- (.I0(\CRC_reg_n_0_[31] ),
- .I1(p_0_in65_in[31]),
- .I2(polynomial[0]),
- .O(p_0_in42_in[1]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[15]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[14]),
- .I3(p_0_in18_in[13]),
- .I4(polynomial[13]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[15]));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[15]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[15]),
- .I3(finalXOR[15]),
- .O(\CRC[15]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[15]_i_4
- (.I0(CRC63_in[15]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[15]),
- .I5(p_0_in46_in[15]),
- .O(\CRC[15]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[15]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[12]),
- .I3(p_0_in22_in[11]),
- .I4(polynomial[11]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[13]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[15]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[14]),
- .I2(p_0_in50_in[13]),
- .I3(polynomial[13]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[15]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[15]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[10]),
- .I3(p_0_in26_in[9]),
- .I4(polynomial[9]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[11]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[15]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[12]),
- .I2(p_0_in54_in[11]),
- .I3(polynomial[11]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[13]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[15]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[8]),
- .I3(p_0_in30_in[7]),
- .I4(polynomial[7]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[9]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[16]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[16]),
- .I2(CRC__20__0),
- .I3(polynomial[16]),
- .I4(\CRC[16]_i_3_n_0 ),
- .I5(\CRC[16]_i_4_n_0 ),
- .O(CRC__28[16]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[16]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[11]),
- .I2(p_0_in58_in[10]),
- .I3(polynomial[10]),
- .I4(CRC__31),
- .O(p_0_in54_in[12]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[16]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[7]),
- .I3(p_0_in34_in[6]),
- .I4(polynomial[6]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[8]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[16]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[9]),
- .I2(\CRC_reg_n_0_[8] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[8]),
- .O(p_0_in58_in[10]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[16]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[5]),
- .I3(p_0_in38_in[4]),
- .I4(polynomial[4]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[6]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[16]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[3]),
- .I3(p_0_in42_in[2]),
- .I4(polynomial[2]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT4 #(
- .INIT(16'hD728))
- \CRC[16]_i_15
- (.I0(polynomial[1]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[0] ),
- .O(p_0_in42_in[2]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[16]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[15]),
- .I3(p_0_in18_in[14]),
- .I4(polynomial[14]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[16]));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[16]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[16]),
- .I3(finalXOR[16]),
- .O(\CRC[16]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[16]_i_4
- (.I0(CRC63_in[16]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[16]),
- .I5(p_0_in46_in[16]),
- .O(\CRC[16]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[16]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[13]),
- .I3(p_0_in22_in[12]),
- .I4(polynomial[12]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[14]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[16]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[15]),
- .I2(p_0_in50_in[14]),
- .I3(polynomial[14]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[16]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[16]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[11]),
- .I3(p_0_in26_in[10]),
- .I4(polynomial[10]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[12]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[16]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[13]),
- .I2(p_0_in54_in[12]),
- .I3(polynomial[12]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[14]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[16]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[9]),
- .I3(p_0_in30_in[8]),
- .I4(polynomial[8]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[10]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[17]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[17]),
- .I2(CRC__20__0),
- .I3(polynomial[17]),
- .I4(\CRC[17]_i_3_n_0 ),
- .I5(\CRC[17]_i_4_n_0 ),
- .O(CRC__28[17]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[17]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[12]),
- .I2(p_0_in58_in[11]),
- .I3(polynomial[11]),
- .I4(CRC__31),
- .O(p_0_in54_in[13]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[17]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[8]),
- .I3(p_0_in34_in[7]),
- .I4(polynomial[7]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[9]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[17]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[10]),
- .I2(\CRC_reg_n_0_[9] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[9]),
- .O(p_0_in58_in[11]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[17]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[6]),
- .I3(p_0_in38_in[5]),
- .I4(polynomial[5]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[7]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[17]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[4]),
- .I3(p_0_in42_in[3]),
- .I4(polynomial[3]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[5]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[17]_i_15
- (.I0(polynomial[2]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[1] ),
- .O(p_0_in42_in[3]));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[17]_i_2
- (.I0(polynomial[16]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[15]),
- .I4(polynomial[15]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[17]));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[17]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[17]),
- .I3(finalXOR[17]),
- .O(\CRC[17]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[17]_i_4
- (.I0(CRC63_in[17]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[17]),
- .I5(p_0_in46_in[17]),
- .O(\CRC[17]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[17]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[14]),
- .I3(p_0_in22_in[13]),
- .I4(polynomial[13]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[15]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[17]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[16]),
- .I2(p_0_in50_in[15]),
- .I3(polynomial[15]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[17]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[17]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[12]),
- .I3(p_0_in26_in[11]),
- .I4(polynomial[11]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[13]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[17]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[14]),
- .I2(p_0_in54_in[13]),
- .I3(polynomial[13]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[15]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[17]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[10]),
- .I3(p_0_in30_in[9]),
- .I4(polynomial[9]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[11]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[18]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[18]),
- .I2(CRC__20__0),
- .I3(polynomial[18]),
- .I4(\CRC[18]_i_3_n_0 ),
- .I5(\CRC[18]_i_4_n_0 ),
- .O(CRC__28[18]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[18]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[13]),
- .I2(p_0_in58_in[12]),
- .I3(polynomial[12]),
- .I4(CRC__31),
- .O(p_0_in54_in[14]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[18]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[9]),
- .I3(p_0_in34_in[8]),
- .I4(polynomial[8]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[10]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[18]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[11]),
- .I2(\CRC_reg_n_0_[10] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[10]),
- .O(p_0_in58_in[12]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[18]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[7]),
- .I3(p_0_in38_in[6]),
- .I4(polynomial[6]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[8]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[18]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[5]),
- .I3(p_0_in42_in[4]),
- .I4(polynomial[4]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[6]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[18]_i_15
- (.I0(polynomial[3]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[2] ),
- .O(p_0_in42_in[4]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[18]_i_2
- (.I0(polynomial[17]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[16]),
- .I4(CRC__18__0),
- .I5(polynomial[16]),
- .O(p_0_in14_in[18]));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[18]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[18]),
- .I3(finalXOR[18]),
- .O(\CRC[18]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[18]_i_4
- (.I0(CRC63_in[18]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[18]),
- .I5(p_0_in46_in[18]),
- .O(\CRC[18]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[18]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[15]),
- .I3(p_0_in22_in[14]),
- .I4(polynomial[14]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[16]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[18]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[17]),
- .I2(p_0_in50_in[16]),
- .I3(polynomial[16]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[18]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[18]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[13]),
- .I3(p_0_in26_in[12]),
- .I4(polynomial[12]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[14]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[18]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[15]),
- .I2(p_0_in54_in[14]),
- .I3(polynomial[14]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[16]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[18]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[11]),
- .I3(p_0_in30_in[10]),
- .I4(polynomial[10]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[12]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[19]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[19]),
- .I2(CRC__20__0),
- .I3(polynomial[19]),
- .I4(\CRC[19]_i_3_n_0 ),
- .I5(\CRC[19]_i_4_n_0 ),
- .O(CRC__28[19]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[19]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[14]),
- .I2(p_0_in58_in[13]),
- .I3(polynomial[13]),
- .I4(CRC__31),
- .O(p_0_in54_in[15]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[19]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[10]),
- .I3(p_0_in34_in[9]),
- .I4(polynomial[9]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[11]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[19]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[12]),
- .I2(\CRC_reg_n_0_[11] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[11]),
- .O(p_0_in58_in[13]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[19]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[8]),
- .I3(p_0_in38_in[7]),
- .I4(polynomial[7]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[9]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[19]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[6]),
- .I3(p_0_in42_in[5]),
- .I4(polynomial[5]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[7]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[19]_i_15
- (.I0(polynomial[4]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[3] ),
- .O(p_0_in42_in[5]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[19]_i_2
- (.I0(polynomial[18]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[17]),
- .I4(CRC__18__0),
- .I5(polynomial[17]),
- .O(p_0_in14_in[19]));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[19]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[19]),
- .I3(finalXOR[19]),
- .O(\CRC[19]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[19]_i_4
- (.I0(CRC63_in[19]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[19]),
- .I5(p_0_in46_in[19]),
- .O(\CRC[19]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[19]_i_5
- (.I0(polynomial[16]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[15]),
- .I4(polynomial[15]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[17]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[19]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[18]),
- .I2(p_0_in50_in[17]),
- .I3(polynomial[17]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[19]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[19]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[14]),
- .I3(p_0_in26_in[13]),
- .I4(polynomial[13]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[15]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[19]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[16]),
- .I2(p_0_in54_in[15]),
- .I3(polynomial[15]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[17]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[19]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[12]),
- .I3(p_0_in30_in[11]),
- .I4(polynomial[11]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[13]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[1]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[1]),
- .I2(polynomial[1]),
- .I3(CRC__20__0),
- .I4(\CRC[1]_i_3_n_0 ),
- .I5(\CRC[1]_i_4_n_0 ),
- .O(CRC__28[1]));
- LUT6 #(
- .INIT(64'h8788877778777888))
- \CRC[1]_i_10
- (.I0(polynomial[27]),
- .I1(\CRC[7]_i_11_n_0 ),
- .I2(initial_value[26]),
- .I3(firstWord_reg_n_0),
- .I4(\CRC_reg_n_0_[26] ),
- .I5(S_AXIS_TDATA[2]),
- .O(p_0_in58_in[28]));
- LUT6 #(
- .INIT(64'h8788877778777888))
- \CRC[1]_i_11
- (.I0(polynomial[31]),
- .I1(\CRC[7]_i_11_n_0 ),
- .I2(initial_value[30]),
- .I3(firstWord_reg_n_0),
- .I4(\CRC_reg_n_0_[30] ),
- .I5(S_AXIS_TDATA[6]),
- .O(CRC__31));
- LUT6 #(
- .INIT(64'h8788877778777888))
- \CRC[1]_i_12
- (.I0(polynomial[29]),
- .I1(\CRC[7]_i_11_n_0 ),
- .I2(initial_value[28]),
- .I3(firstWord_reg_n_0),
- .I4(\CRC_reg_n_0_[28] ),
- .I5(S_AXIS_TDATA[4]),
- .O(p_0_in58_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[1]_i_13
- (.I0(polynomial[28]),
- .I1(CRC__0__0),
- .I2(p_0_in58_in[27]),
- .I3(CRC__31),
- .I4(polynomial[27]),
- .O(p_0_in54_in[29]));
- LUT6 #(
- .INIT(64'h8788877778777888))
- \CRC[1]_i_14
- (.I0(polynomial[26]),
- .I1(\CRC[7]_i_11_n_0 ),
- .I2(initial_value[25]),
- .I3(firstWord_reg_n_0),
- .I4(\CRC_reg_n_0_[25] ),
- .I5(S_AXIS_TDATA[1]),
- .O(p_0_in58_in[27]));
- LUT6 #(
- .INIT(64'h8778787800000000))
- \CRC[1]_i_2
- (.I0(polynomial[30]),
- .I1(CRC__17__0),
- .I2(p_0_in20_in[30]),
- .I3(CRC__18__0),
- .I4(polynomial[31]),
- .I5(polynomial[0]),
- .O(p_0_in14_in[1]));
- LUT6 #(
- .INIT(64'h802A2A2A2A808080))
- \CRC[1]_i_3
- (.I0(\CRC[0]_i_2_n_0 ),
- .I1(CRC__27__0),
- .I2(polynomial[1]),
- .I3(polynomial[0]),
- .I4(CRC__26__0),
- .I5(finalXOR[1]),
- .O(\CRC[1]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hABBBBAAABAAABAAA))
- \CRC[1]_i_4
- (.I0(\CRC[1]_i_5_n_0 ),
- .I1(\CRC[31]_i_15_n_0 ),
- .I2(CRC__5__0),
- .I3(polynomial[1]),
- .I4(polynomial[0]),
- .I5(CRC__4__0),
- .O(\CRC[1]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h0444400040004000))
- \CRC[1]_i_5
- (.I0(last_reg_n_0),
- .I1(state[1]),
- .I2(CRC__26__0),
- .I3(polynomial[0]),
- .I4(polynomial[1]),
- .I5(CRC__27__0),
- .O(\CRC[1]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h827DD728DD227788))
- \CRC[1]_i_6
- (.I0(polynomial[31]),
- .I1(p_0_in54_in[30]),
- .I2(CRC__1__0),
- .I3(p_0_in52_in[30]),
- .I4(CRC__2__0),
- .I5(polynomial[30]),
- .O(CRC__4__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[1]_i_7
- (.I0(polynomial[29]),
- .I1(CRC__0__0),
- .I2(p_0_in58_in[28]),
- .I3(CRC__31),
- .I4(polynomial[28]),
- .O(p_0_in54_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[1]_i_8
- (.I0(polynomial[31]),
- .I1(CRC__0__0),
- .I2(p_0_in58_in[30]),
- .I3(CRC__31),
- .I4(polynomial[30]),
- .O(CRC__1__0));
- LUT3 #(
- .INIT(8'h78))
- \CRC[1]_i_9
- (.I0(polynomial[29]),
- .I1(CRC__1__0),
- .I2(p_0_in54_in[29]),
- .O(p_0_in52_in[30]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[20]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[20]),
- .I2(CRC__20__0),
- .I3(polynomial[20]),
- .I4(\CRC[20]_i_3_n_0 ),
- .I5(\CRC[20]_i_4_n_0 ),
- .O(CRC__28[20]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[20]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[15]),
- .I2(p_0_in58_in[14]),
- .I3(polynomial[14]),
- .I4(CRC__31),
- .O(p_0_in54_in[16]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[20]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[11]),
- .I3(p_0_in34_in[10]),
- .I4(polynomial[10]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[12]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[20]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[13]),
- .I2(\CRC_reg_n_0_[12] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[12]),
- .O(p_0_in58_in[14]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[20]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[9]),
- .I3(p_0_in38_in[8]),
- .I4(polynomial[8]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[10]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[20]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[7]),
- .I3(p_0_in42_in[6]),
- .I4(polynomial[6]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[8]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[20]_i_15
- (.I0(polynomial[5]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[4] ),
- .O(p_0_in42_in[6]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[20]_i_2
- (.I0(polynomial[19]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[18]),
- .I4(CRC__18__0),
- .I5(polynomial[18]),
- .O(p_0_in14_in[20]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[20]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[20]),
- .I3(finalXOR[20]),
- .O(\CRC[20]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[20]_i_4
- (.I0(CRC63_in[20]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[20]),
- .I5(p_0_in46_in[20]),
- .O(\CRC[20]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[20]_i_5
- (.I0(polynomial[17]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[16]),
- .I4(CRC__16__0),
- .I5(polynomial[16]),
- .O(p_0_in18_in[18]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[20]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[19]),
- .I2(p_0_in50_in[18]),
- .I3(polynomial[18]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[20]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[20]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[15]),
- .I3(p_0_in26_in[14]),
- .I4(polynomial[14]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[16]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[20]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[17]),
- .I2(p_0_in54_in[16]),
- .I3(polynomial[16]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[18]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[20]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[13]),
- .I3(p_0_in30_in[12]),
- .I4(polynomial[12]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[14]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[21]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[21]),
- .I2(CRC__20__0),
- .I3(polynomial[21]),
- .I4(\CRC[21]_i_3_n_0 ),
- .I5(\CRC[21]_i_4_n_0 ),
- .O(CRC__28[21]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[21]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[16]),
- .I2(p_0_in58_in[15]),
- .I3(polynomial[15]),
- .I4(CRC__31),
- .O(p_0_in54_in[17]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[21]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[12]),
- .I3(p_0_in34_in[11]),
- .I4(polynomial[11]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[13]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[21]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[14]),
- .I2(\CRC_reg_n_0_[13] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[13]),
- .O(p_0_in58_in[15]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[21]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[10]),
- .I3(p_0_in38_in[9]),
- .I4(polynomial[9]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[11]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[21]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[8]),
- .I3(p_0_in42_in[7]),
- .I4(polynomial[7]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[9]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[21]_i_15
- (.I0(polynomial[6]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[5] ),
- .O(p_0_in42_in[7]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[21]_i_2
- (.I0(polynomial[20]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[19]),
- .I4(CRC__18__0),
- .I5(polynomial[19]),
- .O(p_0_in14_in[21]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[21]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[21]),
- .I3(finalXOR[21]),
- .O(\CRC[21]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[21]_i_4
- (.I0(CRC63_in[21]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[21]),
- .I5(p_0_in46_in[21]),
- .O(\CRC[21]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[21]_i_5
- (.I0(polynomial[18]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[17]),
- .I4(CRC__16__0),
- .I5(polynomial[17]),
- .O(p_0_in18_in[19]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[21]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[20]),
- .I2(p_0_in50_in[19]),
- .I3(polynomial[19]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[21]));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[21]_i_7
- (.I0(polynomial[16]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[15]),
- .I4(polynomial[15]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[17]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[21]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[18]),
- .I2(p_0_in54_in[17]),
- .I3(polynomial[17]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[19]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[21]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[14]),
- .I3(p_0_in30_in[13]),
- .I4(polynomial[13]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[15]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[22]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[22]),
- .I2(CRC__20__0),
- .I3(polynomial[22]),
- .I4(\CRC[22]_i_3_n_0 ),
- .I5(\CRC[22]_i_4_n_0 ),
- .O(CRC__28[22]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[22]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[17]),
- .I2(p_0_in58_in[16]),
- .I3(polynomial[16]),
- .I4(CRC__31),
- .O(p_0_in54_in[18]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[22]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[13]),
- .I3(p_0_in34_in[12]),
- .I4(polynomial[12]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[14]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[22]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[15]),
- .I2(\CRC_reg_n_0_[14] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[14]),
- .O(p_0_in58_in[16]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[22]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[11]),
- .I3(p_0_in38_in[10]),
- .I4(polynomial[10]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[12]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[22]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[9]),
- .I3(p_0_in42_in[8]),
- .I4(polynomial[8]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[10]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[22]_i_15
- (.I0(polynomial[7]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[6] ),
- .O(p_0_in42_in[8]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[22]_i_2
- (.I0(polynomial[21]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[20]),
- .I4(CRC__18__0),
- .I5(polynomial[20]),
- .O(p_0_in14_in[22]));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[22]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[22]),
- .I3(finalXOR[22]),
- .O(\CRC[22]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[22]_i_4
- (.I0(CRC63_in[22]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[22]),
- .I5(p_0_in46_in[22]),
- .O(\CRC[22]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[22]_i_5
- (.I0(polynomial[19]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[18]),
- .I4(CRC__16__0),
- .I5(polynomial[18]),
- .O(p_0_in18_in[20]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[22]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[21]),
- .I2(p_0_in50_in[20]),
- .I3(polynomial[20]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[22]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[22]_i_7
- (.I0(polynomial[17]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[16]),
- .I4(CRC__14__0),
- .I5(polynomial[16]),
- .O(p_0_in22_in[18]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[22]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[19]),
- .I2(p_0_in54_in[18]),
- .I3(polynomial[18]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[20]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[22]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[15]),
- .I3(p_0_in30_in[14]),
- .I4(polynomial[14]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[16]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[23]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[23]),
- .I2(CRC__20__0),
- .I3(polynomial[23]),
- .I4(\CRC[23]_i_3_n_0 ),
- .I5(\CRC[23]_i_4_n_0 ),
- .O(CRC__28[23]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[23]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[18]),
- .I2(p_0_in58_in[17]),
- .I3(polynomial[17]),
- .I4(CRC__31),
- .O(p_0_in54_in[19]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[23]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[14]),
- .I3(p_0_in34_in[13]),
- .I4(polynomial[13]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[15]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[23]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[16]),
- .I2(\CRC_reg_n_0_[15] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[15]),
- .O(p_0_in58_in[17]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[23]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[12]),
- .I3(p_0_in38_in[11]),
- .I4(polynomial[11]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[13]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[23]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[10]),
- .I3(p_0_in42_in[9]),
- .I4(polynomial[9]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[11]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[23]_i_15
- (.I0(polynomial[8]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[7] ),
- .O(p_0_in42_in[9]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[23]_i_2
- (.I0(polynomial[22]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[21]),
- .I4(CRC__18__0),
- .I5(polynomial[21]),
- .O(p_0_in14_in[23]));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[23]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[23]),
- .I3(finalXOR[23]),
- .O(\CRC[23]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[23]_i_4
- (.I0(CRC63_in[23]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[23]),
- .I5(p_0_in46_in[23]),
- .O(\CRC[23]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[23]_i_5
- (.I0(polynomial[20]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[19]),
- .I4(CRC__16__0),
- .I5(polynomial[19]),
- .O(p_0_in18_in[21]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[23]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[22]),
- .I2(p_0_in50_in[21]),
- .I3(polynomial[21]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[23]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[23]_i_7
- (.I0(polynomial[18]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[17]),
- .I4(CRC__14__0),
- .I5(polynomial[17]),
- .O(p_0_in22_in[19]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[23]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[20]),
- .I2(p_0_in54_in[19]),
- .I3(polynomial[19]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[21]));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[23]_i_9
- (.I0(polynomial[16]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[15]),
- .I4(polynomial[15]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[17]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[24]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[24]),
- .I2(CRC__20__0),
- .I3(polynomial[24]),
- .I4(\CRC[24]_i_3_n_0 ),
- .I5(\CRC[24]_i_4_n_0 ),
- .O(CRC__28[24]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[24]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[19]),
- .I2(p_0_in58_in[18]),
- .I3(polynomial[18]),
- .I4(CRC__31),
- .O(p_0_in54_in[20]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[24]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[15]),
- .I3(p_0_in34_in[14]),
- .I4(polynomial[14]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[16]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[24]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[17]),
- .I2(\CRC_reg_n_0_[16] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[16]),
- .O(p_0_in58_in[18]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[24]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[13]),
- .I3(p_0_in38_in[12]),
- .I4(polynomial[12]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[14]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[24]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[11]),
- .I3(p_0_in42_in[10]),
- .I4(polynomial[10]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[12]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[24]_i_15
- (.I0(polynomial[9]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[8] ),
- .O(p_0_in42_in[10]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[24]_i_2
- (.I0(polynomial[23]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[22]),
- .I4(CRC__18__0),
- .I5(polynomial[22]),
- .O(p_0_in14_in[24]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[24]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[24]),
- .I3(finalXOR[24]),
- .O(\CRC[24]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[24]_i_4
- (.I0(CRC63_in[24]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(polynomial[24]),
- .I4(CRC__5__0),
- .I5(p_0_in46_in[24]),
- .O(\CRC[24]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[24]_i_5
- (.I0(polynomial[21]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[20]),
- .I4(CRC__16__0),
- .I5(polynomial[20]),
- .O(p_0_in18_in[22]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[24]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[23]),
- .I2(p_0_in50_in[22]),
- .I3(polynomial[22]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[24]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[24]_i_7
- (.I0(polynomial[19]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[18]),
- .I4(CRC__14__0),
- .I5(polynomial[18]),
- .O(p_0_in22_in[20]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[24]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[21]),
- .I2(p_0_in54_in[20]),
- .I3(polynomial[20]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[22]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[24]_i_9
- (.I0(polynomial[17]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[16]),
- .I4(CRC__12__0),
- .I5(polynomial[16]),
- .O(p_0_in26_in[18]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[25]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[25]),
- .I2(CRC__20__0),
- .I3(polynomial[25]),
- .I4(\CRC[25]_i_3_n_0 ),
- .I5(\CRC[25]_i_4_n_0 ),
- .O(CRC__28[25]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[25]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[20]),
- .I2(p_0_in58_in[19]),
- .I3(polynomial[19]),
- .I4(CRC__31),
- .O(p_0_in54_in[21]));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[25]_i_11
- (.I0(polynomial[16]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[15]),
- .I4(polynomial[15]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[17]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[25]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[18]),
- .I2(\CRC_reg_n_0_[17] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[17]),
- .O(p_0_in58_in[19]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[25]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[14]),
- .I3(p_0_in38_in[13]),
- .I4(polynomial[13]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[15]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[25]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[12]),
- .I3(p_0_in42_in[11]),
- .I4(polynomial[11]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[13]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[25]_i_15
- (.I0(polynomial[10]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[9] ),
- .O(p_0_in42_in[11]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[25]_i_2
- (.I0(polynomial[24]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[23]),
- .I4(CRC__18__0),
- .I5(polynomial[23]),
- .O(p_0_in14_in[25]));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[25]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[25]),
- .I3(finalXOR[25]),
- .O(\CRC[25]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[25]_i_4
- (.I0(CRC63_in[25]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(polynomial[25]),
- .I4(CRC__5__0),
- .I5(p_0_in46_in[25]),
- .O(\CRC[25]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[25]_i_5
- (.I0(polynomial[22]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[21]),
- .I4(CRC__16__0),
- .I5(polynomial[21]),
- .O(p_0_in18_in[23]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[25]_i_6
- (.I0(polynomial[24]),
- .I1(CRC__4__0),
- .I2(p_0_in50_in[23]),
- .I3(polynomial[23]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[25]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[25]_i_7
- (.I0(polynomial[20]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[19]),
- .I4(CRC__14__0),
- .I5(polynomial[19]),
- .O(p_0_in22_in[21]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[25]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[22]),
- .I2(p_0_in54_in[21]),
- .I3(polynomial[21]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[23]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[25]_i_9
- (.I0(polynomial[18]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[17]),
- .I4(CRC__12__0),
- .I5(polynomial[17]),
- .O(p_0_in26_in[19]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[26]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[26]),
- .I2(CRC__20__0),
- .I3(polynomial[26]),
- .I4(\CRC[26]_i_3_n_0 ),
- .I5(\CRC[26]_i_4_n_0 ),
- .O(CRC__28[26]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[26]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[21]),
- .I2(p_0_in58_in[20]),
- .I3(polynomial[20]),
- .I4(CRC__31),
- .O(p_0_in54_in[22]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[26]_i_11
- (.I0(polynomial[17]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[16]),
- .I4(CRC__10__0),
- .I5(polynomial[16]),
- .O(p_0_in30_in[18]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[26]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[19]),
- .I2(\CRC_reg_n_0_[18] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[18]),
- .O(p_0_in58_in[20]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[26]_i_13
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[15]),
- .I3(p_0_in38_in[14]),
- .I4(polynomial[14]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[16]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[26]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[13]),
- .I3(p_0_in42_in[12]),
- .I4(polynomial[12]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[14]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[26]_i_15
- (.I0(polynomial[11]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[10] ),
- .O(p_0_in42_in[12]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[26]_i_2
- (.I0(polynomial[25]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[24]),
- .I4(CRC__18__0),
- .I5(polynomial[24]),
- .O(p_0_in14_in[26]));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[26]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[26]),
- .I3(finalXOR[26]),
- .O(\CRC[26]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[26]_i_4
- (.I0(CRC63_in[26]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(polynomial[26]),
- .I4(CRC__5__0),
- .I5(p_0_in46_in[26]),
- .O(\CRC[26]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[26]_i_5
- (.I0(polynomial[23]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[22]),
- .I4(CRC__16__0),
- .I5(polynomial[22]),
- .O(p_0_in18_in[24]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[26]_i_6
- (.I0(polynomial[25]),
- .I1(CRC__4__0),
- .I2(p_0_in50_in[24]),
- .I3(CRC__3__0),
- .I4(polynomial[24]),
- .O(p_0_in46_in[26]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[26]_i_7
- (.I0(polynomial[21]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[20]),
- .I4(CRC__14__0),
- .I5(polynomial[20]),
- .O(p_0_in22_in[22]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[26]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[23]),
- .I2(p_0_in54_in[22]),
- .I3(polynomial[22]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[24]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[26]_i_9
- (.I0(polynomial[19]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[18]),
- .I4(CRC__12__0),
- .I5(polynomial[18]),
- .O(p_0_in26_in[20]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[27]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[27]),
- .I2(CRC__20__0),
- .I3(polynomial[27]),
- .I4(\CRC[27]_i_3_n_0 ),
- .I5(\CRC[27]_i_4_n_0 ),
- .O(CRC__28[27]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[27]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[22]),
- .I2(p_0_in58_in[21]),
- .I3(polynomial[21]),
- .I4(CRC__31),
- .O(p_0_in54_in[23]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[27]_i_11
- (.I0(polynomial[18]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[17]),
- .I4(CRC__10__0),
- .I5(polynomial[17]),
- .O(p_0_in30_in[19]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[27]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[20]),
- .I2(\CRC_reg_n_0_[19] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[19]),
- .O(p_0_in58_in[21]));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[27]_i_13
- (.I0(polynomial[16]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[15]),
- .I4(polynomial[15]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[17]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[27]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[14]),
- .I3(p_0_in42_in[13]),
- .I4(polynomial[13]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[15]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[27]_i_15
- (.I0(polynomial[12]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[11] ),
- .O(p_0_in42_in[13]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[27]_i_2
- (.I0(polynomial[26]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[25]),
- .I4(CRC__18__0),
- .I5(polynomial[25]),
- .O(p_0_in14_in[27]));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[27]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[27]),
- .I3(finalXOR[27]),
- .O(\CRC[27]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[27]_i_4
- (.I0(CRC63_in[27]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(polynomial[27]),
- .I4(CRC__5__0),
- .I5(p_0_in46_in[27]),
- .O(\CRC[27]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[27]_i_5
- (.I0(polynomial[24]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[23]),
- .I4(CRC__16__0),
- .I5(polynomial[23]),
- .O(p_0_in18_in[25]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[27]_i_6
- (.I0(polynomial[26]),
- .I1(CRC__4__0),
- .I2(p_0_in50_in[25]),
- .I3(CRC__3__0),
- .I4(polynomial[25]),
- .O(p_0_in46_in[27]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[27]_i_7
- (.I0(polynomial[22]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[21]),
- .I4(CRC__14__0),
- .I5(polynomial[21]),
- .O(p_0_in22_in[23]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[27]_i_8
- (.I0(polynomial[24]),
- .I1(CRC__2__0),
- .I2(p_0_in54_in[23]),
- .I3(polynomial[23]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[25]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[27]_i_9
- (.I0(polynomial[20]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[19]),
- .I4(CRC__12__0),
- .I5(polynomial[19]),
- .O(p_0_in26_in[21]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[28]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[28]),
- .I2(CRC__20__0),
- .I3(polynomial[28]),
- .I4(\CRC[28]_i_3_n_0 ),
- .I5(\CRC[28]_i_4_n_0 ),
- .O(CRC__28[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[28]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[23]),
- .I2(p_0_in58_in[22]),
- .I3(polynomial[22]),
- .I4(CRC__31),
- .O(p_0_in54_in[24]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[28]_i_11
- (.I0(polynomial[19]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[18]),
- .I4(CRC__10__0),
- .I5(polynomial[18]),
- .O(p_0_in30_in[20]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[28]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[21]),
- .I2(\CRC_reg_n_0_[20] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[20]),
- .O(p_0_in58_in[22]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[28]_i_13
- (.I0(polynomial[17]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[16]),
- .I4(CRC__8__0),
- .I5(polynomial[16]),
- .O(p_0_in34_in[18]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[28]_i_14
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[15]),
- .I3(p_0_in42_in[14]),
- .I4(polynomial[14]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[16]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[28]_i_15
- (.I0(polynomial[13]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[12] ),
- .O(p_0_in42_in[14]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[28]_i_2
- (.I0(polynomial[27]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[26]),
- .I4(CRC__18__0),
- .I5(polynomial[26]),
- .O(p_0_in14_in[28]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[28]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[28]),
- .I3(finalXOR[28]),
- .O(\CRC[28]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[28]_i_4
- (.I0(CRC63_in[28]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(polynomial[28]),
- .I4(CRC__5__0),
- .I5(p_0_in46_in[28]),
- .O(\CRC[28]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[28]_i_5
- (.I0(polynomial[25]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[24]),
- .I4(CRC__16__0),
- .I5(polynomial[24]),
- .O(p_0_in18_in[26]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[28]_i_6
- (.I0(polynomial[27]),
- .I1(CRC__4__0),
- .I2(p_0_in50_in[26]),
- .I3(CRC__3__0),
- .I4(polynomial[26]),
- .O(p_0_in46_in[28]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[28]_i_7
- (.I0(polynomial[23]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[22]),
- .I4(CRC__14__0),
- .I5(polynomial[22]),
- .O(p_0_in22_in[24]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[28]_i_8
- (.I0(polynomial[25]),
- .I1(CRC__2__0),
- .I2(p_0_in54_in[24]),
- .I3(CRC__1__0),
- .I4(polynomial[24]),
- .O(p_0_in50_in[26]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[28]_i_9
- (.I0(polynomial[21]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[20]),
- .I4(CRC__12__0),
- .I5(polynomial[20]),
- .O(p_0_in26_in[22]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[29]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[29]),
- .I2(CRC__20__0),
- .I3(polynomial[29]),
- .I4(\CRC[29]_i_4_n_0 ),
- .I5(\CRC[29]_i_5_n_0 ),
- .O(CRC__28[29]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[29]_i_10
- (.I0(polynomial[24]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[23]),
- .I4(CRC__14__0),
- .I5(polynomial[23]),
- .O(p_0_in22_in[25]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[29]_i_11
- (.I0(polynomial[26]),
- .I1(CRC__2__0),
- .I2(p_0_in54_in[25]),
- .I3(CRC__1__0),
- .I4(polynomial[25]),
- .O(p_0_in50_in[27]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[29]_i_12
- (.I0(polynomial[26]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[25]),
- .I4(CRC__12__0),
- .I5(polynomial[25]),
- .O(p_0_in26_in[27]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[29]_i_13
- (.I0(polynomial[22]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[21]),
- .I4(CRC__12__0),
- .I5(polynomial[21]),
- .O(p_0_in26_in[23]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[29]_i_14
- (.I0(polynomial[24]),
- .I1(CRC__0__0),
- .I2(p_0_in58_in[23]),
- .I3(polynomial[23]),
- .I4(CRC__31),
- .O(p_0_in54_in[25]));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[29]_i_15
- (.I0(polynomial[24]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[23]),
- .I4(polynomial[23]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[25]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[29]_i_16
- (.I0(polynomial[20]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[19]),
- .I4(CRC__10__0),
- .I5(polynomial[19]),
- .O(p_0_in30_in[21]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[29]_i_17
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[22]),
- .I2(\CRC_reg_n_0_[21] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[21]),
- .O(p_0_in58_in[23]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[29]_i_18
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[22]),
- .I3(p_0_in38_in[21]),
- .I4(polynomial[21]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[23]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[29]_i_19
- (.I0(polynomial[18]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[17]),
- .I4(CRC__8__0),
- .I5(polynomial[17]),
- .O(p_0_in34_in[19]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[29]_i_2
- (.I0(polynomial[28]),
- .I1(polynomial[31]),
- .I2(p_0_in18_in[31]),
- .I3(p_0_in18_in[27]),
- .I4(CRC__18__0),
- .I5(polynomial[27]),
- .O(p_0_in14_in[29]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[29]_i_20
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[20]),
- .I3(p_0_in42_in[19]),
- .I4(polynomial[19]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[21]));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[29]_i_21
- (.I0(polynomial[16]),
- .I1(polynomial[31]),
- .I2(p_0_in42_in[31]),
- .I3(p_0_in42_in[15]),
- .I4(polynomial[15]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[17]));
- LUT5 #(
- .INIT(32'h609F9F60))
- \CRC[29]_i_22
- (.I0(p_0_in65_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[18]),
- .I3(\CRC_reg_n_0_[17] ),
- .I4(p_0_in65_in[17]),
- .O(p_0_in42_in[19]));
- LUT4 #(
- .INIT(16'hD728))
- \CRC[29]_i_23
- (.I0(polynomial[14]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[13] ),
- .O(p_0_in42_in[15]));
- LUT6 #(
- .INIT(64'h827DD728DD227788))
- \CRC[29]_i_3
- (.I0(polynomial[31]),
- .I1(p_0_in20_in[30]),
- .I2(CRC__17__0),
- .I3(p_0_in18_in[30]),
- .I4(CRC__18__0),
- .I5(polynomial[30]),
- .O(CRC__20__0));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[29]_i_4
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[29]),
- .I3(finalXOR[29]),
- .O(\CRC[29]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[29]_i_5
- (.I0(CRC63_in[29]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(polynomial[29]),
- .I4(CRC__5__0),
- .I5(p_0_in46_in[29]),
- .O(\CRC[29]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[29]_i_6
- (.I0(polynomial[30]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[29]),
- .I4(CRC__16__0),
- .I5(polynomial[29]),
- .O(p_0_in18_in[31]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[29]_i_7
- (.I0(polynomial[26]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[25]),
- .I4(CRC__16__0),
- .I5(polynomial[25]),
- .O(p_0_in18_in[27]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[29]_i_8
- (.I0(polynomial[28]),
- .I1(CRC__4__0),
- .I2(p_0_in50_in[27]),
- .I3(CRC__3__0),
- .I4(polynomial[27]),
- .O(p_0_in46_in[29]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[29]_i_9
- (.I0(polynomial[28]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[27]),
- .I4(CRC__14__0),
- .I5(polynomial[27]),
- .O(p_0_in22_in[29]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[2]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[2]),
- .I2(polynomial[2]),
- .I3(CRC__20__0),
- .I4(\CRC[2]_i_3_n_0 ),
- .I5(\CRC[2]_i_4_n_0 ),
- .O(CRC__28[2]));
- LUT6 #(
- .INIT(64'h96FF6900C300C300))
- \CRC[2]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in20_in[30]),
- .I2(\CRC[2]_i_5_n_0 ),
- .I3(polynomial[1]),
- .I4(polynomial[0]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[2]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[2]),
- .I3(finalXOR[2]),
- .O(\CRC[2]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[2]_i_4
- (.I0(CRC63_in[2]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[2]),
- .I5(p_0_in46_in[2]),
- .O(\CRC[2]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT5 #(
- .INIT(32'h6999FFFF))
- \CRC[2]_i_5
- (.I0(CRC__15__0),
- .I1(p_0_in24_in[30]),
- .I2(CRC__16__0),
- .I3(polynomial[31]),
- .I4(polynomial[30]),
- .O(\CRC[2]_i_5_n_0 ));
- LUT4 #(
- .INIT(16'h7888))
- \CRC[2]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[1]),
- .I2(polynomial[0]),
- .I3(CRC__3__0),
- .O(p_0_in46_in[2]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF8228))
- \CRC[30]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(\CRC[30]_i_2_n_0 ),
- .I2(p_0_in16_in[29]),
- .I3(\CRC[30]_i_4_n_0 ),
- .I4(\CRC[30]_i_5_n_0 ),
- .I5(\CRC[30]_i_6_n_0 ),
- .O(CRC__28[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[30]_i_10
- (.I0(polynomial[27]),
- .I1(CRC__2__0),
- .I2(p_0_in54_in[26]),
- .I3(CRC__1__0),
- .I4(polynomial[26]),
- .O(p_0_in50_in[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[30]_i_11
- (.I0(polynomial[22]),
- .I1(CRC__12__0),
- .I2(p_0_in32_in[21]),
- .I3(CRC__11__0),
- .I4(polynomial[21]),
- .O(p_0_in28_in[23]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[30]_i_12
- (.I0(polynomial[25]),
- .I1(CRC__0__0),
- .I2(p_0_in58_in[24]),
- .I3(CRC__31),
- .I4(polynomial[24]),
- .O(p_0_in54_in[26]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[30]_i_13
- (.I0(polynomial[20]),
- .I1(CRC__10__0),
- .I2(p_0_in36_in[19]),
- .I3(CRC__9__0),
- .I4(polynomial[19]),
- .O(p_0_in32_in[21]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[30]_i_14
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[23]),
- .I2(\CRC_reg_n_0_[22] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[22]),
- .O(p_0_in58_in[24]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[30]_i_15
- (.I0(polynomial[18]),
- .I1(CRC__8__0),
- .I2(p_0_in40_in[17]),
- .I3(CRC__7__0),
- .I4(polynomial[17]),
- .O(p_0_in36_in[19]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \CRC[30]_i_16
- (.I0(polynomial[16]),
- .I1(CRC__6__0),
- .I2(\CRC_reg_n_0_[14] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in65_in[31]),
- .I5(polynomial[15]),
- .O(p_0_in40_in[17]));
- LUT6 #(
- .INIT(64'h78878787FFFFFFFF))
- \CRC[30]_i_2
- (.I0(polynomial[30]),
- .I1(CRC__17__0),
- .I2(p_0_in20_in[30]),
- .I3(CRC__18__0),
- .I4(polynomial[31]),
- .I5(polynomial[29]),
- .O(\CRC[30]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[30]_i_3
- (.I0(polynomial[28]),
- .I1(CRC__18__0),
- .I2(p_0_in20_in[27]),
- .I3(CRC__17__0),
- .I4(polynomial[27]),
- .O(p_0_in16_in[29]));
- LUT6 #(
- .INIT(64'h3CC39999FFFFFFFF))
- \CRC[30]_i_4
- (.I0(CRC__18__0),
- .I1(p_0_in18_in[30]),
- .I2(CRC__17__0),
- .I3(p_0_in20_in[30]),
- .I4(polynomial[31]),
- .I5(polynomial[30]),
- .O(\CRC[30]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[30]_i_5
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[30]),
- .I3(finalXOR[30]),
- .O(\CRC[30]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[30]_i_6
- (.I0(CRC63_in[30]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(polynomial[30]),
- .I4(CRC__5__0),
- .I5(p_0_in46_in[30]),
- .O(\CRC[30]_i_6_n_0 ));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[30]_i_7
- (.I0(polynomial[26]),
- .I1(CRC__16__0),
- .I2(p_0_in24_in[25]),
- .I3(CRC__15__0),
- .I4(polynomial[25]),
- .O(p_0_in20_in[27]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[30]_i_8
- (.I0(polynomial[29]),
- .I1(CRC__4__0),
- .I2(p_0_in50_in[28]),
- .I3(CRC__3__0),
- .I4(polynomial[28]),
- .O(p_0_in46_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[30]_i_9
- (.I0(polynomial[24]),
- .I1(CRC__14__0),
- .I2(p_0_in28_in[23]),
- .I3(CRC__13__0),
- .I4(polynomial[23]),
- .O(p_0_in24_in[25]));
- LUT4 #(
- .INIT(16'h33E2))
- \CRC[31]_i_1
- (.I0(S_AXIS_TVALID),
- .I1(state[1]),
- .I2(M_AXIS_TREADY),
- .I3(state[0]),
- .O(\CRC[31]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_10
- (.I0(polynomial[29]),
- .I1(CRC__16__0),
- .I2(p_0_in24_in[28]),
- .I3(CRC__15__0),
- .I4(polynomial[28]),
- .O(p_0_in20_in[30]));
- LUT5 #(
- .INIT(32'h28D7D728))
- \CRC[31]_i_100
- (.I0(polynomial[25]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[24] ),
- .I4(p_0_in65_in[24]),
- .O(p_0_in42_in[26]));
- LUT5 #(
- .INIT(32'h28D7D728))
- \CRC[31]_i_101
- (.I0(polynomial[27]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[26] ),
- .I4(p_0_in65_in[26]),
- .O(p_0_in42_in[28]));
- LUT5 #(
- .INIT(32'h28D7D728))
- \CRC[31]_i_102
- (.I0(polynomial[26]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[25] ),
- .I4(p_0_in65_in[25]),
- .O(p_0_in42_in[27]));
- LUT5 #(
- .INIT(32'h28D7D728))
- \CRC[31]_i_103
- (.I0(polynomial[24]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[23] ),
- .I4(p_0_in65_in[23]),
- .O(p_0_in42_in[25]));
- LUT5 #(
- .INIT(32'h609F9F60))
- \CRC[31]_i_104
- (.I0(p_0_in65_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[21]),
- .I3(\CRC_reg_n_0_[20] ),
- .I4(p_0_in65_in[20]),
- .O(p_0_in42_in[22]));
- LUT5 #(
- .INIT(32'h609F9F60))
- \CRC[31]_i_105
- (.I0(p_0_in65_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[23]),
- .I3(\CRC_reg_n_0_[22] ),
- .I4(p_0_in65_in[22]),
- .O(p_0_in42_in[24]));
- LUT5 #(
- .INIT(32'h609F9F60))
- \CRC[31]_i_106
- (.I0(p_0_in65_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[22]),
- .I3(\CRC_reg_n_0_[21] ),
- .I4(p_0_in65_in[21]),
- .O(p_0_in42_in[23]));
- LUT5 #(
- .INIT(32'h609F9F60))
- \CRC[31]_i_107
- (.I0(p_0_in65_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[19]),
- .I3(\CRC_reg_n_0_[18] ),
- .I4(p_0_in65_in[18]),
- .O(p_0_in42_in[20]));
- LUT5 #(
- .INIT(32'h609F9F60))
- \CRC[31]_i_108
- (.I0(p_0_in65_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[20]),
- .I3(\CRC_reg_n_0_[19] ),
- .I4(p_0_in65_in[19]),
- .O(p_0_in42_in[21]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT5 #(
- .INIT(32'h609F9F60))
- \CRC[31]_i_109
- (.I0(p_0_in65_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[17]),
- .I3(\CRC_reg_n_0_[16] ),
- .I4(p_0_in65_in[16]),
- .O(p_0_in42_in[18]));
- LUT6 #(
- .INIT(64'h827DD728DD227788))
- \CRC[31]_i_11
- (.I0(polynomial[31]),
- .I1(p_0_in24_in[30]),
- .I2(CRC__15__0),
- .I3(p_0_in22_in[30]),
- .I4(CRC__16__0),
- .I5(polynomial[30]),
- .O(CRC__18__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_12
- (.I0(polynomial[27]),
- .I1(CRC__16__0),
- .I2(p_0_in24_in[26]),
- .I3(CRC__15__0),
- .I4(polynomial[26]),
- .O(p_0_in20_in[28]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_13
- (.I0(polynomial[29]),
- .I1(polynomial[31]),
- .I2(p_0_in22_in[31]),
- .I3(p_0_in22_in[28]),
- .I4(CRC__16__0),
- .I5(polynomial[28]),
- .O(p_0_in18_in[30]));
- LUT2 #(
- .INIT(4'h2))
- \CRC[31]_i_14
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .O(\CRC[31]_i_14_n_0 ));
- LUT2 #(
- .INIT(4'hE))
- \CRC[31]_i_15
- (.I0(state[1]),
- .I1(state[0]),
- .O(\CRC[31]_i_15_n_0 ));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_16
- (.I0(polynomial[31]),
- .I1(CRC__4__0),
- .I2(p_0_in50_in[30]),
- .I3(CRC__3__0),
- .I4(polynomial[30]),
- .O(CRC__5__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_17
- (.I0(polynomial[30]),
- .I1(CRC__4__0),
- .I2(p_0_in50_in[29]),
- .I3(CRC__3__0),
- .I4(polynomial[29]),
- .O(p_0_in46_in[31]));
- LUT6 #(
- .INIT(64'h827DD728DD227788))
- \CRC[31]_i_18
- (.I0(polynomial[31]),
- .I1(p_0_in28_in[30]),
- .I2(CRC__13__0),
- .I3(p_0_in26_in[30]),
- .I4(CRC__14__0),
- .I5(polynomial[30]),
- .O(CRC__16__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_19
- (.I0(polynomial[29]),
- .I1(CRC__14__0),
- .I2(p_0_in28_in[28]),
- .I3(CRC__13__0),
- .I4(polynomial[28]),
- .O(p_0_in24_in[30]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF8228))
- \CRC[31]_i_2
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(\CRC[31]_i_4_n_0 ),
- .I2(p_0_in16_in[30]),
- .I3(\CRC[31]_i_6_n_0 ),
- .I4(\CRC[31]_i_7_n_0 ),
- .I5(\CRC[31]_i_8_n_0 ),
- .O(CRC__28[31]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_20
- (.I0(polynomial[31]),
- .I1(CRC__14__0),
- .I2(p_0_in28_in[30]),
- .I3(CRC__13__0),
- .I4(polynomial[30]),
- .O(CRC__15__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_21
- (.I0(polynomial[27]),
- .I1(CRC__14__0),
- .I2(p_0_in28_in[26]),
- .I3(CRC__13__0),
- .I4(polynomial[26]),
- .O(p_0_in24_in[28]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_22
- (.I0(polynomial[29]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[28]),
- .I4(CRC__14__0),
- .I5(polynomial[28]),
- .O(p_0_in22_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_23
- (.I0(polynomial[25]),
- .I1(CRC__14__0),
- .I2(p_0_in28_in[24]),
- .I3(CRC__13__0),
- .I4(polynomial[24]),
- .O(p_0_in24_in[26]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_24
- (.I0(polynomial[30]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[29]),
- .I4(CRC__14__0),
- .I5(polynomial[29]),
- .O(p_0_in22_in[31]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_25
- (.I0(polynomial[27]),
- .I1(polynomial[31]),
- .I2(p_0_in26_in[31]),
- .I3(p_0_in26_in[26]),
- .I4(CRC__14__0),
- .I5(polynomial[26]),
- .O(p_0_in22_in[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_26
- (.I0(polynomial[29]),
- .I1(CRC__2__0),
- .I2(p_0_in54_in[28]),
- .I3(CRC__1__0),
- .I4(polynomial[28]),
- .O(p_0_in50_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_27
- (.I0(polynomial[31]),
- .I1(CRC__2__0),
- .I2(p_0_in54_in[30]),
- .I3(CRC__1__0),
- .I4(polynomial[30]),
- .O(CRC__3__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_28
- (.I0(polynomial[28]),
- .I1(CRC__2__0),
- .I2(p_0_in54_in[27]),
- .I3(CRC__1__0),
- .I4(polynomial[27]),
- .O(p_0_in50_in[29]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_29
- (.I0(polynomial[29]),
- .I1(CRC__12__0),
- .I2(p_0_in32_in[28]),
- .I3(CRC__11__0),
- .I4(polynomial[28]),
- .O(p_0_in28_in[30]));
- LUT2 #(
- .INIT(4'h2))
- \CRC[31]_i_3
- (.I0(state[0]),
- .I1(state[1]),
- .O(\CRC[31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_30
- (.I0(polynomial[31]),
- .I1(CRC__12__0),
- .I2(p_0_in32_in[30]),
- .I3(CRC__11__0),
- .I4(polynomial[30]),
- .O(CRC__13__0));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_31
- (.I0(polynomial[29]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[28]),
- .I4(CRC__12__0),
- .I5(polynomial[28]),
- .O(p_0_in26_in[30]));
- LUT6 #(
- .INIT(64'h827DD728DD227788))
- \CRC[31]_i_32
- (.I0(polynomial[31]),
- .I1(p_0_in32_in[30]),
- .I2(CRC__11__0),
- .I3(p_0_in30_in[30]),
- .I4(CRC__12__0),
- .I5(polynomial[30]),
- .O(CRC__14__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_33
- (.I0(polynomial[27]),
- .I1(CRC__12__0),
- .I2(p_0_in32_in[26]),
- .I3(CRC__11__0),
- .I4(polynomial[26]),
- .O(p_0_in28_in[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_34
- (.I0(polynomial[25]),
- .I1(CRC__12__0),
- .I2(p_0_in32_in[24]),
- .I3(CRC__11__0),
- .I4(polynomial[24]),
- .O(p_0_in28_in[26]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_35
- (.I0(polynomial[30]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[29]),
- .I4(CRC__12__0),
- .I5(polynomial[29]),
- .O(p_0_in26_in[31]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_36
- (.I0(polynomial[27]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[26]),
- .I4(CRC__12__0),
- .I5(polynomial[26]),
- .O(p_0_in26_in[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_37
- (.I0(polynomial[23]),
- .I1(CRC__12__0),
- .I2(p_0_in32_in[22]),
- .I3(CRC__11__0),
- .I4(polynomial[22]),
- .O(p_0_in28_in[24]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_38
- (.I0(polynomial[28]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[27]),
- .I4(CRC__12__0),
- .I5(polynomial[27]),
- .O(p_0_in26_in[29]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_39
- (.I0(polynomial[25]),
- .I1(polynomial[31]),
- .I2(p_0_in30_in[31]),
- .I3(p_0_in30_in[24]),
- .I4(CRC__12__0),
- .I5(polynomial[24]),
- .O(p_0_in26_in[26]));
- LUT5 #(
- .INIT(32'h6999FFFF))
- \CRC[31]_i_4
- (.I0(CRC__17__0),
- .I1(p_0_in20_in[30]),
- .I2(CRC__18__0),
- .I3(polynomial[31]),
- .I4(polynomial[30]),
- .O(\CRC[31]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_40
- (.I0(polynomial[27]),
- .I1(CRC__0__0),
- .I2(p_0_in58_in[26]),
- .I3(CRC__31),
- .I4(polynomial[26]),
- .O(p_0_in54_in[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_41
- (.I0(polynomial[26]),
- .I1(CRC__0__0),
- .I2(p_0_in58_in[25]),
- .I3(CRC__31),
- .I4(polynomial[25]),
- .O(p_0_in54_in[27]));
- LUT6 #(
- .INIT(64'h827DD728DD227788))
- \CRC[31]_i_42
- (.I0(polynomial[31]),
- .I1(p_0_in36_in[30]),
- .I2(CRC__9__0),
- .I3(p_0_in34_in[30]),
- .I4(CRC__10__0),
- .I5(polynomial[30]),
- .O(CRC__12__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_43
- (.I0(polynomial[27]),
- .I1(CRC__10__0),
- .I2(p_0_in36_in[26]),
- .I3(CRC__9__0),
- .I4(polynomial[26]),
- .O(p_0_in32_in[28]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_44
- (.I0(polynomial[31]),
- .I1(CRC__10__0),
- .I2(p_0_in36_in[30]),
- .I3(CRC__9__0),
- .I4(polynomial[30]),
- .O(CRC__11__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_45
- (.I0(polynomial[29]),
- .I1(CRC__10__0),
- .I2(p_0_in36_in[28]),
- .I3(CRC__9__0),
- .I4(polynomial[28]),
- .O(p_0_in32_in[30]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_46
- (.I0(polynomial[30]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[29]),
- .I4(CRC__10__0),
- .I5(polynomial[29]),
- .O(p_0_in30_in[31]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_47
- (.I0(polynomial[27]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[26]),
- .I4(CRC__10__0),
- .I5(polynomial[26]),
- .O(p_0_in30_in[28]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_48
- (.I0(polynomial[29]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[28]),
- .I4(CRC__10__0),
- .I5(polynomial[28]),
- .O(p_0_in30_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_49
- (.I0(polynomial[25]),
- .I1(CRC__10__0),
- .I2(p_0_in36_in[24]),
- .I3(CRC__9__0),
- .I4(polynomial[24]),
- .O(p_0_in32_in[26]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_5
- (.I0(polynomial[29]),
- .I1(CRC__18__0),
- .I2(p_0_in20_in[28]),
- .I3(CRC__17__0),
- .I4(polynomial[28]),
- .O(p_0_in16_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_50
- (.I0(CRC__10__0),
- .I1(polynomial[23]),
- .I2(p_0_in36_in[22]),
- .I3(polynomial[22]),
- .I4(CRC__9__0),
- .O(p_0_in32_in[24]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_51
- (.I0(polynomial[28]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[27]),
- .I4(CRC__10__0),
- .I5(polynomial[27]),
- .O(p_0_in30_in[29]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_52
- (.I0(polynomial[25]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[24]),
- .I4(CRC__10__0),
- .I5(polynomial[24]),
- .O(p_0_in30_in[26]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_53
- (.I0(polynomial[21]),
- .I1(CRC__10__0),
- .I2(p_0_in36_in[20]),
- .I3(CRC__9__0),
- .I4(polynomial[20]),
- .O(p_0_in32_in[22]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_54
- (.I0(polynomial[26]),
- .I1(polynomial[31]),
- .I2(p_0_in34_in[31]),
- .I3(p_0_in34_in[25]),
- .I4(CRC__10__0),
- .I5(polynomial[25]),
- .O(p_0_in30_in[27]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[31]_i_55
- (.I0(polynomial[31]),
- .I1(p_0_in34_in[31]),
- .I2(polynomial[23]),
- .I3(p_0_in34_in[22]),
- .I4(polynomial[22]),
- .I5(CRC__10__0),
- .O(p_0_in30_in[24]));
- LUT6 #(
- .INIT(64'h8788877778777888))
- \CRC[31]_i_56
- (.I0(polynomial[25]),
- .I1(\CRC[7]_i_11_n_0 ),
- .I2(initial_value[24]),
- .I3(firstWord_reg_n_0),
- .I4(\CRC_reg_n_0_[24] ),
- .I5(S_AXIS_TDATA[0]),
- .O(p_0_in58_in[26]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[31]_i_57
- (.I0(polynomial[24]),
- .I1(\CRC[7]_i_11_n_0 ),
- .I2(\CRC_reg_n_0_[23] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[23]),
- .O(p_0_in58_in[25]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_58
- (.I0(polynomial[29]),
- .I1(CRC__8__0),
- .I2(p_0_in40_in[28]),
- .I3(CRC__7__0),
- .I4(polynomial[28]),
- .O(p_0_in36_in[30]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_59
- (.I0(polynomial[31]),
- .I1(CRC__8__0),
- .I2(p_0_in40_in[30]),
- .I3(CRC__7__0),
- .I4(polynomial[30]),
- .O(CRC__9__0));
- LUT6 #(
- .INIT(64'h1EB4E14BFFFFFFFF))
- \CRC[31]_i_6
- (.I0(polynomial[30]),
- .I1(CRC__18__0),
- .I2(p_0_in18_in[30]),
- .I3(CRC__17__0),
- .I4(p_0_in20_in[30]),
- .I5(polynomial[31]),
- .O(\CRC[31]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_60
- (.I0(polynomial[29]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[28]),
- .I4(CRC__8__0),
- .I5(polynomial[28]),
- .O(p_0_in34_in[30]));
- LUT6 #(
- .INIT(64'h827DD728DD227788))
- \CRC[31]_i_61
- (.I0(polynomial[31]),
- .I1(p_0_in40_in[30]),
- .I2(CRC__7__0),
- .I3(p_0_in38_in[30]),
- .I4(CRC__8__0),
- .I5(polynomial[30]),
- .O(CRC__10__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_62
- (.I0(polynomial[25]),
- .I1(CRC__8__0),
- .I2(p_0_in40_in[24]),
- .I3(CRC__7__0),
- .I4(polynomial[24]),
- .O(p_0_in36_in[26]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_63
- (.I0(polynomial[27]),
- .I1(CRC__8__0),
- .I2(p_0_in40_in[26]),
- .I3(CRC__7__0),
- .I4(polynomial[26]),
- .O(p_0_in36_in[28]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_64
- (.I0(polynomial[30]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[29]),
- .I4(CRC__8__0),
- .I5(polynomial[29]),
- .O(p_0_in34_in[31]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_65
- (.I0(polynomial[28]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[27]),
- .I4(CRC__8__0),
- .I5(polynomial[27]),
- .O(p_0_in34_in[29]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_66
- (.I0(polynomial[25]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[24]),
- .I4(CRC__8__0),
- .I5(polynomial[24]),
- .O(p_0_in34_in[26]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_67
- (.I0(polynomial[27]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[26]),
- .I4(CRC__8__0),
- .I5(polynomial[26]),
- .O(p_0_in34_in[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_68
- (.I0(CRC__8__0),
- .I1(polynomial[23]),
- .I2(p_0_in40_in[22]),
- .I3(polynomial[22]),
- .I4(CRC__7__0),
- .O(p_0_in36_in[24]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_69
- (.I0(CRC__8__0),
- .I1(polynomial[21]),
- .I2(p_0_in40_in[20]),
- .I3(polynomial[20]),
- .I4(CRC__7__0),
- .O(p_0_in36_in[22]));
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[31]_i_7
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[31]),
- .I3(finalXOR[31]),
- .O(\CRC[31]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_70
- (.I0(polynomial[26]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[25]),
- .I4(CRC__8__0),
- .I5(polynomial[25]),
- .O(p_0_in34_in[27]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[31]_i_71
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[23]),
- .I3(p_0_in38_in[22]),
- .I4(polynomial[22]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[24]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_72
- (.I0(polynomial[19]),
- .I1(CRC__8__0),
- .I2(p_0_in40_in[18]),
- .I3(CRC__7__0),
- .I4(polynomial[18]),
- .O(p_0_in36_in[20]));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[31]_i_73
- (.I0(polynomial[24]),
- .I1(polynomial[31]),
- .I2(p_0_in38_in[31]),
- .I3(p_0_in38_in[23]),
- .I4(polynomial[23]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[25]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[31]_i_74
- (.I0(polynomial[31]),
- .I1(p_0_in38_in[31]),
- .I2(polynomial[21]),
- .I3(p_0_in38_in[20]),
- .I4(polynomial[20]),
- .I5(CRC__8__0),
- .O(p_0_in34_in[22]));
- LUT5 #(
- .INIT(32'h2D78D278))
- \CRC[31]_i_75
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(p_0_in42_in[30]),
- .I3(CRC__6__0),
- .I4(polynomial[30]),
- .O(CRC__8__0));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \CRC[31]_i_76
- (.I0(polynomial[27]),
- .I1(CRC__6__0),
- .I2(p_0_in65_in[25]),
- .I3(\CRC_reg_n_0_[25] ),
- .I4(\CRC[31]_i_98_n_0 ),
- .I5(polynomial[26]),
- .O(p_0_in40_in[28]));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \CRC[31]_i_77
- (.I0(polynomial[31]),
- .I1(CRC__6__0),
- .I2(p_0_in65_in[29]),
- .I3(\CRC_reg_n_0_[29] ),
- .I4(\CRC[31]_i_98_n_0 ),
- .I5(polynomial[30]),
- .O(CRC__7__0));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \CRC[31]_i_78
- (.I0(polynomial[29]),
- .I1(CRC__6__0),
- .I2(p_0_in65_in[27]),
- .I3(\CRC_reg_n_0_[27] ),
- .I4(\CRC[31]_i_98_n_0 ),
- .I5(polynomial[28]),
- .O(p_0_in40_in[30]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_79
- (.I0(polynomial[30]),
- .I1(polynomial[31]),
- .I2(p_0_in42_in[31]),
- .I3(p_0_in42_in[29]),
- .I4(CRC__6__0),
- .I5(polynomial[29]),
- .O(p_0_in38_in[31]));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[31]_i_8
- (.I0(CRC63_in[31]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(polynomial[31]),
- .I4(CRC__5__0),
- .I5(p_0_in46_in[31]),
- .O(\CRC[31]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_80
- (.I0(polynomial[27]),
- .I1(polynomial[31]),
- .I2(p_0_in42_in[31]),
- .I3(p_0_in42_in[26]),
- .I4(CRC__6__0),
- .I5(polynomial[26]),
- .O(p_0_in38_in[28]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_81
- (.I0(polynomial[29]),
- .I1(polynomial[31]),
- .I2(p_0_in42_in[31]),
- .I3(p_0_in42_in[28]),
- .I4(CRC__6__0),
- .I5(polynomial[28]),
- .O(p_0_in38_in[30]));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \CRC[31]_i_82
- (.I0(CRC__6__0),
- .I1(polynomial[23]),
- .I2(p_0_in65_in[21]),
- .I3(\CRC_reg_n_0_[21] ),
- .I4(polynomial[22]),
- .I5(\CRC[31]_i_98_n_0 ),
- .O(p_0_in40_in[24]));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \CRC[31]_i_83
- (.I0(polynomial[25]),
- .I1(CRC__6__0),
- .I2(p_0_in65_in[23]),
- .I3(\CRC_reg_n_0_[23] ),
- .I4(\CRC[31]_i_98_n_0 ),
- .I5(polynomial[24]),
- .O(p_0_in40_in[26]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_84
- (.I0(polynomial[28]),
- .I1(polynomial[31]),
- .I2(p_0_in42_in[31]),
- .I3(p_0_in42_in[27]),
- .I4(CRC__6__0),
- .I5(polynomial[27]),
- .O(p_0_in38_in[29]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_85
- (.I0(polynomial[26]),
- .I1(polynomial[31]),
- .I2(p_0_in42_in[31]),
- .I3(p_0_in42_in[25]),
- .I4(CRC__6__0),
- .I5(polynomial[25]),
- .O(p_0_in38_in[27]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[31]_i_86
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[23]),
- .I3(p_0_in42_in[22]),
- .I4(polynomial[22]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[24]));
- LUT6 #(
- .INIT(64'h28D75FA0D7285FA0))
- \CRC[31]_i_87
- (.I0(polynomial[25]),
- .I1(polynomial[31]),
- .I2(p_0_in42_in[31]),
- .I3(p_0_in42_in[24]),
- .I4(CRC__6__0),
- .I5(polynomial[24]),
- .O(p_0_in38_in[26]));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \CRC[31]_i_88
- (.I0(CRC__6__0),
- .I1(polynomial[21]),
- .I2(p_0_in65_in[19]),
- .I3(\CRC_reg_n_0_[19] ),
- .I4(polynomial[20]),
- .I5(\CRC[31]_i_98_n_0 ),
- .O(p_0_in40_in[22]));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \CRC[31]_i_89
- (.I0(CRC__6__0),
- .I1(polynomial[19]),
- .I2(p_0_in65_in[17]),
- .I3(\CRC_reg_n_0_[17] ),
- .I4(polynomial[18]),
- .I5(\CRC[31]_i_98_n_0 ),
- .O(p_0_in40_in[20]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[31]_i_9
- (.I0(polynomial[31]),
- .I1(CRC__16__0),
- .I2(p_0_in24_in[30]),
- .I3(CRC__15__0),
- .I4(polynomial[30]),
- .O(CRC__17__0));
- LUT6 #(
- .INIT(64'h28D7D7285FA05FA0))
- \CRC[31]_i_90
- (.I0(polynomial[24]),
- .I1(polynomial[31]),
- .I2(p_0_in42_in[31]),
- .I3(p_0_in42_in[23]),
- .I4(polynomial[23]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[25]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[31]_i_91
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[21]),
- .I3(p_0_in42_in[20]),
- .I4(polynomial[20]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[22]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \CRC[31]_i_92
- (.I0(polynomial[17]),
- .I1(CRC__6__0),
- .I2(\CRC_reg_n_0_[15] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in65_in[31]),
- .I5(polynomial[16]),
- .O(p_0_in40_in[18]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[31]_i_93
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[22]),
- .I3(p_0_in42_in[21]),
- .I4(polynomial[21]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[23]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[31]_i_94
- (.I0(polynomial[31]),
- .I1(p_0_in42_in[31]),
- .I2(polynomial[19]),
- .I3(p_0_in42_in[18]),
- .I4(polynomial[18]),
- .I5(CRC__6__0),
- .O(p_0_in38_in[20]));
- LUT5 #(
- .INIT(32'h28D7D728))
- \CRC[31]_i_95
- (.I0(polynomial[30]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[29] ),
- .I4(p_0_in65_in[29]),
- .O(p_0_in42_in[31]));
- LUT5 #(
- .INIT(32'h28D7D728))
- \CRC[31]_i_96
- (.I0(polynomial[29]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[28] ),
- .I4(p_0_in65_in[28]),
- .O(p_0_in42_in[30]));
- LUT5 #(
- .INIT(32'h28D7D728))
- \CRC[31]_i_97
- (.I0(polynomial[31]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[30] ),
- .I4(p_0_in65_in[30]),
- .O(CRC__6__0));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT2 #(
- .INIT(4'h6))
- \CRC[31]_i_98
- (.I0(p_0_in65_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .O(\CRC[31]_i_98_n_0 ));
- LUT5 #(
- .INIT(32'h28D7D728))
- \CRC[31]_i_99
- (.I0(polynomial[28]),
- .I1(p_0_in65_in[31]),
- .I2(\CRC_reg_n_0_[31] ),
- .I3(\CRC_reg_n_0_[27] ),
- .I4(p_0_in65_in[27]),
- .O(p_0_in42_in[29]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[3]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[3]),
- .I2(polynomial[3]),
- .I3(CRC__20__0),
- .I4(\CRC[3]_i_3_n_0 ),
- .I5(\CRC[3]_i_4_n_0 ),
- .O(CRC__28[3]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[3]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[2]),
- .I3(p_0_in18_in[1]),
- .I4(polynomial[1]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[3]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[3]),
- .I3(finalXOR[3]),
- .O(\CRC[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[3]_i_4
- (.I0(CRC63_in[3]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[3]),
- .I5(p_0_in46_in[3]),
- .O(\CRC[3]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h8778787800000000))
- \CRC[3]_i_5
- (.I0(polynomial[30]),
- .I1(CRC__15__0),
- .I2(p_0_in24_in[30]),
- .I3(CRC__16__0),
- .I4(polynomial[31]),
- .I5(polynomial[0]),
- .O(p_0_in18_in[1]));
- LUT6 #(
- .INIT(64'h8777788878887888))
- \CRC[3]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[2]),
- .I2(CRC__2__0),
- .I3(polynomial[0]),
- .I4(polynomial[1]),
- .I5(CRC__3__0),
- .O(p_0_in46_in[3]));
- LUT3 #(
- .INIT(8'h78))
- \CRC[3]_i_7
- (.I0(polynomial[31]),
- .I1(CRC__1__0),
- .I2(p_0_in54_in[31]),
- .O(CRC__2__0));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[3]_i_8
- (.I0(polynomial[30]),
- .I1(CRC__0__0),
- .I2(p_0_in58_in[29]),
- .I3(CRC__31),
- .I4(polynomial[29]),
- .O(p_0_in54_in[31]));
- LUT6 #(
- .INIT(64'h8788877778777888))
- \CRC[3]_i_9
- (.I0(polynomial[28]),
- .I1(\CRC[7]_i_11_n_0 ),
- .I2(initial_value[27]),
- .I3(firstWord_reg_n_0),
- .I4(\CRC_reg_n_0_[27] ),
- .I5(S_AXIS_TDATA[3]),
- .O(p_0_in58_in[29]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[4]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[4]),
- .I2(polynomial[4]),
- .I3(CRC__20__0),
- .I4(\CRC[4]_i_3_n_0 ),
- .I5(\CRC[4]_i_4_n_0 ),
- .O(CRC__28[4]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[4]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[3]),
- .I3(p_0_in18_in[2]),
- .I4(polynomial[2]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[4]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[4]),
- .I3(finalXOR[4]),
- .O(\CRC[4]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[4]_i_4
- (.I0(CRC63_in[4]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[4]),
- .I5(p_0_in46_in[4]),
- .O(\CRC[4]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h96FF6900C300C300))
- \CRC[4]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in24_in[30]),
- .I2(\CRC[4]_i_7_n_0 ),
- .I3(polynomial[1]),
- .I4(polynomial[0]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[2]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[4]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[3]),
- .I2(p_0_in50_in[2]),
- .I3(polynomial[2]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'h6999FFFF))
- \CRC[4]_i_7
- (.I0(CRC__13__0),
- .I1(p_0_in28_in[30]),
- .I2(CRC__14__0),
- .I3(polynomial[31]),
- .I4(polynomial[30]),
- .O(\CRC[4]_i_7_n_0 ));
- LUT4 #(
- .INIT(16'h7888))
- \CRC[4]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[1]),
- .I2(polynomial[0]),
- .I3(CRC__1__0),
- .O(p_0_in50_in[2]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[5]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[5]),
- .I2(polynomial[5]),
- .I3(CRC__20__0),
- .I4(\CRC[5]_i_3_n_0 ),
- .I5(\CRC[5]_i_4_n_0 ),
- .O(CRC__28[5]));
- LUT6 #(
- .INIT(64'h8788877778777888))
- \CRC[5]_i_10
- (.I0(polynomial[30]),
- .I1(\CRC[7]_i_11_n_0 ),
- .I2(initial_value[29]),
- .I3(firstWord_reg_n_0),
- .I4(\CRC_reg_n_0_[29] ),
- .I5(S_AXIS_TDATA[5]),
- .O(p_0_in58_in[31]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[5]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[4]),
- .I3(p_0_in18_in[3]),
- .I4(polynomial[3]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[5]));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[5]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[5]),
- .I3(finalXOR[5]),
- .O(\CRC[5]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[5]_i_4
- (.I0(CRC63_in[5]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[5]),
- .I5(p_0_in46_in[5]),
- .O(\CRC[5]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[5]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[2]),
- .I3(p_0_in22_in[1]),
- .I4(polynomial[1]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[3]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[5]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[4]),
- .I2(p_0_in50_in[3]),
- .I3(polynomial[3]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[5]));
- LUT6 #(
- .INIT(64'h8778787800000000))
- \CRC[5]_i_7
- (.I0(polynomial[30]),
- .I1(CRC__13__0),
- .I2(p_0_in28_in[30]),
- .I3(CRC__14__0),
- .I4(polynomial[31]),
- .I5(polynomial[0]),
- .O(p_0_in22_in[1]));
- LUT6 #(
- .INIT(64'h8777788878887888))
- \CRC[5]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[2]),
- .I2(CRC__0__0),
- .I3(polynomial[0]),
- .I4(polynomial[1]),
- .I5(CRC__1__0),
- .O(p_0_in50_in[3]));
- LUT3 #(
- .INIT(8'h78))
- \CRC[5]_i_9
- (.I0(polynomial[31]),
- .I1(CRC__31),
- .I2(p_0_in58_in[31]),
- .O(CRC__0__0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[6]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[6]),
- .I2(polynomial[6]),
- .I3(CRC__20__0),
- .I4(\CRC[6]_i_3_n_0 ),
- .I5(\CRC[6]_i_4_n_0 ),
- .O(CRC__28[6]));
- LUT6 #(
- .INIT(64'h8777788878887888))
- \CRC[6]_i_10
- (.I0(CRC__1__0),
- .I1(polynomial[2]),
- .I2(CRC__31),
- .I3(polynomial[0]),
- .I4(polynomial[1]),
- .I5(CRC__0__0),
- .O(p_0_in52_in[3]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[6]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[5]),
- .I3(p_0_in18_in[4]),
- .I4(polynomial[4]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[6]));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[6]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[6]),
- .I3(finalXOR[6]),
- .O(\CRC[6]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[6]_i_4
- (.I0(CRC63_in[6]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[6]),
- .I5(p_0_in46_in[6]),
- .O(\CRC[6]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[6]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[3]),
- .I3(p_0_in22_in[2]),
- .I4(polynomial[2]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[4]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[6]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[5]),
- .I2(p_0_in50_in[4]),
- .I3(polynomial[4]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[6]));
- LUT6 #(
- .INIT(64'h96FF6900C300C300))
- \CRC[6]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in28_in[30]),
- .I2(\CRC[6]_i_9_n_0 ),
- .I3(polynomial[1]),
- .I4(polynomial[0]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT3 #(
- .INIT(8'h78))
- \CRC[6]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[3]),
- .I2(p_0_in52_in[3]),
- .O(p_0_in50_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT5 #(
- .INIT(32'h6999FFFF))
- \CRC[6]_i_9
- (.I0(CRC__11__0),
- .I1(p_0_in32_in[30]),
- .I2(CRC__12__0),
- .I3(polynomial[31]),
- .I4(polynomial[30]),
- .O(\CRC[6]_i_9_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[7]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[7]),
- .I2(polynomial[7]),
- .I3(CRC__20__0),
- .I4(\CRC[7]_i_3_n_0 ),
- .I5(\CRC[7]_i_4_n_0 ),
- .O(CRC__28[7]));
- LUT6 #(
- .INIT(64'h8777788878887888))
- \CRC[7]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[2]),
- .I2(\CRC[7]_i_11_n_0 ),
- .I3(polynomial[0]),
- .I4(polynomial[1]),
- .I5(CRC__31),
- .O(p_0_in54_in[3]));
- LUT4 #(
- .INIT(16'h56A6))
- \CRC[7]_i_11
- (.I0(S_AXIS_TDATA[7]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(firstWord_reg_n_0),
- .I3(initial_value[31]),
- .O(\CRC[7]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[7]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[6]),
- .I3(p_0_in18_in[5]),
- .I4(polynomial[5]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[7]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[7]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[7]),
- .I3(finalXOR[7]),
- .O(\CRC[7]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[7]_i_4
- (.I0(CRC63_in[7]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[7]),
- .I5(p_0_in46_in[7]),
- .O(\CRC[7]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[7]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[4]),
- .I3(p_0_in22_in[3]),
- .I4(polynomial[3]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[5]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[7]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[6]),
- .I2(p_0_in50_in[5]),
- .I3(polynomial[5]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[7]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[7]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[2]),
- .I3(p_0_in26_in[1]),
- .I4(polynomial[1]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[3]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[7]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[4]),
- .I2(p_0_in54_in[3]),
- .I3(polynomial[3]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[5]));
- LUT6 #(
- .INIT(64'h8778787800000000))
- \CRC[7]_i_9
- (.I0(polynomial[30]),
- .I1(CRC__11__0),
- .I2(p_0_in32_in[30]),
- .I3(CRC__12__0),
- .I4(polynomial[31]),
- .I5(polynomial[0]),
- .O(p_0_in26_in[1]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[8]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[8]),
- .I2(polynomial[8]),
- .I3(CRC__20__0),
- .I4(\CRC[8]_i_3_n_0 ),
- .I5(\CRC[8]_i_4_n_0 ),
- .O(CRC__28[8]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[8]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[3]),
- .I2(p_0_in58_in[2]),
- .I3(polynomial[2]),
- .I4(CRC__31),
- .O(p_0_in54_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT5 #(
- .INIT(32'h6999FFFF))
- \CRC[8]_i_11
- (.I0(CRC__9__0),
- .I1(p_0_in36_in[30]),
- .I2(CRC__10__0),
- .I3(polynomial[31]),
- .I4(polynomial[30]),
- .O(\CRC[8]_i_11_n_0 ));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[8]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[1]),
- .I2(\CRC_reg_n_0_[0] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[0]),
- .O(p_0_in58_in[2]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[8]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[7]),
- .I3(p_0_in18_in[6]),
- .I4(polynomial[6]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[8]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[8]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[8]),
- .I3(finalXOR[8]),
- .O(\CRC[8]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[8]_i_4
- (.I0(CRC63_in[8]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[8]),
- .I5(p_0_in46_in[8]),
- .O(\CRC[8]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[8]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[5]),
- .I3(p_0_in22_in[4]),
- .I4(polynomial[4]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[6]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[8]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[7]),
- .I2(p_0_in50_in[6]),
- .I3(polynomial[6]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[8]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[8]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[3]),
- .I3(p_0_in26_in[2]),
- .I4(polynomial[2]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[4]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[8]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[5]),
- .I2(p_0_in54_in[4]),
- .I3(polynomial[4]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[6]));
- LUT6 #(
- .INIT(64'h96FF6900C300C300))
- \CRC[8]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in32_in[30]),
- .I2(\CRC[8]_i_11_n_0 ),
- .I3(polynomial[1]),
- .I4(polynomial[0]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[2]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF2888))
- \CRC[9]_i_1
- (.I0(\CRC[31]_i_3_n_0 ),
- .I1(p_0_in14_in[9]),
- .I2(polynomial[9]),
- .I3(CRC__20__0),
- .I4(\CRC[9]_i_3_n_0 ),
- .I5(\CRC[9]_i_4_n_0 ),
- .O(CRC__28[9]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[9]_i_10
- (.I0(CRC__0__0),
- .I1(polynomial[4]),
- .I2(p_0_in58_in[3]),
- .I3(polynomial[3]),
- .I4(CRC__31),
- .O(p_0_in54_in[5]));
- LUT6 #(
- .INIT(64'h8778787800000000))
- \CRC[9]_i_11
- (.I0(polynomial[30]),
- .I1(CRC__9__0),
- .I2(p_0_in36_in[30]),
- .I3(CRC__10__0),
- .I4(polynomial[31]),
- .I5(polynomial[0]),
- .O(p_0_in30_in[1]));
- LUT5 #(
- .INIT(32'h77788878))
- \CRC[9]_i_12
- (.I0(\CRC[7]_i_11_n_0 ),
- .I1(polynomial[2]),
- .I2(\CRC_reg_n_0_[1] ),
- .I3(firstWord_reg_n_0),
- .I4(initial_value[1]),
- .O(p_0_in58_in[3]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[9]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in18_in[31]),
- .I2(polynomial[8]),
- .I3(p_0_in18_in[7]),
- .I4(polynomial[7]),
- .I5(CRC__18__0),
- .O(p_0_in14_in[9]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h0880))
- \CRC[9]_i_3
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(CRC63_in[9]),
- .I3(finalXOR[9]),
- .O(\CRC[9]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888F8F8F8F888888))
- \CRC[9]_i_4
- (.I0(CRC63_in[9]),
- .I1(\CRC[31]_i_14_n_0 ),
- .I2(\CRC[31]_i_15_n_0 ),
- .I3(CRC__5__0),
- .I4(polynomial[9]),
- .I5(p_0_in46_in[9]),
- .O(\CRC[9]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[9]_i_5
- (.I0(polynomial[31]),
- .I1(p_0_in22_in[31]),
- .I2(polynomial[6]),
- .I3(p_0_in22_in[5]),
- .I4(polynomial[5]),
- .I5(CRC__16__0),
- .O(p_0_in18_in[7]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[9]_i_6
- (.I0(CRC__4__0),
- .I1(polynomial[8]),
- .I2(p_0_in50_in[7]),
- .I3(polynomial[7]),
- .I4(CRC__3__0),
- .O(p_0_in46_in[9]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[9]_i_7
- (.I0(polynomial[31]),
- .I1(p_0_in26_in[31]),
- .I2(polynomial[4]),
- .I3(p_0_in26_in[3]),
- .I4(polynomial[3]),
- .I5(CRC__14__0),
- .O(p_0_in22_in[5]));
- LUT5 #(
- .INIT(32'h87787878))
- \CRC[9]_i_8
- (.I0(CRC__2__0),
- .I1(polynomial[6]),
- .I2(p_0_in54_in[5]),
- .I3(polynomial[5]),
- .I4(CRC__1__0),
- .O(p_0_in50_in[7]));
- LUT6 #(
- .INIT(64'h609F9F603FC03FC0))
- \CRC[9]_i_9
- (.I0(polynomial[31]),
- .I1(p_0_in30_in[31]),
- .I2(polynomial[2]),
- .I3(p_0_in30_in[1]),
- .I4(polynomial[1]),
- .I5(CRC__12__0),
- .O(p_0_in26_in[3]));
- FDRE \CRC_reg[0]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[0]),
- .Q(\CRC_reg_n_0_[0] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[10]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[10]),
- .Q(\CRC_reg_n_0_[10] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[11]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[11]),
- .Q(\CRC_reg_n_0_[11] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[12]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[12]),
- .Q(\CRC_reg_n_0_[12] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[13]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[13]),
- .Q(\CRC_reg_n_0_[13] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[14]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[14]),
- .Q(\CRC_reg_n_0_[14] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[15]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[15]),
- .Q(\CRC_reg_n_0_[15] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[16]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[16]),
- .Q(\CRC_reg_n_0_[16] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[17]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[17]),
- .Q(\CRC_reg_n_0_[17] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[18]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[18]),
- .Q(\CRC_reg_n_0_[18] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[19]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[19]),
- .Q(\CRC_reg_n_0_[19] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[1]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[1]),
- .Q(\CRC_reg_n_0_[1] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[20]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[20]),
- .Q(\CRC_reg_n_0_[20] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[21]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[21]),
- .Q(\CRC_reg_n_0_[21] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[22]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[22]),
- .Q(\CRC_reg_n_0_[22] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[23]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[23]),
- .Q(\CRC_reg_n_0_[23] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[24]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[24]),
- .Q(\CRC_reg_n_0_[24] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[25]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[25]),
- .Q(\CRC_reg_n_0_[25] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[26]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[26]),
- .Q(\CRC_reg_n_0_[26] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[27]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[27]),
- .Q(\CRC_reg_n_0_[27] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[28]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[28]),
- .Q(\CRC_reg_n_0_[28] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[29]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[29]),
- .Q(\CRC_reg_n_0_[29] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[2]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[2]),
- .Q(\CRC_reg_n_0_[2] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[30]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[30]),
- .Q(\CRC_reg_n_0_[30] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[31]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[31]),
- .Q(\CRC_reg_n_0_[31] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[3]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[3]),
- .Q(\CRC_reg_n_0_[3] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[4]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[4]),
- .Q(\CRC_reg_n_0_[4] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[5]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[5]),
- .Q(\CRC_reg_n_0_[5] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[6]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[6]),
- .Q(\CRC_reg_n_0_[6] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[7]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[7]),
- .Q(\CRC_reg_n_0_[7] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[8]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[8]),
- .Q(\CRC_reg_n_0_[8] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- FDRE \CRC_reg[9]
- (.C(CLK),
- .CE(\CRC[31]_i_1_n_0 ),
- .D(CRC__28[9]),
- .Q(\CRC_reg_n_0_[9] ),
- .R(S_AXIS_TREADY_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'h330088F0))
- \FSM_sequential_state[0]_i_1
- (.I0(last_reg_n_0),
- .I1(M_AXIS_TREADY),
- .I2(S_AXIS_TVALID),
- .I3(state[1]),
- .I4(state[0]),
- .O(\FSM_sequential_state[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT4 #(
- .INIT(16'h3FB0))
- \FSM_sequential_state[1]_i_1
- (.I0(last_reg_n_0),
- .I1(M_AXIS_TREADY),
- .I2(state[1]),
- .I3(state[0]),
- .O(\FSM_sequential_state[1]_i_1_n_0 ));
- (* FSM_ENCODED_STATES = "second_half:01,provide_data:10,idle:00,checksum:11" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_state_reg[0]
- (.C(CLK),
- .CE(1'b1),
- .D(\FSM_sequential_state[0]_i_1_n_0 ),
- .Q(state[0]),
- .R(S_AXIS_TREADY_i_1_n_0));
- (* FSM_ENCODED_STATES = "second_half:01,provide_data:10,idle:00,checksum:11" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_state_reg[1]
- (.C(CLK),
- .CE(1'b1),
- .D(\FSM_sequential_state[1]_i_1_n_0 ),
- .Q(state[1]),
- .R(S_AXIS_TREADY_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'h6AFF6A00))
- \M_AXIS_TDATA[0]_i_1
- (.I0(finalXOR[0]),
- .I1(polynomial[0]),
- .I2(CRC__27__0),
- .I3(state[1]),
- .I4(byte_0__0[0]),
- .O(M_AXIS_TDATA0_in[0]));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT2 #(
- .INIT(4'h6))
- \M_AXIS_TDATA[0]_i_10
- (.I0(p_0_in62_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .O(\M_AXIS_TDATA[0]_i_10_n_0 ));
- LUT5 #(
- .INIT(32'h609F9F60))
- \M_AXIS_TDATA[0]_i_11
- (.I0(p_0_in62_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[25]),
- .I3(\CRC_reg_n_0_[24] ),
- .I4(p_0_in62_in[24]),
- .O(p_0_in10_in[26]));
- LUT6 #(
- .INIT(64'h827DD728DD227788))
- \M_AXIS_TDATA[0]_i_2
- (.I0(polynomial[31]),
- .I1(p_0_in4_in[30]),
- .I2(CRC__24__0),
- .I3(p_0_in2_in[30]),
- .I4(CRC__25__0),
- .I5(polynomial[30]),
- .O(CRC__27__0));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[0]_i_3
- (.I0(polynomial[29]),
- .I1(CRC__23__0),
- .I2(p_0_in8_in[28]),
- .I3(polynomial[28]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[0]_i_4
- (.I0(polynomial[31]),
- .I1(CRC__23__0),
- .I2(p_0_in8_in[30]),
- .I3(CRC__22__0),
- .I4(polynomial[30]),
- .O(CRC__24__0));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[0]_i_5
- (.I0(polynomial[29]),
- .I1(CRC__24__0),
- .I2(p_0_in6_in[28]),
- .I3(polynomial[28]),
- .I4(CRC__23__0),
- .O(p_0_in2_in[30]));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \M_AXIS_TDATA[0]_i_6
- (.I0(CRC__21__0),
- .I1(polynomial[27]),
- .I2(p_0_in62_in[25]),
- .I3(\CRC_reg_n_0_[25] ),
- .I4(polynomial[26]),
- .I5(\M_AXIS_TDATA[0]_i_10_n_0 ),
- .O(p_0_in8_in[28]));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \M_AXIS_TDATA[0]_i_7
- (.I0(polynomial[31]),
- .I1(CRC__21__0),
- .I2(p_0_in62_in[29]),
- .I3(\CRC_reg_n_0_[29] ),
- .I4(polynomial[30]),
- .I5(\M_AXIS_TDATA[0]_i_10_n_0 ),
- .O(CRC__22__0));
- LUT6 #(
- .INIT(64'h7887877887788778))
- \M_AXIS_TDATA[0]_i_8
- (.I0(CRC__21__0),
- .I1(polynomial[29]),
- .I2(p_0_in62_in[27]),
- .I3(\CRC_reg_n_0_[27] ),
- .I4(polynomial[28]),
- .I5(\M_AXIS_TDATA[0]_i_10_n_0 ),
- .O(p_0_in8_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[0]_i_9
- (.I0(CRC__22__0),
- .I1(polynomial[27]),
- .I2(p_0_in10_in[26]),
- .I3(polynomial[26]),
- .I4(CRC__21__0),
- .O(p_0_in6_in[28]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[10]_i_1
- (.I0(finalXOR[10]),
- .I1(CRC63_in[10]),
- .I2(state[1]),
- .I3(p_0_in65_in[26]),
- .O(M_AXIS_TDATA0_in[10]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[10]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[10]),
- .I2(p_0_in0_in[9]),
- .I3(polynomial[9]),
- .I4(CRC__26__0),
- .O(CRC63_in[10]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[10]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[8]),
- .I2(p_0_in4_in[7]),
- .I3(polynomial[7]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[9]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[10]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[6]),
- .I2(p_0_in8_in[5]),
- .I3(polynomial[5]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[7]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[10]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[4]),
- .I2(\CRC_reg_n_0_[2] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[3]),
- .O(p_0_in8_in[5]));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[11]_i_1
- (.I0(finalXOR[11]),
- .I1(CRC63_in[11]),
- .I2(state[1]),
- .I3(p_0_in65_in[27]),
- .O(M_AXIS_TDATA0_in[11]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[11]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[11]),
- .I2(p_0_in0_in[10]),
- .I3(polynomial[10]),
- .I4(CRC__26__0),
- .O(CRC63_in[11]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[11]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[9]),
- .I2(p_0_in4_in[8]),
- .I3(polynomial[8]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[10]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[11]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[7]),
- .I2(p_0_in8_in[6]),
- .I3(polynomial[6]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[8]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[11]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[5]),
- .I2(\CRC_reg_n_0_[3] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[4]),
- .O(p_0_in8_in[6]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[12]_i_1
- (.I0(finalXOR[12]),
- .I1(CRC63_in[12]),
- .I2(state[1]),
- .I3(p_0_in65_in[28]),
- .O(M_AXIS_TDATA0_in[12]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[12]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[12]),
- .I2(p_0_in0_in[11]),
- .I3(polynomial[11]),
- .I4(CRC__26__0),
- .O(CRC63_in[12]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[12]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[10]),
- .I2(p_0_in4_in[9]),
- .I3(polynomial[9]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[11]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[12]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[8]),
- .I2(p_0_in8_in[7]),
- .I3(polynomial[7]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[9]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[12]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[6]),
- .I2(\CRC_reg_n_0_[4] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[5]),
- .O(p_0_in8_in[7]));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[13]_i_1
- (.I0(finalXOR[13]),
- .I1(CRC63_in[13]),
- .I2(state[1]),
- .I3(p_0_in65_in[29]),
- .O(M_AXIS_TDATA0_in[13]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[13]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[13]),
- .I2(p_0_in0_in[12]),
- .I3(polynomial[12]),
- .I4(CRC__26__0),
- .O(CRC63_in[13]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[13]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[11]),
- .I2(p_0_in4_in[10]),
- .I3(polynomial[10]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[12]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[13]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[9]),
- .I2(p_0_in8_in[8]),
- .I3(polynomial[8]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[10]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[13]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[7]),
- .I2(\CRC_reg_n_0_[5] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[6]),
- .O(p_0_in8_in[8]));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[14]_i_1
- (.I0(finalXOR[14]),
- .I1(CRC63_in[14]),
- .I2(state[1]),
- .I3(p_0_in65_in[30]),
- .O(M_AXIS_TDATA0_in[14]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[14]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[14]),
- .I2(p_0_in0_in[13]),
- .I3(polynomial[13]),
- .I4(CRC__26__0),
- .O(CRC63_in[14]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[14]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[12]),
- .I2(p_0_in4_in[11]),
- .I3(polynomial[11]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[13]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[14]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[10]),
- .I2(p_0_in8_in[9]),
- .I3(polynomial[9]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[11]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[14]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[8]),
- .I2(\CRC_reg_n_0_[6] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[7]),
- .O(p_0_in8_in[9]));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[15]_i_1
- (.I0(finalXOR[15]),
- .I1(CRC63_in[15]),
- .I2(state[1]),
- .I3(p_0_in65_in[31]),
- .O(M_AXIS_TDATA0_in[15]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[15]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[15]),
- .I2(p_0_in0_in[14]),
- .I3(polynomial[14]),
- .I4(CRC__26__0),
- .O(CRC63_in[15]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[15]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[13]),
- .I2(p_0_in4_in[12]),
- .I3(polynomial[12]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[14]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[15]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[11]),
- .I2(p_0_in8_in[10]),
- .I3(polynomial[10]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[12]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[15]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[9]),
- .I2(\CRC_reg_n_0_[7] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[8]),
- .O(p_0_in8_in[10]));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[16]_i_1
- (.I0(finalXOR[16]),
- .I1(CRC63_in[16]),
- .I2(state[1]),
- .I3(p_0_in65_in[16]),
- .O(M_AXIS_TDATA0_in[16]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[16]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[16]),
- .I2(p_0_in0_in[15]),
- .I3(polynomial[15]),
- .I4(CRC__26__0),
- .O(CRC63_in[16]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[16]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[14]),
- .I2(p_0_in4_in[13]),
- .I3(polynomial[13]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[15]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[16]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[12]),
- .I2(p_0_in8_in[11]),
- .I3(polynomial[11]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[13]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[16]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[10]),
- .I2(\CRC_reg_n_0_[8] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[9]),
- .O(p_0_in8_in[11]));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[17]_i_1
- (.I0(finalXOR[17]),
- .I1(CRC63_in[17]),
- .I2(state[1]),
- .I3(p_0_in65_in[17]),
- .O(M_AXIS_TDATA0_in[17]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[17]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[17]),
- .I2(p_0_in0_in[16]),
- .I3(polynomial[16]),
- .I4(CRC__26__0),
- .O(CRC63_in[17]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[17]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[15]),
- .I2(p_0_in4_in[14]),
- .I3(polynomial[14]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[16]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[17]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[13]),
- .I2(p_0_in8_in[12]),
- .I3(polynomial[12]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[14]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[17]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[11]),
- .I2(\CRC_reg_n_0_[9] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[10]),
- .O(p_0_in8_in[12]));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[18]_i_1
- (.I0(finalXOR[18]),
- .I1(CRC63_in[18]),
- .I2(state[1]),
- .I3(p_0_in65_in[18]),
- .O(M_AXIS_TDATA0_in[18]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[18]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[18]),
- .I2(p_0_in0_in[17]),
- .I3(polynomial[17]),
- .I4(CRC__26__0),
- .O(CRC63_in[18]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[18]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[16]),
- .I2(p_0_in4_in[15]),
- .I3(polynomial[15]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[17]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[18]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[14]),
- .I2(p_0_in8_in[13]),
- .I3(polynomial[13]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[15]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[18]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[12]),
- .I2(\CRC_reg_n_0_[10] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[11]),
- .O(p_0_in8_in[13]));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[19]_i_1
- (.I0(finalXOR[19]),
- .I1(CRC63_in[19]),
- .I2(state[1]),
- .I3(p_0_in65_in[19]),
- .O(M_AXIS_TDATA0_in[19]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[19]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[19]),
- .I2(p_0_in0_in[18]),
- .I3(polynomial[18]),
- .I4(CRC__26__0),
- .O(CRC63_in[19]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[19]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[17]),
- .I2(p_0_in4_in[16]),
- .I3(polynomial[16]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[18]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[19]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[15]),
- .I2(p_0_in8_in[14]),
- .I3(polynomial[14]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[16]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[19]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[13]),
- .I2(\CRC_reg_n_0_[11] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[12]),
- .O(p_0_in8_in[14]));
- LUT3 #(
- .INIT(8'hB8))
- \M_AXIS_TDATA[1]_i_1
- (.I0(CRC064_out[1]),
- .I1(state[1]),
- .I2(byte_0__0[1]),
- .O(M_AXIS_TDATA0_in[1]));
- LUT5 #(
- .INIT(32'h956A6A6A))
- \M_AXIS_TDATA[1]_i_2
- (.I0(finalXOR[1]),
- .I1(CRC__26__0),
- .I2(polynomial[0]),
- .I3(polynomial[1]),
- .I4(CRC__27__0),
- .O(CRC064_out[1]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[20]_i_1
- (.I0(finalXOR[20]),
- .I1(CRC63_in[20]),
- .I2(state[1]),
- .I3(p_0_in65_in[20]),
- .O(M_AXIS_TDATA0_in[20]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[20]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[20]),
- .I2(p_0_in0_in[19]),
- .I3(polynomial[19]),
- .I4(CRC__26__0),
- .O(CRC63_in[20]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[20]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[18]),
- .I2(p_0_in4_in[17]),
- .I3(polynomial[17]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[19]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[20]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[16]),
- .I2(p_0_in8_in[15]),
- .I3(polynomial[15]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[17]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[20]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[14]),
- .I2(\CRC_reg_n_0_[12] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[13]),
- .O(p_0_in8_in[15]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[21]_i_1
- (.I0(finalXOR[21]),
- .I1(CRC63_in[21]),
- .I2(state[1]),
- .I3(p_0_in65_in[21]),
- .O(M_AXIS_TDATA0_in[21]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[21]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[21]),
- .I2(p_0_in0_in[20]),
- .I3(polynomial[20]),
- .I4(CRC__26__0),
- .O(CRC63_in[21]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[21]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[19]),
- .I2(p_0_in4_in[18]),
- .I3(polynomial[18]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[20]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[21]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[17]),
- .I2(p_0_in8_in[16]),
- .I3(polynomial[16]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[18]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[21]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[15]),
- .I2(\CRC_reg_n_0_[13] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[14]),
- .O(p_0_in8_in[16]));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[22]_i_1
- (.I0(finalXOR[22]),
- .I1(CRC63_in[22]),
- .I2(state[1]),
- .I3(p_0_in65_in[22]),
- .O(M_AXIS_TDATA0_in[22]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[22]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[22]),
- .I2(p_0_in0_in[21]),
- .I3(polynomial[21]),
- .I4(CRC__26__0),
- .O(CRC63_in[22]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[22]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[20]),
- .I2(p_0_in4_in[19]),
- .I3(polynomial[19]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[21]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[22]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[18]),
- .I2(p_0_in8_in[17]),
- .I3(polynomial[17]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[19]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[22]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[16]),
- .I2(\CRC_reg_n_0_[14] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[15]),
- .O(p_0_in8_in[17]));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[23]_i_1
- (.I0(finalXOR[23]),
- .I1(CRC63_in[23]),
- .I2(state[1]),
- .I3(p_0_in65_in[23]),
- .O(M_AXIS_TDATA0_in[23]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[23]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[23]),
- .I2(p_0_in0_in[22]),
- .I3(polynomial[22]),
- .I4(CRC__26__0),
- .O(CRC63_in[23]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[23]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[21]),
- .I2(p_0_in4_in[20]),
- .I3(polynomial[20]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[22]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[23]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[19]),
- .I2(p_0_in8_in[18]),
- .I3(polynomial[18]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[20]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[23]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[17]),
- .I2(\CRC_reg_n_0_[15] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[16]),
- .O(p_0_in8_in[18]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[24]_i_1
- (.I0(finalXOR[24]),
- .I1(CRC63_in[24]),
- .I2(state[1]),
- .I3(p_0_in62_in[24]),
- .O(M_AXIS_TDATA0_in[24]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[24]_i_2
- (.I0(polynomial[24]),
- .I1(CRC__27__0),
- .I2(p_0_in0_in[23]),
- .I3(polynomial[23]),
- .I4(CRC__26__0),
- .O(CRC63_in[24]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[24]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[22]),
- .I2(p_0_in4_in[21]),
- .I3(polynomial[21]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[23]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[24]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[20]),
- .I2(p_0_in8_in[19]),
- .I3(polynomial[19]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[21]));
- LUT6 #(
- .INIT(64'h7878877887787878))
- \M_AXIS_TDATA[24]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[18]),
- .I2(\CRC_reg_n_0_[16] ),
- .I3(polynomial[17]),
- .I4(\CRC_reg_n_0_[31] ),
- .I5(p_0_in62_in[31]),
- .O(p_0_in8_in[19]));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[25]_i_1
- (.I0(finalXOR[25]),
- .I1(CRC63_in[25]),
- .I2(state[1]),
- .I3(p_0_in62_in[25]),
- .O(M_AXIS_TDATA0_in[25]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[25]_i_2
- (.I0(polynomial[25]),
- .I1(CRC__27__0),
- .I2(p_0_in0_in[24]),
- .I3(CRC__26__0),
- .I4(polynomial[24]),
- .O(CRC63_in[25]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[25]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[23]),
- .I2(p_0_in4_in[22]),
- .I3(polynomial[22]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[24]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[25]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[21]),
- .I2(p_0_in8_in[20]),
- .I3(polynomial[20]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[22]));
- LUT6 #(
- .INIT(64'h7878877887787878))
- \M_AXIS_TDATA[25]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[19]),
- .I2(\CRC_reg_n_0_[17] ),
- .I3(polynomial[18]),
- .I4(\CRC_reg_n_0_[31] ),
- .I5(p_0_in62_in[31]),
- .O(p_0_in8_in[20]));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[26]_i_1
- (.I0(finalXOR[26]),
- .I1(CRC63_in[26]),
- .I2(state[1]),
- .I3(p_0_in62_in[26]),
- .O(M_AXIS_TDATA0_in[26]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[26]_i_2
- (.I0(polynomial[26]),
- .I1(CRC__27__0),
- .I2(p_0_in0_in[25]),
- .I3(CRC__26__0),
- .I4(polynomial[25]),
- .O(CRC63_in[26]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[26]_i_3
- (.I0(polynomial[24]),
- .I1(CRC__25__0),
- .I2(p_0_in4_in[23]),
- .I3(polynomial[23]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[25]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[26]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[22]),
- .I2(p_0_in8_in[21]),
- .I3(polynomial[21]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[23]));
- LUT6 #(
- .INIT(64'h7878877887787878))
- \M_AXIS_TDATA[26]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[20]),
- .I2(\CRC_reg_n_0_[18] ),
- .I3(polynomial[19]),
- .I4(\CRC_reg_n_0_[31] ),
- .I5(p_0_in62_in[31]),
- .O(p_0_in8_in[21]));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[27]_i_1
- (.I0(finalXOR[27]),
- .I1(CRC63_in[27]),
- .I2(state[1]),
- .I3(p_0_in62_in[27]),
- .O(M_AXIS_TDATA0_in[27]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[27]_i_2
- (.I0(polynomial[27]),
- .I1(CRC__27__0),
- .I2(p_0_in0_in[26]),
- .I3(CRC__26__0),
- .I4(polynomial[26]),
- .O(CRC63_in[27]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[27]_i_3
- (.I0(polynomial[25]),
- .I1(CRC__25__0),
- .I2(p_0_in4_in[24]),
- .I3(CRC__24__0),
- .I4(polynomial[24]),
- .O(p_0_in0_in[26]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[27]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[23]),
- .I2(p_0_in8_in[22]),
- .I3(polynomial[22]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[24]));
- LUT6 #(
- .INIT(64'h7878877887787878))
- \M_AXIS_TDATA[27]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[21]),
- .I2(\CRC_reg_n_0_[19] ),
- .I3(polynomial[20]),
- .I4(\CRC_reg_n_0_[31] ),
- .I5(p_0_in62_in[31]),
- .O(p_0_in8_in[22]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[28]_i_1
- (.I0(finalXOR[28]),
- .I1(CRC63_in[28]),
- .I2(state[1]),
- .I3(p_0_in62_in[28]),
- .O(M_AXIS_TDATA0_in[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[28]_i_2
- (.I0(polynomial[28]),
- .I1(CRC__27__0),
- .I2(p_0_in0_in[27]),
- .I3(CRC__26__0),
- .I4(polynomial[27]),
- .O(CRC63_in[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[28]_i_3
- (.I0(polynomial[26]),
- .I1(CRC__25__0),
- .I2(p_0_in4_in[25]),
- .I3(CRC__24__0),
- .I4(polynomial[25]),
- .O(p_0_in0_in[27]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[28]_i_4
- (.I0(polynomial[24]),
- .I1(CRC__23__0),
- .I2(p_0_in8_in[23]),
- .I3(polynomial[23]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[25]));
- LUT6 #(
- .INIT(64'h7878877887787878))
- \M_AXIS_TDATA[28]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[22]),
- .I2(\CRC_reg_n_0_[20] ),
- .I3(polynomial[21]),
- .I4(\CRC_reg_n_0_[31] ),
- .I5(p_0_in62_in[31]),
- .O(p_0_in8_in[23]));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[29]_i_1
- (.I0(finalXOR[29]),
- .I1(CRC63_in[29]),
- .I2(state[1]),
- .I3(p_0_in62_in[29]),
- .O(M_AXIS_TDATA0_in[29]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[29]_i_2
- (.I0(polynomial[29]),
- .I1(CRC__27__0),
- .I2(p_0_in0_in[28]),
- .I3(CRC__26__0),
- .I4(polynomial[28]),
- .O(CRC63_in[29]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[29]_i_3
- (.I0(polynomial[27]),
- .I1(CRC__25__0),
- .I2(p_0_in4_in[26]),
- .I3(CRC__24__0),
- .I4(polynomial[26]),
- .O(p_0_in0_in[28]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[29]_i_4
- (.I0(polynomial[25]),
- .I1(CRC__23__0),
- .I2(p_0_in8_in[24]),
- .I3(CRC__22__0),
- .I4(polynomial[24]),
- .O(p_0_in4_in[26]));
- LUT6 #(
- .INIT(64'h7878877887787878))
- \M_AXIS_TDATA[29]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[23]),
- .I2(\CRC_reg_n_0_[21] ),
- .I3(polynomial[22]),
- .I4(\CRC_reg_n_0_[31] ),
- .I5(p_0_in62_in[31]),
- .O(p_0_in8_in[24]));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[2]_i_1
- (.I0(finalXOR[2]),
- .I1(CRC63_in[2]),
- .I2(state[1]),
- .I3(byte_0__0[2]),
- .O(M_AXIS_TDATA0_in[2]));
- LUT6 #(
- .INIT(64'h8777788878887888))
- \M_AXIS_TDATA[2]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[2]),
- .I2(CRC__25__0),
- .I3(polynomial[0]),
- .I4(polynomial[1]),
- .I5(CRC__26__0),
- .O(CRC63_in[2]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[2]_i_3
- (.I0(polynomial[31]),
- .I1(CRC__24__0),
- .I2(p_0_in6_in[30]),
- .I3(CRC__23__0),
- .I4(polynomial[30]),
- .O(CRC__25__0));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[2]_i_4
- (.I0(CRC__22__0),
- .I1(polynomial[29]),
- .I2(p_0_in10_in[28]),
- .I3(polynomial[28]),
- .I4(CRC__21__0),
- .O(p_0_in6_in[30]));
- LUT5 #(
- .INIT(32'h609F9F60))
- \M_AXIS_TDATA[2]_i_5
- (.I0(p_0_in62_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[27]),
- .I3(\CRC_reg_n_0_[26] ),
- .I4(p_0_in62_in[26]),
- .O(p_0_in10_in[28]));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[30]_i_1
- (.I0(finalXOR[30]),
- .I1(CRC63_in[30]),
- .I2(state[1]),
- .I3(p_0_in62_in[30]),
- .O(M_AXIS_TDATA0_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[30]_i_2
- (.I0(polynomial[30]),
- .I1(CRC__27__0),
- .I2(p_0_in0_in[29]),
- .I3(CRC__26__0),
- .I4(polynomial[29]),
- .O(CRC63_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[30]_i_3
- (.I0(polynomial[28]),
- .I1(CRC__25__0),
- .I2(p_0_in4_in[27]),
- .I3(CRC__24__0),
- .I4(polynomial[27]),
- .O(p_0_in0_in[29]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[30]_i_4
- (.I0(polynomial[26]),
- .I1(CRC__23__0),
- .I2(p_0_in8_in[25]),
- .I3(CRC__22__0),
- .I4(polynomial[25]),
- .O(p_0_in4_in[27]));
- LUT6 #(
- .INIT(64'h7878877887787878))
- \M_AXIS_TDATA[30]_i_5
- (.I0(polynomial[24]),
- .I1(CRC__21__0),
- .I2(\CRC_reg_n_0_[22] ),
- .I3(polynomial[23]),
- .I4(\CRC_reg_n_0_[31] ),
- .I5(p_0_in62_in[31]),
- .O(p_0_in8_in[25]));
- LUT5 #(
- .INIT(32'h0080F000))
- \M_AXIS_TDATA[31]_i_1
- (.I0(M_AXIS_TREADY),
- .I1(last_reg_n_0),
- .I2(RESETN),
- .I3(state[0]),
- .I4(state[1]),
- .O(\M_AXIS_TDATA[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[31]_i_2
- (.I0(finalXOR[31]),
- .I1(CRC63_in[31]),
- .I2(state[1]),
- .I3(p_0_in62_in[31]),
- .O(M_AXIS_TDATA0_in[31]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[31]_i_3
- (.I0(polynomial[31]),
- .I1(CRC__27__0),
- .I2(p_0_in0_in[30]),
- .I3(CRC__26__0),
- .I4(polynomial[30]),
- .O(CRC63_in[31]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[31]_i_4
- (.I0(polynomial[29]),
- .I1(CRC__25__0),
- .I2(p_0_in4_in[28]),
- .I3(CRC__24__0),
- .I4(polynomial[28]),
- .O(p_0_in0_in[30]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[31]_i_5
- (.I0(polynomial[31]),
- .I1(CRC__25__0),
- .I2(p_0_in4_in[30]),
- .I3(CRC__24__0),
- .I4(polynomial[30]),
- .O(CRC__26__0));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[31]_i_6
- (.I0(polynomial[27]),
- .I1(CRC__23__0),
- .I2(p_0_in8_in[26]),
- .I3(CRC__22__0),
- .I4(polynomial[26]),
- .O(p_0_in4_in[28]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[31]_i_7
- (.I0(polynomial[25]),
- .I1(CRC__21__0),
- .I2(\CRC_reg_n_0_[23] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[24]),
- .O(p_0_in8_in[26]));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[3]_i_1
- (.I0(finalXOR[3]),
- .I1(CRC63_in[3]),
- .I2(state[1]),
- .I3(byte_0__0[3]),
- .O(M_AXIS_TDATA0_in[3]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[3]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[3]),
- .I2(p_0_in0_in[2]),
- .I3(polynomial[2]),
- .I4(CRC__26__0),
- .O(CRC63_in[3]));
- LUT4 #(
- .INIT(16'h7888))
- \M_AXIS_TDATA[3]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[1]),
- .I2(polynomial[0]),
- .I3(CRC__24__0),
- .O(p_0_in0_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[4]_i_1
- (.I0(finalXOR[4]),
- .I1(CRC63_in[4]),
- .I2(state[1]),
- .I3(byte_0__0[4]),
- .O(M_AXIS_TDATA0_in[4]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[4]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[4]),
- .I2(p_0_in0_in[3]),
- .I3(polynomial[3]),
- .I4(CRC__26__0),
- .O(CRC63_in[4]));
- LUT6 #(
- .INIT(64'h8777788878887888))
- \M_AXIS_TDATA[4]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[2]),
- .I2(CRC__23__0),
- .I3(polynomial[0]),
- .I4(polynomial[1]),
- .I5(CRC__24__0),
- .O(p_0_in0_in[3]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[4]_i_4
- (.I0(polynomial[31]),
- .I1(CRC__22__0),
- .I2(p_0_in10_in[30]),
- .I3(polynomial[30]),
- .I4(CRC__21__0),
- .O(CRC__23__0));
- LUT5 #(
- .INIT(32'h609F9F60))
- \M_AXIS_TDATA[4]_i_5
- (.I0(p_0_in62_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[29]),
- .I3(\CRC_reg_n_0_[28] ),
- .I4(p_0_in62_in[28]),
- .O(p_0_in10_in[30]));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[5]_i_1
- (.I0(finalXOR[5]),
- .I1(CRC63_in[5]),
- .I2(state[1]),
- .I3(byte_0__0[5]),
- .O(M_AXIS_TDATA0_in[5]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[5]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[5]),
- .I2(p_0_in0_in[4]),
- .I3(polynomial[4]),
- .I4(CRC__26__0),
- .O(CRC63_in[5]));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT3 #(
- .INIT(8'h78))
- \M_AXIS_TDATA[5]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[3]),
- .I2(p_0_in2_in[3]),
- .O(p_0_in0_in[4]));
- LUT6 #(
- .INIT(64'h8777788878887888))
- \M_AXIS_TDATA[5]_i_4
- (.I0(CRC__24__0),
- .I1(polynomial[2]),
- .I2(CRC__22__0),
- .I3(polynomial[0]),
- .I4(polynomial[1]),
- .I5(CRC__23__0),
- .O(p_0_in2_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[6]_i_1
- (.I0(finalXOR[6]),
- .I1(CRC63_in[6]),
- .I2(state[1]),
- .I3(byte_0__0[6]),
- .O(M_AXIS_TDATA0_in[6]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[6]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[6]),
- .I2(p_0_in0_in[5]),
- .I3(polynomial[5]),
- .I4(CRC__26__0),
- .O(CRC63_in[6]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[6]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[4]),
- .I2(p_0_in4_in[3]),
- .I3(polynomial[3]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[5]));
- LUT6 #(
- .INIT(64'h8777788878887888))
- \M_AXIS_TDATA[6]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[2]),
- .I2(CRC__21__0),
- .I3(polynomial[0]),
- .I4(polynomial[1]),
- .I5(CRC__22__0),
- .O(p_0_in4_in[3]));
- LUT5 #(
- .INIT(32'h609F9F60))
- \M_AXIS_TDATA[6]_i_5
- (.I0(p_0_in62_in[31]),
- .I1(\CRC_reg_n_0_[31] ),
- .I2(polynomial[31]),
- .I3(\CRC_reg_n_0_[30] ),
- .I4(p_0_in62_in[30]),
- .O(CRC__21__0));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[7]_i_1
- (.I0(finalXOR[7]),
- .I1(CRC63_in[7]),
- .I2(state[1]),
- .I3(byte_0__0[7]),
- .O(M_AXIS_TDATA0_in[7]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[7]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[7]),
- .I2(p_0_in0_in[6]),
- .I3(polynomial[6]),
- .I4(CRC__26__0),
- .O(CRC63_in[7]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[7]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[5]),
- .I2(p_0_in4_in[4]),
- .I3(polynomial[4]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[6]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[7]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[3]),
- .I2(p_0_in8_in[2]),
- .I3(polynomial[2]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h88787888))
- \M_AXIS_TDATA[7]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[1]),
- .I2(polynomial[0]),
- .I3(p_0_in62_in[31]),
- .I4(\CRC_reg_n_0_[31] ),
- .O(p_0_in8_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[8]_i_1
- (.I0(finalXOR[8]),
- .I1(CRC63_in[8]),
- .I2(state[1]),
- .I3(p_0_in65_in[24]),
- .O(M_AXIS_TDATA0_in[8]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[8]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[8]),
- .I2(p_0_in0_in[7]),
- .I3(polynomial[7]),
- .I4(CRC__26__0),
- .O(CRC63_in[8]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[8]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[6]),
- .I2(p_0_in4_in[5]),
- .I3(polynomial[5]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[7]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[8]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[4]),
- .I2(p_0_in8_in[3]),
- .I3(polynomial[3]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[5]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[8]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[2]),
- .I2(\CRC_reg_n_0_[0] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[1]),
- .O(p_0_in8_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h6F60))
- \M_AXIS_TDATA[9]_i_1
- (.I0(finalXOR[9]),
- .I1(CRC63_in[9]),
- .I2(state[1]),
- .I3(p_0_in65_in[25]),
- .O(M_AXIS_TDATA0_in[9]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[9]_i_2
- (.I0(CRC__27__0),
- .I1(polynomial[9]),
- .I2(p_0_in0_in[8]),
- .I3(polynomial[8]),
- .I4(CRC__26__0),
- .O(CRC63_in[9]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[9]_i_3
- (.I0(CRC__25__0),
- .I1(polynomial[7]),
- .I2(p_0_in4_in[6]),
- .I3(polynomial[6]),
- .I4(CRC__24__0),
- .O(p_0_in0_in[8]));
- LUT5 #(
- .INIT(32'h87787878))
- \M_AXIS_TDATA[9]_i_4
- (.I0(CRC__23__0),
- .I1(polynomial[5]),
- .I2(p_0_in8_in[4]),
- .I3(polynomial[4]),
- .I4(CRC__22__0),
- .O(p_0_in4_in[6]));
- LUT6 #(
- .INIT(64'h7887877878787878))
- \M_AXIS_TDATA[9]_i_5
- (.I0(CRC__21__0),
- .I1(polynomial[3]),
- .I2(\CRC_reg_n_0_[1] ),
- .I3(\CRC_reg_n_0_[31] ),
- .I4(p_0_in62_in[31]),
- .I5(polynomial[2]),
- .O(p_0_in8_in[4]));
- FDRE \M_AXIS_TDATA_reg[0]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[0]),
- .Q(M_AXIS_TDATA[0]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[10]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[10]),
- .Q(M_AXIS_TDATA[10]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[11]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[11]),
- .Q(M_AXIS_TDATA[11]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[12]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[12]),
- .Q(M_AXIS_TDATA[12]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[13]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[13]),
- .Q(M_AXIS_TDATA[13]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[14]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[14]),
- .Q(M_AXIS_TDATA[14]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[15]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[15]),
- .Q(M_AXIS_TDATA[15]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[16]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[16]),
- .Q(M_AXIS_TDATA[16]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[17]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[17]),
- .Q(M_AXIS_TDATA[17]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[18]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[18]),
- .Q(M_AXIS_TDATA[18]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[19]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[19]),
- .Q(M_AXIS_TDATA[19]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[1]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[1]),
- .Q(M_AXIS_TDATA[1]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[20]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[20]),
- .Q(M_AXIS_TDATA[20]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[21]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[21]),
- .Q(M_AXIS_TDATA[21]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[22]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[22]),
- .Q(M_AXIS_TDATA[22]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[23]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[23]),
- .Q(M_AXIS_TDATA[23]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[24]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[24]),
- .Q(M_AXIS_TDATA[24]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[25]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[25]),
- .Q(M_AXIS_TDATA[25]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[26]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[26]),
- .Q(M_AXIS_TDATA[26]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[27]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[27]),
- .Q(M_AXIS_TDATA[27]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[28]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[28]),
- .Q(M_AXIS_TDATA[28]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[29]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[29]),
- .Q(M_AXIS_TDATA[29]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[2]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[2]),
- .Q(M_AXIS_TDATA[2]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[30]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[30]),
- .Q(M_AXIS_TDATA[30]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[31]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[31]),
- .Q(M_AXIS_TDATA[31]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[3]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[3]),
- .Q(M_AXIS_TDATA[3]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[4]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[4]),
- .Q(M_AXIS_TDATA[4]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[5]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[5]),
- .Q(M_AXIS_TDATA[5]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[6]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[6]),
- .Q(M_AXIS_TDATA[6]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[7]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[7]),
- .Q(M_AXIS_TDATA[7]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[8]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[8]),
- .Q(M_AXIS_TDATA[8]),
- .R(1'b0));
- FDRE \M_AXIS_TDATA_reg[9]
- (.C(CLK),
- .CE(\M_AXIS_TDATA[31]_i_1_n_0 ),
- .D(M_AXIS_TDATA0_in[9]),
- .Q(M_AXIS_TDATA[9]),
- .R(1'b0));
- LUT5 #(
- .INIT(32'h77FF4000))
- M_AXIS_TLAST_i_1
- (.I0(state[0]),
- .I1(M_AXIS_TREADY),
- .I2(last_reg_n_0),
- .I3(state[1]),
- .I4(M_AXIS_TLAST),
- .O(M_AXIS_TLAST_i_1_n_0));
- FDRE M_AXIS_TLAST_reg
- (.C(CLK),
- .CE(1'b1),
- .D(M_AXIS_TLAST_i_1_n_0),
- .Q(M_AXIS_TLAST),
- .R(S_AXIS_TREADY_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT5 #(
- .INIT(32'h5FDF5500))
- M_AXIS_TVALID_i_1
- (.I0(state[1]),
- .I1(last_reg_n_0),
- .I2(M_AXIS_TREADY),
- .I3(state[0]),
- .I4(M_AXIS_TVALID),
- .O(M_AXIS_TVALID_i_1_n_0));
- FDRE M_AXIS_TVALID_reg
- (.C(CLK),
- .CE(1'b1),
- .D(M_AXIS_TVALID_i_1_n_0),
- .Q(M_AXIS_TVALID),
- .R(S_AXIS_TREADY_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- S_AXIS_TREADY_i_1
- (.I0(RESETN),
- .O(S_AXIS_TREADY_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFF5FFF5F3000000))
- S_AXIS_TREADY_i_2
- (.I0(S_AXIS_TVALID),
- .I1(last_reg_n_0),
- .I2(state[0]),
- .I3(state[1]),
- .I4(M_AXIS_TREADY),
- .I5(S_AXIS_TREADY),
- .O(S_AXIS_TREADY_i_2_n_0));
- FDSE S_AXIS_TREADY_reg
- (.C(CLK),
- .CE(1'b1),
- .D(S_AXIS_TREADY_i_2_n_0),
- .Q(S_AXIS_TREADY),
- .S(S_AXIS_TREADY_i_1_n_0));
- FDRE \byte_0_reg[0]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[0]),
- .Q(byte_0__0[0]),
- .R(1'b0));
- FDRE \byte_0_reg[1]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[1]),
- .Q(byte_0__0[1]),
- .R(1'b0));
- FDRE \byte_0_reg[2]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[2]),
- .Q(byte_0__0[2]),
- .R(1'b0));
- FDRE \byte_0_reg[3]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[3]),
- .Q(byte_0__0[3]),
- .R(1'b0));
- FDRE \byte_0_reg[4]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[4]),
- .Q(byte_0__0[4]),
- .R(1'b0));
- FDRE \byte_0_reg[5]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[5]),
- .Q(byte_0__0[5]),
- .R(1'b0));
- FDRE \byte_0_reg[6]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[6]),
- .Q(byte_0__0[6]),
- .R(1'b0));
- FDRE \byte_0_reg[7]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[7]),
- .Q(byte_0__0[7]),
- .R(1'b0));
- LUT4 #(
- .INIT(16'h0008))
- \byte_1[7]_i_1
- (.I0(RESETN),
- .I1(S_AXIS_TVALID),
- .I2(state[0]),
- .I3(state[1]),
- .O(last3_out));
- FDRE \byte_1_reg[0]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[8]),
- .Q(p_0_in65_in[24]),
- .R(1'b0));
- FDRE \byte_1_reg[1]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[9]),
- .Q(p_0_in65_in[25]),
- .R(1'b0));
- FDRE \byte_1_reg[2]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[10]),
- .Q(p_0_in65_in[26]),
- .R(1'b0));
- FDRE \byte_1_reg[3]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[11]),
- .Q(p_0_in65_in[27]),
- .R(1'b0));
- FDRE \byte_1_reg[4]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[12]),
- .Q(p_0_in65_in[28]),
- .R(1'b0));
- FDRE \byte_1_reg[5]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[13]),
- .Q(p_0_in65_in[29]),
- .R(1'b0));
- FDRE \byte_1_reg[6]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[14]),
- .Q(p_0_in65_in[30]),
- .R(1'b0));
- FDRE \byte_1_reg[7]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[15]),
- .Q(p_0_in65_in[31]),
- .R(1'b0));
- FDRE \byte_2_reg[0]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[16]),
- .Q(p_0_in65_in[16]),
- .R(1'b0));
- FDRE \byte_2_reg[1]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[17]),
- .Q(p_0_in65_in[17]),
- .R(1'b0));
- FDRE \byte_2_reg[2]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[18]),
- .Q(p_0_in65_in[18]),
- .R(1'b0));
- FDRE \byte_2_reg[3]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[19]),
- .Q(p_0_in65_in[19]),
- .R(1'b0));
- FDRE \byte_2_reg[4]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[20]),
- .Q(p_0_in65_in[20]),
- .R(1'b0));
- FDRE \byte_2_reg[5]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[21]),
- .Q(p_0_in65_in[21]),
- .R(1'b0));
- FDRE \byte_2_reg[6]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[22]),
- .Q(p_0_in65_in[22]),
- .R(1'b0));
- FDRE \byte_2_reg[7]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[23]),
- .Q(p_0_in65_in[23]),
- .R(1'b0));
- FDRE \byte_3_reg[0]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[24]),
- .Q(p_0_in62_in[24]),
- .R(1'b0));
- FDRE \byte_3_reg[1]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[25]),
- .Q(p_0_in62_in[25]),
- .R(1'b0));
- FDRE \byte_3_reg[2]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[26]),
- .Q(p_0_in62_in[26]),
- .R(1'b0));
- FDRE \byte_3_reg[3]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[27]),
- .Q(p_0_in62_in[27]),
- .R(1'b0));
- FDRE \byte_3_reg[4]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[28]),
- .Q(p_0_in62_in[28]),
- .R(1'b0));
- FDRE \byte_3_reg[5]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[29]),
- .Q(p_0_in62_in[29]),
- .R(1'b0));
- FDRE \byte_3_reg[6]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[30]),
- .Q(p_0_in62_in[30]),
- .R(1'b0));
- FDRE \byte_3_reg[7]
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TDATA[31]),
- .Q(p_0_in62_in[31]),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hFCFF8080))
- firstWord_i_1
- (.I0(M_AXIS_TREADY),
- .I1(state[1]),
- .I2(state[0]),
- .I3(S_AXIS_TVALID),
- .I4(firstWord_reg_n_0),
- .O(firstWord_i_1_n_0));
- FDSE #(
- .INIT(1'b0))
- firstWord_reg
- (.C(CLK),
- .CE(1'b1),
- .D(firstWord_i_1_n_0),
- .Q(firstWord_reg_n_0),
- .S(S_AXIS_TREADY_i_1_n_0));
- FDRE last_reg
- (.C(CLK),
- .CE(last3_out),
- .D(S_AXIS_TLAST),
- .Q(last_reg_n_0),
- .R(1'b0));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
- parameter GRES_WIDTH = 10000;
- parameter GRES_START = 10000;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- wire GRESTORE;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
- reg GRESTORE_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
- assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
- initial begin
- GRESTORE_int = 1'b0;
- #(GRES_START);
- GRESTORE_int = 1'b1;
- #(GRES_WIDTH);
- GRESTORE_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_stub.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_stub.v
deleted file mode 100644
index 67d6e12..0000000
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_stub.v
+++ /dev/null
@@ -1,37 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-// Date : Tue Feb 11 19:47:38 2025
-// Host : BiermannSurface running 64-bit major release (build 9200)
-// Command : write_verilog -force -mode synth_stub
-// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_stub.v
-// Design : axi_crc_dma_syn_1_axis_crc_0_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z020clg400-1
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* x_core_info = "axis_crc,Vivado 2023.1" *)
-module axi_crc_dma_syn_1_axis_crc_0_0(CLK, RESETN, initial_value, polynomial, finalXOR,
- inOutReflected, S_AXIS_TVALID, S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID,
- M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY)
-/* synthesis syn_black_box black_box_pad_pin="RESETN,initial_value[31:0],polynomial[31:0],finalXOR[31:0],inOutReflected[1:0],S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY" */
-/* synthesis syn_force_seq_prim="CLK" */;
- input CLK /* synthesis syn_isclock = 1 */;
- input RESETN;
- input [31:0]initial_value;
- input [31:0]polynomial;
- input [31:0]finalXOR;
- input [1:0]inOutReflected;
- input S_AXIS_TVALID;
- input [31:0]S_AXIS_TDATA;
- input S_AXIS_TLAST;
- output S_AXIS_TREADY;
- output M_AXIS_TVALID;
- output [31:0]M_AXIS_TDATA;
- output M_AXIS_TLAST;
- input M_AXIS_TREADY;
-endmodule
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/sim/axi_crc_dma_syn_1_axis_crc_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/sim/axi_crc_dma_syn_1_axis_crc_0_0.vhd
deleted file mode 100644
index ce9ceb8..0000000
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/sim/axi_crc_dma_syn_1_axis_crc_0_0.vhd
+++ /dev/null
@@ -1,130 +0,0 @@
--- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of AMD and is protected under U.S. and international copyright
--- and other intellectual property laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- AMD, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) AMD shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or AMD had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- AMD products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of AMD products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:module_ref:axis_crc:1.0
--- IP Revision: 1
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY axi_crc_dma_syn_1_axis_crc_0_0 IS
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIS_TVALID : IN STD_LOGIC;
- S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIS_TLAST : IN STD_LOGIC;
- S_AXIS_TREADY : OUT STD_LOGIC;
- M_AXIS_TVALID : OUT STD_LOGIC;
- M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXIS_TLAST : OUT STD_LOGIC;
- M_AXIS_TREADY : IN STD_LOGIC
- );
-END axi_crc_dma_syn_1_axis_crc_0_0;
-
-ARCHITECTURE axi_crc_dma_syn_1_axis_crc_0_0_arch OF axi_crc_dma_syn_1_axis_crc_0_0 IS
- ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
- ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
- COMPONENT axis_crc IS
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIS_TVALID : IN STD_LOGIC;
- S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIS_TLAST : IN STD_LOGIC;
- S_AXIS_TREADY : OUT STD_LOGIC;
- M_AXIS_TVALID : OUT STD_LOGIC;
- M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXIS_TLAST : OUT STD_LOGIC;
- M_AXIS_TREADY : IN STD_LOGIC
- );
- END COMPONENT axis_crc;
- ATTRIBUTE X_INTERFACE_INFO : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
- ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
- ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
- ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
-BEGIN
- U0 : axis_crc
- PORT MAP (
- CLK => CLK,
- RESETN => RESETN,
- initial_value => initial_value,
- polynomial => polynomial,
- finalXOR => finalXOR,
- inOutReflected => inOutReflected,
- S_AXIS_TVALID => S_AXIS_TVALID,
- S_AXIS_TDATA => S_AXIS_TDATA,
- S_AXIS_TLAST => S_AXIS_TLAST,
- S_AXIS_TREADY => S_AXIS_TREADY,
- M_AXIS_TVALID => M_AXIS_TVALID,
- M_AXIS_TDATA => M_AXIS_TDATA,
- M_AXIS_TLAST => M_AXIS_TLAST,
- M_AXIS_TREADY => M_AXIS_TREADY
- );
-END axi_crc_dma_syn_1_axis_crc_0_0_arch;
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/synth/axi_crc_dma_syn_1_axis_crc_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/synth/axi_crc_dma_syn_1_axis_crc_0_0.vhd
deleted file mode 100644
index 257d55a..0000000
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/synth/axi_crc_dma_syn_1_axis_crc_0_0.vhd
+++ /dev/null
@@ -1,138 +0,0 @@
--- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of AMD and is protected under U.S. and international copyright
--- and other intellectual property laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- AMD, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) AMD shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or AMD had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- AMD products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of AMD products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:module_ref:axis_crc:1.0
--- IP Revision: 1
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY axi_crc_dma_syn_1_axis_crc_0_0 IS
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIS_TVALID : IN STD_LOGIC;
- S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIS_TLAST : IN STD_LOGIC;
- S_AXIS_TREADY : OUT STD_LOGIC;
- M_AXIS_TVALID : OUT STD_LOGIC;
- M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXIS_TLAST : OUT STD_LOGIC;
- M_AXIS_TREADY : IN STD_LOGIC
- );
-END axi_crc_dma_syn_1_axis_crc_0_0;
-
-ARCHITECTURE axi_crc_dma_syn_1_axis_crc_0_0_arch OF axi_crc_dma_syn_1_axis_crc_0_0 IS
- ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
- ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
- COMPONENT axis_crc IS
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIS_TVALID : IN STD_LOGIC;
- S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIS_TLAST : IN STD_LOGIC;
- S_AXIS_TREADY : OUT STD_LOGIC;
- M_AXIS_TVALID : OUT STD_LOGIC;
- M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXIS_TLAST : OUT STD_LOGIC;
- M_AXIS_TREADY : IN STD_LOGIC
- );
- END COMPONENT axis_crc;
- ATTRIBUTE X_CORE_INFO : STRING;
- ATTRIBUTE X_CORE_INFO OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc,Vivado 2023.1";
- ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
- ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_syn_1_axis_crc_0_0_arch : ARCHITECTURE IS "axi_crc_dma_syn_1_axis_crc_0_0,axis_crc,{}";
- ATTRIBUTE CORE_GENERATION_INFO : STRING;
- ATTRIBUTE CORE_GENERATION_INFO OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "axi_crc_dma_syn_1_axis_crc_0_0,axis_crc,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_crc,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
- ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
- ATTRIBUTE IP_DEFINITION_SOURCE OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "module_ref";
- ATTRIBUTE X_INTERFACE_INFO : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
- ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
- ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
- ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
-BEGIN
- U0 : axis_crc
- PORT MAP (
- CLK => CLK,
- RESETN => RESETN,
- initial_value => initial_value,
- polynomial => polynomial,
- finalXOR => finalXOR,
- inOutReflected => inOutReflected,
- S_AXIS_TVALID => S_AXIS_TVALID,
- S_AXIS_TDATA => S_AXIS_TDATA,
- S_AXIS_TLAST => S_AXIS_TLAST,
- S_AXIS_TREADY => S_AXIS_TREADY,
- M_AXIS_TVALID => M_AXIS_TVALID,
- M_AXIS_TDATA => M_AXIS_TDATA,
- M_AXIS_TLAST => M_AXIS_TLAST,
- M_AXIS_TREADY => M_AXIS_TREADY
- );
-END axi_crc_dma_syn_1_axis_crc_0_0_arch;
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0.xml
index 9721589..9776121 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0.xml
@@ -119,7 +119,7 @@
FREQ_HZ
- 1e+08
+ 100000000
none
@@ -137,7 +137,7 @@
CLK_DOMAIN
- axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0
+
none
@@ -278,7 +278,7 @@
FREQ_HZ
- 1e+08
+ 100000000
none
@@ -296,7 +296,7 @@
CLK_DOMAIN
- axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0
+
none
@@ -625,7 +625,7 @@
FREQ_HZ
- 1e+08
+ 100000000
none
@@ -832,7 +832,7 @@
CLK_DOMAIN
- axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0
+
none
@@ -1052,7 +1052,7 @@
FREQ_HZ
- 1e+08
+ 100000000
none
@@ -1259,7 +1259,7 @@
CLK_DOMAIN
- axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0
+
none
@@ -1370,7 +1370,7 @@
FREQ_HZ
- 1e+08
+ 100000000
none
@@ -1397,7 +1397,7 @@
CLK_DOMAIN
- axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0
+
none
@@ -1479,101 +1479,6 @@
-
-
- xilinx_anylanguagebehavioralsimulation
- Simulation
- :vivado.xilinx.com:simulation
- axis_dma
-
-
- outputProductCRC
- 9:338a2746
-
-
-
-
- xilinx_anylanguagesynthesis
- Synthesis
- :vivado.xilinx.com:synthesis
- axis_dma
-
-
- outputProductCRC
- 9:2d5f1ca5
-
-
-
-
- xilinx_externalfiles
- External Files
- :vivado.xilinx.com:external.files
-
- xilinx_externalfiles_view_fileset
-
-
-
- GENtimestamp
- Tue Feb 11 18:38:52 UTC 2025
-
-
- outputProductCRC
- 9:2d5f1ca5
-
-
-
-
- xilinx_synthesisconstraints
- Synthesis Constraints
- :vivado.xilinx.com:synthesis.constraints
-
-
- outputProductCRC
- 9:2d5f1ca5
-
-
-
-
- xilinx_vhdlsimulationwrapper
- VHDL Simulation Wrapper
- vhdlSource:vivado.xilinx.com:simulation.wrapper
- vhdl
- axi_crc_dma_syn_1_axis_dma_0_0
-
- xilinx_vhdlsimulationwrapper_view_fileset
-
-
-
- GENtimestamp
- Mon Feb 10 21:58:20 UTC 2025
-
-
- outputProductCRC
- 9:338a2746
-
-
-
-
- xilinx_vhdlsynthesiswrapper
- VHDL Synthesis Wrapper
- vhdlSource:vivado.xilinx.com:synthesis.wrapper
- vhdl
- axi_crc_dma_syn_1_axis_dma_0_0
-
- xilinx_vhdlsynthesiswrapper_view_fileset
-
-
-
- GENtimestamp
- Mon Feb 10 21:58:20 UTC 2025
-
-
- outputProductCRC
- 9:2d5f1ca5
-
-
-
-
CLK
@@ -1582,8 +1487,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1595,8 +1499,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1608,8 +1511,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1618,7 +1520,7 @@
- initial_value
+ initialValue
out
@@ -1628,8 +1530,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1645,8 +1546,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1662,8 +1562,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1679,8 +1578,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1696,8 +1594,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1713,8 +1610,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1730,8 +1626,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1746,8 +1641,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1762,8 +1656,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1779,8 +1672,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1795,8 +1687,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1811,8 +1702,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1828,8 +1718,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1844,8 +1733,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1857,8 +1745,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1877,8 +1764,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1894,8 +1780,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1910,8 +1795,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1926,8 +1810,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1943,8 +1826,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1956,8 +1838,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1969,8 +1850,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1989,8 +1869,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2002,8 +1881,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2018,8 +1896,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2038,8 +1915,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2055,8 +1931,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2072,8 +1947,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2089,8 +1963,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2106,8 +1979,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2123,8 +1995,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2140,8 +2011,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2153,8 +2023,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2166,8 +2035,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2186,8 +2054,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2206,8 +2073,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2226,8 +2092,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2242,8 +2107,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2258,8 +2122,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2274,8 +2137,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2294,8 +2156,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2311,8 +2172,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2328,8 +2188,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2345,8 +2204,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2362,8 +2220,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2379,8 +2236,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2396,8 +2252,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2409,8 +2264,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2425,8 +2279,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2445,8 +2298,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2462,8 +2314,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2475,8 +2326,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2495,8 +2345,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2508,8 +2357,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2521,8 +2369,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2541,8 +2388,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2561,8 +2407,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2577,8 +2422,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2594,8 +2438,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2610,8 +2453,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2626,8 +2468,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2639,8 +2480,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2656,8 +2496,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2669,8 +2508,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2682,8 +2520,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -2718,11 +2555,6 @@
Polynomial Default
0x04C11DB7
-
- initial_value_default
- Initial Value Default
- 0x00000000
-
@@ -2739,60 +2571,6 @@
ACTIVE_LOW
-
-
- xilinx_externalfiles_view_fileset
-
- axi_crc_dma_syn_1_axis_dma_0_0.dcp
- dcp
- USED_IN_implementation
- USED_IN_synthesis
- xil_defaultlib
-
-
- axi_crc_dma_syn_1_axis_dma_0_0_stub.v
- verilogSource
- USED_IN_synth_blackbox_stub
- xil_defaultlib
-
-
- axi_crc_dma_syn_1_axis_dma_0_0_stub.vhdl
- vhdlSource
- USED_IN_synth_blackbox_stub
- xil_defaultlib
-
-
- axi_crc_dma_syn_1_axis_dma_0_0_sim_netlist.v
- verilogSource
- USED_IN_simulation
- USED_IN_single_language
- xil_defaultlib
-
-
- axi_crc_dma_syn_1_axis_dma_0_0_sim_netlist.vhdl
- vhdlSource
- USED_IN_simulation
- USED_IN_single_language
- xil_defaultlib
-
-
-
- xilinx_vhdlsimulationwrapper_view_fileset
-
- sim/axi_crc_dma_syn_1_axis_dma_0_0.vhd
- vhdlSource
- xil_defaultlib
-
-
-
- xilinx_vhdlsynthesiswrapper_view_fileset
-
- synth/axi_crc_dma_syn_1_axis_dma_0_0.vhd
- vhdlSource
- xil_defaultlib
-
-
-
xilinx.com:module_ref:axis_dma:1.0
@@ -2820,11 +2598,6 @@
Polynomial Default
0x04C11DB7
-
- initial_value_default
- Initial Value Default
- 0x00000000
-
Component_Name
axi_crc_dma_syn_1_axis_dma_0_0
@@ -2839,28 +2612,28 @@
-
-
+
+
-
+
-
-
-
-
-
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
@@ -2868,15 +2641,15 @@
-
-
+
+
-
+
-
-
-
+
+
+
@@ -2888,38 +2661,38 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
-
+
-
-
+
+
-
+
-
-
-
+
+
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_sim_netlist.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_sim_netlist.v
deleted file mode 100644
index 31772b0..0000000
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_sim_netlist.v
+++ /dev/null
@@ -1,9293 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-// Date : Tue Feb 11 19:38:52 2025
-// Host : BiermannSurface running 64-bit major release (build 9200)
-// Command : write_verilog -force -mode funcsim
-// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_sim_netlist.v
-// Design : axi_crc_dma_syn_1_axis_dma_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z020clg400-1
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "axi_crc_dma_syn_1_axis_dma_0_0,axis_dma,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *)
-(* x_core_info = "axis_dma,Vivado 2023.1" *)
-(* NotValidForBitStream *)
-module axi_crc_dma_syn_1_axis_dma_0_0
- (CLK,
- RESETN,
- INTERRUPT,
- initial_value,
- polynomial,
- finalXOR,
- inOutReflected,
- FIFO_NUM_FREE,
- FIFO_NUM_AVAIL,
- S_AXIL_AWADDR,
- S_AXIL_AWVALID,
- S_AXIL_AWREADY,
- S_AXIL_WDATA,
- S_AXIL_WVALID,
- S_AXIL_WREADY,
- S_AXIL_WSTRB,
- S_AXIL_BVALID,
- S_AXIL_BREADY,
- S_AXIL_BRESP,
- S_AXIL_ARADDR,
- S_AXIL_ARVALID,
- S_AXIL_ARREADY,
- S_AXIL_RDATA,
- S_AXIL_RVALID,
- S_AXIL_RREADY,
- S_AXIL_RRESP,
- M_AXI_ARREADY,
- M_AXI_ARVALID,
- M_AXI_ARADDR,
- M_AXI_ARID,
- M_AXI_ARLEN,
- M_AXI_ARSIZE,
- M_AXI_ARBURST,
- M_AXI_ARPROT,
- M_AXI_ARCACHE,
- M_AXI_RREADY,
- M_AXI_RVALID,
- M_AXI_RDATA,
- M_AXI_RRESP,
- M_AXI_RID,
- M_AXI_RLAST,
- M_AXI_AWREADY,
- M_AXI_AWVALID,
- M_AXI_AWADDR,
- M_AXI_AWLEN,
- M_AXI_AWSIZE,
- M_AXI_AWID,
- M_AXI_AWBURST,
- M_AXI_AWPROT,
- M_AXI_AWCACHE,
- M_AXI_WREADY,
- M_AXI_WVALID,
- M_AXI_WDATA,
- M_AXI_WSTRB,
- M_AXI_WLAST,
- M_AXI_WID,
- M_AXI_BREADY,
- M_AXI_BVALID,
- M_AXI_BID,
- M_AXI_BRESP,
- S_AXIS_TVALID,
- S_AXIS_TDATA,
- S_AXIS_TLAST,
- S_AXIS_TREADY,
- M_AXIS_TVALID,
- M_AXIS_TDATA,
- M_AXIS_TLAST,
- M_AXIS_TREADY);
- (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) input CLK;
- (* x_interface_info = "xilinx.com:signal:reset:1.0 RESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input RESETN;
- (* x_interface_info = "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT" *) (* x_interface_parameter = "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1" *) output INTERRUPT;
- output [31:0]initial_value;
- output [31:0]polynomial;
- output [31:0]finalXOR;
- output [1:0]inOutReflected;
- input [7:0]FIFO_NUM_FREE;
- input [7:0]FIFO_NUM_AVAIL;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [7:0]S_AXIL_AWADDR;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID" *) input S_AXIL_AWVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY" *) output S_AXIL_AWREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL WDATA" *) input [31:0]S_AXIL_WDATA;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL WVALID" *) input S_AXIL_WVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL WREADY" *) output S_AXIL_WREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB" *) input [3:0]S_AXIL_WSTRB;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL BVALID" *) output S_AXIL_BVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL BREADY" *) input S_AXIL_BREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL BRESP" *) output [1:0]S_AXIL_BRESP;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR" *) input [7:0]S_AXIL_ARADDR;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID" *) input S_AXIL_ARVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY" *) output S_AXIL_ARREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL RDATA" *) output [31:0]S_AXIL_RDATA;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL RVALID" *) output S_AXIL_RVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL RREADY" *) input S_AXIL_RREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL RRESP" *) output [1:0]S_AXIL_RRESP;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input M_AXI_ARREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output M_AXI_ARVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]M_AXI_ARADDR;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output [0:0]M_AXI_ARID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [3:0]M_AXI_ARLEN;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]M_AXI_ARSIZE;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]M_AXI_ARBURST;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]M_AXI_ARPROT;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]M_AXI_ARCACHE;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output M_AXI_RREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input M_AXI_RVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]M_AXI_RDATA;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]M_AXI_RRESP;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input [0:0]M_AXI_RID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input M_AXI_RLAST;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input M_AXI_AWREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output M_AXI_AWVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]M_AXI_AWADDR;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [3:0]M_AXI_AWLEN;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]M_AXI_AWSIZE;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output [0:0]M_AXI_AWID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]M_AXI_AWBURST;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]M_AXI_AWPROT;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]M_AXI_AWCACHE;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input M_AXI_WREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output M_AXI_WVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]M_AXI_WDATA;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]M_AXI_WSTRB;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output M_AXI_WLAST;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WID" *) output [31:0]M_AXI_WID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output M_AXI_BREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input M_AXI_BVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input [31:0]M_AXI_BID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]M_AXI_BRESP;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 66666672, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [31:0]S_AXIS_TDATA;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input S_AXIS_TLAST;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 66666672, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [31:0]M_AXIS_TDATA;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) output M_AXIS_TLAST;
- (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
-
- wire \ ;
- wire \ ;
- wire CLK;
- wire [7:0]FIFO_NUM_AVAIL;
- wire [7:0]FIFO_NUM_FREE;
- wire INTERRUPT;
- wire M_AXIS_TLAST;
- wire [31:0]M_AXI_ARADDR;
- wire [3:0]M_AXI_ARLEN;
- wire M_AXI_ARREADY;
- wire M_AXI_ARVALID;
- wire [31:0]M_AXI_AWADDR;
- wire [3:0]M_AXI_AWLEN;
- wire M_AXI_AWREADY;
- wire M_AXI_AWVALID;
- wire [31:0]M_AXI_RDATA;
- wire M_AXI_RLAST;
- wire M_AXI_RVALID;
- wire M_AXI_WLAST;
- wire M_AXI_WREADY;
- wire M_AXI_WVALID;
- wire RESETN;
- wire [7:0]S_AXIL_ARADDR;
- wire S_AXIL_ARVALID;
- wire [7:0]S_AXIL_AWADDR;
- wire S_AXIL_AWREADY;
- wire S_AXIL_AWVALID;
- wire S_AXIL_BREADY;
- wire S_AXIL_BVALID;
- wire [31:0]S_AXIL_RDATA;
- wire S_AXIL_RREADY;
- wire S_AXIL_RVALID;
- wire [31:0]S_AXIL_WDATA;
- wire [3:0]S_AXIL_WSTRB;
- wire S_AXIL_WVALID;
- wire [31:0]S_AXIS_TDATA;
- wire S_AXIS_TREADY;
- wire S_AXIS_TVALID;
- wire [31:0]finalXOR;
- wire [1:0]inOutReflected;
- wire [31:0]initial_value;
- wire [31:0]polynomial;
-
- assign M_AXIS_TDATA[31:0] = M_AXI_RDATA;
- assign M_AXIS_TVALID = M_AXI_RVALID;
- assign M_AXI_ARBURST[1] = \ ;
- assign M_AXI_ARBURST[0] = \ ;
- assign M_AXI_ARCACHE[3] = \ ;
- assign M_AXI_ARCACHE[2] = \ ;
- assign M_AXI_ARCACHE[1] = \ ;
- assign M_AXI_ARCACHE[0] = \ ;
- assign M_AXI_ARID[0] = \ ;
- assign M_AXI_ARPROT[2] = \ ;
- assign M_AXI_ARPROT[1] = \ ;
- assign M_AXI_ARPROT[0] = \ ;
- assign M_AXI_ARSIZE[2] = \ ;
- assign M_AXI_ARSIZE[1] = \ ;
- assign M_AXI_ARSIZE[0] = \ ;
- assign M_AXI_AWBURST[1] = \ ;
- assign M_AXI_AWBURST[0] = \ ;
- assign M_AXI_AWCACHE[3] = \ ;
- assign M_AXI_AWCACHE[2] = \ ;
- assign M_AXI_AWCACHE[1] = \ ;
- assign M_AXI_AWCACHE[0] = \ ;
- assign M_AXI_AWID[0] = \ ;
- assign M_AXI_AWPROT[2] = \ ;
- assign M_AXI_AWPROT[1] = \ ;
- assign M_AXI_AWPROT[0] = \ ;
- assign M_AXI_AWSIZE[2] = \ ;
- assign M_AXI_AWSIZE[1] = \ ;
- assign M_AXI_AWSIZE[0] = \ ;
- assign M_AXI_BREADY = \ ;
- assign M_AXI_RREADY = \ ;
- assign M_AXI_WDATA[31:0] = S_AXIS_TDATA;
- assign M_AXI_WID[31] = \ ;
- assign M_AXI_WID[30] = \ ;
- assign M_AXI_WID[29] = \ ;
- assign M_AXI_WID[28] = \ ;
- assign M_AXI_WID[27] = \ ;
- assign M_AXI_WID[26] = \ ;
- assign M_AXI_WID[25] = \ ;
- assign M_AXI_WID[24] = \ ;
- assign M_AXI_WID[23] = \ ;
- assign M_AXI_WID[22] = \ ;
- assign M_AXI_WID[21] = \ ;
- assign M_AXI_WID[20] = \ ;
- assign M_AXI_WID[19] = \ ;
- assign M_AXI_WID[18] = \ ;
- assign M_AXI_WID[17] = \ ;
- assign M_AXI_WID[16] = \ ;
- assign M_AXI_WID[15] = \ ;
- assign M_AXI_WID[14] = \ ;
- assign M_AXI_WID[13] = \ ;
- assign M_AXI_WID[12] = \ ;
- assign M_AXI_WID[11] = \ ;
- assign M_AXI_WID[10] = \ ;
- assign M_AXI_WID[9] = \ ;
- assign M_AXI_WID[8] = \ ;
- assign M_AXI_WID[7] = \ ;
- assign M_AXI_WID[6] = \ ;
- assign M_AXI_WID[5] = \ ;
- assign M_AXI_WID[4] = \ ;
- assign M_AXI_WID[3] = \ ;
- assign M_AXI_WID[2] = \ ;
- assign M_AXI_WID[1] = \ ;
- assign M_AXI_WID[0] = \ ;
- assign M_AXI_WSTRB[3] = \ ;
- assign M_AXI_WSTRB[2] = \ ;
- assign M_AXI_WSTRB[1] = \ ;
- assign M_AXI_WSTRB[0] = \ ;
- assign S_AXIL_ARREADY = \ ;
- assign S_AXIL_BRESP[1] = \ ;
- assign S_AXIL_BRESP[0] = \ ;
- assign S_AXIL_RRESP[1] = \ ;
- assign S_AXIL_RRESP[0] = \ ;
- assign S_AXIL_WREADY = S_AXIL_AWREADY;
- GND GND
- (.G(\ ));
- axi_crc_dma_syn_1_axis_dma_0_0_axis_dma U0
- (.CLK(CLK),
- .FIFO_NUM_AVAIL(FIFO_NUM_AVAIL),
- .FIFO_NUM_FREE(FIFO_NUM_FREE[7:4]),
- .INTERRUPT(INTERRUPT),
- .M_AXIS_TLAST(M_AXIS_TLAST),
- .M_AXI_ARADDR(M_AXI_ARADDR),
- .M_AXI_ARLEN(M_AXI_ARLEN),
- .M_AXI_ARREADY(M_AXI_ARREADY),
- .M_AXI_ARVALID(M_AXI_ARVALID),
- .M_AXI_AWADDR(M_AXI_AWADDR),
- .M_AXI_AWLEN(M_AXI_AWLEN),
- .M_AXI_AWREADY(M_AXI_AWREADY),
- .M_AXI_AWVALID(M_AXI_AWVALID),
- .M_AXI_RLAST(M_AXI_RLAST),
- .M_AXI_RVALID(M_AXI_RVALID),
- .M_AXI_WLAST(M_AXI_WLAST),
- .M_AXI_WREADY(M_AXI_WREADY),
- .M_AXI_WVALID(M_AXI_WVALID),
- .RESETN(RESETN),
- .S_AXIL_ARADDR(S_AXIL_ARADDR),
- .S_AXIL_ARVALID(S_AXIL_ARVALID),
- .S_AXIL_AWADDR(S_AXIL_AWADDR),
- .S_AXIL_AWVALID(S_AXIL_AWVALID),
- .S_AXIL_BREADY(S_AXIL_BREADY),
- .S_AXIL_BVALID(S_AXIL_BVALID),
- .S_AXIL_RDATA(S_AXIL_RDATA),
- .S_AXIL_RREADY(S_AXIL_RREADY),
- .S_AXIL_RVALID(S_AXIL_RVALID),
- .S_AXIL_WDATA(S_AXIL_WDATA),
- .S_AXIL_WSTRB(S_AXIL_WSTRB),
- .S_AXIL_WVALID(S_AXIL_WVALID),
- .S_AXIL_WVALID_0(S_AXIL_AWREADY),
- .S_AXIS_TREADY(S_AXIS_TREADY),
- .S_AXIS_TVALID(S_AXIS_TVALID),
- .finalXOR(finalXOR),
- .inOutReflected(inOutReflected),
- .initial_value(initial_value),
- .polynomial(polynomial));
- VCC VCC
- (.P(\ ));
-endmodule
-
-(* ORIG_REF_NAME = "axis_dma" *)
-module axi_crc_dma_syn_1_axis_dma_0_0_axis_dma
- (inOutReflected,
- finalXOR,
- initial_value,
- polynomial,
- S_AXIL_RDATA,
- M_AXI_ARADDR,
- M_AXI_ARLEN,
- M_AXI_AWADDR,
- M_AXI_AWLEN,
- INTERRUPT,
- S_AXIL_WVALID_0,
- S_AXIS_TREADY,
- M_AXI_WVALID,
- M_AXIS_TLAST,
- S_AXIL_BVALID,
- S_AXIL_RVALID,
- M_AXI_ARVALID,
- M_AXI_AWVALID,
- M_AXI_WLAST,
- S_AXIL_AWADDR,
- S_AXIL_AWVALID,
- S_AXIL_WVALID,
- S_AXIL_WSTRB,
- S_AXIL_ARADDR,
- M_AXI_AWREADY,
- M_AXI_WREADY,
- S_AXIL_ARVALID,
- RESETN,
- CLK,
- S_AXIL_WDATA,
- S_AXIS_TVALID,
- M_AXI_RLAST,
- M_AXI_RVALID,
- M_AXI_ARREADY,
- FIFO_NUM_AVAIL,
- FIFO_NUM_FREE,
- S_AXIL_BREADY,
- S_AXIL_RREADY);
- output [1:0]inOutReflected;
- output [31:0]finalXOR;
- output [31:0]initial_value;
- output [31:0]polynomial;
- output [31:0]S_AXIL_RDATA;
- output [31:0]M_AXI_ARADDR;
- output [3:0]M_AXI_ARLEN;
- output [31:0]M_AXI_AWADDR;
- output [3:0]M_AXI_AWLEN;
- output INTERRUPT;
- output S_AXIL_WVALID_0;
- output S_AXIS_TREADY;
- output M_AXI_WVALID;
- output M_AXIS_TLAST;
- output S_AXIL_BVALID;
- output S_AXIL_RVALID;
- output M_AXI_ARVALID;
- output M_AXI_AWVALID;
- output M_AXI_WLAST;
- input [7:0]S_AXIL_AWADDR;
- input S_AXIL_AWVALID;
- input S_AXIL_WVALID;
- input [3:0]S_AXIL_WSTRB;
- input [7:0]S_AXIL_ARADDR;
- input M_AXI_AWREADY;
- input M_AXI_WREADY;
- input S_AXIL_ARVALID;
- input RESETN;
- input CLK;
- input [31:0]S_AXIL_WDATA;
- input S_AXIS_TVALID;
- input M_AXI_RLAST;
- input M_AXI_RVALID;
- input M_AXI_ARREADY;
- input [7:0]FIFO_NUM_AVAIL;
- input [3:0]FIFO_NUM_FREE;
- input S_AXIL_BREADY;
- input S_AXIL_RREADY;
-
- wire [15:0]A;
- wire [15:0]B;
- wire CLK;
- wire [7:0]FIFO_NUM_AVAIL;
- wire [3:0]FIFO_NUM_FREE;
- wire INTERRUPT;
- wire INTERRUPT_INST_0_i_1_n_0;
- wire [31:0]L__0;
- wire M_AXIS_TLAST;
- wire [31:0]M_AXI_ARADDR;
- wire \M_AXI_ARADDR[31]_i_1_n_0 ;
- wire \M_AXI_ARADDR[31]_i_2_n_0 ;
- wire [3:0]M_AXI_ARLEN;
- wire \M_AXI_ARLEN[0]_i_1_n_0 ;
- wire \M_AXI_ARLEN[1]_i_1_n_0 ;
- wire \M_AXI_ARLEN[2]_i_1_n_0 ;
- wire \M_AXI_ARLEN[3]_i_10_n_0 ;
- wire \M_AXI_ARLEN[3]_i_13_n_0 ;
- wire \M_AXI_ARLEN[3]_i_14_n_0 ;
- wire \M_AXI_ARLEN[3]_i_1_n_0 ;
- wire \M_AXI_ARLEN[3]_i_2_n_0 ;
- wire \M_AXI_ARLEN[3]_i_3_n_0 ;
- wire \M_AXI_ARLEN[3]_i_4_n_0 ;
- wire \M_AXI_ARLEN[3]_i_8_n_0 ;
- wire \M_AXI_ARLEN_reg[3]_i_11_n_2 ;
- wire \M_AXI_ARLEN_reg[3]_i_11_n_3 ;
- wire \M_AXI_ARLEN_reg[3]_i_11_n_5 ;
- wire \M_AXI_ARLEN_reg[3]_i_11_n_6 ;
- wire \M_AXI_ARLEN_reg[3]_i_11_n_7 ;
- wire \M_AXI_ARLEN_reg[3]_i_12_n_0 ;
- wire \M_AXI_ARLEN_reg[3]_i_12_n_1 ;
- wire \M_AXI_ARLEN_reg[3]_i_12_n_2 ;
- wire \M_AXI_ARLEN_reg[3]_i_12_n_3 ;
- wire \M_AXI_ARLEN_reg[3]_i_12_n_4 ;
- wire \M_AXI_ARLEN_reg[3]_i_15_n_0 ;
- wire \M_AXI_ARLEN_reg[3]_i_15_n_1 ;
- wire \M_AXI_ARLEN_reg[3]_i_15_n_2 ;
- wire \M_AXI_ARLEN_reg[3]_i_15_n_3 ;
- wire \M_AXI_ARLEN_reg[3]_i_15_n_4 ;
- wire \M_AXI_ARLEN_reg[3]_i_15_n_5 ;
- wire \M_AXI_ARLEN_reg[3]_i_15_n_6 ;
- wire \M_AXI_ARLEN_reg[3]_i_15_n_7 ;
- wire \M_AXI_ARLEN_reg[3]_i_16_n_0 ;
- wire \M_AXI_ARLEN_reg[3]_i_16_n_1 ;
- wire \M_AXI_ARLEN_reg[3]_i_16_n_2 ;
- wire \M_AXI_ARLEN_reg[3]_i_16_n_3 ;
- wire \M_AXI_ARLEN_reg[3]_i_16_n_4 ;
- wire \M_AXI_ARLEN_reg[3]_i_16_n_5 ;
- wire \M_AXI_ARLEN_reg[3]_i_16_n_6 ;
- wire \M_AXI_ARLEN_reg[3]_i_16_n_7 ;
- wire \M_AXI_ARLEN_reg[3]_i_5_n_0 ;
- wire \M_AXI_ARLEN_reg[3]_i_5_n_1 ;
- wire \M_AXI_ARLEN_reg[3]_i_5_n_2 ;
- wire \M_AXI_ARLEN_reg[3]_i_5_n_3 ;
- wire \M_AXI_ARLEN_reg[3]_i_5_n_4 ;
- wire \M_AXI_ARLEN_reg[3]_i_5_n_5 ;
- wire \M_AXI_ARLEN_reg[3]_i_5_n_6 ;
- wire \M_AXI_ARLEN_reg[3]_i_5_n_7 ;
- wire \M_AXI_ARLEN_reg[3]_i_6_n_0 ;
- wire \M_AXI_ARLEN_reg[3]_i_6_n_1 ;
- wire \M_AXI_ARLEN_reg[3]_i_6_n_2 ;
- wire \M_AXI_ARLEN_reg[3]_i_6_n_3 ;
- wire \M_AXI_ARLEN_reg[3]_i_6_n_4 ;
- wire \M_AXI_ARLEN_reg[3]_i_6_n_5 ;
- wire \M_AXI_ARLEN_reg[3]_i_6_n_6 ;
- wire \M_AXI_ARLEN_reg[3]_i_6_n_7 ;
- wire \M_AXI_ARLEN_reg[3]_i_7_n_0 ;
- wire \M_AXI_ARLEN_reg[3]_i_7_n_1 ;
- wire \M_AXI_ARLEN_reg[3]_i_7_n_2 ;
- wire \M_AXI_ARLEN_reg[3]_i_7_n_3 ;
- wire \M_AXI_ARLEN_reg[3]_i_7_n_4 ;
- wire \M_AXI_ARLEN_reg[3]_i_7_n_5 ;
- wire \M_AXI_ARLEN_reg[3]_i_7_n_6 ;
- wire \M_AXI_ARLEN_reg[3]_i_7_n_7 ;
- wire \M_AXI_ARLEN_reg[3]_i_9_n_0 ;
- wire \M_AXI_ARLEN_reg[3]_i_9_n_1 ;
- wire \M_AXI_ARLEN_reg[3]_i_9_n_2 ;
- wire \M_AXI_ARLEN_reg[3]_i_9_n_3 ;
- wire \M_AXI_ARLEN_reg[3]_i_9_n_4 ;
- wire \M_AXI_ARLEN_reg[3]_i_9_n_5 ;
- wire \M_AXI_ARLEN_reg[3]_i_9_n_6 ;
- wire \M_AXI_ARLEN_reg[3]_i_9_n_7 ;
- wire M_AXI_ARREADY;
- wire M_AXI_ARVALID;
- wire M_AXI_ARVALID_i_1_n_0;
- wire M_AXI_ARVALID_i_2_n_0;
- wire [31:0]M_AXI_AWADDR;
- wire \M_AXI_AWADDR[31]_i_1_n_0 ;
- wire \M_AXI_AWADDR[31]_i_2_n_0 ;
- wire \M_AXI_AWADDR[31]_i_3_n_0 ;
- wire \M_AXI_AWADDR[31]_i_4_n_0 ;
- wire \M_AXI_AWADDR[31]_i_5_n_0 ;
- wire [3:0]M_AXI_AWLEN;
- wire \M_AXI_AWLEN[0]_i_1_n_0 ;
- wire \M_AXI_AWLEN[1]_i_1_n_0 ;
- wire \M_AXI_AWLEN[2]_i_1_n_0 ;
- wire \M_AXI_AWLEN[3]_i_1_n_0 ;
- wire M_AXI_AWREADY;
- wire M_AXI_AWVALID;
- wire M_AXI_AWVALID2;
- wire M_AXI_AWVALID2_carry__0_i_1_n_0;
- wire M_AXI_AWVALID2_carry__0_i_2_n_0;
- wire M_AXI_AWVALID2_carry__0_i_3_n_0;
- wire M_AXI_AWVALID2_carry__0_i_4_n_0;
- wire M_AXI_AWVALID2_carry__0_i_5_n_0;
- wire M_AXI_AWVALID2_carry__0_i_5_n_1;
- wire M_AXI_AWVALID2_carry__0_i_5_n_2;
- wire M_AXI_AWVALID2_carry__0_i_5_n_3;
- wire M_AXI_AWVALID2_carry__0_i_5_n_4;
- wire M_AXI_AWVALID2_carry__0_i_5_n_5;
- wire M_AXI_AWVALID2_carry__0_i_5_n_6;
- wire M_AXI_AWVALID2_carry__0_i_5_n_7;
- wire M_AXI_AWVALID2_carry__0_i_6_n_0;
- wire M_AXI_AWVALID2_carry__0_i_6_n_1;
- wire M_AXI_AWVALID2_carry__0_i_6_n_2;
- wire M_AXI_AWVALID2_carry__0_i_6_n_3;
- wire M_AXI_AWVALID2_carry__0_i_6_n_4;
- wire M_AXI_AWVALID2_carry__0_i_6_n_5;
- wire M_AXI_AWVALID2_carry__0_i_6_n_6;
- wire M_AXI_AWVALID2_carry__0_i_6_n_7;
- wire M_AXI_AWVALID2_carry__0_i_7_n_0;
- wire M_AXI_AWVALID2_carry__0_i_7_n_1;
- wire M_AXI_AWVALID2_carry__0_i_7_n_2;
- wire M_AXI_AWVALID2_carry__0_i_7_n_3;
- wire M_AXI_AWVALID2_carry__0_i_7_n_4;
- wire M_AXI_AWVALID2_carry__0_i_7_n_5;
- wire M_AXI_AWVALID2_carry__0_i_7_n_6;
- wire M_AXI_AWVALID2_carry__0_i_7_n_7;
- wire M_AXI_AWVALID2_carry__0_n_0;
- wire M_AXI_AWVALID2_carry__0_n_1;
- wire M_AXI_AWVALID2_carry__0_n_2;
- wire M_AXI_AWVALID2_carry__0_n_3;
- wire M_AXI_AWVALID2_carry__1_i_1_n_0;
- wire M_AXI_AWVALID2_carry__1_i_2_n_0;
- wire M_AXI_AWVALID2_carry__1_i_3_n_0;
- wire M_AXI_AWVALID2_carry__1_i_4_n_2;
- wire M_AXI_AWVALID2_carry__1_i_4_n_3;
- wire M_AXI_AWVALID2_carry__1_i_4_n_5;
- wire M_AXI_AWVALID2_carry__1_i_4_n_6;
- wire M_AXI_AWVALID2_carry__1_i_4_n_7;
- wire M_AXI_AWVALID2_carry__1_i_5_n_0;
- wire M_AXI_AWVALID2_carry__1_i_5_n_1;
- wire M_AXI_AWVALID2_carry__1_i_5_n_2;
- wire M_AXI_AWVALID2_carry__1_i_5_n_3;
- wire M_AXI_AWVALID2_carry__1_i_5_n_4;
- wire M_AXI_AWVALID2_carry__1_i_5_n_5;
- wire M_AXI_AWVALID2_carry__1_i_5_n_6;
- wire M_AXI_AWVALID2_carry__1_i_5_n_7;
- wire M_AXI_AWVALID2_carry__1_n_2;
- wire M_AXI_AWVALID2_carry__1_n_3;
- wire M_AXI_AWVALID2_carry_i_1_n_0;
- wire M_AXI_AWVALID2_carry_i_2_n_0;
- wire M_AXI_AWVALID2_carry_i_3_n_0;
- wire M_AXI_AWVALID2_carry_i_4_n_0;
- wire M_AXI_AWVALID2_carry_i_5_n_0;
- wire M_AXI_AWVALID2_carry_i_5_n_1;
- wire M_AXI_AWVALID2_carry_i_5_n_2;
- wire M_AXI_AWVALID2_carry_i_5_n_3;
- wire M_AXI_AWVALID2_carry_i_5_n_4;
- wire M_AXI_AWVALID2_carry_i_5_n_5;
- wire M_AXI_AWVALID2_carry_i_5_n_6;
- wire M_AXI_AWVALID2_carry_i_5_n_7;
- wire M_AXI_AWVALID2_carry_i_6_n_0;
- wire M_AXI_AWVALID2_carry_i_6_n_1;
- wire M_AXI_AWVALID2_carry_i_6_n_2;
- wire M_AXI_AWVALID2_carry_i_6_n_3;
- wire M_AXI_AWVALID2_carry_i_6_n_4;
- wire M_AXI_AWVALID2_carry_i_6_n_5;
- wire M_AXI_AWVALID2_carry_i_6_n_6;
- wire M_AXI_AWVALID2_carry_i_6_n_7;
- wire M_AXI_AWVALID2_carry_i_7_n_0;
- wire M_AXI_AWVALID2_carry_i_7_n_1;
- wire M_AXI_AWVALID2_carry_i_7_n_2;
- wire M_AXI_AWVALID2_carry_i_7_n_3;
- wire M_AXI_AWVALID2_carry_i_7_n_4;
- wire M_AXI_AWVALID2_carry_i_7_n_5;
- wire M_AXI_AWVALID2_carry_i_7_n_6;
- wire M_AXI_AWVALID2_carry_i_7_n_7;
- wire M_AXI_AWVALID2_carry_n_0;
- wire M_AXI_AWVALID2_carry_n_1;
- wire M_AXI_AWVALID2_carry_n_2;
- wire M_AXI_AWVALID2_carry_n_3;
- wire M_AXI_AWVALID_i_1_n_0;
- wire M_AXI_AWVALID_i_2_n_0;
- wire M_AXI_AWVALID_i_3_n_0;
- wire M_AXI_AWVALID_i_4_n_0;
- wire M_AXI_AWVALID_i_5_n_0;
- wire M_AXI_AWVALID_i_6_n_0;
- wire M_AXI_AWVALID_i_7_n_0;
- wire M_AXI_AWVALID_i_8_n_0;
- wire M_AXI_AWVALID_i_9_n_0;
- wire M_AXI_RLAST;
- wire M_AXI_RVALID;
- wire M_AXI_WLAST;
- wire M_AXI_WLAST_i_1_n_0;
- wire M_AXI_WLAST_i_2_n_0;
- wire M_AXI_WLAST_i_3_n_0;
- wire M_AXI_WLAST_i_4_n_0;
- wire M_AXI_WLAST_i_5_n_0;
- wire M_AXI_WLAST_i_6_n_0;
- wire M_AXI_WLAST_i_7_n_0;
- wire M_AXI_WREADY;
- wire M_AXI_WVALID;
- wire RESETN;
- wire [7:0]S_AXIL_ARADDR;
- wire S_AXIL_ARVALID;
- wire [7:0]S_AXIL_AWADDR;
- wire S_AXIL_AWVALID;
- wire S_AXIL_BREADY;
- wire S_AXIL_BVALID;
- wire S_AXIL_BVALID_i_1_n_0;
- wire [31:0]S_AXIL_RDATA;
- wire \S_AXIL_RDATA[0]_i_1_n_0 ;
- wire \S_AXIL_RDATA[0]_i_2_n_0 ;
- wire \S_AXIL_RDATA[0]_i_3_n_0 ;
- wire \S_AXIL_RDATA[0]_i_4_n_0 ;
- wire \S_AXIL_RDATA[0]_i_5_n_0 ;
- wire \S_AXIL_RDATA[10]_i_1_n_0 ;
- wire \S_AXIL_RDATA[10]_i_2_n_0 ;
- wire \S_AXIL_RDATA[10]_i_3_n_0 ;
- wire \S_AXIL_RDATA[11]_i_1_n_0 ;
- wire \S_AXIL_RDATA[11]_i_2_n_0 ;
- wire \S_AXIL_RDATA[11]_i_3_n_0 ;
- wire \S_AXIL_RDATA[12]_i_1_n_0 ;
- wire \S_AXIL_RDATA[12]_i_2_n_0 ;
- wire \S_AXIL_RDATA[12]_i_3_n_0 ;
- wire \S_AXIL_RDATA[13]_i_1_n_0 ;
- wire \S_AXIL_RDATA[13]_i_2_n_0 ;
- wire \S_AXIL_RDATA[13]_i_3_n_0 ;
- wire \S_AXIL_RDATA[14]_i_1_n_0 ;
- wire \S_AXIL_RDATA[14]_i_2_n_0 ;
- wire \S_AXIL_RDATA[14]_i_3_n_0 ;
- wire \S_AXIL_RDATA[15]_i_1_n_0 ;
- wire \S_AXIL_RDATA[15]_i_2_n_0 ;
- wire \S_AXIL_RDATA[15]_i_3_n_0 ;
- wire \S_AXIL_RDATA[16]_i_1_n_0 ;
- wire \S_AXIL_RDATA[16]_i_2_n_0 ;
- wire \S_AXIL_RDATA[16]_i_3_n_0 ;
- wire \S_AXIL_RDATA[17]_i_1_n_0 ;
- wire \S_AXIL_RDATA[17]_i_2_n_0 ;
- wire \S_AXIL_RDATA[17]_i_3_n_0 ;
- wire \S_AXIL_RDATA[18]_i_1_n_0 ;
- wire \S_AXIL_RDATA[18]_i_2_n_0 ;
- wire \S_AXIL_RDATA[18]_i_3_n_0 ;
- wire \S_AXIL_RDATA[19]_i_1_n_0 ;
- wire \S_AXIL_RDATA[19]_i_2_n_0 ;
- wire \S_AXIL_RDATA[19]_i_3_n_0 ;
- wire \S_AXIL_RDATA[1]_i_1_n_0 ;
- wire \S_AXIL_RDATA[1]_i_2_n_0 ;
- wire \S_AXIL_RDATA[1]_i_4_n_0 ;
- wire \S_AXIL_RDATA[1]_i_5_n_0 ;
- wire \S_AXIL_RDATA[1]_i_6_n_0 ;
- wire \S_AXIL_RDATA[1]_i_7_n_0 ;
- wire \S_AXIL_RDATA[20]_i_1_n_0 ;
- wire \S_AXIL_RDATA[20]_i_2_n_0 ;
- wire \S_AXIL_RDATA[20]_i_3_n_0 ;
- wire \S_AXIL_RDATA[21]_i_1_n_0 ;
- wire \S_AXIL_RDATA[21]_i_2_n_0 ;
- wire \S_AXIL_RDATA[21]_i_3_n_0 ;
- wire \S_AXIL_RDATA[22]_i_1_n_0 ;
- wire \S_AXIL_RDATA[22]_i_2_n_0 ;
- wire \S_AXIL_RDATA[22]_i_3_n_0 ;
- wire \S_AXIL_RDATA[23]_i_1_n_0 ;
- wire \S_AXIL_RDATA[23]_i_2_n_0 ;
- wire \S_AXIL_RDATA[23]_i_3_n_0 ;
- wire \S_AXIL_RDATA[24]_i_1_n_0 ;
- wire \S_AXIL_RDATA[24]_i_2_n_0 ;
- wire \S_AXIL_RDATA[24]_i_3_n_0 ;
- wire \S_AXIL_RDATA[25]_i_1_n_0 ;
- wire \S_AXIL_RDATA[25]_i_2_n_0 ;
- wire \S_AXIL_RDATA[25]_i_3_n_0 ;
- wire \S_AXIL_RDATA[26]_i_1_n_0 ;
- wire \S_AXIL_RDATA[26]_i_2_n_0 ;
- wire \S_AXIL_RDATA[26]_i_3_n_0 ;
- wire \S_AXIL_RDATA[27]_i_1_n_0 ;
- wire \S_AXIL_RDATA[27]_i_2_n_0 ;
- wire \S_AXIL_RDATA[27]_i_3_n_0 ;
- wire \S_AXIL_RDATA[28]_i_1_n_0 ;
- wire \S_AXIL_RDATA[28]_i_2_n_0 ;
- wire \S_AXIL_RDATA[28]_i_3_n_0 ;
- wire \S_AXIL_RDATA[29]_i_1_n_0 ;
- wire \S_AXIL_RDATA[29]_i_2_n_0 ;
- wire \S_AXIL_RDATA[29]_i_3_n_0 ;
- wire \S_AXIL_RDATA[2]_i_1_n_0 ;
- wire \S_AXIL_RDATA[2]_i_2_n_0 ;
- wire \S_AXIL_RDATA[2]_i_3_n_0 ;
- wire \S_AXIL_RDATA[30]_i_1_n_0 ;
- wire \S_AXIL_RDATA[30]_i_2_n_0 ;
- wire \S_AXIL_RDATA[30]_i_3_n_0 ;
- wire \S_AXIL_RDATA[31]_i_1_n_0 ;
- wire \S_AXIL_RDATA[31]_i_2_n_0 ;
- wire \S_AXIL_RDATA[31]_i_3_n_0 ;
- wire \S_AXIL_RDATA[31]_i_4_n_0 ;
- wire \S_AXIL_RDATA[31]_i_5_n_0 ;
- wire \S_AXIL_RDATA[31]_i_6_n_0 ;
- wire \S_AXIL_RDATA[31]_i_7_n_0 ;
- wire \S_AXIL_RDATA[3]_i_1_n_0 ;
- wire \S_AXIL_RDATA[3]_i_2_n_0 ;
- wire \S_AXIL_RDATA[3]_i_3_n_0 ;
- wire \S_AXIL_RDATA[4]_i_1_n_0 ;
- wire \S_AXIL_RDATA[4]_i_2_n_0 ;
- wire \S_AXIL_RDATA[4]_i_3_n_0 ;
- wire \S_AXIL_RDATA[5]_i_1_n_0 ;
- wire \S_AXIL_RDATA[5]_i_2_n_0 ;
- wire \S_AXIL_RDATA[5]_i_3_n_0 ;
- wire \S_AXIL_RDATA[6]_i_1_n_0 ;
- wire \S_AXIL_RDATA[6]_i_2_n_0 ;
- wire \S_AXIL_RDATA[6]_i_3_n_0 ;
- wire \S_AXIL_RDATA[7]_i_1_n_0 ;
- wire \S_AXIL_RDATA[7]_i_2_n_0 ;
- wire \S_AXIL_RDATA[7]_i_3_n_0 ;
- wire \S_AXIL_RDATA[8]_i_1_n_0 ;
- wire \S_AXIL_RDATA[8]_i_2_n_0 ;
- wire \S_AXIL_RDATA[8]_i_3_n_0 ;
- wire \S_AXIL_RDATA[9]_i_1_n_0 ;
- wire \S_AXIL_RDATA[9]_i_2_n_0 ;
- wire \S_AXIL_RDATA[9]_i_3_n_0 ;
- wire \S_AXIL_RDATA_reg[1]_i_3_n_0 ;
- wire S_AXIL_RREADY;
- wire S_AXIL_RVALID;
- wire S_AXIL_RVALID_i_1_n_0;
- wire [31:0]S_AXIL_WDATA;
- wire [3:0]S_AXIL_WSTRB;
- wire S_AXIL_WVALID;
- wire S_AXIL_WVALID_0;
- wire S_AXIS_TREADY;
- wire S_AXIS_TVALID;
- wire __0_carry__0_i_1_n_0;
- wire __0_carry__0_i_2_n_0;
- wire __0_carry__0_i_3_n_0;
- wire __0_carry__0_i_4_n_0;
- wire __0_carry__0_i_5_n_0;
- wire __0_carry__0_i_6_n_0;
- wire __0_carry__0_i_7_n_0;
- wire __0_carry__0_i_8_n_0;
- wire __0_carry__0_n_0;
- wire __0_carry__0_n_1;
- wire __0_carry__0_n_2;
- wire __0_carry__0_n_3;
- wire __0_carry__1_i_1_n_0;
- wire __0_carry__1_i_2_n_0;
- wire __0_carry__1_i_3_n_0;
- wire __0_carry__1_i_4_n_0;
- wire __0_carry__1_i_5_n_0;
- wire __0_carry__1_i_6_n_0;
- wire __0_carry__1_i_7_n_0;
- wire __0_carry__1_i_8_n_0;
- wire __0_carry__1_n_0;
- wire __0_carry__1_n_1;
- wire __0_carry__1_n_2;
- wire __0_carry__1_n_3;
- wire __0_carry__2_i_1_n_0;
- wire __0_carry__2_i_2_n_0;
- wire __0_carry__2_i_3_n_0;
- wire __0_carry__2_i_4_n_0;
- wire __0_carry__2_i_5_n_0;
- wire __0_carry__2_i_6_n_0;
- wire __0_carry__2_i_7_n_0;
- wire __0_carry__2_i_8_n_0;
- wire __0_carry__2_n_0;
- wire __0_carry__2_n_1;
- wire __0_carry__2_n_2;
- wire __0_carry__2_n_3;
- wire __0_carry__3_i_1_n_0;
- wire __0_carry__3_i_2_n_0;
- wire __0_carry__3_i_3_n_0;
- wire __0_carry__3_i_4_n_0;
- wire __0_carry__3_i_5_n_0;
- wire __0_carry__3_i_6_n_0;
- wire __0_carry__3_i_7_n_0;
- wire __0_carry__3_i_8_n_0;
- wire __0_carry__3_n_0;
- wire __0_carry__3_n_1;
- wire __0_carry__3_n_2;
- wire __0_carry__3_n_3;
- wire __0_carry__4_i_1_n_0;
- wire __0_carry__4_i_2_n_0;
- wire __0_carry__4_i_3_n_0;
- wire __0_carry__4_i_4_n_0;
- wire __0_carry__4_i_5_n_0;
- wire __0_carry__4_i_6_n_0;
- wire __0_carry__4_i_7_n_0;
- wire __0_carry__4_i_8_n_0;
- wire __0_carry__4_n_0;
- wire __0_carry__4_n_1;
- wire __0_carry__4_n_2;
- wire __0_carry__4_n_3;
- wire __0_carry__5_i_1_n_0;
- wire __0_carry__5_i_2_n_0;
- wire __0_carry__5_i_3_n_0;
- wire __0_carry__5_i_4_n_0;
- wire __0_carry__5_i_5_n_0;
- wire __0_carry__5_i_6_n_0;
- wire __0_carry__5_i_7_n_0;
- wire __0_carry__5_i_8_n_0;
- wire __0_carry__5_n_0;
- wire __0_carry__5_n_1;
- wire __0_carry__5_n_2;
- wire __0_carry__5_n_3;
- wire __0_carry__6_i_1_n_0;
- wire __0_carry__6_i_2_n_0;
- wire __0_carry__6_i_3_n_0;
- wire __0_carry__6_i_4_n_0;
- wire __0_carry__6_i_5_n_0;
- wire __0_carry__6_i_6_n_0;
- wire __0_carry__6_i_7_n_0;
- wire __0_carry__6_n_1;
- wire __0_carry__6_n_2;
- wire __0_carry__6_n_3;
- wire __0_carry_i_1_n_0;
- wire __0_carry_i_2_n_0;
- wire __0_carry_i_3_n_0;
- wire __0_carry_i_4_n_0;
- wire __0_carry_i_5_n_0;
- wire __0_carry_i_6_n_0;
- wire __0_carry_i_7_n_0;
- wire __0_carry_n_0;
- wire __0_carry_n_1;
- wire __0_carry_n_2;
- wire __0_carry_n_3;
- wire __93_carry__0_i_1_n_0;
- wire __93_carry__0_i_2_n_0;
- wire __93_carry__0_i_3_n_0;
- wire __93_carry__0_i_4_n_0;
- wire __93_carry__0_i_5_n_0;
- wire __93_carry__0_i_6_n_0;
- wire __93_carry__0_i_7_n_0;
- wire __93_carry__0_i_8_n_0;
- wire __93_carry__0_n_0;
- wire __93_carry__0_n_1;
- wire __93_carry__0_n_2;
- wire __93_carry__0_n_3;
- wire __93_carry__1_i_1_n_0;
- wire __93_carry__1_i_2_n_0;
- wire __93_carry__1_i_3_n_0;
- wire __93_carry__1_i_4_n_0;
- wire __93_carry__1_i_5_n_0;
- wire __93_carry__1_i_6_n_0;
- wire __93_carry__1_i_7_n_0;
- wire __93_carry__1_i_8_n_0;
- wire __93_carry__1_n_0;
- wire __93_carry__1_n_1;
- wire __93_carry__1_n_2;
- wire __93_carry__1_n_3;
- wire __93_carry__2_i_1_n_0;
- wire __93_carry__2_i_2_n_0;
- wire __93_carry__2_i_3_n_0;
- wire __93_carry__2_i_4_n_0;
- wire __93_carry__2_i_5_n_0;
- wire __93_carry__2_i_6_n_0;
- wire __93_carry__2_i_7_n_0;
- wire __93_carry__2_i_8_n_0;
- wire __93_carry__2_n_0;
- wire __93_carry__2_n_1;
- wire __93_carry__2_n_2;
- wire __93_carry__2_n_3;
- wire __93_carry__3_i_1_n_0;
- wire __93_carry__3_i_2_n_0;
- wire __93_carry__3_i_3_n_0;
- wire __93_carry__3_i_4_n_0;
- wire __93_carry__3_i_5_n_0;
- wire __93_carry__3_i_6_n_0;
- wire __93_carry__3_i_7_n_0;
- wire __93_carry__3_i_8_n_0;
- wire __93_carry__3_n_0;
- wire __93_carry__3_n_1;
- wire __93_carry__3_n_2;
- wire __93_carry__3_n_3;
- wire __93_carry__4_i_1_n_0;
- wire __93_carry__4_i_2_n_0;
- wire __93_carry__4_i_3_n_0;
- wire __93_carry__4_i_4_n_0;
- wire __93_carry__4_i_5_n_0;
- wire __93_carry__4_i_6_n_0;
- wire __93_carry__4_i_7_n_0;
- wire __93_carry__4_i_8_n_0;
- wire __93_carry__4_n_0;
- wire __93_carry__4_n_1;
- wire __93_carry__4_n_2;
- wire __93_carry__4_n_3;
- wire __93_carry__5_i_1_n_0;
- wire __93_carry__5_i_2_n_0;
- wire __93_carry__5_i_3_n_0;
- wire __93_carry__5_i_4_n_0;
- wire __93_carry__5_i_5_n_0;
- wire __93_carry__5_i_6_n_0;
- wire __93_carry__5_i_7_n_0;
- wire __93_carry__5_i_8_n_0;
- wire __93_carry__5_n_0;
- wire __93_carry__5_n_1;
- wire __93_carry__5_n_2;
- wire __93_carry__5_n_3;
- wire __93_carry__6_i_1_n_0;
- wire __93_carry__6_i_2_n_0;
- wire __93_carry__6_i_3_n_0;
- wire __93_carry__6_i_4_n_0;
- wire __93_carry__6_i_5_n_0;
- wire __93_carry__6_n_2;
- wire __93_carry__6_n_3;
- wire __93_carry_i_1_n_0;
- wire __93_carry_i_2_n_0;
- wire __93_carry_i_3_n_0;
- wire __93_carry_i_4_n_0;
- wire __93_carry_i_5_n_0;
- wire __93_carry_i_6_n_0;
- wire __93_carry_i_7_n_0;
- wire __93_carry_i_8_n_0;
- wire __93_carry_i_9_n_0;
- wire __93_carry_n_0;
- wire __93_carry_n_1;
- wire __93_carry_n_2;
- wire __93_carry_n_3;
- wire [4:0]burst_data_cnt;
- wire \burst_data_cnt[4]_i_1_n_0 ;
- wire \burst_data_cnt[4]_i_3_n_0 ;
- wire \burst_data_cnt_reg_n_0_[0] ;
- wire \burst_data_cnt_reg_n_0_[1] ;
- wire \burst_data_cnt_reg_n_0_[2] ;
- wire \burst_data_cnt_reg_n_0_[3] ;
- wire \burst_data_cnt_reg_n_0_[4] ;
- wire [31:0]data_cnt;
- wire [31:0]data_cnt1_in;
- wire data_cnt_3;
- wire \data_cnt_reg[0]__0_n_0 ;
- wire \data_cnt_reg[10]__0_n_0 ;
- wire \data_cnt_reg[11]__0_n_0 ;
- wire \data_cnt_reg[12]__0_n_0 ;
- wire \data_cnt_reg[13]__0_n_0 ;
- wire \data_cnt_reg[14]__0_n_0 ;
- wire \data_cnt_reg[15]__0_n_0 ;
- wire \data_cnt_reg[16]__0_n_0 ;
- wire \data_cnt_reg[17]__0_n_0 ;
- wire \data_cnt_reg[18]__0_n_0 ;
- wire \data_cnt_reg[19]__0_n_0 ;
- wire \data_cnt_reg[1]__0_n_0 ;
- wire \data_cnt_reg[20]__0_n_0 ;
- wire \data_cnt_reg[21]__0_n_0 ;
- wire \data_cnt_reg[22]__0_n_0 ;
- wire \data_cnt_reg[23]__0_n_0 ;
- wire \data_cnt_reg[24]__0_n_0 ;
- wire \data_cnt_reg[25]__0_n_0 ;
- wire \data_cnt_reg[26]__0_n_0 ;
- wire \data_cnt_reg[27]__0_n_0 ;
- wire \data_cnt_reg[28]__0_n_0 ;
- wire \data_cnt_reg[29]__0_n_0 ;
- wire \data_cnt_reg[2]__0_n_0 ;
- wire \data_cnt_reg[30]__0_n_0 ;
- wire \data_cnt_reg[31]__0_n_0 ;
- wire \data_cnt_reg[3]__0_n_0 ;
- wire \data_cnt_reg[4]__0_n_0 ;
- wire \data_cnt_reg[5]__0_n_0 ;
- wire \data_cnt_reg[6]__0_n_0 ;
- wire \data_cnt_reg[7]__0_n_0 ;
- wire \data_cnt_reg[8]__0_n_0 ;
- wire \data_cnt_reg[9]__0_n_0 ;
- wire \data_cnt_reg_n_0_[0] ;
- wire \data_cnt_reg_n_0_[10] ;
- wire \data_cnt_reg_n_0_[11] ;
- wire \data_cnt_reg_n_0_[12] ;
- wire \data_cnt_reg_n_0_[13] ;
- wire \data_cnt_reg_n_0_[14] ;
- wire \data_cnt_reg_n_0_[15] ;
- wire \data_cnt_reg_n_0_[16] ;
- wire \data_cnt_reg_n_0_[17] ;
- wire \data_cnt_reg_n_0_[18] ;
- wire \data_cnt_reg_n_0_[19] ;
- wire \data_cnt_reg_n_0_[1] ;
- wire \data_cnt_reg_n_0_[20] ;
- wire \data_cnt_reg_n_0_[21] ;
- wire \data_cnt_reg_n_0_[22] ;
- wire \data_cnt_reg_n_0_[23] ;
- wire \data_cnt_reg_n_0_[24] ;
- wire \data_cnt_reg_n_0_[25] ;
- wire \data_cnt_reg_n_0_[26] ;
- wire \data_cnt_reg_n_0_[27] ;
- wire \data_cnt_reg_n_0_[28] ;
- wire \data_cnt_reg_n_0_[29] ;
- wire \data_cnt_reg_n_0_[2] ;
- wire \data_cnt_reg_n_0_[30] ;
- wire \data_cnt_reg_n_0_[31] ;
- wire \data_cnt_reg_n_0_[3] ;
- wire \data_cnt_reg_n_0_[4] ;
- wire \data_cnt_reg_n_0_[5] ;
- wire \data_cnt_reg_n_0_[6] ;
- wire \data_cnt_reg_n_0_[7] ;
- wire \data_cnt_reg_n_0_[8] ;
- wire \data_cnt_reg_n_0_[9] ;
- wire [31:0]finalXOR;
- wire \finalXOR_reg[31]_i_1_n_0 ;
- wire \finalXOR_reg[31]_i_2_n_0 ;
- wire \finalXOR_reg[31]_i_3_n_0 ;
- wire [31:3]in15;
- wire [15:1]in8;
- wire [1:0]inOutReflected;
- wire inOut_reflected_reg;
- wire \inOut_reflected_reg[0]_i_1_n_0 ;
- wire \inOut_reflected_reg[1]_i_1_n_0 ;
- wire \inOut_reflected_reg[1]_i_3_n_0 ;
- wire [31:0]initial_value;
- wire initial_value_reg;
- wire \initial_value_reg[31]_i_1_n_0 ;
- wire \initial_value_reg[31]_i_3_n_0 ;
- wire \initial_value_reg[31]_i_4_n_0 ;
- wire interrupt_enable_reg_i_1_n_0;
- wire interrupt_reset_i_1_n_0;
- wire interrupt_reset_i_2_n_0;
- wire interrupt_reset_i_3_n_0;
- wire interrupt_reset_reg_n_0;
- wire [15:1]minusOp;
- wire minusOp__28_carry__0_i_1_n_0;
- wire minusOp__28_carry__0_i_2_n_0;
- wire minusOp__28_carry__0_i_3_n_0;
- wire minusOp__28_carry__0_i_4_n_0;
- wire minusOp__28_carry__0_n_0;
- wire minusOp__28_carry__0_n_1;
- wire minusOp__28_carry__0_n_2;
- wire minusOp__28_carry__0_n_3;
- wire minusOp__28_carry__1_i_1_n_0;
- wire minusOp__28_carry__1_i_2_n_0;
- wire minusOp__28_carry__1_i_3_n_0;
- wire minusOp__28_carry__1_i_4_n_0;
- wire minusOp__28_carry__1_n_0;
- wire minusOp__28_carry__1_n_1;
- wire minusOp__28_carry__1_n_2;
- wire minusOp__28_carry__1_n_3;
- wire minusOp__28_carry__2_i_1_n_0;
- wire minusOp__28_carry__2_i_2_n_0;
- wire minusOp__28_carry__2_i_3_n_0;
- wire minusOp__28_carry__2_n_2;
- wire minusOp__28_carry__2_n_3;
- wire minusOp__28_carry_i_1_n_0;
- wire minusOp__28_carry_i_2_n_0;
- wire minusOp__28_carry_i_3_n_0;
- wire minusOp__28_carry_i_4_n_0;
- wire minusOp__28_carry_n_0;
- wire minusOp__28_carry_n_1;
- wire minusOp__28_carry_n_2;
- wire minusOp__28_carry_n_3;
- wire minusOp_carry__0_i_1_n_0;
- wire minusOp_carry__0_i_2_n_0;
- wire minusOp_carry__0_i_3_n_0;
- wire minusOp_carry__0_i_4_n_0;
- wire minusOp_carry__0_n_0;
- wire minusOp_carry__0_n_1;
- wire minusOp_carry__0_n_2;
- wire minusOp_carry__0_n_3;
- wire minusOp_carry__1_i_1_n_0;
- wire minusOp_carry__1_i_2_n_0;
- wire minusOp_carry__1_i_3_n_0;
- wire minusOp_carry__1_i_4_n_0;
- wire minusOp_carry__1_n_0;
- wire minusOp_carry__1_n_1;
- wire minusOp_carry__1_n_2;
- wire minusOp_carry__1_n_3;
- wire minusOp_carry__2_i_1_n_0;
- wire minusOp_carry__2_i_2_n_0;
- wire minusOp_carry__2_i_3_n_0;
- wire minusOp_carry__2_n_2;
- wire minusOp_carry__2_n_3;
- wire minusOp_carry_i_1_n_0;
- wire minusOp_carry_i_2_n_0;
- wire minusOp_carry_i_3_n_0;
- wire minusOp_carry_i_4_n_0;
- wire minusOp_carry_n_0;
- wire minusOp_carry_n_1;
- wire minusOp_carry_n_2;
- wire minusOp_carry_n_3;
- wire [2:0]p_0_in;
- wire [1:0]p_5_in;
- wire [15:0]packet_data_cnt;
- wire \packet_data_cnt[0]_i_2_n_0 ;
- wire \packet_data_cnt[0]_i_3_n_0 ;
- wire \packet_data_cnt[0]_i_4_n_0 ;
- wire \packet_data_cnt[0]_i_5_n_0 ;
- wire \packet_data_cnt[15]_i_1_n_0 ;
- wire \packet_data_cnt[15]_i_3_n_0 ;
- wire \packet_data_cnt_reg_n_0_[0] ;
- wire \packet_data_cnt_reg_n_0_[10] ;
- wire \packet_data_cnt_reg_n_0_[11] ;
- wire \packet_data_cnt_reg_n_0_[12] ;
- wire \packet_data_cnt_reg_n_0_[13] ;
- wire \packet_data_cnt_reg_n_0_[14] ;
- wire \packet_data_cnt_reg_n_0_[15] ;
- wire \packet_data_cnt_reg_n_0_[1] ;
- wire \packet_data_cnt_reg_n_0_[2] ;
- wire \packet_data_cnt_reg_n_0_[3] ;
- wire \packet_data_cnt_reg_n_0_[4] ;
- wire \packet_data_cnt_reg_n_0_[5] ;
- wire \packet_data_cnt_reg_n_0_[6] ;
- wire \packet_data_cnt_reg_n_0_[7] ;
- wire \packet_data_cnt_reg_n_0_[8] ;
- wire \packet_data_cnt_reg_n_0_[9] ;
- wire packet_last_word3_out;
- wire packet_last_word_i_1_n_0;
- wire packet_last_word_i_3_n_0;
- wire packet_last_word_i_4_n_0;
- wire packet_last_word_reg_n_0;
- wire [15:0]packet_number_reg;
- wire packet_number_reg_1;
- wire [15:0]packet_size_reg;
- wire \packet_size_reg[15]_i_1_n_0 ;
- wire [15:0]packets_cnt;
- wire \packets_cnt[15]_i_1_n_0 ;
- wire \packets_cnt[15]_i_3_n_0 ;
- wire \packets_cnt[15]_i_4_n_0 ;
- wire \packets_cnt[15]_i_5_n_0 ;
- wire \packets_cnt[15]_i_6_n_0 ;
- wire \packets_cnt[15]_i_7_n_0 ;
- wire \packets_cnt_reg_n_0_[0] ;
- wire \packets_cnt_reg_n_0_[10] ;
- wire \packets_cnt_reg_n_0_[11] ;
- wire \packets_cnt_reg_n_0_[12] ;
- wire \packets_cnt_reg_n_0_[13] ;
- wire \packets_cnt_reg_n_0_[14] ;
- wire \packets_cnt_reg_n_0_[15] ;
- wire \packets_cnt_reg_n_0_[1] ;
- wire \packets_cnt_reg_n_0_[2] ;
- wire \packets_cnt_reg_n_0_[3] ;
- wire \packets_cnt_reg_n_0_[4] ;
- wire \packets_cnt_reg_n_0_[5] ;
- wire \packets_cnt_reg_n_0_[6] ;
- wire \packets_cnt_reg_n_0_[7] ;
- wire \packets_cnt_reg_n_0_[8] ;
- wire \packets_cnt_reg_n_0_[9] ;
- wire plusOp__28_carry__0_n_0;
- wire plusOp__28_carry__0_n_1;
- wire plusOp__28_carry__0_n_2;
- wire plusOp__28_carry__0_n_3;
- wire plusOp__28_carry__1_n_0;
- wire plusOp__28_carry__1_n_1;
- wire plusOp__28_carry__1_n_2;
- wire plusOp__28_carry__1_n_3;
- wire plusOp__28_carry__2_n_2;
- wire plusOp__28_carry__2_n_3;
- wire plusOp__28_carry_n_0;
- wire plusOp__28_carry_n_1;
- wire plusOp__28_carry_n_2;
- wire plusOp__28_carry_n_3;
- wire plusOp_carry__0_n_0;
- wire plusOp_carry__0_n_1;
- wire plusOp_carry__0_n_2;
- wire plusOp_carry__0_n_3;
- wire plusOp_carry__1_n_0;
- wire plusOp_carry__1_n_1;
- wire plusOp_carry__1_n_2;
- wire plusOp_carry__1_n_3;
- wire plusOp_carry__2_n_2;
- wire plusOp_carry__2_n_3;
- wire plusOp_carry_n_0;
- wire plusOp_carry_n_1;
- wire plusOp_carry_n_2;
- wire plusOp_carry_n_3;
- wire [31:0]polynomial;
- wire polynomial_reg;
- wire \polynomial_reg[31]_i_2_n_0 ;
- wire \polynomial_reg[31]_i_3_n_0 ;
- wire [31:0]read_addr_cnt;
- wire read_addr_cnt0_carry__0_n_0;
- wire read_addr_cnt0_carry__0_n_1;
- wire read_addr_cnt0_carry__0_n_2;
- wire read_addr_cnt0_carry__0_n_3;
- wire read_addr_cnt0_carry__0_n_4;
- wire read_addr_cnt0_carry__0_n_5;
- wire read_addr_cnt0_carry__0_n_6;
- wire read_addr_cnt0_carry__0_n_7;
- wire read_addr_cnt0_carry__1_n_0;
- wire read_addr_cnt0_carry__1_n_1;
- wire read_addr_cnt0_carry__1_n_2;
- wire read_addr_cnt0_carry__1_n_3;
- wire read_addr_cnt0_carry__1_n_4;
- wire read_addr_cnt0_carry__1_n_5;
- wire read_addr_cnt0_carry__1_n_6;
- wire read_addr_cnt0_carry__1_n_7;
- wire read_addr_cnt0_carry__2_n_0;
- wire read_addr_cnt0_carry__2_n_1;
- wire read_addr_cnt0_carry__2_n_2;
- wire read_addr_cnt0_carry__2_n_3;
- wire read_addr_cnt0_carry__2_n_4;
- wire read_addr_cnt0_carry__2_n_5;
- wire read_addr_cnt0_carry__2_n_6;
- wire read_addr_cnt0_carry__2_n_7;
- wire read_addr_cnt0_carry__3_n_0;
- wire read_addr_cnt0_carry__3_n_1;
- wire read_addr_cnt0_carry__3_n_2;
- wire read_addr_cnt0_carry__3_n_3;
- wire read_addr_cnt0_carry__3_n_4;
- wire read_addr_cnt0_carry__3_n_5;
- wire read_addr_cnt0_carry__3_n_6;
- wire read_addr_cnt0_carry__3_n_7;
- wire read_addr_cnt0_carry__4_n_0;
- wire read_addr_cnt0_carry__4_n_1;
- wire read_addr_cnt0_carry__4_n_2;
- wire read_addr_cnt0_carry__4_n_3;
- wire read_addr_cnt0_carry__4_n_4;
- wire read_addr_cnt0_carry__4_n_5;
- wire read_addr_cnt0_carry__4_n_6;
- wire read_addr_cnt0_carry__4_n_7;
- wire read_addr_cnt0_carry__5_n_0;
- wire read_addr_cnt0_carry__5_n_1;
- wire read_addr_cnt0_carry__5_n_2;
- wire read_addr_cnt0_carry__5_n_3;
- wire read_addr_cnt0_carry__5_n_4;
- wire read_addr_cnt0_carry__5_n_5;
- wire read_addr_cnt0_carry__5_n_6;
- wire read_addr_cnt0_carry__5_n_7;
- wire read_addr_cnt0_carry__6_n_7;
- wire read_addr_cnt0_carry_i_1_n_0;
- wire read_addr_cnt0_carry_n_0;
- wire read_addr_cnt0_carry_n_1;
- wire read_addr_cnt0_carry_n_2;
- wire read_addr_cnt0_carry_n_3;
- wire read_addr_cnt0_carry_n_4;
- wire read_addr_cnt0_carry_n_5;
- wire read_addr_cnt0_carry_n_6;
- wire read_addr_cnt0_carry_n_7;
- wire \read_addr_cnt[31]_i_1_n_0 ;
- wire \read_addr_cnt[31]_i_3_n_0 ;
- wire \read_addr_cnt[31]_i_4_n_0 ;
- wire \read_addr_cnt_reg_n_0_[0] ;
- wire \read_addr_cnt_reg_n_0_[10] ;
- wire \read_addr_cnt_reg_n_0_[11] ;
- wire \read_addr_cnt_reg_n_0_[12] ;
- wire \read_addr_cnt_reg_n_0_[13] ;
- wire \read_addr_cnt_reg_n_0_[14] ;
- wire \read_addr_cnt_reg_n_0_[15] ;
- wire \read_addr_cnt_reg_n_0_[16] ;
- wire \read_addr_cnt_reg_n_0_[17] ;
- wire \read_addr_cnt_reg_n_0_[18] ;
- wire \read_addr_cnt_reg_n_0_[19] ;
- wire \read_addr_cnt_reg_n_0_[1] ;
- wire \read_addr_cnt_reg_n_0_[20] ;
- wire \read_addr_cnt_reg_n_0_[21] ;
- wire \read_addr_cnt_reg_n_0_[22] ;
- wire \read_addr_cnt_reg_n_0_[23] ;
- wire \read_addr_cnt_reg_n_0_[24] ;
- wire \read_addr_cnt_reg_n_0_[25] ;
- wire \read_addr_cnt_reg_n_0_[26] ;
- wire \read_addr_cnt_reg_n_0_[27] ;
- wire \read_addr_cnt_reg_n_0_[28] ;
- wire \read_addr_cnt_reg_n_0_[29] ;
- wire \read_addr_cnt_reg_n_0_[2] ;
- wire \read_addr_cnt_reg_n_0_[30] ;
- wire \read_addr_cnt_reg_n_0_[31] ;
- wire \read_addr_cnt_reg_n_0_[3] ;
- wire \read_addr_cnt_reg_n_0_[4] ;
- wire \read_addr_cnt_reg_n_0_[5] ;
- wire \read_addr_cnt_reg_n_0_[6] ;
- wire \read_addr_cnt_reg_n_0_[7] ;
- wire \read_addr_cnt_reg_n_0_[8] ;
- wire \read_addr_cnt_reg_n_0_[9] ;
- wire [31:0]read_address_reg;
- wire \read_address_reg[31]_i_2_n_0 ;
- wire read_address_reg_0;
- wire \read_state[0]_i_1_n_0 ;
- wire \read_state[1]_i_1_n_0 ;
- wire \read_state[2]_i_10_n_0 ;
- wire \read_state[2]_i_11_n_0 ;
- wire \read_state[2]_i_12_n_0 ;
- wire \read_state[2]_i_13_n_0 ;
- wire \read_state[2]_i_1_n_0 ;
- wire \read_state[2]_i_2_n_0 ;
- wire \read_state[2]_i_3_n_0 ;
- wire \read_state[2]_i_4_n_0 ;
- wire \read_state[2]_i_5_n_0 ;
- wire \read_state[2]_i_6_n_0 ;
- wire \read_state[2]_i_7_n_0 ;
- wire \read_state[2]_i_8_n_0 ;
- wire \read_state[2]_i_9_n_0 ;
- wire [2:0]read_state_reg;
- wire run_reg_clear_i_1_n_0;
- wire run_reg_clear_i_2_n_0;
- wire run_reg_clear_i_3_n_0;
- wire run_reg_clear_reg_n_0;
- wire run_reg_i_1_n_0;
- wire run_reg_set_i_1_n_0;
- wire run_reg_set_i_2_n_0;
- wire run_reg_set_reg_n_0;
- wire [31:0]write_addr;
- wire write_addr0_carry__0_n_0;
- wire write_addr0_carry__0_n_1;
- wire write_addr0_carry__0_n_2;
- wire write_addr0_carry__0_n_3;
- wire write_addr0_carry__1_n_0;
- wire write_addr0_carry__1_n_1;
- wire write_addr0_carry__1_n_2;
- wire write_addr0_carry__1_n_3;
- wire write_addr0_carry__2_n_0;
- wire write_addr0_carry__2_n_1;
- wire write_addr0_carry__2_n_2;
- wire write_addr0_carry__2_n_3;
- wire write_addr0_carry__3_n_0;
- wire write_addr0_carry__3_n_1;
- wire write_addr0_carry__3_n_2;
- wire write_addr0_carry__3_n_3;
- wire write_addr0_carry__4_n_0;
- wire write_addr0_carry__4_n_1;
- wire write_addr0_carry__4_n_2;
- wire write_addr0_carry__4_n_3;
- wire write_addr0_carry__5_n_0;
- wire write_addr0_carry__5_n_1;
- wire write_addr0_carry__5_n_2;
- wire write_addr0_carry__5_n_3;
- wire write_addr0_carry_i_1_n_0;
- wire write_addr0_carry_n_0;
- wire write_addr0_carry_n_1;
- wire write_addr0_carry_n_2;
- wire write_addr0_carry_n_3;
- wire \write_addr[31]_i_1_n_0 ;
- wire \write_addr_reg_n_0_[0] ;
- wire \write_addr_reg_n_0_[10] ;
- wire \write_addr_reg_n_0_[11] ;
- wire \write_addr_reg_n_0_[12] ;
- wire \write_addr_reg_n_0_[13] ;
- wire \write_addr_reg_n_0_[14] ;
- wire \write_addr_reg_n_0_[15] ;
- wire \write_addr_reg_n_0_[16] ;
- wire \write_addr_reg_n_0_[17] ;
- wire \write_addr_reg_n_0_[18] ;
- wire \write_addr_reg_n_0_[19] ;
- wire \write_addr_reg_n_0_[1] ;
- wire \write_addr_reg_n_0_[20] ;
- wire \write_addr_reg_n_0_[21] ;
- wire \write_addr_reg_n_0_[22] ;
- wire \write_addr_reg_n_0_[23] ;
- wire \write_addr_reg_n_0_[24] ;
- wire \write_addr_reg_n_0_[25] ;
- wire \write_addr_reg_n_0_[26] ;
- wire \write_addr_reg_n_0_[27] ;
- wire \write_addr_reg_n_0_[28] ;
- wire \write_addr_reg_n_0_[29] ;
- wire \write_addr_reg_n_0_[2] ;
- wire \write_addr_reg_n_0_[30] ;
- wire \write_addr_reg_n_0_[31] ;
- wire \write_addr_reg_n_0_[3] ;
- wire \write_addr_reg_n_0_[4] ;
- wire \write_addr_reg_n_0_[5] ;
- wire \write_addr_reg_n_0_[6] ;
- wire \write_addr_reg_n_0_[7] ;
- wire \write_addr_reg_n_0_[8] ;
- wire \write_addr_reg_n_0_[9] ;
- wire [31:0]write_address_reg;
- wire \write_address_reg[31]_i_2_n_0 ;
- wire write_address_reg_2;
- wire \write_state[0]_i_1_n_0 ;
- wire \write_state[1]_i_1_n_0 ;
- wire \write_state[2]_i_10_n_0 ;
- wire \write_state[2]_i_11_n_0 ;
- wire \write_state[2]_i_12_n_0 ;
- wire \write_state[2]_i_1_n_0 ;
- wire \write_state[2]_i_3_n_0 ;
- wire \write_state[2]_i_4_n_0 ;
- wire \write_state[2]_i_5_n_0 ;
- wire \write_state[2]_i_6_n_0 ;
- wire \write_state[2]_i_7_n_0 ;
- wire \write_state[2]_i_8_n_0 ;
- wire \write_state[2]_i_9_n_0 ;
- wire [2:0]write_state_reg;
- wire NLW_L_CARRYCASCOUT_UNCONNECTED;
- wire NLW_L_MULTSIGNOUT_UNCONNECTED;
- wire NLW_L_OVERFLOW_UNCONNECTED;
- wire NLW_L_PATTERNBDETECT_UNCONNECTED;
- wire NLW_L_PATTERNDETECT_UNCONNECTED;
- wire NLW_L_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_L_ACOUT_UNCONNECTED;
- wire [17:0]NLW_L_BCOUT_UNCONNECTED;
- wire [3:0]NLW_L_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_L_P_UNCONNECTED;
- wire [47:0]NLW_L_PCOUT_UNCONNECTED;
- wire [3:2]\NLW_M_AXI_ARLEN_reg[3]_i_11_CO_UNCONNECTED ;
- wire [3:3]\NLW_M_AXI_ARLEN_reg[3]_i_11_O_UNCONNECTED ;
- wire [2:0]\NLW_M_AXI_ARLEN_reg[3]_i_12_O_UNCONNECTED ;
- wire [3:0]NLW_M_AXI_AWVALID2_carry_O_UNCONNECTED;
- wire [3:0]NLW_M_AXI_AWVALID2_carry__0_O_UNCONNECTED;
- wire [3:3]NLW_M_AXI_AWVALID2_carry__1_CO_UNCONNECTED;
- wire [3:0]NLW_M_AXI_AWVALID2_carry__1_O_UNCONNECTED;
- wire [3:2]NLW_M_AXI_AWVALID2_carry__1_i_4_CO_UNCONNECTED;
- wire [3:3]NLW_M_AXI_AWVALID2_carry__1_i_4_O_UNCONNECTED;
- wire [3:3]NLW___0_carry__6_CO_UNCONNECTED;
- wire [3:2]NLW___93_carry__6_CO_UNCONNECTED;
- wire [3:3]NLW___93_carry__6_O_UNCONNECTED;
- wire [3:2]NLW_minusOp__28_carry__2_CO_UNCONNECTED;
- wire [3:3]NLW_minusOp__28_carry__2_O_UNCONNECTED;
- wire [3:2]NLW_minusOp_carry__2_CO_UNCONNECTED;
- wire [3:3]NLW_minusOp_carry__2_O_UNCONNECTED;
- wire [3:2]NLW_plusOp__28_carry__2_CO_UNCONNECTED;
- wire [3:3]NLW_plusOp__28_carry__2_O_UNCONNECTED;
- wire [3:2]NLW_plusOp_carry__2_CO_UNCONNECTED;
- wire [3:3]NLW_plusOp_carry__2_O_UNCONNECTED;
- wire [3:0]NLW_read_addr_cnt0_carry__6_CO_UNCONNECTED;
- wire [3:1]NLW_read_addr_cnt0_carry__6_O_UNCONNECTED;
- wire [3:0]NLW_write_addr0_carry__6_CO_UNCONNECTED;
- wire [3:1]NLW_write_addr0_carry__6_O_UNCONNECTED;
-
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT5 #(
- .INIT(32'h00000800))
- INTERRUPT_INST_0
- (.I0(INTERRUPT_INST_0_i_1_n_0),
- .I1(p_5_in[1]),
- .I2(read_state_reg[0]),
- .I3(read_state_reg[2]),
- .I4(read_state_reg[1]),
- .O(INTERRUPT));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT3 #(
- .INIT(8'h04))
- INTERRUPT_INST_0_i_1
- (.I0(write_state_reg[0]),
- .I1(write_state_reg[2]),
- .I2(write_state_reg[1]),
- .O(INTERRUPT_INST_0_i_1_n_0));
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(0),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(0),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(0),
- .BREG(0),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(1),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(0),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("MULTIPLY"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- L
- (.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,A}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_L_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b0,1'b0,B}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_L_BCOUT_UNCONNECTED[17:0]),
- .C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_L_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_L_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(1'b0),
- .CLK(1'b0),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_L_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
- .OVERFLOW(NLW_L_OVERFLOW_UNCONNECTED),
- .P({NLW_L_P_UNCONNECTED[47:32],L__0}),
- .PATTERNBDETECT(NLW_L_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_L_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_L_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(1'b0),
- .UNDERFLOW(NLW_L_UNDERFLOW_UNCONNECTED));
- LUT1 #(
- .INIT(2'h1))
- L_i_1
- (.I0(packet_number_reg[0]),
- .O(B[0]));
- LUT1 #(
- .INIT(2'h1))
- L_i_2
- (.I0(packet_size_reg[0]),
- .O(A[0]));
- LUT2 #(
- .INIT(4'h8))
- M_AXIS_TLAST_INST_0
- (.I0(M_AXI_RVALID),
- .I1(packet_last_word_reg_n_0),
- .O(M_AXIS_TLAST));
- LUT3 #(
- .INIT(8'h02))
- \M_AXI_ARADDR[31]_i_1
- (.I0(\M_AXI_ARADDR[31]_i_2_n_0 ),
- .I1(read_state_reg[2]),
- .I2(read_state_reg[1]),
- .O(\M_AXI_ARADDR[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT5 #(
- .INIT(32'hAAAAAAA8))
- \M_AXI_ARADDR[31]_i_2
- (.I0(read_state_reg[0]),
- .I1(FIFO_NUM_FREE[3]),
- .I2(FIFO_NUM_FREE[2]),
- .I3(FIFO_NUM_FREE[0]),
- .I4(FIFO_NUM_FREE[1]),
- .O(\M_AXI_ARADDR[31]_i_2_n_0 ));
- FDRE \M_AXI_ARADDR_reg[0]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[0] ),
- .Q(M_AXI_ARADDR[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[10]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[10] ),
- .Q(M_AXI_ARADDR[10]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[11]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[11] ),
- .Q(M_AXI_ARADDR[11]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[12]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[12] ),
- .Q(M_AXI_ARADDR[12]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[13]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[13] ),
- .Q(M_AXI_ARADDR[13]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[14]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[14] ),
- .Q(M_AXI_ARADDR[14]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[15]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[15] ),
- .Q(M_AXI_ARADDR[15]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[16]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[16] ),
- .Q(M_AXI_ARADDR[16]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[17]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[17] ),
- .Q(M_AXI_ARADDR[17]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[18]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[18] ),
- .Q(M_AXI_ARADDR[18]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[19]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[19] ),
- .Q(M_AXI_ARADDR[19]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[1]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[1] ),
- .Q(M_AXI_ARADDR[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[20]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[20] ),
- .Q(M_AXI_ARADDR[20]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[21]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[21] ),
- .Q(M_AXI_ARADDR[21]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[22]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[22] ),
- .Q(M_AXI_ARADDR[22]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[23]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[23] ),
- .Q(M_AXI_ARADDR[23]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[24]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[24] ),
- .Q(M_AXI_ARADDR[24]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[25]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[25] ),
- .Q(M_AXI_ARADDR[25]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[26]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[26] ),
- .Q(M_AXI_ARADDR[26]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[27]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[27] ),
- .Q(M_AXI_ARADDR[27]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[28]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[28] ),
- .Q(M_AXI_ARADDR[28]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[29]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[29] ),
- .Q(M_AXI_ARADDR[29]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[2]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[2] ),
- .Q(M_AXI_ARADDR[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[30]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[30] ),
- .Q(M_AXI_ARADDR[30]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[31]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[31] ),
- .Q(M_AXI_ARADDR[31]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[3]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[3] ),
- .Q(M_AXI_ARADDR[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[4]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[4] ),
- .Q(M_AXI_ARADDR[4]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[5]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[5] ),
- .Q(M_AXI_ARADDR[5]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[6]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[6] ),
- .Q(M_AXI_ARADDR[6]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[7]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[7] ),
- .Q(M_AXI_ARADDR[7]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[8]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[8] ),
- .Q(M_AXI_ARADDR[8]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[9]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\read_addr_cnt_reg_n_0_[9] ),
- .Q(M_AXI_ARADDR[9]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \M_AXI_ARLEN[0]_i_1
- (.I0(\data_cnt_reg[0]__0_n_0 ),
- .I1(\M_AXI_ARLEN[3]_i_2_n_0 ),
- .I2(\M_AXI_ARLEN[3]_i_3_n_0 ),
- .I3(\M_AXI_ARLEN[3]_i_4_n_0 ),
- .O(\M_AXI_ARLEN[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \M_AXI_ARLEN[1]_i_1
- (.I0(\data_cnt_reg[1]__0_n_0 ),
- .I1(\M_AXI_ARLEN[3]_i_2_n_0 ),
- .I2(\M_AXI_ARLEN[3]_i_3_n_0 ),
- .I3(\M_AXI_ARLEN[3]_i_4_n_0 ),
- .O(\M_AXI_ARLEN[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \M_AXI_ARLEN[2]_i_1
- (.I0(\data_cnt_reg[2]__0_n_0 ),
- .I1(\M_AXI_ARLEN[3]_i_2_n_0 ),
- .I2(\M_AXI_ARLEN[3]_i_3_n_0 ),
- .I3(\M_AXI_ARLEN[3]_i_4_n_0 ),
- .O(\M_AXI_ARLEN[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \M_AXI_ARLEN[3]_i_1
- (.I0(\data_cnt_reg[3]__0_n_0 ),
- .I1(\M_AXI_ARLEN[3]_i_2_n_0 ),
- .I2(\M_AXI_ARLEN[3]_i_3_n_0 ),
- .I3(\M_AXI_ARLEN[3]_i_4_n_0 ),
- .O(\M_AXI_ARLEN[3]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \M_AXI_ARLEN[3]_i_10
- (.I0(\M_AXI_ARLEN_reg[3]_i_15_n_6 ),
- .I1(\M_AXI_ARLEN_reg[3]_i_5_n_7 ),
- .I2(\M_AXI_ARLEN_reg[3]_i_9_n_4 ),
- .I3(\M_AXI_ARLEN_reg[3]_i_15_n_4 ),
- .O(\M_AXI_ARLEN[3]_i_10_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \M_AXI_ARLEN[3]_i_13
- (.I0(\M_AXI_ARLEN_reg[3]_i_9_n_7 ),
- .I1(\M_AXI_ARLEN_reg[3]_i_16_n_7 ),
- .I2(\M_AXI_ARLEN_reg[3]_i_16_n_5 ),
- .I3(\M_AXI_ARLEN_reg[3]_i_11_n_7 ),
- .O(\M_AXI_ARLEN[3]_i_13_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \M_AXI_ARLEN[3]_i_14
- (.I0(\M_AXI_ARLEN_reg[3]_i_16_n_6 ),
- .I1(\M_AXI_ARLEN_reg[3]_i_6_n_6 ),
- .I2(\M_AXI_ARLEN_reg[3]_i_15_n_5 ),
- .I3(\M_AXI_ARLEN_reg[3]_i_5_n_4 ),
- .O(\M_AXI_ARLEN[3]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \M_AXI_ARLEN[3]_i_2
- (.I0(\M_AXI_ARLEN_reg[3]_i_5_n_6 ),
- .I1(\M_AXI_ARLEN_reg[3]_i_6_n_4 ),
- .I2(\M_AXI_ARLEN_reg[3]_i_7_n_5 ),
- .I3(\M_AXI_ARLEN_reg[3]_i_6_n_5 ),
- .I4(\M_AXI_ARLEN[3]_i_8_n_0 ),
- .O(\M_AXI_ARLEN[3]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \M_AXI_ARLEN[3]_i_3
- (.I0(\M_AXI_ARLEN_reg[3]_i_6_n_7 ),
- .I1(\M_AXI_ARLEN_reg[3]_i_9_n_5 ),
- .I2(\M_AXI_ARLEN_reg[3]_i_7_n_7 ),
- .I3(\M_AXI_ARLEN_reg[3]_i_5_n_5 ),
- .I4(\M_AXI_ARLEN[3]_i_10_n_0 ),
- .O(\M_AXI_ARLEN[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \M_AXI_ARLEN[3]_i_4
- (.I0(\M_AXI_ARLEN_reg[3]_i_11_n_6 ),
- .I1(\M_AXI_ARLEN_reg[3]_i_7_n_6 ),
- .I2(\M_AXI_ARLEN_reg[3]_i_12_n_4 ),
- .I3(\M_AXI_ARLEN_reg[3]_i_11_n_5 ),
- .I4(\M_AXI_ARLEN[3]_i_13_n_0 ),
- .I5(\M_AXI_ARLEN[3]_i_14_n_0 ),
- .O(\M_AXI_ARLEN[3]_i_4_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \M_AXI_ARLEN[3]_i_8
- (.I0(\M_AXI_ARLEN_reg[3]_i_9_n_6 ),
- .I1(\M_AXI_ARLEN_reg[3]_i_7_n_4 ),
- .I2(\M_AXI_ARLEN_reg[3]_i_16_n_4 ),
- .I3(\M_AXI_ARLEN_reg[3]_i_15_n_7 ),
- .O(\M_AXI_ARLEN[3]_i_8_n_0 ));
- FDRE \M_AXI_ARLEN_reg[0]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\M_AXI_ARLEN[0]_i_1_n_0 ),
- .Q(M_AXI_ARLEN[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARLEN_reg[1]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\M_AXI_ARLEN[1]_i_1_n_0 ),
- .Q(M_AXI_ARLEN[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARLEN_reg[2]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\M_AXI_ARLEN[2]_i_1_n_0 ),
- .Q(M_AXI_ARLEN[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_ARLEN_reg[3]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(\M_AXI_ARLEN[3]_i_1_n_0 ),
- .Q(M_AXI_ARLEN[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 \M_AXI_ARLEN_reg[3]_i_11
- (.CI(\M_AXI_ARLEN_reg[3]_i_7_n_0 ),
- .CO({\NLW_M_AXI_ARLEN_reg[3]_i_11_CO_UNCONNECTED [3:2],\M_AXI_ARLEN_reg[3]_i_11_n_2 ,\M_AXI_ARLEN_reg[3]_i_11_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\NLW_M_AXI_ARLEN_reg[3]_i_11_O_UNCONNECTED [3],\M_AXI_ARLEN_reg[3]_i_11_n_5 ,\M_AXI_ARLEN_reg[3]_i_11_n_6 ,\M_AXI_ARLEN_reg[3]_i_11_n_7 }),
- .S({1'b0,\data_cnt_reg[31]__0_n_0 ,\data_cnt_reg[30]__0_n_0 ,\data_cnt_reg[29]__0_n_0 }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 \M_AXI_ARLEN_reg[3]_i_12
- (.CI(1'b0),
- .CO({\M_AXI_ARLEN_reg[3]_i_12_n_0 ,\M_AXI_ARLEN_reg[3]_i_12_n_1 ,\M_AXI_ARLEN_reg[3]_i_12_n_2 ,\M_AXI_ARLEN_reg[3]_i_12_n_3 }),
- .CYINIT(\data_cnt_reg[0]__0_n_0 ),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\M_AXI_ARLEN_reg[3]_i_12_n_4 ,\NLW_M_AXI_ARLEN_reg[3]_i_12_O_UNCONNECTED [2:0]}),
- .S({\data_cnt_reg[4]__0_n_0 ,\data_cnt_reg[3]__0_n_0 ,\data_cnt_reg[2]__0_n_0 ,\data_cnt_reg[1]__0_n_0 }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 \M_AXI_ARLEN_reg[3]_i_15
- (.CI(\M_AXI_ARLEN_reg[3]_i_6_n_0 ),
- .CO({\M_AXI_ARLEN_reg[3]_i_15_n_0 ,\M_AXI_ARLEN_reg[3]_i_15_n_1 ,\M_AXI_ARLEN_reg[3]_i_15_n_2 ,\M_AXI_ARLEN_reg[3]_i_15_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\M_AXI_ARLEN_reg[3]_i_15_n_4 ,\M_AXI_ARLEN_reg[3]_i_15_n_5 ,\M_AXI_ARLEN_reg[3]_i_15_n_6 ,\M_AXI_ARLEN_reg[3]_i_15_n_7 }),
- .S({\data_cnt_reg[20]__0_n_0 ,\data_cnt_reg[19]__0_n_0 ,\data_cnt_reg[18]__0_n_0 ,\data_cnt_reg[17]__0_n_0 }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 \M_AXI_ARLEN_reg[3]_i_16
- (.CI(\M_AXI_ARLEN_reg[3]_i_9_n_0 ),
- .CO({\M_AXI_ARLEN_reg[3]_i_16_n_0 ,\M_AXI_ARLEN_reg[3]_i_16_n_1 ,\M_AXI_ARLEN_reg[3]_i_16_n_2 ,\M_AXI_ARLEN_reg[3]_i_16_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\M_AXI_ARLEN_reg[3]_i_16_n_4 ,\M_AXI_ARLEN_reg[3]_i_16_n_5 ,\M_AXI_ARLEN_reg[3]_i_16_n_6 ,\M_AXI_ARLEN_reg[3]_i_16_n_7 }),
- .S({\data_cnt_reg[12]__0_n_0 ,\data_cnt_reg[11]__0_n_0 ,\data_cnt_reg[10]__0_n_0 ,\data_cnt_reg[9]__0_n_0 }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 \M_AXI_ARLEN_reg[3]_i_5
- (.CI(\M_AXI_ARLEN_reg[3]_i_15_n_0 ),
- .CO({\M_AXI_ARLEN_reg[3]_i_5_n_0 ,\M_AXI_ARLEN_reg[3]_i_5_n_1 ,\M_AXI_ARLEN_reg[3]_i_5_n_2 ,\M_AXI_ARLEN_reg[3]_i_5_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\M_AXI_ARLEN_reg[3]_i_5_n_4 ,\M_AXI_ARLEN_reg[3]_i_5_n_5 ,\M_AXI_ARLEN_reg[3]_i_5_n_6 ,\M_AXI_ARLEN_reg[3]_i_5_n_7 }),
- .S({\data_cnt_reg[24]__0_n_0 ,\data_cnt_reg[23]__0_n_0 ,\data_cnt_reg[22]__0_n_0 ,\data_cnt_reg[21]__0_n_0 }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 \M_AXI_ARLEN_reg[3]_i_6
- (.CI(\M_AXI_ARLEN_reg[3]_i_16_n_0 ),
- .CO({\M_AXI_ARLEN_reg[3]_i_6_n_0 ,\M_AXI_ARLEN_reg[3]_i_6_n_1 ,\M_AXI_ARLEN_reg[3]_i_6_n_2 ,\M_AXI_ARLEN_reg[3]_i_6_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\M_AXI_ARLEN_reg[3]_i_6_n_4 ,\M_AXI_ARLEN_reg[3]_i_6_n_5 ,\M_AXI_ARLEN_reg[3]_i_6_n_6 ,\M_AXI_ARLEN_reg[3]_i_6_n_7 }),
- .S({\data_cnt_reg[16]__0_n_0 ,\data_cnt_reg[15]__0_n_0 ,\data_cnt_reg[14]__0_n_0 ,\data_cnt_reg[13]__0_n_0 }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 \M_AXI_ARLEN_reg[3]_i_7
- (.CI(\M_AXI_ARLEN_reg[3]_i_5_n_0 ),
- .CO({\M_AXI_ARLEN_reg[3]_i_7_n_0 ,\M_AXI_ARLEN_reg[3]_i_7_n_1 ,\M_AXI_ARLEN_reg[3]_i_7_n_2 ,\M_AXI_ARLEN_reg[3]_i_7_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\M_AXI_ARLEN_reg[3]_i_7_n_4 ,\M_AXI_ARLEN_reg[3]_i_7_n_5 ,\M_AXI_ARLEN_reg[3]_i_7_n_6 ,\M_AXI_ARLEN_reg[3]_i_7_n_7 }),
- .S({\data_cnt_reg[28]__0_n_0 ,\data_cnt_reg[27]__0_n_0 ,\data_cnt_reg[26]__0_n_0 ,\data_cnt_reg[25]__0_n_0 }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 \M_AXI_ARLEN_reg[3]_i_9
- (.CI(\M_AXI_ARLEN_reg[3]_i_12_n_0 ),
- .CO({\M_AXI_ARLEN_reg[3]_i_9_n_0 ,\M_AXI_ARLEN_reg[3]_i_9_n_1 ,\M_AXI_ARLEN_reg[3]_i_9_n_2 ,\M_AXI_ARLEN_reg[3]_i_9_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\M_AXI_ARLEN_reg[3]_i_9_n_4 ,\M_AXI_ARLEN_reg[3]_i_9_n_5 ,\M_AXI_ARLEN_reg[3]_i_9_n_6 ,\M_AXI_ARLEN_reg[3]_i_9_n_7 }),
- .S({\data_cnt_reg[8]__0_n_0 ,\data_cnt_reg[7]__0_n_0 ,\data_cnt_reg[6]__0_n_0 ,\data_cnt_reg[5]__0_n_0 }));
- LUT6 #(
- .INIT(64'hFFDDFFFF0000000C))
- M_AXI_ARVALID_i_1
- (.I0(M_AXI_ARREADY),
- .I1(read_state_reg[0]),
- .I2(M_AXI_ARVALID_i_2_n_0),
- .I3(read_state_reg[2]),
- .I4(read_state_reg[1]),
- .I5(M_AXI_ARVALID),
- .O(M_AXI_ARVALID_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h0001))
- M_AXI_ARVALID_i_2
- (.I0(FIFO_NUM_FREE[1]),
- .I1(FIFO_NUM_FREE[0]),
- .I2(FIFO_NUM_FREE[2]),
- .I3(FIFO_NUM_FREE[3]),
- .O(M_AXI_ARVALID_i_2_n_0));
- FDRE #(
- .INIT(1'b0))
- M_AXI_ARVALID_reg
- (.C(CLK),
- .CE(1'b1),
- .D(M_AXI_ARVALID_i_1_n_0),
- .Q(M_AXI_ARVALID),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h0000FF04))
- \M_AXI_AWADDR[31]_i_1
- (.I0(\M_AXI_AWADDR[31]_i_2_n_0 ),
- .I1(\M_AXI_AWADDR[31]_i_3_n_0 ),
- .I2(\M_AXI_AWADDR[31]_i_4_n_0 ),
- .I3(M_AXI_AWVALID_i_4_n_0),
- .I4(M_AXI_AWVALID_i_3_n_0),
- .O(\M_AXI_AWADDR[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \M_AXI_AWADDR[31]_i_2
- (.I0(M_AXI_AWVALID2_carry_i_5_n_6),
- .I1(M_AXI_AWVALID2_carry_i_5_n_5),
- .I2(M_AXI_AWVALID2_carry_i_5_n_7),
- .I3(M_AXI_AWVALID2_carry__0_i_6_n_6),
- .I4(M_AXI_AWVALID2_carry__0_i_6_n_5),
- .I5(M_AXI_AWVALID2_carry__0_i_6_n_4),
- .O(\M_AXI_AWADDR[31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h01))
- \M_AXI_AWADDR[31]_i_3
- (.I0(M_AXI_AWVALID2_carry__0_i_7_n_7),
- .I1(M_AXI_AWVALID2_carry_i_5_n_4),
- .I2(M_AXI_AWVALID2_carry__0_i_7_n_6),
- .O(\M_AXI_AWADDR[31]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \M_AXI_AWADDR[31]_i_4
- (.I0(\M_AXI_AWADDR[31]_i_5_n_0 ),
- .I1(M_AXI_AWVALID2_carry_i_6_n_5),
- .I2(M_AXI_AWVALID2_carry_i_6_n_6),
- .I3(M_AXI_AWVALID_i_8_n_0),
- .I4(M_AXI_AWVALID_i_7_n_0),
- .I5(M_AXI_AWVALID_i_6_n_0),
- .O(\M_AXI_AWADDR[31]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT2 #(
- .INIT(4'hE))
- \M_AXI_AWADDR[31]_i_5
- (.I0(M_AXI_AWVALID2_carry__1_i_4_n_6),
- .I1(M_AXI_AWVALID2_carry__1_i_4_n_5),
- .O(\M_AXI_AWADDR[31]_i_5_n_0 ));
- FDRE \M_AXI_AWADDR_reg[0]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[0] ),
- .Q(M_AXI_AWADDR[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[10]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[10] ),
- .Q(M_AXI_AWADDR[10]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[11]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[11] ),
- .Q(M_AXI_AWADDR[11]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[12]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[12] ),
- .Q(M_AXI_AWADDR[12]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[13]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[13] ),
- .Q(M_AXI_AWADDR[13]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[14]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[14] ),
- .Q(M_AXI_AWADDR[14]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[15]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[15] ),
- .Q(M_AXI_AWADDR[15]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[16]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[16] ),
- .Q(M_AXI_AWADDR[16]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[17]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[17] ),
- .Q(M_AXI_AWADDR[17]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[18]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[18] ),
- .Q(M_AXI_AWADDR[18]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[19]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[19] ),
- .Q(M_AXI_AWADDR[19]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[1]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[1] ),
- .Q(M_AXI_AWADDR[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[20]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[20] ),
- .Q(M_AXI_AWADDR[20]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[21]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[21] ),
- .Q(M_AXI_AWADDR[21]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[22]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[22] ),
- .Q(M_AXI_AWADDR[22]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[23]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[23] ),
- .Q(M_AXI_AWADDR[23]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[24]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[24] ),
- .Q(M_AXI_AWADDR[24]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[25]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[25] ),
- .Q(M_AXI_AWADDR[25]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[26]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[26] ),
- .Q(M_AXI_AWADDR[26]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[27]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[27] ),
- .Q(M_AXI_AWADDR[27]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[28]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[28] ),
- .Q(M_AXI_AWADDR[28]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[29]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[29] ),
- .Q(M_AXI_AWADDR[29]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[2]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[2] ),
- .Q(M_AXI_AWADDR[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[30]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[30] ),
- .Q(M_AXI_AWADDR[30]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[31]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[31] ),
- .Q(M_AXI_AWADDR[31]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[3]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[3] ),
- .Q(M_AXI_AWADDR[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[4]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[4] ),
- .Q(M_AXI_AWADDR[4]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[5]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[5] ),
- .Q(M_AXI_AWADDR[5]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[6]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[6] ),
- .Q(M_AXI_AWADDR[6]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[7]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[7] ),
- .Q(M_AXI_AWADDR[7]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[8]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[8] ),
- .Q(M_AXI_AWADDR[8]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[9]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\write_addr_reg_n_0_[9] ),
- .Q(M_AXI_AWADDR[9]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \M_AXI_AWLEN[0]_i_1
- (.I0(\data_cnt_reg_n_0_[0] ),
- .I1(FIFO_NUM_AVAIL[6]),
- .I2(FIFO_NUM_AVAIL[7]),
- .I3(FIFO_NUM_AVAIL[4]),
- .I4(FIFO_NUM_AVAIL[5]),
- .O(\M_AXI_AWLEN[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \M_AXI_AWLEN[1]_i_1
- (.I0(\data_cnt_reg_n_0_[1] ),
- .I1(FIFO_NUM_AVAIL[6]),
- .I2(FIFO_NUM_AVAIL[7]),
- .I3(FIFO_NUM_AVAIL[4]),
- .I4(FIFO_NUM_AVAIL[5]),
- .O(\M_AXI_AWLEN[1]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \M_AXI_AWLEN[2]_i_1
- (.I0(\data_cnt_reg_n_0_[2] ),
- .I1(FIFO_NUM_AVAIL[6]),
- .I2(FIFO_NUM_AVAIL[7]),
- .I3(FIFO_NUM_AVAIL[4]),
- .I4(FIFO_NUM_AVAIL[5]),
- .O(\M_AXI_AWLEN[2]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \M_AXI_AWLEN[3]_i_1
- (.I0(\data_cnt_reg_n_0_[3] ),
- .I1(FIFO_NUM_AVAIL[6]),
- .I2(FIFO_NUM_AVAIL[7]),
- .I3(FIFO_NUM_AVAIL[4]),
- .I4(FIFO_NUM_AVAIL[5]),
- .O(\M_AXI_AWLEN[3]_i_1_n_0 ));
- FDRE \M_AXI_AWLEN_reg[0]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\M_AXI_AWLEN[0]_i_1_n_0 ),
- .Q(M_AXI_AWLEN[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWLEN_reg[1]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\M_AXI_AWLEN[1]_i_1_n_0 ),
- .Q(M_AXI_AWLEN[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWLEN_reg[2]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\M_AXI_AWLEN[2]_i_1_n_0 ),
- .Q(M_AXI_AWLEN[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \M_AXI_AWLEN_reg[3]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(\M_AXI_AWLEN[3]_i_1_n_0 ),
- .Q(M_AXI_AWLEN[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry
- (.CI(1'b0),
- .CO({M_AXI_AWVALID2_carry_n_0,M_AXI_AWVALID2_carry_n_1,M_AXI_AWVALID2_carry_n_2,M_AXI_AWVALID2_carry_n_3}),
- .CYINIT(1'b1),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(NLW_M_AXI_AWVALID2_carry_O_UNCONNECTED[3:0]),
- .S({M_AXI_AWVALID2_carry_i_1_n_0,M_AXI_AWVALID2_carry_i_2_n_0,M_AXI_AWVALID2_carry_i_3_n_0,M_AXI_AWVALID2_carry_i_4_n_0}));
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry__0
- (.CI(M_AXI_AWVALID2_carry_n_0),
- .CO({M_AXI_AWVALID2_carry__0_n_0,M_AXI_AWVALID2_carry__0_n_1,M_AXI_AWVALID2_carry__0_n_2,M_AXI_AWVALID2_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(NLW_M_AXI_AWVALID2_carry__0_O_UNCONNECTED[3:0]),
- .S({M_AXI_AWVALID2_carry__0_i_1_n_0,M_AXI_AWVALID2_carry__0_i_2_n_0,M_AXI_AWVALID2_carry__0_i_3_n_0,M_AXI_AWVALID2_carry__0_i_4_n_0}));
- LUT3 #(
- .INIT(8'h01))
- M_AXI_AWVALID2_carry__0_i_1
- (.I0(M_AXI_AWVALID2_carry__0_i_5_n_6),
- .I1(M_AXI_AWVALID2_carry__0_i_5_n_5),
- .I2(M_AXI_AWVALID2_carry__0_i_5_n_7),
- .O(M_AXI_AWVALID2_carry__0_i_1_n_0));
- LUT3 #(
- .INIT(8'h01))
- M_AXI_AWVALID2_carry__0_i_2
- (.I0(M_AXI_AWVALID2_carry__0_i_6_n_6),
- .I1(M_AXI_AWVALID2_carry__0_i_6_n_5),
- .I2(M_AXI_AWVALID2_carry__0_i_6_n_4),
- .O(M_AXI_AWVALID2_carry__0_i_2_n_0));
- LUT3 #(
- .INIT(8'h01))
- M_AXI_AWVALID2_carry__0_i_3
- (.I0(M_AXI_AWVALID2_carry__0_i_7_n_4),
- .I1(M_AXI_AWVALID2_carry__0_i_6_n_7),
- .I2(M_AXI_AWVALID2_carry__0_i_7_n_5),
- .O(M_AXI_AWVALID2_carry__0_i_3_n_0));
- LUT3 #(
- .INIT(8'h01))
- M_AXI_AWVALID2_carry__0_i_4
- (.I0(M_AXI_AWVALID2_carry__0_i_7_n_7),
- .I1(M_AXI_AWVALID2_carry_i_5_n_4),
- .I2(M_AXI_AWVALID2_carry__0_i_7_n_6),
- .O(M_AXI_AWVALID2_carry__0_i_4_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry__0_i_5
- (.CI(M_AXI_AWVALID2_carry__0_i_6_n_0),
- .CO({M_AXI_AWVALID2_carry__0_i_5_n_0,M_AXI_AWVALID2_carry__0_i_5_n_1,M_AXI_AWVALID2_carry__0_i_5_n_2,M_AXI_AWVALID2_carry__0_i_5_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({M_AXI_AWVALID2_carry__0_i_5_n_4,M_AXI_AWVALID2_carry__0_i_5_n_5,M_AXI_AWVALID2_carry__0_i_5_n_6,M_AXI_AWVALID2_carry__0_i_5_n_7}),
- .S({\data_cnt_reg_n_0_[24] ,\data_cnt_reg_n_0_[23] ,\data_cnt_reg_n_0_[22] ,\data_cnt_reg_n_0_[21] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry__0_i_6
- (.CI(M_AXI_AWVALID2_carry__0_i_7_n_0),
- .CO({M_AXI_AWVALID2_carry__0_i_6_n_0,M_AXI_AWVALID2_carry__0_i_6_n_1,M_AXI_AWVALID2_carry__0_i_6_n_2,M_AXI_AWVALID2_carry__0_i_6_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({M_AXI_AWVALID2_carry__0_i_6_n_4,M_AXI_AWVALID2_carry__0_i_6_n_5,M_AXI_AWVALID2_carry__0_i_6_n_6,M_AXI_AWVALID2_carry__0_i_6_n_7}),
- .S({\data_cnt_reg_n_0_[20] ,\data_cnt_reg_n_0_[19] ,\data_cnt_reg_n_0_[18] ,\data_cnt_reg_n_0_[17] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry__0_i_7
- (.CI(M_AXI_AWVALID2_carry_i_5_n_0),
- .CO({M_AXI_AWVALID2_carry__0_i_7_n_0,M_AXI_AWVALID2_carry__0_i_7_n_1,M_AXI_AWVALID2_carry__0_i_7_n_2,M_AXI_AWVALID2_carry__0_i_7_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({M_AXI_AWVALID2_carry__0_i_7_n_4,M_AXI_AWVALID2_carry__0_i_7_n_5,M_AXI_AWVALID2_carry__0_i_7_n_6,M_AXI_AWVALID2_carry__0_i_7_n_7}),
- .S({\data_cnt_reg_n_0_[16] ,\data_cnt_reg_n_0_[15] ,\data_cnt_reg_n_0_[14] ,\data_cnt_reg_n_0_[13] }));
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry__1
- (.CI(M_AXI_AWVALID2_carry__0_n_0),
- .CO({NLW_M_AXI_AWVALID2_carry__1_CO_UNCONNECTED[3],M_AXI_AWVALID2,M_AXI_AWVALID2_carry__1_n_2,M_AXI_AWVALID2_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(NLW_M_AXI_AWVALID2_carry__1_O_UNCONNECTED[3:0]),
- .S({1'b0,M_AXI_AWVALID2_carry__1_i_1_n_0,M_AXI_AWVALID2_carry__1_i_2_n_0,M_AXI_AWVALID2_carry__1_i_3_n_0}));
- LUT2 #(
- .INIT(4'h1))
- M_AXI_AWVALID2_carry__1_i_1
- (.I0(M_AXI_AWVALID2_carry__1_i_4_n_5),
- .I1(M_AXI_AWVALID2_carry__1_i_4_n_6),
- .O(M_AXI_AWVALID2_carry__1_i_1_n_0));
- LUT3 #(
- .INIT(8'h01))
- M_AXI_AWVALID2_carry__1_i_2
- (.I0(M_AXI_AWVALID2_carry__1_i_5_n_4),
- .I1(M_AXI_AWVALID2_carry__1_i_4_n_7),
- .I2(M_AXI_AWVALID2_carry__1_i_5_n_5),
- .O(M_AXI_AWVALID2_carry__1_i_2_n_0));
- LUT3 #(
- .INIT(8'h01))
- M_AXI_AWVALID2_carry__1_i_3
- (.I0(M_AXI_AWVALID2_carry__0_i_5_n_4),
- .I1(M_AXI_AWVALID2_carry__1_i_5_n_7),
- .I2(M_AXI_AWVALID2_carry__1_i_5_n_6),
- .O(M_AXI_AWVALID2_carry__1_i_3_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry__1_i_4
- (.CI(M_AXI_AWVALID2_carry__1_i_5_n_0),
- .CO({NLW_M_AXI_AWVALID2_carry__1_i_4_CO_UNCONNECTED[3:2],M_AXI_AWVALID2_carry__1_i_4_n_2,M_AXI_AWVALID2_carry__1_i_4_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({NLW_M_AXI_AWVALID2_carry__1_i_4_O_UNCONNECTED[3],M_AXI_AWVALID2_carry__1_i_4_n_5,M_AXI_AWVALID2_carry__1_i_4_n_6,M_AXI_AWVALID2_carry__1_i_4_n_7}),
- .S({1'b0,\data_cnt_reg_n_0_[31] ,\data_cnt_reg_n_0_[30] ,\data_cnt_reg_n_0_[29] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry__1_i_5
- (.CI(M_AXI_AWVALID2_carry__0_i_5_n_0),
- .CO({M_AXI_AWVALID2_carry__1_i_5_n_0,M_AXI_AWVALID2_carry__1_i_5_n_1,M_AXI_AWVALID2_carry__1_i_5_n_2,M_AXI_AWVALID2_carry__1_i_5_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({M_AXI_AWVALID2_carry__1_i_5_n_4,M_AXI_AWVALID2_carry__1_i_5_n_5,M_AXI_AWVALID2_carry__1_i_5_n_6,M_AXI_AWVALID2_carry__1_i_5_n_7}),
- .S({\data_cnt_reg_n_0_[28] ,\data_cnt_reg_n_0_[27] ,\data_cnt_reg_n_0_[26] ,\data_cnt_reg_n_0_[25] }));
- LUT3 #(
- .INIT(8'h01))
- M_AXI_AWVALID2_carry_i_1
- (.I0(M_AXI_AWVALID2_carry_i_5_n_6),
- .I1(M_AXI_AWVALID2_carry_i_5_n_5),
- .I2(M_AXI_AWVALID2_carry_i_5_n_7),
- .O(M_AXI_AWVALID2_carry_i_1_n_0));
- LUT5 #(
- .INIT(32'h09000009))
- M_AXI_AWVALID2_carry_i_2
- (.I0(FIFO_NUM_AVAIL[7]),
- .I1(M_AXI_AWVALID2_carry_i_6_n_5),
- .I2(M_AXI_AWVALID2_carry_i_6_n_4),
- .I3(M_AXI_AWVALID2_carry_i_6_n_6),
- .I4(FIFO_NUM_AVAIL[6]),
- .O(M_AXI_AWVALID2_carry_i_2_n_0));
- LUT6 #(
- .INIT(64'h9009000000009009))
- M_AXI_AWVALID2_carry_i_3
- (.I0(FIFO_NUM_AVAIL[3]),
- .I1(M_AXI_AWVALID2_carry_i_7_n_5),
- .I2(FIFO_NUM_AVAIL[4]),
- .I3(M_AXI_AWVALID2_carry_i_7_n_4),
- .I4(M_AXI_AWVALID2_carry_i_6_n_7),
- .I5(FIFO_NUM_AVAIL[5]),
- .O(M_AXI_AWVALID2_carry_i_3_n_0));
- LUT6 #(
- .INIT(64'h6006000000006006))
- M_AXI_AWVALID2_carry_i_4
- (.I0(\data_cnt_reg_n_0_[0] ),
- .I1(FIFO_NUM_AVAIL[0]),
- .I2(FIFO_NUM_AVAIL[2]),
- .I3(M_AXI_AWVALID2_carry_i_7_n_6),
- .I4(FIFO_NUM_AVAIL[1]),
- .I5(M_AXI_AWVALID2_carry_i_7_n_7),
- .O(M_AXI_AWVALID2_carry_i_4_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry_i_5
- (.CI(M_AXI_AWVALID2_carry_i_6_n_0),
- .CO({M_AXI_AWVALID2_carry_i_5_n_0,M_AXI_AWVALID2_carry_i_5_n_1,M_AXI_AWVALID2_carry_i_5_n_2,M_AXI_AWVALID2_carry_i_5_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({M_AXI_AWVALID2_carry_i_5_n_4,M_AXI_AWVALID2_carry_i_5_n_5,M_AXI_AWVALID2_carry_i_5_n_6,M_AXI_AWVALID2_carry_i_5_n_7}),
- .S({\data_cnt_reg_n_0_[12] ,\data_cnt_reg_n_0_[11] ,\data_cnt_reg_n_0_[10] ,\data_cnt_reg_n_0_[9] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry_i_6
- (.CI(M_AXI_AWVALID2_carry_i_7_n_0),
- .CO({M_AXI_AWVALID2_carry_i_6_n_0,M_AXI_AWVALID2_carry_i_6_n_1,M_AXI_AWVALID2_carry_i_6_n_2,M_AXI_AWVALID2_carry_i_6_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({M_AXI_AWVALID2_carry_i_6_n_4,M_AXI_AWVALID2_carry_i_6_n_5,M_AXI_AWVALID2_carry_i_6_n_6,M_AXI_AWVALID2_carry_i_6_n_7}),
- .S({\data_cnt_reg_n_0_[8] ,\data_cnt_reg_n_0_[7] ,\data_cnt_reg_n_0_[6] ,\data_cnt_reg_n_0_[5] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 M_AXI_AWVALID2_carry_i_7
- (.CI(1'b0),
- .CO({M_AXI_AWVALID2_carry_i_7_n_0,M_AXI_AWVALID2_carry_i_7_n_1,M_AXI_AWVALID2_carry_i_7_n_2,M_AXI_AWVALID2_carry_i_7_n_3}),
- .CYINIT(\data_cnt_reg_n_0_[0] ),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({M_AXI_AWVALID2_carry_i_7_n_4,M_AXI_AWVALID2_carry_i_7_n_5,M_AXI_AWVALID2_carry_i_7_n_6,M_AXI_AWVALID2_carry_i_7_n_7}),
- .S({\data_cnt_reg_n_0_[4] ,\data_cnt_reg_n_0_[3] ,\data_cnt_reg_n_0_[2] ,\data_cnt_reg_n_0_[1] }));
- LUT6 #(
- .INIT(64'h7575753345454500))
- M_AXI_AWVALID_i_1
- (.I0(write_state_reg[1]),
- .I1(M_AXI_AWVALID_i_2_n_0),
- .I2(M_AXI_AWVALID_i_3_n_0),
- .I3(M_AXI_AWVALID_i_4_n_0),
- .I4(M_AXI_AWVALID_i_5_n_0),
- .I5(M_AXI_AWVALID),
- .O(M_AXI_AWVALID_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h0040))
- M_AXI_AWVALID_i_2
- (.I0(write_state_reg[0]),
- .I1(M_AXI_AWREADY),
- .I2(write_state_reg[1]),
- .I3(write_state_reg[2]),
- .O(M_AXI_AWVALID_i_2_n_0));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT3 #(
- .INIT(8'hEF))
- M_AXI_AWVALID_i_3
- (.I0(write_state_reg[2]),
- .I1(write_state_reg[1]),
- .I2(write_state_reg[0]),
- .O(M_AXI_AWVALID_i_3_n_0));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'hFFFE))
- M_AXI_AWVALID_i_4
- (.I0(FIFO_NUM_AVAIL[5]),
- .I1(FIFO_NUM_AVAIL[4]),
- .I2(FIFO_NUM_AVAIL[7]),
- .I3(FIFO_NUM_AVAIL[6]),
- .O(M_AXI_AWVALID_i_4_n_0));
- LUT6 #(
- .INIT(64'h0000000000000004))
- M_AXI_AWVALID_i_5
- (.I0(\M_AXI_AWADDR[31]_i_2_n_0 ),
- .I1(\M_AXI_AWADDR[31]_i_3_n_0 ),
- .I2(M_AXI_AWVALID_i_6_n_0),
- .I3(M_AXI_AWVALID_i_7_n_0),
- .I4(M_AXI_AWVALID_i_8_n_0),
- .I5(M_AXI_AWVALID_i_9_n_0),
- .O(M_AXI_AWVALID_i_5_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- M_AXI_AWVALID_i_6
- (.I0(M_AXI_AWVALID2_carry__0_i_7_n_4),
- .I1(M_AXI_AWVALID2_carry__0_i_6_n_7),
- .I2(M_AXI_AWVALID2_carry__0_i_7_n_5),
- .I3(M_AXI_AWVALID2_carry__1_i_5_n_4),
- .I4(M_AXI_AWVALID2_carry__1_i_4_n_7),
- .I5(M_AXI_AWVALID2_carry__1_i_5_n_5),
- .O(M_AXI_AWVALID_i_6_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- M_AXI_AWVALID_i_7
- (.I0(M_AXI_AWVALID2_carry__0_i_5_n_6),
- .I1(M_AXI_AWVALID2_carry__0_i_5_n_5),
- .I2(M_AXI_AWVALID2_carry__0_i_5_n_7),
- .I3(M_AXI_AWVALID2_carry__0_i_5_n_4),
- .I4(M_AXI_AWVALID2_carry__1_i_5_n_7),
- .I5(M_AXI_AWVALID2_carry__1_i_5_n_6),
- .O(M_AXI_AWVALID_i_7_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- M_AXI_AWVALID_i_8
- (.I0(M_AXI_AWVALID2_carry_i_6_n_4),
- .I1(M_AXI_AWVALID2_carry_i_6_n_7),
- .I2(M_AXI_AWVALID2),
- .I3(M_AXI_AWVALID2_carry_i_7_n_4),
- .O(M_AXI_AWVALID_i_8_n_0));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'hFFFE))
- M_AXI_AWVALID_i_9
- (.I0(M_AXI_AWVALID2_carry__1_i_4_n_5),
- .I1(M_AXI_AWVALID2_carry__1_i_4_n_6),
- .I2(M_AXI_AWVALID2_carry_i_6_n_5),
- .I3(M_AXI_AWVALID2_carry_i_6_n_6),
- .O(M_AXI_AWVALID_i_9_n_0));
- FDRE #(
- .INIT(1'b0))
- M_AXI_AWVALID_reg
- (.C(CLK),
- .CE(1'b1),
- .D(M_AXI_AWVALID_i_1_n_0),
- .Q(M_AXI_AWVALID),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFF2EFF00002E00))
- M_AXI_WLAST_i_1
- (.I0(M_AXI_AWREADY),
- .I1(write_state_reg[0]),
- .I2(M_AXI_WLAST_i_2_n_0),
- .I3(M_AXI_WLAST_i_3_n_0),
- .I4(M_AXI_WLAST_i_4_n_0),
- .I5(M_AXI_WLAST),
- .O(M_AXI_WLAST_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT5 #(
- .INIT(32'h00000001))
- M_AXI_WLAST_i_2
- (.I0(\burst_data_cnt_reg_n_0_[1] ),
- .I1(\burst_data_cnt_reg_n_0_[0] ),
- .I2(\burst_data_cnt_reg_n_0_[2] ),
- .I3(\burst_data_cnt_reg_n_0_[3] ),
- .I4(\burst_data_cnt_reg_n_0_[4] ),
- .O(M_AXI_WLAST_i_2_n_0));
- LUT6 #(
- .INIT(64'h0000000000000E0C))
- M_AXI_WLAST_i_3
- (.I0(M_AXI_WLAST_i_5_n_0),
- .I1(M_AXI_WLAST_i_6_n_0),
- .I2(\burst_data_cnt_reg_n_0_[1] ),
- .I3(\burst_data_cnt_reg_n_0_[0] ),
- .I4(\burst_data_cnt_reg_n_0_[2] ),
- .I5(M_AXI_WLAST_i_7_n_0),
- .O(M_AXI_WLAST_i_3_n_0));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT2 #(
- .INIT(4'hB))
- M_AXI_WLAST_i_4
- (.I0(write_state_reg[2]),
- .I1(write_state_reg[1]),
- .O(M_AXI_WLAST_i_4_n_0));
- (* SOFT_HLUTNM = "soft_lutpair48" *)
- LUT2 #(
- .INIT(4'h2))
- M_AXI_WLAST_i_5
- (.I0(M_AXI_AWREADY),
- .I1(write_state_reg[0]),
- .O(M_AXI_WLAST_i_5_n_0));
- (* SOFT_HLUTNM = "soft_lutpair47" *)
- LUT2 #(
- .INIT(4'h8))
- M_AXI_WLAST_i_6
- (.I0(M_AXI_WREADY),
- .I1(write_state_reg[0]),
- .O(M_AXI_WLAST_i_6_n_0));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT2 #(
- .INIT(4'hE))
- M_AXI_WLAST_i_7
- (.I0(\burst_data_cnt_reg_n_0_[4] ),
- .I1(\burst_data_cnt_reg_n_0_[3] ),
- .O(M_AXI_WLAST_i_7_n_0));
- FDRE #(
- .INIT(1'b0))
- M_AXI_WLAST_reg
- (.C(CLK),
- .CE(1'b1),
- .D(M_AXI_WLAST_i_1_n_0),
- .Q(M_AXI_WLAST),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h0080))
- M_AXI_WVALID_INST_0
- (.I0(S_AXIS_TVALID),
- .I1(write_state_reg[0]),
- .I2(write_state_reg[1]),
- .I3(write_state_reg[2]),
- .O(M_AXI_WVALID));
- LUT4 #(
- .INIT(16'hD5C0))
- S_AXIL_BVALID_i_1
- (.I0(S_AXIL_BREADY),
- .I1(S_AXIL_AWVALID),
- .I2(S_AXIL_WVALID),
- .I3(S_AXIL_BVALID),
- .O(S_AXIL_BVALID_i_1_n_0));
- FDRE S_AXIL_BVALID_reg
- (.C(CLK),
- .CE(1'b1),
- .D(S_AXIL_BVALID_i_1_n_0),
- .Q(S_AXIL_BVALID),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAAAAAAAAAAAEF))
- \S_AXIL_RDATA[0]_i_1
- (.I0(\S_AXIL_RDATA[0]_i_2_n_0 ),
- .I1(\S_AXIL_RDATA[0]_i_3_n_0 ),
- .I2(S_AXIL_ARADDR[4]),
- .I3(S_AXIL_ARADDR[0]),
- .I4(S_AXIL_ARADDR[5]),
- .I5(\S_AXIL_RDATA[0]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00000000CCCCAACA))
- \S_AXIL_RDATA[0]_i_2
- (.I0(finalXOR[0]),
- .I1(inOutReflected[0]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(S_AXIL_ARADDR[3]),
- .I4(S_AXIL_ARADDR[4]),
- .I5(\S_AXIL_RDATA[1]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[0]_i_3
- (.I0(initial_value[0]),
- .I1(polynomial[0]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[0]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[0]),
- .O(\S_AXIL_RDATA[0]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0000ABEF))
- \S_AXIL_RDATA[0]_i_4
- (.I0(S_AXIL_ARADDR[3]),
- .I1(S_AXIL_ARADDR[2]),
- .I2(p_5_in[0]),
- .I3(INTERRUPT),
- .I4(\S_AXIL_RDATA[0]_i_5_n_0 ),
- .O(\S_AXIL_RDATA[0]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hEAEEEAAA))
- \S_AXIL_RDATA[0]_i_5
- (.I0(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I1(S_AXIL_ARADDR[3]),
- .I2(write_address_reg[0]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(read_address_reg[0]),
- .O(\S_AXIL_RDATA[0]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[10]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[10]_i_2_n_0 ),
- .I3(finalXOR[10]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[10]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[10]_i_2
- (.I0(\S_AXIL_RDATA[10]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[10]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[10]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[10]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[10]_i_3
- (.I0(initial_value[10]),
- .I1(polynomial[10]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[10]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[10]),
- .O(\S_AXIL_RDATA[10]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[11]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[11]_i_2_n_0 ),
- .I3(finalXOR[11]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[11]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[11]_i_2
- (.I0(\S_AXIL_RDATA[11]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[11]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[11]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[11]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[11]_i_3
- (.I0(initial_value[11]),
- .I1(polynomial[11]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[11]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[11]),
- .O(\S_AXIL_RDATA[11]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[12]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[12]_i_2_n_0 ),
- .I3(finalXOR[12]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[12]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[12]_i_2
- (.I0(\S_AXIL_RDATA[12]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[12]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[12]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[12]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[12]_i_3
- (.I0(initial_value[12]),
- .I1(polynomial[12]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[12]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[12]),
- .O(\S_AXIL_RDATA[12]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[13]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[13]_i_2_n_0 ),
- .I3(finalXOR[13]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[13]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[13]_i_2
- (.I0(\S_AXIL_RDATA[13]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[13]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[13]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[13]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[13]_i_3
- (.I0(initial_value[13]),
- .I1(polynomial[13]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[13]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[13]),
- .O(\S_AXIL_RDATA[13]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[14]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[14]_i_2_n_0 ),
- .I3(finalXOR[14]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[14]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[14]_i_2
- (.I0(\S_AXIL_RDATA[14]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[14]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[14]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[14]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[14]_i_3
- (.I0(initial_value[14]),
- .I1(polynomial[14]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[14]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[14]),
- .O(\S_AXIL_RDATA[14]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[15]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[15]_i_2_n_0 ),
- .I3(finalXOR[15]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[15]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[15]_i_2
- (.I0(\S_AXIL_RDATA[15]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[15]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[15]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[15]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[15]_i_3
- (.I0(initial_value[15]),
- .I1(polynomial[15]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[15]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[15]),
- .O(\S_AXIL_RDATA[15]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[16]_i_1
- (.I0(\S_AXIL_RDATA[16]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[16]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[16]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[16]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[16]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[16]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[16]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[16]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[16]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[16]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[16]),
- .O(\S_AXIL_RDATA[16]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[17]_i_1
- (.I0(\S_AXIL_RDATA[17]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[17]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[17]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[17]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[17]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[17]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[17]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[17]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[17]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[17]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[17]),
- .O(\S_AXIL_RDATA[17]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[18]_i_1
- (.I0(\S_AXIL_RDATA[18]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[18]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[18]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[18]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[18]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[18]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[18]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[18]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[18]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[18]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[18]),
- .O(\S_AXIL_RDATA[18]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[19]_i_1
- (.I0(\S_AXIL_RDATA[19]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[19]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[19]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[19]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[19]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[19]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[19]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[19]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[19]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[19]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[19]),
- .O(\S_AXIL_RDATA[19]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h8F8F8F88888F8888))
- \S_AXIL_RDATA[1]_i_1
- (.I0(\S_AXIL_RDATA[1]_i_2_n_0 ),
- .I1(\S_AXIL_RDATA_reg[1]_i_3_n_0 ),
- .I2(\S_AXIL_RDATA[1]_i_4_n_0 ),
- .I3(\S_AXIL_RDATA[1]_i_5_n_0 ),
- .I4(inOutReflected[1]),
- .I5(finalXOR[1]),
- .O(\S_AXIL_RDATA[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT2 #(
- .INIT(4'h1))
- \S_AXIL_RDATA[1]_i_2
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .O(\S_AXIL_RDATA[1]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFEF))
- \S_AXIL_RDATA[1]_i_4
- (.I0(S_AXIL_ARADDR[0]),
- .I1(S_AXIL_ARADDR[4]),
- .I2(S_AXIL_ARADDR[5]),
- .I3(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[1]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT3 #(
- .INIT(8'h45))
- \S_AXIL_RDATA[1]_i_5
- (.I0(S_AXIL_ARADDR[4]),
- .I1(S_AXIL_ARADDR[3]),
- .I2(S_AXIL_ARADDR[2]),
- .O(\S_AXIL_RDATA[1]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \S_AXIL_RDATA[1]_i_6
- (.I0(write_address_reg[1]),
- .I1(read_address_reg[1]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(p_5_in[1]),
- .I4(S_AXIL_ARADDR[2]),
- .O(\S_AXIL_RDATA[1]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[1]_i_7
- (.I0(initial_value[1]),
- .I1(polynomial[1]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[1]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[1]),
- .O(\S_AXIL_RDATA[1]_i_7_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[20]_i_1
- (.I0(\S_AXIL_RDATA[20]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[20]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[20]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[20]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[20]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[20]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[20]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[20]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[20]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[20]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[20]),
- .O(\S_AXIL_RDATA[20]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[21]_i_1
- (.I0(\S_AXIL_RDATA[21]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[21]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[21]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[21]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[21]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[21]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[21]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[21]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[21]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[21]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[21]),
- .O(\S_AXIL_RDATA[21]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[22]_i_1
- (.I0(\S_AXIL_RDATA[22]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[22]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[22]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[22]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[22]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[22]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[22]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[22]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[22]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[22]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[22]),
- .O(\S_AXIL_RDATA[22]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[23]_i_1
- (.I0(\S_AXIL_RDATA[23]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[23]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[23]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[23]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[23]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[23]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[23]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[23]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[23]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[23]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[23]),
- .O(\S_AXIL_RDATA[23]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[24]_i_1
- (.I0(\S_AXIL_RDATA[24]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[24]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[24]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[24]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[24]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[24]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[24]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[24]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[24]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[24]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[24]),
- .O(\S_AXIL_RDATA[24]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[25]_i_1
- (.I0(\S_AXIL_RDATA[25]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[25]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[25]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[25]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[25]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[25]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[25]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[25]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[25]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[25]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[25]),
- .O(\S_AXIL_RDATA[25]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[26]_i_1
- (.I0(\S_AXIL_RDATA[26]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[26]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[26]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[26]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[26]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[26]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[26]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[26]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[26]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[26]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[26]),
- .O(\S_AXIL_RDATA[26]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[27]_i_1
- (.I0(\S_AXIL_RDATA[27]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[27]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[27]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[27]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[27]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[27]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[27]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[27]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[27]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[27]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[27]),
- .O(\S_AXIL_RDATA[27]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[28]_i_1
- (.I0(\S_AXIL_RDATA[28]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[28]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[28]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[28]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[28]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[28]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[28]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[28]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[28]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[28]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[28]),
- .O(\S_AXIL_RDATA[28]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[29]_i_1
- (.I0(\S_AXIL_RDATA[29]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[29]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[29]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[29]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[29]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[29]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[29]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[29]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[29]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[29]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[29]),
- .O(\S_AXIL_RDATA[29]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[2]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[2]_i_2_n_0 ),
- .I3(finalXOR[2]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[2]_i_2
- (.I0(\S_AXIL_RDATA[2]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[2]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[2]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[2]_i_3
- (.I0(initial_value[2]),
- .I1(polynomial[2]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[2]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[2]),
- .O(\S_AXIL_RDATA[2]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0101FF01))
- \S_AXIL_RDATA[30]_i_1
- (.I0(\S_AXIL_RDATA[30]_i_2_n_0 ),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[0]),
- .I3(finalXOR[30]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[30]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[30]_i_2
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[30]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[30]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[30]_i_3_n_0 ),
- .O(\S_AXIL_RDATA[30]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[30]_i_3
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[30]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[30]),
- .O(\S_AXIL_RDATA[30]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h88888880))
- \S_AXIL_RDATA[31]_i_1
- (.I0(S_AXIL_ARVALID),
- .I1(RESETN),
- .I2(S_AXIL_ARADDR[6]),
- .I3(S_AXIL_ARADDR[7]),
- .I4(S_AXIL_ARADDR[1]),
- .O(\S_AXIL_RDATA[31]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \S_AXIL_RDATA[31]_i_2
- (.I0(RESETN),
- .I1(S_AXIL_ARVALID),
- .O(\S_AXIL_RDATA[31]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'h4444444F))
- \S_AXIL_RDATA[31]_i_3
- (.I0(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .I1(finalXOR[31]),
- .I2(\S_AXIL_RDATA[31]_i_5_n_0 ),
- .I3(S_AXIL_ARADDR[5]),
- .I4(S_AXIL_ARADDR[0]),
- .O(\S_AXIL_RDATA[31]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFEF))
- \S_AXIL_RDATA[31]_i_4
- (.I0(S_AXIL_ARADDR[2]),
- .I1(S_AXIL_ARADDR[3]),
- .I2(S_AXIL_ARADDR[5]),
- .I3(S_AXIL_ARADDR[4]),
- .I4(S_AXIL_ARADDR[0]),
- .O(\S_AXIL_RDATA[31]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h57F7FFFF57F70000))
- \S_AXIL_RDATA[31]_i_5
- (.I0(S_AXIL_ARADDR[3]),
- .I1(polynomial[31]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(initial_value[31]),
- .I4(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I5(\S_AXIL_RDATA[31]_i_7_n_0 ),
- .O(\S_AXIL_RDATA[31]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'hBA))
- \S_AXIL_RDATA[31]_i_6
- (.I0(S_AXIL_ARADDR[0]),
- .I1(S_AXIL_ARADDR[5]),
- .I2(S_AXIL_ARADDR[4]),
- .O(\S_AXIL_RDATA[31]_i_6_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT4 #(
- .INIT(16'h57F7))
- \S_AXIL_RDATA[31]_i_7
- (.I0(S_AXIL_ARADDR[3]),
- .I1(read_address_reg[31]),
- .I2(S_AXIL_ARADDR[2]),
- .I3(write_address_reg[31]),
- .O(\S_AXIL_RDATA[31]_i_7_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[3]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[3]_i_2_n_0 ),
- .I3(finalXOR[3]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[3]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[3]_i_2
- (.I0(\S_AXIL_RDATA[3]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[3]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[3]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[3]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[3]_i_3
- (.I0(initial_value[3]),
- .I1(polynomial[3]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[3]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[3]),
- .O(\S_AXIL_RDATA[3]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[4]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[4]_i_2_n_0 ),
- .I3(finalXOR[4]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[4]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[4]_i_2
- (.I0(\S_AXIL_RDATA[4]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[4]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[4]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[4]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[4]_i_3
- (.I0(initial_value[4]),
- .I1(polynomial[4]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[4]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[4]),
- .O(\S_AXIL_RDATA[4]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[5]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[5]_i_2_n_0 ),
- .I3(finalXOR[5]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[5]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[5]_i_2
- (.I0(\S_AXIL_RDATA[5]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[5]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[5]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[5]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[5]_i_3
- (.I0(initial_value[5]),
- .I1(polynomial[5]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[5]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[5]),
- .O(\S_AXIL_RDATA[5]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[6]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[6]_i_2_n_0 ),
- .I3(finalXOR[6]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[6]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[6]_i_2
- (.I0(\S_AXIL_RDATA[6]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[6]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[6]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[6]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[6]_i_3
- (.I0(initial_value[6]),
- .I1(polynomial[6]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[6]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[6]),
- .O(\S_AXIL_RDATA[6]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[7]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[7]_i_2_n_0 ),
- .I3(finalXOR[7]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[7]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[7]_i_2
- (.I0(\S_AXIL_RDATA[7]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[7]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[7]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[7]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[7]_i_3
- (.I0(initial_value[7]),
- .I1(polynomial[7]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[7]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[7]),
- .O(\S_AXIL_RDATA[7]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[8]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[8]_i_2_n_0 ),
- .I3(finalXOR[8]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[8]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[8]_i_2
- (.I0(\S_AXIL_RDATA[8]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[8]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[8]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[8]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[8]_i_3
- (.I0(initial_value[8]),
- .I1(polynomial[8]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[8]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[8]),
- .O(\S_AXIL_RDATA[8]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h1010FF10))
- \S_AXIL_RDATA[9]_i_1
- (.I0(S_AXIL_ARADDR[5]),
- .I1(S_AXIL_ARADDR[0]),
- .I2(\S_AXIL_RDATA[9]_i_2_n_0 ),
- .I3(finalXOR[9]),
- .I4(\S_AXIL_RDATA[31]_i_4_n_0 ),
- .O(\S_AXIL_RDATA[9]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB888B888888888))
- \S_AXIL_RDATA[9]_i_2
- (.I0(\S_AXIL_RDATA[9]_i_3_n_0 ),
- .I1(\S_AXIL_RDATA[31]_i_6_n_0 ),
- .I2(read_address_reg[9]),
- .I3(S_AXIL_ARADDR[2]),
- .I4(write_address_reg[9]),
- .I5(S_AXIL_ARADDR[3]),
- .O(\S_AXIL_RDATA[9]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \S_AXIL_RDATA[9]_i_3
- (.I0(initial_value[9]),
- .I1(polynomial[9]),
- .I2(S_AXIL_ARADDR[3]),
- .I3(packet_number_reg[9]),
- .I4(S_AXIL_ARADDR[2]),
- .I5(packet_size_reg[9]),
- .O(\S_AXIL_RDATA[9]_i_3_n_0 ));
- FDRE \S_AXIL_RDATA_reg[0]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[0]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[0]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[10]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[10]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[10]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[11]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[11]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[11]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[12]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[12]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[12]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[13]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[13]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[13]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[14]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[14]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[14]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[15]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[15]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[15]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[16]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[16]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[16]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[17]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[17]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[17]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[18]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[18]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[18]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[19]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[19]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[19]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[1]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[1]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[1]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- MUXF7 \S_AXIL_RDATA_reg[1]_i_3
- (.I0(\S_AXIL_RDATA[1]_i_6_n_0 ),
- .I1(\S_AXIL_RDATA[1]_i_7_n_0 ),
- .O(\S_AXIL_RDATA_reg[1]_i_3_n_0 ),
- .S(\S_AXIL_RDATA[31]_i_6_n_0 ));
- FDRE \S_AXIL_RDATA_reg[20]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[20]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[20]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[21]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[21]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[21]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[22]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[22]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[22]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[23]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[23]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[23]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[24]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[24]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[24]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[25]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[25]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[25]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[26]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[26]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[26]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[27]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[27]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[27]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[28]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[28]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[28]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[29]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[29]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[29]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[2]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[2]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[2]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[30]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[30]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[30]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[31]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[31]_i_3_n_0 ),
- .Q(S_AXIL_RDATA[31]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[3]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[3]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[3]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[4]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[4]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[4]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[5]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[5]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[5]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[6]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[6]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[6]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[7]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[7]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[7]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[8]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[8]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[8]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- FDRE \S_AXIL_RDATA_reg[9]
- (.C(CLK),
- .CE(\S_AXIL_RDATA[31]_i_2_n_0 ),
- .D(\S_AXIL_RDATA[9]_i_1_n_0 ),
- .Q(S_AXIL_RDATA[9]),
- .R(\S_AXIL_RDATA[31]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'hBA))
- S_AXIL_RVALID_i_1
- (.I0(S_AXIL_ARVALID),
- .I1(S_AXIL_RREADY),
- .I2(S_AXIL_RVALID),
- .O(S_AXIL_RVALID_i_1_n_0));
- FDRE S_AXIL_RVALID_reg
- (.C(CLK),
- .CE(1'b1),
- .D(S_AXIL_RVALID_i_1_n_0),
- .Q(S_AXIL_RVALID),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT2 #(
- .INIT(4'h8))
- S_AXIL_WREADY_INST_0
- (.I0(S_AXIL_WVALID),
- .I1(S_AXIL_AWVALID),
- .O(S_AXIL_WVALID_0));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h0080))
- S_AXIS_TREADY_INST_0
- (.I0(write_state_reg[0]),
- .I1(M_AXI_WREADY),
- .I2(write_state_reg[1]),
- .I3(write_state_reg[2]),
- .O(S_AXIS_TREADY));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __0_carry
- (.CI(1'b0),
- .CO({__0_carry_n_0,__0_carry_n_1,__0_carry_n_2,__0_carry_n_3}),
- .CYINIT(1'b0),
- .DI({__0_carry_i_1_n_0,__0_carry_i_2_n_0,__0_carry_i_3_n_0,1'b0}),
- .O(data_cnt1_in[3:0]),
- .S({__0_carry_i_4_n_0,__0_carry_i_5_n_0,__0_carry_i_6_n_0,__0_carry_i_7_n_0}));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __0_carry__0
- (.CI(__0_carry_n_0),
- .CO({__0_carry__0_n_0,__0_carry__0_n_1,__0_carry__0_n_2,__0_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({__0_carry__0_i_1_n_0,__0_carry__0_i_2_n_0,__0_carry__0_i_3_n_0,__0_carry__0_i_4_n_0}),
- .O(data_cnt1_in[7:4]),
- .S({__0_carry__0_i_5_n_0,__0_carry__0_i_6_n_0,__0_carry__0_i_7_n_0,__0_carry__0_i_8_n_0}));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__0_i_1
- (.I0(packet_number_reg[6]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[6] ),
- .I3(L__0[6]),
- .I4(write_state_reg[0]),
- .O(__0_carry__0_i_1_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__0_i_2
- (.I0(packet_number_reg[5]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[5] ),
- .I3(L__0[5]),
- .I4(write_state_reg[0]),
- .O(__0_carry__0_i_2_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__0_i_3
- (.I0(packet_number_reg[4]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[4] ),
- .I3(L__0[4]),
- .I4(write_state_reg[0]),
- .O(__0_carry__0_i_3_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__0_i_4
- (.I0(packet_number_reg[3]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[3] ),
- .I3(L__0[3]),
- .I4(write_state_reg[0]),
- .O(__0_carry__0_i_4_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__0_i_5
- (.I0(__0_carry__0_i_1_n_0),
- .I1(packet_number_reg[7]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[7] ),
- .I4(L__0[7]),
- .I5(write_state_reg[0]),
- .O(__0_carry__0_i_5_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__0_i_6
- (.I0(__0_carry__0_i_2_n_0),
- .I1(packet_number_reg[6]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[6] ),
- .I4(L__0[6]),
- .I5(write_state_reg[0]),
- .O(__0_carry__0_i_6_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__0_i_7
- (.I0(__0_carry__0_i_3_n_0),
- .I1(packet_number_reg[5]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[5] ),
- .I4(L__0[5]),
- .I5(write_state_reg[0]),
- .O(__0_carry__0_i_7_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__0_i_8
- (.I0(__0_carry__0_i_4_n_0),
- .I1(packet_number_reg[4]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[4] ),
- .I4(L__0[4]),
- .I5(write_state_reg[0]),
- .O(__0_carry__0_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __0_carry__1
- (.CI(__0_carry__0_n_0),
- .CO({__0_carry__1_n_0,__0_carry__1_n_1,__0_carry__1_n_2,__0_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({__0_carry__1_i_1_n_0,__0_carry__1_i_2_n_0,__0_carry__1_i_3_n_0,__0_carry__1_i_4_n_0}),
- .O(data_cnt1_in[11:8]),
- .S({__0_carry__1_i_5_n_0,__0_carry__1_i_6_n_0,__0_carry__1_i_7_n_0,__0_carry__1_i_8_n_0}));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__1_i_1
- (.I0(packet_number_reg[10]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[10] ),
- .I3(L__0[10]),
- .I4(write_state_reg[0]),
- .O(__0_carry__1_i_1_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__1_i_2
- (.I0(packet_number_reg[9]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[9] ),
- .I3(L__0[9]),
- .I4(write_state_reg[0]),
- .O(__0_carry__1_i_2_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__1_i_3
- (.I0(packet_number_reg[8]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[8] ),
- .I3(L__0[8]),
- .I4(write_state_reg[0]),
- .O(__0_carry__1_i_3_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__1_i_4
- (.I0(packet_number_reg[7]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[7] ),
- .I3(L__0[7]),
- .I4(write_state_reg[0]),
- .O(__0_carry__1_i_4_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__1_i_5
- (.I0(__0_carry__1_i_1_n_0),
- .I1(packet_number_reg[11]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[11] ),
- .I4(L__0[11]),
- .I5(write_state_reg[0]),
- .O(__0_carry__1_i_5_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__1_i_6
- (.I0(__0_carry__1_i_2_n_0),
- .I1(packet_number_reg[10]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[10] ),
- .I4(L__0[10]),
- .I5(write_state_reg[0]),
- .O(__0_carry__1_i_6_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__1_i_7
- (.I0(__0_carry__1_i_3_n_0),
- .I1(packet_number_reg[9]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[9] ),
- .I4(L__0[9]),
- .I5(write_state_reg[0]),
- .O(__0_carry__1_i_7_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__1_i_8
- (.I0(__0_carry__1_i_4_n_0),
- .I1(packet_number_reg[8]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[8] ),
- .I4(L__0[8]),
- .I5(write_state_reg[0]),
- .O(__0_carry__1_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __0_carry__2
- (.CI(__0_carry__1_n_0),
- .CO({__0_carry__2_n_0,__0_carry__2_n_1,__0_carry__2_n_2,__0_carry__2_n_3}),
- .CYINIT(1'b0),
- .DI({__0_carry__2_i_1_n_0,__0_carry__2_i_2_n_0,__0_carry__2_i_3_n_0,__0_carry__2_i_4_n_0}),
- .O(data_cnt1_in[15:12]),
- .S({__0_carry__2_i_5_n_0,__0_carry__2_i_6_n_0,__0_carry__2_i_7_n_0,__0_carry__2_i_8_n_0}));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__2_i_1
- (.I0(packet_number_reg[14]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[14] ),
- .I3(L__0[14]),
- .I4(write_state_reg[0]),
- .O(__0_carry__2_i_1_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__2_i_2
- (.I0(packet_number_reg[13]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[13] ),
- .I3(L__0[13]),
- .I4(write_state_reg[0]),
- .O(__0_carry__2_i_2_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__2_i_3
- (.I0(packet_number_reg[12]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[12] ),
- .I3(L__0[12]),
- .I4(write_state_reg[0]),
- .O(__0_carry__2_i_3_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__2_i_4
- (.I0(packet_number_reg[11]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[11] ),
- .I3(L__0[11]),
- .I4(write_state_reg[0]),
- .O(__0_carry__2_i_4_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__2_i_5
- (.I0(__0_carry__2_i_1_n_0),
- .I1(packet_number_reg[15]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[15] ),
- .I4(L__0[15]),
- .I5(write_state_reg[0]),
- .O(__0_carry__2_i_5_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__2_i_6
- (.I0(__0_carry__2_i_2_n_0),
- .I1(packet_number_reg[14]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[14] ),
- .I4(L__0[14]),
- .I5(write_state_reg[0]),
- .O(__0_carry__2_i_6_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__2_i_7
- (.I0(__0_carry__2_i_3_n_0),
- .I1(packet_number_reg[13]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[13] ),
- .I4(L__0[13]),
- .I5(write_state_reg[0]),
- .O(__0_carry__2_i_7_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry__2_i_8
- (.I0(__0_carry__2_i_4_n_0),
- .I1(packet_number_reg[12]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[12] ),
- .I4(L__0[12]),
- .I5(write_state_reg[0]),
- .O(__0_carry__2_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __0_carry__3
- (.CI(__0_carry__2_n_0),
- .CO({__0_carry__3_n_0,__0_carry__3_n_1,__0_carry__3_n_2,__0_carry__3_n_3}),
- .CYINIT(1'b0),
- .DI({__0_carry__3_i_1_n_0,__0_carry__3_i_2_n_0,__0_carry__3_i_3_n_0,__0_carry__3_i_4_n_0}),
- .O(data_cnt1_in[19:16]),
- .S({__0_carry__3_i_5_n_0,__0_carry__3_i_6_n_0,__0_carry__3_i_7_n_0,__0_carry__3_i_8_n_0}));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__3_i_1
- (.I0(\data_cnt_reg_n_0_[18] ),
- .I1(write_state_reg[1]),
- .I2(L__0[18]),
- .I3(write_state_reg[0]),
- .O(__0_carry__3_i_1_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__3_i_2
- (.I0(\data_cnt_reg_n_0_[17] ),
- .I1(write_state_reg[1]),
- .I2(L__0[17]),
- .I3(write_state_reg[0]),
- .O(__0_carry__3_i_2_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__3_i_3
- (.I0(\data_cnt_reg_n_0_[16] ),
- .I1(write_state_reg[1]),
- .I2(L__0[16]),
- .I3(write_state_reg[0]),
- .O(__0_carry__3_i_3_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry__3_i_4
- (.I0(packet_number_reg[15]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[15] ),
- .I3(L__0[15]),
- .I4(write_state_reg[0]),
- .O(__0_carry__3_i_4_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__3_i_5
- (.I0(L__0[18]),
- .I1(\data_cnt_reg_n_0_[18] ),
- .I2(\data_cnt_reg_n_0_[19] ),
- .I3(write_state_reg[1]),
- .I4(L__0[19]),
- .I5(write_state_reg[0]),
- .O(__0_carry__3_i_5_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__3_i_6
- (.I0(L__0[17]),
- .I1(\data_cnt_reg_n_0_[17] ),
- .I2(\data_cnt_reg_n_0_[18] ),
- .I3(write_state_reg[1]),
- .I4(L__0[18]),
- .I5(write_state_reg[0]),
- .O(__0_carry__3_i_6_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__3_i_7
- (.I0(L__0[16]),
- .I1(\data_cnt_reg_n_0_[16] ),
- .I2(\data_cnt_reg_n_0_[17] ),
- .I3(write_state_reg[1]),
- .I4(L__0[17]),
- .I5(write_state_reg[0]),
- .O(__0_carry__3_i_7_n_0));
- LUT5 #(
- .INIT(32'h9595956A))
- __0_carry__3_i_8
- (.I0(__0_carry__3_i_4_n_0),
- .I1(\data_cnt_reg_n_0_[16] ),
- .I2(write_state_reg[1]),
- .I3(L__0[16]),
- .I4(write_state_reg[0]),
- .O(__0_carry__3_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __0_carry__4
- (.CI(__0_carry__3_n_0),
- .CO({__0_carry__4_n_0,__0_carry__4_n_1,__0_carry__4_n_2,__0_carry__4_n_3}),
- .CYINIT(1'b0),
- .DI({__0_carry__4_i_1_n_0,__0_carry__4_i_2_n_0,__0_carry__4_i_3_n_0,__0_carry__4_i_4_n_0}),
- .O(data_cnt1_in[23:20]),
- .S({__0_carry__4_i_5_n_0,__0_carry__4_i_6_n_0,__0_carry__4_i_7_n_0,__0_carry__4_i_8_n_0}));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__4_i_1
- (.I0(\data_cnt_reg_n_0_[22] ),
- .I1(write_state_reg[1]),
- .I2(L__0[22]),
- .I3(write_state_reg[0]),
- .O(__0_carry__4_i_1_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__4_i_2
- (.I0(\data_cnt_reg_n_0_[21] ),
- .I1(write_state_reg[1]),
- .I2(L__0[21]),
- .I3(write_state_reg[0]),
- .O(__0_carry__4_i_2_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__4_i_3
- (.I0(\data_cnt_reg_n_0_[20] ),
- .I1(write_state_reg[1]),
- .I2(L__0[20]),
- .I3(write_state_reg[0]),
- .O(__0_carry__4_i_3_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__4_i_4
- (.I0(\data_cnt_reg_n_0_[19] ),
- .I1(write_state_reg[1]),
- .I2(L__0[19]),
- .I3(write_state_reg[0]),
- .O(__0_carry__4_i_4_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__4_i_5
- (.I0(L__0[22]),
- .I1(\data_cnt_reg_n_0_[22] ),
- .I2(\data_cnt_reg_n_0_[23] ),
- .I3(write_state_reg[1]),
- .I4(L__0[23]),
- .I5(write_state_reg[0]),
- .O(__0_carry__4_i_5_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__4_i_6
- (.I0(L__0[21]),
- .I1(\data_cnt_reg_n_0_[21] ),
- .I2(\data_cnt_reg_n_0_[22] ),
- .I3(write_state_reg[1]),
- .I4(L__0[22]),
- .I5(write_state_reg[0]),
- .O(__0_carry__4_i_6_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__4_i_7
- (.I0(L__0[20]),
- .I1(\data_cnt_reg_n_0_[20] ),
- .I2(\data_cnt_reg_n_0_[21] ),
- .I3(write_state_reg[1]),
- .I4(L__0[21]),
- .I5(write_state_reg[0]),
- .O(__0_carry__4_i_7_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__4_i_8
- (.I0(L__0[19]),
- .I1(\data_cnt_reg_n_0_[19] ),
- .I2(\data_cnt_reg_n_0_[20] ),
- .I3(write_state_reg[1]),
- .I4(L__0[20]),
- .I5(write_state_reg[0]),
- .O(__0_carry__4_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __0_carry__5
- (.CI(__0_carry__4_n_0),
- .CO({__0_carry__5_n_0,__0_carry__5_n_1,__0_carry__5_n_2,__0_carry__5_n_3}),
- .CYINIT(1'b0),
- .DI({__0_carry__5_i_1_n_0,__0_carry__5_i_2_n_0,__0_carry__5_i_3_n_0,__0_carry__5_i_4_n_0}),
- .O(data_cnt1_in[27:24]),
- .S({__0_carry__5_i_5_n_0,__0_carry__5_i_6_n_0,__0_carry__5_i_7_n_0,__0_carry__5_i_8_n_0}));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__5_i_1
- (.I0(\data_cnt_reg_n_0_[26] ),
- .I1(write_state_reg[1]),
- .I2(L__0[26]),
- .I3(write_state_reg[0]),
- .O(__0_carry__5_i_1_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__5_i_2
- (.I0(\data_cnt_reg_n_0_[25] ),
- .I1(write_state_reg[1]),
- .I2(L__0[25]),
- .I3(write_state_reg[0]),
- .O(__0_carry__5_i_2_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__5_i_3
- (.I0(\data_cnt_reg_n_0_[24] ),
- .I1(write_state_reg[1]),
- .I2(L__0[24]),
- .I3(write_state_reg[0]),
- .O(__0_carry__5_i_3_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__5_i_4
- (.I0(\data_cnt_reg_n_0_[23] ),
- .I1(write_state_reg[1]),
- .I2(L__0[23]),
- .I3(write_state_reg[0]),
- .O(__0_carry__5_i_4_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__5_i_5
- (.I0(L__0[26]),
- .I1(\data_cnt_reg_n_0_[26] ),
- .I2(\data_cnt_reg_n_0_[27] ),
- .I3(write_state_reg[1]),
- .I4(L__0[27]),
- .I5(write_state_reg[0]),
- .O(__0_carry__5_i_5_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__5_i_6
- (.I0(L__0[25]),
- .I1(\data_cnt_reg_n_0_[25] ),
- .I2(\data_cnt_reg_n_0_[26] ),
- .I3(write_state_reg[1]),
- .I4(L__0[26]),
- .I5(write_state_reg[0]),
- .O(__0_carry__5_i_6_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__5_i_7
- (.I0(L__0[24]),
- .I1(\data_cnt_reg_n_0_[24] ),
- .I2(\data_cnt_reg_n_0_[25] ),
- .I3(write_state_reg[1]),
- .I4(L__0[25]),
- .I5(write_state_reg[0]),
- .O(__0_carry__5_i_7_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__5_i_8
- (.I0(L__0[23]),
- .I1(\data_cnt_reg_n_0_[23] ),
- .I2(\data_cnt_reg_n_0_[24] ),
- .I3(write_state_reg[1]),
- .I4(L__0[24]),
- .I5(write_state_reg[0]),
- .O(__0_carry__5_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __0_carry__6
- (.CI(__0_carry__5_n_0),
- .CO({NLW___0_carry__6_CO_UNCONNECTED[3],__0_carry__6_n_1,__0_carry__6_n_2,__0_carry__6_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,__0_carry__6_i_1_n_0,__0_carry__6_i_2_n_0,__0_carry__6_i_3_n_0}),
- .O(data_cnt1_in[31:28]),
- .S({__0_carry__6_i_4_n_0,__0_carry__6_i_5_n_0,__0_carry__6_i_6_n_0,__0_carry__6_i_7_n_0}));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__6_i_1
- (.I0(\data_cnt_reg_n_0_[29] ),
- .I1(write_state_reg[1]),
- .I2(L__0[29]),
- .I3(write_state_reg[0]),
- .O(__0_carry__6_i_1_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__6_i_2
- (.I0(\data_cnt_reg_n_0_[28] ),
- .I1(write_state_reg[1]),
- .I2(L__0[28]),
- .I3(write_state_reg[0]),
- .O(__0_carry__6_i_2_n_0));
- LUT4 #(
- .INIT(16'h8880))
- __0_carry__6_i_3
- (.I0(\data_cnt_reg_n_0_[27] ),
- .I1(write_state_reg[1]),
- .I2(L__0[27]),
- .I3(write_state_reg[0]),
- .O(__0_carry__6_i_3_n_0));
- LUT6 #(
- .INIT(64'hC8C7FFF03738FFF0))
- __0_carry__6_i_4
- (.I0(L__0[30]),
- .I1(\data_cnt_reg_n_0_[30] ),
- .I2(write_state_reg[0]),
- .I3(L__0[31]),
- .I4(write_state_reg[1]),
- .I5(\data_cnt_reg_n_0_[31] ),
- .O(__0_carry__6_i_4_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__6_i_5
- (.I0(L__0[29]),
- .I1(\data_cnt_reg_n_0_[29] ),
- .I2(\data_cnt_reg_n_0_[30] ),
- .I3(write_state_reg[1]),
- .I4(L__0[30]),
- .I5(write_state_reg[0]),
- .O(__0_carry__6_i_5_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__6_i_6
- (.I0(L__0[28]),
- .I1(\data_cnt_reg_n_0_[28] ),
- .I2(\data_cnt_reg_n_0_[29] ),
- .I3(write_state_reg[1]),
- .I4(L__0[29]),
- .I5(write_state_reg[0]),
- .O(__0_carry__6_i_6_n_0));
- LUT6 #(
- .INIT(64'hC3FFC3FF87FF7800))
- __0_carry__6_i_7
- (.I0(L__0[27]),
- .I1(\data_cnt_reg_n_0_[27] ),
- .I2(\data_cnt_reg_n_0_[28] ),
- .I3(write_state_reg[1]),
- .I4(L__0[28]),
- .I5(write_state_reg[0]),
- .O(__0_carry__6_i_7_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry_i_1
- (.I0(packet_number_reg[2]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[2] ),
- .I3(L__0[2]),
- .I4(write_state_reg[0]),
- .O(__0_carry_i_1_n_0));
- LUT5 #(
- .INIT(32'hE2E2E200))
- __0_carry_i_2
- (.I0(packet_number_reg[1]),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[1] ),
- .I3(L__0[1]),
- .I4(write_state_reg[0]),
- .O(__0_carry_i_2_n_0));
- LUT5 #(
- .INIT(32'hEEE000E0))
- __0_carry_i_3
- (.I0(L__0[0]),
- .I1(write_state_reg[0]),
- .I2(packet_number_reg[0]),
- .I3(write_state_reg[1]),
- .I4(\data_cnt_reg_n_0_[0] ),
- .O(__0_carry_i_3_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry_i_4
- (.I0(__0_carry_i_1_n_0),
- .I1(packet_number_reg[3]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[3] ),
- .I4(L__0[3]),
- .I5(write_state_reg[0]),
- .O(__0_carry_i_4_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry_i_5
- (.I0(__0_carry_i_2_n_0),
- .I1(packet_number_reg[2]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[2] ),
- .I4(L__0[2]),
- .I5(write_state_reg[0]),
- .O(__0_carry_i_5_n_0));
- LUT6 #(
- .INIT(64'hA959A959A95956A6))
- __0_carry_i_6
- (.I0(__0_carry_i_3_n_0),
- .I1(packet_number_reg[1]),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[1] ),
- .I4(L__0[1]),
- .I5(write_state_reg[0]),
- .O(__0_carry_i_6_n_0));
- LUT5 #(
- .INIT(32'h03FC5656))
- __0_carry_i_7
- (.I0(packet_number_reg[0]),
- .I1(write_state_reg[0]),
- .I2(L__0[0]),
- .I3(\data_cnt_reg_n_0_[0] ),
- .I4(write_state_reg[1]),
- .O(__0_carry_i_7_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __93_carry
- (.CI(1'b0),
- .CO({__93_carry_n_0,__93_carry_n_1,__93_carry_n_2,__93_carry_n_3}),
- .CYINIT(__93_carry_i_1_n_0),
- .DI({__93_carry_i_2_n_0,__93_carry_i_3_n_0,__93_carry_i_4_n_0,__93_carry_i_5_n_0}),
- .O(data_cnt[4:1]),
- .S({__93_carry_i_6_n_0,__93_carry_i_7_n_0,__93_carry_i_8_n_0,__93_carry_i_9_n_0}));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __93_carry__0
- (.CI(__93_carry_n_0),
- .CO({__93_carry__0_n_0,__93_carry__0_n_1,__93_carry__0_n_2,__93_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({__93_carry__0_i_1_n_0,__93_carry__0_i_2_n_0,__93_carry__0_i_3_n_0,__93_carry__0_i_4_n_0}),
- .O(data_cnt[8:5]),
- .S({__93_carry__0_i_5_n_0,__93_carry__0_i_6_n_0,__93_carry__0_i_7_n_0,__93_carry__0_i_8_n_0}));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__0_i_1
- (.I0(\data_cnt_reg[8]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[8]),
- .O(__93_carry__0_i_1_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__0_i_2
- (.I0(\data_cnt_reg[7]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[7]),
- .O(__93_carry__0_i_2_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__0_i_3
- (.I0(\data_cnt_reg[6]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[6]),
- .O(__93_carry__0_i_3_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__0_i_4
- (.I0(\data_cnt_reg[5]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[5]),
- .O(__93_carry__0_i_4_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__0_i_5
- (.I0(L__0[8]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[8]__0_n_0 ),
- .O(__93_carry__0_i_5_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__0_i_6
- (.I0(L__0[7]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[7]__0_n_0 ),
- .O(__93_carry__0_i_6_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__0_i_7
- (.I0(L__0[6]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[6]__0_n_0 ),
- .O(__93_carry__0_i_7_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__0_i_8
- (.I0(L__0[5]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[5]__0_n_0 ),
- .O(__93_carry__0_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __93_carry__1
- (.CI(__93_carry__0_n_0),
- .CO({__93_carry__1_n_0,__93_carry__1_n_1,__93_carry__1_n_2,__93_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({__93_carry__1_i_1_n_0,__93_carry__1_i_2_n_0,__93_carry__1_i_3_n_0,__93_carry__1_i_4_n_0}),
- .O(data_cnt[12:9]),
- .S({__93_carry__1_i_5_n_0,__93_carry__1_i_6_n_0,__93_carry__1_i_7_n_0,__93_carry__1_i_8_n_0}));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__1_i_1
- (.I0(\data_cnt_reg[12]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[12]),
- .O(__93_carry__1_i_1_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__1_i_2
- (.I0(\data_cnt_reg[11]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[11]),
- .O(__93_carry__1_i_2_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__1_i_3
- (.I0(\data_cnt_reg[10]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[10]),
- .O(__93_carry__1_i_3_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__1_i_4
- (.I0(\data_cnt_reg[9]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[9]),
- .O(__93_carry__1_i_4_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__1_i_5
- (.I0(L__0[12]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[12]__0_n_0 ),
- .O(__93_carry__1_i_5_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__1_i_6
- (.I0(L__0[11]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[11]__0_n_0 ),
- .O(__93_carry__1_i_6_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__1_i_7
- (.I0(L__0[10]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[10]__0_n_0 ),
- .O(__93_carry__1_i_7_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__1_i_8
- (.I0(L__0[9]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[9]__0_n_0 ),
- .O(__93_carry__1_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __93_carry__2
- (.CI(__93_carry__1_n_0),
- .CO({__93_carry__2_n_0,__93_carry__2_n_1,__93_carry__2_n_2,__93_carry__2_n_3}),
- .CYINIT(1'b0),
- .DI({__93_carry__2_i_1_n_0,__93_carry__2_i_2_n_0,__93_carry__2_i_3_n_0,__93_carry__2_i_4_n_0}),
- .O(data_cnt[16:13]),
- .S({__93_carry__2_i_5_n_0,__93_carry__2_i_6_n_0,__93_carry__2_i_7_n_0,__93_carry__2_i_8_n_0}));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__2_i_1
- (.I0(\data_cnt_reg[16]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[16]),
- .O(__93_carry__2_i_1_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__2_i_2
- (.I0(\data_cnt_reg[15]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[15]),
- .O(__93_carry__2_i_2_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__2_i_3
- (.I0(\data_cnt_reg[14]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[14]),
- .O(__93_carry__2_i_3_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__2_i_4
- (.I0(\data_cnt_reg[13]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[13]),
- .O(__93_carry__2_i_4_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__2_i_5
- (.I0(L__0[16]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[16]__0_n_0 ),
- .O(__93_carry__2_i_5_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__2_i_6
- (.I0(L__0[15]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[15]__0_n_0 ),
- .O(__93_carry__2_i_6_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__2_i_7
- (.I0(L__0[14]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[14]__0_n_0 ),
- .O(__93_carry__2_i_7_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__2_i_8
- (.I0(L__0[13]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[13]__0_n_0 ),
- .O(__93_carry__2_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __93_carry__3
- (.CI(__93_carry__2_n_0),
- .CO({__93_carry__3_n_0,__93_carry__3_n_1,__93_carry__3_n_2,__93_carry__3_n_3}),
- .CYINIT(1'b0),
- .DI({__93_carry__3_i_1_n_0,__93_carry__3_i_2_n_0,__93_carry__3_i_3_n_0,__93_carry__3_i_4_n_0}),
- .O(data_cnt[20:17]),
- .S({__93_carry__3_i_5_n_0,__93_carry__3_i_6_n_0,__93_carry__3_i_7_n_0,__93_carry__3_i_8_n_0}));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__3_i_1
- (.I0(\data_cnt_reg[20]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[20]),
- .O(__93_carry__3_i_1_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__3_i_2
- (.I0(\data_cnt_reg[19]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[19]),
- .O(__93_carry__3_i_2_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__3_i_3
- (.I0(\data_cnt_reg[18]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[18]),
- .O(__93_carry__3_i_3_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__3_i_4
- (.I0(\data_cnt_reg[17]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[17]),
- .O(__93_carry__3_i_4_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__3_i_5
- (.I0(L__0[20]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[20]__0_n_0 ),
- .O(__93_carry__3_i_5_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__3_i_6
- (.I0(L__0[19]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[19]__0_n_0 ),
- .O(__93_carry__3_i_6_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__3_i_7
- (.I0(L__0[18]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[18]__0_n_0 ),
- .O(__93_carry__3_i_7_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__3_i_8
- (.I0(L__0[17]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[17]__0_n_0 ),
- .O(__93_carry__3_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __93_carry__4
- (.CI(__93_carry__3_n_0),
- .CO({__93_carry__4_n_0,__93_carry__4_n_1,__93_carry__4_n_2,__93_carry__4_n_3}),
- .CYINIT(1'b0),
- .DI({__93_carry__4_i_1_n_0,__93_carry__4_i_2_n_0,__93_carry__4_i_3_n_0,__93_carry__4_i_4_n_0}),
- .O(data_cnt[24:21]),
- .S({__93_carry__4_i_5_n_0,__93_carry__4_i_6_n_0,__93_carry__4_i_7_n_0,__93_carry__4_i_8_n_0}));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__4_i_1
- (.I0(\data_cnt_reg[24]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[24]),
- .O(__93_carry__4_i_1_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__4_i_2
- (.I0(\data_cnt_reg[23]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[23]),
- .O(__93_carry__4_i_2_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__4_i_3
- (.I0(\data_cnt_reg[22]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[22]),
- .O(__93_carry__4_i_3_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__4_i_4
- (.I0(\data_cnt_reg[21]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[21]),
- .O(__93_carry__4_i_4_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__4_i_5
- (.I0(L__0[24]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[24]__0_n_0 ),
- .O(__93_carry__4_i_5_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__4_i_6
- (.I0(L__0[23]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[23]__0_n_0 ),
- .O(__93_carry__4_i_6_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__4_i_7
- (.I0(L__0[22]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[22]__0_n_0 ),
- .O(__93_carry__4_i_7_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__4_i_8
- (.I0(L__0[21]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[21]__0_n_0 ),
- .O(__93_carry__4_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __93_carry__5
- (.CI(__93_carry__4_n_0),
- .CO({__93_carry__5_n_0,__93_carry__5_n_1,__93_carry__5_n_2,__93_carry__5_n_3}),
- .CYINIT(1'b0),
- .DI({__93_carry__5_i_1_n_0,__93_carry__5_i_2_n_0,__93_carry__5_i_3_n_0,__93_carry__5_i_4_n_0}),
- .O(data_cnt[28:25]),
- .S({__93_carry__5_i_5_n_0,__93_carry__5_i_6_n_0,__93_carry__5_i_7_n_0,__93_carry__5_i_8_n_0}));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__5_i_1
- (.I0(\data_cnt_reg[28]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[28]),
- .O(__93_carry__5_i_1_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__5_i_2
- (.I0(\data_cnt_reg[27]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[27]),
- .O(__93_carry__5_i_2_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__5_i_3
- (.I0(\data_cnt_reg[26]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[26]),
- .O(__93_carry__5_i_3_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__5_i_4
- (.I0(\data_cnt_reg[25]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[25]),
- .O(__93_carry__5_i_4_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__5_i_5
- (.I0(L__0[28]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[28]__0_n_0 ),
- .O(__93_carry__5_i_5_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__5_i_6
- (.I0(L__0[27]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[27]__0_n_0 ),
- .O(__93_carry__5_i_6_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__5_i_7
- (.I0(L__0[26]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[26]__0_n_0 ),
- .O(__93_carry__5_i_7_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__5_i_8
- (.I0(L__0[25]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[25]__0_n_0 ),
- .O(__93_carry__5_i_8_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 __93_carry__6
- (.CI(__93_carry__5_n_0),
- .CO({NLW___93_carry__6_CO_UNCONNECTED[3:2],__93_carry__6_n_2,__93_carry__6_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,__93_carry__6_i_1_n_0,__93_carry__6_i_2_n_0}),
- .O({NLW___93_carry__6_O_UNCONNECTED[3],data_cnt[31:29]}),
- .S({1'b0,__93_carry__6_i_3_n_0,__93_carry__6_i_4_n_0,__93_carry__6_i_5_n_0}));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry__6_i_1
- (.I0(\data_cnt_reg[30]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[30]),
- .O(__93_carry__6_i_1_n_0));
- LUT3 #(
- .INIT(8'hE2))
- __93_carry__6_i_2
- (.I0(L__0[29]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[29]__0_n_0 ),
- .O(__93_carry__6_i_2_n_0));
- LUT3 #(
- .INIT(8'h47))
- __93_carry__6_i_3
- (.I0(\data_cnt_reg[31]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[31]),
- .O(__93_carry__6_i_3_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry__6_i_4
- (.I0(L__0[30]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[30]__0_n_0 ),
- .O(__93_carry__6_i_4_n_0));
- LUT3 #(
- .INIT(8'h47))
- __93_carry__6_i_5
- (.I0(\data_cnt_reg[29]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[29]),
- .O(__93_carry__6_i_5_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry_i_1
- (.I0(\data_cnt_reg[0]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[0]),
- .O(__93_carry_i_1_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry_i_2
- (.I0(\data_cnt_reg[4]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[4]),
- .O(__93_carry_i_2_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry_i_3
- (.I0(\data_cnt_reg[3]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[3]),
- .O(__93_carry_i_3_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry_i_4
- (.I0(\data_cnt_reg[2]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[2]),
- .O(__93_carry_i_4_n_0));
- LUT3 #(
- .INIT(8'hB8))
- __93_carry_i_5
- (.I0(\data_cnt_reg[1]__0_n_0 ),
- .I1(read_state_reg[0]),
- .I2(L__0[1]),
- .O(__93_carry_i_5_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry_i_6
- (.I0(L__0[4]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[4]__0_n_0 ),
- .O(__93_carry_i_6_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry_i_7
- (.I0(L__0[3]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[3]__0_n_0 ),
- .O(__93_carry_i_7_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry_i_8
- (.I0(L__0[2]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[2]__0_n_0 ),
- .O(__93_carry_i_8_n_0));
- LUT3 #(
- .INIT(8'h1D))
- __93_carry_i_9
- (.I0(L__0[1]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[1]__0_n_0 ),
- .O(__93_carry_i_9_n_0));
- LUT4 #(
- .INIT(16'h7774))
- \burst_data_cnt[0]_i_1
- (.I0(\burst_data_cnt_reg_n_0_[0] ),
- .I1(write_state_reg[1]),
- .I2(\data_cnt_reg_n_0_[0] ),
- .I3(M_AXI_AWVALID_i_4_n_0),
- .O(burst_data_cnt[0]));
- LUT5 #(
- .INIT(32'h9F9F9F90))
- \burst_data_cnt[1]_i_1
- (.I0(\burst_data_cnt_reg_n_0_[1] ),
- .I1(\burst_data_cnt_reg_n_0_[0] ),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[1] ),
- .I4(M_AXI_AWVALID_i_4_n_0),
- .O(burst_data_cnt[1]));
- LUT6 #(
- .INIT(64'hE1FFE1FFE1FFE100))
- \burst_data_cnt[2]_i_1
- (.I0(\burst_data_cnt_reg_n_0_[1] ),
- .I1(\burst_data_cnt_reg_n_0_[0] ),
- .I2(\burst_data_cnt_reg_n_0_[2] ),
- .I3(write_state_reg[1]),
- .I4(\data_cnt_reg_n_0_[2] ),
- .I5(M_AXI_AWVALID_i_4_n_0),
- .O(burst_data_cnt[2]));
- LUT5 #(
- .INIT(32'h9F9F9F90))
- \burst_data_cnt[3]_i_1
- (.I0(\burst_data_cnt[4]_i_3_n_0 ),
- .I1(\burst_data_cnt_reg_n_0_[3] ),
- .I2(write_state_reg[1]),
- .I3(\data_cnt_reg_n_0_[3] ),
- .I4(M_AXI_AWVALID_i_4_n_0),
- .O(burst_data_cnt[3]));
- LUT6 #(
- .INIT(64'h2300230023002000))
- \burst_data_cnt[4]_i_1
- (.I0(M_AXI_WREADY),
- .I1(write_state_reg[2]),
- .I2(write_state_reg[1]),
- .I3(write_state_reg[0]),
- .I4(M_AXI_AWVALID_i_4_n_0),
- .I5(M_AXI_AWVALID_i_5_n_0),
- .O(\burst_data_cnt[4]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hE100E100E1FFE100))
- \burst_data_cnt[4]_i_2
- (.I0(\burst_data_cnt_reg_n_0_[3] ),
- .I1(\burst_data_cnt[4]_i_3_n_0 ),
- .I2(\burst_data_cnt_reg_n_0_[4] ),
- .I3(write_state_reg[1]),
- .I4(\data_cnt_reg_n_0_[4] ),
- .I5(M_AXI_AWVALID_i_4_n_0),
- .O(burst_data_cnt[4]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT3 #(
- .INIT(8'hFE))
- \burst_data_cnt[4]_i_3
- (.I0(\burst_data_cnt_reg_n_0_[2] ),
- .I1(\burst_data_cnt_reg_n_0_[0] ),
- .I2(\burst_data_cnt_reg_n_0_[1] ),
- .O(\burst_data_cnt[4]_i_3_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \burst_data_cnt_reg[0]
- (.C(CLK),
- .CE(\burst_data_cnt[4]_i_1_n_0 ),
- .D(burst_data_cnt[0]),
- .Q(\burst_data_cnt_reg_n_0_[0] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \burst_data_cnt_reg[1]
- (.C(CLK),
- .CE(\burst_data_cnt[4]_i_1_n_0 ),
- .D(burst_data_cnt[1]),
- .Q(\burst_data_cnt_reg_n_0_[1] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \burst_data_cnt_reg[2]
- (.C(CLK),
- .CE(\burst_data_cnt[4]_i_1_n_0 ),
- .D(burst_data_cnt[2]),
- .Q(\burst_data_cnt_reg_n_0_[2] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \burst_data_cnt_reg[3]
- (.C(CLK),
- .CE(\burst_data_cnt[4]_i_1_n_0 ),
- .D(burst_data_cnt[3]),
- .Q(\burst_data_cnt_reg_n_0_[3] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \burst_data_cnt_reg[4]
- (.C(CLK),
- .CE(\burst_data_cnt[4]_i_1_n_0 ),
- .D(burst_data_cnt[4]),
- .Q(\burst_data_cnt_reg_n_0_[4] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h1D))
- \data_cnt[0]__0_i_1
- (.I0(L__0[0]),
- .I1(read_state_reg[0]),
- .I2(\data_cnt_reg[0]__0_n_0 ),
- .O(data_cnt[0]));
- LUT5 #(
- .INIT(32'h00008380))
- \data_cnt[31]_i_1
- (.I0(M_AXI_WREADY),
- .I1(write_state_reg[1]),
- .I2(write_state_reg[0]),
- .I3(p_5_in[0]),
- .I4(write_state_reg[2]),
- .O(data_cnt_3));
- FDRE \data_cnt_reg[0]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[0]),
- .Q(\data_cnt_reg_n_0_[0] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[0]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[0]),
- .Q(\data_cnt_reg[0]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[10]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[10]),
- .Q(\data_cnt_reg_n_0_[10] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[10]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[10]),
- .Q(\data_cnt_reg[10]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[11]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[11]),
- .Q(\data_cnt_reg_n_0_[11] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[11]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[11]),
- .Q(\data_cnt_reg[11]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[12]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[12]),
- .Q(\data_cnt_reg_n_0_[12] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[12]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[12]),
- .Q(\data_cnt_reg[12]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[13]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[13]),
- .Q(\data_cnt_reg_n_0_[13] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[13]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[13]),
- .Q(\data_cnt_reg[13]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[14]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[14]),
- .Q(\data_cnt_reg_n_0_[14] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[14]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[14]),
- .Q(\data_cnt_reg[14]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[15]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[15]),
- .Q(\data_cnt_reg_n_0_[15] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[15]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[15]),
- .Q(\data_cnt_reg[15]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[16]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[16]),
- .Q(\data_cnt_reg_n_0_[16] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[16]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[16]),
- .Q(\data_cnt_reg[16]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[17]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[17]),
- .Q(\data_cnt_reg_n_0_[17] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[17]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[17]),
- .Q(\data_cnt_reg[17]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[18]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[18]),
- .Q(\data_cnt_reg_n_0_[18] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[18]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[18]),
- .Q(\data_cnt_reg[18]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[19]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[19]),
- .Q(\data_cnt_reg_n_0_[19] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[19]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[19]),
- .Q(\data_cnt_reg[19]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[1]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[1]),
- .Q(\data_cnt_reg_n_0_[1] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[1]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[1]),
- .Q(\data_cnt_reg[1]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[20]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[20]),
- .Q(\data_cnt_reg_n_0_[20] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[20]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[20]),
- .Q(\data_cnt_reg[20]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[21]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[21]),
- .Q(\data_cnt_reg_n_0_[21] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[21]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[21]),
- .Q(\data_cnt_reg[21]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[22]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[22]),
- .Q(\data_cnt_reg_n_0_[22] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[22]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[22]),
- .Q(\data_cnt_reg[22]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[23]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[23]),
- .Q(\data_cnt_reg_n_0_[23] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[23]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[23]),
- .Q(\data_cnt_reg[23]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[24]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[24]),
- .Q(\data_cnt_reg_n_0_[24] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[24]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[24]),
- .Q(\data_cnt_reg[24]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[25]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[25]),
- .Q(\data_cnt_reg_n_0_[25] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[25]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[25]),
- .Q(\data_cnt_reg[25]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[26]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[26]),
- .Q(\data_cnt_reg_n_0_[26] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[26]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[26]),
- .Q(\data_cnt_reg[26]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[27]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[27]),
- .Q(\data_cnt_reg_n_0_[27] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[27]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[27]),
- .Q(\data_cnt_reg[27]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[28]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[28]),
- .Q(\data_cnt_reg_n_0_[28] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[28]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[28]),
- .Q(\data_cnt_reg[28]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[29]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[29]),
- .Q(\data_cnt_reg_n_0_[29] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[29]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[29]),
- .Q(\data_cnt_reg[29]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[2]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[2]),
- .Q(\data_cnt_reg_n_0_[2] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[2]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[2]),
- .Q(\data_cnt_reg[2]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[30]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[30]),
- .Q(\data_cnt_reg_n_0_[30] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[30]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[30]),
- .Q(\data_cnt_reg[30]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[31]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[31]),
- .Q(\data_cnt_reg_n_0_[31] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[31]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[31]),
- .Q(\data_cnt_reg[31]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[3]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[3]),
- .Q(\data_cnt_reg_n_0_[3] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[3]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[3]),
- .Q(\data_cnt_reg[3]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[4]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[4]),
- .Q(\data_cnt_reg_n_0_[4] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[4]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[4]),
- .Q(\data_cnt_reg[4]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[5]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[5]),
- .Q(\data_cnt_reg_n_0_[5] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[5]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[5]),
- .Q(\data_cnt_reg[5]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[6]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[6]),
- .Q(\data_cnt_reg_n_0_[6] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[6]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[6]),
- .Q(\data_cnt_reg[6]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[7]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[7]),
- .Q(\data_cnt_reg_n_0_[7] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[7]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[7]),
- .Q(\data_cnt_reg[7]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[8]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[8]),
- .Q(\data_cnt_reg_n_0_[8] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[8]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[8]),
- .Q(\data_cnt_reg[8]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[9]
- (.C(CLK),
- .CE(data_cnt_3),
- .D(data_cnt1_in[9]),
- .Q(\data_cnt_reg_n_0_[9] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \data_cnt_reg[9]__0
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(data_cnt[9]),
- .Q(\data_cnt_reg[9]__0_n_0 ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h00000002))
- \finalXOR_reg[31]_i_1
- (.I0(\finalXOR_reg[31]_i_2_n_0 ),
- .I1(S_AXIL_AWADDR[2]),
- .I2(S_AXIL_AWADDR[3]),
- .I3(S_AXIL_AWADDR[4]),
- .I4(\finalXOR_reg[31]_i_3_n_0 ),
- .O(\finalXOR_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h1000000000000000))
- \finalXOR_reg[31]_i_2
- (.I0(S_AXIL_AWADDR[0]),
- .I1(S_AXIL_AWADDR[1]),
- .I2(S_AXIL_WSTRB[3]),
- .I3(S_AXIL_WSTRB[2]),
- .I4(S_AXIL_WSTRB[0]),
- .I5(S_AXIL_WSTRB[1]),
- .O(\finalXOR_reg[31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'hFDFFFFFF))
- \finalXOR_reg[31]_i_3
- (.I0(S_AXIL_AWADDR[5]),
- .I1(S_AXIL_AWADDR[6]),
- .I2(S_AXIL_AWADDR[7]),
- .I3(S_AXIL_AWVALID),
- .I4(S_AXIL_WVALID),
- .O(\finalXOR_reg[31]_i_3_n_0 ));
- FDRE \finalXOR_reg_reg[0]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[0]),
- .Q(finalXOR[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[10]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[10]),
- .Q(finalXOR[10]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[11]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[11]),
- .Q(finalXOR[11]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[12]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[12]),
- .Q(finalXOR[12]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[13]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[13]),
- .Q(finalXOR[13]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[14]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[14]),
- .Q(finalXOR[14]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[15]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[15]),
- .Q(finalXOR[15]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[16]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[16]),
- .Q(finalXOR[16]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[17]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[17]),
- .Q(finalXOR[17]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[18]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[18]),
- .Q(finalXOR[18]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[19]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[19]),
- .Q(finalXOR[19]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[1]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[1]),
- .Q(finalXOR[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[20]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[20]),
- .Q(finalXOR[20]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[21]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[21]),
- .Q(finalXOR[21]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[22]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[22]),
- .Q(finalXOR[22]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[23]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[23]),
- .Q(finalXOR[23]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[24]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[24]),
- .Q(finalXOR[24]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[25]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[25]),
- .Q(finalXOR[25]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[26]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[26]),
- .Q(finalXOR[26]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[27]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[27]),
- .Q(finalXOR[27]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[28]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[28]),
- .Q(finalXOR[28]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[29]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[29]),
- .Q(finalXOR[29]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[2]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[2]),
- .Q(finalXOR[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[30]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[30]),
- .Q(finalXOR[30]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[31]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[31]),
- .Q(finalXOR[31]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[3]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[3]),
- .Q(finalXOR[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[4]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[4]),
- .Q(finalXOR[4]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[5]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[5]),
- .Q(finalXOR[5]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[6]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[6]),
- .Q(finalXOR[6]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[7]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[7]),
- .Q(finalXOR[7]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[8]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[8]),
- .Q(finalXOR[8]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \finalXOR_reg_reg[9]
- (.C(CLK),
- .CE(\finalXOR_reg[31]_i_1_n_0 ),
- .D(S_AXIL_WDATA[9]),
- .Q(finalXOR[9]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \inOut_reflected_reg[0]_i_1
- (.I0(S_AXIL_WDATA[0]),
- .I1(inOut_reflected_reg),
- .I2(inOutReflected[0]),
- .O(\inOut_reflected_reg[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT3 #(
- .INIT(8'hB8))
- \inOut_reflected_reg[1]_i_1
- (.I0(S_AXIL_WDATA[1]),
- .I1(inOut_reflected_reg),
- .I2(inOutReflected[1]),
- .O(\inOut_reflected_reg[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000010000000000))
- \inOut_reflected_reg[1]_i_2
- (.I0(\finalXOR_reg[31]_i_3_n_0 ),
- .I1(S_AXIL_AWADDR[4]),
- .I2(S_AXIL_AWADDR[3]),
- .I3(S_AXIL_AWADDR[2]),
- .I4(\inOut_reflected_reg[1]_i_3_n_0 ),
- .I5(S_AXIL_WSTRB[0]),
- .O(inOut_reflected_reg));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT2 #(
- .INIT(4'hE))
- \inOut_reflected_reg[1]_i_3
- (.I0(S_AXIL_AWADDR[1]),
- .I1(S_AXIL_AWADDR[0]),
- .O(\inOut_reflected_reg[1]_i_3_n_0 ));
- FDRE \inOut_reflected_reg_reg[0]
- (.C(CLK),
- .CE(1'b1),
- .D(\inOut_reflected_reg[0]_i_1_n_0 ),
- .Q(inOutReflected[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \inOut_reflected_reg_reg[1]
- (.C(CLK),
- .CE(1'b1),
- .D(\inOut_reflected_reg[1]_i_1_n_0 ),
- .Q(inOutReflected[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \initial_value_reg[31]_i_1
- (.I0(RESETN),
- .O(\initial_value_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000000080000000))
- \initial_value_reg[31]_i_2
- (.I0(S_AXIL_WSTRB[1]),
- .I1(S_AXIL_WSTRB[0]),
- .I2(S_AXIL_WSTRB[2]),
- .I3(S_AXIL_WSTRB[3]),
- .I4(S_AXIL_AWADDR[3]),
- .I5(\initial_value_reg[31]_i_3_n_0 ),
- .O(initial_value_reg));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT5 #(
- .INIT(32'hFFFDFFFF))
- \initial_value_reg[31]_i_3
- (.I0(S_AXIL_AWADDR[4]),
- .I1(S_AXIL_AWADDR[5]),
- .I2(S_AXIL_AWADDR[7]),
- .I3(S_AXIL_AWADDR[6]),
- .I4(\initial_value_reg[31]_i_4_n_0 ),
- .O(\initial_value_reg[31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'h10000000))
- \initial_value_reg[31]_i_4
- (.I0(S_AXIL_AWADDR[0]),
- .I1(S_AXIL_AWADDR[1]),
- .I2(S_AXIL_WVALID),
- .I3(S_AXIL_AWVALID),
- .I4(S_AXIL_AWADDR[2]),
- .O(\initial_value_reg[31]_i_4_n_0 ));
- FDRE \initial_value_reg_reg[0]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[0]),
- .Q(initial_value[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[10]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[10]),
- .Q(initial_value[10]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[11]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[11]),
- .Q(initial_value[11]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[12]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[12]),
- .Q(initial_value[12]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[13]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[13]),
- .Q(initial_value[13]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[14]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[14]),
- .Q(initial_value[14]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[15]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[15]),
- .Q(initial_value[15]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[16]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[16]),
- .Q(initial_value[16]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[17]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[17]),
- .Q(initial_value[17]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[18]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[18]),
- .Q(initial_value[18]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[19]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[19]),
- .Q(initial_value[19]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[1]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[1]),
- .Q(initial_value[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[20]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[20]),
- .Q(initial_value[20]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[21]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[21]),
- .Q(initial_value[21]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[22]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[22]),
- .Q(initial_value[22]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[23]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[23]),
- .Q(initial_value[23]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[24]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[24]),
- .Q(initial_value[24]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[25]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[25]),
- .Q(initial_value[25]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[26]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[26]),
- .Q(initial_value[26]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[27]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[27]),
- .Q(initial_value[27]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[28]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[28]),
- .Q(initial_value[28]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[29]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[29]),
- .Q(initial_value[29]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[2]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[2]),
- .Q(initial_value[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[30]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[30]),
- .Q(initial_value[30]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[31]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[31]),
- .Q(initial_value[31]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[3]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[3]),
- .Q(initial_value[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[4]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[4]),
- .Q(initial_value[4]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[5]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[5]),
- .Q(initial_value[5]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[6]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[6]),
- .Q(initial_value[6]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[7]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[7]),
- .Q(initial_value[7]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[8]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[8]),
- .Q(initial_value[8]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \initial_value_reg_reg[9]
- (.C(CLK),
- .CE(initial_value_reg),
- .D(S_AXIL_WDATA[9]),
- .Q(initial_value[9]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT3 #(
- .INIT(8'hB8))
- interrupt_enable_reg_i_1
- (.I0(p_5_in[1]),
- .I1(run_reg_set_i_2_n_0),
- .I2(S_AXIL_WDATA[1]),
- .O(interrupt_enable_reg_i_1_n_0));
- FDRE interrupt_enable_reg_reg
- (.C(CLK),
- .CE(1'b1),
- .D(interrupt_enable_reg_i_1_n_0),
- .Q(p_5_in[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00003000AAAAAAAA))
- interrupt_reset_i_1
- (.I0(interrupt_reset_reg_n_0),
- .I1(S_AXIL_WDATA[0]),
- .I2(interrupt_reset_i_2_n_0),
- .I3(S_AXIL_WVALID_0),
- .I4(interrupt_reset_i_3_n_0),
- .I5(RESETN),
- .O(interrupt_reset_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h00000001))
- interrupt_reset_i_2
- (.I0(S_AXIL_AWADDR[3]),
- .I1(S_AXIL_AWADDR[5]),
- .I2(S_AXIL_AWADDR[7]),
- .I3(S_AXIL_AWADDR[6]),
- .I4(S_AXIL_AWADDR[4]),
- .O(interrupt_reset_i_2_n_0));
- LUT4 #(
- .INIT(16'hFDFF))
- interrupt_reset_i_3
- (.I0(S_AXIL_WSTRB[0]),
- .I1(S_AXIL_AWADDR[1]),
- .I2(S_AXIL_AWADDR[0]),
- .I3(S_AXIL_AWADDR[2]),
- .O(interrupt_reset_i_3_n_0));
- FDRE interrupt_reset_reg
- (.C(CLK),
- .CE(1'b1),
- .D(interrupt_reset_i_1_n_0),
- .Q(interrupt_reset_reg_n_0),
- .R(1'b0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 minusOp__28_carry
- (.CI(1'b0),
- .CO({minusOp__28_carry_n_0,minusOp__28_carry_n_1,minusOp__28_carry_n_2,minusOp__28_carry_n_3}),
- .CYINIT(\packet_data_cnt_reg_n_0_[0] ),
- .DI({\packet_data_cnt_reg_n_0_[4] ,\packet_data_cnt_reg_n_0_[3] ,\packet_data_cnt_reg_n_0_[2] ,\packet_data_cnt_reg_n_0_[1] }),
- .O(minusOp[4:1]),
- .S({minusOp__28_carry_i_1_n_0,minusOp__28_carry_i_2_n_0,minusOp__28_carry_i_3_n_0,minusOp__28_carry_i_4_n_0}));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 minusOp__28_carry__0
- (.CI(minusOp__28_carry_n_0),
- .CO({minusOp__28_carry__0_n_0,minusOp__28_carry__0_n_1,minusOp__28_carry__0_n_2,minusOp__28_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({\packet_data_cnt_reg_n_0_[8] ,\packet_data_cnt_reg_n_0_[7] ,\packet_data_cnt_reg_n_0_[6] ,\packet_data_cnt_reg_n_0_[5] }),
- .O(minusOp[8:5]),
- .S({minusOp__28_carry__0_i_1_n_0,minusOp__28_carry__0_i_2_n_0,minusOp__28_carry__0_i_3_n_0,minusOp__28_carry__0_i_4_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__0_i_1
- (.I0(\packet_data_cnt_reg_n_0_[8] ),
- .O(minusOp__28_carry__0_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__0_i_2
- (.I0(\packet_data_cnt_reg_n_0_[7] ),
- .O(minusOp__28_carry__0_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__0_i_3
- (.I0(\packet_data_cnt_reg_n_0_[6] ),
- .O(minusOp__28_carry__0_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__0_i_4
- (.I0(\packet_data_cnt_reg_n_0_[5] ),
- .O(minusOp__28_carry__0_i_4_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 minusOp__28_carry__1
- (.CI(minusOp__28_carry__0_n_0),
- .CO({minusOp__28_carry__1_n_0,minusOp__28_carry__1_n_1,minusOp__28_carry__1_n_2,minusOp__28_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({\packet_data_cnt_reg_n_0_[12] ,\packet_data_cnt_reg_n_0_[11] ,\packet_data_cnt_reg_n_0_[10] ,\packet_data_cnt_reg_n_0_[9] }),
- .O(minusOp[12:9]),
- .S({minusOp__28_carry__1_i_1_n_0,minusOp__28_carry__1_i_2_n_0,minusOp__28_carry__1_i_3_n_0,minusOp__28_carry__1_i_4_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__1_i_1
- (.I0(\packet_data_cnt_reg_n_0_[12] ),
- .O(minusOp__28_carry__1_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__1_i_2
- (.I0(\packet_data_cnt_reg_n_0_[11] ),
- .O(minusOp__28_carry__1_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__1_i_3
- (.I0(\packet_data_cnt_reg_n_0_[10] ),
- .O(minusOp__28_carry__1_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__1_i_4
- (.I0(\packet_data_cnt_reg_n_0_[9] ),
- .O(minusOp__28_carry__1_i_4_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 minusOp__28_carry__2
- (.CI(minusOp__28_carry__1_n_0),
- .CO({NLW_minusOp__28_carry__2_CO_UNCONNECTED[3:2],minusOp__28_carry__2_n_2,minusOp__28_carry__2_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,\packet_data_cnt_reg_n_0_[14] ,\packet_data_cnt_reg_n_0_[13] }),
- .O({NLW_minusOp__28_carry__2_O_UNCONNECTED[3],minusOp[15:13]}),
- .S({1'b0,minusOp__28_carry__2_i_1_n_0,minusOp__28_carry__2_i_2_n_0,minusOp__28_carry__2_i_3_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__2_i_1
- (.I0(\packet_data_cnt_reg_n_0_[15] ),
- .O(minusOp__28_carry__2_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__2_i_2
- (.I0(\packet_data_cnt_reg_n_0_[14] ),
- .O(minusOp__28_carry__2_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry__2_i_3
- (.I0(\packet_data_cnt_reg_n_0_[13] ),
- .O(minusOp__28_carry__2_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry_i_1
- (.I0(\packet_data_cnt_reg_n_0_[4] ),
- .O(minusOp__28_carry_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry_i_2
- (.I0(\packet_data_cnt_reg_n_0_[3] ),
- .O(minusOp__28_carry_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry_i_3
- (.I0(\packet_data_cnt_reg_n_0_[2] ),
- .O(minusOp__28_carry_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp__28_carry_i_4
- (.I0(\packet_data_cnt_reg_n_0_[1] ),
- .O(minusOp__28_carry_i_4_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 minusOp_carry
- (.CI(1'b0),
- .CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}),
- .CYINIT(\packets_cnt_reg_n_0_[0] ),
- .DI({\packets_cnt_reg_n_0_[4] ,\packets_cnt_reg_n_0_[3] ,\packets_cnt_reg_n_0_[2] ,\packets_cnt_reg_n_0_[1] }),
- .O(in8[4:1]),
- .S({minusOp_carry_i_1_n_0,minusOp_carry_i_2_n_0,minusOp_carry_i_3_n_0,minusOp_carry_i_4_n_0}));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 minusOp_carry__0
- (.CI(minusOp_carry_n_0),
- .CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({\packets_cnt_reg_n_0_[8] ,\packets_cnt_reg_n_0_[7] ,\packets_cnt_reg_n_0_[6] ,\packets_cnt_reg_n_0_[5] }),
- .O(in8[8:5]),
- .S({minusOp_carry__0_i_1_n_0,minusOp_carry__0_i_2_n_0,minusOp_carry__0_i_3_n_0,minusOp_carry__0_i_4_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_1
- (.I0(\packets_cnt_reg_n_0_[8] ),
- .O(minusOp_carry__0_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_2
- (.I0(\packets_cnt_reg_n_0_[7] ),
- .O(minusOp_carry__0_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_3
- (.I0(\packets_cnt_reg_n_0_[6] ),
- .O(minusOp_carry__0_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_4
- (.I0(\packets_cnt_reg_n_0_[5] ),
- .O(minusOp_carry__0_i_4_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 minusOp_carry__1
- (.CI(minusOp_carry__0_n_0),
- .CO({minusOp_carry__1_n_0,minusOp_carry__1_n_1,minusOp_carry__1_n_2,minusOp_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({\packets_cnt_reg_n_0_[12] ,\packets_cnt_reg_n_0_[11] ,\packets_cnt_reg_n_0_[10] ,\packets_cnt_reg_n_0_[9] }),
- .O(in8[12:9]),
- .S({minusOp_carry__1_i_1_n_0,minusOp_carry__1_i_2_n_0,minusOp_carry__1_i_3_n_0,minusOp_carry__1_i_4_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_1
- (.I0(\packets_cnt_reg_n_0_[12] ),
- .O(minusOp_carry__1_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_2
- (.I0(\packets_cnt_reg_n_0_[11] ),
- .O(minusOp_carry__1_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_3
- (.I0(\packets_cnt_reg_n_0_[10] ),
- .O(minusOp_carry__1_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_4
- (.I0(\packets_cnt_reg_n_0_[9] ),
- .O(minusOp_carry__1_i_4_n_0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 minusOp_carry__2
- (.CI(minusOp_carry__1_n_0),
- .CO({NLW_minusOp_carry__2_CO_UNCONNECTED[3:2],minusOp_carry__2_n_2,minusOp_carry__2_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,\packets_cnt_reg_n_0_[14] ,\packets_cnt_reg_n_0_[13] }),
- .O({NLW_minusOp_carry__2_O_UNCONNECTED[3],in8[15:13]}),
- .S({1'b0,minusOp_carry__2_i_1_n_0,minusOp_carry__2_i_2_n_0,minusOp_carry__2_i_3_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__2_i_1
- (.I0(\packets_cnt_reg_n_0_[15] ),
- .O(minusOp_carry__2_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__2_i_2
- (.I0(\packets_cnt_reg_n_0_[14] ),
- .O(minusOp_carry__2_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__2_i_3
- (.I0(\packets_cnt_reg_n_0_[13] ),
- .O(minusOp_carry__2_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_1
- (.I0(\packets_cnt_reg_n_0_[4] ),
- .O(minusOp_carry_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_2
- (.I0(\packets_cnt_reg_n_0_[3] ),
- .O(minusOp_carry_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_3
- (.I0(\packets_cnt_reg_n_0_[2] ),
- .O(minusOp_carry_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_4
- (.I0(\packets_cnt_reg_n_0_[1] ),
- .O(minusOp_carry_i_4_n_0));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT5 #(
- .INIT(32'h8FCC88CC))
- \packet_data_cnt[0]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[0]),
- .I2(\packet_data_cnt_reg_n_0_[0] ),
- .I3(read_state_reg[0]),
- .I4(\packet_data_cnt[0]_i_2_n_0 ),
- .O(packet_data_cnt[0]));
- LUT6 #(
- .INIT(64'hFFFFFFFEFFFFFFFF))
- \packet_data_cnt[0]_i_2
- (.I0(\packet_data_cnt[0]_i_3_n_0 ),
- .I1(\packet_data_cnt_reg_n_0_[3] ),
- .I2(\packet_data_cnt_reg_n_0_[8] ),
- .I3(\packet_data_cnt_reg_n_0_[2] ),
- .I4(\packet_data_cnt[0]_i_4_n_0 ),
- .I5(\packet_data_cnt[0]_i_5_n_0 ),
- .O(\packet_data_cnt[0]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \packet_data_cnt[0]_i_3
- (.I0(\packet_data_cnt_reg_n_0_[5] ),
- .I1(\packet_data_cnt_reg_n_0_[4] ),
- .I2(\packet_data_cnt_reg_n_0_[11] ),
- .I3(\packet_data_cnt_reg_n_0_[1] ),
- .O(\packet_data_cnt[0]_i_3_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \packet_data_cnt[0]_i_4
- (.I0(\packet_data_cnt_reg_n_0_[12] ),
- .I1(\packet_data_cnt_reg_n_0_[6] ),
- .I2(\packet_data_cnt_reg_n_0_[13] ),
- .I3(\packet_data_cnt_reg_n_0_[10] ),
- .O(\packet_data_cnt[0]_i_4_n_0 ));
- LUT4 #(
- .INIT(16'h0001))
- \packet_data_cnt[0]_i_5
- (.I0(\packet_data_cnt_reg_n_0_[15] ),
- .I1(\packet_data_cnt_reg_n_0_[14] ),
- .I2(\packet_data_cnt_reg_n_0_[9] ),
- .I3(\packet_data_cnt_reg_n_0_[7] ),
- .O(\packet_data_cnt[0]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[10]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[10]),
- .I2(read_state_reg[0]),
- .I3(minusOp[10]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[10]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[11]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[11]),
- .I2(read_state_reg[0]),
- .I3(minusOp[11]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[11]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[12]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[12]),
- .I2(read_state_reg[0]),
- .I3(minusOp[12]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[12]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[13]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[13]),
- .I2(read_state_reg[0]),
- .I3(minusOp[13]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[13]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[14]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[14]),
- .I2(read_state_reg[0]),
- .I3(minusOp[14]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[14]));
- LUT5 #(
- .INIT(32'h00A0000C))
- \packet_data_cnt[15]_i_1
- (.I0(M_AXI_RVALID),
- .I1(run_reg_set_reg_n_0),
- .I2(read_state_reg[0]),
- .I3(read_state_reg[2]),
- .I4(read_state_reg[1]),
- .O(\packet_data_cnt[15]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[15]_i_2
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[15]),
- .I2(read_state_reg[0]),
- .I3(minusOp[15]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[15]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT2 #(
- .INIT(4'hE))
- \packet_data_cnt[15]_i_3
- (.I0(\packet_data_cnt_reg_n_0_[0] ),
- .I1(\packet_data_cnt[0]_i_2_n_0 ),
- .O(\packet_data_cnt[15]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[1]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[1]),
- .I2(read_state_reg[0]),
- .I3(minusOp[1]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[1]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[2]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[2]),
- .I2(read_state_reg[0]),
- .I3(minusOp[2]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[2]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[3]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[3]),
- .I2(read_state_reg[0]),
- .I3(minusOp[3]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[3]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[4]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[4]),
- .I2(read_state_reg[0]),
- .I3(minusOp[4]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[4]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[5]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[5]),
- .I2(read_state_reg[0]),
- .I3(minusOp[5]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[5]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[6]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[6]),
- .I2(read_state_reg[0]),
- .I3(minusOp[6]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[6]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[7]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[7]),
- .I2(read_state_reg[0]),
- .I3(minusOp[7]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[7]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[8]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[8]),
- .I2(read_state_reg[0]),
- .I3(minusOp[8]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[8]));
- LUT5 #(
- .INIT(32'hFC8C8C8C))
- \packet_data_cnt[9]_i_1
- (.I0(\packets_cnt[15]_i_3_n_0 ),
- .I1(packet_size_reg[9]),
- .I2(read_state_reg[0]),
- .I3(minusOp[9]),
- .I4(\packet_data_cnt[15]_i_3_n_0 ),
- .O(packet_data_cnt[9]));
- FDRE \packet_data_cnt_reg[0]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[0]),
- .Q(\packet_data_cnt_reg_n_0_[0] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[10]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[10]),
- .Q(\packet_data_cnt_reg_n_0_[10] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[11]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[11]),
- .Q(\packet_data_cnt_reg_n_0_[11] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[12]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[12]),
- .Q(\packet_data_cnt_reg_n_0_[12] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[13]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[13]),
- .Q(\packet_data_cnt_reg_n_0_[13] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[14]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[14]),
- .Q(\packet_data_cnt_reg_n_0_[14] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[15]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[15]),
- .Q(\packet_data_cnt_reg_n_0_[15] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[1]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[1]),
- .Q(\packet_data_cnt_reg_n_0_[1] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[2]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[2]),
- .Q(\packet_data_cnt_reg_n_0_[2] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[3]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[3]),
- .Q(\packet_data_cnt_reg_n_0_[3] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[4]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[4]),
- .Q(\packet_data_cnt_reg_n_0_[4] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[5]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[5]),
- .Q(\packet_data_cnt_reg_n_0_[5] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[6]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[6]),
- .Q(\packet_data_cnt_reg_n_0_[6] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[7]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[7]),
- .Q(\packet_data_cnt_reg_n_0_[7] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[8]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[8]),
- .Q(\packet_data_cnt_reg_n_0_[8] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_data_cnt_reg[9]
- (.C(CLK),
- .CE(\packet_data_cnt[15]_i_1_n_0 ),
- .D(packet_data_cnt[9]),
- .Q(\packet_data_cnt_reg_n_0_[9] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h3A0AFFFF3A0A0000))
- packet_last_word_i_1
- (.I0(M_AXI_ARREADY),
- .I1(M_AXI_RLAST),
- .I2(read_state_reg[0]),
- .I3(\packet_data_cnt[15]_i_3_n_0 ),
- .I4(packet_last_word3_out),
- .I5(packet_last_word_reg_n_0),
- .O(packet_last_word_i_1_n_0));
- LUT6 #(
- .INIT(64'hAAAA0A0A00080008))
- packet_last_word_i_2
- (.I0(RESETN),
- .I1(packet_last_word_i_3_n_0),
- .I2(\packet_data_cnt[0]_i_2_n_0 ),
- .I3(\packet_data_cnt_reg_n_0_[0] ),
- .I4(M_AXI_RLAST),
- .I5(packet_last_word_i_4_n_0),
- .O(packet_last_word3_out));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h0400))
- packet_last_word_i_3
- (.I0(read_state_reg[0]),
- .I1(M_AXI_ARREADY),
- .I2(read_state_reg[2]),
- .I3(read_state_reg[1]),
- .O(packet_last_word_i_3_n_0));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h4000))
- packet_last_word_i_4
- (.I0(read_state_reg[2]),
- .I1(read_state_reg[1]),
- .I2(read_state_reg[0]),
- .I3(M_AXI_RVALID),
- .O(packet_last_word_i_4_n_0));
- FDRE #(
- .INIT(1'b0))
- packet_last_word_reg
- (.C(CLK),
- .CE(1'b1),
- .D(packet_last_word_i_1_n_0),
- .Q(packet_last_word_reg_n_0),
- .R(1'b0));
- LUT4 #(
- .INIT(16'h0008))
- \packet_number_reg[15]_i_1
- (.I0(S_AXIL_WSTRB[0]),
- .I1(S_AXIL_WSTRB[1]),
- .I2(S_AXIL_AWADDR[3]),
- .I3(\initial_value_reg[31]_i_3_n_0 ),
- .O(packet_number_reg_1));
- FDRE \packet_number_reg_reg[0]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[0]),
- .Q(packet_number_reg[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[10]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[10]),
- .Q(packet_number_reg[10]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[11]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[11]),
- .Q(packet_number_reg[11]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[12]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[12]),
- .Q(packet_number_reg[12]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[13]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[13]),
- .Q(packet_number_reg[13]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[14]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[14]),
- .Q(packet_number_reg[14]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[15]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[15]),
- .Q(packet_number_reg[15]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[1]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[1]),
- .Q(packet_number_reg[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[2]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[2]),
- .Q(packet_number_reg[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[3]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[3]),
- .Q(packet_number_reg[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[4]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[4]),
- .Q(packet_number_reg[4]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[5]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[5]),
- .Q(packet_number_reg[5]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[6]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[6]),
- .Q(packet_number_reg[6]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[7]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[7]),
- .Q(packet_number_reg[7]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[8]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[8]),
- .Q(packet_number_reg[8]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_number_reg_reg[9]
- (.C(CLK),
- .CE(packet_number_reg_1),
- .D(S_AXIL_WDATA[9]),
- .Q(packet_number_reg[9]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h0008))
- \packet_size_reg[15]_i_1
- (.I0(S_AXIL_WSTRB[0]),
- .I1(S_AXIL_WSTRB[1]),
- .I2(S_AXIL_AWADDR[3]),
- .I3(\polynomial_reg[31]_i_2_n_0 ),
- .O(\packet_size_reg[15]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[0]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[0]),
- .Q(packet_size_reg[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[10]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[10]),
- .Q(packet_size_reg[10]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[11]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[11]),
- .Q(packet_size_reg[11]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[12]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[12]),
- .Q(packet_size_reg[12]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[13]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[13]),
- .Q(packet_size_reg[13]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[14]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[14]),
- .Q(packet_size_reg[14]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[15]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[15]),
- .Q(packet_size_reg[15]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[1]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[1]),
- .Q(packet_size_reg[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[2]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[2]),
- .Q(packet_size_reg[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[3]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[3]),
- .Q(packet_size_reg[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[4]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[4]),
- .Q(packet_size_reg[4]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[5]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[5]),
- .Q(packet_size_reg[5]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[6]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[6]),
- .Q(packet_size_reg[6]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[7]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[7]),
- .Q(packet_size_reg[7]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[8]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[8]),
- .Q(packet_size_reg[8]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packet_size_reg_reg[9]
- (.C(CLK),
- .CE(\packet_size_reg[15]_i_1_n_0 ),
- .D(S_AXIL_WDATA[9]),
- .Q(packet_size_reg[9]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT3 #(
- .INIT(8'h3A))
- \packets_cnt[0]_i_1
- (.I0(packet_number_reg[0]),
- .I1(\packets_cnt_reg_n_0_[0] ),
- .I2(read_state_reg[0]),
- .O(packets_cnt[0]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[10]_i_1
- (.I0(in8[10]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[10]),
- .O(packets_cnt[10]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[11]_i_1
- (.I0(in8[11]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[11]),
- .O(packets_cnt[11]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[12]_i_1
- (.I0(in8[12]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[12]),
- .O(packets_cnt[12]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[13]_i_1
- (.I0(in8[13]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[13]),
- .O(packets_cnt[13]));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[14]_i_1
- (.I0(in8[14]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[14]),
- .O(packets_cnt[14]));
- LUT6 #(
- .INIT(64'h0080000F00800000))
- \packets_cnt[15]_i_1
- (.I0(M_AXI_RVALID),
- .I1(\packets_cnt[15]_i_3_n_0 ),
- .I2(read_state_reg[1]),
- .I3(read_state_reg[2]),
- .I4(read_state_reg[0]),
- .I5(run_reg_set_reg_n_0),
- .O(\packets_cnt[15]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[15]_i_2
- (.I0(in8[15]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[15]),
- .O(packets_cnt[15]));
- LUT2 #(
- .INIT(4'h2))
- \packets_cnt[15]_i_3
- (.I0(\packets_cnt[15]_i_4_n_0 ),
- .I1(\packet_data_cnt[15]_i_3_n_0 ),
- .O(\packets_cnt[15]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFEFFFFFFFF))
- \packets_cnt[15]_i_4
- (.I0(\packets_cnt[15]_i_5_n_0 ),
- .I1(\packets_cnt_reg_n_0_[7] ),
- .I2(\packets_cnt_reg_n_0_[0] ),
- .I3(\packets_cnt_reg_n_0_[6] ),
- .I4(\packets_cnt_reg_n_0_[2] ),
- .I5(\packets_cnt[15]_i_6_n_0 ),
- .O(\packets_cnt[15]_i_4_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \packets_cnt[15]_i_5
- (.I0(\packets_cnt_reg_n_0_[8] ),
- .I1(\packets_cnt_reg_n_0_[9] ),
- .I2(\packets_cnt_reg_n_0_[15] ),
- .I3(\packets_cnt_reg_n_0_[13] ),
- .O(\packets_cnt[15]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'h00000001))
- \packets_cnt[15]_i_6
- (.I0(\packets_cnt_reg_n_0_[1] ),
- .I1(\packets_cnt_reg_n_0_[5] ),
- .I2(\packets_cnt_reg_n_0_[4] ),
- .I3(\packets_cnt_reg_n_0_[11] ),
- .I4(\packets_cnt[15]_i_7_n_0 ),
- .O(\packets_cnt[15]_i_6_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \packets_cnt[15]_i_7
- (.I0(\packets_cnt_reg_n_0_[14] ),
- .I1(\packets_cnt_reg_n_0_[12] ),
- .I2(\packets_cnt_reg_n_0_[10] ),
- .I3(\packets_cnt_reg_n_0_[3] ),
- .O(\packets_cnt[15]_i_7_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[1]_i_1
- (.I0(in8[1]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[1]),
- .O(packets_cnt[1]));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[2]_i_1
- (.I0(in8[2]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[2]),
- .O(packets_cnt[2]));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[3]_i_1
- (.I0(in8[3]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[3]),
- .O(packets_cnt[3]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[4]_i_1
- (.I0(in8[4]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[4]),
- .O(packets_cnt[4]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[5]_i_1
- (.I0(in8[5]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[5]),
- .O(packets_cnt[5]));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[6]_i_1
- (.I0(in8[6]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[6]),
- .O(packets_cnt[6]));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[7]_i_1
- (.I0(in8[7]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[7]),
- .O(packets_cnt[7]));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[8]_i_1
- (.I0(in8[8]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[8]),
- .O(packets_cnt[8]));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT3 #(
- .INIT(8'hB8))
- \packets_cnt[9]_i_1
- (.I0(in8[9]),
- .I1(read_state_reg[0]),
- .I2(packet_number_reg[9]),
- .O(packets_cnt[9]));
- FDRE \packets_cnt_reg[0]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[0]),
- .Q(\packets_cnt_reg_n_0_[0] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[10]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[10]),
- .Q(\packets_cnt_reg_n_0_[10] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[11]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[11]),
- .Q(\packets_cnt_reg_n_0_[11] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[12]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[12]),
- .Q(\packets_cnt_reg_n_0_[12] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[13]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[13]),
- .Q(\packets_cnt_reg_n_0_[13] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[14]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[14]),
- .Q(\packets_cnt_reg_n_0_[14] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[15]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[15]),
- .Q(\packets_cnt_reg_n_0_[15] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[1]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[1]),
- .Q(\packets_cnt_reg_n_0_[1] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[2]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[2]),
- .Q(\packets_cnt_reg_n_0_[2] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[3]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[3]),
- .Q(\packets_cnt_reg_n_0_[3] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[4]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[4]),
- .Q(\packets_cnt_reg_n_0_[4] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[5]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[5]),
- .Q(\packets_cnt_reg_n_0_[5] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[6]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[6]),
- .Q(\packets_cnt_reg_n_0_[6] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[7]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[7]),
- .Q(\packets_cnt_reg_n_0_[7] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[8]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[8]),
- .Q(\packets_cnt_reg_n_0_[8] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \packets_cnt_reg[9]
- (.C(CLK),
- .CE(\packets_cnt[15]_i_1_n_0 ),
- .D(packets_cnt[9]),
- .Q(\packets_cnt_reg_n_0_[9] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 plusOp__28_carry
- (.CI(1'b0),
- .CO({plusOp__28_carry_n_0,plusOp__28_carry_n_1,plusOp__28_carry_n_2,plusOp__28_carry_n_3}),
- .CYINIT(packet_number_reg[0]),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(B[4:1]),
- .S(packet_number_reg[4:1]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 plusOp__28_carry__0
- (.CI(plusOp__28_carry_n_0),
- .CO({plusOp__28_carry__0_n_0,plusOp__28_carry__0_n_1,plusOp__28_carry__0_n_2,plusOp__28_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(B[8:5]),
- .S(packet_number_reg[8:5]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 plusOp__28_carry__1
- (.CI(plusOp__28_carry__0_n_0),
- .CO({plusOp__28_carry__1_n_0,plusOp__28_carry__1_n_1,plusOp__28_carry__1_n_2,plusOp__28_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(B[12:9]),
- .S(packet_number_reg[12:9]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 plusOp__28_carry__2
- (.CI(plusOp__28_carry__1_n_0),
- .CO({NLW_plusOp__28_carry__2_CO_UNCONNECTED[3:2],plusOp__28_carry__2_n_2,plusOp__28_carry__2_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({NLW_plusOp__28_carry__2_O_UNCONNECTED[3],B[15:13]}),
- .S({1'b0,packet_number_reg[15:13]}));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 plusOp_carry
- (.CI(1'b0),
- .CO({plusOp_carry_n_0,plusOp_carry_n_1,plusOp_carry_n_2,plusOp_carry_n_3}),
- .CYINIT(packet_size_reg[0]),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(A[4:1]),
- .S(packet_size_reg[4:1]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 plusOp_carry__0
- (.CI(plusOp_carry_n_0),
- .CO({plusOp_carry__0_n_0,plusOp_carry__0_n_1,plusOp_carry__0_n_2,plusOp_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(A[8:5]),
- .S(packet_size_reg[8:5]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 plusOp_carry__1
- (.CI(plusOp_carry__0_n_0),
- .CO({plusOp_carry__1_n_0,plusOp_carry__1_n_1,plusOp_carry__1_n_2,plusOp_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(A[12:9]),
- .S(packet_size_reg[12:9]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 plusOp_carry__2
- (.CI(plusOp_carry__1_n_0),
- .CO({NLW_plusOp_carry__2_CO_UNCONNECTED[3:2],plusOp_carry__2_n_2,plusOp_carry__2_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({NLW_plusOp_carry__2_O_UNCONNECTED[3],A[15:13]}),
- .S({1'b0,packet_size_reg[15:13]}));
- LUT6 #(
- .INIT(64'h0000000080000000))
- \polynomial_reg[31]_i_1
- (.I0(S_AXIL_WSTRB[1]),
- .I1(S_AXIL_WSTRB[0]),
- .I2(S_AXIL_WSTRB[2]),
- .I3(S_AXIL_WSTRB[3]),
- .I4(S_AXIL_AWADDR[3]),
- .I5(\polynomial_reg[31]_i_2_n_0 ),
- .O(polynomial_reg));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFEFFF))
- \polynomial_reg[31]_i_2
- (.I0(\polynomial_reg[31]_i_3_n_0 ),
- .I1(S_AXIL_AWADDR[2]),
- .I2(S_AXIL_AWVALID),
- .I3(S_AXIL_WVALID),
- .I4(S_AXIL_AWADDR[1]),
- .I5(S_AXIL_AWADDR[0]),
- .O(\polynomial_reg[31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT4 #(
- .INIT(16'hFEFF))
- \polynomial_reg[31]_i_3
- (.I0(S_AXIL_AWADDR[6]),
- .I1(S_AXIL_AWADDR[7]),
- .I2(S_AXIL_AWADDR[5]),
- .I3(S_AXIL_AWADDR[4]),
- .O(\polynomial_reg[31]_i_3_n_0 ));
- FDSE \polynomial_reg_reg[0]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[0]),
- .Q(polynomial[0]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[10]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[10]),
- .Q(polynomial[10]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[11]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[11]),
- .Q(polynomial[11]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[12]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[12]),
- .Q(polynomial[12]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[13]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[13]),
- .Q(polynomial[13]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[14]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[14]),
- .Q(polynomial[14]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[15]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[15]),
- .Q(polynomial[15]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[16]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[16]),
- .Q(polynomial[16]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[17]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[17]),
- .Q(polynomial[17]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[18]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[18]),
- .Q(polynomial[18]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[19]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[19]),
- .Q(polynomial[19]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[1]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[1]),
- .Q(polynomial[1]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[20]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[20]),
- .Q(polynomial[20]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[21]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[21]),
- .Q(polynomial[21]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[22]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[22]),
- .Q(polynomial[22]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[23]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[23]),
- .Q(polynomial[23]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[24]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[24]),
- .Q(polynomial[24]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[25]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[25]),
- .Q(polynomial[25]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[26]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[26]),
- .Q(polynomial[26]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[27]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[27]),
- .Q(polynomial[27]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[28]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[28]),
- .Q(polynomial[28]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[29]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[29]),
- .Q(polynomial[29]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[2]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[2]),
- .Q(polynomial[2]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[30]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[30]),
- .Q(polynomial[30]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[31]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[31]),
- .Q(polynomial[31]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[3]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[3]),
- .Q(polynomial[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[4]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[4]),
- .Q(polynomial[4]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[5]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[5]),
- .Q(polynomial[5]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[6]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[6]),
- .Q(polynomial[6]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[7]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[7]),
- .Q(polynomial[7]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDSE \polynomial_reg_reg[8]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[8]),
- .Q(polynomial[8]),
- .S(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \polynomial_reg_reg[9]
- (.C(CLK),
- .CE(polynomial_reg),
- .D(S_AXIL_WDATA[9]),
- .Q(polynomial[9]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 read_addr_cnt0_carry
- (.CI(1'b0),
- .CO({read_addr_cnt0_carry_n_0,read_addr_cnt0_carry_n_1,read_addr_cnt0_carry_n_2,read_addr_cnt0_carry_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,\read_addr_cnt_reg_n_0_[4] ,1'b0}),
- .O({read_addr_cnt0_carry_n_4,read_addr_cnt0_carry_n_5,read_addr_cnt0_carry_n_6,read_addr_cnt0_carry_n_7}),
- .S({\read_addr_cnt_reg_n_0_[6] ,\read_addr_cnt_reg_n_0_[5] ,read_addr_cnt0_carry_i_1_n_0,\read_addr_cnt_reg_n_0_[3] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 read_addr_cnt0_carry__0
- (.CI(read_addr_cnt0_carry_n_0),
- .CO({read_addr_cnt0_carry__0_n_0,read_addr_cnt0_carry__0_n_1,read_addr_cnt0_carry__0_n_2,read_addr_cnt0_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({read_addr_cnt0_carry__0_n_4,read_addr_cnt0_carry__0_n_5,read_addr_cnt0_carry__0_n_6,read_addr_cnt0_carry__0_n_7}),
- .S({\read_addr_cnt_reg_n_0_[10] ,\read_addr_cnt_reg_n_0_[9] ,\read_addr_cnt_reg_n_0_[8] ,\read_addr_cnt_reg_n_0_[7] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 read_addr_cnt0_carry__1
- (.CI(read_addr_cnt0_carry__0_n_0),
- .CO({read_addr_cnt0_carry__1_n_0,read_addr_cnt0_carry__1_n_1,read_addr_cnt0_carry__1_n_2,read_addr_cnt0_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({read_addr_cnt0_carry__1_n_4,read_addr_cnt0_carry__1_n_5,read_addr_cnt0_carry__1_n_6,read_addr_cnt0_carry__1_n_7}),
- .S({\read_addr_cnt_reg_n_0_[14] ,\read_addr_cnt_reg_n_0_[13] ,\read_addr_cnt_reg_n_0_[12] ,\read_addr_cnt_reg_n_0_[11] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 read_addr_cnt0_carry__2
- (.CI(read_addr_cnt0_carry__1_n_0),
- .CO({read_addr_cnt0_carry__2_n_0,read_addr_cnt0_carry__2_n_1,read_addr_cnt0_carry__2_n_2,read_addr_cnt0_carry__2_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({read_addr_cnt0_carry__2_n_4,read_addr_cnt0_carry__2_n_5,read_addr_cnt0_carry__2_n_6,read_addr_cnt0_carry__2_n_7}),
- .S({\read_addr_cnt_reg_n_0_[18] ,\read_addr_cnt_reg_n_0_[17] ,\read_addr_cnt_reg_n_0_[16] ,\read_addr_cnt_reg_n_0_[15] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 read_addr_cnt0_carry__3
- (.CI(read_addr_cnt0_carry__2_n_0),
- .CO({read_addr_cnt0_carry__3_n_0,read_addr_cnt0_carry__3_n_1,read_addr_cnt0_carry__3_n_2,read_addr_cnt0_carry__3_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({read_addr_cnt0_carry__3_n_4,read_addr_cnt0_carry__3_n_5,read_addr_cnt0_carry__3_n_6,read_addr_cnt0_carry__3_n_7}),
- .S({\read_addr_cnt_reg_n_0_[22] ,\read_addr_cnt_reg_n_0_[21] ,\read_addr_cnt_reg_n_0_[20] ,\read_addr_cnt_reg_n_0_[19] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 read_addr_cnt0_carry__4
- (.CI(read_addr_cnt0_carry__3_n_0),
- .CO({read_addr_cnt0_carry__4_n_0,read_addr_cnt0_carry__4_n_1,read_addr_cnt0_carry__4_n_2,read_addr_cnt0_carry__4_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({read_addr_cnt0_carry__4_n_4,read_addr_cnt0_carry__4_n_5,read_addr_cnt0_carry__4_n_6,read_addr_cnt0_carry__4_n_7}),
- .S({\read_addr_cnt_reg_n_0_[26] ,\read_addr_cnt_reg_n_0_[25] ,\read_addr_cnt_reg_n_0_[24] ,\read_addr_cnt_reg_n_0_[23] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 read_addr_cnt0_carry__5
- (.CI(read_addr_cnt0_carry__4_n_0),
- .CO({read_addr_cnt0_carry__5_n_0,read_addr_cnt0_carry__5_n_1,read_addr_cnt0_carry__5_n_2,read_addr_cnt0_carry__5_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({read_addr_cnt0_carry__5_n_4,read_addr_cnt0_carry__5_n_5,read_addr_cnt0_carry__5_n_6,read_addr_cnt0_carry__5_n_7}),
- .S({\read_addr_cnt_reg_n_0_[30] ,\read_addr_cnt_reg_n_0_[29] ,\read_addr_cnt_reg_n_0_[28] ,\read_addr_cnt_reg_n_0_[27] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 read_addr_cnt0_carry__6
- (.CI(read_addr_cnt0_carry__5_n_0),
- .CO(NLW_read_addr_cnt0_carry__6_CO_UNCONNECTED[3:0]),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({NLW_read_addr_cnt0_carry__6_O_UNCONNECTED[3:1],read_addr_cnt0_carry__6_n_7}),
- .S({1'b0,1'b0,1'b0,\read_addr_cnt_reg_n_0_[31] }));
- LUT1 #(
- .INIT(2'h1))
- read_addr_cnt0_carry_i_1
- (.I0(\read_addr_cnt_reg_n_0_[4] ),
- .O(read_addr_cnt0_carry_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair46" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[0]_i_1
- (.I0(\read_addr_cnt_reg_n_0_[0] ),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[0]),
- .O(read_addr_cnt[0]));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[10]_i_1
- (.I0(read_addr_cnt0_carry__0_n_4),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[10]),
- .O(read_addr_cnt[10]));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[11]_i_1
- (.I0(read_addr_cnt0_carry__1_n_7),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[11]),
- .O(read_addr_cnt[11]));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[12]_i_1
- (.I0(read_addr_cnt0_carry__1_n_6),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[12]),
- .O(read_addr_cnt[12]));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[13]_i_1
- (.I0(read_addr_cnt0_carry__1_n_5),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[13]),
- .O(read_addr_cnt[13]));
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[14]_i_1
- (.I0(read_addr_cnt0_carry__1_n_4),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[14]),
- .O(read_addr_cnt[14]));
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[15]_i_1
- (.I0(read_addr_cnt0_carry__2_n_7),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[15]),
- .O(read_addr_cnt[15]));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[16]_i_1
- (.I0(read_addr_cnt0_carry__2_n_6),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[16]),
- .O(read_addr_cnt[16]));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[17]_i_1
- (.I0(read_addr_cnt0_carry__2_n_5),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[17]),
- .O(read_addr_cnt[17]));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[18]_i_1
- (.I0(read_addr_cnt0_carry__2_n_4),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[18]),
- .O(read_addr_cnt[18]));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[19]_i_1
- (.I0(read_addr_cnt0_carry__3_n_7),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[19]),
- .O(read_addr_cnt[19]));
- (* SOFT_HLUTNM = "soft_lutpair46" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[1]_i_1
- (.I0(\read_addr_cnt_reg_n_0_[1] ),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[1]),
- .O(read_addr_cnt[1]));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[20]_i_1
- (.I0(read_addr_cnt0_carry__3_n_6),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[20]),
- .O(read_addr_cnt[20]));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[21]_i_1
- (.I0(read_addr_cnt0_carry__3_n_5),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[21]),
- .O(read_addr_cnt[21]));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[22]_i_1
- (.I0(read_addr_cnt0_carry__3_n_4),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[22]),
- .O(read_addr_cnt[22]));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[23]_i_1
- (.I0(read_addr_cnt0_carry__4_n_7),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[23]),
- .O(read_addr_cnt[23]));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[24]_i_1
- (.I0(read_addr_cnt0_carry__4_n_6),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[24]),
- .O(read_addr_cnt[24]));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[25]_i_1
- (.I0(read_addr_cnt0_carry__4_n_5),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[25]),
- .O(read_addr_cnt[25]));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[26]_i_1
- (.I0(read_addr_cnt0_carry__4_n_4),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[26]),
- .O(read_addr_cnt[26]));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[27]_i_1
- (.I0(read_addr_cnt0_carry__5_n_7),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[27]),
- .O(read_addr_cnt[27]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[28]_i_1
- (.I0(read_addr_cnt0_carry__5_n_6),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[28]),
- .O(read_addr_cnt[28]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[29]_i_1
- (.I0(read_addr_cnt0_carry__5_n_5),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[29]),
- .O(read_addr_cnt[29]));
- (* SOFT_HLUTNM = "soft_lutpair45" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[2]_i_1
- (.I0(\read_addr_cnt_reg_n_0_[2] ),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[2]),
- .O(read_addr_cnt[2]));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[30]_i_1
- (.I0(read_addr_cnt0_carry__5_n_4),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[30]),
- .O(read_addr_cnt[30]));
- LUT5 #(
- .INIT(32'hBBBBBBBA))
- \read_addr_cnt[31]_i_1
- (.I0(\read_addr_cnt[31]_i_3_n_0 ),
- .I1(\read_addr_cnt[31]_i_4_n_0 ),
- .I2(\M_AXI_ARLEN[3]_i_4_n_0 ),
- .I3(\M_AXI_ARLEN[3]_i_3_n_0 ),
- .I4(\M_AXI_ARLEN[3]_i_2_n_0 ),
- .O(\read_addr_cnt[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[31]_i_2
- (.I0(read_addr_cnt0_carry__6_n_7),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[31]),
- .O(read_addr_cnt[31]));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT4 #(
- .INIT(16'h0100))
- \read_addr_cnt[31]_i_3
- (.I0(read_state_reg[1]),
- .I1(read_state_reg[2]),
- .I2(read_state_reg[0]),
- .I3(run_reg_set_reg_n_0),
- .O(\read_addr_cnt[31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT3 #(
- .INIT(8'hEF))
- \read_addr_cnt[31]_i_4
- (.I0(read_state_reg[1]),
- .I1(read_state_reg[2]),
- .I2(\M_AXI_ARADDR[31]_i_2_n_0 ),
- .O(\read_addr_cnt[31]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair45" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[3]_i_1
- (.I0(read_addr_cnt0_carry_n_7),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[3]),
- .O(read_addr_cnt[3]));
- (* SOFT_HLUTNM = "soft_lutpair44" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[4]_i_1
- (.I0(read_addr_cnt0_carry_n_6),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[4]),
- .O(read_addr_cnt[4]));
- (* SOFT_HLUTNM = "soft_lutpair44" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[5]_i_1
- (.I0(read_addr_cnt0_carry_n_5),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[5]),
- .O(read_addr_cnt[5]));
- (* SOFT_HLUTNM = "soft_lutpair43" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[6]_i_1
- (.I0(read_addr_cnt0_carry_n_4),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[6]),
- .O(read_addr_cnt[6]));
- (* SOFT_HLUTNM = "soft_lutpair43" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[7]_i_1
- (.I0(read_addr_cnt0_carry__0_n_7),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[7]),
- .O(read_addr_cnt[7]));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[8]_i_1
- (.I0(read_addr_cnt0_carry__0_n_6),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[8]),
- .O(read_addr_cnt[8]));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT3 #(
- .INIT(8'hB8))
- \read_addr_cnt[9]_i_1
- (.I0(read_addr_cnt0_carry__0_n_5),
- .I1(read_state_reg[0]),
- .I2(read_address_reg[9]),
- .O(read_addr_cnt[9]));
- FDRE \read_addr_cnt_reg[0]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[0]),
- .Q(\read_addr_cnt_reg_n_0_[0] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[10]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[10]),
- .Q(\read_addr_cnt_reg_n_0_[10] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[11]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[11]),
- .Q(\read_addr_cnt_reg_n_0_[11] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[12]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[12]),
- .Q(\read_addr_cnt_reg_n_0_[12] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[13]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[13]),
- .Q(\read_addr_cnt_reg_n_0_[13] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[14]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[14]),
- .Q(\read_addr_cnt_reg_n_0_[14] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[15]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[15]),
- .Q(\read_addr_cnt_reg_n_0_[15] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[16]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[16]),
- .Q(\read_addr_cnt_reg_n_0_[16] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[17]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[17]),
- .Q(\read_addr_cnt_reg_n_0_[17] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[18]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[18]),
- .Q(\read_addr_cnt_reg_n_0_[18] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[19]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[19]),
- .Q(\read_addr_cnt_reg_n_0_[19] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[1]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[1]),
- .Q(\read_addr_cnt_reg_n_0_[1] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[20]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[20]),
- .Q(\read_addr_cnt_reg_n_0_[20] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[21]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[21]),
- .Q(\read_addr_cnt_reg_n_0_[21] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[22]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[22]),
- .Q(\read_addr_cnt_reg_n_0_[22] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[23]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[23]),
- .Q(\read_addr_cnt_reg_n_0_[23] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[24]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[24]),
- .Q(\read_addr_cnt_reg_n_0_[24] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[25]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[25]),
- .Q(\read_addr_cnt_reg_n_0_[25] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[26]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[26]),
- .Q(\read_addr_cnt_reg_n_0_[26] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[27]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[27]),
- .Q(\read_addr_cnt_reg_n_0_[27] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[28]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[28]),
- .Q(\read_addr_cnt_reg_n_0_[28] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[29]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[29]),
- .Q(\read_addr_cnt_reg_n_0_[29] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[2]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[2]),
- .Q(\read_addr_cnt_reg_n_0_[2] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[30]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[30]),
- .Q(\read_addr_cnt_reg_n_0_[30] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[31]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[31]),
- .Q(\read_addr_cnt_reg_n_0_[31] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[3]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[3]),
- .Q(\read_addr_cnt_reg_n_0_[3] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[4]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[4]),
- .Q(\read_addr_cnt_reg_n_0_[4] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[5]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[5]),
- .Q(\read_addr_cnt_reg_n_0_[5] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[6]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[6]),
- .Q(\read_addr_cnt_reg_n_0_[6] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[7]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[7]),
- .Q(\read_addr_cnt_reg_n_0_[7] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[8]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[8]),
- .Q(\read_addr_cnt_reg_n_0_[8] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_addr_cnt_reg[9]
- (.C(CLK),
- .CE(\read_addr_cnt[31]_i_1_n_0 ),
- .D(read_addr_cnt[9]),
- .Q(\read_addr_cnt_reg_n_0_[9] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000800000))
- \read_address_reg[31]_i_1
- (.I0(\finalXOR_reg[31]_i_2_n_0 ),
- .I1(S_AXIL_WVALID),
- .I2(S_AXIL_AWVALID),
- .I3(S_AXIL_AWADDR[2]),
- .I4(S_AXIL_AWADDR[3]),
- .I5(\read_address_reg[31]_i_2_n_0 ),
- .O(read_address_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \read_address_reg[31]_i_2
- (.I0(S_AXIL_AWADDR[4]),
- .I1(S_AXIL_AWADDR[6]),
- .I2(S_AXIL_AWADDR[7]),
- .I3(S_AXIL_AWADDR[5]),
- .O(\read_address_reg[31]_i_2_n_0 ));
- FDRE \read_address_reg_reg[0]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[0]),
- .Q(read_address_reg[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[10]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[10]),
- .Q(read_address_reg[10]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[11]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[11]),
- .Q(read_address_reg[11]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[12]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[12]),
- .Q(read_address_reg[12]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[13]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[13]),
- .Q(read_address_reg[13]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[14]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[14]),
- .Q(read_address_reg[14]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[15]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[15]),
- .Q(read_address_reg[15]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[16]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[16]),
- .Q(read_address_reg[16]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[17]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[17]),
- .Q(read_address_reg[17]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[18]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[18]),
- .Q(read_address_reg[18]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[19]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[19]),
- .Q(read_address_reg[19]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[1]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[1]),
- .Q(read_address_reg[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[20]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[20]),
- .Q(read_address_reg[20]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[21]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[21]),
- .Q(read_address_reg[21]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[22]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[22]),
- .Q(read_address_reg[22]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[23]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[23]),
- .Q(read_address_reg[23]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[24]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[24]),
- .Q(read_address_reg[24]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[25]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[25]),
- .Q(read_address_reg[25]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[26]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[26]),
- .Q(read_address_reg[26]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[27]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[27]),
- .Q(read_address_reg[27]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[28]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[28]),
- .Q(read_address_reg[28]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[29]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[29]),
- .Q(read_address_reg[29]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[2]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[2]),
- .Q(read_address_reg[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[30]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[30]),
- .Q(read_address_reg[30]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[31]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[31]),
- .Q(read_address_reg[31]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[3]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[3]),
- .Q(read_address_reg[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[4]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[4]),
- .Q(read_address_reg[4]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[5]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[5]),
- .Q(read_address_reg[5]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[6]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[6]),
- .Q(read_address_reg[6]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[7]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[7]),
- .Q(read_address_reg[7]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[8]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[8]),
- .Q(read_address_reg[8]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \read_address_reg_reg[9]
- (.C(CLK),
- .CE(read_address_reg_0),
- .D(S_AXIL_WDATA[9]),
- .Q(read_address_reg[9]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT5 #(
- .INIT(32'h08FF0A00))
- \read_state[0]_i_1
- (.I0(\read_state[2]_i_2_n_0 ),
- .I1(read_state_reg[1]),
- .I2(read_state_reg[2]),
- .I3(\read_state[2]_i_3_n_0 ),
- .I4(read_state_reg[0]),
- .O(\read_state[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT3 #(
- .INIT(8'h78))
- \read_state[1]_i_1
- (.I0(read_state_reg[0]),
- .I1(\read_state[2]_i_3_n_0 ),
- .I2(read_state_reg[1]),
- .O(\read_state[1]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h08FF0800))
- \read_state[2]_i_1
- (.I0(p_5_in[1]),
- .I1(read_state_reg[1]),
- .I2(\read_state[2]_i_2_n_0 ),
- .I3(\read_state[2]_i_3_n_0 ),
- .I4(read_state_reg[2]),
- .O(\read_state[2]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \read_state[2]_i_10
- (.I0(\data_cnt_reg[23]__0_n_0 ),
- .I1(\data_cnt_reg[21]__0_n_0 ),
- .I2(\data_cnt_reg[24]__0_n_0 ),
- .I3(\data_cnt_reg[9]__0_n_0 ),
- .O(\read_state[2]_i_10_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \read_state[2]_i_11
- (.I0(\data_cnt_reg[6]__0_n_0 ),
- .I1(\data_cnt_reg[12]__0_n_0 ),
- .I2(\data_cnt_reg[10]__0_n_0 ),
- .I3(\data_cnt_reg[13]__0_n_0 ),
- .I4(\read_state[2]_i_13_n_0 ),
- .O(\read_state[2]_i_11_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \read_state[2]_i_12
- (.I0(\data_cnt_reg[17]__0_n_0 ),
- .I1(\data_cnt_reg[11]__0_n_0 ),
- .I2(\data_cnt_reg[31]__0_n_0 ),
- .I3(\data_cnt_reg[15]__0_n_0 ),
- .O(\read_state[2]_i_12_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \read_state[2]_i_13
- (.I0(\data_cnt_reg[19]__0_n_0 ),
- .I1(\data_cnt_reg[5]__0_n_0 ),
- .I2(\data_cnt_reg[25]__0_n_0 ),
- .I3(\data_cnt_reg[3]__0_n_0 ),
- .O(\read_state[2]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \read_state[2]_i_2
- (.I0(\read_state[2]_i_4_n_0 ),
- .I1(\read_state[2]_i_5_n_0 ),
- .I2(\read_state[2]_i_6_n_0 ),
- .I3(\data_cnt_reg[28]__0_n_0 ),
- .I4(\data_cnt_reg[30]__0_n_0 ),
- .I5(\data_cnt_reg[22]__0_n_0 ),
- .O(\read_state[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h4F4F4F4F4F4F4F44))
- \read_state[2]_i_3
- (.I0(\read_state[2]_i_7_n_0 ),
- .I1(interrupt_reset_reg_n_0),
- .I2(\read_state[2]_i_8_n_0 ),
- .I3(\M_AXI_ARADDR[31]_i_2_n_0 ),
- .I4(\read_state[2]_i_9_n_0 ),
- .I5(read_state_reg[1]),
- .O(\read_state[2]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \read_state[2]_i_4
- (.I0(\read_state[2]_i_10_n_0 ),
- .I1(\data_cnt_reg[7]__0_n_0 ),
- .I2(\data_cnt_reg[0]__0_n_0 ),
- .I3(\data_cnt_reg[8]__0_n_0 ),
- .I4(\data_cnt_reg[2]__0_n_0 ),
- .I5(\read_state[2]_i_11_n_0 ),
- .O(\read_state[2]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \read_state[2]_i_5
- (.I0(read_state_reg[0]),
- .I1(\data_cnt_reg[29]__0_n_0 ),
- .I2(\data_cnt_reg[16]__0_n_0 ),
- .I3(\data_cnt_reg[26]__0_n_0 ),
- .I4(\data_cnt_reg[14]__0_n_0 ),
- .I5(\data_cnt_reg[27]__0_n_0 ),
- .O(\read_state[2]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \read_state[2]_i_6
- (.I0(\data_cnt_reg[1]__0_n_0 ),
- .I1(\data_cnt_reg[18]__0_n_0 ),
- .I2(\data_cnt_reg[4]__0_n_0 ),
- .I3(\data_cnt_reg[20]__0_n_0 ),
- .I4(\read_state[2]_i_12_n_0 ),
- .O(\read_state[2]_i_6_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT3 #(
- .INIT(8'hFB))
- \read_state[2]_i_7
- (.I0(read_state_reg[0]),
- .I1(read_state_reg[2]),
- .I2(read_state_reg[1]),
- .O(\read_state[2]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'hABAAEFAAEFAAEFAA))
- \read_state[2]_i_8
- (.I0(read_state_reg[2]),
- .I1(read_state_reg[0]),
- .I2(M_AXI_ARREADY),
- .I3(read_state_reg[1]),
- .I4(M_AXI_RVALID),
- .I5(M_AXI_RLAST),
- .O(\read_state[2]_i_8_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT2 #(
- .INIT(4'h2))
- \read_state[2]_i_9
- (.I0(run_reg_set_reg_n_0),
- .I1(read_state_reg[0]),
- .O(\read_state[2]_i_9_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \read_state_reg[0]
- (.C(CLK),
- .CE(1'b1),
- .D(\read_state[0]_i_1_n_0 ),
- .Q(read_state_reg[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \read_state_reg[1]
- (.C(CLK),
- .CE(1'b1),
- .D(\read_state[1]_i_1_n_0 ),
- .Q(read_state_reg[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \read_state_reg[2]
- (.C(CLK),
- .CE(1'b1),
- .D(\read_state[2]_i_1_n_0 ),
- .Q(read_state_reg[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h2FFF2F2F20002020))
- run_reg_clear_i_1
- (.I0(M_AXI_WREADY),
- .I1(write_state_reg[2]),
- .I2(RESETN),
- .I3(INTERRUPT_INST_0_i_1_n_0),
- .I4(run_reg_clear_i_2_n_0),
- .I5(run_reg_clear_reg_n_0),
- .O(run_reg_clear_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFEFFFF))
- run_reg_clear_i_2
- (.I0(run_reg_clear_i_3_n_0),
- .I1(\write_state[2]_i_6_n_0 ),
- .I2(\write_state[2]_i_5_n_0 ),
- .I3(write_state_reg[2]),
- .I4(write_state_reg[1]),
- .I5(\write_state[2]_i_4_n_0 ),
- .O(run_reg_clear_i_2_n_0));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT5 #(
- .INIT(32'hFEFFFFFF))
- run_reg_clear_i_3
- (.I0(\burst_data_cnt_reg_n_0_[4] ),
- .I1(\burst_data_cnt_reg_n_0_[3] ),
- .I2(\burst_data_cnt[4]_i_3_n_0 ),
- .I3(write_state_reg[0]),
- .I4(M_AXI_WREADY),
- .O(run_reg_clear_i_3_n_0));
- FDRE run_reg_clear_reg
- (.C(CLK),
- .CE(1'b1),
- .D(run_reg_clear_i_1_n_0),
- .Q(run_reg_clear_reg_n_0),
- .R(1'b0));
- LUT5 #(
- .INIT(32'h0000DC00))
- run_reg_i_1
- (.I0(run_reg_clear_reg_n_0),
- .I1(run_reg_set_reg_n_0),
- .I2(p_5_in[0]),
- .I3(RESETN),
- .I4(INTERRUPT),
- .O(run_reg_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- run_reg_reg
- (.C(CLK),
- .CE(1'b1),
- .D(run_reg_i_1_n_0),
- .Q(p_5_in[0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT4 #(
- .INIT(16'h2F20))
- run_reg_set_i_1
- (.I0(S_AXIL_WDATA[0]),
- .I1(run_reg_set_i_2_n_0),
- .I2(RESETN),
- .I3(run_reg_set_reg_n_0),
- .O(run_reg_set_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFBFFFFFFFFFFFF))
- run_reg_set_i_2
- (.I0(S_AXIL_AWADDR[2]),
- .I1(S_AXIL_WVALID_0),
- .I2(S_AXIL_AWADDR[0]),
- .I3(S_AXIL_AWADDR[1]),
- .I4(S_AXIL_WSTRB[0]),
- .I5(interrupt_reset_i_2_n_0),
- .O(run_reg_set_i_2_n_0));
- FDRE run_reg_set_reg
- (.C(CLK),
- .CE(1'b1),
- .D(run_reg_set_i_1_n_0),
- .Q(run_reg_set_reg_n_0),
- .R(1'b0));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 write_addr0_carry
- (.CI(1'b0),
- .CO({write_addr0_carry_n_0,write_addr0_carry_n_1,write_addr0_carry_n_2,write_addr0_carry_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,\write_addr_reg_n_0_[4] ,1'b0}),
- .O(in15[6:3]),
- .S({\write_addr_reg_n_0_[6] ,\write_addr_reg_n_0_[5] ,write_addr0_carry_i_1_n_0,\write_addr_reg_n_0_[3] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 write_addr0_carry__0
- (.CI(write_addr0_carry_n_0),
- .CO({write_addr0_carry__0_n_0,write_addr0_carry__0_n_1,write_addr0_carry__0_n_2,write_addr0_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(in15[10:7]),
- .S({\write_addr_reg_n_0_[10] ,\write_addr_reg_n_0_[9] ,\write_addr_reg_n_0_[8] ,\write_addr_reg_n_0_[7] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 write_addr0_carry__1
- (.CI(write_addr0_carry__0_n_0),
- .CO({write_addr0_carry__1_n_0,write_addr0_carry__1_n_1,write_addr0_carry__1_n_2,write_addr0_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(in15[14:11]),
- .S({\write_addr_reg_n_0_[14] ,\write_addr_reg_n_0_[13] ,\write_addr_reg_n_0_[12] ,\write_addr_reg_n_0_[11] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 write_addr0_carry__2
- (.CI(write_addr0_carry__1_n_0),
- .CO({write_addr0_carry__2_n_0,write_addr0_carry__2_n_1,write_addr0_carry__2_n_2,write_addr0_carry__2_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(in15[18:15]),
- .S({\write_addr_reg_n_0_[18] ,\write_addr_reg_n_0_[17] ,\write_addr_reg_n_0_[16] ,\write_addr_reg_n_0_[15] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 write_addr0_carry__3
- (.CI(write_addr0_carry__2_n_0),
- .CO({write_addr0_carry__3_n_0,write_addr0_carry__3_n_1,write_addr0_carry__3_n_2,write_addr0_carry__3_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(in15[22:19]),
- .S({\write_addr_reg_n_0_[22] ,\write_addr_reg_n_0_[21] ,\write_addr_reg_n_0_[20] ,\write_addr_reg_n_0_[19] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 write_addr0_carry__4
- (.CI(write_addr0_carry__3_n_0),
- .CO({write_addr0_carry__4_n_0,write_addr0_carry__4_n_1,write_addr0_carry__4_n_2,write_addr0_carry__4_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(in15[26:23]),
- .S({\write_addr_reg_n_0_[26] ,\write_addr_reg_n_0_[25] ,\write_addr_reg_n_0_[24] ,\write_addr_reg_n_0_[23] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 write_addr0_carry__5
- (.CI(write_addr0_carry__4_n_0),
- .CO({write_addr0_carry__5_n_0,write_addr0_carry__5_n_1,write_addr0_carry__5_n_2,write_addr0_carry__5_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(in15[30:27]),
- .S({\write_addr_reg_n_0_[30] ,\write_addr_reg_n_0_[29] ,\write_addr_reg_n_0_[28] ,\write_addr_reg_n_0_[27] }));
- (* ADDER_THRESHOLD = "35" *)
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
- CARRY4 write_addr0_carry__6
- (.CI(write_addr0_carry__5_n_0),
- .CO(NLW_write_addr0_carry__6_CO_UNCONNECTED[3:0]),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({NLW_write_addr0_carry__6_O_UNCONNECTED[3:1],in15[31]}),
- .S({1'b0,1'b0,1'b0,\write_addr_reg_n_0_[31] }));
- LUT1 #(
- .INIT(2'h1))
- write_addr0_carry_i_1
- (.I0(\write_addr_reg_n_0_[4] ),
- .O(write_addr0_carry_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair63" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[0]_i_1
- (.I0(\write_addr_reg_n_0_[0] ),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[0]),
- .O(write_addr[0]));
- (* SOFT_HLUTNM = "soft_lutpair58" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[10]_i_1
- (.I0(in15[10]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[10]),
- .O(write_addr[10]));
- (* SOFT_HLUTNM = "soft_lutpair58" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[11]_i_1
- (.I0(in15[11]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[11]),
- .O(write_addr[11]));
- (* SOFT_HLUTNM = "soft_lutpair57" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[12]_i_1
- (.I0(in15[12]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[12]),
- .O(write_addr[12]));
- (* SOFT_HLUTNM = "soft_lutpair57" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[13]_i_1
- (.I0(in15[13]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[13]),
- .O(write_addr[13]));
- (* SOFT_HLUTNM = "soft_lutpair56" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[14]_i_1
- (.I0(in15[14]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[14]),
- .O(write_addr[14]));
- (* SOFT_HLUTNM = "soft_lutpair56" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[15]_i_1
- (.I0(in15[15]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[15]),
- .O(write_addr[15]));
- (* SOFT_HLUTNM = "soft_lutpair55" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[16]_i_1
- (.I0(in15[16]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[16]),
- .O(write_addr[16]));
- (* SOFT_HLUTNM = "soft_lutpair55" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[17]_i_1
- (.I0(in15[17]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[17]),
- .O(write_addr[17]));
- (* SOFT_HLUTNM = "soft_lutpair54" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[18]_i_1
- (.I0(in15[18]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[18]),
- .O(write_addr[18]));
- (* SOFT_HLUTNM = "soft_lutpair54" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[19]_i_1
- (.I0(in15[19]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[19]),
- .O(write_addr[19]));
- (* SOFT_HLUTNM = "soft_lutpair63" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[1]_i_1
- (.I0(\write_addr_reg_n_0_[1] ),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[1]),
- .O(write_addr[1]));
- (* SOFT_HLUTNM = "soft_lutpair53" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[20]_i_1
- (.I0(in15[20]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[20]),
- .O(write_addr[20]));
- (* SOFT_HLUTNM = "soft_lutpair53" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[21]_i_1
- (.I0(in15[21]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[21]),
- .O(write_addr[21]));
- (* SOFT_HLUTNM = "soft_lutpair52" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[22]_i_1
- (.I0(in15[22]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[22]),
- .O(write_addr[22]));
- (* SOFT_HLUTNM = "soft_lutpair52" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[23]_i_1
- (.I0(in15[23]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[23]),
- .O(write_addr[23]));
- (* SOFT_HLUTNM = "soft_lutpair51" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[24]_i_1
- (.I0(in15[24]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[24]),
- .O(write_addr[24]));
- (* SOFT_HLUTNM = "soft_lutpair51" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[25]_i_1
- (.I0(in15[25]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[25]),
- .O(write_addr[25]));
- (* SOFT_HLUTNM = "soft_lutpair50" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[26]_i_1
- (.I0(in15[26]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[26]),
- .O(write_addr[26]));
- (* SOFT_HLUTNM = "soft_lutpair50" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[27]_i_1
- (.I0(in15[27]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[27]),
- .O(write_addr[27]));
- (* SOFT_HLUTNM = "soft_lutpair49" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[28]_i_1
- (.I0(in15[28]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[28]),
- .O(write_addr[28]));
- (* SOFT_HLUTNM = "soft_lutpair49" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[29]_i_1
- (.I0(in15[29]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[29]),
- .O(write_addr[29]));
- (* SOFT_HLUTNM = "soft_lutpair62" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[2]_i_1
- (.I0(\write_addr_reg_n_0_[2] ),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[2]),
- .O(write_addr[2]));
- (* SOFT_HLUTNM = "soft_lutpair48" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[30]_i_1
- (.I0(in15[30]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[30]),
- .O(write_addr[30]));
- LUT5 #(
- .INIT(32'h03020002))
- \write_addr[31]_i_1
- (.I0(p_5_in[0]),
- .I1(write_state_reg[2]),
- .I2(write_state_reg[1]),
- .I3(write_state_reg[0]),
- .I4(M_AXI_AWVALID_i_4_n_0),
- .O(\write_addr[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair47" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[31]_i_2
- (.I0(in15[31]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[31]),
- .O(write_addr[31]));
- (* SOFT_HLUTNM = "soft_lutpair62" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[3]_i_1
- (.I0(in15[3]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[3]),
- .O(write_addr[3]));
- (* SOFT_HLUTNM = "soft_lutpair61" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[4]_i_1
- (.I0(in15[4]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[4]),
- .O(write_addr[4]));
- (* SOFT_HLUTNM = "soft_lutpair61" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[5]_i_1
- (.I0(in15[5]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[5]),
- .O(write_addr[5]));
- (* SOFT_HLUTNM = "soft_lutpair60" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[6]_i_1
- (.I0(in15[6]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[6]),
- .O(write_addr[6]));
- (* SOFT_HLUTNM = "soft_lutpair60" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[7]_i_1
- (.I0(in15[7]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[7]),
- .O(write_addr[7]));
- (* SOFT_HLUTNM = "soft_lutpair59" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[8]_i_1
- (.I0(in15[8]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[8]),
- .O(write_addr[8]));
- (* SOFT_HLUTNM = "soft_lutpair59" *)
- LUT3 #(
- .INIT(8'hB8))
- \write_addr[9]_i_1
- (.I0(in15[9]),
- .I1(write_state_reg[0]),
- .I2(write_address_reg[9]),
- .O(write_addr[9]));
- FDRE \write_addr_reg[0]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[0]),
- .Q(\write_addr_reg_n_0_[0] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[10]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[10]),
- .Q(\write_addr_reg_n_0_[10] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[11]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[11]),
- .Q(\write_addr_reg_n_0_[11] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[12]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[12]),
- .Q(\write_addr_reg_n_0_[12] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[13]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[13]),
- .Q(\write_addr_reg_n_0_[13] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[14]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[14]),
- .Q(\write_addr_reg_n_0_[14] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[15]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[15]),
- .Q(\write_addr_reg_n_0_[15] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[16]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[16]),
- .Q(\write_addr_reg_n_0_[16] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[17]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[17]),
- .Q(\write_addr_reg_n_0_[17] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[18]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[18]),
- .Q(\write_addr_reg_n_0_[18] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[19]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[19]),
- .Q(\write_addr_reg_n_0_[19] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[1]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[1]),
- .Q(\write_addr_reg_n_0_[1] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[20]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[20]),
- .Q(\write_addr_reg_n_0_[20] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[21]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[21]),
- .Q(\write_addr_reg_n_0_[21] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[22]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[22]),
- .Q(\write_addr_reg_n_0_[22] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[23]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[23]),
- .Q(\write_addr_reg_n_0_[23] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[24]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[24]),
- .Q(\write_addr_reg_n_0_[24] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[25]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[25]),
- .Q(\write_addr_reg_n_0_[25] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[26]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[26]),
- .Q(\write_addr_reg_n_0_[26] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[27]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[27]),
- .Q(\write_addr_reg_n_0_[27] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[28]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[28]),
- .Q(\write_addr_reg_n_0_[28] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[29]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[29]),
- .Q(\write_addr_reg_n_0_[29] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[2]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[2]),
- .Q(\write_addr_reg_n_0_[2] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[30]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[30]),
- .Q(\write_addr_reg_n_0_[30] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[31]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[31]),
- .Q(\write_addr_reg_n_0_[31] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[3]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[3]),
- .Q(\write_addr_reg_n_0_[3] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[4]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[4]),
- .Q(\write_addr_reg_n_0_[4] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[5]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[5]),
- .Q(\write_addr_reg_n_0_[5] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[6]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[6]),
- .Q(\write_addr_reg_n_0_[6] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[7]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[7]),
- .Q(\write_addr_reg_n_0_[7] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[8]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[8]),
- .Q(\write_addr_reg_n_0_[8] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_addr_reg[9]
- (.C(CLK),
- .CE(\write_addr[31]_i_1_n_0 ),
- .D(write_addr[9]),
- .Q(\write_addr_reg_n_0_[9] ),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000080000))
- \write_address_reg[31]_i_1
- (.I0(S_AXIL_AWADDR[2]),
- .I1(S_AXIL_WVALID_0),
- .I2(S_AXIL_AWADDR[1]),
- .I3(S_AXIL_AWADDR[0]),
- .I4(\write_address_reg[31]_i_2_n_0 ),
- .I5(\read_address_reg[31]_i_2_n_0 ),
- .O(write_address_reg_2));
- LUT5 #(
- .INIT(32'h80000000))
- \write_address_reg[31]_i_2
- (.I0(S_AXIL_AWADDR[3]),
- .I1(S_AXIL_WSTRB[3]),
- .I2(S_AXIL_WSTRB[2]),
- .I3(S_AXIL_WSTRB[0]),
- .I4(S_AXIL_WSTRB[1]),
- .O(\write_address_reg[31]_i_2_n_0 ));
- FDRE \write_address_reg_reg[0]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[0]),
- .Q(write_address_reg[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[10]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[10]),
- .Q(write_address_reg[10]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[11]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[11]),
- .Q(write_address_reg[11]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[12]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[12]),
- .Q(write_address_reg[12]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[13]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[13]),
- .Q(write_address_reg[13]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[14]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[14]),
- .Q(write_address_reg[14]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[15]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[15]),
- .Q(write_address_reg[15]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[16]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[16]),
- .Q(write_address_reg[16]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[17]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[17]),
- .Q(write_address_reg[17]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[18]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[18]),
- .Q(write_address_reg[18]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[19]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[19]),
- .Q(write_address_reg[19]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[1]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[1]),
- .Q(write_address_reg[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[20]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[20]),
- .Q(write_address_reg[20]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[21]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[21]),
- .Q(write_address_reg[21]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[22]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[22]),
- .Q(write_address_reg[22]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[23]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[23]),
- .Q(write_address_reg[23]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[24]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[24]),
- .Q(write_address_reg[24]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[25]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[25]),
- .Q(write_address_reg[25]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[26]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[26]),
- .Q(write_address_reg[26]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[27]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[27]),
- .Q(write_address_reg[27]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[28]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[28]),
- .Q(write_address_reg[28]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[29]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[29]),
- .Q(write_address_reg[29]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[2]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[2]),
- .Q(write_address_reg[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[30]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[30]),
- .Q(write_address_reg[30]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[31]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[31]),
- .Q(write_address_reg[31]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[3]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[3]),
- .Q(write_address_reg[3]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[4]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[4]),
- .Q(write_address_reg[4]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[5]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[5]),
- .Q(write_address_reg[5]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[6]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[6]),
- .Q(write_address_reg[6]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[7]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[7]),
- .Q(write_address_reg[7]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[8]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[8]),
- .Q(write_address_reg[8]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE \write_address_reg_reg[9]
- (.C(CLK),
- .CE(write_address_reg_2),
- .D(S_AXIL_WDATA[9]),
- .Q(write_address_reg[9]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAEEEFAAAA2220))
- \write_state[0]_i_1
- (.I0(p_0_in[0]),
- .I1(M_AXI_AWVALID_i_3_n_0),
- .I2(M_AXI_AWVALID_i_4_n_0),
- .I3(M_AXI_AWVALID_i_5_n_0),
- .I4(\write_state[2]_i_3_n_0 ),
- .I5(write_state_reg[0]),
- .O(\write_state[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00000000FFEF0F0F))
- \write_state[0]_i_2
- (.I0(\write_state[2]_i_4_n_0 ),
- .I1(\write_state[2]_i_5_n_0 ),
- .I2(write_state_reg[0]),
- .I3(\write_state[2]_i_6_n_0 ),
- .I4(write_state_reg[1]),
- .I5(write_state_reg[2]),
- .O(p_0_in[0]));
- LUT6 #(
- .INIT(64'h3C3C3C3CDCDCDCCC))
- \write_state[1]_i_1
- (.I0(write_state_reg[2]),
- .I1(write_state_reg[1]),
- .I2(write_state_reg[0]),
- .I3(M_AXI_AWVALID_i_4_n_0),
- .I4(M_AXI_AWVALID_i_5_n_0),
- .I5(\write_state[2]_i_3_n_0 ),
- .O(\write_state[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAEEEFAAAA2220))
- \write_state[2]_i_1
- (.I0(p_0_in[2]),
- .I1(M_AXI_AWVALID_i_3_n_0),
- .I2(M_AXI_AWVALID_i_4_n_0),
- .I3(M_AXI_AWVALID_i_5_n_0),
- .I4(\write_state[2]_i_3_n_0 ),
- .I5(write_state_reg[2]),
- .O(\write_state[2]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \write_state[2]_i_10
- (.I0(\data_cnt_reg_n_0_[2] ),
- .I1(\data_cnt_reg_n_0_[3] ),
- .I2(\data_cnt_reg_n_0_[1] ),
- .I3(\data_cnt_reg_n_0_[0] ),
- .O(\write_state[2]_i_10_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \write_state[2]_i_11
- (.I0(\data_cnt_reg_n_0_[5] ),
- .I1(\data_cnt_reg_n_0_[4] ),
- .I2(\data_cnt_reg_n_0_[6] ),
- .I3(\data_cnt_reg_n_0_[7] ),
- .O(\write_state[2]_i_11_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \write_state[2]_i_12
- (.I0(\data_cnt_reg_n_0_[29] ),
- .I1(\data_cnt_reg_n_0_[18] ),
- .I2(\data_cnt_reg_n_0_[28] ),
- .I3(\data_cnt_reg_n_0_[19] ),
- .O(\write_state[2]_i_12_n_0 ));
- LUT5 #(
- .INIT(32'h00100000))
- \write_state[2]_i_2
- (.I0(\write_state[2]_i_4_n_0 ),
- .I1(\write_state[2]_i_5_n_0 ),
- .I2(write_state_reg[0]),
- .I3(\write_state[2]_i_6_n_0 ),
- .I4(write_state_reg[1]),
- .O(p_0_in[2]));
- LUT6 #(
- .INIT(64'hD0FFD0D0D0FFD0FF))
- \write_state[2]_i_3
- (.I0(p_5_in[1]),
- .I1(interrupt_reset_reg_n_0),
- .I2(INTERRUPT_INST_0_i_1_n_0),
- .I3(\write_state[2]_i_7_n_0 ),
- .I4(M_AXI_WLAST_i_2_n_0),
- .I5(write_state_reg[0]),
- .O(\write_state[2]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \write_state[2]_i_4
- (.I0(\data_cnt_reg_n_0_[22] ),
- .I1(\data_cnt_reg_n_0_[23] ),
- .I2(\data_cnt_reg_n_0_[21] ),
- .I3(\write_state[2]_i_8_n_0 ),
- .I4(\write_state[2]_i_9_n_0 ),
- .I5(\write_state[2]_i_10_n_0 ),
- .O(\write_state[2]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \write_state[2]_i_5
- (.I0(\data_cnt_reg_n_0_[27] ),
- .I1(\data_cnt_reg_n_0_[8] ),
- .I2(\data_cnt_reg_n_0_[11] ),
- .I3(\data_cnt_reg_n_0_[20] ),
- .I4(\data_cnt_reg_n_0_[10] ),
- .I5(\data_cnt_reg_n_0_[9] ),
- .O(\write_state[2]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \write_state[2]_i_6
- (.I0(\data_cnt_reg_n_0_[16] ),
- .I1(\data_cnt_reg_n_0_[17] ),
- .I2(\data_cnt_reg_n_0_[30] ),
- .I3(\data_cnt_reg_n_0_[31] ),
- .I4(\write_state[2]_i_11_n_0 ),
- .I5(\write_state[2]_i_12_n_0 ),
- .O(\write_state[2]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAAEFBBEFEEEFFFEF))
- \write_state[2]_i_7
- (.I0(write_state_reg[2]),
- .I1(write_state_reg[0]),
- .I2(p_5_in[0]),
- .I3(write_state_reg[1]),
- .I4(M_AXI_AWREADY),
- .I5(M_AXI_WREADY),
- .O(\write_state[2]_i_7_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \write_state[2]_i_8
- (.I0(\data_cnt_reg_n_0_[15] ),
- .I1(\data_cnt_reg_n_0_[14] ),
- .I2(\data_cnt_reg_n_0_[12] ),
- .I3(\data_cnt_reg_n_0_[13] ),
- .O(\write_state[2]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'hFE))
- \write_state[2]_i_9
- (.I0(\data_cnt_reg_n_0_[25] ),
- .I1(\data_cnt_reg_n_0_[26] ),
- .I2(\data_cnt_reg_n_0_[24] ),
- .O(\write_state[2]_i_9_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \write_state_reg[0]
- (.C(CLK),
- .CE(1'b1),
- .D(\write_state[0]_i_1_n_0 ),
- .Q(write_state_reg[0]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \write_state_reg[1]
- (.C(CLK),
- .CE(1'b1),
- .D(\write_state[1]_i_1_n_0 ),
- .Q(write_state_reg[1]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \write_state_reg[2]
- (.C(CLK),
- .CE(1'b1),
- .D(\write_state[2]_i_1_n_0 ),
- .Q(write_state_reg[2]),
- .R(\initial_value_reg[31]_i_1_n_0 ));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
- parameter GRES_WIDTH = 10000;
- parameter GRES_START = 10000;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- wire GRESTORE;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
- reg GRESTORE_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
- assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
- initial begin
- GRESTORE_int = 1'b0;
- #(GRES_START);
- GRESTORE_int = 1'b1;
- #(GRES_WIDTH);
- GRESTORE_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_stub.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_stub.v
deleted file mode 100644
index bebc3c3..0000000
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_stub.v
+++ /dev/null
@@ -1,100 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-// Date : Tue Feb 11 19:38:52 2025
-// Host : BiermannSurface running 64-bit major release (build 9200)
-// Command : write_verilog -force -mode synth_stub
-// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_stub.v
-// Design : axi_crc_dma_syn_1_axis_dma_0_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z020clg400-1
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* x_core_info = "axis_dma,Vivado 2023.1" *)
-module axi_crc_dma_syn_1_axis_dma_0_0(CLK, RESETN, INTERRUPT, initial_value,
- polynomial, finalXOR, inOutReflected, FIFO_NUM_FREE, FIFO_NUM_AVAIL, S_AXIL_AWADDR,
- S_AXIL_AWVALID, S_AXIL_AWREADY, S_AXIL_WDATA, S_AXIL_WVALID, S_AXIL_WREADY, S_AXIL_WSTRB,
- S_AXIL_BVALID, S_AXIL_BREADY, S_AXIL_BRESP, S_AXIL_ARADDR, S_AXIL_ARVALID, S_AXIL_ARREADY,
- S_AXIL_RDATA, S_AXIL_RVALID, S_AXIL_RREADY, S_AXIL_RRESP, M_AXI_ARREADY, M_AXI_ARVALID,
- M_AXI_ARADDR, M_AXI_ARID, M_AXI_ARLEN, M_AXI_ARSIZE, M_AXI_ARBURST, M_AXI_ARPROT,
- M_AXI_ARCACHE, M_AXI_RREADY, M_AXI_RVALID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RID, M_AXI_RLAST,
- M_AXI_AWREADY, M_AXI_AWVALID, M_AXI_AWADDR, M_AXI_AWLEN, M_AXI_AWSIZE, M_AXI_AWID,
- M_AXI_AWBURST, M_AXI_AWPROT, M_AXI_AWCACHE, M_AXI_WREADY, M_AXI_WVALID, M_AXI_WDATA,
- M_AXI_WSTRB, M_AXI_WLAST, M_AXI_WID, M_AXI_BREADY, M_AXI_BVALID, M_AXI_BID, M_AXI_BRESP,
- S_AXIS_TVALID, S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA,
- M_AXIS_TLAST, M_AXIS_TREADY)
-/* synthesis syn_black_box black_box_pad_pin="RESETN,INTERRUPT,initial_value[31:0],polynomial[31:0],finalXOR[31:0],inOutReflected[1:0],FIFO_NUM_FREE[7:0],FIFO_NUM_AVAIL[7:0],S_AXIL_AWADDR[7:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[7:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARID[0:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[0:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[0:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[31:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[31:0],M_AXI_BRESP[1:0],S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY" */
-/* synthesis syn_force_seq_prim="CLK" */;
- input CLK /* synthesis syn_isclock = 1 */;
- input RESETN;
- output INTERRUPT;
- output [31:0]initial_value;
- output [31:0]polynomial;
- output [31:0]finalXOR;
- output [1:0]inOutReflected;
- input [7:0]FIFO_NUM_FREE;
- input [7:0]FIFO_NUM_AVAIL;
- input [7:0]S_AXIL_AWADDR;
- input S_AXIL_AWVALID;
- output S_AXIL_AWREADY;
- input [31:0]S_AXIL_WDATA;
- input S_AXIL_WVALID;
- output S_AXIL_WREADY;
- input [3:0]S_AXIL_WSTRB;
- output S_AXIL_BVALID;
- input S_AXIL_BREADY;
- output [1:0]S_AXIL_BRESP;
- input [7:0]S_AXIL_ARADDR;
- input S_AXIL_ARVALID;
- output S_AXIL_ARREADY;
- output [31:0]S_AXIL_RDATA;
- output S_AXIL_RVALID;
- input S_AXIL_RREADY;
- output [1:0]S_AXIL_RRESP;
- input M_AXI_ARREADY;
- output M_AXI_ARVALID;
- output [31:0]M_AXI_ARADDR;
- output [0:0]M_AXI_ARID;
- output [3:0]M_AXI_ARLEN;
- output [2:0]M_AXI_ARSIZE;
- output [1:0]M_AXI_ARBURST;
- output [2:0]M_AXI_ARPROT;
- output [3:0]M_AXI_ARCACHE;
- output M_AXI_RREADY;
- input M_AXI_RVALID;
- input [31:0]M_AXI_RDATA;
- input [1:0]M_AXI_RRESP;
- input [0:0]M_AXI_RID;
- input M_AXI_RLAST;
- input M_AXI_AWREADY;
- output M_AXI_AWVALID;
- output [31:0]M_AXI_AWADDR;
- output [3:0]M_AXI_AWLEN;
- output [2:0]M_AXI_AWSIZE;
- output [0:0]M_AXI_AWID;
- output [1:0]M_AXI_AWBURST;
- output [2:0]M_AXI_AWPROT;
- output [3:0]M_AXI_AWCACHE;
- input M_AXI_WREADY;
- output M_AXI_WVALID;
- output [31:0]M_AXI_WDATA;
- output [3:0]M_AXI_WSTRB;
- output M_AXI_WLAST;
- output [31:0]M_AXI_WID;
- output M_AXI_BREADY;
- input M_AXI_BVALID;
- input [31:0]M_AXI_BID;
- input [1:0]M_AXI_BRESP;
- input S_AXIS_TVALID;
- input [31:0]S_AXIS_TDATA;
- input S_AXIS_TLAST;
- output S_AXIS_TREADY;
- output M_AXIS_TVALID;
- output [31:0]M_AXIS_TDATA;
- output M_AXIS_TLAST;
- input M_AXIS_TREADY;
-endmodule
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/sim/axi_crc_dma_syn_1_axis_dma_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/sim/axi_crc_dma_syn_1_axis_dma_0_0.vhd
deleted file mode 100644
index 281ff0c..0000000
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/sim/axi_crc_dma_syn_1_axis_dma_0_0.vhd
+++ /dev/null
@@ -1,365 +0,0 @@
--- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of AMD and is protected under U.S. and international copyright
--- and other intellectual property laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- AMD, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) AMD shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or AMD had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- AMD products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of AMD products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:module_ref:axis_dma:1.0
--- IP Revision: 1
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY axi_crc_dma_syn_1_axis_dma_0_0 IS
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- INTERRUPT : OUT STD_LOGIC;
- initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_AWVALID : IN STD_LOGIC;
- S_AXIL_AWREADY : OUT STD_LOGIC;
- S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIL_WVALID : IN STD_LOGIC;
- S_AXIL_WREADY : OUT STD_LOGIC;
- S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- S_AXIL_BVALID : OUT STD_LOGIC;
- S_AXIL_BREADY : IN STD_LOGIC;
- S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_ARVALID : IN STD_LOGIC;
- S_AXIL_ARREADY : OUT STD_LOGIC;
- S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIL_RVALID : OUT STD_LOGIC;
- S_AXIL_RREADY : IN STD_LOGIC;
- S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARREADY : IN STD_LOGIC;
- M_AXI_ARVALID : OUT STD_LOGIC;
- M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_RREADY : OUT STD_LOGIC;
- M_AXI_RVALID : IN STD_LOGIC;
- M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_RLAST : IN STD_LOGIC;
- M_AXI_AWREADY : IN STD_LOGIC;
- M_AXI_AWVALID : OUT STD_LOGIC;
- M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WREADY : IN STD_LOGIC;
- M_AXI_WVALID : OUT STD_LOGIC;
- M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WLAST : OUT STD_LOGIC;
- M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BREADY : OUT STD_LOGIC;
- M_AXI_BVALID : IN STD_LOGIC;
- M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIS_TVALID : IN STD_LOGIC;
- S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIS_TLAST : IN STD_LOGIC;
- S_AXIS_TREADY : OUT STD_LOGIC;
- M_AXIS_TVALID : OUT STD_LOGIC;
- M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXIS_TLAST : OUT STD_LOGIC;
- M_AXIS_TREADY : IN STD_LOGIC
- );
-END axi_crc_dma_syn_1_axis_dma_0_0;
-
-ARCHITECTURE axi_crc_dma_syn_1_axis_dma_0_0_arch OF axi_crc_dma_syn_1_axis_dma_0_0 IS
- ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
- ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "yes";
- COMPONENT axis_dma IS
- GENERIC (
- DWIDTH : INTEGER;
- IDWIDTH : INTEGER;
- MAX_BURSTLEN : INTEGER;
- FIFO_AWIDTH : INTEGER;
- polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0);
- initial_value_default : STD_LOGIC_VECTOR(31 DOWNTO 0)
- );
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- INTERRUPT : OUT STD_LOGIC;
- initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_AWVALID : IN STD_LOGIC;
- S_AXIL_AWREADY : OUT STD_LOGIC;
- S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIL_WVALID : IN STD_LOGIC;
- S_AXIL_WREADY : OUT STD_LOGIC;
- S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- S_AXIL_BVALID : OUT STD_LOGIC;
- S_AXIL_BREADY : IN STD_LOGIC;
- S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_ARVALID : IN STD_LOGIC;
- S_AXIL_ARREADY : OUT STD_LOGIC;
- S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIL_RVALID : OUT STD_LOGIC;
- S_AXIL_RREADY : IN STD_LOGIC;
- S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARREADY : IN STD_LOGIC;
- M_AXI_ARVALID : OUT STD_LOGIC;
- M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_RREADY : OUT STD_LOGIC;
- M_AXI_RVALID : IN STD_LOGIC;
- M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_RLAST : IN STD_LOGIC;
- M_AXI_AWREADY : IN STD_LOGIC;
- M_AXI_AWVALID : OUT STD_LOGIC;
- M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WREADY : IN STD_LOGIC;
- M_AXI_WVALID : OUT STD_LOGIC;
- M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WLAST : OUT STD_LOGIC;
- M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BREADY : OUT STD_LOGIC;
- M_AXI_BVALID : IN STD_LOGIC;
- M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIS_TVALID : IN STD_LOGIC;
- S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIS_TLAST : IN STD_LOGIC;
- S_AXIS_TREADY : OUT STD_LOGIC;
- M_AXIS_TVALID : OUT STD_LOGIC;
- M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXIS_TLAST : OUT STD_LOGIC;
- M_AXIS_TREADY : IN STD_LOGIC
- );
- END COMPONENT axis_dma;
- ATTRIBUTE X_INTERFACE_INFO : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
- ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
- ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
- ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 66666672, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, LAYERED_METADATA undef, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
- ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR" &
-"EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
- ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
- ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_" &
-"THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
- ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 66666672, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, LAYERED_METADATA undef, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
-BEGIN
- U0 : axis_dma
- GENERIC MAP (
- DWIDTH => 32,
- IDWIDTH => 1,
- MAX_BURSTLEN => 16,
- FIFO_AWIDTH => 8,
- polynomial_default => X"04C11DB7",
- initial_value_default => X"00000000"
- )
- PORT MAP (
- CLK => CLK,
- RESETN => RESETN,
- INTERRUPT => INTERRUPT,
- initial_value => initial_value,
- polynomial => polynomial,
- finalXOR => finalXOR,
- inOutReflected => inOutReflected,
- FIFO_NUM_FREE => FIFO_NUM_FREE,
- FIFO_NUM_AVAIL => FIFO_NUM_AVAIL,
- S_AXIL_AWADDR => S_AXIL_AWADDR,
- S_AXIL_AWVALID => S_AXIL_AWVALID,
- S_AXIL_AWREADY => S_AXIL_AWREADY,
- S_AXIL_WDATA => S_AXIL_WDATA,
- S_AXIL_WVALID => S_AXIL_WVALID,
- S_AXIL_WREADY => S_AXIL_WREADY,
- S_AXIL_WSTRB => S_AXIL_WSTRB,
- S_AXIL_BVALID => S_AXIL_BVALID,
- S_AXIL_BREADY => S_AXIL_BREADY,
- S_AXIL_BRESP => S_AXIL_BRESP,
- S_AXIL_ARADDR => S_AXIL_ARADDR,
- S_AXIL_ARVALID => S_AXIL_ARVALID,
- S_AXIL_ARREADY => S_AXIL_ARREADY,
- S_AXIL_RDATA => S_AXIL_RDATA,
- S_AXIL_RVALID => S_AXIL_RVALID,
- S_AXIL_RREADY => S_AXIL_RREADY,
- S_AXIL_RRESP => S_AXIL_RRESP,
- M_AXI_ARREADY => M_AXI_ARREADY,
- M_AXI_ARVALID => M_AXI_ARVALID,
- M_AXI_ARADDR => M_AXI_ARADDR,
- M_AXI_ARID => M_AXI_ARID,
- M_AXI_ARLEN => M_AXI_ARLEN,
- M_AXI_ARSIZE => M_AXI_ARSIZE,
- M_AXI_ARBURST => M_AXI_ARBURST,
- M_AXI_ARPROT => M_AXI_ARPROT,
- M_AXI_ARCACHE => M_AXI_ARCACHE,
- M_AXI_RREADY => M_AXI_RREADY,
- M_AXI_RVALID => M_AXI_RVALID,
- M_AXI_RDATA => M_AXI_RDATA,
- M_AXI_RRESP => M_AXI_RRESP,
- M_AXI_RID => M_AXI_RID,
- M_AXI_RLAST => M_AXI_RLAST,
- M_AXI_AWREADY => M_AXI_AWREADY,
- M_AXI_AWVALID => M_AXI_AWVALID,
- M_AXI_AWADDR => M_AXI_AWADDR,
- M_AXI_AWLEN => M_AXI_AWLEN,
- M_AXI_AWSIZE => M_AXI_AWSIZE,
- M_AXI_AWID => M_AXI_AWID,
- M_AXI_AWBURST => M_AXI_AWBURST,
- M_AXI_AWPROT => M_AXI_AWPROT,
- M_AXI_AWCACHE => M_AXI_AWCACHE,
- M_AXI_WREADY => M_AXI_WREADY,
- M_AXI_WVALID => M_AXI_WVALID,
- M_AXI_WDATA => M_AXI_WDATA,
- M_AXI_WSTRB => M_AXI_WSTRB,
- M_AXI_WLAST => M_AXI_WLAST,
- M_AXI_WID => M_AXI_WID,
- M_AXI_BREADY => M_AXI_BREADY,
- M_AXI_BVALID => M_AXI_BVALID,
- M_AXI_BID => M_AXI_BID,
- M_AXI_BRESP => M_AXI_BRESP,
- S_AXIS_TVALID => S_AXIS_TVALID,
- S_AXIS_TDATA => S_AXIS_TDATA,
- S_AXIS_TLAST => S_AXIS_TLAST,
- S_AXIS_TREADY => S_AXIS_TREADY,
- M_AXIS_TVALID => M_AXIS_TVALID,
- M_AXIS_TDATA => M_AXIS_TDATA,
- M_AXIS_TLAST => M_AXIS_TLAST,
- M_AXIS_TREADY => M_AXIS_TREADY
- );
-END axi_crc_dma_syn_1_axis_dma_0_0_arch;
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/synth/axi_crc_dma_syn_1_axis_dma_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/synth/axi_crc_dma_syn_1_axis_dma_0_0.vhd
deleted file mode 100644
index 239b6d5..0000000
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/synth/axi_crc_dma_syn_1_axis_dma_0_0.vhd
+++ /dev/null
@@ -1,373 +0,0 @@
--- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of AMD and is protected under U.S. and international copyright
--- and other intellectual property laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- AMD, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) AMD shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or AMD had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- AMD products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of AMD products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:module_ref:axis_dma:1.0
--- IP Revision: 1
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY axi_crc_dma_syn_1_axis_dma_0_0 IS
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- INTERRUPT : OUT STD_LOGIC;
- initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_AWVALID : IN STD_LOGIC;
- S_AXIL_AWREADY : OUT STD_LOGIC;
- S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIL_WVALID : IN STD_LOGIC;
- S_AXIL_WREADY : OUT STD_LOGIC;
- S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- S_AXIL_BVALID : OUT STD_LOGIC;
- S_AXIL_BREADY : IN STD_LOGIC;
- S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_ARVALID : IN STD_LOGIC;
- S_AXIL_ARREADY : OUT STD_LOGIC;
- S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIL_RVALID : OUT STD_LOGIC;
- S_AXIL_RREADY : IN STD_LOGIC;
- S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARREADY : IN STD_LOGIC;
- M_AXI_ARVALID : OUT STD_LOGIC;
- M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_RREADY : OUT STD_LOGIC;
- M_AXI_RVALID : IN STD_LOGIC;
- M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_RLAST : IN STD_LOGIC;
- M_AXI_AWREADY : IN STD_LOGIC;
- M_AXI_AWVALID : OUT STD_LOGIC;
- M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WREADY : IN STD_LOGIC;
- M_AXI_WVALID : OUT STD_LOGIC;
- M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WLAST : OUT STD_LOGIC;
- M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BREADY : OUT STD_LOGIC;
- M_AXI_BVALID : IN STD_LOGIC;
- M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIS_TVALID : IN STD_LOGIC;
- S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIS_TLAST : IN STD_LOGIC;
- S_AXIS_TREADY : OUT STD_LOGIC;
- M_AXIS_TVALID : OUT STD_LOGIC;
- M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXIS_TLAST : OUT STD_LOGIC;
- M_AXIS_TREADY : IN STD_LOGIC
- );
-END axi_crc_dma_syn_1_axis_dma_0_0;
-
-ARCHITECTURE axi_crc_dma_syn_1_axis_dma_0_0_arch OF axi_crc_dma_syn_1_axis_dma_0_0 IS
- ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
- ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "yes";
- COMPONENT axis_dma IS
- GENERIC (
- DWIDTH : INTEGER;
- IDWIDTH : INTEGER;
- MAX_BURSTLEN : INTEGER;
- FIFO_AWIDTH : INTEGER;
- polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0);
- initial_value_default : STD_LOGIC_VECTOR(31 DOWNTO 0)
- );
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- INTERRUPT : OUT STD_LOGIC;
- initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_AWVALID : IN STD_LOGIC;
- S_AXIL_AWREADY : OUT STD_LOGIC;
- S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIL_WVALID : IN STD_LOGIC;
- S_AXIL_WREADY : OUT STD_LOGIC;
- S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- S_AXIL_BVALID : OUT STD_LOGIC;
- S_AXIL_BREADY : IN STD_LOGIC;
- S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- S_AXIL_ARVALID : IN STD_LOGIC;
- S_AXIL_ARREADY : OUT STD_LOGIC;
- S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIL_RVALID : OUT STD_LOGIC;
- S_AXIL_RREADY : IN STD_LOGIC;
- S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARREADY : IN STD_LOGIC;
- M_AXI_ARVALID : OUT STD_LOGIC;
- M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_RREADY : OUT STD_LOGIC;
- M_AXI_RVALID : IN STD_LOGIC;
- M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_RLAST : IN STD_LOGIC;
- M_AXI_AWREADY : IN STD_LOGIC;
- M_AXI_AWVALID : OUT STD_LOGIC;
- M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WREADY : IN STD_LOGIC;
- M_AXI_WVALID : OUT STD_LOGIC;
- M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WLAST : OUT STD_LOGIC;
- M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BREADY : OUT STD_LOGIC;
- M_AXI_BVALID : IN STD_LOGIC;
- M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- S_AXIS_TVALID : IN STD_LOGIC;
- S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- S_AXIS_TLAST : IN STD_LOGIC;
- S_AXIS_TREADY : OUT STD_LOGIC;
- M_AXIS_TVALID : OUT STD_LOGIC;
- M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXIS_TLAST : OUT STD_LOGIC;
- M_AXIS_TREADY : IN STD_LOGIC
- );
- END COMPONENT axis_dma;
- ATTRIBUTE X_CORE_INFO : STRING;
- ATTRIBUTE X_CORE_INFO OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "axis_dma,Vivado 2023.1";
- ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
- ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_syn_1_axis_dma_0_0_arch : ARCHITECTURE IS "axi_crc_dma_syn_1_axis_dma_0_0,axis_dma,{}";
- ATTRIBUTE CORE_GENERATION_INFO : STRING;
- ATTRIBUTE CORE_GENERATION_INFO OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "axi_crc_dma_syn_1_axis_dma_0_0,axis_dma,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_dma,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DWIDTH=32,IDWIDTH=1,MAX_BURSTLEN=16,FIFO_AWIDTH=8,polynomial_default=0x04C11DB7,initial_value_default=0x00000000}";
- ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
- ATTRIBUTE IP_DEFINITION_SOURCE OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "module_ref";
- ATTRIBUTE X_INTERFACE_INFO : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
- ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
- ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
- ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 66666672, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, LAYERED_METADATA undef, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
- ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR" &
-"EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
- ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
- ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_" &
-"THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
- ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 66666672, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, LAYERED_METADATA undef, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
-BEGIN
- U0 : axis_dma
- GENERIC MAP (
- DWIDTH => 32,
- IDWIDTH => 1,
- MAX_BURSTLEN => 16,
- FIFO_AWIDTH => 8,
- polynomial_default => X"04C11DB7",
- initial_value_default => X"00000000"
- )
- PORT MAP (
- CLK => CLK,
- RESETN => RESETN,
- INTERRUPT => INTERRUPT,
- initial_value => initial_value,
- polynomial => polynomial,
- finalXOR => finalXOR,
- inOutReflected => inOutReflected,
- FIFO_NUM_FREE => FIFO_NUM_FREE,
- FIFO_NUM_AVAIL => FIFO_NUM_AVAIL,
- S_AXIL_AWADDR => S_AXIL_AWADDR,
- S_AXIL_AWVALID => S_AXIL_AWVALID,
- S_AXIL_AWREADY => S_AXIL_AWREADY,
- S_AXIL_WDATA => S_AXIL_WDATA,
- S_AXIL_WVALID => S_AXIL_WVALID,
- S_AXIL_WREADY => S_AXIL_WREADY,
- S_AXIL_WSTRB => S_AXIL_WSTRB,
- S_AXIL_BVALID => S_AXIL_BVALID,
- S_AXIL_BREADY => S_AXIL_BREADY,
- S_AXIL_BRESP => S_AXIL_BRESP,
- S_AXIL_ARADDR => S_AXIL_ARADDR,
- S_AXIL_ARVALID => S_AXIL_ARVALID,
- S_AXIL_ARREADY => S_AXIL_ARREADY,
- S_AXIL_RDATA => S_AXIL_RDATA,
- S_AXIL_RVALID => S_AXIL_RVALID,
- S_AXIL_RREADY => S_AXIL_RREADY,
- S_AXIL_RRESP => S_AXIL_RRESP,
- M_AXI_ARREADY => M_AXI_ARREADY,
- M_AXI_ARVALID => M_AXI_ARVALID,
- M_AXI_ARADDR => M_AXI_ARADDR,
- M_AXI_ARID => M_AXI_ARID,
- M_AXI_ARLEN => M_AXI_ARLEN,
- M_AXI_ARSIZE => M_AXI_ARSIZE,
- M_AXI_ARBURST => M_AXI_ARBURST,
- M_AXI_ARPROT => M_AXI_ARPROT,
- M_AXI_ARCACHE => M_AXI_ARCACHE,
- M_AXI_RREADY => M_AXI_RREADY,
- M_AXI_RVALID => M_AXI_RVALID,
- M_AXI_RDATA => M_AXI_RDATA,
- M_AXI_RRESP => M_AXI_RRESP,
- M_AXI_RID => M_AXI_RID,
- M_AXI_RLAST => M_AXI_RLAST,
- M_AXI_AWREADY => M_AXI_AWREADY,
- M_AXI_AWVALID => M_AXI_AWVALID,
- M_AXI_AWADDR => M_AXI_AWADDR,
- M_AXI_AWLEN => M_AXI_AWLEN,
- M_AXI_AWSIZE => M_AXI_AWSIZE,
- M_AXI_AWID => M_AXI_AWID,
- M_AXI_AWBURST => M_AXI_AWBURST,
- M_AXI_AWPROT => M_AXI_AWPROT,
- M_AXI_AWCACHE => M_AXI_AWCACHE,
- M_AXI_WREADY => M_AXI_WREADY,
- M_AXI_WVALID => M_AXI_WVALID,
- M_AXI_WDATA => M_AXI_WDATA,
- M_AXI_WSTRB => M_AXI_WSTRB,
- M_AXI_WLAST => M_AXI_WLAST,
- M_AXI_WID => M_AXI_WID,
- M_AXI_BREADY => M_AXI_BREADY,
- M_AXI_BVALID => M_AXI_BVALID,
- M_AXI_BID => M_AXI_BID,
- M_AXI_BRESP => M_AXI_BRESP,
- S_AXIS_TVALID => S_AXIS_TVALID,
- S_AXIS_TDATA => S_AXIS_TDATA,
- S_AXIS_TLAST => S_AXIS_TLAST,
- S_AXIS_TREADY => S_AXIS_TREADY,
- M_AXIS_TVALID => M_AXIS_TVALID,
- M_AXIS_TDATA => M_AXIS_TDATA,
- M_AXIS_TLAST => M_AXIS_TLAST,
- M_AXIS_TREADY => M_AXIS_TREADY
- );
-END axi_crc_dma_syn_1_axis_dma_0_0_arch;
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xml
index d31e48f..ce65b7c 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xml
@@ -9107,7 +9107,7 @@
FREQ_HZ
- 1e+08
+ 100000000
FREQ_TOLERANCE_HZ
@@ -9199,7 +9199,7 @@
FREQ_HZ
- 1.25e+08
+ 125000000
FREQ_TOLERANCE_HZ
@@ -9291,7 +9291,7 @@
FREQ_HZ
- 2e+08
+ 200000000
FREQ_TOLERANCE_HZ
@@ -9383,7 +9383,7 @@
FREQ_HZ
- 6.66667e+07
+ 66666672
FREQ_TOLERANCE_HZ
@@ -40687,22 +40687,22 @@
-
-
+
+
-
-
-
-
-
-
+
+
+
+
+
+
-
-
-
+
+
+
diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/axi_crc_dma_syn_1_system_ila_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/axi_crc_dma_syn_1_system_ila_0_0.xml
index ca3b4fb..260527a 100644
--- a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/axi_crc_dma_syn_1_system_ila_0_0.xml
+++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/axi_crc_dma_syn_1_system_ila_0_0.xml
@@ -2181,7 +2181,7 @@
GENtimestamp
- Tue Feb 11 18:46:03 UTC 2025
+ Tue Feb 11 20:11:14 UTC 2025
outputProductCRC
@@ -2199,7 +2199,7 @@
GENtimestamp
- Tue Feb 11 18:35:33 UTC 2025
+ Tue Feb 11 18:46:01 UTC 2025
outputProductCRC
@@ -2235,7 +2235,7 @@
GENtimestamp
- Tue Feb 11 18:46:24 UTC 2025
+ Tue Feb 11 20:11:44 UTC 2025
outputProductCRC
@@ -2254,7 +2254,7 @@
GENtimestamp
- Tue Feb 11 18:46:03 UTC 2025
+ Tue Feb 11 20:11:14 UTC 2025
outputProductCRC
@@ -2307,7 +2307,7 @@
GENtimestamp
- Tue Feb 11 18:46:03 UTC 2025
+ Tue Feb 11 20:11:14 UTC 2025
outputProductCRC
@@ -39904,7 +39904,7 @@
-
+