From b786fa8a51f21b62e6737682296d2c23b9c0da51 Mon Sep 17 00:00:00 2001 From: Matthias Biermann Date: Sat, 1 Feb 2025 14:15:55 +0100 Subject: [PATCH] axis_crc.vhd separierter Ansatz --- Hardware/CRC.vhd | 42 +- Hardware/aci_crc_dma/.gitignore | 89 + .../axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml | 11 + ...crc_dma_sim_1_axil_master_with_rom_0_0.xml | 1039 +++++++ .../axi_crc_dma_sim_1_axis_crc_0_0.xml | 691 +++++ .../axi_crc_dma_sim_1_axis_dma_0_0.xml | 2570 +++++++++++++++++ .../axi_crc_dma_sim_1_axis_downsizer_0_0.xml | 721 +++++ .../axi_crc_dma_sim_1_axis_fifo_0_0.xml | 1907 ++++++++++++ .../axi_crc_dma_sim_1_axis_fifo_1_0.xml | 1907 ++++++++++++ .../axi_crc_dma_sim_1_axis_upsizer_0_0.xml | 737 +++++ ...xi_crc_dma_sim_1_clk_rst_generator_0_0.xml | 164 ++ .../bd/axis_crc_sim_1/axis_crc_sim_1.bxml | 56 + .../bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc | 10 + .../hdl/axis_crc_sim_1_wrapper.vhd | 24 + .../axis_crc_sim_1_axis_crc_0_0.xml | 735 +++++ .../sim/axis_crc_sim_1_axis_crc_0_0.vhd | 132 + .../axis_crc_sim_1_axis_downsizer_0_0.xml | 779 +++++ .../sim/axis_crc_sim_1_axis_downsizer_0_0.vhd | 136 + ...xis_crc_sim_1_axis_master_simmodel_0_0.xml | 735 +++++ ...xis_crc_sim_1_axis_master_simmodel_0_0.vhd | 152 + ...axis_crc_sim_1_axis_slave_simmodel_0_0.xml | 639 ++++ ...axis_crc_sim_1_axis_slave_simmodel_0_0.vhd | 136 + .../axis_crc_sim_1_axis_upsizer_0_0.xml | 795 +++++ .../sim/axis_crc_sim_1_axis_upsizer_0_0.vhd | 136 + .../axis_crc_sim_1_clk_rst_generator_0_0.xml | 222 ++ .../axis_crc_sim_1_clk_rst_generator_0_0.vhd | 99 + .../axis_crc_sim_1_xlconstant_0_0.xml | 205 ++ .../sim/axis_crc_sim_1_xlconstant_0_0.h | 65 + .../sim/axis_crc_sim_1_xlconstant_0_0.v | 68 + .../sim/axis_crc_sim_1_xlconstant_0_0_stub.sv | 79 + .../sim/xlconstant_v1_1_7.h | 69 + .../axis_crc_sim_1_xlconstant_1_0.xml | 205 ++ .../sim/axis_crc_sim_1_xlconstant_1_0.h | 65 + .../sim/axis_crc_sim_1_xlconstant_1_0.v | 68 + .../sim/axis_crc_sim_1_xlconstant_1_0_stub.sv | 79 + .../sim/xlconstant_v1_1_7.h | 69 + .../9185/sources_1/new/axis_downsizer.vhd | 94 + .../9a97/sources_1/new/clk_rst_generator.vhd | 114 + .../b0f2/hdl/xlconstant_v1_1_vl_rfs.v | 31 + .../ipshared/c453/axis_slave_simmodel.vhd | 317 ++ .../axis_crc_sim_1/ipshared/c453/bmp_pkg.vhd | 207 ++ .../ipshared/d44d/axis_master_simmodel.vhd | 375 +++ .../axis_crc_sim_1/ipshared/d44d/bmp_pkg.vhd | 208 ++ .../dfd1/sources_1/new/axis_upsizer.vhd | 103 + .../bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd | 286 ++ .../axis_crc_sim_1/synth/axis_crc_sim_1.vhd | 286 ++ .../sources_1/bd/mref/axis_crc/component.xml | 426 +++ .../bd/mref/axis_crc/xgui/axis_crc_v1_0.tcl | 40 + .../sources_1/bd/mref/axis_dma/component.xml | 1734 +++++++++++ .../bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl | 55 + .../bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd | 1112 +++++++ ...crc_dma_sim_1_axil_master_with_rom_0_0.xci | 173 ++ .../axi_crc_dma_sim_1_axis_crc_0_0.xci | 144 + .../axi_crc_dma_sim_1_axis_dma_0_0.xci | 350 +++ .../axi_crc_dma_sim_1_axis_downsizer_0_0.xci | 148 + .../axi_crc_dma_sim_1_axis_fifo_0_0.xci | 197 ++ .../axi_crc_dma_sim_1_axis_fifo_1_0.xci | 197 ++ .../axi_crc_dma_sim_1_axis_upsizer_0_0.xci | 148 + ...xi_crc_dma_sim_1_clk_rst_generator_0_0.xci | 57 + .../bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui | 34 + .../bd/axis_crc_sim_1/axis_crc_sim_1.bd | 387 +++ .../axis_crc_sim_1_axis_crc_0_0.xci | 144 + .../axis_crc_sim_1_axis_downsizer_0_0.xci | 148 + ...xis_crc_sim_1_axis_master_simmodel_0_0.xci | 148 + ...axis_crc_sim_1_axis_slave_simmodel_0_0.xci | 135 + .../axis_crc_sim_1_axis_upsizer_0_0.xci | 148 + .../axis_crc_sim_1_clk_rst_generator_0_0.xci | 57 + .../axis_crc_sim_1_xlconstant_0_0.xci | 49 + .../axis_crc_sim_1_xlconstant_1_0.xci | 49 + .../bd/axis_crc_sim_1/ui/bd_9f9006c0.ui | 36 + .../aci_crc_dma.xpr} | 96 +- .../axis_crc_sim_1_wrapper_behav.wcfg | 106 + Hardware/axis_crc.vhd | 78 + Hardware/axis_dma.vhd | 95 + Hardware/crc_dma/crc_dma.cache/wt/project.wpc | 3 - Hardware/crc_dma/crc_dma.hw/crc_dma.lpr | 7 - 76 files changed, 24112 insertions(+), 46 deletions(-) create mode 100644 Hardware/aci_crc_dma/.gitignore create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_downsizer_0_0/axi_crc_dma_sim_1_axis_downsizer_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_upsizer_0_0/axi_crc_dma_sim_1_axis_upsizer_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/sim/axis_crc_sim_1_axis_crc_0_0.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0/axis_crc_sim_1_axis_downsizer_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0/sim/axis_crc_sim_1_axis_downsizer_0_0.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/sim/axis_crc_sim_1_axis_master_simmodel_0_0.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/sim/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0/axis_crc_sim_1_axis_upsizer_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0/sim/axis_crc_sim_1_axis_upsizer_0_0.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/sim/axis_crc_sim_1_clk_rst_generator_0_0.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0.h create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0.v create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0_stub.sv create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0.h create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0.v create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0_stub.sv create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/xlconstant_v1_1_7.h create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/9185/sources_1/new/axis_downsizer.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/c453/axis_slave_simmodel.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/c453/bmp_pkg.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/d44d/axis_master_simmodel.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/d44d/bmp_pkg.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/dfd1/sources_1/new/axis_upsizer.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/xgui/axis_crc_v1_0.tcl create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_downsizer_0_0/axi_crc_dma_sim_1_axis_downsizer_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_upsizer_0_0/axi_crc_dma_sim_1_axis_upsizer_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0/axis_crc_sim_1_axis_downsizer_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0/axis_crc_sim_1_axis_upsizer_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xci create mode 100644 Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui rename Hardware/{crc_dma/crc_dma.xpr => aci_crc_dma/aci_crc_dma.xpr} (73%) create mode 100644 Hardware/aci_crc_dma/axis_crc_sim_1_wrapper_behav.wcfg create mode 100644 Hardware/axis_crc.vhd create mode 100644 Hardware/axis_dma.vhd delete mode 100644 Hardware/crc_dma/crc_dma.cache/wt/project.wpc delete mode 100644 Hardware/crc_dma/crc_dma.hw/crc_dma.lpr diff --git a/Hardware/CRC.vhd b/Hardware/CRC.vhd index b0da3cf..5ef9fd0 100644 --- a/Hardware/CRC.vhd +++ b/Hardware/CRC.vhd @@ -1,43 +1,43 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; entity crc is generic ( - crcLength : positive; - inDataLength : positive + CRC_WIDTH : positive; + DWIDTH : positive ); port ( - clk : in std_logic; + clk : in std_logic; -- Kontrollsignale - reset : in std_logic; - enable : in std_logic; - initialValue : in std_logic_vector(crcLength-1 downto 0); - polynomial : in std_logic_vector(crcLength-1 downto 0); + reset : in std_logic; + enable : in std_logic; + initial_value : in std_logic_vector(CRC_WIDTH-1 downto 0); + polynomial : in std_logic_vector(CRC_WIDTH-1 downto 0); -- Datensignale - inData : in std_logic_vector(inDataLength-1 downto 0); - checksum : out std_logic_vector(crcLength-1 downto 0) + data : in std_logic_vector(DWIDTH-1 downto 0); + checksum : out std_logic_vector(CRC_WIDTH-1 downto 0) ); end crc; -architecture Behavioral of crc is +architecture rtl of crc is -- Interne Signale fuer CRC Pruefsumme - signal checksum_i : std_logic_vector(crcLength-1 downto 0); - signal nextChecksum : std_logic_vector(crcLength-1 downto 0); + signal checksum_i : std_logic_vector(CRC_WIDTH-1 downto 0); + signal nextChecksum : std_logic_vector(CRC_WIDTH-1 downto 0); begin -- Kombinatorik fuer CRC-Berechnung - ProcNextCRC: process (inData, checksum_i) - variable mix: std_logic_vector(crcLength-1 downto 0); + ProcNextCRC: process (data, checksum_i) + variable mix: std_logic_vector(CRC_WIDTH-1 downto 0); variable MSB : std_logic; begin mix := checksum_i; - for i in inData'range loop + for i in data'range loop -- Pruefen ob MSB gesetzt ist MSB := mix(mix'length-1); -- neues Bit reinschieben - mix := mix(mix'length-2 downto 0) & inData(i); + mix := mix(mix'length-2 downto 0) & data(i); -- XOR Verknuepfung if MSB = '1' then mix := mix XOR polynomial; @@ -51,7 +51,7 @@ begin begin if rising_edge(clk) then if reset = '1' then - checksum_i <= initialValue; + checksum_i <= initial_value; elsif enable = '1' then checksum_i <= nextChecksum; end if; @@ -60,4 +60,4 @@ begin checksum <= checksum_i; -end Behavioral; +end architecture; diff --git a/Hardware/aci_crc_dma/.gitignore b/Hardware/aci_crc_dma/.gitignore new file mode 100644 index 0000000..67f001d --- /dev/null +++ b/Hardware/aci_crc_dma/.gitignore @@ -0,0 +1,89 @@ +# Created by https://www.toptal.com/developers/gitignore/api/vivado +# Edit at https://www.toptal.com/developers/gitignore?templates=vivado + +### Vivado ### +######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######### +#Exclude all +* +!*/ +!.gitignore +########################################################################### +## VIVADO +#Source files: +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.sv +!*.bd +!*.edif +#IP files +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#.xcix: Core container file +#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41) +!*.xcix +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +#System Generator +!*.mdl +!*.slx +!*.bxml +#Simulation logic analyzer +!*.wcfg +!*.coe +#MIG +!*.prj +!*.mem +#Project files +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +!*.xml +#Constraint files +#Do NOT ignore *.xdc files +!*.xdc +#TCL - files +!*.tcl +#Journal - files +!*.jou +#Reports +!*.rpt +!*.txt +!*.vdi +#C-files +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp + +# End of https://www.toptal.com/developers/gitignore/api/vivado + +# Vidado project directories which are not needed +.Xil/ +*.cache/ +*.hw/ +*.ip_user_files/ +*.runs/ +*.sim/ +# design checkpoint file +*.dcp + +# ignore Vivado log files +*.log +*.jou +vivado_pid*.str + +# DO NOT ignore images as bitmap files +!*.bmp \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml new file mode 100644 index 0000000..4b3d991 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml @@ -0,0 +1,11 @@ + + + + Composite Fileset + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml new file mode 100644 index 0000000..f027342 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml @@ -0,0 +1,1039 @@ + + + wg + customized_ip + axi_crc_dma_sim_1_axil_master_with_rom_0_0 + 1.0 + + + M_AXIL + + + + + + + + + AWADDR + + + M_AXIL_AWADDR + + + + + AWPROT + + + M_AXIL_AWPROT + + + + + AWVALID + + + M_AXIL_AWVALID + + + + + AWREADY + + + M_AXIL_AWREADY + + + + + WDATA + + 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+ in + + + std_logic + dummy_view + + + + + + AXIS_ARESETN + + in + + + std_logic + dummy_view + + + + + + S_AXIS_TVALID + + in + + + std_logic + dummy_view + + + + + + S_AXIS_TDATA + + in + + 15 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + dummy_view + + + + 0 + + + + + S_AXIS_TREADY + + out + + + std_logic + dummy_view + + + + + + S_AXIS_TUSER + + in + + + std_logic + dummy_view + + + + 0 + + + + + M_AXIS_TVALID + + out + + + std_logic + dummy_view + + + + + + M_AXIS_TDATA + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + M_AXIS_TLAST + + out + + + std_logic + dummy_view + + + + + + M_AXIS_TREADY + + in + + + std_logic + dummy_view + + + + 1 + + + + + M_AXIS_TUSER + + out + + + std_logic + dummy_view + + + + + + + + WIDTH_IN + Width In + 16 + + + SIZE_FACTOR + Size Factor + 2 + + + BIG_ENDIAN + Big Endian + false + + + + + + choice_list_552a89ba + 2 + 4 + 8 + 16 + + + choice_list_5f2cf65b + 1 + 8 + 16 + 32 + 64 + 128 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + axis_upsizer_v1_0 + + + WIDTH_IN + Width In + 16 + + + SIZE_FACTOR + Size Factor + 2 + + + BIG_ENDIAN + Big Endian + false + + + Component_Name + axi_crc_dma_sim_1_axis_upsizer_0_0 + + + + + axis_upsizer_v1_0 + package_project + 3 + + d:/Projekte/edvs/vivado/vivado/ip_projects/axis_upsizer/axis_upsizer.srcs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xml new file mode 100644 index 0000000..53aa449 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xml @@ -0,0 +1,164 @@ + + + wg + customized_ip + axi_crc_dma_sim_1_clk_rst_generator_0_0 + 1.0 + + + + clk_in + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + + true + + + + + + rst_in + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + + true + + + + + + clk + + out + + + std_logic + dummy_view + + + + + + rst_n + + out + + + std_logic + dummy_view + + + + + + stop_simulation + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + + true + + + + + + + + CLOCK_PERIOD + Clock Period + 10000 + + + HAS_CLK_INPUT + Has Clk Input + true + + + HAS_RESET_INPUT + Has Reset Input + true + + + HAS_STOP_INPUT + Has Stop Input + true + + + + clk_rst_generator + + + CLOCK_PERIOD + Clock Period [ps] + 10000 + + + HAS_CLK_INPUT + Clock Input + true + + + HAS_RESET_INPUT + Reset Input + true + + + HAS_STOP_INPUT + Stop Input + true + + + Component_Name + axi_crc_dma_sim_1_clk_rst_generator_0_0 + + + + + clk_rst_generator + package_project + 7 + + + 2023.1 + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml new file mode 100644 index 0000000..5c3fb9f --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml @@ -0,0 +1,56 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc new file mode 100644 index 0000000..7fac2b2 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc @@ -0,0 +1,10 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ + +################################################################################ \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd new file mode 100644 index 0000000..579236f --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd @@ -0,0 +1,24 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Sat Feb 1 13:46:52 2025 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target axis_crc_sim_1_wrapper.bd +--Design : axis_crc_sim_1_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity axis_crc_sim_1_wrapper is +end axis_crc_sim_1_wrapper; + +architecture STRUCTURE of axis_crc_sim_1_wrapper is + component axis_crc_sim_1 is + end component axis_crc_sim_1; +begin +axis_crc_sim_1_i: component axis_crc_sim_1 + ; +end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml new file mode 100644 index 0000000..2376639 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml @@ -0,0 +1,735 @@ + + + xilinx.com + customized_ip + axis_crc_sim_1_axis_crc_0_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 2 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 2 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RESETN + + + + + + + RST + + + RESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK + + + + + + + CLK + + + CLK + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS + + + ASSOCIATED_RESET + RESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_crc + + + outputProductCRC + 9:4c49e31c + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axis_crc_sim_1_axis_crc_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sat Feb 01 12:46:52 UTC 2025 + + + outputProductCRC + 9:4c49e31c + + + + + + + CLK + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + RESETN + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + initial_value + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + polynomial + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + + CRC_WIDTH + Crc Width + 32 + + + DWITH + Dwith + 16 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_axis_crc_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx.com:module_ref:axis_crc:1.0 + + + CRC_WIDTH + Crc Width + 32 + + + DWITH + Dwith + 16 + + + Component_Name + axis_crc_sim_1_axis_crc_0_0 + + + + + axis_crc_v1_0 + module_ref + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/sim/axis_crc_sim_1_axis_crc_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/sim/axis_crc_sim_1_axis_crc_0_0.vhd new file mode 100644 index 0000000..0173d61 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/sim/axis_crc_sim_1_axis_crc_0_0.vhd @@ -0,0 +1,132 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:axis_crc:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_axis_crc_0_0 IS + PORT ( + CLK : IN STD_LOGIC; + RESETN : IN STD_LOGIC; + initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC + ); +END axis_crc_sim_1_axis_crc_0_0; + +ARCHITECTURE axis_crc_sim_1_axis_crc_0_0_arch OF axis_crc_sim_1_axis_crc_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_crc IS + GENERIC ( + CRC_WIDTH : INTEGER; + DWITH : INTEGER + ); + PORT ( + CLK : IN STD_LOGIC; + RESETN : IN STD_LOGIC; + initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC + ); + END COMPONENT axis_crc; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_crc + GENERIC MAP ( + CRC_WIDTH => 32, + DWITH => 16 + ) + PORT MAP ( + CLK => CLK, + RESETN => RESETN, + initial_value => initial_value, + polynomial => polynomial, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY + ); +END axis_crc_sim_1_axis_crc_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0/axis_crc_sim_1_axis_downsizer_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0/axis_crc_sim_1_axis_downsizer_0_0.xml new file mode 100644 index 0000000..b649903 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0/axis_crc_sim_1_axis_downsizer_0_0.xml @@ -0,0 +1,779 @@ + + + xilinx.com + customized_ip + axis_crc_sim_1_axis_downsizer_0_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TUSER + + + M_AXIS_TUSER + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 2 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TUSER + + + S_AXIS_TUSER + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXIS_ARESETN + + + + + + + RST + + + AXIS_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXIS_ACLK + + + + + + + CLK + + + AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS + + + ASSOCIATED_RESET + AXIS_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_downsizer + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:0d47368c + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axis_crc_sim_1_axis_downsizer_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:0d47368c + + + + + + + AXIS_ACLK + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + AXIS_ARESETN + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TUSER + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + M_AXIS_TUSER + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + + + WIDTH_OUT + Width Out + 16 + + + SIZE_FACTOR + Size Factor + 2 + + + BIG_ENDIAN + Big Endian + false + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/9185/sources_1/new/axis_downsizer.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_axis_downsizer_0_0.vhd + vhdlSource + xil_defaultlib + + + + axis_downsizer_v1_0 + + + WIDTH_OUT + Width Out + 16 + + + SIZE_FACTOR + Size Factor + 2 + + + BIG_ENDIAN + Big Endian + false + + + Component_Name + axis_crc_sim_1_axis_downsizer_0_0 + + + + + axis_downsizer_v1_0 + package_project + 2 + + d:/projekte/edvs/vivado/vivado/ip_projects/axis_downsizer/axis_downsizer.srcs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0/sim/axis_crc_sim_1_axis_downsizer_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0/sim/axis_crc_sim_1_axis_downsizer_0_0.vhd new file mode 100644 index 0000000..b676174 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0/sim/axis_crc_sim_1_axis_downsizer_0_0.vhd @@ -0,0 +1,136 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:user:axis_downsizer:1.0 +-- IP Revision: 2 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_axis_downsizer_0_0 IS + PORT ( + AXIS_ACLK : IN STD_LOGIC; + AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC + ); +END axis_crc_sim_1_axis_downsizer_0_0; + +ARCHITECTURE axis_crc_sim_1_axis_downsizer_0_0_arch OF axis_crc_sim_1_axis_downsizer_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_downsizer_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_downsizer IS + GENERIC ( + WIDTH_OUT : INTEGER; + SIZE_FACTOR : INTEGER; + BIG_ENDIAN : BOOLEAN + ); + PORT ( + AXIS_ACLK : IN STD_LOGIC; + AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC + ); + END COMPONENT axis_downsizer; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_downsizer + GENERIC MAP ( + WIDTH_OUT => 16, + SIZE_FACTOR => 2, + BIG_ENDIAN => false + ) + PORT MAP ( + AXIS_ACLK => AXIS_ACLK, + AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TUSER => S_AXIS_TUSER, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TUSER => M_AXIS_TUSER + ); +END axis_crc_sim_1_axis_downsizer_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xml new file mode 100644 index 0000000..33dffe1 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xml @@ -0,0 +1,735 @@ + + + Gehrke + customized_ip + axis_crc_sim_1_axis_master_simmodel_0_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TUSER + + + M_AXIS_TUSER + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + signal_reset + + + + + + + RST + + + ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + signal_clock + + + + + + + CLK + + + ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS + + + ASSOCIATED_RESET + ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_master_simmodel + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:1454e34a + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axis_crc_sim_1_axis_master_simmodel_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Jan 31 17:40:16 UTC 2025 + + + outputProductCRC + 9:1454e34a + + + + + + + ACLK + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + ARESETN + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + FINISHED + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TUSER + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_NUM_FREE + + in + + 10 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + + + DATA_WIDTH + Data Width + 32 + + + HAS_FIFO_INTERFACE + Has Fifo Interface + false + + + FIFO_AWIDTH + Fifo Awidth + 11 + + + FIFO_REQUEST_TRESHOLD + Fifo Request Treshold + 32 + + + TUSERWIDTH + Tuserwidth + 1 + + + FILE_NAME + File Name + ../../../../tst + + + FILE_EXTENSION + File Extension + raw + + + FILE_AUTONUMBERING + File Autonumbering + false + + + NUM_PIX_PER_LINE + Num Pix Per Line + 128 + + + NUM_LINES + Num Lines + 128 + + + NUM_FRAMES_PER_FILE + Num Frames Per File + 1 + + + RANDOM_TVALID + Random Tvalid + true + + + PIXEL_FORMAT + Pixel Format + 1 + + + ALPHA_VALUE + Alpha Value + 255 + + + FRAMING_PIXELS + Framing Pixels + 0 + + + FRAMING_LINES + Framing Lines + 0 + + + FRAMING_VAL_R_V + Framing Val R V + 128 + + + FRAMING_VAL_G_Y + Framing Val G Y + 128 + + + FRAMING_VAL_B_U + Framing Val B U + 128 + + + + + + choice_list_91f15632 + bmp + yuv + bin + raw + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/d44d/bmp_pkg.vhd + vhdlSource + + + ../../ipshared/d44d/axis_master_simmodel.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_axis_master_simmodel_0_0.vhd + vhdlSource + xil_defaultlib + + + + axis_master_simmodel + + + FRAMING_VAL_B_U + Framing Val B U + 128 + + + FRAMING_VAL_G_Y + Framing Val G Y + 128 + + + FRAMING_VAL_R_V + Framing Val R V + 128 + + + FRAMING_LINES + Framing Lines + 0 + + + FRAMING_PIXELS + Framing Pixels + 0 + + + ALPHA_VALUE + Alpha Value + 255 + + + PIXEL_FORMAT + Pixel Format + 1 + + + RANDOM_TVALID + Random Tvalid + true + + + NUM_FRAMES_PER_FILE + Num Frames Per File + 1 + + + NUM_LINES + Num Lines + 128 + + + NUM_PIX_PER_LINE + Num Pix Per Line + 128 + + + FILE_AUTONUMBERING + File Autonumbering + false + + + FILE_EXTENSION + File Extension + raw + + + FILE_NAME + File Name + ../../../tst + + + TUSERWIDTH + Tuserwidth + 1 + + + FIFO_REQUEST_TRESHOLD + Fifo Request Treshold + 32 + + + FIFO_AWIDTH + Fifo Awidth + 11 + + + HAS_FIFO_INTERFACE + Has Fifo Interface + false + + + Component_Name + Component Name + axis_crc_sim_1_axis_master_simmodel_0_0 + + + + + axis_master_simmodel + 10 + + D:/Projekte/edvs/vivado/ip_projects/axis_master_simmodel/axis_master_simmodel.srcs/sources_1/new + D:/Projekte/edvs/vivado/ip_projects/axis_master_simmodel/axis_master_simmodel.srcs/sources_1/new + D:/Projekte/edvs/vivado/ip_projects/axis_master_simmodel/axis_master_simmodel.srcs/sources_1/new + + + + + + + + + + + + + + + + + + + + + + + + + + + 2015.2 + + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/sim/axis_crc_sim_1_axis_master_simmodel_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/sim/axis_crc_sim_1_axis_master_simmodel_0_0.vhd new file mode 100644 index 0000000..d7bfa54 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/sim/axis_crc_sim_1_axis_master_simmodel_0_0.vhd @@ -0,0 +1,152 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: Gehrke:user:axis_master_simmodel:1.0 +-- IP Revision: 10 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_axis_master_simmodel_0_0 IS + PORT ( + ACLK : IN STD_LOGIC; + ARESETN : IN STD_LOGIC; + FINISHED : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END axis_crc_sim_1_axis_master_simmodel_0_0; + +ARCHITECTURE axis_crc_sim_1_axis_master_simmodel_0_0_arch OF axis_crc_sim_1_axis_master_simmodel_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_master_simmodel_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_master_simmodel IS + GENERIC ( + DATA_WIDTH : INTEGER; + HAS_FIFO_INTERFACE : BOOLEAN; + FIFO_AWIDTH : INTEGER; + FIFO_REQUEST_TRESHOLD : INTEGER; + TUSERWIDTH : INTEGER; + FILE_NAME : STRING; + FILE_EXTENSION : STRING; + FILE_AUTONUMBERING : BOOLEAN; + NUM_PIX_PER_LINE : INTEGER; + NUM_LINES : INTEGER; + NUM_FRAMES_PER_FILE : INTEGER; + RANDOM_TVALID : BOOLEAN; + PIXEL_FORMAT : INTEGER; + ALPHA_VALUE : INTEGER; + FRAMING_PIXELS : INTEGER; + FRAMING_LINES : INTEGER; + FRAMING_VAL_R_V : INTEGER; + FRAMING_VAL_G_Y : INTEGER; + FRAMING_VAL_B_U : INTEGER + ); + PORT ( + ACLK : IN STD_LOGIC; + ARESETN : IN STD_LOGIC; + FINISHED : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_AXIS_NUM_FREE : IN STD_LOGIC_VECTOR(10 DOWNTO 0) + ); + END COMPONENT axis_master_simmodel; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; +BEGIN + U0 : axis_master_simmodel + GENERIC MAP ( + DATA_WIDTH => 32, + HAS_FIFO_INTERFACE => false, + FIFO_AWIDTH => 11, + FIFO_REQUEST_TRESHOLD => 32, + TUSERWIDTH => 1, + FILE_NAME => "../../../../tst", + FILE_EXTENSION => "raw", + FILE_AUTONUMBERING => false, + NUM_PIX_PER_LINE => 128, + NUM_LINES => 128, + NUM_FRAMES_PER_FILE => 1, + RANDOM_TVALID => true, + PIXEL_FORMAT => 1, + ALPHA_VALUE => 255, + FRAMING_PIXELS => 0, + FRAMING_LINES => 0, + FRAMING_VAL_R_V => 128, + FRAMING_VAL_G_Y => 128, + FRAMING_VAL_B_U => 128 + ) + PORT MAP ( + ACLK => ACLK, + ARESETN => ARESETN, + FINISHED => FINISHED, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_NUM_FREE => STD_LOGIC_VECTOR(TO_UNSIGNED(1, 11)) + ); +END axis_crc_sim_1_axis_master_simmodel_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xml new file mode 100644 index 0000000..7c95a80 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xml @@ -0,0 +1,639 @@ + + + Gehrke + customized_ip + axis_crc_sim_1_axis_slave_simmodel_0_0 + 1.0 + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TUSER + + + S_AXIS_TUSER + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS_signal_reset + + + + + + + RST + + + S_AXIS_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS_signal_clock + + + + + + + CLK + + + S_AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXIS + + + ASSOCIATED_RESET + S_AXIS_ARESETN + + + FREQ_HZ + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_slave_simmodel + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:ac7016c1 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axis_crc_sim_1_axis_slave_simmodel_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Jan 31 17:40:16 UTC 2025 + + + outputProductCRC + 9:ac7016c1 + + + + + + + FINISHED + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_ACLK + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_ARESETN + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TUSER + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + + + + + TUSERWIDTH + Tuserwidth + 1 + + + FILE_NAME + File Name + ../../../../tst_out + + + FILE_EXTENSION + File Extension + raw + + + FILE_AUTONUMBERING + File Autonumbering + false + + + PIXEL_FORMAT + Pixel Format + 1 + + + NUM_PIX_PER_LINE + Num Pix Per Line + 128 + + + NUM_LINES + Num Lines + 128 + + + NUM_FRAMES_PER_FILE + Num Frames Per File + 1 + + + NUM_FILES + Num Files + 1 + + + FRAMING_PIXELS + Framing Pixels + 0 + + + FRAMING_LINES + Framing Lines + 0 + + + RANDOM_TREADY + Random Tready + true + + + + + + choice_list_91f15632 + bmp + yuv + bin + raw + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/c453/bmp_pkg.vhd + vhdlSource + + + ../../ipshared/c453/axis_slave_simmodel.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd + vhdlSource + xil_defaultlib + + + + axis_slave_simmodel_v1_0 + + + RANDOM_TREADY + Random Tready + true + + + FRAMING_LINES + Framing Lines + 0 + + + FRAMING_PIXELS + Framing Pixels + 0 + + + NUM_FILES + Num Files + 1 + + + NUM_FRAMES_PER_FILE + Num Frames Per File + 1 + + + NUM_LINES + Num Lines + 128 + + + NUM_PIX_PER_LINE + Num Pix Per Line + 128 + + + PIXEL_FORMAT + Pixel Format + 1 + + + FILE_AUTONUMBERING + File Autonumbering + false + + + FILE_EXTENSION + File Extension + raw + + + FILE_NAME + File Name + ../../../tst_out + + + TUSERWIDTH + Tuserwidth + 1 + + + Component_Name + Component Name + axis_crc_sim_1_axis_slave_simmodel_0_0 + + + + + axis_slave_simmodel_v1_0 + 4 + + D:/Projekte/edvs/vivado/ip_projects/axis_slave_simmodel/axis_slave_simmodel.srcs/sources_1/new + D:/Projekte/edvs/vivado/ip_projects/axis_slave_simmodel/axis_slave_simmodel.srcs/sources_1/new + D:/Projekte/edvs/vivado/ip_projects/axis_slave_simmodel/axis_slave_simmodel.srcs/sources_1/new + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/sim/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/sim/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd new file mode 100644 index 0000000..db13f81 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/sim/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd @@ -0,0 +1,136 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: Gehrke:user:axis_slave_simmodel:1.0 +-- IP Revision: 4 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_axis_slave_simmodel_0_0 IS + PORT ( + FINISHED : OUT STD_LOGIC; + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END axis_crc_sim_1_axis_slave_simmodel_0_0; + +ARCHITECTURE axis_crc_sim_1_axis_slave_simmodel_0_0_arch OF axis_crc_sim_1_axis_slave_simmodel_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_slave_simmodel_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_slave_simmodel IS + GENERIC ( + TUSERWIDTH : INTEGER; + FILE_NAME : STRING; + FILE_EXTENSION : STRING; + FILE_AUTONUMBERING : BOOLEAN; + PIXEL_FORMAT : INTEGER; + NUM_PIX_PER_LINE : INTEGER; + NUM_LINES : INTEGER; + NUM_FRAMES_PER_FILE : INTEGER; + NUM_FILES : INTEGER; + FRAMING_PIXELS : INTEGER; + FRAMING_LINES : INTEGER; + RANDOM_TREADY : BOOLEAN + ); + PORT ( + FINISHED : OUT STD_LOGIC; + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT axis_slave_simmodel; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_slave_simmodel + GENERIC MAP ( + TUSERWIDTH => 1, + FILE_NAME => "../../../../tst_out", + FILE_EXTENSION => "raw", + FILE_AUTONUMBERING => false, + PIXEL_FORMAT => 1, + NUM_PIX_PER_LINE => 128, + NUM_LINES => 128, + NUM_FRAMES_PER_FILE => 1, + NUM_FILES => 1, + FRAMING_PIXELS => 0, + FRAMING_LINES => 0, + RANDOM_TREADY => true + ) + PORT MAP ( + FINISHED => FINISHED, + S_AXIS_ACLK => S_AXIS_ACLK, + S_AXIS_ARESETN => S_AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TUSER => S_AXIS_TUSER + ); +END axis_crc_sim_1_axis_slave_simmodel_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0/axis_crc_sim_1_axis_upsizer_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0/axis_crc_sim_1_axis_upsizer_0_0.xml new file mode 100644 index 0000000..7f973d6 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0/axis_crc_sim_1_axis_upsizer_0_0.xml @@ -0,0 +1,795 @@ + + + xilinx.com + customized_ip + axis_crc_sim_1_axis_upsizer_0_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TUSER + + + M_AXIS_TUSER + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TUSER + + + S_AXIS_TUSER + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 2 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXIS_ARESETN + + + + + + + RST + + + AXIS_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXIS_ACLK + + + + + + + CLK + + + AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS + + + ASSOCIATED_RESET + AXIS_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_upsizer + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:e18349df + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axis_crc_sim_1_axis_upsizer_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:e18349df + + + + + + + AXIS_ACLK + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + AXIS_ARESETN + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TUSER + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + M_AXIS_TUSER + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + + + WIDTH_IN + Width In + 16 + + + SIZE_FACTOR + Size Factor + 2 + + + BIG_ENDIAN + Big Endian + false + + + + + + choice_list_552a89ba + 2 + 4 + 8 + 16 + + + choice_list_5f2cf65b + 1 + 8 + 16 + 32 + 64 + 128 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/dfd1/sources_1/new/axis_upsizer.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_axis_upsizer_0_0.vhd + vhdlSource + xil_defaultlib + + + + axis_upsizer_v1_0 + + + WIDTH_IN + Width In + 16 + + + SIZE_FACTOR + Size Factor + 2 + + + BIG_ENDIAN + Big Endian + false + + + Component_Name + axis_crc_sim_1_axis_upsizer_0_0 + + + + + axis_upsizer_v1_0 + package_project + 3 + + d:/Projekte/edvs/vivado/vivado/ip_projects/axis_upsizer/axis_upsizer.srcs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0/sim/axis_crc_sim_1_axis_upsizer_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0/sim/axis_crc_sim_1_axis_upsizer_0_0.vhd new file mode 100644 index 0000000..35299bc --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0/sim/axis_crc_sim_1_axis_upsizer_0_0.vhd @@ -0,0 +1,136 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:user:axis_upsizer:1.0 +-- IP Revision: 3 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_axis_upsizer_0_0 IS + PORT ( + AXIS_ACLK : IN STD_LOGIC; + AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC + ); +END axis_crc_sim_1_axis_upsizer_0_0; + +ARCHITECTURE axis_crc_sim_1_axis_upsizer_0_0_arch OF axis_crc_sim_1_axis_upsizer_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_upsizer_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_upsizer IS + GENERIC ( + WIDTH_IN : INTEGER; + SIZE_FACTOR : INTEGER; + BIG_ENDIAN : BOOLEAN + ); + PORT ( + AXIS_ACLK : IN STD_LOGIC; + AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC + ); + END COMPONENT axis_upsizer; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_upsizer + GENERIC MAP ( + WIDTH_IN => 16, + SIZE_FACTOR => 2, + BIG_ENDIAN => false + ) + PORT MAP ( + AXIS_ACLK => AXIS_ACLK, + AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TUSER => S_AXIS_TUSER, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TUSER => M_AXIS_TUSER + ); +END axis_crc_sim_1_axis_upsizer_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xml new file mode 100644 index 0000000..6e3b10f --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xml @@ -0,0 +1,222 @@ + + + wg + customized_ip + axis_crc_sim_1_clk_rst_generator_0_0 + 1.0 + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + clk_rst_generator + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:0d2409a5 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + axis_crc_sim_1_clk_rst_generator_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:0d2409a5 + + + + + + + clk_in + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + + true + + + + + + rst_in + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + clk + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + rst_n + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + stop_simulation + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + + + CLOCK_PERIOD + Clock Period + 10000 + + + HAS_CLK_INPUT + Has Clk Input + true + + + HAS_RESET_INPUT + Has Reset Input + true + + + HAS_STOP_INPUT + Has Stop Input + true + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_clk_rst_generator_0_0.vhd + vhdlSource + xil_defaultlib + + + + clk_rst_generator + + + CLOCK_PERIOD + Clock Period [ps] + 10000 + + + HAS_CLK_INPUT + Clock Input + true + + + HAS_RESET_INPUT + Reset Input + true + + + HAS_STOP_INPUT + Stop Input + true + + + Component_Name + axis_crc_sim_1_clk_rst_generator_0_0 + + + + + clk_rst_generator + package_project + 7 + + + 2023.1 + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/sim/axis_crc_sim_1_clk_rst_generator_0_0.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/sim/axis_crc_sim_1_clk_rst_generator_0_0.vhd new file mode 100644 index 0000000..c0cf252 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/sim/axis_crc_sim_1_clk_rst_generator_0_0.vhd @@ -0,0 +1,99 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: wg:user:clk_rst_generator:1.0 +-- IP Revision: 7 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY axis_crc_sim_1_clk_rst_generator_0_0 IS + PORT ( + clk_in : IN STD_LOGIC; + rst_in : IN STD_LOGIC; + clk : OUT STD_LOGIC; + rst_n : OUT STD_LOGIC; + stop_simulation : IN STD_LOGIC + ); +END axis_crc_sim_1_clk_rst_generator_0_0; + +ARCHITECTURE axis_crc_sim_1_clk_rst_generator_0_0_arch OF axis_crc_sim_1_clk_rst_generator_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT clk_rst_generator IS + GENERIC ( + CLOCK_PERIOD : INTEGER; + HAS_CLK_INPUT : BOOLEAN; + HAS_RESET_INPUT : BOOLEAN; + HAS_STOP_INPUT : BOOLEAN + ); + PORT ( + clk_in : IN STD_LOGIC; + rst_in : IN STD_LOGIC; + clk : OUT STD_LOGIC; + rst_n : OUT STD_LOGIC; + stop_simulation : IN STD_LOGIC + ); + END COMPONENT clk_rst_generator; +BEGIN + U0 : clk_rst_generator + GENERIC MAP ( + CLOCK_PERIOD => 10000, + HAS_CLK_INPUT => true, + HAS_RESET_INPUT => true, + HAS_STOP_INPUT => true + ) + PORT MAP ( + clk_in => clk_in, + rst_in => rst_in, + clk => clk, + rst_n => rst_n, + stop_simulation => stop_simulation + ); +END axis_crc_sim_1_clk_rst_generator_0_0_arch; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xml new file mode 100644 index 0000000..6a9522f --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xml @@ -0,0 +1,205 @@ + + + xilinx.com + customized_ip + axis_crc_sim_1_xlconstant_0_0 + 1.0 + + + + xilinx_systemcsimulation + SystemC Simulation + systemCSource:vivado.xilinx.com:simulation + systemc + xlconstant_v1_1_7 + + xilinx_systemcsimulation_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:d9490f21 + + + sim_type + tlm + + + + + xilinx_systemcsimulationwrapper + SystemC Simulation Wrapper + systemCSource:vivado.xilinx.com:simulation.wrapper + systemc + axis_crc_sim_1_xlconstant_0_0 + + xilinx_systemcsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:d9490f21 + + + sim_type + tlm + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:d9490f21 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + axis_crc_sim_1_xlconstant_0_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:d9490f21 + + + + + + + dout + + out + + 31 + 0 + + + + std_logic_vector + xilinx_verilogbehavioralsimulation + + + + + + + + CONST_WIDTH + Const Width + 32 + + + CONST_VAL + Const Val + 0x00000001 + + + + + + xilinx_systemcsimulation_view_fileset + + sim/xlconstant_v1_1_7.h + systemCSource + true + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_xlconstant_0_0.h + systemCSource + true + + + sim/axis_crc_sim_1_xlconstant_0_0.cpp + systemCSource + + + sim/axis_crc_sim_1_xlconstant_0_0_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + xlconstant_v1_1_7 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_xlconstant_0_0.v + verilogSource + xil_defaultlib + + + + Gives a constant signed value. + + + Component_Name + axis_crc_sim_1_xlconstant_0_0 + + + CONST_WIDTH + Const Width + 32 + + + CONST_VAL + Const Val + 1 + + + + + Constant + 7 + + + + + + 2023.1 + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0.h b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0.h new file mode 100644 index 0000000..c895b8e --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _axis_crc_sim_1_xlconstant_0_0_H_ +#define _axis_crc_sim_1_xlconstant_0_0_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class axis_crc_sim_1_xlconstant_0_0 : public sc_module { + public: +xlconstant_v1_1_7<32,1> mod; + sc_out< sc_bv<32> > dout; +axis_crc_sim_1_xlconstant_0_0 (sc_core::sc_module_name name); + }; + +#endif diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0.v new file mode 100644 index 0000000..d477c6d --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0.v @@ -0,0 +1,68 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module axis_crc_sim_1_xlconstant_0_0 ( + dout +); + +output wire [31 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(32), + .CONST_VAL(32'H00000001) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0_stub.sv b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0_stub.sv new file mode 100644 index 0000000..b9bc377 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/axis_crc_sim_1_xlconstant_0_0_stub.sv @@ -0,0 +1,79 @@ +// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +//------------------------------------------------------------------------------------ +// Filename: xl_Constant_stub.sv +// Description: This HDL file is intended to be used with following simulators only: +// +// Vivado Simulator (XSim) +// Cadence Xcelium Simulator +// +//------------------------------------------------------------------------------------ +`ifdef XILINX_SIMULATOR +`ifndef XILINX_SIMULATOR_BITASBOOL +`define XILINX_SIMULATOR_BITASBOOL +typedef bit bit_as_bool; +`endif + +(* SC_MODULE_EXPORT *) +module axis_crc_sim_1_xlconstant_0_0 ( + output bit [31 : 0 ] dout +); +endmodule +`endif + +`ifdef XCELIUM +(* XMSC_MODULE_EXPORT *) +module axis_crc_sim_1_xlconstant_0_0 (dout) +(* integer foreign = "SystemC"; +*); + output wire [31 : 0 ] dout; +endmodule +`endif + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h new file mode 100644 index 0000000..653886b --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _xlconstant_v1_1_7_H_ +#define _xlconstant_v1_1_7_H_ + +#include "systemc.h" +template +SC_MODULE(xlconstant_v1_1_7) { + public: + sc_out< sc_bv > dout; + void init() { + dout.write(CONST_VAL); + } + SC_CTOR(xlconstant_v1_1_7) { + SC_METHOD(init); + } +}; + +#endif diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xml new file mode 100644 index 0000000..7481c11 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xml @@ -0,0 +1,205 @@ + + + xilinx.com + customized_ip + axis_crc_sim_1_xlconstant_1_0 + 1.0 + + + + xilinx_systemcsimulation + SystemC Simulation + systemCSource:vivado.xilinx.com:simulation + systemc + xlconstant_v1_1_7 + + xilinx_systemcsimulation_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:9db2c4a2 + + + sim_type + tlm + + + + + xilinx_systemcsimulationwrapper + SystemC Simulation Wrapper + systemCSource:vivado.xilinx.com:simulation.wrapper + systemc + axis_crc_sim_1_xlconstant_1_0 + + xilinx_systemcsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:9db2c4a2 + + + sim_type + tlm + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:9db2c4a2 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + axis_crc_sim_1_xlconstant_1_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Jan 31 17:33:27 UTC 2025 + + + outputProductCRC + 9:9db2c4a2 + + + + + + + dout + + out + + 31 + 0 + + + + std_logic_vector + xilinx_verilogbehavioralsimulation + + + + + + + + CONST_WIDTH + Const Width + 32 + + + CONST_VAL + Const Val + 0x00000001 + + + + + + xilinx_systemcsimulation_view_fileset + + sim/xlconstant_v1_1_7.h + systemCSource + true + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_xlconstant_1_0.h + systemCSource + true + + + sim/axis_crc_sim_1_xlconstant_1_0.cpp + systemCSource + + + sim/axis_crc_sim_1_xlconstant_1_0_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + xlconstant_v1_1_7 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axis_crc_sim_1_xlconstant_1_0.v + verilogSource + xil_defaultlib + + + + Gives a constant signed value. + + + Component_Name + axis_crc_sim_1_xlconstant_1_0 + + + CONST_WIDTH + Const Width + 32 + + + CONST_VAL + Const Val + 1 + + + + + Constant + 7 + + + + + + 2023.1 + + + + + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0.h b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0.h new file mode 100644 index 0000000..850c44a --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _axis_crc_sim_1_xlconstant_1_0_H_ +#define _axis_crc_sim_1_xlconstant_1_0_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class axis_crc_sim_1_xlconstant_1_0 : public sc_module { + public: +xlconstant_v1_1_7<32,1> mod; + sc_out< sc_bv<32> > dout; +axis_crc_sim_1_xlconstant_1_0 (sc_core::sc_module_name name); + }; + +#endif diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0.v new file mode 100644 index 0000000..523b267 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0.v @@ -0,0 +1,68 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module axis_crc_sim_1_xlconstant_1_0 ( + dout +); + +output wire [31 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(32), + .CONST_VAL(32'H00000001) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0_stub.sv b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0_stub.sv new file mode 100644 index 0000000..b67bd1e --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/axis_crc_sim_1_xlconstant_1_0_stub.sv @@ -0,0 +1,79 @@ +// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +//------------------------------------------------------------------------------------ +// Filename: xl_Constant_stub.sv +// Description: This HDL file is intended to be used with following simulators only: +// +// Vivado Simulator (XSim) +// Cadence Xcelium Simulator +// +//------------------------------------------------------------------------------------ +`ifdef XILINX_SIMULATOR +`ifndef XILINX_SIMULATOR_BITASBOOL +`define XILINX_SIMULATOR_BITASBOOL +typedef bit bit_as_bool; +`endif + +(* SC_MODULE_EXPORT *) +module axis_crc_sim_1_xlconstant_1_0 ( + output bit [31 : 0 ] dout +); +endmodule +`endif + +`ifdef XCELIUM +(* XMSC_MODULE_EXPORT *) +module axis_crc_sim_1_xlconstant_1_0 (dout) +(* integer foreign = "SystemC"; +*); + output wire [31 : 0 ] dout; +endmodule +`endif + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/xlconstant_v1_1_7.h b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/xlconstant_v1_1_7.h new file mode 100644 index 0000000..653886b --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/sim/xlconstant_v1_1_7.h @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _xlconstant_v1_1_7_H_ +#define _xlconstant_v1_1_7_H_ + +#include "systemc.h" +template +SC_MODULE(xlconstant_v1_1_7) { + public: + sc_out< sc_bv > dout; + void init() { + dout.write(CONST_VAL); + } + SC_CTOR(xlconstant_v1_1_7) { + SC_METHOD(init); + } +}; + +#endif diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/9185/sources_1/new/axis_downsizer.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/9185/sources_1/new/axis_downsizer.vhd new file mode 100644 index 0000000..43b4bc7 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/9185/sources_1/new/axis_downsizer.vhd @@ -0,0 +1,94 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axis_downsizer is + generic + ( + WIDTH_OUT : integer := 8; + SIZE_FACTOR : integer := 2; + BIG_ENDIAN : boolean := false + ); + + port + ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + + -- AXIS SLAVE + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(WIDTH_OUT*SIZE_FACTOR-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TUSER : in std_logic; + + -- AXIS Master + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(WIDTH_OUT-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TUSER : out std_logic + ); +end; + + +architecture rtl of axis_downsizer is + type T_STATE is (BYTE0,BYTE1); + signal state : T_STATE := BYTE0; + signal last : std_logic; + signal data : std_logic_vector(WIDTH_OUT*SIZE_FACTOR-1 downto 0); + signal ui : unsigned(5 downto 0); +begin + S_AXIS_TREADY <= M_AXIS_TREADY when state = BYTE0 else '0'; + M_AXIS_TVALID <= S_AXIS_TVALID when state = BYTE0 else '1'; + M_AXIS_TLAST <= last when ui = to_unsigned(SIZE_FACTOR-1,6) else '0'; + M_AXIS_TUSER <= S_AXIS_TUSER when state = BYTE0 else '0'; + + + process (S_AXIS_TDATA, ui) + variable i: integer; + begin + i := to_integer(ui); + if BIG_ENDIAN then + if ui = 0 then + M_AXIS_TDATA <= S_AXIS_TDATA(WIDTH_OUT*SIZE_FACTOR-1 downto WIDTH_OUT*(SIZE_FACTOR-1)); + else + M_AXIS_TDATA <= data(WIDTH_OUT*(SIZE_FACTOR-i)-1 downto WIDTH_OUT*(SIZE_FACTOR-i-1)); + end if; + else + if ui = 0 then + M_AXIS_TDATA <= S_AXIS_TDATA(WIDTH_OUT-1 downto 0); + else + M_AXIS_TDATA <= data(WIDTH_OUT*(i+1)-1 downto WIDTH_OUT*i); + end if; + end if; + end process; + + process + begin + wait until rising_edge (AXIS_ACLK); + if AXIS_ARESETN = '0' then + state <= BYTE0; + else + case state is + when BYTE0 => + if S_AXIS_TVALID = '1' and M_AXIS_TREADY='1' then + last <= S_AXIS_TLAST; + data <= S_AXIS_TDATA; + ui <= to_unsigned(1,6); + state <= BYTE1; + end if; + when BYTE1 => + if M_AXIS_TREADY='1' then + if ui >= SIZE_FACTOR-1 then + state <= BYTE0; + ui <= to_unsigned(0,6); + else + ui <= ui+1; + end if; + end if; + end case; + end if; + end process; + +end; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd new file mode 100644 index 0000000..5a4bb56 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd @@ -0,0 +1,114 @@ +------------------------------------------------------------------------------ +-- clk_rst_generator.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2024 +---------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity clk_rst_generator is + generic + ( + CLOCK_PERIOD : integer := 10000; + HAS_CLK_INPUT : boolean := true; + HAS_RESET_INPUT : boolean := true; + HAS_STOP_INPUT : boolean := true + ); + port + ( + clk_in : in std_logic := '1'; + rst_in : in std_logic := '0'; + + clk : out std_logic; + rst_n : out std_logic; + + stop_simulation : in std_logic := '0' + ); + +end; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture rtl of clk_rst_generator is + + signal clk_sim : std_logic := '1'; + signal clk_in_sig : std_logic := '1'; + signal clk_sig : std_logic := '1'; + signal rst_sig : std_logic := '0'; + signal rst_in_sync : std_logic := '0'; + +begin + clk <= clk_sig; + rst_n <= not rst_sig; + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- CLOCK GENERATION + --------------------------------------------------------------- + --------------------------------------------------------------- + + clk_sig <= clk_in_sig and clk_sim; + -- Dies ist kein gated Clock! + -- Fuer die Synthese ist clk_sim konstant '1' + -- somit wird die UND-Verknuepfung 'wegoptimiert' + -- und was übrig bleibt, ist ein 'Draht' + + -- synthesis translate_off + clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2; + assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note; + assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note; + assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note; + -- synthesis translate_on + + process (clk_in) begin + clk_in_sig <= clk_in; + -- synthesis translate_off + clk_in_sig <= '1'; + -- synthesis translate_on + end process; + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- RESET GENERATION + --------------------------------------------------------------- + --------------------------------------------------------------- + + process + variable rescnt : unsigned (6 downto 0) := (others=>'1'); + begin + wait until rising_edge(clk_sig); + + rst_in_sync <= rst_in; + if rst_in_sync = '1' then + rescnt := (others=>'1'); + end if; + + if rescnt = 0 then + rst_sig <= '0'; + else + rescnt := rescnt - 1; + rst_sig <= '1'; + end if; + end process; + + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- STOP SIMULATION INPUT (simulation only) + --------------------------------------------------------------- + --------------------------------------------------------------- + + -- synthesis translate_off + process (stop_simulation) begin + if stop_simulation = '1' then + assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure; + end if; + end process; + -- synthesis translate_on + +end rtl; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v new file mode 100644 index 0000000..51977ac --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v @@ -0,0 +1,31 @@ +//------------------------------------------------------------------------ +//-- +//-- Filename : xlconstant.v +//-- +//-- Date : 06/05/12 +//-- +//-- Description : VERILOG description of a constant block. This +//-- block does not use a core. +//-- +//------------------------------------------------------------------------ + + +//------------------------------------------------------------------------ +//-- +//-- Module : xlconstant +//-- +//-- Architecture : behavior +//-- +//-- Description : Top level VERILOG description of constant block +//-- +//------------------------------------------------------------------------ +`timescale 1ps/1ps +module xlconstant_v1_1_7_xlconstant (dout); + parameter CONST_VAL = 1; + parameter CONST_WIDTH = 1; + output [CONST_WIDTH-1:0] dout; + + assign dout = CONST_VAL; +endmodule + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/c453/axis_slave_simmodel.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/c453/axis_slave_simmodel.vhd new file mode 100644 index 0000000..43fac51 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/c453/axis_slave_simmodel.vhd @@ -0,0 +1,317 @@ +------------------------------------------------------------------------------ +-- axis_slave_simmodel.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2013 +---------------------------------------------------------- + +use std.textio.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.bmp_pkg.all; + + +entity axis_slave_simmodel is + generic + ( + TUSERWIDTH : integer := 1; + FILE_NAME : string := string'("tst_out"); + FILE_EXTENSION : string := string'("bmp"); + FILE_AUTONUMBERING : boolean := false; + PIXEL_FORMAT : integer := 1; + NUM_PIX_PER_LINE : integer := 128; + NUM_LINES : integer := 128; + NUM_FRAMES_PER_FILE : integer := 1; + NUM_FILES : integer := 1; + FRAMING_PIXELS : integer := 0; + FRAMING_LINES : integer := 0; + RANDOM_TREADY : boolean := true +); + port + ( + FINISHED : out std_logic; + S_AXIS_ACLK : in std_logic; + S_AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TUSER : in std_logic_vector(TUSERWIDTH-1 downto 0) + ); + +end entity axis_slave_simmodel; + + +architecture sim of axis_slave_simmodel is + + signal rnd : unsigned (31 downto 0) := x"DEADBEEF"; + signal local_clk : std_logic; + +begin + + local_clk <= S_AXIS_ACLK after 10 ps; + +-- synthesis translate_off +-- translate off + + -- uint32_t xorshift32() { + -- static uint32_t x = 314159265; + -- x ^= x << 13; + -- x ^= x >> 17; + -- x ^= x << 5; + -- return x; + -- } + process + variable r : unsigned (31 downto 0); + begin + wait until rising_edge(local_clk); + r := rnd; + r := r xor (r(18 downto 0)& x"000"&"0"); + r := r xor (x"0000"&"0"&r(31 downto 17)); + r := r xor (r(26 downto 0)& "00000"); + rnd <= r; + end process; + + process + + variable file_num : integer := 0; + variable is_bmp_file: boolean; + variable is_yuv_file: boolean; + + variable r : integer; + variable g : integer; + variable b : integer; + + variable y1 : integer; + variable u1 : integer; + variable v1 : integer; + variable y2 : integer; + variable u2 : integer; + variable v2 : integer; + + variable delay_cnt : integer; + variable tready_cnt : integer := 31415; + + file f : BMP_FILE_TYPE; + + variable file_status : file_open_status; + + variable x : integer; + variable pixels_per_beat : integer; + + + type rgbyuv is record + r : integer; + g : integer; + b : integer; + y : integer; + u : integer; + v : integer; + end record; + type tarr1 is array(0 to NUM_PIX_PER_LINE-1) of rgbyuv; + type tarr2 is array(0 to NUM_LINES-1) of tarr1; + variable pix : tarr2; + + type t_pixel_data is array(0 to 3) of rgbyuv; + variable p : t_pixel_data; + + type t_raw_data is array(0 to 3) of integer; + variable raw_data : t_raw_data; + + begin + wait until rising_edge(local_clk); + if (S_AXIS_ARESETN = '0') then + S_AXIS_TREADY <= '0'; + FINISHED <= '0'; + tready_cnt := to_integer(rnd and x"0000001F"); + else + S_AXIS_TREADY <= '1'; + + -- Check if output file is in BMP format + is_bmp_file := false; + is_yuv_file := false; + if (FILE_EXTENSION = "BMP") or (FILE_EXTENSION = "bmp") then + is_bmp_file := true; + elsif (FILE_EXTENSION = "YUV") or (FILE_EXTENSION = "yuv") then + is_yuv_file := true; + end if; + + case PIXEL_FORMAT is + when 0 => pixels_per_beat := 2; + when 1|5 => pixels_per_beat := 1; + when 2|6 => pixels_per_beat := 1; + when 12 => pixels_per_beat := 1; + when 13 => pixels_per_beat := 4; + when others => pixels_per_beat := 4; + end case; + + + for files in 0 to NUM_FILES-1 loop -- file loop + + -- Create filename and try to open the file + if FILE_AUTONUMBERING then + file_open ( file_status, f, FILE_NAME & "_" & integer'image(file_num) & "." & FILE_EXTENSION, write_mode); + else + file_open ( file_status, f, FILE_NAME & "." & FILE_EXTENSION, write_mode); + end if; + + file_num := file_num + 1; -- increase filenum idx + if is_bmp_file then + write_bmp_header(NUM_PIX_PER_LINE,NUM_LINES,f); + end if; + + for fr in 0 to NUM_FRAMES_PER_FILE-1 loop -- frame loop + + -- wait for start of frame + while S_AXIS_TVALID /= '1' or S_AXIS_TUSER(0) /= '1' loop + wait until rising_edge (local_clk); + end loop; + + for y in 0 to NUM_LINES+2*FRAMING_LINES-1 loop + x := 0; + while x < NUM_PIX_PER_LINE+2*FRAMING_PIXELS loop + + -- wait for valid data + while S_AXIS_TVALID /= '1' loop + wait until rising_edge (local_clk); + end loop; + + -- "active" pixel area ? + if (y >= FRAMING_LINES) and (y < FRAMING_LINES+NUM_LINES) and + (x >= FRAMING_PIXELS) and (x < FRAMING_PIXELS+NUM_PIX_PER_LINE) then + + if is_bmp_file or is_yuv_file then -- bmp format or yuv format ? + case PIXEL_FORMAT is + when 0 => + p(1).y := to_integer(unsigned(S_AXIS_TDATA(31 downto 24))); + p(1).v := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(0).v := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(0).y := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(1).u := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + p(0).u := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b); + yuv2rgb(p(1).y,p(1).u,p(1).v,p(1).r,p(1).g,p(1).b); + when 1|5 => + p(0).v := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(0).u := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b); + when 2|6 => + p(0).r := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(0).b := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(0).g := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + rgb2yuv(p(0).r,p(0).g,p(0).b,p(0).y,p(0).u,p(0).v); + when 12 => + p(0).v := 128; + p(0).u := 128; + p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b); + when 13 => + p(3).y := to_integer(unsigned(S_AXIS_TDATA(31 downto 24))); + p(3).v := 128; + p(3).u := 128; + p(2).y := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(2).v := 128; + p(2).u := 128; + p(1).y := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(1).v := 128; + p(1).u := 128; + p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + p(0).v := 128; + p(0).u := 128; + yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b); + yuv2rgb(p(1).y,p(1).u,p(1).v,p(1).r,p(1).g,p(1).b); + yuv2rgb(p(2).y,p(2).u,p(2).v,p(2).r,p(2).g,p(2).b); + yuv2rgb(p(3).y,p(3).u,p(3).v,p(3).r,p(3).g,p(3).b); + when others => + p(3).y := to_integer(unsigned(S_AXIS_TDATA(31 downto 24))); + p(3).v := 128; + p(3).u := 128; + p(2).y := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(2).v := 128; + p(2).u := 128; + p(1).y := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(1).v := 128; + p(1).u := 128; + p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + p(0).v := 128; + p(0).u := 128; + end case; + else -- raw format + raw_data(3) := to_integer(unsigned(S_AXIS_TDATA(31 downto 24))); + raw_data(2) := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + raw_data(1) := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + raw_data(0) := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + end if; + + if is_bmp_file or is_yuv_file then -- bmp format or yuv format ? + for xi in 0 to pixels_per_beat-1 loop + pix(y-FRAMING_LINES)(x+xi-FRAMING_PIXELS) := p(xi); + end loop; + x := x+pixels_per_beat; + else + bmpput8(raw_data(0),f); + bmpput8(raw_data(1),f); + bmpput8(raw_data(2),f); + bmpput8(raw_data(3),f); + end if; + end if; + + tready_cnt := tready_cnt - 1; + if RANDOM_TREADY and tready_cnt <= 0 then + -- random TREADY delay + delay_cnt := to_integer(rnd and x"00000007"); + while delay_cnt > 0 loop + S_AXIS_TREADY <= '0'; + delay_cnt := delay_cnt - 1; + wait until rising_edge (local_clk); + tready_cnt := to_integer(rnd and x"0000001F"); + end loop; + end if; + + S_AXIS_TREADY <= '1'; + wait until rising_edge (local_clk); + + end loop; -- hor loop (x) + end loop; -- ver loop (y) + if is_bmp_file then -- bmp format ? + for y in NUM_LINES-1 downto 0 loop + for x in 0 to NUM_PIX_PER_LINE-1 loop + write_bmp_pixel(pix(y)(x).r,pix(y)(x).g,pix(y)(x).b,f); + end loop; + end loop; + end if; + if is_bmp_file then -- yuv format ? + for y in NUM_LINES-1 downto 0 loop + for x in 0 to NUM_PIX_PER_LINE/2-1 loop + bmpput8(pix(y)(2*x).u,f); + bmpput8(pix(y)(2*x).y,f); + bmpput8(pix(y)(2*x).v,f); + bmpput8(pix(y)(2*x+1).y,f); + end loop; + end loop; + end if; + end loop; -- frame loop (fr) + file_close(f); + end loop; -- files loop (files) + + + FINISHED <= '1'; + S_AXIS_TREADY <= '0'; + + -- wait until reset is activated + while S_AXIS_ARESETN = '1' loop + wait until rising_edge (local_clk); + end loop; + + end if; + end process; + +-- synthesis translate_on +-- translate on + + +end sim; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/c453/bmp_pkg.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/c453/bmp_pkg.vhd new file mode 100644 index 0000000..b3afae7 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/c453/bmp_pkg.vhd @@ -0,0 +1,207 @@ + +use std.textio.all; + +package bmp_pkg is + + type BMP_FILE_TYPE is file of character; + + procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ); + procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ); + procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ); + procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ); + procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ); + + function bmpget8 (file f : BMP_FILE_TYPE ) return integer; + function bmpget16 (file f : BMP_FILE_TYPE ) return integer; + function bmpget32 (file f : BMP_FILE_TYPE ) return integer; + procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ); + procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ); + procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ); + procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ); + procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ); + +end; + +package body bmp_pkg is + +procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + write(f, character'val(value)); +end bmpput8; + +procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8((value) mod 256,f); + bmpput8((value/256) mod 256,f); +end bmpput16; + +procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8((value) mod 256,f); + bmpput8((value/256) mod 256,f); + bmpput8((value/256/256) mod 256,f); + bmpput8((value/256/256/256) mod 256,f); +end bmpput32; + + +procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ) is +begin + write(f,'B'); + write(f,'M'); + bmpput32(54+sizex*sizey*3,f); -- bfSize : size of file (unsave) + bmpput32( 0, f); -- bfReserved : always 0 + bmpput32(54, f); -- bfOffBits : image data offset (=54) + bmpput32(40, f); -- biSize : header size (=40) + bmpput32(sizex,f); -- biWidth : num horizontal pixel + bmpput32(sizey,f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap) + bmpput16( 1, f); -- biPlanes : num bitplanes, always 1 + bmpput16(24, f); -- biBitCount : bpp + bmpput32( 0, f); -- biCompression : compression (0: uncompressed) + bmpput32(3*sizex*sizey,f); -- biSizeImage : if uncompressed: image size or 0 + bmpput32( 0, f); -- biXPelsPerMeter : hor resolution + bmpput32( 0, f); -- biYPelsPerMeter : ver resolution + bmpput32( 0, f); -- biClrUsed : for supported format always 0 + bmpput32( 0, f); -- biClrImportant : no color table => 0 + +end write_bmp_header; + +procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8(b,f); + bmpput8(g,f); + bmpput8(r,f); +end write_bmp_pixel; + + +function bmpget8 (file f : BMP_FILE_TYPE ) return integer is + variable chr : character; +begin + read (f,chr); + return character'pos(chr); +end bmpget8; + +function bmpget16 (file f : BMP_FILE_TYPE ) return integer is + variable value : integer; +begin + value := bmpget8(f); + value := value + bmpget8(f)*256; + return value; +end bmpget16; + +function bmpget32 (file f : BMP_FILE_TYPE ) return integer is + variable value : integer; +begin + value := bmpget8(f); + value := value + bmpget8(f)*256; + value := value + bmpget8(f)*256*256; + value := value + bmpget8(f)*256*256*256; + return value; +end bmpget32; + +procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ) is + variable chr : character; + variable val : integer; +begin + success := true; + read (f,chr); + if chr /= 'B' then success := false; end if; + read (f,chr); + if chr /= 'M' then success := false; end if; + val := bmpget32(f); -- bfSize : size of file (unsave) + val := bmpget32(f); -- bfReserved : always 0 + if val /= 0 then success := false; end if; + val := bmpget32(f); -- bfOffBits : image data offset + val := bmpget32(f); -- biSize : header size (=40) + if val /= 40 then success := false; end if; + sizex := bmpget32(f); -- biWidth : num horizontal pixel + sizey := bmpget32(f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap) + val := bmpget16(f); -- biPlanes : num bitplanes, always 1 + if val /= 1 then success := false; end if; + val := bmpget16(f); -- biBitCount : bpp + if val /= 24 then success := false; end if; + val := bmpget32(f); -- biCompression : compression (0: uncompressed) + if val /= 0 then success := false; end if; + val := bmpget32(f); -- biSizeImage : if uncompressed: image size or 0 + val := bmpget32(f); -- biXPelsPerMeter : hor resolution + val := bmpget32(f); -- biYPelsPerMeter : ver resolution + val := bmpget32(f); -- biClrUsed : for supported format always 0 + if val /= 0 then success := false; end if; + val := bmpget32(f); -- biClrImportant : no color table => 0 + if val /= 0 then success := false; end if; +end read_bmp_header; + + +procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ) is +begin + if endfile(f) then + success := false; + else + b := bmpget8(f); + g := bmpget8(f); + r := bmpget8(f); + success := true; + end if; +end read_bmp_pixel; + +procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ) is +begin + if endfile(f) then + success := false; + else + u := bmpget8(f); + y1 := bmpget8(f); + v := bmpget8(f); + y2 := bmpget8(f); + success := true; + end if; +end read_yuv422_pixels; + +procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ) is +begin + y := INTEGER( (0.299 * REAL(r)) + (0.587 * REAL(g)) + (0.114 * REAL(b)) + 0.0 ); + u := INTEGER(-(0.169 * REAL(r)) - (0.331 * REAL(g)) + (0.500 * REAL(b)) + 128.0 ); + v := INTEGER( (0.500 * REAL(r)) - (0.419 * REAL(g)) - (0.081 * REAL(b)) + 128.0 ); + if (y>255) then + y := 255; + elsif (y<0) then + y := 0; + end if; + if (u>255) then + u := 255; + elsif (u<0) then + u := 0; + end if; + if (v>255) then + v := 255; + elsif (v<0) then + v := 0; + end if; +end rgb2yuv; + +procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ) is +begin + r := INTEGER( (1.000 * REAL(y)) + (0.000 * REAL(u-128)) + (1.400 * REAL(v-128))); + g := INTEGER( (1.000 * REAL(y)) - (0.343 * REAL(u-128)) - (0.711 * REAL(v-128))); + b := INTEGER( (1.000 * REAL(y)) + (1.765 * REAL(u-128)) - (0.000 * REAL(v-128))); + if (r>255) then + r := 255; + elsif (r<0) then + r := 0; + end if; + if (g>255) then + g := 255; + elsif (g<0) then + g := 0; + end if; + if (b>255) then + b := 255; + elsif (b<0) then + b := 0; + end if; +end yuv2rgb; + + + + + +end package body; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/d44d/axis_master_simmodel.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/d44d/axis_master_simmodel.vhd new file mode 100644 index 0000000..9215244 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/d44d/axis_master_simmodel.vhd @@ -0,0 +1,375 @@ +------------------------------------------------------------------------------ +-- axis_master_simmodel.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2013/2015 +---------------------------------------------------------- + +use std.textio.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.bmp_pkg.all; + +entity axis_master_simmodel is + generic + ( + DATA_WIDTH : integer := 32; + HAS_FIFO_INTERFACE : boolean := false; + FIFO_AWIDTH : integer := 11; + FIFO_REQUEST_TRESHOLD : integer := 32; + TUSERWIDTH : integer := 1; + FILE_NAME : string := string'("tst"); + FILE_EXTENSION : string := string'("bmp"); + FILE_AUTONUMBERING : boolean := false; + NUM_PIX_PER_LINE : integer := 32; + NUM_LINES : integer := 32; + NUM_FRAMES_PER_FILE : integer := 1; + RANDOM_TVALID : boolean := true; + PIXEL_FORMAT : integer := 1; + ALPHA_VALUE : integer := 255; + FRAMING_PIXELS : integer := 0; + FRAMING_LINES : integer := 0; + FRAMING_VAL_R_V : integer := 128; + FRAMING_VAL_G_Y : integer := 128; + FRAMING_VAL_B_U : integer := 128 + ); + port + ( + ACLK : in std_logic; + ARESETN : in std_logic; + FINISHED : out std_logic; + + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(DATA_WIDTH-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TUSER : out std_logic_vector(TUSERWIDTH-1 downto 0); + M_AXIS_NUM_FREE : in std_logic_vector(FIFO_AWIDTH-1 downto 0) := (others=>'1') -- Number of free entries in target + ); + + +end entity axis_master_simmodel; + + +architecture sim of axis_master_simmodel is + + signal rnd : unsigned (31 downto 0) := x"ABBAABBA"; + signal local_clk : std_logic; + +begin + +-- synthesis translate_off +-- translate off + + local_clk <= ACLK; + + -- uint32_t xorshift32() { + -- static uint32_t x = 314159265; + -- x ^= x << 13; + -- x ^= x >> 17; + -- x ^= x << 5; + -- return x; + -- } + process + variable r : unsigned (31 downto 0); + begin + wait until rising_edge(local_clk); + r := rnd; + r := r xor (r(18 downto 0)& x"000"&"0"); + r := r xor (x"0000"&"0"&r(31 downto 17)); + r := r xor (r(26 downto 0)& "00000"); + rnd <= r; + end process; + + + process + + variable file_num : integer := 0; + variable is_bmp_file: boolean; + variable is_yuv_file: boolean; + + variable r : integer; + variable g : integer; + variable b : integer; + + variable y1 : integer; + variable u1 : integer; + variable v1 : integer; + variable y2 : integer; + variable u2 : integer; + variable v2 : integer; + + variable sizex : integer; + variable sizey : integer; + + variable delay_cnt : integer; + variable tvalid_cnt : integer := 31415; + + variable ok : boolean; + + file f : BMP_FILE_TYPE; + + variable file_status : file_open_status; + + + variable x : integer; + variable pixels_per_beat : integer; + + + type rgbyuv is record + r : integer; + g : integer; + b : integer; + y : integer; + u : integer; + v : integer; + end record; + type tarr1 is array(0 to NUM_PIX_PER_LINE-1) of rgbyuv; + type tarr2 is array(0 to NUM_LINES-1) of tarr1; + variable pix : tarr2; + + type t_pixel_data is array(0 to 3) of rgbyuv; + variable p : t_pixel_data; + + type t_raw_data is array(0 to 3) of integer; + variable raw_data : t_raw_data; + + begin + + wait until rising_edge (local_clk); + if (ARESETN = '0') then + M_AXIS_TVALID <= '0'; + M_AXIS_TDATA <= (others=>'0'); + M_AXIS_TLAST <= '0'; + M_AXIS_TUSER <= (others=>'0'); + FINISHED <= '0'; + file_num := 0; + tvalid_cnt := to_integer(rnd and x"0000001F"); + else + M_AXIS_TLAST <= '0'; + M_AXIS_TVALID <= '0'; + M_AXIS_TUSER <= (others=>'0'); + FINISHED <= '0'; + + -- Start-Up delay + for i in 0 to 100 loop + wait until rising_edge (local_clk); + end loop; + + -- Send dummy data in front of the frame to chen + M_AXIS_TVALID <= '1'; + M_AXIS_TDATA <= (others=>'0'); + M_AXIS_TLAST <= '0'; + M_AXIS_TUSER <= (others=>'0'); + + for i in 0 to 5000 loop + wait until rising_edge (local_clk); + end loop; + + M_AXIS_TVALID <= '0'; + + + -- Check if input file is in BMP format + is_bmp_file := false; + is_yuv_file := false; + if (FILE_EXTENSION = "BMP") or (FILE_EXTENSION = "bmp") then + is_bmp_file := true; + elsif (FILE_EXTENSION = "YUV") or (FILE_EXTENSION = "yuv") then + is_yuv_file := true; + end if; + + file_status := open_ok; + + while file_status = open_ok loop + -- Create filename and try to open the file + if FILE_AUTONUMBERING then + file_open ( file_status, f, FILE_NAME & "_" & integer'image(file_num) & "." & FILE_EXTENSION, read_mode); + else + file_open ( file_status, f, FILE_NAME & "." & FILE_EXTENSION, read_mode); + end if; + + -- File open succeeded ? + if file_status = open_ok then + file_num := file_num + 1; -- increase filenum idx + if is_bmp_file then + read_bmp_header(ok,sizex,sizey,f); + if sizey < 0 then + sizey := -sizey; + end if; + else + sizex := NUM_PIX_PER_LINE; + sizey := NUM_LINES; + ok := true; + end if; + + if ok then + for fr in 0 to NUM_FRAMES_PER_FILE-1 loop -- frame loop + M_AXIS_TUSER(0) <= '1'; -- start of frame + + if is_bmp_file then -- bmp format ? + for y in NUM_LINES-1 downto 0 loop + for x in 0 to NUM_PIX_PER_LINE-1 loop + read_bmp_pixel(ok,pix(y)(x).r,pix(y)(x).g,pix(y)(x).b,f); + rgb2yuv(pix(y)(x).r,pix(y)(x).g,pix(y)(x).b,pix(y)(x).y,pix(y)(x).u,pix(y)(x).v); + end loop; + end loop; + end if; + + if is_yuv_file then -- yuv format (YUV422) ? + for y in NUM_LINES-1 downto 0 loop + for x in 0 to NUM_PIX_PER_LINE/2-1 loop + read_yuv422_pixels(ok,pix(y)(x).y,pix(y)(x+1).y,pix(y)(x).u,pix(y)(x).v,f); + pix(y)(x+1).u := pix(y)(x).u; + pix(y)(x+1).v := pix(y)(x).v; + yuv2rgb(pix(y)(x).y,pix(y)(x).u,pix(y)(x).v,pix(y)(x).r,pix(y)(x).g,pix(y)(x).b); + yuv2rgb(pix(y)(x+1).y,pix(y)(x+1).u,pix(y)(x+1).v,pix(y)(x+1).r,pix(y)(x+1).g,pix(y)(x+1).b); + end loop; + end loop; + end if; + + if DATA_WIDTH = 32 then + case PIXEL_FORMAT is + when 0 => pixels_per_beat := 2; + when 1|5 => pixels_per_beat := 1; + when 2|6 => pixels_per_beat := 1; + when 12 => pixels_per_beat := 1; + when 13 => pixels_per_beat := 4; + when others => pixels_per_beat := 4; + end case; + else + pixels_per_beat := 1; + end if; + + for y in 0 to (sizey+2*FRAMING_LINES)-1 loop -- line loop + x := 0; + while x<(sizex+2*FRAMING_PIXELS) loop + if (y >= FRAMING_LINES) and (y < FRAMING_LINES+sizey) and + (x >= FRAMING_PIXELS) and (x < FRAMING_PIXELS+sizex) then + -- "active" pixel area + if is_bmp_file or is_yuv_file then -- bmp_format or yuv format ? + p(0) := pix(y-FRAMING_LINES)(x-FRAMING_PIXELS); + if pixels_per_beat > 1 then + p(1) := pix(y-FRAMING_LINES)(x+1-FRAMING_PIXELS); + end if; + if pixels_per_beat > 2 then + p(2) := pix(y-FRAMING_LINES)(x+2-FRAMING_PIXELS); + end if; + if pixels_per_beat > 3 then + p(3) := pix(y-FRAMING_LINES)(x+3-FRAMING_PIXELS); + end if; + else + raw_data(0) := bmpget8(f); + if DATA_WIDTH = 32 then + raw_data(1) := bmpget8(f); + raw_data(2) := bmpget8(f); + raw_data(3) := bmpget8(f); + end if; + end if; + else + -- "framing" area + p(0).r := FRAMING_VAL_R_V; + p(0).g := FRAMING_VAL_G_Y; + p(0).b := FRAMING_VAL_B_U; + p(0).v := FRAMING_VAL_R_V; + p(0).y := FRAMING_VAL_G_Y; + p(0).u := FRAMING_VAL_B_U; + p(1) := p(0); + p(2) := p(0); + p(3) := p(0); + end if; + + -- wait until receiving FIFO has sufficient space + -- if FIFO_REQUEST_TRESHOLD equals 0, this function is disabled + if HAS_FIFO_INTERFACE then + while FIFO_REQUEST_TRESHOLD /= 0 and to_integer(unsigned(M_AXIS_NUM_FREE)) < FIFO_REQUEST_TRESHOLD loop + wait until rising_edge (local_clk); + end loop; + end if; + + -- output data, valid and last + + if is_bmp_file or is_yuv_file then -- bmp format or yuv format ? + if DATA_WIDTH = 32 then + case PIXEL_FORMAT is + when 0 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(1).y,8)&to_unsigned((p(1).v+p(0).v)/2,8)&to_unsigned(p(0).y,8)&to_unsigned((p(1).u+p(0).u)/2,8)); + when 1|5 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(ALPHA_VALUE,8)&to_unsigned(p(0).v,8)&to_unsigned(p(0).u,8)&to_unsigned(p(0).y,8)); + when 2|6 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(ALPHA_VALUE,8)&to_unsigned(p(0).r,8)&to_unsigned(p(0).b,8)&to_unsigned(p(0).g,8)); + when 12 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(ALPHA_VALUE,8)&to_unsigned(128,8)&to_unsigned(128,8)&to_unsigned(p(0).y,8)); + when 13 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(3).y,8)&to_unsigned(p(2).y,8)&to_unsigned(p(1).y,8)&to_unsigned(p(0).y,8)); + when others => M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(3).y,8)&to_unsigned(p(2).y,8)&to_unsigned(p(1).y,8)&to_unsigned(p(0).y,8)); + end case; + else + M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(0).y,8)); + end if; + else -- raw format + if DATA_WIDTH = 32 then + M_AXIS_TDATA <= std_logic_vector(to_unsigned(raw_data(3),8)&to_unsigned(raw_data(2),8)&to_unsigned(raw_data(1),8)&to_unsigned(raw_data(0),8)); + else + M_AXIS_TDATA <= std_logic_vector(to_unsigned(raw_data(0),8)); + end if; + end if; + + M_AXIS_TVALID <= '1'; + if x = (sizex+2*FRAMING_PIXELS)-pixels_per_beat then + M_AXIS_TLAST <= '1'; + else + M_AXIS_TLAST <= '0'; + end if; + + -- wait until data has been acknowledged + wait until rising_edge (local_clk); + while M_AXIS_TREADY = '0' loop + wait until rising_edge (local_clk); + end loop; + + M_AXIS_TUSER(0) <= '0'; + + tvalid_cnt := tvalid_cnt - 1; + if RANDOM_TVALID and tvalid_cnt <= 0 then + -- random TVALID delay + delay_cnt := to_integer(rnd and x"00000007"); + while delay_cnt > 0 loop + M_AXIS_TVALID <= '0'; + delay_cnt := delay_cnt - 1; + wait until rising_edge (local_clk); + tvalid_cnt := to_integer(rnd and x"0000001F"); + end loop; + M_AXIS_TVALID <= '1'; + end if; + + x := x + pixels_per_beat; + + end loop; -- pixel loop + end loop; -- line loop + end loop; -- frame loop + file_close(f); + end if; -- if ok + end if; -- if open_status ok + end loop; + + FINISHED <= '1'; + M_AXIS_TLAST <= '0'; + M_AXIS_TVALID <= '1'; + M_AXIS_TUSER <= (others=>'0'); + if DATA_WIDTH = 32 then + M_AXIS_TDATA <= x"80808080"; + else + M_AXIS_TDATA <= x"80"; + end if; + + -- wait until reset is activated + while ARESETN = '1' loop + wait until rising_edge (local_clk); + end loop; + + end if; + end process; + +-- synthesis translate_on +-- translate on + + +end sim; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/d44d/bmp_pkg.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/d44d/bmp_pkg.vhd new file mode 100644 index 0000000..16857b4 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/d44d/bmp_pkg.vhd @@ -0,0 +1,208 @@ + +use std.textio.all; + +package bmp_pkg is + + type BMP_FILE_TYPE is file of character; + + procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ); + procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ); + procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ); + procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ); + procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ); + + function bmpget8 (file f : BMP_FILE_TYPE ) return integer; + function bmpget16 (file f : BMP_FILE_TYPE ) return integer; + function bmpget32 (file f : BMP_FILE_TYPE ) return integer; + procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ); + procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ); + procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ); + procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ); + procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ); + +end; + +package body bmp_pkg is + +procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + write(f, character'val(value)); +end bmpput8; + +procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8((value) mod 256,f); + bmpput8((value/256) mod 256,f); +end bmpput16; + +procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8((value) mod 256,f); + bmpput8((value/256) mod 256,f); + bmpput8((value/256/256) mod 256,f); + bmpput8((value/256/256/256) mod 256,f); +end bmpput32; + + +procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ) is +begin + write(f,'B'); + write(f,'M'); + bmpput32(54+sizex*sizey*3,f); -- bfSize : size of file (unsave) + bmpput32( 0, f); -- bfReserved : always 0 + bmpput32(54, f); -- bfOffBits : image data offset (=54) + bmpput32(40, f); -- biSize : header size (=40) + bmpput32(sizex,f); -- biWidth : num horizontal pixel + bmpput32(sizey,f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap) + bmpput16( 1, f); -- biPlanes : num bitplanes, always 1 + bmpput16(24, f); -- biBitCount : bpp + bmpput32( 0, f); -- biCompression : compression (0: uncompressed) + bmpput32(3*sizex*sizey,f); -- biSizeImage : if uncompressed: image size or 0 + bmpput32( 0, f); -- biXPelsPerMeter : hor resolution + bmpput32( 0, f); -- biYPelsPerMeter : ver resolution + bmpput32( 0, f); -- biClrUsed : for supported format always 0 + bmpput32( 0, f); -- biClrImportant : no color table => 0 + +end write_bmp_header; + +procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8(b,f); + bmpput8(g,f); + bmpput8(r,f); +end write_bmp_pixel; + + +function bmpget8 (file f : BMP_FILE_TYPE ) return integer is + variable chr : character; +begin + read (f,chr); + return character'pos(chr); +end bmpget8; + +function bmpget16 (file f : BMP_FILE_TYPE ) return integer is + variable value : integer; +begin + value := bmpget8(f); + value := value + bmpget8(f)*256; + return value; +end bmpget16; + +function bmpget32 (file f : BMP_FILE_TYPE ) return integer is + variable value : integer; +begin + value := bmpget8(f); + value := value + bmpget8(f)*256; + value := value + bmpget8(f)*256*256; + value := value + bmpget8(f)*256*256*256; + return value; +end bmpget32; + +procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ) is + variable chr : character; + variable val : integer; +begin + success := true; + read (f,chr); + if chr /= 'B' then success := false; end if; + read (f,chr); + if chr /= 'M' then success := false; end if; + val := bmpget32(f); -- bfSize : size of file (unsave) + val := bmpget32(f); -- bfReserved : always 0 + if val /= 0 then success := false; end if; + val := bmpget32(f); -- bfOffBits : image data offset + val := bmpget32(f); -- biSize : header size (=40) + if val /= 40 then success := false; end if; + sizex := bmpget32(f); -- biWidth : num horizontal pixel + sizey := bmpget32(f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap) + val := bmpget16(f); -- biPlanes : num bitplanes, always 1 + if val /= 1 then success := false; end if; + val := bmpget16(f); -- biBitCount : bpp + if val /= 24 then success := false; end if; + val := bmpget32(f); -- biCompression : compression (0: uncompressed) + if val /= 0 then success := false; end if; + val := bmpget32(f); -- biSizeImage : if uncompressed: image size or 0 + val := bmpget32(f); -- biXPelsPerMeter : hor resolution + val := bmpget32(f); -- biYPelsPerMeter : ver resolution + val := bmpget32(f); -- biClrUsed : for supported format always 0 + if val /= 0 then success := false; end if; + val := bmpget32(f); -- biClrImportant : no color table => 0 + if val /= 0 then success := false; end if; +end read_bmp_header; + + +procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ) is +begin + if endfile(f) then + success := false; + else + b := bmpget8(f); + g := bmpget8(f); + r := bmpget8(f); + success := true; + end if; +end read_bmp_pixel; + +procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ) is +begin + if endfile(f) then + success := false; + else + u := bmpget8(f); + y1 := bmpget8(f); + v := bmpget8(f); + y2 := bmpget8(f); + success := true; + end if; +end read_yuv422_pixels; + +procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ) is +begin + y := INTEGER( (0.299 * REAL(r)) + (0.587 * REAL(g)) + (0.114 * REAL(b)) + 0.0 ); + u := INTEGER(-(0.169 * REAL(r)) - (0.331 * REAL(g)) + (0.500 * REAL(b)) + 128.0 ); + v := INTEGER( (0.500 * REAL(r)) - (0.419 * REAL(g)) - (0.081 * REAL(b)) + 128.0 ); + if (y>255) then + y := 255; + elsif (y<0) then + y := 0; + end if; + if (u>255) then + u := 255; + elsif (u<0) then + u := 0; + end if; + if (v>255) then + v := 255; + elsif (v<0) then + v := 0; + end if; +end rgb2yuv; + +procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ) is +begin + r := INTEGER( (1.000 * REAL(y)) + (0.000 * REAL(u-128)) + (1.400 * REAL(v-128))); + g := INTEGER( (1.000 * REAL(y)) - (0.343 * REAL(u-128)) - (0.711 * REAL(v-128))); + b := INTEGER( (1.000 * REAL(y)) + (1.765 * REAL(u-128)) - (0.000 * REAL(v-128))); + if (r>255) then + r := 255; + elsif (r<0) then + r := 0; + end if; + if (g>255) then + g := 255; + elsif (g<0) then + g := 0; + end if; + if (b>255) then + b := 255; + elsif (b<0) then + b := 0; + end if; +end yuv2rgb; + + + + + +end package body; + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/dfd1/sources_1/new/axis_upsizer.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/dfd1/sources_1/new/axis_upsizer.vhd new file mode 100644 index 0000000..aa9f0a9 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ipshared/dfd1/sources_1/new/axis_upsizer.vhd @@ -0,0 +1,103 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axis_upsizer is + generic + ( + WIDTH_IN : integer := 8; + SIZE_FACTOR : integer := 2; + BIG_ENDIAN : boolean := false + ); + + port + ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + + -- AXIS SLAVE + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(WIDTH_IN-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TUSER : in std_logic; + + -- AXIS Master + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(WIDTH_IN*SIZE_FACTOR-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TUSER : out std_logic + ); +end; + + +architecture rtl of axis_upsizer is + type T_STATE is (BYTE0,BYTE1,BYTEF); + signal state : T_STATE := BYTE0; + signal user : std_logic; + signal data : std_logic_vector(WIDTH_IN*SIZE_FACTOR-1 downto 0); +begin + S_AXIS_TREADY <= M_AXIS_TREADY when state = BYTEF else '1'; + M_AXIS_TVALID <= S_AXIS_TVALID when state = BYTEF else '0'; + M_AXIS_TLAST <= S_AXIS_TLAST when state = BYTEF else '0'; + M_AXIS_TUSER <= user when state = BYTEF else '0'; + + process (S_AXIS_TDATA, data) + begin + if BIG_ENDIAN then + for i in 0 to SIZE_FACTOR-1 loop + M_AXIS_TDATA(WIDTH_IN*SIZE_FACTOR-1-WIDTH_IN*i downto (WIDTH_IN-1)*SIZE_FACTOR-WIDTH_IN*i) <= data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i); + end loop; + M_AXIS_TDATA(WIDTH_IN-1 downto 0) <= S_AXIS_TDATA; + + else + M_AXIS_TDATA <= S_AXIS_TDATA & data(WIDTH_IN*(SIZE_FACTOR-1)-1 downto 0); + end if; + end process; + + process + variable i : integer; + variable ui : unsigned(5 downto 0); + begin + wait until rising_edge (AXIS_ACLK); + if AXIS_ARESETN = '0' then + state <= BYTE0; + else + case state is + when BYTE0 => + if S_AXIS_TVALID = '1' then + ui := (others=>'0'); + i := to_integer(ui); + data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i) <= S_AXIS_TDATA; + user <= S_AXIS_TUSER; + if S_AXIS_TLAST = '1' then + state <= BYTE0; + else + if (i + if S_AXIS_TVALID = '1' then + ui := ui+1; + i := to_integer(ui); + data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i) <= S_AXIS_TDATA; + if S_AXIS_TLAST = '1' then + state <= BYTE0; + elsif (i>=SIZE_FACTOR-2) then + state <= BYTEF; + end if; + end if; + when BYTEF => + if S_AXIS_TVALID = '1' and M_AXIS_TREADY='1' then + state <= BYTE0; + end if; + end case; + end if; + end process; + +end; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd new file mode 100644 index 0000000..b3b9e27 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd @@ -0,0 +1,286 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Sat Feb 1 13:46:51 2025 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target axis_crc_sim_1.bd +--Design : axis_crc_sim_1 +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity crc_imp_156I22D is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + M_AXIS_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_tlast : out STD_LOGIC; + M_AXIS_tready : in STD_LOGIC; + M_AXIS_tuser : out STD_LOGIC; + M_AXIS_tvalid : out STD_LOGIC; + S_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_tlast : in STD_LOGIC; + S_AXIS_tready : out STD_LOGIC; + S_AXIS_tuser : in STD_LOGIC; + S_AXIS_tvalid : in STD_LOGIC + ); +end crc_imp_156I22D; + +architecture STRUCTURE of crc_imp_156I22D is + component axis_crc_sim_1_axis_downsizer_0_0 is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC + ); + end component axis_crc_sim_1_axis_downsizer_0_0; + component axis_crc_sim_1_axis_upsizer_0_0 is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC + ); + end component axis_crc_sim_1_axis_upsizer_0_0; + component axis_crc_sim_1_xlconstant_1_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + end component axis_crc_sim_1_xlconstant_1_0; + component axis_crc_sim_1_xlconstant_0_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + end component axis_crc_sim_1_xlconstant_0_0; + component axis_crc_sim_1_axis_crc_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 ); + polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC + ); + end component axis_crc_sim_1_axis_crc_0_0; + signal AXIS_ACLK_1 : STD_LOGIC; + signal AXIS_ARESETN_1 : STD_LOGIC; + signal Conn1_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_TLAST : STD_LOGIC; + signal Conn1_TREADY : STD_LOGIC; + signal Conn1_TUSER : STD_LOGIC; + signal Conn1_TVALID : STD_LOGIC; + signal Conn2_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_TLAST : STD_LOGIC; + signal Conn2_TREADY : STD_LOGIC; + signal Conn2_TUSER : STD_LOGIC; + signal Conn2_TVALID : STD_LOGIC; + signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC; + signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_axis_downsizer_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC; +begin + AXIS_ACLK_1 <= AXIS_ACLK; + AXIS_ARESETN_1 <= AXIS_ARESETN; + Conn1_TDATA(31 downto 0) <= S_AXIS_tdata(31 downto 0); + Conn1_TLAST <= S_AXIS_tlast; + Conn1_TUSER <= S_AXIS_tuser; + Conn1_TVALID <= S_AXIS_tvalid; + Conn2_TREADY <= M_AXIS_tready; + M_AXIS_tdata(31 downto 0) <= Conn2_TDATA(31 downto 0); + M_AXIS_tlast <= Conn2_TLAST; + M_AXIS_tuser <= Conn2_TUSER; + M_AXIS_tvalid <= Conn2_TVALID; + S_AXIS_tready <= Conn1_TREADY; +axis_crc_0: component axis_crc_sim_1_axis_crc_0_0 + port map ( + CLK => AXIS_ACLK_1, + M_AXIS_TDATA(15 downto 0) => axis_crc_0_M_AXIS_TDATA(15 downto 0), + M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY, + M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID, + RESETN => AXIS_ARESETN_1, + S_AXIS_TDATA(15 downto 0) => axis_downsizer_0_M_AXIS_TDATA(15 downto 0), + S_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY, + S_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID, + initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0), + polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0) + ); +axis_downsizer_0: component axis_crc_sim_1_axis_downsizer_0_0 + port map ( + AXIS_ACLK => AXIS_ACLK_1, + AXIS_ARESETN => AXIS_ARESETN_1, + M_AXIS_TDATA(15 downto 0) => axis_downsizer_0_M_AXIS_TDATA(15 downto 0), + M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY, + M_AXIS_TUSER => NLW_axis_downsizer_0_M_AXIS_TUSER_UNCONNECTED, + M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID, + S_AXIS_TDATA(31 downto 0) => Conn1_TDATA(31 downto 0), + S_AXIS_TLAST => Conn1_TLAST, + S_AXIS_TREADY => Conn1_TREADY, + S_AXIS_TUSER => Conn1_TUSER, + S_AXIS_TVALID => Conn1_TVALID + ); +axis_upsizer_0: component axis_crc_sim_1_axis_upsizer_0_0 + port map ( + AXIS_ACLK => AXIS_ACLK_1, + AXIS_ARESETN => AXIS_ARESETN_1, + M_AXIS_TDATA(31 downto 0) => Conn2_TDATA(31 downto 0), + M_AXIS_TLAST => Conn2_TLAST, + M_AXIS_TREADY => Conn2_TREADY, + M_AXIS_TUSER => Conn2_TUSER, + M_AXIS_TVALID => Conn2_TVALID, + S_AXIS_TDATA(15 downto 0) => axis_crc_0_M_AXIS_TDATA(15 downto 0), + S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY, + S_AXIS_TUSER => '0', + S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID + ); +xlconstant_0: component axis_crc_sim_1_xlconstant_0_0 + port map ( + dout(31 downto 0) => xlconstant_0_dout(31 downto 0) + ); +xlconstant_1: component axis_crc_sim_1_xlconstant_1_0 + port map ( + dout(31 downto 0) => xlconstant_1_dout(31 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity axis_crc_sim_1 is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=8,numNonXlnxBlks=3,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef"; +end axis_crc_sim_1; + +architecture STRUCTURE of axis_crc_sim_1 is + component axis_crc_sim_1_clk_rst_generator_0_0 is + port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + clk : out STD_LOGIC; + rst_n : out STD_LOGIC; + stop_simulation : in STD_LOGIC + ); + end component axis_crc_sim_1_clk_rst_generator_0_0; + component axis_crc_sim_1_axis_slave_simmodel_0_0 is + port ( + FINISHED : out STD_LOGIC; + S_AXIS_ACLK : in STD_LOGIC; + S_AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component axis_crc_sim_1_axis_slave_simmodel_0_0; + component axis_crc_sim_1_axis_master_simmodel_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + FINISHED : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component axis_crc_sim_1_axis_master_simmodel_0_0; + signal AXIS_ARESETN_1 : STD_LOGIC; + signal axis_master_simmodel_0_FINISHED : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; + signal clk_rst_generator_0_clk : STD_LOGIC; + signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal crc_M_AXIS_TLAST : STD_LOGIC; + signal crc_M_AXIS_TREADY : STD_LOGIC; + signal crc_M_AXIS_TUSER : STD_LOGIC; + signal crc_M_AXIS_TVALID : STD_LOGIC; + signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC; +begin +axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0 + port map ( + ACLK => clk_rst_generator_0_clk, + ARESETN => AXIS_ARESETN_1, + FINISHED => axis_master_simmodel_0_FINISHED, + M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, + M_AXIS_TUSER(0) => axis_master_simmodel_0_M_AXIS_TUSER(0), + M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID + ); +axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0 + port map ( + FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED, + S_AXIS_ACLK => clk_rst_generator_0_clk, + S_AXIS_ARESETN => AXIS_ARESETN_1, + S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => crc_M_AXIS_TLAST, + S_AXIS_TREADY => crc_M_AXIS_TREADY, + S_AXIS_TUSER(0) => crc_M_AXIS_TUSER, + S_AXIS_TVALID => crc_M_AXIS_TVALID + ); +clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0 + port map ( + clk => clk_rst_generator_0_clk, + clk_in => '1', + rst_in => '0', + rst_n => AXIS_ARESETN_1, + stop_simulation => axis_master_simmodel_0_FINISHED + ); +crc: entity work.crc_imp_156I22D + port map ( + AXIS_ACLK => clk_rst_generator_0_clk, + AXIS_ARESETN => AXIS_ARESETN_1, + M_AXIS_tdata(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), + M_AXIS_tlast => crc_M_AXIS_TLAST, + M_AXIS_tready => crc_M_AXIS_TREADY, + M_AXIS_tuser => crc_M_AXIS_TUSER, + M_AXIS_tvalid => crc_M_AXIS_TVALID, + S_AXIS_tdata(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_tlast => axis_master_simmodel_0_M_AXIS_TLAST, + S_AXIS_tready => axis_master_simmodel_0_M_AXIS_TREADY, + S_AXIS_tuser => axis_master_simmodel_0_M_AXIS_TUSER(0), + S_AXIS_tvalid => axis_master_simmodel_0_M_AXIS_TVALID + ); +end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd new file mode 100644 index 0000000..b3b9e27 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd @@ -0,0 +1,286 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Sat Feb 1 13:46:51 2025 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target axis_crc_sim_1.bd +--Design : axis_crc_sim_1 +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity crc_imp_156I22D is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + M_AXIS_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_tlast : out STD_LOGIC; + M_AXIS_tready : in STD_LOGIC; + M_AXIS_tuser : out STD_LOGIC; + M_AXIS_tvalid : out STD_LOGIC; + S_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_tlast : in STD_LOGIC; + S_AXIS_tready : out STD_LOGIC; + S_AXIS_tuser : in STD_LOGIC; + S_AXIS_tvalid : in STD_LOGIC + ); +end crc_imp_156I22D; + +architecture STRUCTURE of crc_imp_156I22D is + component axis_crc_sim_1_axis_downsizer_0_0 is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC + ); + end component axis_crc_sim_1_axis_downsizer_0_0; + component axis_crc_sim_1_axis_upsizer_0_0 is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC + ); + end component axis_crc_sim_1_axis_upsizer_0_0; + component axis_crc_sim_1_xlconstant_1_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + end component axis_crc_sim_1_xlconstant_1_0; + component axis_crc_sim_1_xlconstant_0_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + end component axis_crc_sim_1_xlconstant_0_0; + component axis_crc_sim_1_axis_crc_0_0 is + port ( + CLK : in STD_LOGIC; + RESETN : in STD_LOGIC; + initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 ); + polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC + ); + end component axis_crc_sim_1_axis_crc_0_0; + signal AXIS_ACLK_1 : STD_LOGIC; + signal AXIS_ARESETN_1 : STD_LOGIC; + signal Conn1_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_TLAST : STD_LOGIC; + signal Conn1_TREADY : STD_LOGIC; + signal Conn1_TUSER : STD_LOGIC; + signal Conn1_TVALID : STD_LOGIC; + signal Conn2_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_TLAST : STD_LOGIC; + signal Conn2_TREADY : STD_LOGIC; + signal Conn2_TUSER : STD_LOGIC; + signal Conn2_TVALID : STD_LOGIC; + signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC; + signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_axis_downsizer_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC; +begin + AXIS_ACLK_1 <= AXIS_ACLK; + AXIS_ARESETN_1 <= AXIS_ARESETN; + Conn1_TDATA(31 downto 0) <= S_AXIS_tdata(31 downto 0); + Conn1_TLAST <= S_AXIS_tlast; + Conn1_TUSER <= S_AXIS_tuser; + Conn1_TVALID <= S_AXIS_tvalid; + Conn2_TREADY <= M_AXIS_tready; + M_AXIS_tdata(31 downto 0) <= Conn2_TDATA(31 downto 0); + M_AXIS_tlast <= Conn2_TLAST; + M_AXIS_tuser <= Conn2_TUSER; + M_AXIS_tvalid <= Conn2_TVALID; + S_AXIS_tready <= Conn1_TREADY; +axis_crc_0: component axis_crc_sim_1_axis_crc_0_0 + port map ( + CLK => AXIS_ACLK_1, + M_AXIS_TDATA(15 downto 0) => axis_crc_0_M_AXIS_TDATA(15 downto 0), + M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY, + M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID, + RESETN => AXIS_ARESETN_1, + S_AXIS_TDATA(15 downto 0) => axis_downsizer_0_M_AXIS_TDATA(15 downto 0), + S_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY, + S_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID, + initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0), + polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0) + ); +axis_downsizer_0: component axis_crc_sim_1_axis_downsizer_0_0 + port map ( + AXIS_ACLK => AXIS_ACLK_1, + AXIS_ARESETN => AXIS_ARESETN_1, + M_AXIS_TDATA(15 downto 0) => axis_downsizer_0_M_AXIS_TDATA(15 downto 0), + M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY, + M_AXIS_TUSER => NLW_axis_downsizer_0_M_AXIS_TUSER_UNCONNECTED, + M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID, + S_AXIS_TDATA(31 downto 0) => Conn1_TDATA(31 downto 0), + S_AXIS_TLAST => Conn1_TLAST, + S_AXIS_TREADY => Conn1_TREADY, + S_AXIS_TUSER => Conn1_TUSER, + S_AXIS_TVALID => Conn1_TVALID + ); +axis_upsizer_0: component axis_crc_sim_1_axis_upsizer_0_0 + port map ( + AXIS_ACLK => AXIS_ACLK_1, + AXIS_ARESETN => AXIS_ARESETN_1, + M_AXIS_TDATA(31 downto 0) => Conn2_TDATA(31 downto 0), + M_AXIS_TLAST => Conn2_TLAST, + M_AXIS_TREADY => Conn2_TREADY, + M_AXIS_TUSER => Conn2_TUSER, + M_AXIS_TVALID => Conn2_TVALID, + S_AXIS_TDATA(15 downto 0) => axis_crc_0_M_AXIS_TDATA(15 downto 0), + S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY, + S_AXIS_TUSER => '0', + S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID + ); +xlconstant_0: component axis_crc_sim_1_xlconstant_0_0 + port map ( + dout(31 downto 0) => xlconstant_0_dout(31 downto 0) + ); +xlconstant_1: component axis_crc_sim_1_xlconstant_1_0 + port map ( + dout(31 downto 0) => xlconstant_1_dout(31 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity axis_crc_sim_1 is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=8,numNonXlnxBlks=3,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef"; +end axis_crc_sim_1; + +architecture STRUCTURE of axis_crc_sim_1 is + component axis_crc_sim_1_clk_rst_generator_0_0 is + port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + clk : out STD_LOGIC; + rst_n : out STD_LOGIC; + stop_simulation : in STD_LOGIC + ); + end component axis_crc_sim_1_clk_rst_generator_0_0; + component axis_crc_sim_1_axis_slave_simmodel_0_0 is + port ( + FINISHED : out STD_LOGIC; + S_AXIS_ACLK : in STD_LOGIC; + S_AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component axis_crc_sim_1_axis_slave_simmodel_0_0; + component axis_crc_sim_1_axis_master_simmodel_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + FINISHED : out STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component axis_crc_sim_1_axis_master_simmodel_0_0; + signal AXIS_ARESETN_1 : STD_LOGIC; + signal axis_master_simmodel_0_FINISHED : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; + signal clk_rst_generator_0_clk : STD_LOGIC; + signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal crc_M_AXIS_TLAST : STD_LOGIC; + signal crc_M_AXIS_TREADY : STD_LOGIC; + signal crc_M_AXIS_TUSER : STD_LOGIC; + signal crc_M_AXIS_TVALID : STD_LOGIC; + signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC; +begin +axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0 + port map ( + ACLK => clk_rst_generator_0_clk, + ARESETN => AXIS_ARESETN_1, + FINISHED => axis_master_simmodel_0_FINISHED, + M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, + M_AXIS_TUSER(0) => axis_master_simmodel_0_M_AXIS_TUSER(0), + M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID + ); +axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0 + port map ( + FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED, + S_AXIS_ACLK => clk_rst_generator_0_clk, + S_AXIS_ARESETN => AXIS_ARESETN_1, + S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => crc_M_AXIS_TLAST, + S_AXIS_TREADY => crc_M_AXIS_TREADY, + S_AXIS_TUSER(0) => crc_M_AXIS_TUSER, + S_AXIS_TVALID => crc_M_AXIS_TVALID + ); +clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0 + port map ( + clk => clk_rst_generator_0_clk, + clk_in => '1', + rst_in => '0', + rst_n => AXIS_ARESETN_1, + stop_simulation => axis_master_simmodel_0_FINISHED + ); +crc: entity work.crc_imp_156I22D + port map ( + AXIS_ACLK => clk_rst_generator_0_clk, + AXIS_ARESETN => AXIS_ARESETN_1, + M_AXIS_tdata(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0), + M_AXIS_tlast => crc_M_AXIS_TLAST, + M_AXIS_tready => crc_M_AXIS_TREADY, + M_AXIS_tuser => crc_M_AXIS_TUSER, + M_AXIS_tvalid => crc_M_AXIS_TVALID, + S_AXIS_tdata(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_tlast => axis_master_simmodel_0_M_AXIS_TLAST, + S_AXIS_tready => axis_master_simmodel_0_M_AXIS_TREADY, + S_AXIS_tuser => axis_master_simmodel_0_M_AXIS_TUSER(0), + S_AXIS_tvalid => axis_master_simmodel_0_M_AXIS_TVALID + ); +end STRUCTURE; diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml new file mode 100644 index 0000000..2a2b606 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml @@ -0,0 +1,426 @@ + + + xilinx.com + module_ref + axis_crc + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + RESETN + + + + + + + RST + + + RESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + CLK + + + + + + + CLK + + + CLK + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS + + + ASSOCIATED_RESET + RESETN + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_crc + + + viewChecksum + 23871aa0 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_crc + + + viewChecksum + 23871aa0 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + + + CLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + RESETN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + initial_value + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + polynomial + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + + CRC_WIDTH + Crc Width + 32 + + + DWITH + Dwith + 16 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_xpgui_view_fileset + + xgui/axis_crc_v1_0.tcl + tclSource + CHECKSUM_2a632c0b + XGUI_VERSION_2 + + + + xilinx.com:module_ref:axis_crc:1.0 + + + CRC_WIDTH + Crc Width + 32 + + + DWITH + Dwith + 16 + + + Component_Name + axis_crc_v1_0 + + + + + + zynq + + + /UserIP + + axis_crc_v1_0 + level_1 + module_ref + + IPI + + 1 + 2025-02-01T12:46:45Z + + + 2023.1 + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/xgui/axis_crc_v1_0.tcl b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/xgui/axis_crc_v1_0.tcl new file mode 100644 index 0000000..67ca062 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/xgui/axis_crc_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CRC_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DWITH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.CRC_WIDTH { PARAM_VALUE.CRC_WIDTH } { + # Procedure called to update CRC_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CRC_WIDTH { PARAM_VALUE.CRC_WIDTH } { + # Procedure called to validate CRC_WIDTH + return true +} + +proc update_PARAM_VALUE.DWITH { PARAM_VALUE.DWITH } { + # Procedure called to update DWITH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DWITH { PARAM_VALUE.DWITH } { + # Procedure called to validate DWITH + return true +} + + +proc update_MODELPARAM_VALUE.CRC_WIDTH { MODELPARAM_VALUE.CRC_WIDTH PARAM_VALUE.CRC_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CRC_WIDTH}] ${MODELPARAM_VALUE.CRC_WIDTH} +} + +proc update_MODELPARAM_VALUE.DWITH { MODELPARAM_VALUE.DWITH PARAM_VALUE.DWITH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DWITH}] ${MODELPARAM_VALUE.DWITH} +} + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml new file mode 100644 index 0000000..e88bcb5 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml @@ -0,0 +1,1734 @@ + + + xilinx.com + module_ref + axis_dma + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + M_AXI + + + + + + + + + AWID + + + M_AXI_AWID + + + + + AWADDR + + + M_AXI_AWADDR + + + + + AWLEN + + + M_AXI_AWLEN + + + + + AWSIZE + + + M_AXI_AWSIZE + + + + + AWBURST + + + M_AXI_AWBURST + + + + + AWCACHE + + + M_AXI_AWCACHE + + + + + AWPROT + + + M_AXI_AWPROT + + + + + AWVALID + + + M_AXI_AWVALID + + + + + AWREADY + + + M_AXI_AWREADY + + + + + WID + + + M_AXI_WID + + + + + WDATA + + + M_AXI_WDATA + + + + + WSTRB + + + M_AXI_WSTRB + + + + + WLAST + + + M_AXI_WLAST + + + + + WVALID + + + M_AXI_WVALID + + + + + WREADY + + + M_AXI_WREADY + + + + + BID + + + M_AXI_BID + + + + + BRESP + + + M_AXI_BRESP + + + + + BVALID + + + M_AXI_BVALID + + + + + BREADY + + + M_AXI_BREADY + + + + + ARID + + + M_AXI_ARID + + + + + ARADDR + + + M_AXI_ARADDR + + + + + ARLEN + + + M_AXI_ARLEN + + + + + ARSIZE + + + M_AXI_ARSIZE + + + + + ARBURST + + + M_AXI_ARBURST + + + + + ARCACHE + + + M_AXI_ARCACHE + + + + + ARPROT + + + M_AXI_ARPROT + + + + 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xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + S_AXIL_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_ARADDR + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_ARREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXI_ARVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + M_AXI_ARADDR + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_ARID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_ARLEN + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_ARSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_ARBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_ARPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_ARCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_RREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_RVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXI_RDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXI_RRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXI_RID + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXI_RLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXI_AWREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + M_AXI_AWVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + M_AXI_AWADDR + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_AWLEN + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_AWSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_AWID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_AWBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_AWPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_AWCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_WREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + M_AXI_WVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + M_AXI_WDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_WSTRB + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_WLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_WID + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_BREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_BVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + M_AXI_BID + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXI_BRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + + DWIDTH + Dwidth + 32 + + + IDWIDTH + Idwidth + 1 + + + MAX_BURSTLEN + Max Burstlen + 16 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_xpgui_view_fileset + + xgui/axis_dma_v1_0.tcl + tclSource + CHECKSUM_dc83b24a + XGUI_VERSION_2 + + + + xilinx.com:module_ref:axis_dma:1.0 + + + DWIDTH + Dwidth + 32 + + + IDWIDTH + Idwidth + 1 + + + MAX_BURSTLEN + Max Burstlen + 16 + + + Component_Name + axis_dma_v1_0 + + + + + + zynq + + + /UserIP + + axis_dma_v1_0 + level_1 + module_ref + + IPI + + 1 + 2025-01-31T17:03:28Z + + + 2023.1 + + + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl new file mode 100644 index 0000000..3f2fcb6 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "IDWIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "MAX_BURSTLEN" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } { + # Procedure called to update DWIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } { + # Procedure called to validate DWIDTH + return true +} + +proc update_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } { + # Procedure called to update IDWIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } { + # Procedure called to validate IDWIDTH + return true +} + +proc update_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } { + # Procedure called to update MAX_BURSTLEN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } { + # Procedure called to validate MAX_BURSTLEN + return true +} + + +proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH} +} + +proc update_MODELPARAM_VALUE.IDWIDTH { MODELPARAM_VALUE.IDWIDTH PARAM_VALUE.IDWIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IDWIDTH}] ${MODELPARAM_VALUE.IDWIDTH} +} + +proc update_MODELPARAM_VALUE.MAX_BURSTLEN { MODELPARAM_VALUE.MAX_BURSTLEN PARAM_VALUE.MAX_BURSTLEN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MAX_BURSTLEN}] ${MODELPARAM_VALUE.MAX_BURSTLEN} +} + diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd new file mode 100644 index 0000000..7c1a12c --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd @@ -0,0 +1,1112 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x0", + "device": "xc7z020clg400-1", + "gen_directory": "../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1", + "name": "axi_crc_dma_sim_1", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2023.1" + }, + "design_tree": { + "axi_crc_dma": { + "axis_dma_0": "", + "axis_fifo_0": "", + "axis_fifo_1": "", + "crc": { + "axis_downsizer_0": "", + "axis_upsizer_0": "", + "axis_crc_0": "" + } + }, + "axil_master_with_rom_0": "", + "clk_rst_generator_0": "" + }, + "components": { + "axi_crc_dma": { + "interface_ports": { + "S_AXIL": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "CLK": { + "type": "clk", + "direction": "I" + }, + "RESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "axis_dma_0": { + "vlnv": "xilinx.com:module_ref:axis_dma:1.0", + "xci_name": "axi_crc_dma_sim_1_axis_dma_0_0", + "xci_path": "ip\\axi_crc_dma_sim_1_axis_dma_0_0\\axi_crc_dma_sim_1_axis_dma_0_0.xci", + "inst_hier_path": "axi_crc_dma/axis_dma_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "axis_dma", + "boundary_crc": "0x0" + }, + "interface_ports": { + "M_AXIS": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "4", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "M_AXIS_TDATA", + "direction": "O", + "left": "31", + "right": "0" + }, + "TLAST": { + "physical_name": "M_AXIS_TLAST", + "direction": "O" + }, + "TVALID": { + "physical_name": "M_AXIS_TVALID", + "direction": "O" + }, + "TREADY": { + "physical_name": "M_AXIS_TREADY", + "direction": "I" + } + } + }, + "S_AXIS": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "4", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "S_AXIS_TDATA", + "direction": "I", + "left": "31", + "right": "0" + }, + "TLAST": { + "physical_name": "S_AXIS_TLAST", + "direction": "I" + }, + "TVALID": { + "physical_name": "S_AXIS_TVALID", + "direction": "I" + }, + "TREADY": { + "physical_name": "S_AXIS_TREADY", + "direction": "O" + } + } + }, + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "DATA_WIDTH": { + "value": "32", + "value_src": "auto" + }, + "PROTOCOL": { + "value": "AXI3", + "value_src": "constant" + }, + "ID_WIDTH": { + "value": "1", + "value_src": "auto" + }, + "ADDR_WIDTH": { + "value": "32", + "value_src": "constant" + }, + "AWUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "ARUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "WUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "RUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "BUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE", + "value_src": "constant" + }, + "HAS_BURST": { + "value": "1", + "value_src": "constant" + }, + "HAS_LOCK": { + "value": "0", + "value_src": "constant" + }, + "HAS_PROT": { + "value": "1", + "value_src": "constant" + }, + "HAS_CACHE": { + "value": "1", + "value_src": "constant" + }, + "HAS_QOS": { + "value": "0", + "value_src": "constant" + }, + "HAS_REGION": { + "value": "0", + "value_src": "constant" + }, + "HAS_WSTRB": { + "value": "1", + "value_src": "constant" + }, + "HAS_BRESP": { + "value": "1", + "value_src": "constant" + }, + "HAS_RRESP": { + "value": "1", + "value_src": "constant" + }, + "SUPPORTS_NARROW_BURST": { + "value": "1", + "value_src": "auto" + }, + "NUM_READ_OUTSTANDING": { + "value": "2", + "value_src": "auto" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "2", + "value_src": "auto" + }, + "MAX_BURST_LENGTH": { + "value": "16", + "value_src": "auto" + } + }, + "address_space_ref": "M_AXI", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + }, + "port_maps": { + "AWID": { + "physical_name": "M_AXI_AWID", + "direction": "O", + "left": "0", + "right": "0" + }, + "AWADDR": { + "physical_name": "M_AXI_AWADDR", + "direction": "O", + "left": "31", + "right": "0" + }, + "AWLEN": { + "physical_name": "M_AXI_AWLEN", + "direction": "O", + "left": "3", + "right": "0" + }, + "AWSIZE": { + "physical_name": "M_AXI_AWSIZE", + "direction": "O", + "left": "2", + "right": "0" + }, + "AWBURST": { + "physical_name": "M_AXI_AWBURST", + "direction": "O", + "left": "1", + "right": "0" + }, + "AWCACHE": { + "physical_name": "M_AXI_AWCACHE", + "direction": "O", + "left": "3", + "right": "0" + }, + "AWPROT": { + "physical_name": "M_AXI_AWPROT", + "direction": "O", + "left": "2", + "right": "0" + }, + "AWVALID": { + "physical_name": "M_AXI_AWVALID", + "direction": "O" + }, + "AWREADY": { + "physical_name": "M_AXI_AWREADY", + "direction": "I" + }, + "WID": { + "physical_name": "M_AXI_WID", + "direction": "O", + "left": "31", + "right": "0" + }, + "WDATA": { + "physical_name": "M_AXI_WDATA", + "direction": "O", + "left": "31", + "right": "0" + }, + "WSTRB": { + "physical_name": "M_AXI_WSTRB", + "direction": "O", + "left": "3", + "right": "0" + }, + "WLAST": { + "physical_name": "M_AXI_WLAST", + "direction": "O" + }, + "WVALID": { + "physical_name": "M_AXI_WVALID", + "direction": "O" + }, + "WREADY": { + "physical_name": "M_AXI_WREADY", + "direction": "I" + }, + "BID": { + "physical_name": "M_AXI_BID", + "direction": "I", + "left": "31", + "right": "0" + }, + "BRESP": { + "physical_name": "M_AXI_BRESP", + "direction": "I", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "M_AXI_BVALID", + "direction": "I" + }, + "BREADY": { + "physical_name": "M_AXI_BREADY", + "direction": "O" + }, + "ARID": { + "physical_name": "M_AXI_ARID", + "direction": "O", + "left": "0", + "right": "0" + }, + "ARADDR": { + "physical_name": "M_AXI_ARADDR", + "direction": "O", + "left": "31", + "right": "0" + }, + "ARLEN": { + "physical_name": "M_AXI_ARLEN", + "direction": "O", + "left": "3", + "right": "0" + }, + "ARSIZE": { + "physical_name": "M_AXI_ARSIZE", + "direction": "O", + "left": "2", + "right": "0" + }, + "ARBURST": { + "physical_name": "M_AXI_ARBURST", + "direction": "O", + "left": "1", + "right": "0" + }, + "ARCACHE": { + "physical_name": "M_AXI_ARCACHE", + "direction": "O", + "left": "3", + "right": "0" + }, + "ARPROT": { + "physical_name": "M_AXI_ARPROT", + "direction": "O", + "left": "2", + "right": "0" + }, + "ARVALID": { + "physical_name": "M_AXI_ARVALID", + "direction": "O" + }, + "ARREADY": { + "physical_name": "M_AXI_ARREADY", + "direction": "I" + }, + "RID": { + "physical_name": "M_AXI_RID", + "direction": "I", + "left": "0", + "right": "0" + }, + "RDATA": { + "physical_name": "M_AXI_RDATA", + "direction": "I", + "left": "31", + "right": "0" + }, + "RRESP": { + "physical_name": "M_AXI_RRESP", + "direction": "I", + "left": "1", + "right": "0" + }, + "RLAST": { + "physical_name": "M_AXI_RLAST", + "direction": "I" + }, + "RVALID": { + "physical_name": "M_AXI_RVALID", + "direction": "I" + }, + "RREADY": { + "physical_name": "M_AXI_RREADY", + "direction": "O" + } + } + }, + "S_AXIL": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "DATA_WIDTH": { + "value": "32", + "value_src": "constant" + }, + "PROTOCOL": { + "value": "AXI4LITE", + "value_src": "constant" + }, + "ID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "ADDR_WIDTH": { + "value": "8", + "value_src": "constant" + }, + "AWUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "ARUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "WUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "RUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "BUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE", + "value_src": "constant" + }, + "HAS_BURST": { + "value": "0", + "value_src": "constant" + }, + "HAS_LOCK": { + "value": "0", + "value_src": "constant" + }, + "HAS_PROT": { + "value": "0", + "value_src": "constant" + }, + "HAS_CACHE": { + "value": "0", + "value_src": "constant" + }, + "HAS_QOS": { + "value": "0", + "value_src": "constant" + }, + "HAS_REGION": { + "value": "0", + "value_src": "constant" + }, + "HAS_WSTRB": { + "value": "1", + "value_src": "constant" + }, + "HAS_BRESP": { + "value": "1", + "value_src": "constant" + }, + "HAS_RRESP": { + "value": "1", + "value_src": "constant" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0", + "value_src": "auto" + }, + "NUM_READ_OUTSTANDING": { + "value": "1", + "value_src": "auto" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1", + "value_src": "auto" + }, + "MAX_BURST_LENGTH": { + "value": "1", + "value_src": "auto" + } + }, + "memory_map_ref": "S_AXIL", + "port_maps": { + "AWADDR": { + "physical_name": "S_AXIL_AWADDR", + "direction": "I", + "left": "7", + "right": "0" + }, + "AWVALID": { + "physical_name": "S_AXIL_AWVALID", + "direction": "I" + }, + "AWREADY": { + "physical_name": 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a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xci new file mode 100644 index 0000000..695ab33 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xci @@ -0,0 +1,57 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_crc_dma_sim_1_clk_rst_generator_0_0", + "cell_name": "clk_rst_generator_0", + "component_reference": "wg:user:clk_rst_generator:1.0", + "ip_revision": "7", + "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0", + "parameters": { + "component_parameters": { + "CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Component_Name": [ { "value": "axi_crc_dma_sim_1_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ] + }, + "project_parameters": { + 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7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace inst axi_crc_dma -pg 1 -lvl 3 -x 360 -y 60 -defaultsOSRD +preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 140 -y 60 -defaultsOSRD +preplace netloc clk_rst_generator_0_clk 1 1 2 220 30n 460J +preplace netloc clk_rst_generator_0_rst_n 1 1 2 220 190n 460J +preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 N 60 +levelinfo -pg 1 0 20 140 360 440 +pagesize -pg 1 -db -bbox -sgen 0 0 1990 480 +", + "Interfaces View_ScaleFactor":"1.64938", + "Interfaces View_TopLeft":"-199,-369", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace inst axi_crc_dma -pg 1 -lvl 3 -x 590 -y 78 -defaultsOSRD +preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 350 -y 110 -defaultsOSRD +preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 120 -defaultsOSRD +preplace netloc clk_rst_generator_0_clk 1 1 2 220 20 490J +preplace netloc clk_rst_generator_0_rst_n 1 1 2 230 30 470J +preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 480 58n +levelinfo -pg 1 0 110 350 590 670 +pagesize -pg 1 -db -bbox -sgen 0 -10 2680 420 +" +} +{ + "da_clkrst_cnt":"6" +} diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd new file mode 100644 index 0000000..a455a09 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd @@ -0,0 +1,387 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x0", + "device": "xc7z020clg400-1", + "gen_directory": "../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1", + "name": "axis_crc_sim_1", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2023.1", + "validated": "true" + }, + "design_tree": { + "clk_rst_generator_0": "", + "axis_slave_simmodel_0": "", + "axis_master_simmodel_0": "", + "crc": { + "axis_downsizer_0": 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b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xci @@ -0,0 +1,57 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axis_crc_sim_1_clk_rst_generator_0_0", + "cell_name": "clk_rst_generator_0", + "component_reference": "wg:user:clk_rst_generator:1.0", + "ip_revision": "7", + "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0", + "parameters": { + "component_parameters": { + "CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Component_Name": [ { "value": "axis_crc_sim_1_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VHDL" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "7" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "clk_in": [ { "direction": "in", "driver_value": "0x1" } ], + "rst_in": [ { "direction": "in", "driver_value": "0x0" } ], + "clk": [ { "direction": "out" } ], + "rst_n": [ { "direction": "out" } ], + "stop_simulation": [ { "direction": "in", "driver_value": "0x0" } ] + } + } + } +} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xci new file mode 100644 index 0000000..fa4b18f --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xci @@ -0,0 +1,49 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axis_crc_sim_1_xlconstant_0_0", + "cell_name": "crc/xlconstant_0", + "component_reference": "xilinx.com:ip:xlconstant:1.1", + "ip_revision": "7", + "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axis_crc_sim_1_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ], + "CONST_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CONST_VAL": [ { "value": "1", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "CONST_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CONST_VAL": [ { "value": "0x00000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VHDL" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "7" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "GLOBAL" } ] + } + }, + "boundary": { + "ports": { + "dout": [ { "direction": "out", "size_left": "31", "size_right": "0" } ] + } + } + } +} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xci b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xci new file mode 100644 index 0000000..28893db --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xci @@ -0,0 +1,49 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axis_crc_sim_1_xlconstant_1_0", + "cell_name": "crc/xlconstant_1", + "component_reference": "xilinx.com:ip:xlconstant:1.1", + "ip_revision": "7", + "gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axis_crc_sim_1_xlconstant_1_0", "resolve_type": "user", "usage": "all" } ], + "CONST_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CONST_VAL": [ { "value": "1", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "CONST_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CONST_VAL": [ { "value": "0x00000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VHDL" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "7" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "GLOBAL" } ] + } + }, + "boundary": { + "ports": { + "dout": [ { "direction": "out", "size_left": "31", "size_right": "0" } ] + } + } + } +} \ No newline at end of file diff --git a/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui new file mode 100644 index 0000000..74c8585 --- /dev/null +++ b/Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui @@ -0,0 +1,36 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.876705", + "Default View_TopLeft":"10,-91", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 130 -y 490 -defaultsOSRD +preplace inst axis_slave_simmodel_0 -pg 1 -lvl 4 -x 1660 -y 80 -defaultsOSRD +preplace inst axis_master_simmodel_0 -pg 1 -lvl 2 -x 350 -y 490 -defaultsOSRD +preplace inst crc -pg 1 -lvl 3 -x 680 -y 240 -defaultsOSRD +preplace inst crc|axis_downsizer_0 -pg 1 -lvl 1 -x 750 -y 500 -defaultsOSRD +preplace inst crc|axis_upsizer_0 -pg 1 -lvl 3 -x 1310 -y 560 -defaultsOSRD +preplace inst crc|xlconstant_1 -pg 1 -lvl 1 -x 750 -y 250 -defaultsOSRD +preplace inst crc|xlconstant_0 -pg 1 -lvl 1 -x 750 -y 350 -defaultsOSRD +preplace inst crc|axis_crc_0 -pg 1 -lvl 2 -x 1040 -y 540 -defaultsOSRD +preplace netloc clk_rst_generator_0_clk 1 1 3 240 410 460 80 NJ +preplace netloc AXIS_ARESETN_1 1 1 3 250 420 470 100 NJ +preplace netloc axis_master_simmodel_0_FINISHED 1 0 3 20 400 NJ 400 450 +preplace netloc axis_master_simmodel_0_M_AXIS 1 2 1 N 480 +preplace netloc crc_M_AXIS 1 3 1 1540 60n +preplace netloc crc|AXIS_ACLK_1 1 0 3 630 580 870 640 1180J +preplace netloc crc|AXIS_ARESETN_1 1 0 3 620 590 890 650 1190J +preplace netloc crc|xlconstant_1_dout 1 1 1 900J 250n +preplace netloc crc|xlconstant_0_dout 1 1 1 880J 350n +preplace netloc crc|axis_downsizer_0_M_AXIS 1 1 1 N 500 +preplace netloc crc|axis_crc_0_M_AXIS 1 2 1 N 540 +preplace netloc crc|Conn1 1 0 1 N 480 +preplace netloc crc|Conn2 1 3 1 N 560 +levelinfo -pg 1 0 130 350 680 1660 1800 +levelinfo -hier crc * 750 1040 1310 * +pagesize -pg 1 -db -bbox -sgen 0 0 1800 680 +pagesize -hier crc -db -bbox -sgen 590 190 1460 660 +" +} + diff --git a/Hardware/crc_dma/crc_dma.xpr b/Hardware/aci_crc_dma/aci_crc_dma.xpr similarity index 73% rename from Hardware/crc_dma/crc_dma.xpr rename to Hardware/aci_crc_dma/aci_crc_dma.xpr index 680a2d1..a8957ca 100644 --- a/Hardware/crc_dma/crc_dma.xpr +++ b/Hardware/aci_crc_dma/aci_crc_dma.xpr @@ -4,10 +4,10 @@ - + -