diff --git a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml
index c2b7eaf..fff87f0 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml
+++ b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml
@@ -2,10 +2,10 @@
Composite Fileset
-
-
-
-
+
+
+
+
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml
index 9a682ff..b8d6ce0 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml
+++ b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml
@@ -2,10 +2,10 @@
Composite Fileset
-
-
-
-
+
+
+
+
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml
index 5a8754e..8e540bb 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml
+++ b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml
@@ -1701,7 +1701,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1714,7 +1714,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1731,7 +1731,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1758,7 +1758,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1785,7 +1785,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1812,7 +1812,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1839,7 +1839,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1866,7 +1866,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1893,7 +1893,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1920,7 +1920,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1947,7 +1947,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1974,7 +1974,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2001,7 +2001,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2024,7 +2024,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2047,7 +2047,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2071,7 +2071,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2098,7 +2098,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2125,7 +2125,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2148,7 +2148,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2175,7 +2175,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2198,7 +2198,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2221,7 +2221,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2245,7 +2245,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2269,7 +2269,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2293,7 +2293,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2313,7 +2313,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2333,7 +2333,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2360,7 +2360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2387,7 +2387,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2414,7 +2414,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2441,7 +2441,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2468,7 +2468,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2495,7 +2495,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2522,7 +2522,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2549,7 +2549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2576,7 +2576,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2603,7 +2603,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2630,7 +2630,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2653,7 +2653,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2676,7 +2676,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2700,7 +2700,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2724,7 +2724,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2748,7 +2748,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2768,7 +2768,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2792,7 +2792,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2812,7 +2812,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2832,7 +2832,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2859,7 +2859,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2883,7 +2883,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2907,7 +2907,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2931,7 +2931,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2955,7 +2955,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2979,7 +2979,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3003,7 +3003,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3027,7 +3027,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3051,7 +3051,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3075,7 +3075,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3099,7 +3099,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3119,7 +3119,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3139,7 +3139,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3166,7 +3166,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3190,7 +3190,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3214,7 +3214,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3234,7 +3234,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3258,7 +3258,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3278,7 +3278,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3298,7 +3298,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3325,7 +3325,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3352,7 +3352,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3379,7 +3379,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3402,7 +3402,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3425,7 +3425,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3449,7 +3449,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3473,7 +3473,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3497,7 +3497,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3521,7 +3521,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3545,7 +3545,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3569,7 +3569,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3593,7 +3593,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3617,7 +3617,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3641,7 +3641,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3665,7 +3665,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3689,7 +3689,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3709,7 +3709,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3729,7 +3729,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3756,7 +3756,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3783,7 +3783,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3810,7 +3810,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3833,7 +3833,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3860,7 +3860,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3883,7 +3883,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3906,7 +3906,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -4552,67 +4552,68 @@
-
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
-
-
-
-
+
+
+
+
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
-
+
-
+
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml
index 7f589c7..7b8573a 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml
+++ b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml
@@ -1746,7 +1746,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1762,7 +1762,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1782,7 +1782,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1809,7 +1809,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1836,7 +1836,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1863,7 +1863,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1890,7 +1890,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1917,7 +1917,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1944,7 +1944,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1971,7 +1971,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1998,7 +1998,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2025,7 +2025,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2048,7 +2048,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2071,7 +2071,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2095,7 +2095,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2122,7 +2122,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2145,7 +2145,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2168,7 +2168,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2191,7 +2191,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2215,7 +2215,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2239,7 +2239,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2259,7 +2259,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2279,7 +2279,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2306,7 +2306,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2333,7 +2333,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2360,7 +2360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2387,7 +2387,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2414,7 +2414,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2441,7 +2441,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2468,7 +2468,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2495,7 +2495,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2522,7 +2522,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2549,7 +2549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2572,7 +2572,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2595,7 +2595,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2619,7 +2619,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2643,7 +2643,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2667,7 +2667,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2687,7 +2687,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2707,7 +2707,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2727,7 +2727,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2750,7 +2750,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2773,7 +2773,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2800,7 +2800,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2824,7 +2824,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2848,7 +2848,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2872,7 +2872,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2896,7 +2896,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2920,7 +2920,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2944,7 +2944,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2968,7 +2968,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2992,7 +2992,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3012,7 +3012,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3032,7 +3032,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3059,7 +3059,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3083,7 +3083,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3103,7 +3103,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3123,7 +3123,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3143,7 +3143,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3170,7 +3170,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3193,7 +3193,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3216,7 +3216,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3240,7 +3240,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3264,7 +3264,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3288,7 +3288,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3312,7 +3312,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3336,7 +3336,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3360,7 +3360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3384,7 +3384,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3408,7 +3408,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3432,7 +3432,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3452,7 +3452,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3472,7 +3472,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3499,7 +3499,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3526,7 +3526,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3549,7 +3549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3572,7 +3572,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3595,7 +3595,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -4387,7 +4387,7 @@
-
+
@@ -4420,31 +4420,32 @@
-
+
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xml b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xml
index a989fb5..f3b7e85 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xml
+++ b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xml
@@ -40687,22 +40687,22 @@
-
-
+
+
-
-
-
-
-
-
+
+
+
+
+
+
-
-
+
+
@@ -40710,7 +40710,7 @@
-
+
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/mref/axi_crc_dma_ip_wrapper/component.xml b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/mref/axi_crc_dma_ip_wrapper/component.xml
index 15547cd..d758ba0 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/mref/axi_crc_dma_ip_wrapper/component.xml
+++ b/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/mref/axi_crc_dma_ip_wrapper/component.xml
@@ -537,7 +537,7 @@
viewChecksum
- ad42eba3
+ 88f3664d
@@ -550,7 +550,7 @@
viewChecksum
- ad42eba3
+ 88f3664d
@@ -1491,7 +1491,7 @@
IPI
1
- 2025-02-13T21:47:34Z
+ 2025-02-14T11:18:47Z
2023.1
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xci b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xci
index 490db4e..634aa13 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xci
+++ b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xci
@@ -132,26 +132,26 @@
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "slave",
"parameters": {
- "DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "PROTOCOL": [ { "value": "AXI3", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ID_WIDTH": [ { "value": "12", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -210,26 +210,26 @@
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "master",
"parameters": {
- "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_CACHE": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_LOCK": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_CACHE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_QOS": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -289,7 +289,7 @@
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
- "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+ "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xci b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xci
index 4939060..2d765a0 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xci
+++ b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xci
@@ -145,26 +145,26 @@
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "slave",
"parameters": {
- "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "PROTOCOL": [ { "value": "AXI3", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "PROTOCOL": [ { "value": "AXI3", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ID_WIDTH": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ADDR_WIDTH": [ { "value": "32", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ID_WIDTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -222,7 +222,7 @@
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "master",
"parameters": {
- "DATA_WIDTH": [ { "value": "64", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "DATA_WIDTH": [ { "value": "64", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -315,7 +315,7 @@
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
- "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+ "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axi_aresetn" } ]
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xci b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xci
index 1828581..f97172e 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xci
+++ b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xci
@@ -1249,22 +1249,22 @@
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "ID_WIDTH": [ { "value": "3", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "AWUSER_WIDTH": [ { "value": "5", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "ARUSER_WIDTH": [ { "value": "5", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "AWUSER_WIDTH": [ { "value": "5", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "ARUSER_WIDTH": [ { "value": "5", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
- "HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+ "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ui/bd_a79714db.ui b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ui/bd_a79714db.ui
index a1aee4c..b1db544 100644
--- a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ui/bd_a79714db.ui
+++ b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ui/bd_a79714db.ui
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"2.0",
- "Default View_TopLeft":"87,-56",
+ "Default View_TopLeft":"88,-57",
"Display-PortTypeClock":"true",
"Display-PortTypeInterrupt":"true",
"Display-PortTypeOthers":"true",
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/design_1/design_1.bd b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/design_1/design_1.bd
new file mode 100644
index 0000000..292bd3e
--- /dev/null
+++ b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/design_1/design_1.bd
@@ -0,0 +1,13 @@
+{
+ "design": {
+ "design_info": {
+ "boundary_crc": "0x0",
+ "gen_directory": "../../../../axi_crc_dma.gen/sources_1/bd/design_1",
+ "name": "design_1",
+ "rev_ctrl_bd_flag": "RevCtrlBdOff",
+ "synth_flow_mode": "Hierarchical",
+ "tool_version": "2023.1"
+ },
+ "design_tree": {}
+ }
+}
\ No newline at end of file
diff --git a/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
new file mode 100644
index 0000000..8542941
--- /dev/null
+++ b/Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
@@ -0,0 +1,13 @@
+{
+ "ActiveEmotionalView":"Default View",
+ "Default View_ScaleFactor":"2.03063",
+ "Default View_TopLeft":"-227,-41",
+ "ExpandedHierarchyInLayout":"",
+ "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
+# -string -flagsOSRD
+preplace inst axis_dma_0 -pg 1 -lvl 1 -x 180 -y 130 -defaultsOSRD
+levelinfo -pg 1 0 180 360
+pagesize -pg 1 -db -bbox -sgen 0 0 360 250
+"
+}
+
diff --git a/Software/axi_crc_dma.h b/Software/axi_crc_dma.h
index e0e391f..9bf8447 100644
--- a/Software/axi_crc_dma.h
+++ b/Software/axi_crc_dma.h
@@ -42,7 +42,7 @@
// 1 : Output Reflected
// 31..2 : Reserved
// -------------------------------------------------------------------------------------------------
-// 0x28 - AWCache Register:
+// 0x28 - AxCache Register:
// 3.. 0 : AWCache for M_AXI Write
// 7.. 4 : ARCache for M_AXI Read
// 31..8 : Reserved