diff --git a/Hardware/axi_crc/axi_crc.cache/wt/project.wpc b/Hardware/axi_crc/axi_crc.cache/wt/project.wpc
index d9ddfe2..d7dd432 100644
--- a/Hardware/axi_crc/axi_crc.cache/wt/project.wpc
+++ b/Hardware/axi_crc/axi_crc.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:3
+6d6f64655f636f756e7465727c4755494d6f6465:4
eof:
diff --git a/Hardware/axi_crc/axi_crc.srcs/sources_1/bd/design_1/design_1.bd b/Hardware/axi_crc/axi_crc.srcs/sources_1/bd/design_1/design_1.bd
new file mode 100644
index 0000000..565ffff
--- /dev/null
+++ b/Hardware/axi_crc/axi_crc.srcs/sources_1/bd/design_1/design_1.bd
@@ -0,0 +1,13 @@
+{
+ "design": {
+ "design_info": {
+ "boundary_crc": "0x0",
+ "gen_directory": "../../../../axi_crc.gen/sources_1/bd/design_1",
+ "name": "design_1",
+ "rev_ctrl_bd_flag": "RevCtrlBdOff",
+ "synth_flow_mode": "Hierarchical",
+ "tool_version": "2023.1"
+ },
+ "design_tree": {}
+ }
+}
\ No newline at end of file
diff --git a/Hardware/axi_crc/axi_crc.xpr b/Hardware/axi_crc/axi_crc.xpr
index 87331c2..b9afe7b 100644
--- a/Hardware/axi_crc/axi_crc.xpr
+++ b/Hardware/axi_crc/axi_crc.xpr
@@ -119,6 +119,14 @@
+
+
+
+
+
+
+
+
diff --git a/Hardware/crc_axi_control.vhd b/Hardware/crc_axi_control.vhd
index 6f1ff87..f914e1a 100644
--- a/Hardware/crc_axi_control.vhd
+++ b/Hardware/crc_axi_control.vhd
@@ -4,52 +4,80 @@ use IEEE.NUMERIC_STD.ALL;
entity crc_axi_control is
generic (
- BRAM_AWIDTH : positve := 4
+ LUTRAM_AWIDTH : positive := 4;
+ PACKET_SIZE_WIDTH : positive := 16;
+ PACKET_NUM_WIDTH : positive := 16;
+ MAX_BURSTLEN : positive := 16;
);
port (
- CLK : in std_logic;
- RESETN : in std_logic;
+ CLK : in std_logic;
+ RESETN : in std_logic;
-- AXIL Registers
- start_ip : in std_logic;
- stop_ip : in std_logic;
- status : out std_logic;
- interrupt_enable : in std_logic;
- interrupt_status : out std_logic;
- interrupt_reset : in std_logic;
- raddr : in std_logic_vector(31 downto 0);
- waddr : in std_logic_vector(31 downto 0);
- packet_size : in std_logic_vector(15 downto 0);
- packet_number : in std_logic_vector(15 downto 0);
+ start_ip : in std_logic;
+ stop_ip : in std_logic;
+ status : out std_logic;
+ interrupt_enable : in std_logic;
+ interrupt_status : out std_logic;
+ interrupt_reset : in std_logic;
+ raddr : in std_logic_vector(31 downto 0);
+ waddr : in std_logic_vector(31 downto 0);
+ packet_size : in std_logic_vector(PACKET_SIZE_WIDTH-1 downto 0);
+ packet_number : in std_logic_vector(PACKET_NUM_WIDTH-1 downto 0);
-- Interface to Block-RAM
- ram_sel : out std_logic;
- ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
- ram_we : out std_logic;
- ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
- ram_re : out std_logic;
+ ram_sel : out std_logic;
+ ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
+ ram_we : out std_logic;
+ ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
+ ram_re : out std_logic;
-- Interface to AXI Master component
- axi_start : out std_logic;
- axi_write : out std_logic;
- axi_addr : out std_logic_vector(31 downto 0);
- axi_size : out std_logic_vector(3 downto 0);
- axi_idle : in std_logic;
+ axi_start : out std_logic;
+ axi_write : out std_logic;
+ axi_addr : out std_logic_vector(31 downto 0);
+ axi_size : out std_logic_vector(3 downto 0);
+ axi_idle : in std_logic;
-- Control signals for CRC component
- crc_en : out std_logic;
- cec_rst : out std_logic;
- byte_sel : out std_logic_vector(1 downto 0);
+ crc_en : out std_logic;
+ cec_rst : out std_logic;
+ byte_sel : out std_logic_vector(1 downto 0);
);
end entity;
architecture rtl of crc_axi_control is
- type state_t is (IDLE);
+ type state_t is (IDLE, READ_DATA);
signal state : state_t := IDLE;
+ signal packets_cnt : unsigned(PACKET_NUM_WIDTH-1 downto 0) := (others=>'0');
+ signal data_cnt : unsigned(PACKET_SIZE_WIDTH+PACKET_NUM_WIDTH-1 downto 0) := (others=>'0');
+ signal read_addr : unsigned(31 downto 0) := (others=>'0');
+ signal write_addr : unsigned(31 downto 0) := (others=>'0');
+
begin
+ process
+ begin
+ wait until rising_edge(CLK);
+ if RESETN = '0' then
+ state <= IDLE;
+ else
+ case state is
+ when IDLE =>
+ if start_ip = '1' then
+ packets_cnt <= unsigned(packet_number);
+ data_cnt <= unsigned(packet_size);
+ read_addr <= unsigned(raddr);
+ write_addr <= unsigned(waddr);
+ end if;
+
+ when others =>
+ null;
+ end case;
+ end if;
+ end process;
end architecture;
\ No newline at end of file
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bxml b/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bxml
index 8598f2c..ce4717f 100644
--- a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bxml
+++ b/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bxml
@@ -2,55 +2,10 @@
Composite Fileset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim_ooc.xdc b/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim_ooc.xdc
deleted file mode 100644
index 7fac2b2..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim_ooc.xdc
+++ /dev/null
@@ -1,10 +0,0 @@
-################################################################################
-
-# This XDC is used only for OOC mode of synthesis, implementation
-# This constraints file contains default clock frequencies to be used during
-# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
-# This constraints file is not used in normal top-down synthesis (default flow
-# of Vivado)
-################################################################################
-
-################################################################################
\ No newline at end of file
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xml b/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xml
index e16fc97..757d642 100644
--- a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xml
+++ b/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xml
@@ -1222,7 +1222,7 @@
-
+
@@ -1233,7 +1233,7 @@
-
+
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_0_2/crc_axi_master_sim_crc_axi_master_0_2.xml b/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_0_2/crc_axi_master_sim_crc_axi_master_0_2.xml
index 527c862..902f96e 100644
--- a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_0_2/crc_axi_master_sim_crc_axi_master_0_2.xml
+++ b/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_0_2/crc_axi_master_sim_crc_axi_master_0_2.xml
@@ -689,40 +689,6 @@
-
-
- xilinx_anylanguagebehavioralsimulation
- Simulation
- :vivado.xilinx.com:simulation
- crc_axi_master
-
-
- outputProductCRC
- 9:cf9c9909
-
-
-
-
- xilinx_vhdlsimulationwrapper
- VHDL Simulation Wrapper
- vhdlSource:vivado.xilinx.com:simulation.wrapper
- vhdl
- crc_axi_master_sim_crc_axi_master_0_2
-
- xilinx_vhdlsimulationwrapper_view_fileset
-
-
-
- GENtimestamp
- Fri Jan 31 00:46:20 UTC 2025
-
-
- outputProductCRC
- 9:cf9c9909
-
-
-
-
CLK
@@ -731,7 +697,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -743,7 +709,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -755,7 +721,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -767,7 +733,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -783,7 +749,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -799,7 +765,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -811,7 +777,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -827,7 +793,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -843,7 +809,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -855,7 +821,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -871,7 +837,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -887,7 +853,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -899,7 +865,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -911,7 +877,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -926,7 +892,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -945,7 +911,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -961,7 +927,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -977,7 +943,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -993,7 +959,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1009,7 +975,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1025,7 +991,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1041,7 +1007,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1053,7 +1019,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1065,7 +1031,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1084,7 +1050,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1103,7 +1069,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1122,7 +1088,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1137,7 +1103,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1152,7 +1118,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1167,7 +1133,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1186,7 +1152,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1202,7 +1168,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1218,7 +1184,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1234,7 +1200,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1250,7 +1216,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1266,7 +1232,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1282,7 +1248,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1294,7 +1260,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1309,7 +1275,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1328,7 +1294,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1344,7 +1310,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1356,7 +1322,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1372,7 +1338,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1384,7 +1350,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1396,7 +1362,7 @@
std_logic
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1415,7 +1381,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1434,7 +1400,7 @@
std_logic_vector
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1473,16 +1439,6 @@
ACTIVE_LOW
-
-
- xilinx_vhdlsimulationwrapper_view_fileset
-
- sim/crc_axi_master_sim_crc_axi_master_0_2.vhd
- vhdlSource
- xil_defaultlib
-
-
-
xilinx.com:module_ref:crc_axi_master:1.0
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/sim/crc_axi_master_sim.vhd b/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/sim/crc_axi_master_sim.vhd
deleted file mode 100644
index 9ebeff6..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/sim/crc_axi_master_sim.vhd
+++ /dev/null
@@ -1,293 +0,0 @@
---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
---Date : Fri Jan 31 01:46:20 2025
---Host : BiermannSurface running 64-bit major release (build 9200)
---Command : generate_target crc_axi_master_sim.bd
---Design : crc_axi_master_sim
---Purpose : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity crc_axi_master_sim is
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of crc_axi_master_sim : entity is "crc_axi_master_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=4,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
- attribute HW_HANDOFF : string;
- attribute HW_HANDOFF of crc_axi_master_sim : entity is "crc_axi_master_sim.hwdef";
-end crc_axi_master_sim;
-
-architecture STRUCTURE of crc_axi_master_sim is
- component crc_axi_master_sim_clk_rst_generator_0_0 is
- port (
- clk_in : in STD_LOGIC;
- rst_in : in STD_LOGIC;
- clk : out STD_LOGIC;
- rst_n : out STD_LOGIC;
- stop_simulation : in STD_LOGIC
- );
- end component crc_axi_master_sim_clk_rst_generator_0_0;
- component crc_axi_master_sim_axi3_slave_verif_0_0 is
- port (
- CLK : in STD_LOGIC;
- RESETN : in STD_LOGIC;
- S_AXI_ARVALID : in STD_LOGIC;
- S_AXI_ARREADY : out STD_LOGIC;
- S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
- S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_RVALID : out STD_LOGIC;
- S_AXI_RREADY : in STD_LOGIC;
- S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
- S_AXI_RLAST : out STD_LOGIC;
- S_AXI_AWVALID : in STD_LOGIC;
- S_AXI_AWREADY : out STD_LOGIC;
- S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_WVALID : in STD_LOGIC;
- S_AXI_WREADY : out STD_LOGIC;
- S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_WLAST : in STD_LOGIC;
- S_AXI_BVALID : out STD_LOGIC;
- S_AXI_BREADY : in STD_LOGIC;
- S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
- );
- end component crc_axi_master_sim_axi3_slave_verif_0_0;
- component crc_axi_master_sim_crc_axi_master_sim_c_0_0 is
- port (
- clk : in STD_LOGIC;
- resetn : in STD_LOGIC;
- start : out STD_LOGIC;
- write : out STD_LOGIC;
- addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- size : out STD_LOGIC_VECTOR ( 3 downto 0 );
- axi_idle : in STD_LOGIC
- );
- end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
- component crc_axi_master_sim_crc_axi_ram_0_0 is
- port (
- waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
- wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- we : in STD_LOGIC;
- raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
- rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- re : in STD_LOGIC
- );
- end component crc_axi_master_sim_crc_axi_ram_0_0;
- component crc_axi_master_sim_crc_axi_master_0_2 is
- port (
- CLK : in STD_LOGIC;
- RESETN : in STD_LOGIC;
- start : in STD_LOGIC;
- write : in STD_LOGIC;
- addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
- size : in STD_LOGIC_VECTOR ( 3 downto 0 );
- ip_idle : out STD_LOGIC;
- waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
- wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- we : out STD_LOGIC;
- raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
- rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- re : out STD_LOGIC;
- M_AXI_ARREADY : in STD_LOGIC;
- M_AXI_ARVALID : out STD_LOGIC;
- M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_RREADY : out STD_LOGIC;
- M_AXI_RVALID : in STD_LOGIC;
- M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_RLAST : in STD_LOGIC;
- M_AXI_AWREADY : in STD_LOGIC;
- M_AXI_AWVALID : out STD_LOGIC;
- M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_WREADY : in STD_LOGIC;
- M_AXI_WVALID : out STD_LOGIC;
- M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_WLAST : out STD_LOGIC;
- M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_BREADY : out STD_LOGIC;
- M_AXI_BVALID : in STD_LOGIC;
- M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
- );
- end component crc_axi_master_sim_crc_axi_master_0_2;
- signal clk_rst_generator_0_clk : STD_LOGIC;
- signal clk_rst_generator_0_rst_n : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
- signal crc_axi_master_0_idle : STD_LOGIC;
- signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_re : STD_LOGIC;
- signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_we : STD_LOGIC;
- signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_sim_c_0_start : STD_LOGIC;
- signal crc_axi_master_sim_c_0_write : STD_LOGIC;
- signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
-begin
-axi3_slave_verif_0: component crc_axi_master_sim_axi3_slave_verif_0_0
- port map (
- CLK => clk_rst_generator_0_clk,
- RESETN => clk_rst_generator_0_rst_n,
- S_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- S_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- S_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
- S_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- S_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
- S_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- S_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
- S_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- S_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- S_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- S_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
- S_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- S_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
- S_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
- S_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- S_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
- S_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- S_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
- S_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
- S_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
- S_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- S_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
- S_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- S_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
- S_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
- S_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- S_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID
- );
-clk_rst_generator_0: component crc_axi_master_sim_clk_rst_generator_0_0
- port map (
- clk => clk_rst_generator_0_clk,
- clk_in => '1',
- rst_in => '0',
- rst_n => clk_rst_generator_0_rst_n,
- stop_simulation => '0'
- );
-crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
- port map (
- CLK => clk_rst_generator_0_clk,
- M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- M_AXI_ARCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
- M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
- M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- M_AXI_ARPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
- M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
- M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
- M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- M_AXI_AWCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
- M_AXI_AWID(0) => NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED(0),
- M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- M_AXI_AWPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
- M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
- M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
- M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
- M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
- M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
- M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
- M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
- M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
- M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
- M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- M_AXI_WID(31 downto 0) => NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED(31 downto 0),
- M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
- M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
- M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
- RESETN => clk_rst_generator_0_rst_n,
- addr_axi(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
- ip_idle => crc_axi_master_0_idle,
- raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- re => crc_axi_master_0_re,
- size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
- start => crc_axi_master_sim_c_0_start,
- waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- we => crc_axi_master_0_we,
- write => crc_axi_master_sim_c_0_write
- );
-crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
- port map (
- addr(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
- axi_idle => crc_axi_master_0_idle,
- clk => clk_rst_generator_0_clk,
- resetn => clk_rst_generator_0_rst_n,
- size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
- start => crc_axi_master_sim_c_0_start,
- write => crc_axi_master_sim_c_0_write
- );
-crc_axi_ram_0: component crc_axi_master_sim_crc_axi_ram_0_0
- port map (
- raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- re => crc_axi_master_0_re,
- waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- we => crc_axi_master_0_we
- );
-end STRUCTURE;
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/synth/crc_axi_master_sim.vhd b/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/synth/crc_axi_master_sim.vhd
deleted file mode 100644
index 9ebeff6..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/synth/crc_axi_master_sim.vhd
+++ /dev/null
@@ -1,293 +0,0 @@
---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
---Date : Fri Jan 31 01:46:20 2025
---Host : BiermannSurface running 64-bit major release (build 9200)
---Command : generate_target crc_axi_master_sim.bd
---Design : crc_axi_master_sim
---Purpose : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity crc_axi_master_sim is
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of crc_axi_master_sim : entity is "crc_axi_master_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=4,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
- attribute HW_HANDOFF : string;
- attribute HW_HANDOFF of crc_axi_master_sim : entity is "crc_axi_master_sim.hwdef";
-end crc_axi_master_sim;
-
-architecture STRUCTURE of crc_axi_master_sim is
- component crc_axi_master_sim_clk_rst_generator_0_0 is
- port (
- clk_in : in STD_LOGIC;
- rst_in : in STD_LOGIC;
- clk : out STD_LOGIC;
- rst_n : out STD_LOGIC;
- stop_simulation : in STD_LOGIC
- );
- end component crc_axi_master_sim_clk_rst_generator_0_0;
- component crc_axi_master_sim_axi3_slave_verif_0_0 is
- port (
- CLK : in STD_LOGIC;
- RESETN : in STD_LOGIC;
- S_AXI_ARVALID : in STD_LOGIC;
- S_AXI_ARREADY : out STD_LOGIC;
- S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
- S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_RVALID : out STD_LOGIC;
- S_AXI_RREADY : in STD_LOGIC;
- S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
- S_AXI_RLAST : out STD_LOGIC;
- S_AXI_AWVALID : in STD_LOGIC;
- S_AXI_AWREADY : out STD_LOGIC;
- S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_WVALID : in STD_LOGIC;
- S_AXI_WREADY : out STD_LOGIC;
- S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_WLAST : in STD_LOGIC;
- S_AXI_BVALID : out STD_LOGIC;
- S_AXI_BREADY : in STD_LOGIC;
- S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
- );
- end component crc_axi_master_sim_axi3_slave_verif_0_0;
- component crc_axi_master_sim_crc_axi_master_sim_c_0_0 is
- port (
- clk : in STD_LOGIC;
- resetn : in STD_LOGIC;
- start : out STD_LOGIC;
- write : out STD_LOGIC;
- addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- size : out STD_LOGIC_VECTOR ( 3 downto 0 );
- axi_idle : in STD_LOGIC
- );
- end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
- component crc_axi_master_sim_crc_axi_ram_0_0 is
- port (
- waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
- wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- we : in STD_LOGIC;
- raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
- rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- re : in STD_LOGIC
- );
- end component crc_axi_master_sim_crc_axi_ram_0_0;
- component crc_axi_master_sim_crc_axi_master_0_2 is
- port (
- CLK : in STD_LOGIC;
- RESETN : in STD_LOGIC;
- start : in STD_LOGIC;
- write : in STD_LOGIC;
- addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
- size : in STD_LOGIC_VECTOR ( 3 downto 0 );
- ip_idle : out STD_LOGIC;
- waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
- wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- we : out STD_LOGIC;
- raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
- rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- re : out STD_LOGIC;
- M_AXI_ARREADY : in STD_LOGIC;
- M_AXI_ARVALID : out STD_LOGIC;
- M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_RREADY : out STD_LOGIC;
- M_AXI_RVALID : in STD_LOGIC;
- M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_RLAST : in STD_LOGIC;
- M_AXI_AWREADY : in STD_LOGIC;
- M_AXI_AWVALID : out STD_LOGIC;
- M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_WREADY : in STD_LOGIC;
- M_AXI_WVALID : out STD_LOGIC;
- M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_WLAST : out STD_LOGIC;
- M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_BREADY : out STD_LOGIC;
- M_AXI_BVALID : in STD_LOGIC;
- M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
- );
- end component crc_axi_master_sim_crc_axi_master_0_2;
- signal clk_rst_generator_0_clk : STD_LOGIC;
- signal clk_rst_generator_0_rst_n : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
- signal crc_axi_master_0_idle : STD_LOGIC;
- signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_re : STD_LOGIC;
- signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_0_we : STD_LOGIC;
- signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal crc_axi_master_sim_c_0_start : STD_LOGIC;
- signal crc_axi_master_sim_c_0_write : STD_LOGIC;
- signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
-begin
-axi3_slave_verif_0: component crc_axi_master_sim_axi3_slave_verif_0_0
- port map (
- CLK => clk_rst_generator_0_clk,
- RESETN => clk_rst_generator_0_rst_n,
- S_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- S_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- S_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
- S_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- S_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
- S_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- S_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
- S_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- S_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- S_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- S_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
- S_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- S_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
- S_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
- S_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- S_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
- S_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- S_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
- S_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
- S_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
- S_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- S_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
- S_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- S_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
- S_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
- S_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- S_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID
- );
-clk_rst_generator_0: component crc_axi_master_sim_clk_rst_generator_0_0
- port map (
- clk => clk_rst_generator_0_clk,
- clk_in => '1',
- rst_in => '0',
- rst_n => clk_rst_generator_0_rst_n,
- stop_simulation => '0'
- );
-crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
- port map (
- CLK => clk_rst_generator_0_clk,
- M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- M_AXI_ARCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
- M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
- M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- M_AXI_ARPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
- M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
- M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
- M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- M_AXI_AWCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
- M_AXI_AWID(0) => NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED(0),
- M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- M_AXI_AWPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
- M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
- M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
- M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
- M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
- M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
- M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
- M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
- M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
- M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
- M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- M_AXI_WID(31 downto 0) => NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED(31 downto 0),
- M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
- M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
- M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
- RESETN => clk_rst_generator_0_rst_n,
- addr_axi(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
- ip_idle => crc_axi_master_0_idle,
- raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- re => crc_axi_master_0_re,
- size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
- start => crc_axi_master_sim_c_0_start,
- waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- we => crc_axi_master_0_we,
- write => crc_axi_master_sim_c_0_write
- );
-crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
- port map (
- addr(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
- axi_idle => crc_axi_master_0_idle,
- clk => clk_rst_generator_0_clk,
- resetn => clk_rst_generator_0_rst_n,
- size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
- start => crc_axi_master_sim_c_0_start,
- write => crc_axi_master_sim_c_0_write
- );
-crc_axi_ram_0: component crc_axi_master_sim_crc_axi_ram_0_0
- port map (
- raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- re => crc_axi_master_0_re,
- waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- we => crc_axi_master_0_we
- );
-end STRUCTURE;
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/crc_axi_master_syn.bxml b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/crc_axi_master_syn.bxml
index aea5d01..582c097 100644
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/crc_axi_master_syn.bxml
+++ b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/crc_axi_master_syn.bxml
@@ -2,10 +2,10 @@
Composite Fileset
-
-
-
-
+
+
+
+
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_auto_us_0/crc_axi_master_syn_auto_us_0.xml b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_auto_us_0/crc_axi_master_syn_auto_us_0.xml
index 09aee83..9f8fe2c 100644
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_auto_us_0/crc_axi_master_syn_auto_us_0.xml
+++ b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_auto_us_0/crc_axi_master_syn_auto_us_0.xml
@@ -1746,7 +1746,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1762,7 +1762,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1782,7 +1782,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1809,7 +1809,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1836,7 +1836,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1863,7 +1863,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1890,7 +1890,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1917,7 +1917,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1944,7 +1944,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1971,7 +1971,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -1998,7 +1998,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2025,7 +2025,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2048,7 +2048,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2071,7 +2071,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2095,7 +2095,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2122,7 +2122,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2145,7 +2145,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2168,7 +2168,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2191,7 +2191,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2215,7 +2215,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2239,7 +2239,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2259,7 +2259,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2279,7 +2279,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2306,7 +2306,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2333,7 +2333,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2360,7 +2360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2387,7 +2387,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2414,7 +2414,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2441,7 +2441,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2468,7 +2468,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2495,7 +2495,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2522,7 +2522,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2549,7 +2549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2572,7 +2572,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2595,7 +2595,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2619,7 +2619,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2643,7 +2643,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2667,7 +2667,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2687,7 +2687,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2707,7 +2707,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2727,7 +2727,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2750,7 +2750,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2773,7 +2773,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2800,7 +2800,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2824,7 +2824,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2848,7 +2848,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2872,7 +2872,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2896,7 +2896,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2920,7 +2920,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2944,7 +2944,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2968,7 +2968,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -2992,7 +2992,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3012,7 +3012,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3032,7 +3032,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3059,7 +3059,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3083,7 +3083,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3103,7 +3103,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3123,7 +3123,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3143,7 +3143,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3170,7 +3170,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3193,7 +3193,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3216,7 +3216,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3240,7 +3240,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3264,7 +3264,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3288,7 +3288,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3312,7 +3312,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3336,7 +3336,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3360,7 +3360,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3384,7 +3384,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3408,7 +3408,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3432,7 +3432,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3452,7 +3452,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3472,7 +3472,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3499,7 +3499,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3526,7 +3526,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3549,7 +3549,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3572,7 +3572,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -3595,7 +3595,7 @@
wire
xilinx_verilogsynthesis
- xilinx_verilogbehavioralsimulation
+ xilinx_systemcsimulation
@@ -4387,7 +4387,7 @@
-
+
@@ -4420,31 +4420,32 @@
-
+
+
-
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
+
+
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xml b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xml
index 6b06736..995026b 100644
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xml
+++ b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xml
@@ -40687,22 +40687,22 @@
-
-
+
+
-
-
-
-
-
-
+
+
+
+
+
+
-
-
+
+
@@ -40710,7 +40710,7 @@
-
+
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port.bxml b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port.bxml
index f43b2e9..083355c 100644
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port.bxml
+++ b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port.bxml
@@ -2,55 +2,10 @@
Composite Fileset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port_ooc.xdc b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port_ooc.xdc
deleted file mode 100644
index 5ee9a4d..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port_ooc.xdc
+++ /dev/null
@@ -1,14 +0,0 @@
-################################################################################
-
-# This XDC is used only for OOC mode of synthesis, implementation
-# This constraints file contains default clock frequencies to be used during
-# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
-# This constraints file is not used in normal top-down synthesis (default flow
-# of Vivado)
-################################################################################
-create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 10 [get_pins PS/processing_system7_0/FCLK_CLK0]
-create_clock -name PS_processing_system7_0_FCLK_CLK1 -period 8 [get_pins PS/processing_system7_0/FCLK_CLK1]
-create_clock -name PS_processing_system7_0_FCLK_CLK2 -period 5 [get_pins PS/processing_system7_0/FCLK_CLK2]
-create_clock -name PS_processing_system7_0_FCLK_CLK3 -period 15 [get_pins PS/processing_system7_0/FCLK_CLK3]
-
-################################################################################
\ No newline at end of file
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.xml b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.xml
index ad80792..f536ea2 100644
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.xml
+++ b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.xml
@@ -514,7 +514,7 @@
CLK_DOMAIN
- crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0
+
none
@@ -652,7 +652,7 @@
CLK_DOMAIN
- crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0
+
none
@@ -689,101 +689,6 @@
-
-
- xilinx_anylanguagebehavioralsimulation
- Simulation
- :vivado.xilinx.com:simulation
- crc_axi_master
-
-
- outputProductCRC
- 9:b8bf5ced
-
-
-
-
- xilinx_anylanguagesynthesis
- Synthesis
- :vivado.xilinx.com:synthesis
- crc_axi_master
-
-
- outputProductCRC
- 9:679a87f9
-
-
-
-
- xilinx_externalfiles
- External Files
- :vivado.xilinx.com:external.files
-
- xilinx_externalfiles_view_fileset
-
-
-
- GENtimestamp
- Fri Jan 31 00:49:53 UTC 2025
-
-
- outputProductCRC
- 9:679a87f9
-
-
-
-
- xilinx_synthesisconstraints
- Synthesis Constraints
- :vivado.xilinx.com:synthesis.constraints
-
-
- outputProductCRC
- 9:679a87f9
-
-
-
-
- xilinx_vhdlsimulationwrapper
- VHDL Simulation Wrapper
- vhdlSource:vivado.xilinx.com:simulation.wrapper
- vhdl
- crc_axi_master_syn_HP_Port_crc_axi_master_0_0
-
- xilinx_vhdlsimulationwrapper_view_fileset
-
-
-
- GENtimestamp
- Fri Jan 31 00:48:45 UTC 2025
-
-
- outputProductCRC
- 9:b8bf5ced
-
-
-
-
- xilinx_vhdlsynthesiswrapper
- VHDL Synthesis Wrapper
- vhdlSource:vivado.xilinx.com:synthesis.wrapper
- vhdl
- crc_axi_master_syn_HP_Port_crc_axi_master_0_0
-
- xilinx_vhdlsynthesiswrapper_view_fileset
-
-
-
- GENtimestamp
- Fri Jan 31 00:48:45 UTC 2025
-
-
- outputProductCRC
- 9:679a87f9
-
-
-
-
CLK
@@ -792,8 +697,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -805,8 +709,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -818,8 +721,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -831,8 +733,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -848,8 +749,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -865,8 +765,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -878,8 +777,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -895,8 +793,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -912,8 +809,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -925,8 +821,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -942,8 +837,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -959,8 +853,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -972,8 +865,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -985,8 +877,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1001,8 +892,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1021,8 +911,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1038,8 +927,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1055,8 +943,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1072,8 +959,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1089,8 +975,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1106,8 +991,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1123,8 +1007,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1136,8 +1019,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1149,8 +1031,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1169,8 +1050,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1189,8 +1069,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1209,8 +1088,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1225,8 +1103,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1241,8 +1118,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1257,8 +1133,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1277,8 +1152,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1294,8 +1168,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1311,8 +1184,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1328,8 +1200,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1345,8 +1216,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1362,8 +1232,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1379,8 +1248,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1392,8 +1260,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1408,8 +1275,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1428,8 +1294,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1445,8 +1310,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1458,8 +1322,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1475,8 +1338,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1488,8 +1350,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1501,8 +1362,7 @@
std_logic
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1521,8 +1381,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1541,8 +1400,7 @@
std_logic_vector
- xilinx_anylanguagesynthesis
- xilinx_anylanguagebehavioralsimulation
+ dummy_view
@@ -1581,60 +1439,6 @@
ACTIVE_LOW
-
-
- xilinx_externalfiles_view_fileset
-
- crc_axi_master_syn_HP_Port_crc_axi_master_0_0.dcp
- dcp
- USED_IN_implementation
- USED_IN_synthesis
- xil_defaultlib
-
-
- crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.v
- verilogSource
- USED_IN_synth_blackbox_stub
- xil_defaultlib
-
-
- crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.vhdl
- vhdlSource
- USED_IN_synth_blackbox_stub
- xil_defaultlib
-
-
- crc_axi_master_syn_HP_Port_crc_axi_master_0_0_sim_netlist.v
- verilogSource
- USED_IN_simulation
- USED_IN_single_language
- xil_defaultlib
-
-
- crc_axi_master_syn_HP_Port_crc_axi_master_0_0_sim_netlist.vhdl
- vhdlSource
- USED_IN_simulation
- USED_IN_single_language
- xil_defaultlib
-
-
-
- xilinx_vhdlsimulationwrapper_view_fileset
-
- sim/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd
- vhdlSource
- xil_defaultlib
-
-
-
- xilinx_vhdlsynthesiswrapper_view_fileset
-
- synth/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd
- vhdlSource
- xil_defaultlib
-
-
-
xilinx.com:module_ref:crc_axi_master:1.0
@@ -1671,7 +1475,7 @@
-
+
@@ -1679,7 +1483,7 @@
-
+
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_sim_netlist.v b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_sim_netlist.v
deleted file mode 100644
index 80f10cf..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_sim_netlist.v
+++ /dev/null
@@ -1,1619 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-// Date : Fri Jan 31 01:49:53 2025
-// Host : BiermannSurface running 64-bit major release (build 9200)
-// Command : write_verilog -force -mode funcsim
-// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_sim_netlist.v
-// Design : crc_axi_master_syn_HP_Port_crc_axi_master_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z020clg400-1
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "crc_axi_master_syn_HP_Port_crc_axi_master_0_0,crc_axi_master,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *)
-(* x_core_info = "crc_axi_master,Vivado 2023.1" *)
-(* NotValidForBitStream *)
-module crc_axi_master_syn_HP_Port_crc_axi_master_0_0
- (CLK,
- RESETN,
- start,
- write,
- addr_axi,
- size,
- ip_idle,
- waddr,
- wdata,
- we,
- raddr,
- rdata,
- re,
- M_AXI_ARREADY,
- M_AXI_ARVALID,
- M_AXI_ARADDR,
- M_AXI_ARID,
- M_AXI_ARLEN,
- M_AXI_ARSIZE,
- M_AXI_ARBURST,
- M_AXI_ARPROT,
- M_AXI_ARCACHE,
- M_AXI_RREADY,
- M_AXI_RVALID,
- M_AXI_RDATA,
- M_AXI_RRESP,
- M_AXI_RID,
- M_AXI_RLAST,
- M_AXI_AWREADY,
- M_AXI_AWVALID,
- M_AXI_AWADDR,
- M_AXI_AWLEN,
- M_AXI_AWSIZE,
- M_AXI_AWID,
- M_AXI_AWBURST,
- M_AXI_AWPROT,
- M_AXI_AWCACHE,
- M_AXI_WREADY,
- M_AXI_WVALID,
- M_AXI_WDATA,
- M_AXI_WSTRB,
- M_AXI_WLAST,
- M_AXI_WID,
- M_AXI_BREADY,
- M_AXI_BVALID,
- M_AXI_BID,
- M_AXI_BRESP);
- (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input CLK;
- (* x_interface_info = "xilinx.com:signal:reset:1.0 RESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input RESETN;
- input start;
- input write;
- input [31:0]addr_axi;
- input [3:0]size;
- output ip_idle;
- output [3:0]waddr;
- output [31:0]wdata;
- output we;
- output [3:0]raddr;
- input [31:0]rdata;
- output re;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input M_AXI_ARREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output M_AXI_ARVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]M_AXI_ARADDR;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output [0:0]M_AXI_ARID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [3:0]M_AXI_ARLEN;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]M_AXI_ARSIZE;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]M_AXI_ARBURST;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]M_AXI_ARPROT;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]M_AXI_ARCACHE;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output M_AXI_RREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input M_AXI_RVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]M_AXI_RDATA;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]M_AXI_RRESP;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input [0:0]M_AXI_RID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input M_AXI_RLAST;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input M_AXI_AWREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output M_AXI_AWVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]M_AXI_AWADDR;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [3:0]M_AXI_AWLEN;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]M_AXI_AWSIZE;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output [0:0]M_AXI_AWID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]M_AXI_AWBURST;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]M_AXI_AWPROT;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]M_AXI_AWCACHE;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input M_AXI_WREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output M_AXI_WVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]M_AXI_WDATA;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]M_AXI_WSTRB;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output M_AXI_WLAST;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI WID" *) output [31:0]M_AXI_WID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output M_AXI_BREADY;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input M_AXI_BVALID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input [31:0]M_AXI_BID;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]M_AXI_BRESP;
-
- wire \ ;
- wire \ ;
- wire CLK;
- wire [31:0]M_AXI_ARADDR;
- wire [3:0]M_AXI_ARLEN;
- wire M_AXI_ARREADY;
- wire M_AXI_ARVALID;
- wire [31:0]M_AXI_AWADDR;
- wire [3:0]M_AXI_AWLEN;
- wire M_AXI_AWREADY;
- wire M_AXI_AWVALID;
- wire [31:0]M_AXI_RDATA;
- wire M_AXI_RLAST;
- wire M_AXI_RVALID;
- wire M_AXI_WLAST;
- wire M_AXI_WREADY;
- wire M_AXI_WVALID;
- wire RESETN;
- wire [31:0]addr_axi;
- wire ip_idle;
- wire [31:0]rdata;
- wire re;
- wire [3:0]size;
- wire start;
- wire [3:0]waddr;
- wire write;
-
- assign M_AXI_ARBURST[1] = \ ;
- assign M_AXI_ARBURST[0] = \ ;
- assign M_AXI_ARCACHE[3] = \ ;
- assign M_AXI_ARCACHE[2] = \ ;
- assign M_AXI_ARCACHE[1] = \ ;
- assign M_AXI_ARCACHE[0] = \ ;
- assign M_AXI_ARID[0] = \ ;
- assign M_AXI_ARPROT[2] = \ ;
- assign M_AXI_ARPROT[1] = \ ;
- assign M_AXI_ARPROT[0] = \ ;
- assign M_AXI_ARSIZE[2] = \ ;
- assign M_AXI_ARSIZE[1] = \ ;
- assign M_AXI_ARSIZE[0] = \ ;
- assign M_AXI_AWBURST[1] = \ ;
- assign M_AXI_AWBURST[0] = \ ;
- assign M_AXI_AWCACHE[3] = \ ;
- assign M_AXI_AWCACHE[2] = \ ;
- assign M_AXI_AWCACHE[1] = \ ;
- assign M_AXI_AWCACHE[0] = \ ;
- assign M_AXI_AWID[0] = \ ;
- assign M_AXI_AWPROT[2] = \ ;
- assign M_AXI_AWPROT[1] = \ ;
- assign M_AXI_AWPROT[0] = \ ;
- assign M_AXI_AWSIZE[2] = \ ;
- assign M_AXI_AWSIZE[1] = \ ;
- assign M_AXI_AWSIZE[0] = \ ;
- assign M_AXI_BREADY = \ ;
- assign M_AXI_RREADY = \ ;
- assign M_AXI_WDATA[31:0] = rdata;
- assign M_AXI_WID[31] = \ ;
- assign M_AXI_WID[30] = \ ;
- assign M_AXI_WID[29] = \ ;
- assign M_AXI_WID[28] = \ ;
- assign M_AXI_WID[27] = \ ;
- assign M_AXI_WID[26] = \ ;
- assign M_AXI_WID[25] = \ ;
- assign M_AXI_WID[24] = \ ;
- assign M_AXI_WID[23] = \ ;
- assign M_AXI_WID[22] = \ ;
- assign M_AXI_WID[21] = \ ;
- assign M_AXI_WID[20] = \ ;
- assign M_AXI_WID[19] = \ ;
- assign M_AXI_WID[18] = \ ;
- assign M_AXI_WID[17] = \ ;
- assign M_AXI_WID[16] = \ ;
- assign M_AXI_WID[15] = \ ;
- assign M_AXI_WID[14] = \ ;
- assign M_AXI_WID[13] = \ ;
- assign M_AXI_WID[12] = \ ;
- assign M_AXI_WID[11] = \ ;
- assign M_AXI_WID[10] = \ ;
- assign M_AXI_WID[9] = \ ;
- assign M_AXI_WID[8] = \ ;
- assign M_AXI_WID[7] = \ ;
- assign M_AXI_WID[6] = \ ;
- assign M_AXI_WID[5] = \ ;
- assign M_AXI_WID[4] = \ ;
- assign M_AXI_WID[3] = \ ;
- assign M_AXI_WID[2] = \ ;
- assign M_AXI_WID[1] = \ ;
- assign M_AXI_WID[0] = \ ;
- assign M_AXI_WSTRB[3] = \ ;
- assign M_AXI_WSTRB[2] = \ ;
- assign M_AXI_WSTRB[1] = \ ;
- assign M_AXI_WSTRB[0] = \ ;
- assign raddr[3:0] = waddr;
- assign wdata[31:0] = M_AXI_RDATA;
- assign we = M_AXI_RVALID;
- GND GND
- (.G(\ ));
- crc_axi_master_syn_HP_Port_crc_axi_master_0_0_crc_axi_master U0
- (.CLK(CLK),
- .M_AXI_ARADDR(M_AXI_ARADDR),
- .M_AXI_ARLEN(M_AXI_ARLEN),
- .M_AXI_ARREADY(M_AXI_ARREADY),
- .M_AXI_ARVALID(M_AXI_ARVALID),
- .M_AXI_AWADDR(M_AXI_AWADDR),
- .M_AXI_AWLEN(M_AXI_AWLEN),
- .M_AXI_AWREADY(M_AXI_AWREADY),
- .M_AXI_AWVALID(M_AXI_AWVALID),
- .M_AXI_RLAST(M_AXI_RLAST),
- .M_AXI_RVALID(M_AXI_RVALID),
- .M_AXI_WLAST(M_AXI_WLAST),
- .M_AXI_WREADY(M_AXI_WREADY),
- .M_AXI_WVALID(M_AXI_WVALID),
- .RESETN(RESETN),
- .addr_axi(addr_axi),
- .ip_idle(ip_idle),
- .re(re),
- .size(size),
- .start(start),
- .waddr(waddr),
- .write(write));
- VCC VCC
- (.P(\ ));
-endmodule
-
-(* ORIG_REF_NAME = "crc_axi_master" *)
-module crc_axi_master_syn_HP_Port_crc_axi_master_0_0_crc_axi_master
- (waddr,
- M_AXI_ARADDR,
- M_AXI_ARLEN,
- M_AXI_AWADDR,
- M_AXI_AWLEN,
- re,
- ip_idle,
- M_AXI_ARVALID,
- M_AXI_AWVALID,
- M_AXI_WVALID,
- M_AXI_WLAST,
- write,
- M_AXI_AWREADY,
- CLK,
- addr_axi,
- size,
- M_AXI_RLAST,
- M_AXI_RVALID,
- start,
- RESETN,
- M_AXI_WREADY,
- M_AXI_ARREADY);
- output [3:0]waddr;
- output [31:0]M_AXI_ARADDR;
- output [3:0]M_AXI_ARLEN;
- output [31:0]M_AXI_AWADDR;
- output [3:0]M_AXI_AWLEN;
- output re;
- output ip_idle;
- output M_AXI_ARVALID;
- output M_AXI_AWVALID;
- output M_AXI_WVALID;
- output M_AXI_WLAST;
- input write;
- input M_AXI_AWREADY;
- input CLK;
- input [31:0]addr_axi;
- input [3:0]size;
- input M_AXI_RLAST;
- input M_AXI_RVALID;
- input start;
- input RESETN;
- input M_AXI_WREADY;
- input M_AXI_ARREADY;
-
- wire CLK;
- wire \FSM_sequential_state[0]_i_1_n_0 ;
- wire \FSM_sequential_state[1]_i_1_n_0 ;
- wire \FSM_sequential_state[2]_i_1_n_0 ;
- wire \FSM_sequential_state[2]_i_2_n_0 ;
- wire \FSM_sequential_state[2]_i_3_n_0 ;
- wire [31:0]M_AXI_ARADDR;
- wire \M_AXI_ARADDR[31]_i_1_n_0 ;
- wire [3:0]M_AXI_ARLEN;
- wire M_AXI_ARREADY;
- wire M_AXI_ARVALID;
- wire M_AXI_ARVALID_i_1_n_0;
- wire M_AXI_ARVALID_i_2_n_0;
- wire [31:0]M_AXI_AWADDR;
- wire \M_AXI_AWADDR[31]_i_1_n_0 ;
- wire [3:0]M_AXI_AWLEN;
- wire M_AXI_AWREADY;
- wire M_AXI_AWVALID;
- wire M_AXI_AWVALID_i_1_n_0;
- wire M_AXI_RLAST;
- wire M_AXI_RVALID;
- wire M_AXI_WLAST;
- wire M_AXI_WLAST_i_1_n_0;
- wire M_AXI_WLAST_i_2_n_0;
- wire M_AXI_WLAST_i_3_n_0;
- wire M_AXI_WLAST_i_4_n_0;
- wire M_AXI_WLAST_i_5_n_0;
- wire M_AXI_WREADY;
- wire M_AXI_WVALID;
- wire M_AXI_WVALID_i_1_n_0;
- wire M_AXI_WVALID_i_2_n_0;
- wire RESETN;
- wire \addr_LUTRAM[0]_i_1_n_0 ;
- wire \addr_LUTRAM[1]_i_1_n_0 ;
- wire \addr_LUTRAM[2]_i_1_n_0 ;
- wire \addr_LUTRAM[3]_i_1_n_0 ;
- wire \addr_LUTRAM[3]_i_2_n_0 ;
- wire \addr_LUTRAM[3]_i_3_n_0 ;
- wire \addr_LUTRAM[3]_i_4_n_0 ;
- wire [31:0]addr_axi;
- wire [31:0]addr_mem;
- wire \addr_mem[31]_i_1_n_0 ;
- wire [4:0]data_cnt0_in;
- wire \data_cnt[2]_i_2_n_0 ;
- wire \data_cnt[4]_i_1_n_0 ;
- wire \data_cnt[4]_i_3_n_0 ;
- wire \data_cnt[4]_i_4_n_0 ;
- wire \data_cnt[4]_i_5_n_0 ;
- wire \data_cnt_reg_n_0_[0] ;
- wire \data_cnt_reg_n_0_[1] ;
- wire \data_cnt_reg_n_0_[2] ;
- wire \data_cnt_reg_n_0_[3] ;
- wire \data_cnt_reg_n_0_[4] ;
- wire ip_idle;
- wire ip_idle_i_1_n_0;
- wire ip_idle_i_2_n_0;
- wire ip_idle_i_3_n_0;
- wire ip_idle_i_4_n_0;
- wire re;
- wire [3:0]size;
- wire start;
- wire [2:0]state;
- wire [3:0]waddr;
- wire write;
-
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h00FF3D00))
- \FSM_sequential_state[0]_i_1
- (.I0(write),
- .I1(state[1]),
- .I2(state[2]),
- .I3(\FSM_sequential_state[2]_i_2_n_0 ),
- .I4(state[0]),
- .O(\FSM_sequential_state[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'h05FFD000))
- \FSM_sequential_state[1]_i_1
- (.I0(state[2]),
- .I1(M_AXI_AWREADY),
- .I2(state[0]),
- .I3(\FSM_sequential_state[2]_i_2_n_0 ),
- .I4(state[1]),
- .O(\FSM_sequential_state[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0F03FFFF02020000))
- \FSM_sequential_state[2]_i_1
- (.I0(write),
- .I1(state[0]),
- .I2(state[1]),
- .I3(M_AXI_AWREADY),
- .I4(\FSM_sequential_state[2]_i_2_n_0 ),
- .I5(state[2]),
- .O(\FSM_sequential_state[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hACACFCFCACAC0CFC))
- \FSM_sequential_state[2]_i_2
- (.I0(M_AXI_WVALID_i_2_n_0),
- .I1(\FSM_sequential_state[2]_i_3_n_0 ),
- .I2(state[2]),
- .I3(state[0]),
- .I4(state[1]),
- .I5(M_AXI_AWREADY),
- .O(\FSM_sequential_state[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hC0AAFFFFC0AAFF00))
- \FSM_sequential_state[2]_i_3
- (.I0(M_AXI_ARREADY),
- .I1(M_AXI_RLAST),
- .I2(M_AXI_RVALID),
- .I3(state[0]),
- .I4(state[1]),
- .I5(start),
- .O(\FSM_sequential_state[2]_i_3_n_0 ));
- (* FSM_ENCODED_STATES = "r_wait_req_accept:010,read_data:011,w_wait_req_accept:101,w_req:100,r_req:001,idle:000,write_data:110" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_state_reg[0]
- (.C(CLK),
- .CE(1'b1),
- .D(\FSM_sequential_state[0]_i_1_n_0 ),
- .Q(state[0]),
- .R(M_AXI_ARVALID_i_1_n_0));
- (* FSM_ENCODED_STATES = "r_wait_req_accept:010,read_data:011,w_wait_req_accept:101,w_req:100,r_req:001,idle:000,write_data:110" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_state_reg[1]
- (.C(CLK),
- .CE(1'b1),
- .D(\FSM_sequential_state[1]_i_1_n_0 ),
- .Q(state[1]),
- .R(M_AXI_ARVALID_i_1_n_0));
- (* FSM_ENCODED_STATES = "r_wait_req_accept:010,read_data:011,w_wait_req_accept:101,w_req:100,r_req:001,idle:000,write_data:110" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_state_reg[2]
- (.C(CLK),
- .CE(1'b1),
- .D(\FSM_sequential_state[2]_i_1_n_0 ),
- .Q(state[2]),
- .R(M_AXI_ARVALID_i_1_n_0));
- LUT3 #(
- .INIT(8'h04))
- \M_AXI_ARADDR[31]_i_1
- (.I0(state[1]),
- .I1(state[0]),
- .I2(state[2]),
- .O(\M_AXI_ARADDR[31]_i_1_n_0 ));
- FDRE \M_AXI_ARADDR_reg[0]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[0]),
- .Q(M_AXI_ARADDR[0]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[10]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[10]),
- .Q(M_AXI_ARADDR[10]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[11]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[11]),
- .Q(M_AXI_ARADDR[11]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[12]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[12]),
- .Q(M_AXI_ARADDR[12]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[13]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[13]),
- .Q(M_AXI_ARADDR[13]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[14]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[14]),
- .Q(M_AXI_ARADDR[14]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[15]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[15]),
- .Q(M_AXI_ARADDR[15]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[16]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[16]),
- .Q(M_AXI_ARADDR[16]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[17]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[17]),
- .Q(M_AXI_ARADDR[17]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[18]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[18]),
- .Q(M_AXI_ARADDR[18]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[19]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[19]),
- .Q(M_AXI_ARADDR[19]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[1]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[1]),
- .Q(M_AXI_ARADDR[1]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[20]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[20]),
- .Q(M_AXI_ARADDR[20]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[21]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[21]),
- .Q(M_AXI_ARADDR[21]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[22]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[22]),
- .Q(M_AXI_ARADDR[22]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[23]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[23]),
- .Q(M_AXI_ARADDR[23]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[24]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[24]),
- .Q(M_AXI_ARADDR[24]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[25]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[25]),
- .Q(M_AXI_ARADDR[25]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[26]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[26]),
- .Q(M_AXI_ARADDR[26]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[27]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[27]),
- .Q(M_AXI_ARADDR[27]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[28]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[28]),
- .Q(M_AXI_ARADDR[28]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[29]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[29]),
- .Q(M_AXI_ARADDR[29]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[2]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[2]),
- .Q(M_AXI_ARADDR[2]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[30]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[30]),
- .Q(M_AXI_ARADDR[30]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[31]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[31]),
- .Q(M_AXI_ARADDR[31]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[3]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[3]),
- .Q(M_AXI_ARADDR[3]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[4]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[4]),
- .Q(M_AXI_ARADDR[4]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[5]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[5]),
- .Q(M_AXI_ARADDR[5]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[6]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[6]),
- .Q(M_AXI_ARADDR[6]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[7]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[7]),
- .Q(M_AXI_ARADDR[7]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[8]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[8]),
- .Q(M_AXI_ARADDR[8]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARADDR_reg[9]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(addr_mem[9]),
- .Q(M_AXI_ARADDR[9]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARLEN_reg[0]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(size[0]),
- .Q(M_AXI_ARLEN[0]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARLEN_reg[1]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(size[1]),
- .Q(M_AXI_ARLEN[1]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARLEN_reg[2]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(size[2]),
- .Q(M_AXI_ARLEN[2]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_ARLEN_reg[3]
- (.C(CLK),
- .CE(\M_AXI_ARADDR[31]_i_1_n_0 ),
- .D(size[3]),
- .Q(M_AXI_ARLEN[3]),
- .R(M_AXI_ARVALID_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- M_AXI_ARVALID_i_1
- (.I0(RESETN),
- .O(M_AXI_ARVALID_i_1_n_0));
- LUT5 #(
- .INIT(32'hFDFF0030))
- M_AXI_ARVALID_i_2
- (.I0(M_AXI_ARREADY),
- .I1(state[2]),
- .I2(state[0]),
- .I3(state[1]),
- .I4(M_AXI_ARVALID),
- .O(M_AXI_ARVALID_i_2_n_0));
- FDRE #(
- .INIT(1'b0))
- M_AXI_ARVALID_reg
- (.C(CLK),
- .CE(1'b1),
- .D(M_AXI_ARVALID_i_2_n_0),
- .Q(M_AXI_ARVALID),
- .R(M_AXI_ARVALID_i_1_n_0));
- LUT3 #(
- .INIT(8'h02))
- \M_AXI_AWADDR[31]_i_1
- (.I0(state[2]),
- .I1(state[0]),
- .I2(state[1]),
- .O(\M_AXI_AWADDR[31]_i_1_n_0 ));
- FDRE \M_AXI_AWADDR_reg[0]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[0]),
- .Q(M_AXI_AWADDR[0]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[10]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[10]),
- .Q(M_AXI_AWADDR[10]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[11]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[11]),
- .Q(M_AXI_AWADDR[11]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[12]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[12]),
- .Q(M_AXI_AWADDR[12]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[13]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[13]),
- .Q(M_AXI_AWADDR[13]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[14]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[14]),
- .Q(M_AXI_AWADDR[14]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[15]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[15]),
- .Q(M_AXI_AWADDR[15]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[16]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[16]),
- .Q(M_AXI_AWADDR[16]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[17]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[17]),
- .Q(M_AXI_AWADDR[17]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[18]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[18]),
- .Q(M_AXI_AWADDR[18]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[19]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[19]),
- .Q(M_AXI_AWADDR[19]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[1]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[1]),
- .Q(M_AXI_AWADDR[1]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[20]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[20]),
- .Q(M_AXI_AWADDR[20]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[21]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[21]),
- .Q(M_AXI_AWADDR[21]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[22]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[22]),
- .Q(M_AXI_AWADDR[22]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[23]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[23]),
- .Q(M_AXI_AWADDR[23]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[24]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[24]),
- .Q(M_AXI_AWADDR[24]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[25]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[25]),
- .Q(M_AXI_AWADDR[25]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[26]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[26]),
- .Q(M_AXI_AWADDR[26]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[27]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[27]),
- .Q(M_AXI_AWADDR[27]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[28]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[28]),
- .Q(M_AXI_AWADDR[28]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[29]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[29]),
- .Q(M_AXI_AWADDR[29]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[2]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[2]),
- .Q(M_AXI_AWADDR[2]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[30]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[30]),
- .Q(M_AXI_AWADDR[30]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[31]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[31]),
- .Q(M_AXI_AWADDR[31]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[3]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[3]),
- .Q(M_AXI_AWADDR[3]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[4]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[4]),
- .Q(M_AXI_AWADDR[4]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[5]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[5]),
- .Q(M_AXI_AWADDR[5]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[6]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[6]),
- .Q(M_AXI_AWADDR[6]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[7]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[7]),
- .Q(M_AXI_AWADDR[7]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[8]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[8]),
- .Q(M_AXI_AWADDR[8]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWADDR_reg[9]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(addr_mem[9]),
- .Q(M_AXI_AWADDR[9]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWLEN_reg[0]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(size[0]),
- .Q(M_AXI_AWLEN[0]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWLEN_reg[1]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(size[1]),
- .Q(M_AXI_AWLEN[1]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWLEN_reg[2]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(size[2]),
- .Q(M_AXI_AWLEN[2]),
- .R(M_AXI_ARVALID_i_1_n_0));
- FDRE \M_AXI_AWLEN_reg[3]
- (.C(CLK),
- .CE(\M_AXI_AWADDR[31]_i_1_n_0 ),
- .D(size[3]),
- .Q(M_AXI_AWLEN[3]),
- .R(M_AXI_ARVALID_i_1_n_0));
- LUT5 #(
- .INIT(32'hBFFF0404))
- M_AXI_AWVALID_i_1
- (.I0(state[1]),
- .I1(state[2]),
- .I2(state[0]),
- .I3(M_AXI_AWREADY),
- .I4(M_AXI_AWVALID),
- .O(M_AXI_AWVALID_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- M_AXI_AWVALID_reg
- (.C(CLK),
- .CE(1'b1),
- .D(M_AXI_AWVALID_i_1_n_0),
- .Q(M_AXI_AWVALID),
- .R(M_AXI_ARVALID_i_1_n_0));
- LUT6 #(
- .INIT(64'h444FFFFF444F0000))
- M_AXI_WLAST_i_1
- (.I0(state[1]),
- .I1(M_AXI_AWREADY),
- .I2(state[0]),
- .I3(M_AXI_WLAST_i_2_n_0),
- .I4(M_AXI_WLAST_i_3_n_0),
- .I5(M_AXI_WLAST),
- .O(M_AXI_WLAST_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT5 #(
- .INIT(32'h00000004))
- M_AXI_WLAST_i_2
- (.I0(\data_cnt_reg_n_0_[1] ),
- .I1(\data_cnt_reg_n_0_[0] ),
- .I2(\data_cnt_reg_n_0_[2] ),
- .I3(\data_cnt_reg_n_0_[3] ),
- .I4(\data_cnt_reg_n_0_[4] ),
- .O(M_AXI_WLAST_i_2_n_0));
- LUT6 #(
- .INIT(64'h00000F8000000880))
- M_AXI_WLAST_i_3
- (.I0(M_AXI_WREADY),
- .I1(re),
- .I2(\data_cnt_reg_n_0_[1] ),
- .I3(\data_cnt_reg_n_0_[0] ),
- .I4(M_AXI_WLAST_i_4_n_0),
- .I5(M_AXI_WLAST_i_5_n_0),
- .O(M_AXI_WLAST_i_3_n_0));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT3 #(
- .INIT(8'hFE))
- M_AXI_WLAST_i_4
- (.I0(\data_cnt_reg_n_0_[4] ),
- .I1(\data_cnt_reg_n_0_[3] ),
- .I2(\data_cnt_reg_n_0_[2] ),
- .O(M_AXI_WLAST_i_4_n_0));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT4 #(
- .INIT(16'h0800))
- M_AXI_WLAST_i_5
- (.I0(M_AXI_AWREADY),
- .I1(state[2]),
- .I2(state[1]),
- .I3(state[0]),
- .O(M_AXI_WLAST_i_5_n_0));
- FDRE M_AXI_WLAST_reg
- (.C(CLK),
- .CE(1'b1),
- .D(M_AXI_WLAST_i_1_n_0),
- .Q(M_AXI_WLAST),
- .R(M_AXI_ARVALID_i_1_n_0));
- LUT6 #(
- .INIT(64'hDFFFDFFF0C000000))
- M_AXI_WVALID_i_1
- (.I0(M_AXI_WVALID_i_2_n_0),
- .I1(state[0]),
- .I2(state[1]),
- .I3(state[2]),
- .I4(M_AXI_AWREADY),
- .I5(M_AXI_WVALID),
- .O(M_AXI_WVALID_i_1_n_0));
- LUT6 #(
- .INIT(64'h0000000000020000))
- M_AXI_WVALID_i_2
- (.I0(M_AXI_WREADY),
- .I1(\data_cnt_reg_n_0_[4] ),
- .I2(\data_cnt_reg_n_0_[3] ),
- .I3(\data_cnt_reg_n_0_[2] ),
- .I4(\data_cnt_reg_n_0_[0] ),
- .I5(\data_cnt_reg_n_0_[1] ),
- .O(M_AXI_WVALID_i_2_n_0));
- FDRE #(
- .INIT(1'b0))
- M_AXI_WVALID_reg
- (.C(CLK),
- .CE(1'b1),
- .D(M_AXI_WVALID_i_1_n_0),
- .Q(M_AXI_WVALID),
- .R(M_AXI_ARVALID_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h002A))
- \addr_LUTRAM[0]_i_1
- (.I0(state[1]),
- .I1(state[2]),
- .I2(state[0]),
- .I3(waddr[0]),
- .O(\addr_LUTRAM[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT5 #(
- .INIT(32'h00707000))
- \addr_LUTRAM[1]_i_1
- (.I0(state[0]),
- .I1(state[2]),
- .I2(state[1]),
- .I3(waddr[0]),
- .I4(waddr[1]),
- .O(\addr_LUTRAM[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0070707070000000))
- \addr_LUTRAM[2]_i_1
- (.I0(state[0]),
- .I1(state[2]),
- .I2(state[1]),
- .I3(waddr[0]),
- .I4(waddr[1]),
- .I5(waddr[2]),
- .O(\addr_LUTRAM[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0808A80808080808))
- \addr_LUTRAM[3]_i_1
- (.I0(RESETN),
- .I1(\addr_LUTRAM[3]_i_3_n_0 ),
- .I2(state[0]),
- .I3(M_AXI_RVALID),
- .I4(state[2]),
- .I5(state[1]),
- .O(\addr_LUTRAM[3]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h2AAA8000))
- \addr_LUTRAM[3]_i_2
- (.I0(\addr_LUTRAM[3]_i_4_n_0 ),
- .I1(waddr[1]),
- .I2(waddr[0]),
- .I3(waddr[2]),
- .I4(waddr[3]),
- .O(\addr_LUTRAM[3]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h8830))
- \addr_LUTRAM[3]_i_3
- (.I0(M_AXI_WREADY),
- .I1(state[1]),
- .I2(start),
- .I3(state[2]),
- .O(\addr_LUTRAM[3]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT3 #(
- .INIT(8'h70))
- \addr_LUTRAM[3]_i_4
- (.I0(state[0]),
- .I1(state[2]),
- .I2(state[1]),
- .O(\addr_LUTRAM[3]_i_4_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \addr_LUTRAM_reg[0]
- (.C(CLK),
- .CE(\addr_LUTRAM[3]_i_1_n_0 ),
- .D(\addr_LUTRAM[0]_i_1_n_0 ),
- .Q(waddr[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_LUTRAM_reg[1]
- (.C(CLK),
- .CE(\addr_LUTRAM[3]_i_1_n_0 ),
- .D(\addr_LUTRAM[1]_i_1_n_0 ),
- .Q(waddr[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_LUTRAM_reg[2]
- (.C(CLK),
- .CE(\addr_LUTRAM[3]_i_1_n_0 ),
- .D(\addr_LUTRAM[2]_i_1_n_0 ),
- .Q(waddr[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_LUTRAM_reg[3]
- (.C(CLK),
- .CE(\addr_LUTRAM[3]_i_1_n_0 ),
- .D(\addr_LUTRAM[3]_i_2_n_0 ),
- .Q(waddr[3]),
- .R(1'b0));
- LUT5 #(
- .INIT(32'h00000008))
- \addr_mem[31]_i_1
- (.I0(start),
- .I1(RESETN),
- .I2(state[1]),
- .I3(state[2]),
- .I4(state[0]),
- .O(\addr_mem[31]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[0]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[0]),
- .Q(addr_mem[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[10]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[10]),
- .Q(addr_mem[10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[11]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[11]),
- .Q(addr_mem[11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[12]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[12]),
- .Q(addr_mem[12]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[13]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[13]),
- .Q(addr_mem[13]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[14]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[14]),
- .Q(addr_mem[14]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[15]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[15]),
- .Q(addr_mem[15]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[16]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[16]),
- .Q(addr_mem[16]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[17]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[17]),
- .Q(addr_mem[17]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[18]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[18]),
- .Q(addr_mem[18]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[19]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[19]),
- .Q(addr_mem[19]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[1]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[1]),
- .Q(addr_mem[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[20]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[20]),
- .Q(addr_mem[20]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[21]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[21]),
- .Q(addr_mem[21]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[22]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[22]),
- .Q(addr_mem[22]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[23]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[23]),
- .Q(addr_mem[23]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[24]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[24]),
- .Q(addr_mem[24]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[25]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[25]),
- .Q(addr_mem[25]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[26]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[26]),
- .Q(addr_mem[26]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[27]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[27]),
- .Q(addr_mem[27]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[28]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[28]),
- .Q(addr_mem[28]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[29]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[29]),
- .Q(addr_mem[29]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[2]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[2]),
- .Q(addr_mem[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[30]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[30]),
- .Q(addr_mem[30]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[31]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[31]),
- .Q(addr_mem[31]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[3]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[3]),
- .Q(addr_mem[3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[4]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[4]),
- .Q(addr_mem[4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[5]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[5]),
- .Q(addr_mem[5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[6]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[6]),
- .Q(addr_mem[6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[7]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[7]),
- .Q(addr_mem[7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[8]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[8]),
- .Q(addr_mem[8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \addr_mem_reg[9]
- (.C(CLK),
- .CE(\addr_mem[31]_i_1_n_0 ),
- .D(addr_axi[9]),
- .Q(addr_mem[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT3 #(
- .INIT(8'h1B))
- \data_cnt[0]_i_1
- (.I0(state[2]),
- .I1(size[0]),
- .I2(\data_cnt_reg_n_0_[0] ),
- .O(data_cnt0_in[0]));
- LUT5 #(
- .INIT(32'hA3AC535C))
- \data_cnt[1]_i_1
- (.I0(\data_cnt_reg_n_0_[0] ),
- .I1(size[0]),
- .I2(state[2]),
- .I3(size[1]),
- .I4(\data_cnt_reg_n_0_[1] ),
- .O(data_cnt0_in[1]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'hF30CAF50))
- \data_cnt[2]_i_1
- (.I0(\data_cnt_reg_n_0_[0] ),
- .I1(size[0]),
- .I2(state[2]),
- .I3(\data_cnt[4]_i_3_n_0 ),
- .I4(\data_cnt[2]_i_2_n_0 ),
- .O(data_cnt0_in[2]));
- LUT4 #(
- .INIT(16'h0A0C))
- \data_cnt[2]_i_2
- (.I0(\data_cnt_reg_n_0_[1] ),
- .I1(size[1]),
- .I2(state[0]),
- .I3(state[2]),
- .O(\data_cnt[2]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'h665A99A5))
- \data_cnt[3]_i_1
- (.I0(\data_cnt[4]_i_4_n_0 ),
- .I1(\data_cnt_reg_n_0_[3] ),
- .I2(size[3]),
- .I3(state[2]),
- .I4(\data_cnt[4]_i_3_n_0 ),
- .O(data_cnt0_in[3]));
- LUT6 #(
- .INIT(64'h4040040000000400))
- \data_cnt[4]_i_1
- (.I0(state[0]),
- .I1(RESETN),
- .I2(state[2]),
- .I3(start),
- .I4(state[1]),
- .I5(M_AXI_WREADY),
- .O(\data_cnt[4]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h7888E111))
- \data_cnt[4]_i_2
- (.I0(\data_cnt[4]_i_3_n_0 ),
- .I1(\data_cnt[4]_i_4_n_0 ),
- .I2(state[2]),
- .I3(\data_cnt_reg_n_0_[4] ),
- .I4(\data_cnt[4]_i_5_n_0 ),
- .O(data_cnt0_in[4]));
- LUT4 #(
- .INIT(16'h0A0C))
- \data_cnt[4]_i_3
- (.I0(\data_cnt_reg_n_0_[2] ),
- .I1(size[2]),
- .I2(state[0]),
- .I3(state[2]),
- .O(\data_cnt[4]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h5555757555555511))
- \data_cnt[4]_i_4
- (.I0(\data_cnt[4]_i_3_n_0 ),
- .I1(state[2]),
- .I2(size[0]),
- .I3(\data_cnt_reg_n_0_[0] ),
- .I4(state[0]),
- .I5(\data_cnt[2]_i_2_n_0 ),
- .O(\data_cnt[4]_i_4_n_0 ));
- LUT4 #(
- .INIT(16'h0A0C))
- \data_cnt[4]_i_5
- (.I0(\data_cnt_reg_n_0_[3] ),
- .I1(size[3]),
- .I2(state[0]),
- .I3(state[2]),
- .O(\data_cnt[4]_i_5_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \data_cnt_reg[0]
- (.C(CLK),
- .CE(\data_cnt[4]_i_1_n_0 ),
- .D(data_cnt0_in[0]),
- .Q(\data_cnt_reg_n_0_[0] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \data_cnt_reg[1]
- (.C(CLK),
- .CE(\data_cnt[4]_i_1_n_0 ),
- .D(data_cnt0_in[1]),
- .Q(\data_cnt_reg_n_0_[1] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \data_cnt_reg[2]
- (.C(CLK),
- .CE(\data_cnt[4]_i_1_n_0 ),
- .D(data_cnt0_in[2]),
- .Q(\data_cnt_reg_n_0_[2] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \data_cnt_reg[3]
- (.C(CLK),
- .CE(\data_cnt[4]_i_1_n_0 ),
- .D(data_cnt0_in[3]),
- .Q(\data_cnt_reg_n_0_[3] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \data_cnt_reg[4]
- (.C(CLK),
- .CE(\data_cnt[4]_i_1_n_0 ),
- .D(data_cnt0_in[4]),
- .Q(\data_cnt_reg_n_0_[4] ),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hBBBF8880))
- ip_idle_i_1
- (.I0(ip_idle_i_2_n_0),
- .I1(RESETN),
- .I2(ip_idle_i_3_n_0),
- .I3(ip_idle_i_4_n_0),
- .I4(ip_idle),
- .O(ip_idle_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'h0808F808))
- ip_idle_i_2
- (.I0(M_AXI_RLAST),
- .I1(state[1]),
- .I2(state[2]),
- .I3(M_AXI_WREADY),
- .I4(state[0]),
- .O(ip_idle_i_2_n_0));
- LUT5 #(
- .INIT(32'h40000000))
- ip_idle_i_3
- (.I0(state[0]),
- .I1(state[2]),
- .I2(state[1]),
- .I3(M_AXI_WLAST_i_2_n_0),
- .I4(M_AXI_WREADY),
- .O(ip_idle_i_3_n_0));
- LUT6 #(
- .INIT(64'h00880000000000F0))
- ip_idle_i_4
- (.I0(M_AXI_RLAST),
- .I1(M_AXI_RVALID),
- .I2(start),
- .I3(state[2]),
- .I4(state[0]),
- .I5(state[1]),
- .O(ip_idle_i_4_n_0));
- FDRE ip_idle_reg
- (.C(CLK),
- .CE(1'b1),
- .D(ip_idle_i_1_n_0),
- .Q(ip_idle),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT3 #(
- .INIT(8'h08))
- re_INST_0
- (.I0(state[1]),
- .I1(state[2]),
- .I2(state[0]),
- .O(re));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
- parameter GRES_WIDTH = 10000;
- parameter GRES_START = 10000;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- wire GRESTORE;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
- reg GRESTORE_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
- assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
- initial begin
- GRESTORE_int = 1'b0;
- #(GRES_START);
- GRESTORE_int = 1'b1;
- #(GRES_WIDTH);
- GRESTORE_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.v b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.v
deleted file mode 100644
index e894230..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.v
+++ /dev/null
@@ -1,74 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-// Date : Fri Jan 31 01:49:53 2025
-// Host : BiermannSurface running 64-bit major release (build 9200)
-// Command : write_verilog -force -mode synth_stub
-// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.v
-// Design : crc_axi_master_syn_HP_Port_crc_axi_master_0_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z020clg400-1
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* x_core_info = "crc_axi_master,Vivado 2023.1" *)
-module crc_axi_master_syn_HP_Port_crc_axi_master_0_0(CLK, RESETN, start, write, addr_axi, size, ip_idle,
- waddr, wdata, we, raddr, rdata, re, M_AXI_ARREADY, M_AXI_ARVALID, M_AXI_ARADDR, M_AXI_ARID,
- M_AXI_ARLEN, M_AXI_ARSIZE, M_AXI_ARBURST, M_AXI_ARPROT, M_AXI_ARCACHE, M_AXI_RREADY,
- M_AXI_RVALID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RID, M_AXI_RLAST, M_AXI_AWREADY, M_AXI_AWVALID,
- M_AXI_AWADDR, M_AXI_AWLEN, M_AXI_AWSIZE, M_AXI_AWID, M_AXI_AWBURST, M_AXI_AWPROT,
- M_AXI_AWCACHE, M_AXI_WREADY, M_AXI_WVALID, M_AXI_WDATA, M_AXI_WSTRB, M_AXI_WLAST, M_AXI_WID,
- M_AXI_BREADY, M_AXI_BVALID, M_AXI_BID, M_AXI_BRESP)
-/* synthesis syn_black_box black_box_pad_pin="RESETN,start,write,addr_axi[31:0],size[3:0],ip_idle,waddr[3:0],wdata[31:0],we,raddr[3:0],rdata[31:0],re,M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARID[0:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[0:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[0:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[31:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[31:0],M_AXI_BRESP[1:0]" */
-/* synthesis syn_force_seq_prim="CLK" */;
- input CLK /* synthesis syn_isclock = 1 */;
- input RESETN;
- input start;
- input write;
- input [31:0]addr_axi;
- input [3:0]size;
- output ip_idle;
- output [3:0]waddr;
- output [31:0]wdata;
- output we;
- output [3:0]raddr;
- input [31:0]rdata;
- output re;
- input M_AXI_ARREADY;
- output M_AXI_ARVALID;
- output [31:0]M_AXI_ARADDR;
- output [0:0]M_AXI_ARID;
- output [3:0]M_AXI_ARLEN;
- output [2:0]M_AXI_ARSIZE;
- output [1:0]M_AXI_ARBURST;
- output [2:0]M_AXI_ARPROT;
- output [3:0]M_AXI_ARCACHE;
- output M_AXI_RREADY;
- input M_AXI_RVALID;
- input [31:0]M_AXI_RDATA;
- input [1:0]M_AXI_RRESP;
- input [0:0]M_AXI_RID;
- input M_AXI_RLAST;
- input M_AXI_AWREADY;
- output M_AXI_AWVALID;
- output [31:0]M_AXI_AWADDR;
- output [3:0]M_AXI_AWLEN;
- output [2:0]M_AXI_AWSIZE;
- output [0:0]M_AXI_AWID;
- output [1:0]M_AXI_AWBURST;
- output [2:0]M_AXI_AWPROT;
- output [3:0]M_AXI_AWCACHE;
- input M_AXI_WREADY;
- output M_AXI_WVALID;
- output [31:0]M_AXI_WDATA;
- output [3:0]M_AXI_WSTRB;
- output M_AXI_WLAST;
- output [31:0]M_AXI_WID;
- output M_AXI_BREADY;
- input M_AXI_BVALID;
- input [31:0]M_AXI_BID;
- input [1:0]M_AXI_BRESP;
-endmodule
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/sim/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/sim/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd
deleted file mode 100644
index 2c9299c..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/sim/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd
+++ /dev/null
@@ -1,267 +0,0 @@
--- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of AMD and is protected under U.S. and international copyright
--- and other intellectual property laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- AMD, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) AMD shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or AMD had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- AMD products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of AMD products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:module_ref:crc_axi_master:1.0
--- IP Revision: 1
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- start : IN STD_LOGIC;
- write : IN STD_LOGIC;
- addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- ip_idle : OUT STD_LOGIC;
- waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- we : OUT STD_LOGIC;
- raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- re : OUT STD_LOGIC;
- M_AXI_ARREADY : IN STD_LOGIC;
- M_AXI_ARVALID : OUT STD_LOGIC;
- M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_RREADY : OUT STD_LOGIC;
- M_AXI_RVALID : IN STD_LOGIC;
- M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_RLAST : IN STD_LOGIC;
- M_AXI_AWREADY : IN STD_LOGIC;
- M_AXI_AWVALID : OUT STD_LOGIC;
- M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WREADY : IN STD_LOGIC;
- M_AXI_WVALID : OUT STD_LOGIC;
- M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WLAST : OUT STD_LOGIC;
- M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BREADY : OUT STD_LOGIC;
- M_AXI_BVALID : IN STD_LOGIC;
- M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
- );
-END crc_axi_master_syn_HP_Port_crc_axi_master_0_0;
-
-ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
- ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
- ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "yes";
- COMPONENT crc_axi_master IS
- GENERIC (
- DWIDTH : INTEGER;
- IDWIDTH : INTEGER;
- MAX_BURSTLEN : INTEGER;
- LUTRAM_AWIDTH : INTEGER
- );
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- start : IN STD_LOGIC;
- write : IN STD_LOGIC;
- addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- ip_idle : OUT STD_LOGIC;
- waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- we : OUT STD_LOGIC;
- raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- re : OUT STD_LOGIC;
- M_AXI_ARREADY : IN STD_LOGIC;
- M_AXI_ARVALID : OUT STD_LOGIC;
- M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_RREADY : OUT STD_LOGIC;
- M_AXI_RVALID : IN STD_LOGIC;
- M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_RLAST : IN STD_LOGIC;
- M_AXI_AWREADY : IN STD_LOGIC;
- M_AXI_AWVALID : OUT STD_LOGIC;
- M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WREADY : IN STD_LOGIC;
- M_AXI_WVALID : OUT STD_LOGIC;
- M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WLAST : OUT STD_LOGIC;
- M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BREADY : OUT STD_LOGIC;
- M_AXI_BVALID : IN STD_LOGIC;
- M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
- );
- END COMPONENT crc_axi_master;
- ATTRIBUTE X_INTERFACE_INFO : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
- ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, NU" &
-"M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
- ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
-BEGIN
- U0 : crc_axi_master
- GENERIC MAP (
- DWIDTH => 32,
- IDWIDTH => 1,
- MAX_BURSTLEN => 16,
- LUTRAM_AWIDTH => 4
- )
- PORT MAP (
- CLK => CLK,
- RESETN => RESETN,
- start => start,
- write => write,
- addr_axi => addr_axi,
- size => size,
- ip_idle => ip_idle,
- waddr => waddr,
- wdata => wdata,
- we => we,
- raddr => raddr,
- rdata => rdata,
- re => re,
- M_AXI_ARREADY => M_AXI_ARREADY,
- M_AXI_ARVALID => M_AXI_ARVALID,
- M_AXI_ARADDR => M_AXI_ARADDR,
- M_AXI_ARID => M_AXI_ARID,
- M_AXI_ARLEN => M_AXI_ARLEN,
- M_AXI_ARSIZE => M_AXI_ARSIZE,
- M_AXI_ARBURST => M_AXI_ARBURST,
- M_AXI_ARPROT => M_AXI_ARPROT,
- M_AXI_ARCACHE => M_AXI_ARCACHE,
- M_AXI_RREADY => M_AXI_RREADY,
- M_AXI_RVALID => M_AXI_RVALID,
- M_AXI_RDATA => M_AXI_RDATA,
- M_AXI_RRESP => M_AXI_RRESP,
- M_AXI_RID => M_AXI_RID,
- M_AXI_RLAST => M_AXI_RLAST,
- M_AXI_AWREADY => M_AXI_AWREADY,
- M_AXI_AWVALID => M_AXI_AWVALID,
- M_AXI_AWADDR => M_AXI_AWADDR,
- M_AXI_AWLEN => M_AXI_AWLEN,
- M_AXI_AWSIZE => M_AXI_AWSIZE,
- M_AXI_AWID => M_AXI_AWID,
- M_AXI_AWBURST => M_AXI_AWBURST,
- M_AXI_AWPROT => M_AXI_AWPROT,
- M_AXI_AWCACHE => M_AXI_AWCACHE,
- M_AXI_WREADY => M_AXI_WREADY,
- M_AXI_WVALID => M_AXI_WVALID,
- M_AXI_WDATA => M_AXI_WDATA,
- M_AXI_WSTRB => M_AXI_WSTRB,
- M_AXI_WLAST => M_AXI_WLAST,
- M_AXI_WID => M_AXI_WID,
- M_AXI_BREADY => M_AXI_BREADY,
- M_AXI_BVALID => M_AXI_BVALID,
- M_AXI_BID => M_AXI_BID,
- M_AXI_BRESP => M_AXI_BRESP
- );
-END crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch;
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/synth/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/synth/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd
deleted file mode 100644
index 8e48177..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/synth/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd
+++ /dev/null
@@ -1,275 +0,0 @@
--- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of AMD and is protected under U.S. and international copyright
--- and other intellectual property laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- AMD, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) AMD shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or AMD had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- AMD products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of AMD products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:module_ref:crc_axi_master:1.0
--- IP Revision: 1
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- start : IN STD_LOGIC;
- write : IN STD_LOGIC;
- addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- ip_idle : OUT STD_LOGIC;
- waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- we : OUT STD_LOGIC;
- raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- re : OUT STD_LOGIC;
- M_AXI_ARREADY : IN STD_LOGIC;
- M_AXI_ARVALID : OUT STD_LOGIC;
- M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_RREADY : OUT STD_LOGIC;
- M_AXI_RVALID : IN STD_LOGIC;
- M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_RLAST : IN STD_LOGIC;
- M_AXI_AWREADY : IN STD_LOGIC;
- M_AXI_AWVALID : OUT STD_LOGIC;
- M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WREADY : IN STD_LOGIC;
- M_AXI_WVALID : OUT STD_LOGIC;
- M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WLAST : OUT STD_LOGIC;
- M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BREADY : OUT STD_LOGIC;
- M_AXI_BVALID : IN STD_LOGIC;
- M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
- );
-END crc_axi_master_syn_HP_Port_crc_axi_master_0_0;
-
-ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
- ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
- ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "yes";
- COMPONENT crc_axi_master IS
- GENERIC (
- DWIDTH : INTEGER;
- IDWIDTH : INTEGER;
- MAX_BURSTLEN : INTEGER;
- LUTRAM_AWIDTH : INTEGER
- );
- PORT (
- CLK : IN STD_LOGIC;
- RESETN : IN STD_LOGIC;
- start : IN STD_LOGIC;
- write : IN STD_LOGIC;
- addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- ip_idle : OUT STD_LOGIC;
- waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- we : OUT STD_LOGIC;
- raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- re : OUT STD_LOGIC;
- M_AXI_ARREADY : IN STD_LOGIC;
- M_AXI_ARVALID : OUT STD_LOGIC;
- M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_RREADY : OUT STD_LOGIC;
- M_AXI_RVALID : IN STD_LOGIC;
- M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_RLAST : IN STD_LOGIC;
- M_AXI_AWREADY : IN STD_LOGIC;
- M_AXI_AWVALID : OUT STD_LOGIC;
- M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WREADY : IN STD_LOGIC;
- M_AXI_WVALID : OUT STD_LOGIC;
- M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- M_AXI_WLAST : OUT STD_LOGIC;
- M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BREADY : OUT STD_LOGIC;
- M_AXI_BVALID : IN STD_LOGIC;
- M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
- );
- END COMPONENT crc_axi_master;
- ATTRIBUTE X_CORE_INFO : STRING;
- ATTRIBUTE X_CORE_INFO OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "crc_axi_master,Vivado 2023.1";
- ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
- ATTRIBUTE CHECK_LICENSE_TYPE OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch : ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_master_0_0,crc_axi_master,{}";
- ATTRIBUTE CORE_GENERATION_INFO : STRING;
- ATTRIBUTE CORE_GENERATION_INFO OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_master_0_0,crc_axi_master,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=crc_axi_master,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DWIDTH=32,IDWIDTH=1,MAX_BURSTLEN=16,LUTRAM_AWIDTH=4}";
- ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
- ATTRIBUTE IP_DEFINITION_SOURCE OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "module_ref";
- ATTRIBUTE X_INTERFACE_INFO : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
- ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, NU" &
-"M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
- ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
- ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
- ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
-BEGIN
- U0 : crc_axi_master
- GENERIC MAP (
- DWIDTH => 32,
- IDWIDTH => 1,
- MAX_BURSTLEN => 16,
- LUTRAM_AWIDTH => 4
- )
- PORT MAP (
- CLK => CLK,
- RESETN => RESETN,
- start => start,
- write => write,
- addr_axi => addr_axi,
- size => size,
- ip_idle => ip_idle,
- waddr => waddr,
- wdata => wdata,
- we => we,
- raddr => raddr,
- rdata => rdata,
- re => re,
- M_AXI_ARREADY => M_AXI_ARREADY,
- M_AXI_ARVALID => M_AXI_ARVALID,
- M_AXI_ARADDR => M_AXI_ARADDR,
- M_AXI_ARID => M_AXI_ARID,
- M_AXI_ARLEN => M_AXI_ARLEN,
- M_AXI_ARSIZE => M_AXI_ARSIZE,
- M_AXI_ARBURST => M_AXI_ARBURST,
- M_AXI_ARPROT => M_AXI_ARPROT,
- M_AXI_ARCACHE => M_AXI_ARCACHE,
- M_AXI_RREADY => M_AXI_RREADY,
- M_AXI_RVALID => M_AXI_RVALID,
- M_AXI_RDATA => M_AXI_RDATA,
- M_AXI_RRESP => M_AXI_RRESP,
- M_AXI_RID => M_AXI_RID,
- M_AXI_RLAST => M_AXI_RLAST,
- M_AXI_AWREADY => M_AXI_AWREADY,
- M_AXI_AWVALID => M_AXI_AWVALID,
- M_AXI_AWADDR => M_AXI_AWADDR,
- M_AXI_AWLEN => M_AXI_AWLEN,
- M_AXI_AWSIZE => M_AXI_AWSIZE,
- M_AXI_AWID => M_AXI_AWID,
- M_AXI_AWBURST => M_AXI_AWBURST,
- M_AXI_AWPROT => M_AXI_AWPROT,
- M_AXI_AWCACHE => M_AXI_AWCACHE,
- M_AXI_WREADY => M_AXI_WREADY,
- M_AXI_WVALID => M_AXI_WVALID,
- M_AXI_WDATA => M_AXI_WDATA,
- M_AXI_WSTRB => M_AXI_WSTRB,
- M_AXI_WLAST => M_AXI_WLAST,
- M_AXI_WID => M_AXI_WID,
- M_AXI_BREADY => M_AXI_BREADY,
- M_AXI_BVALID => M_AXI_BVALID,
- M_AXI_BID => M_AXI_BID,
- M_AXI_BRESP => M_AXI_BRESP
- );
-END crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch;
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/sim/crc_axi_master_syn_HP_Port.vhd b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/sim/crc_axi_master_syn_HP_Port.vhd
deleted file mode 100644
index 5f4c24e..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/sim/crc_axi_master_syn_HP_Port.vhd
+++ /dev/null
@@ -1,1601 +0,0 @@
---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
---Date : Fri Jan 31 01:48:41 2025
---Host : BiermannSurface running 64-bit major release (build 9200)
---Command : generate_target crc_axi_master_syn_HP_Port.bd
---Design : crc_axi_master_syn_HP_Port
---Purpose : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity s00_couplers_imp_1N0N7ZR is
- port (
- M_ACLK : in STD_LOGIC;
- M_ARESETN : in STD_LOGIC;
- M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_arready : in STD_LOGIC;
- M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_arvalid : out STD_LOGIC;
- M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_awready : in STD_LOGIC;
- M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_awvalid : out STD_LOGIC;
- M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
- M_AXI_bready : out STD_LOGIC;
- M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_bvalid : in STD_LOGIC;
- M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
- M_AXI_rlast : in STD_LOGIC;
- M_AXI_rready : out STD_LOGIC;
- M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_rvalid : in STD_LOGIC;
- M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_wid : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_wlast : out STD_LOGIC;
- M_AXI_wready : in STD_LOGIC;
- M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_wvalid : out STD_LOGIC;
- S_ACLK : in STD_LOGIC;
- S_ARESETN : in STD_LOGIC;
- S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_arready : out STD_LOGIC;
- S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_arvalid : in STD_LOGIC;
- S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_awready : out STD_LOGIC;
- S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_awvalid : in STD_LOGIC;
- S_AXI_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_bready : in STD_LOGIC;
- S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_bvalid : out STD_LOGIC;
- S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_rlast : out STD_LOGIC;
- S_AXI_rready : in STD_LOGIC;
- S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_rvalid : out STD_LOGIC;
- S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_wid : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_wlast : in STD_LOGIC;
- S_AXI_wready : out STD_LOGIC;
- S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_wvalid : in STD_LOGIC
- );
-end s00_couplers_imp_1N0N7ZR;
-
-architecture STRUCTURE of s00_couplers_imp_1N0N7ZR is
- signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s00_couplers_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s00_couplers_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal s00_couplers_to_s00_couplers_RLAST : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_WLAST : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC;
-begin
- M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
- M_AXI_arburst(1 downto 0) <= s00_couplers_to_s00_couplers_ARBURST(1 downto 0);
- M_AXI_arcache(3 downto 0) <= s00_couplers_to_s00_couplers_ARCACHE(3 downto 0);
- M_AXI_arid(0) <= s00_couplers_to_s00_couplers_ARID(0);
- M_AXI_arlen(3 downto 0) <= s00_couplers_to_s00_couplers_ARLEN(3 downto 0);
- M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
- M_AXI_arsize(2 downto 0) <= s00_couplers_to_s00_couplers_ARSIZE(2 downto 0);
- M_AXI_arvalid <= s00_couplers_to_s00_couplers_ARVALID;
- M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
- M_AXI_awburst(1 downto 0) <= s00_couplers_to_s00_couplers_AWBURST(1 downto 0);
- M_AXI_awcache(3 downto 0) <= s00_couplers_to_s00_couplers_AWCACHE(3 downto 0);
- M_AXI_awid(0) <= s00_couplers_to_s00_couplers_AWID(0);
- M_AXI_awlen(3 downto 0) <= s00_couplers_to_s00_couplers_AWLEN(3 downto 0);
- M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
- M_AXI_awsize(2 downto 0) <= s00_couplers_to_s00_couplers_AWSIZE(2 downto 0);
- M_AXI_awvalid <= s00_couplers_to_s00_couplers_AWVALID;
- M_AXI_bready <= s00_couplers_to_s00_couplers_BREADY;
- M_AXI_rready <= s00_couplers_to_s00_couplers_RREADY;
- M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
- M_AXI_wid(31 downto 0) <= s00_couplers_to_s00_couplers_WID(31 downto 0);
- M_AXI_wlast <= s00_couplers_to_s00_couplers_WLAST;
- M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
- M_AXI_wvalid <= s00_couplers_to_s00_couplers_WVALID;
- S_AXI_arready <= s00_couplers_to_s00_couplers_ARREADY;
- S_AXI_awready <= s00_couplers_to_s00_couplers_AWREADY;
- S_AXI_bid(5 downto 0) <= s00_couplers_to_s00_couplers_BID(5 downto 0);
- S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
- S_AXI_bvalid <= s00_couplers_to_s00_couplers_BVALID;
- S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
- S_AXI_rid(5 downto 0) <= s00_couplers_to_s00_couplers_RID(5 downto 0);
- S_AXI_rlast <= s00_couplers_to_s00_couplers_RLAST;
- S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
- S_AXI_rvalid <= s00_couplers_to_s00_couplers_RVALID;
- S_AXI_wready <= s00_couplers_to_s00_couplers_WREADY;
- s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
- s00_couplers_to_s00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
- s00_couplers_to_s00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
- s00_couplers_to_s00_couplers_ARID(0) <= S_AXI_arid(0);
- s00_couplers_to_s00_couplers_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
- s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
- s00_couplers_to_s00_couplers_ARREADY <= M_AXI_arready;
- s00_couplers_to_s00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
- s00_couplers_to_s00_couplers_ARVALID <= S_AXI_arvalid;
- s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
- s00_couplers_to_s00_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
- s00_couplers_to_s00_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
- s00_couplers_to_s00_couplers_AWID(0) <= S_AXI_awid(0);
- s00_couplers_to_s00_couplers_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
- s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
- s00_couplers_to_s00_couplers_AWREADY <= M_AXI_awready;
- s00_couplers_to_s00_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
- s00_couplers_to_s00_couplers_AWVALID <= S_AXI_awvalid;
- s00_couplers_to_s00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
- s00_couplers_to_s00_couplers_BREADY <= S_AXI_bready;
- s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
- s00_couplers_to_s00_couplers_BVALID <= M_AXI_bvalid;
- s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
- s00_couplers_to_s00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
- s00_couplers_to_s00_couplers_RLAST <= M_AXI_rlast;
- s00_couplers_to_s00_couplers_RREADY <= S_AXI_rready;
- s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
- s00_couplers_to_s00_couplers_RVALID <= M_AXI_rvalid;
- s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
- s00_couplers_to_s00_couplers_WID(31 downto 0) <= S_AXI_wid(31 downto 0);
- s00_couplers_to_s00_couplers_WLAST <= S_AXI_wlast;
- s00_couplers_to_s00_couplers_WREADY <= M_AXI_wready;
- s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
- s00_couplers_to_s00_couplers_WVALID <= S_AXI_wvalid;
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity crc_axi_master_syn_HP_Port_axi_mem_intercon_0 is
- port (
- ACLK : in STD_LOGIC;
- ARESETN : in STD_LOGIC;
- M00_ACLK : in STD_LOGIC;
- M00_ARESETN : in STD_LOGIC;
- M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
- M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M00_AXI_arready : in STD_LOGIC;
- M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M00_AXI_arvalid : out STD_LOGIC;
- M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
- M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M00_AXI_awready : in STD_LOGIC;
- M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M00_AXI_awvalid : out STD_LOGIC;
- M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
- M00_AXI_bready : out STD_LOGIC;
- M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M00_AXI_bvalid : in STD_LOGIC;
- M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
- M00_AXI_rlast : in STD_LOGIC;
- M00_AXI_rready : out STD_LOGIC;
- M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M00_AXI_rvalid : in STD_LOGIC;
- M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_wid : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_wlast : out STD_LOGIC;
- M00_AXI_wready : in STD_LOGIC;
- M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_wvalid : out STD_LOGIC;
- S00_ACLK : in STD_LOGIC;
- S00_ARESETN : in STD_LOGIC;
- S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_arready : out STD_LOGIC;
- S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_arvalid : in STD_LOGIC;
- S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_awready : out STD_LOGIC;
- S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_awvalid : in STD_LOGIC;
- S00_AXI_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S00_AXI_bready : in STD_LOGIC;
- S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_bvalid : out STD_LOGIC;
- S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S00_AXI_rlast : out STD_LOGIC;
- S00_AXI_rready : in STD_LOGIC;
- S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_rvalid : out STD_LOGIC;
- S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_wid : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_wlast : in STD_LOGIC;
- S00_AXI_wready : out STD_LOGIC;
- S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_wvalid : in STD_LOGIC
- );
-end crc_axi_master_syn_HP_Port_axi_mem_intercon_0;
-
-architecture STRUCTURE of crc_axi_master_syn_HP_Port_axi_mem_intercon_0 is
- signal S00_ACLK_1 : STD_LOGIC;
- signal S00_ARESETN_1 : STD_LOGIC;
- signal axi_mem_intercon_ACLK_net : STD_LOGIC;
- signal axi_mem_intercon_ARESETN_net : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
-begin
- M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
- M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
- M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
- M00_AXI_arid(0) <= s00_couplers_to_axi_mem_intercon_ARID(0);
- M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
- M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
- M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
- M00_AXI_arvalid <= s00_couplers_to_axi_mem_intercon_ARVALID;
- M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
- M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
- M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
- M00_AXI_awid(0) <= s00_couplers_to_axi_mem_intercon_AWID(0);
- M00_AXI_awlen(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
- M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
- M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
- M00_AXI_awvalid <= s00_couplers_to_axi_mem_intercon_AWVALID;
- M00_AXI_bready <= s00_couplers_to_axi_mem_intercon_BREADY;
- M00_AXI_rready <= s00_couplers_to_axi_mem_intercon_RREADY;
- M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
- M00_AXI_wid(31 downto 0) <= s00_couplers_to_axi_mem_intercon_WID(31 downto 0);
- M00_AXI_wlast <= s00_couplers_to_axi_mem_intercon_WLAST;
- M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
- M00_AXI_wvalid <= s00_couplers_to_axi_mem_intercon_WVALID;
- S00_ACLK_1 <= S00_ACLK;
- S00_ARESETN_1 <= S00_ARESETN;
- S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
- S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY;
- S00_AXI_bid(5 downto 0) <= axi_mem_intercon_to_s00_couplers_BID(5 downto 0);
- S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0);
- S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID;
- S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
- S00_AXI_rid(5 downto 0) <= axi_mem_intercon_to_s00_couplers_RID(5 downto 0);
- S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
- S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
- S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
- S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY;
- axi_mem_intercon_ACLK_net <= M00_ACLK;
- axi_mem_intercon_ARESETN_net <= M00_ARESETN;
- axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
- axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
- axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
- axi_mem_intercon_to_s00_couplers_ARID(0) <= S00_AXI_arid(0);
- axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
- axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
- axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
- axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
- axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
- axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
- axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
- axi_mem_intercon_to_s00_couplers_AWID(0) <= S00_AXI_awid(0);
- axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
- axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
- axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
- axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
- axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready;
- axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
- axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
- axi_mem_intercon_to_s00_couplers_WID(31 downto 0) <= S00_AXI_wid(31 downto 0);
- axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast;
- axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
- axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid;
- s00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
- s00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
- s00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
- s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
- s00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
- s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
- s00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
- s00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
- s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
- s00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
- s00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
-s00_couplers: entity work.s00_couplers_imp_1N0N7ZR
- port map (
- M_ACLK => axi_mem_intercon_ACLK_net,
- M_ARESETN => axi_mem_intercon_ARESETN_net,
- M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
- M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
- M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
- M_AXI_arid(0) => s00_couplers_to_axi_mem_intercon_ARID(0),
- M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
- M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
- M_AXI_arready => s00_couplers_to_axi_mem_intercon_ARREADY,
- M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
- M_AXI_arvalid => s00_couplers_to_axi_mem_intercon_ARVALID,
- M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
- M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
- M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
- M_AXI_awid(0) => s00_couplers_to_axi_mem_intercon_AWID(0),
- M_AXI_awlen(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
- M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
- M_AXI_awready => s00_couplers_to_axi_mem_intercon_AWREADY,
- M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
- M_AXI_awvalid => s00_couplers_to_axi_mem_intercon_AWVALID,
- M_AXI_bid(5 downto 0) => s00_couplers_to_axi_mem_intercon_BID(5 downto 0),
- M_AXI_bready => s00_couplers_to_axi_mem_intercon_BREADY,
- M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
- M_AXI_bvalid => s00_couplers_to_axi_mem_intercon_BVALID,
- M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
- M_AXI_rid(5 downto 0) => s00_couplers_to_axi_mem_intercon_RID(5 downto 0),
- M_AXI_rlast => s00_couplers_to_axi_mem_intercon_RLAST,
- M_AXI_rready => s00_couplers_to_axi_mem_intercon_RREADY,
- M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
- M_AXI_rvalid => s00_couplers_to_axi_mem_intercon_RVALID,
- M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
- M_AXI_wid(31 downto 0) => s00_couplers_to_axi_mem_intercon_WID(31 downto 0),
- M_AXI_wlast => s00_couplers_to_axi_mem_intercon_WLAST,
- M_AXI_wready => s00_couplers_to_axi_mem_intercon_WREADY,
- M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
- M_AXI_wvalid => s00_couplers_to_axi_mem_intercon_WVALID,
- S_ACLK => S00_ACLK_1,
- S_ARESETN => S00_ARESETN_1,
- S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
- S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
- S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
- S_AXI_arid(0) => axi_mem_intercon_to_s00_couplers_ARID(0),
- S_AXI_arlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0),
- S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
- S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
- S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
- S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
- S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0),
- S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0),
- S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0),
- S_AXI_awid(0) => axi_mem_intercon_to_s00_couplers_AWID(0),
- S_AXI_awlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0),
- S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0),
- S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY,
- S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0),
- S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID,
- S_AXI_bid(5 downto 0) => axi_mem_intercon_to_s00_couplers_BID(5 downto 0),
- S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY,
- S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0),
- S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID,
- S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
- S_AXI_rid(5 downto 0) => axi_mem_intercon_to_s00_couplers_RID(5 downto 0),
- S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
- S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
- S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
- S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID,
- S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0),
- S_AXI_wid(31 downto 0) => axi_mem_intercon_to_s00_couplers_WID(31 downto 0),
- S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST,
- S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY,
- S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0),
- S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity PS_imp_1MAYGMX is
- port (
- DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_cas_n : inout STD_LOGIC;
- DDR_ck_n : inout STD_LOGIC;
- DDR_ck_p : inout STD_LOGIC;
- DDR_cke : inout STD_LOGIC;
- DDR_cs_n : inout STD_LOGIC;
- DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_odt : inout STD_LOGIC;
- DDR_ras_n : inout STD_LOGIC;
- DDR_reset_n : inout STD_LOGIC;
- DDR_we_n : inout STD_LOGIC;
- FCLK_CLK0 : out STD_LOGIC;
- FIXED_IO_ddr_vrn : inout STD_LOGIC;
- FIXED_IO_ddr_vrp : inout STD_LOGIC;
- FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- FIXED_IO_ps_clk : inout STD_LOGIC;
- FIXED_IO_ps_porb : inout STD_LOGIC;
- FIXED_IO_ps_srstb : inout STD_LOGIC;
- S00_ARESETN : out STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_arready : out STD_LOGIC;
- S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_arvalid : in STD_LOGIC;
- S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_awready : out STD_LOGIC;
- S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_awvalid : in STD_LOGIC;
- S00_AXI_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S00_AXI_bready : in STD_LOGIC;
- S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_bvalid : out STD_LOGIC;
- S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S00_AXI_rlast : out STD_LOGIC;
- S00_AXI_rready : in STD_LOGIC;
- S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_rvalid : out STD_LOGIC;
- S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_wid : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_wlast : in STD_LOGIC;
- S00_AXI_wready : out STD_LOGIC;
- S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_wvalid : in STD_LOGIC
- );
-end PS_imp_1MAYGMX;
-
-architecture STRUCTURE of PS_imp_1MAYGMX is
- component crc_axi_master_syn_HP_Port_processing_system7_0_0 is
- port (
- SDIO0_WP : in STD_LOGIC;
- TTC0_WAVE0_OUT : out STD_LOGIC;
- TTC0_WAVE1_OUT : out STD_LOGIC;
- TTC0_WAVE2_OUT : out STD_LOGIC;
- USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
- USB0_VBUS_PWRSELECT : out STD_LOGIC;
- USB0_VBUS_PWRFAULT : in STD_LOGIC;
- S_AXI_HP0_ARREADY : out STD_LOGIC;
- S_AXI_HP0_AWREADY : out STD_LOGIC;
- S_AXI_HP0_BVALID : out STD_LOGIC;
- S_AXI_HP0_RLAST : out STD_LOGIC;
- S_AXI_HP0_RVALID : out STD_LOGIC;
- S_AXI_HP0_WREADY : out STD_LOGIC;
- S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
- S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
- S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_ACLK : in STD_LOGIC;
- S_AXI_HP0_ARVALID : in STD_LOGIC;
- S_AXI_HP0_AWVALID : in STD_LOGIC;
- S_AXI_HP0_BREADY : in STD_LOGIC;
- S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
- S_AXI_HP0_RREADY : in STD_LOGIC;
- S_AXI_HP0_WLAST : in STD_LOGIC;
- S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
- S_AXI_HP0_WVALID : in STD_LOGIC;
- S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
- IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
- FCLK_CLK0 : out STD_LOGIC;
- FCLK_CLK1 : out STD_LOGIC;
- FCLK_CLK2 : out STD_LOGIC;
- FCLK_CLK3 : out STD_LOGIC;
- FCLK_RESET0_N : out STD_LOGIC;
- MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- DDR_CAS_n : inout STD_LOGIC;
- DDR_CKE : inout STD_LOGIC;
- DDR_Clk_n : inout STD_LOGIC;
- DDR_Clk : inout STD_LOGIC;
- DDR_CS_n : inout STD_LOGIC;
- DDR_DRSTB : inout STD_LOGIC;
- DDR_ODT : inout STD_LOGIC;
- DDR_RAS_n : inout STD_LOGIC;
- DDR_WEB : inout STD_LOGIC;
- DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_VRN : inout STD_LOGIC;
- DDR_VRP : inout STD_LOGIC;
- DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- PS_SRSTB : inout STD_LOGIC;
- PS_CLK : inout STD_LOGIC;
- PS_PORB : inout STD_LOGIC
- );
- end component crc_axi_master_syn_HP_Port_processing_system7_0_0;
- component crc_axi_master_syn_HP_Port_xlconstant_0_0 is
- port (
- dout : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component crc_axi_master_syn_HP_Port_xlconstant_0_0;
- component crc_axi_master_syn_HP_Port_rst_ps7_0_100M_0 is
- port (
- slowest_sync_clk : in STD_LOGIC;
- ext_reset_in : in STD_LOGIC;
- aux_reset_in : in STD_LOGIC;
- mb_debug_sys_rst : in STD_LOGIC;
- dcm_locked : in STD_LOGIC;
- mb_reset : out STD_LOGIC;
- bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
- peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
- interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
- peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component crc_axi_master_syn_HP_Port_rst_ps7_0_100M_0;
- signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG : string;
- attribute DEBUG of crc_axi_master_0_M_AXI_ARADDR : signal is "true";
- signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARBURST : signal is "true";
- signal crc_axi_master_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARCACHE : signal is "true";
- signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARID : signal is "true";
- signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARLEN : signal is "true";
- signal crc_axi_master_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARPROT : signal is "true";
- signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_ARREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARSIZE : signal is "true";
- signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_ARVALID : signal is "true";
- signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWADDR : signal is "true";
- signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWBURST : signal is "true";
- signal crc_axi_master_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWCACHE : signal is "true";
- signal crc_axi_master_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWID : signal is "true";
- signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWLEN : signal is "true";
- signal crc_axi_master_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWPROT : signal is "true";
- signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_AWREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWSIZE : signal is "true";
- signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_AWVALID : signal is "true";
- signal crc_axi_master_0_M_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_BID : signal is "true";
- signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_BREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_BRESP : signal is "true";
- signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_BVALID : signal is "true";
- signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_RDATA : signal is "true";
- signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_RID : signal is "true";
- signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_RLAST : signal is "true";
- signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_RREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_RRESP : signal is "true";
- signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_RVALID : signal is "true";
- signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_WDATA : signal is "true";
- signal crc_axi_master_0_M_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_WID : signal is "true";
- signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_WLAST : signal is "true";
- signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_WREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_WSTRB : signal is "true";
- signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_WVALID : signal is "true";
- signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
- signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_CKE : STD_LOGIC;
- signal processing_system7_0_DDR_CK_N : STD_LOGIC;
- signal processing_system7_0_DDR_CK_P : STD_LOGIC;
- signal processing_system7_0_DDR_CS_N : STD_LOGIC;
- signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_ODT : STD_LOGIC;
- signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
- signal processing_system7_0_DDR_WE_N : STD_LOGIC;
- signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
- signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
- signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
- signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
- signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
- signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_rst_ps7_0_100M_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- FCLK_CLK0 <= processing_system7_0_FCLK_CLK0;
- S00_ARESETN(0) <= rst_ps7_0_100M_peripheral_aresetn(0);
- S00_AXI_arready <= crc_axi_master_0_M_AXI_ARREADY;
- S00_AXI_awready <= crc_axi_master_0_M_AXI_AWREADY;
- S00_AXI_bid(5 downto 0) <= crc_axi_master_0_M_AXI_BID(5 downto 0);
- S00_AXI_bresp(1 downto 0) <= crc_axi_master_0_M_AXI_BRESP(1 downto 0);
- S00_AXI_bvalid <= crc_axi_master_0_M_AXI_BVALID;
- S00_AXI_rdata(31 downto 0) <= crc_axi_master_0_M_AXI_RDATA(31 downto 0);
- S00_AXI_rid(5 downto 0) <= crc_axi_master_0_M_AXI_RID(5 downto 0);
- S00_AXI_rlast <= crc_axi_master_0_M_AXI_RLAST;
- S00_AXI_rresp(1 downto 0) <= crc_axi_master_0_M_AXI_RRESP(1 downto 0);
- S00_AXI_rvalid <= crc_axi_master_0_M_AXI_RVALID;
- S00_AXI_wready <= crc_axi_master_0_M_AXI_WREADY;
- crc_axi_master_0_M_AXI_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
- crc_axi_master_0_M_AXI_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
- crc_axi_master_0_M_AXI_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
- crc_axi_master_0_M_AXI_ARID(0) <= S00_AXI_arid(0);
- crc_axi_master_0_M_AXI_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
- crc_axi_master_0_M_AXI_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
- crc_axi_master_0_M_AXI_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
- crc_axi_master_0_M_AXI_ARVALID <= S00_AXI_arvalid;
- crc_axi_master_0_M_AXI_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
- crc_axi_master_0_M_AXI_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
- crc_axi_master_0_M_AXI_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
- crc_axi_master_0_M_AXI_AWID(0) <= S00_AXI_awid(0);
- crc_axi_master_0_M_AXI_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
- crc_axi_master_0_M_AXI_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
- crc_axi_master_0_M_AXI_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
- crc_axi_master_0_M_AXI_AWVALID <= S00_AXI_awvalid;
- crc_axi_master_0_M_AXI_BREADY <= S00_AXI_bready;
- crc_axi_master_0_M_AXI_RREADY <= S00_AXI_rready;
- crc_axi_master_0_M_AXI_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
- crc_axi_master_0_M_AXI_WID(31 downto 0) <= S00_AXI_wid(31 downto 0);
- crc_axi_master_0_M_AXI_WLAST <= S00_AXI_wlast;
- crc_axi_master_0_M_AXI_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
- crc_axi_master_0_M_AXI_WVALID <= S00_AXI_wvalid;
-axi_mem_intercon: entity work.crc_axi_master_syn_HP_Port_axi_mem_intercon_0
- port map (
- ACLK => processing_system7_0_FCLK_CLK0,
- ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
- M00_ACLK => processing_system7_0_FCLK_CLK0,
- M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
- M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
- M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
- M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
- M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
- M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
- M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
- M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
- M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
- M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
- M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
- M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
- M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
- M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
- M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
- M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
- M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
- M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
- M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
- M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
- M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
- M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
- M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
- M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
- M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
- M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
- M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
- M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
- M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
- M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
- M00_AXI_wid(31 downto 0) => axi_mem_intercon_M00_AXI_WID(31 downto 0),
- M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
- M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
- M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
- M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
- S00_ACLK => processing_system7_0_FCLK_CLK0,
- S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
- S00_AXI_araddr(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- S00_AXI_arburst(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- S00_AXI_arcache(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
- S00_AXI_arid(0) => crc_axi_master_0_M_AXI_ARID(0),
- S00_AXI_arlen(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- S00_AXI_arprot(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
- S00_AXI_arready => crc_axi_master_0_M_AXI_ARREADY,
- S00_AXI_arsize(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- S00_AXI_arvalid => crc_axi_master_0_M_AXI_ARVALID,
- S00_AXI_awaddr(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- S00_AXI_awburst(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- S00_AXI_awcache(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
- S00_AXI_awid(0) => crc_axi_master_0_M_AXI_AWID(0),
- S00_AXI_awlen(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- S00_AXI_awprot(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
- S00_AXI_awready => crc_axi_master_0_M_AXI_AWREADY,
- S00_AXI_awsize(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- S00_AXI_awvalid => crc_axi_master_0_M_AXI_AWVALID,
- S00_AXI_bid(5 downto 0) => crc_axi_master_0_M_AXI_BID(5 downto 0),
- S00_AXI_bready => crc_axi_master_0_M_AXI_BREADY,
- S00_AXI_bresp(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- S00_AXI_bvalid => crc_axi_master_0_M_AXI_BVALID,
- S00_AXI_rdata(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- S00_AXI_rid(5 downto 0) => crc_axi_master_0_M_AXI_RID(5 downto 0),
- S00_AXI_rlast => crc_axi_master_0_M_AXI_RLAST,
- S00_AXI_rready => crc_axi_master_0_M_AXI_RREADY,
- S00_AXI_rresp(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- S00_AXI_rvalid => crc_axi_master_0_M_AXI_RVALID,
- S00_AXI_wdata(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- S00_AXI_wid(31 downto 0) => crc_axi_master_0_M_AXI_WID(31 downto 0),
- S00_AXI_wlast => crc_axi_master_0_M_AXI_WLAST,
- S00_AXI_wready => crc_axi_master_0_M_AXI_WREADY,
- S00_AXI_wstrb(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- S00_AXI_wvalid => crc_axi_master_0_M_AXI_WVALID
- );
-processing_system7_0: component crc_axi_master_syn_HP_Port_processing_system7_0_0
- port map (
- DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
- DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
- DDR_CAS_n => DDR_cas_n,
- DDR_CKE => DDR_cke,
- DDR_CS_n => DDR_cs_n,
- DDR_Clk => DDR_ck_p,
- DDR_Clk_n => DDR_ck_n,
- DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
- DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
- DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
- DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
- DDR_DRSTB => DDR_reset_n,
- DDR_ODT => DDR_odt,
- DDR_RAS_n => DDR_ras_n,
- DDR_VRN => FIXED_IO_ddr_vrn,
- DDR_VRP => FIXED_IO_ddr_vrp,
- DDR_WEB => DDR_we_n,
- FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
- FCLK_CLK1 => NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED,
- FCLK_CLK2 => NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED,
- FCLK_CLK3 => NLW_processing_system7_0_FCLK_CLK3_UNCONNECTED,
- FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
- IRQ_F2P(0) => '0',
- MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
- PS_CLK => FIXED_IO_ps_clk,
- PS_PORB => FIXED_IO_ps_porb,
- PS_SRSTB => FIXED_IO_ps_srstb,
- SDIO0_WP => xlconstant_0_dout(0),
- S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
- S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
- S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
- S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
- S_AXI_HP0_ARID(5 downto 1) => B"00000",
- S_AXI_HP0_ARID(0) => axi_mem_intercon_M00_AXI_ARID(0),
- S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
- S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
- S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
- S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
- S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
- S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
- S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
- S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
- S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
- S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
- S_AXI_HP0_AWID(5 downto 1) => B"00000",
- S_AXI_HP0_AWID(0) => axi_mem_intercon_M00_AXI_AWID(0),
- S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
- S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
- S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
- S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
- S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
- S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
- S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
- S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
- S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
- S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
- S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
- S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
- S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
- S_AXI_HP0_RDATA(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
- S_AXI_HP0_RDISSUECAP1_EN => '0',
- S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
- S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
- S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
- S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
- S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
- S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
- S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
- S_AXI_HP0_WDATA(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
- S_AXI_HP0_WID(5 downto 0) => axi_mem_intercon_M00_AXI_WID(5 downto 0),
- S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
- S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
- S_AXI_HP0_WRISSUECAP1_EN => '0',
- S_AXI_HP0_WSTRB(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
- S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
- TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
- TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
- TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
- USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
- USB0_VBUS_PWRFAULT => '0',
- USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
- );
-rst_ps7_0_100M: component crc_axi_master_syn_HP_Port_rst_ps7_0_100M_0
- port map (
- aux_reset_in => '1',
- bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0),
- dcm_locked => '1',
- ext_reset_in => processing_system7_0_FCLK_RESET0_N,
- interconnect_aresetn(0) => NLW_rst_ps7_0_100M_interconnect_aresetn_UNCONNECTED(0),
- mb_debug_sys_rst => '0',
- mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED,
- peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0),
- peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0),
- slowest_sync_clk => processing_system7_0_FCLK_CLK0
- );
-xlconstant_0: component crc_axi_master_syn_HP_Port_xlconstant_0_0
- port map (
- dout(0) => xlconstant_0_dout(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity crc_axi_master_syn_HP_Port is
- port (
- DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_cas_n : inout STD_LOGIC;
- DDR_ck_n : inout STD_LOGIC;
- DDR_ck_p : inout STD_LOGIC;
- DDR_cke : inout STD_LOGIC;
- DDR_cs_n : inout STD_LOGIC;
- DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_odt : inout STD_LOGIC;
- DDR_ras_n : inout STD_LOGIC;
- DDR_reset_n : inout STD_LOGIC;
- DDR_we_n : inout STD_LOGIC;
- FIXED_IO_ddr_vrn : inout STD_LOGIC;
- FIXED_IO_ddr_vrp : inout STD_LOGIC;
- FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- FIXED_IO_ps_clk : inout STD_LOGIC;
- FIXED_IO_ps_porb : inout STD_LOGIC;
- FIXED_IO_ps_srstb : inout STD_LOGIC
- );
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of crc_axi_master_syn_HP_Port : entity is "crc_axi_master_syn_HP_Port,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_syn_HP_Port,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=10,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=3,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=1,da_clkrst_cnt=2,synth_mode=OOC_per_IP}";
- attribute HW_HANDOFF : string;
- attribute HW_HANDOFF of crc_axi_master_syn_HP_Port : entity is "crc_axi_master_syn_HP_Port.hwdef";
-end crc_axi_master_syn_HP_Port;
-
-architecture STRUCTURE of crc_axi_master_syn_HP_Port is
- component crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0 is
- port (
- clk : in STD_LOGIC;
- resetn : in STD_LOGIC;
- finished : out STD_LOGIC;
- start : out STD_LOGIC;
- write : out STD_LOGIC;
- addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- size : out STD_LOGIC_VECTOR ( 3 downto 0 );
- axi_idle : in STD_LOGIC
- );
- end component crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0;
- component crc_axi_master_syn_HP_Port_system_ila_0_0 is
- port (
- clk : in STD_LOGIC;
- probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
- probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
- probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
- probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe6 : in STD_LOGIC_VECTOR ( 31 downto 0 );
- probe7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
- probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- SLOT_0_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- SLOT_0_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_awvalid : in STD_LOGIC;
- SLOT_0_AXI_awready : in STD_LOGIC;
- SLOT_0_AXI_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_wlast : in STD_LOGIC;
- SLOT_0_AXI_wvalid : in STD_LOGIC;
- SLOT_0_AXI_wready : in STD_LOGIC;
- SLOT_0_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_bvalid : in STD_LOGIC;
- SLOT_0_AXI_bready : in STD_LOGIC;
- SLOT_0_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- SLOT_0_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- SLOT_0_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_arvalid : in STD_LOGIC;
- SLOT_0_AXI_arready : in STD_LOGIC;
- SLOT_0_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_rlast : in STD_LOGIC;
- SLOT_0_AXI_rvalid : in STD_LOGIC;
- SLOT_0_AXI_rready : in STD_LOGIC;
- resetn : in STD_LOGIC
- );
- end component crc_axi_master_syn_HP_Port_system_ila_0_0;
- component crc_axi_master_syn_HP_Port_crc_axi_ram_0_0 is
- port (
- waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
- wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- we : in STD_LOGIC;
- raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
- rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- re : in STD_LOGIC
- );
- end component crc_axi_master_syn_HP_Port_crc_axi_ram_0_0;
- component crc_axi_master_syn_HP_Port_crc_axi_master_0_0 is
- port (
- CLK : in STD_LOGIC;
- RESETN : in STD_LOGIC;
- start : in STD_LOGIC;
- write : in STD_LOGIC;
- addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
- size : in STD_LOGIC_VECTOR ( 3 downto 0 );
- ip_idle : out STD_LOGIC;
- waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
- wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- we : out STD_LOGIC;
- raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
- rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- re : out STD_LOGIC;
- M_AXI_ARREADY : in STD_LOGIC;
- M_AXI_ARVALID : out STD_LOGIC;
- M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_RREADY : out STD_LOGIC;
- M_AXI_RVALID : in STD_LOGIC;
- M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_RLAST : in STD_LOGIC;
- M_AXI_AWREADY : in STD_LOGIC;
- M_AXI_AWVALID : out STD_LOGIC;
- M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_WREADY : in STD_LOGIC;
- M_AXI_WVALID : out STD_LOGIC;
- M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_WLAST : out STD_LOGIC;
- M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_BREADY : out STD_LOGIC;
- M_AXI_BVALID : in STD_LOGIC;
- M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
- );
- end component crc_axi_master_syn_HP_Port_crc_axi_master_0_0;
- signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO : string;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARADDR : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARADDR";
- attribute DEBUG : string;
- attribute DEBUG of crc_axi_master_0_M_AXI_ARADDR : signal is "true";
- attribute MARK_DEBUG : boolean;
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARADDR : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARBURST : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARBURST";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARBURST : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARBURST : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARCACHE : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARCACHE";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARCACHE : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARCACHE : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARID";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARLEN : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARLEN";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARLEN : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARLEN : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARPROT : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARPROT";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARPROT : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARPROT : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARSIZE : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARSIZE";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARSIZE : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARSIZE : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARVALID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWADDR : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWADDR";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWADDR : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWADDR : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWBURST : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWBURST";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWBURST : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWBURST : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWCACHE : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWCACHE";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWCACHE : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWCACHE : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWID";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWLEN : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWLEN";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWLEN : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWLEN : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWPROT : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWPROT";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWPROT : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWPROT : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWSIZE : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWSIZE";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWSIZE : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWSIZE : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWVALID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_BID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 BID";
- attribute DEBUG of crc_axi_master_0_M_AXI_BID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_BID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_BREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 BREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_BREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_BREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_BRESP : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 BRESP";
- attribute DEBUG of crc_axi_master_0_M_AXI_BRESP : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_BRESP : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_BVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 BVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_BVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_BVALID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RDATA : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RDATA";
- attribute DEBUG of crc_axi_master_0_M_AXI_RDATA : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RDATA : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RID";
- attribute DEBUG of crc_axi_master_0_M_AXI_RID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RLAST : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RLAST";
- attribute DEBUG of crc_axi_master_0_M_AXI_RLAST : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RLAST : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_RREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RRESP : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RRESP";
- attribute DEBUG of crc_axi_master_0_M_AXI_RRESP : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RRESP : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_RVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RVALID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WDATA : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WDATA";
- attribute DEBUG of crc_axi_master_0_M_AXI_WDATA : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WDATA : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WID";
- attribute DEBUG of crc_axi_master_0_M_AXI_WID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WLAST : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WLAST";
- attribute DEBUG of crc_axi_master_0_M_AXI_WLAST : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WLAST : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_WREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WSTRB : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WSTRB";
- attribute DEBUG of crc_axi_master_0_M_AXI_WSTRB : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WSTRB : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_WVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WVALID : signal is std.standard.true;
- signal crc_axi_master_0_ip_idle : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_ip_idle : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_ip_idle : signal is std.standard.true;
- signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_raddr : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_raddr : signal is std.standard.true;
- signal crc_axi_master_0_re : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_re : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_re : signal is std.standard.true;
- signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_waddr : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_waddr : signal is std.standard.true;
- signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_wdata : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_wdata : signal is std.standard.true;
- signal crc_axi_master_0_we : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_we : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_we : signal is std.standard.true;
- signal crc_axi_master_contr_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_contr_0_addr : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_contr_0_addr : signal is std.standard.true;
- signal crc_axi_master_contr_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_contr_0_size : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_contr_0_size : signal is std.standard.true;
- signal crc_axi_master_contr_0_start : STD_LOGIC;
- attribute DEBUG of crc_axi_master_contr_0_start : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_contr_0_start : signal is std.standard.true;
- signal crc_axi_master_contr_0_write : STD_LOGIC;
- attribute DEBUG of crc_axi_master_contr_0_write : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_contr_0_write : signal is std.standard.true;
- signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_ram_0_rdata : signal is "true";
- attribute MARK_DEBUG of crc_axi_ram_0_rdata : signal is std.standard.true;
- signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
- signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_CKE : STD_LOGIC;
- signal processing_system7_0_DDR_CK_N : STD_LOGIC;
- signal processing_system7_0_DDR_CK_P : STD_LOGIC;
- signal processing_system7_0_DDR_CS_N : STD_LOGIC;
- signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_ODT : STD_LOGIC;
- signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
- signal processing_system7_0_DDR_WE_N : STD_LOGIC;
- signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
- signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
- signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_crc_axi_master_contr_0_finished_UNCONNECTED : STD_LOGIC;
- attribute X_INTERFACE_INFO : string;
- attribute X_INTERFACE_INFO of DDR_cas_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
- attribute X_INTERFACE_INFO of DDR_ck_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
- attribute X_INTERFACE_INFO of DDR_ck_p : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
- attribute X_INTERFACE_INFO of DDR_cke : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
- attribute X_INTERFACE_INFO of DDR_cs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
- attribute X_INTERFACE_INFO of DDR_odt : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
- attribute X_INTERFACE_INFO of DDR_ras_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
- attribute X_INTERFACE_INFO of DDR_reset_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
- attribute X_INTERFACE_INFO of DDR_we_n : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrn : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
- attribute X_INTERFACE_PARAMETER : string;
- attribute X_INTERFACE_PARAMETER of FIXED_IO_ddr_vrn : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrp : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_clk : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_porb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_srstb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
- attribute X_INTERFACE_INFO of DDR_addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
- attribute X_INTERFACE_PARAMETER of DDR_addr : signal is "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250";
- attribute X_INTERFACE_INFO of DDR_ba : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
- attribute X_INTERFACE_INFO of DDR_dm : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
- attribute X_INTERFACE_INFO of DDR_dq : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
- attribute X_INTERFACE_INFO of DDR_dqs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
- attribute X_INTERFACE_INFO of DDR_dqs_p : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
- attribute X_INTERFACE_INFO of FIXED_IO_mio : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
-begin
-PS: entity work.PS_imp_1MAYGMX
- port map (
- DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
- DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
- DDR_cas_n => DDR_cas_n,
- DDR_ck_n => DDR_ck_n,
- DDR_ck_p => DDR_ck_p,
- DDR_cke => DDR_cke,
- DDR_cs_n => DDR_cs_n,
- DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
- DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
- DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
- DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
- DDR_odt => DDR_odt,
- DDR_ras_n => DDR_ras_n,
- DDR_reset_n => DDR_reset_n,
- DDR_we_n => DDR_we_n,
- FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
- FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
- FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
- FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
- FIXED_IO_ps_clk => FIXED_IO_ps_clk,
- FIXED_IO_ps_porb => FIXED_IO_ps_porb,
- FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
- S00_ARESETN(0) => rst_ps7_0_100M_peripheral_aresetn(0),
- S00_AXI_araddr(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- S00_AXI_arburst(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- S00_AXI_arcache(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
- S00_AXI_arid(0) => crc_axi_master_0_M_AXI_ARID(0),
- S00_AXI_arlen(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- S00_AXI_arprot(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
- S00_AXI_arready => crc_axi_master_0_M_AXI_ARREADY,
- S00_AXI_arsize(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- S00_AXI_arvalid => crc_axi_master_0_M_AXI_ARVALID,
- S00_AXI_awaddr(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- S00_AXI_awburst(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- S00_AXI_awcache(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
- S00_AXI_awid(0) => crc_axi_master_0_M_AXI_AWID(0),
- S00_AXI_awlen(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- S00_AXI_awprot(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
- S00_AXI_awready => crc_axi_master_0_M_AXI_AWREADY,
- S00_AXI_awsize(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- S00_AXI_awvalid => crc_axi_master_0_M_AXI_AWVALID,
- S00_AXI_bid(5 downto 0) => crc_axi_master_0_M_AXI_BID(5 downto 0),
- S00_AXI_bready => crc_axi_master_0_M_AXI_BREADY,
- S00_AXI_bresp(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- S00_AXI_bvalid => crc_axi_master_0_M_AXI_BVALID,
- S00_AXI_rdata(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- S00_AXI_rid(5 downto 0) => crc_axi_master_0_M_AXI_RID(5 downto 0),
- S00_AXI_rlast => crc_axi_master_0_M_AXI_RLAST,
- S00_AXI_rready => crc_axi_master_0_M_AXI_RREADY,
- S00_AXI_rresp(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- S00_AXI_rvalid => crc_axi_master_0_M_AXI_RVALID,
- S00_AXI_wdata(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- S00_AXI_wid(31 downto 0) => crc_axi_master_0_M_AXI_WID(31 downto 0),
- S00_AXI_wlast => crc_axi_master_0_M_AXI_WLAST,
- S00_AXI_wready => crc_axi_master_0_M_AXI_WREADY,
- S00_AXI_wstrb(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- S00_AXI_wvalid => crc_axi_master_0_M_AXI_WVALID
- );
-crc_axi_master_0: component crc_axi_master_syn_HP_Port_crc_axi_master_0_0
- port map (
- CLK => processing_system7_0_FCLK_CLK0,
- M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- M_AXI_ARCACHE(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
- M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
- M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- M_AXI_ARPROT(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
- M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
- M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
- M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- M_AXI_AWCACHE(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
- M_AXI_AWID(0) => crc_axi_master_0_M_AXI_AWID(0),
- M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- M_AXI_AWPROT(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
- M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
- M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
- M_AXI_BID(31 downto 6) => B"00000000000000000000000000",
- M_AXI_BID(5 downto 0) => crc_axi_master_0_M_AXI_BID(5 downto 0),
- M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
- M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
- M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
- M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
- M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
- M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
- M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- M_AXI_WID(31 downto 0) => crc_axi_master_0_M_AXI_WID(31 downto 0),
- M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
- M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
- M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
- RESETN => rst_ps7_0_100M_peripheral_aresetn(0),
- addr_axi(31 downto 0) => crc_axi_master_contr_0_addr(31 downto 0),
- ip_idle => crc_axi_master_0_ip_idle,
- raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- re => crc_axi_master_0_re,
- size(3 downto 0) => crc_axi_master_contr_0_size(3 downto 0),
- start => crc_axi_master_contr_0_start,
- waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- we => crc_axi_master_0_we,
- write => crc_axi_master_contr_0_write
- );
-crc_axi_master_contr_0: component crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0
- port map (
- addr(31 downto 0) => crc_axi_master_contr_0_addr(31 downto 0),
- axi_idle => crc_axi_master_0_ip_idle,
- clk => processing_system7_0_FCLK_CLK0,
- finished => NLW_crc_axi_master_contr_0_finished_UNCONNECTED,
- resetn => rst_ps7_0_100M_peripheral_aresetn(0),
- size(3 downto 0) => crc_axi_master_contr_0_size(3 downto 0),
- start => crc_axi_master_contr_0_start,
- write => crc_axi_master_contr_0_write
- );
-crc_axi_ram_0: component crc_axi_master_syn_HP_Port_crc_axi_ram_0_0
- port map (
- raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- re => crc_axi_master_0_re,
- waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- we => crc_axi_master_0_we
- );
-system_ila_0: component crc_axi_master_syn_HP_Port_system_ila_0_0
- port map (
- SLOT_0_AXI_araddr(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- SLOT_0_AXI_arburst(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- SLOT_0_AXI_arcache(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
- SLOT_0_AXI_arid(0) => crc_axi_master_0_M_AXI_ARID(0),
- SLOT_0_AXI_arlen(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- SLOT_0_AXI_arlock(1 downto 0) => B"00",
- SLOT_0_AXI_arprot(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
- SLOT_0_AXI_arqos(3 downto 0) => B"0000",
- SLOT_0_AXI_arready => crc_axi_master_0_M_AXI_ARREADY,
- SLOT_0_AXI_arsize(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- SLOT_0_AXI_arvalid => crc_axi_master_0_M_AXI_ARVALID,
- SLOT_0_AXI_awaddr(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- SLOT_0_AXI_awburst(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- SLOT_0_AXI_awcache(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
- SLOT_0_AXI_awid(0) => crc_axi_master_0_M_AXI_AWID(0),
- SLOT_0_AXI_awlen(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- SLOT_0_AXI_awlock(1 downto 0) => B"00",
- SLOT_0_AXI_awprot(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
- SLOT_0_AXI_awqos(3 downto 0) => B"0000",
- SLOT_0_AXI_awready => crc_axi_master_0_M_AXI_AWREADY,
- SLOT_0_AXI_awsize(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- SLOT_0_AXI_awvalid => crc_axi_master_0_M_AXI_AWVALID,
- SLOT_0_AXI_bid(0) => crc_axi_master_0_M_AXI_BID(0),
- SLOT_0_AXI_bready => crc_axi_master_0_M_AXI_BREADY,
- SLOT_0_AXI_bresp(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- SLOT_0_AXI_bvalid => crc_axi_master_0_M_AXI_BVALID,
- SLOT_0_AXI_rdata(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- SLOT_0_AXI_rid(0) => crc_axi_master_0_M_AXI_RID(0),
- SLOT_0_AXI_rlast => crc_axi_master_0_M_AXI_RLAST,
- SLOT_0_AXI_rready => crc_axi_master_0_M_AXI_RREADY,
- SLOT_0_AXI_rresp(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- SLOT_0_AXI_rvalid => crc_axi_master_0_M_AXI_RVALID,
- SLOT_0_AXI_wdata(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- SLOT_0_AXI_wid(0) => crc_axi_master_0_M_AXI_WID(0),
- SLOT_0_AXI_wlast => crc_axi_master_0_M_AXI_WLAST,
- SLOT_0_AXI_wready => crc_axi_master_0_M_AXI_WREADY,
- SLOT_0_AXI_wstrb(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- SLOT_0_AXI_wvalid => crc_axi_master_0_M_AXI_WVALID,
- clk => processing_system7_0_FCLK_CLK0,
- probe0(0) => crc_axi_master_0_ip_idle,
- probe1(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- probe10(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- probe2(0) => crc_axi_master_0_re,
- probe3(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- probe4(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- probe5(0) => crc_axi_master_0_we,
- probe6(31 downto 0) => crc_axi_master_contr_0_addr(31 downto 0),
- probe7(3 downto 0) => crc_axi_master_contr_0_size(3 downto 0),
- probe8(0) => crc_axi_master_contr_0_start,
- probe9(0) => crc_axi_master_contr_0_write,
- resetn => rst_ps7_0_100M_peripheral_aresetn(0)
- );
-end STRUCTURE;
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/synth/crc_axi_master_syn_HP_Port.vhd b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/synth/crc_axi_master_syn_HP_Port.vhd
deleted file mode 100644
index 5f4c24e..0000000
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/synth/crc_axi_master_syn_HP_Port.vhd
+++ /dev/null
@@ -1,1601 +0,0 @@
---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
---Date : Fri Jan 31 01:48:41 2025
---Host : BiermannSurface running 64-bit major release (build 9200)
---Command : generate_target crc_axi_master_syn_HP_Port.bd
---Design : crc_axi_master_syn_HP_Port
---Purpose : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity s00_couplers_imp_1N0N7ZR is
- port (
- M_ACLK : in STD_LOGIC;
- M_ARESETN : in STD_LOGIC;
- M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_arready : in STD_LOGIC;
- M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_arvalid : out STD_LOGIC;
- M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_awready : in STD_LOGIC;
- M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_awvalid : out STD_LOGIC;
- M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
- M_AXI_bready : out STD_LOGIC;
- M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_bvalid : in STD_LOGIC;
- M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
- M_AXI_rlast : in STD_LOGIC;
- M_AXI_rready : out STD_LOGIC;
- M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_rvalid : in STD_LOGIC;
- M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_wid : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_wlast : out STD_LOGIC;
- M_AXI_wready : in STD_LOGIC;
- M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_wvalid : out STD_LOGIC;
- S_ACLK : in STD_LOGIC;
- S_ARESETN : in STD_LOGIC;
- S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_arready : out STD_LOGIC;
- S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_arvalid : in STD_LOGIC;
- S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_awready : out STD_LOGIC;
- S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_awvalid : in STD_LOGIC;
- S_AXI_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_bready : in STD_LOGIC;
- S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_bvalid : out STD_LOGIC;
- S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_rlast : out STD_LOGIC;
- S_AXI_rready : in STD_LOGIC;
- S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_rvalid : out STD_LOGIC;
- S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_wid : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_wlast : in STD_LOGIC;
- S_AXI_wready : out STD_LOGIC;
- S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_wvalid : in STD_LOGIC
- );
-end s00_couplers_imp_1N0N7ZR;
-
-architecture STRUCTURE of s00_couplers_imp_1N0N7ZR is
- signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s00_couplers_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s00_couplers_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal s00_couplers_to_s00_couplers_RLAST : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_s00_couplers_WLAST : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC;
- signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC;
-begin
- M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
- M_AXI_arburst(1 downto 0) <= s00_couplers_to_s00_couplers_ARBURST(1 downto 0);
- M_AXI_arcache(3 downto 0) <= s00_couplers_to_s00_couplers_ARCACHE(3 downto 0);
- M_AXI_arid(0) <= s00_couplers_to_s00_couplers_ARID(0);
- M_AXI_arlen(3 downto 0) <= s00_couplers_to_s00_couplers_ARLEN(3 downto 0);
- M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
- M_AXI_arsize(2 downto 0) <= s00_couplers_to_s00_couplers_ARSIZE(2 downto 0);
- M_AXI_arvalid <= s00_couplers_to_s00_couplers_ARVALID;
- M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
- M_AXI_awburst(1 downto 0) <= s00_couplers_to_s00_couplers_AWBURST(1 downto 0);
- M_AXI_awcache(3 downto 0) <= s00_couplers_to_s00_couplers_AWCACHE(3 downto 0);
- M_AXI_awid(0) <= s00_couplers_to_s00_couplers_AWID(0);
- M_AXI_awlen(3 downto 0) <= s00_couplers_to_s00_couplers_AWLEN(3 downto 0);
- M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
- M_AXI_awsize(2 downto 0) <= s00_couplers_to_s00_couplers_AWSIZE(2 downto 0);
- M_AXI_awvalid <= s00_couplers_to_s00_couplers_AWVALID;
- M_AXI_bready <= s00_couplers_to_s00_couplers_BREADY;
- M_AXI_rready <= s00_couplers_to_s00_couplers_RREADY;
- M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
- M_AXI_wid(31 downto 0) <= s00_couplers_to_s00_couplers_WID(31 downto 0);
- M_AXI_wlast <= s00_couplers_to_s00_couplers_WLAST;
- M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
- M_AXI_wvalid <= s00_couplers_to_s00_couplers_WVALID;
- S_AXI_arready <= s00_couplers_to_s00_couplers_ARREADY;
- S_AXI_awready <= s00_couplers_to_s00_couplers_AWREADY;
- S_AXI_bid(5 downto 0) <= s00_couplers_to_s00_couplers_BID(5 downto 0);
- S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
- S_AXI_bvalid <= s00_couplers_to_s00_couplers_BVALID;
- S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
- S_AXI_rid(5 downto 0) <= s00_couplers_to_s00_couplers_RID(5 downto 0);
- S_AXI_rlast <= s00_couplers_to_s00_couplers_RLAST;
- S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
- S_AXI_rvalid <= s00_couplers_to_s00_couplers_RVALID;
- S_AXI_wready <= s00_couplers_to_s00_couplers_WREADY;
- s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
- s00_couplers_to_s00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
- s00_couplers_to_s00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
- s00_couplers_to_s00_couplers_ARID(0) <= S_AXI_arid(0);
- s00_couplers_to_s00_couplers_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
- s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
- s00_couplers_to_s00_couplers_ARREADY <= M_AXI_arready;
- s00_couplers_to_s00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
- s00_couplers_to_s00_couplers_ARVALID <= S_AXI_arvalid;
- s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
- s00_couplers_to_s00_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
- s00_couplers_to_s00_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
- s00_couplers_to_s00_couplers_AWID(0) <= S_AXI_awid(0);
- s00_couplers_to_s00_couplers_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
- s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
- s00_couplers_to_s00_couplers_AWREADY <= M_AXI_awready;
- s00_couplers_to_s00_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
- s00_couplers_to_s00_couplers_AWVALID <= S_AXI_awvalid;
- s00_couplers_to_s00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
- s00_couplers_to_s00_couplers_BREADY <= S_AXI_bready;
- s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
- s00_couplers_to_s00_couplers_BVALID <= M_AXI_bvalid;
- s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
- s00_couplers_to_s00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
- s00_couplers_to_s00_couplers_RLAST <= M_AXI_rlast;
- s00_couplers_to_s00_couplers_RREADY <= S_AXI_rready;
- s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
- s00_couplers_to_s00_couplers_RVALID <= M_AXI_rvalid;
- s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
- s00_couplers_to_s00_couplers_WID(31 downto 0) <= S_AXI_wid(31 downto 0);
- s00_couplers_to_s00_couplers_WLAST <= S_AXI_wlast;
- s00_couplers_to_s00_couplers_WREADY <= M_AXI_wready;
- s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
- s00_couplers_to_s00_couplers_WVALID <= S_AXI_wvalid;
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity crc_axi_master_syn_HP_Port_axi_mem_intercon_0 is
- port (
- ACLK : in STD_LOGIC;
- ARESETN : in STD_LOGIC;
- M00_ACLK : in STD_LOGIC;
- M00_ARESETN : in STD_LOGIC;
- M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
- M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M00_AXI_arready : in STD_LOGIC;
- M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M00_AXI_arvalid : out STD_LOGIC;
- M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
- M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M00_AXI_awready : in STD_LOGIC;
- M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M00_AXI_awvalid : out STD_LOGIC;
- M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
- M00_AXI_bready : out STD_LOGIC;
- M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M00_AXI_bvalid : in STD_LOGIC;
- M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
- M00_AXI_rlast : in STD_LOGIC;
- M00_AXI_rready : out STD_LOGIC;
- M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M00_AXI_rvalid : in STD_LOGIC;
- M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_wid : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M00_AXI_wlast : out STD_LOGIC;
- M00_AXI_wready : in STD_LOGIC;
- M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M00_AXI_wvalid : out STD_LOGIC;
- S00_ACLK : in STD_LOGIC;
- S00_ARESETN : in STD_LOGIC;
- S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_arready : out STD_LOGIC;
- S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_arvalid : in STD_LOGIC;
- S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_awready : out STD_LOGIC;
- S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_awvalid : in STD_LOGIC;
- S00_AXI_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S00_AXI_bready : in STD_LOGIC;
- S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_bvalid : out STD_LOGIC;
- S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S00_AXI_rlast : out STD_LOGIC;
- S00_AXI_rready : in STD_LOGIC;
- S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_rvalid : out STD_LOGIC;
- S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_wid : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_wlast : in STD_LOGIC;
- S00_AXI_wready : out STD_LOGIC;
- S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_wvalid : in STD_LOGIC
- );
-end crc_axi_master_syn_HP_Port_axi_mem_intercon_0;
-
-architecture STRUCTURE of crc_axi_master_syn_HP_Port_axi_mem_intercon_0 is
- signal S00_ACLK_1 : STD_LOGIC;
- signal S00_ARESETN_1 : STD_LOGIC;
- signal axi_mem_intercon_ACLK_net : STD_LOGIC;
- signal axi_mem_intercon_ARESETN_net : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC;
- signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
- signal s00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal s00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
-begin
- M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
- M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
- M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
- M00_AXI_arid(0) <= s00_couplers_to_axi_mem_intercon_ARID(0);
- M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
- M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
- M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
- M00_AXI_arvalid <= s00_couplers_to_axi_mem_intercon_ARVALID;
- M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
- M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
- M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
- M00_AXI_awid(0) <= s00_couplers_to_axi_mem_intercon_AWID(0);
- M00_AXI_awlen(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
- M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
- M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
- M00_AXI_awvalid <= s00_couplers_to_axi_mem_intercon_AWVALID;
- M00_AXI_bready <= s00_couplers_to_axi_mem_intercon_BREADY;
- M00_AXI_rready <= s00_couplers_to_axi_mem_intercon_RREADY;
- M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
- M00_AXI_wid(31 downto 0) <= s00_couplers_to_axi_mem_intercon_WID(31 downto 0);
- M00_AXI_wlast <= s00_couplers_to_axi_mem_intercon_WLAST;
- M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
- M00_AXI_wvalid <= s00_couplers_to_axi_mem_intercon_WVALID;
- S00_ACLK_1 <= S00_ACLK;
- S00_ARESETN_1 <= S00_ARESETN;
- S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
- S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY;
- S00_AXI_bid(5 downto 0) <= axi_mem_intercon_to_s00_couplers_BID(5 downto 0);
- S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0);
- S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID;
- S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
- S00_AXI_rid(5 downto 0) <= axi_mem_intercon_to_s00_couplers_RID(5 downto 0);
- S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
- S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
- S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
- S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY;
- axi_mem_intercon_ACLK_net <= M00_ACLK;
- axi_mem_intercon_ARESETN_net <= M00_ARESETN;
- axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
- axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
- axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
- axi_mem_intercon_to_s00_couplers_ARID(0) <= S00_AXI_arid(0);
- axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
- axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
- axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
- axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
- axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
- axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
- axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
- axi_mem_intercon_to_s00_couplers_AWID(0) <= S00_AXI_awid(0);
- axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
- axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
- axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
- axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
- axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready;
- axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
- axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
- axi_mem_intercon_to_s00_couplers_WID(31 downto 0) <= S00_AXI_wid(31 downto 0);
- axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast;
- axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
- axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid;
- s00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
- s00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
- s00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
- s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
- s00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
- s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
- s00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
- s00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
- s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
- s00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
- s00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
-s00_couplers: entity work.s00_couplers_imp_1N0N7ZR
- port map (
- M_ACLK => axi_mem_intercon_ACLK_net,
- M_ARESETN => axi_mem_intercon_ARESETN_net,
- M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
- M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
- M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
- M_AXI_arid(0) => s00_couplers_to_axi_mem_intercon_ARID(0),
- M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
- M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
- M_AXI_arready => s00_couplers_to_axi_mem_intercon_ARREADY,
- M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
- M_AXI_arvalid => s00_couplers_to_axi_mem_intercon_ARVALID,
- M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
- M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
- M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
- M_AXI_awid(0) => s00_couplers_to_axi_mem_intercon_AWID(0),
- M_AXI_awlen(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
- M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
- M_AXI_awready => s00_couplers_to_axi_mem_intercon_AWREADY,
- M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
- M_AXI_awvalid => s00_couplers_to_axi_mem_intercon_AWVALID,
- M_AXI_bid(5 downto 0) => s00_couplers_to_axi_mem_intercon_BID(5 downto 0),
- M_AXI_bready => s00_couplers_to_axi_mem_intercon_BREADY,
- M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
- M_AXI_bvalid => s00_couplers_to_axi_mem_intercon_BVALID,
- M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
- M_AXI_rid(5 downto 0) => s00_couplers_to_axi_mem_intercon_RID(5 downto 0),
- M_AXI_rlast => s00_couplers_to_axi_mem_intercon_RLAST,
- M_AXI_rready => s00_couplers_to_axi_mem_intercon_RREADY,
- M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
- M_AXI_rvalid => s00_couplers_to_axi_mem_intercon_RVALID,
- M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
- M_AXI_wid(31 downto 0) => s00_couplers_to_axi_mem_intercon_WID(31 downto 0),
- M_AXI_wlast => s00_couplers_to_axi_mem_intercon_WLAST,
- M_AXI_wready => s00_couplers_to_axi_mem_intercon_WREADY,
- M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
- M_AXI_wvalid => s00_couplers_to_axi_mem_intercon_WVALID,
- S_ACLK => S00_ACLK_1,
- S_ARESETN => S00_ARESETN_1,
- S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
- S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
- S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
- S_AXI_arid(0) => axi_mem_intercon_to_s00_couplers_ARID(0),
- S_AXI_arlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0),
- S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
- S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
- S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
- S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
- S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0),
- S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0),
- S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0),
- S_AXI_awid(0) => axi_mem_intercon_to_s00_couplers_AWID(0),
- S_AXI_awlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0),
- S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0),
- S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY,
- S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0),
- S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID,
- S_AXI_bid(5 downto 0) => axi_mem_intercon_to_s00_couplers_BID(5 downto 0),
- S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY,
- S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0),
- S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID,
- S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
- S_AXI_rid(5 downto 0) => axi_mem_intercon_to_s00_couplers_RID(5 downto 0),
- S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
- S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
- S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
- S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID,
- S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0),
- S_AXI_wid(31 downto 0) => axi_mem_intercon_to_s00_couplers_WID(31 downto 0),
- S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST,
- S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY,
- S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0),
- S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity PS_imp_1MAYGMX is
- port (
- DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_cas_n : inout STD_LOGIC;
- DDR_ck_n : inout STD_LOGIC;
- DDR_ck_p : inout STD_LOGIC;
- DDR_cke : inout STD_LOGIC;
- DDR_cs_n : inout STD_LOGIC;
- DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_odt : inout STD_LOGIC;
- DDR_ras_n : inout STD_LOGIC;
- DDR_reset_n : inout STD_LOGIC;
- DDR_we_n : inout STD_LOGIC;
- FCLK_CLK0 : out STD_LOGIC;
- FIXED_IO_ddr_vrn : inout STD_LOGIC;
- FIXED_IO_ddr_vrp : inout STD_LOGIC;
- FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- FIXED_IO_ps_clk : inout STD_LOGIC;
- FIXED_IO_ps_porb : inout STD_LOGIC;
- FIXED_IO_ps_srstb : inout STD_LOGIC;
- S00_ARESETN : out STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_arready : out STD_LOGIC;
- S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_arvalid : in STD_LOGIC;
- S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
- S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_awready : out STD_LOGIC;
- S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S00_AXI_awvalid : in STD_LOGIC;
- S00_AXI_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S00_AXI_bready : in STD_LOGIC;
- S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_bvalid : out STD_LOGIC;
- S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S00_AXI_rlast : out STD_LOGIC;
- S00_AXI_rready : in STD_LOGIC;
- S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S00_AXI_rvalid : out STD_LOGIC;
- S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_wid : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S00_AXI_wlast : in STD_LOGIC;
- S00_AXI_wready : out STD_LOGIC;
- S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S00_AXI_wvalid : in STD_LOGIC
- );
-end PS_imp_1MAYGMX;
-
-architecture STRUCTURE of PS_imp_1MAYGMX is
- component crc_axi_master_syn_HP_Port_processing_system7_0_0 is
- port (
- SDIO0_WP : in STD_LOGIC;
- TTC0_WAVE0_OUT : out STD_LOGIC;
- TTC0_WAVE1_OUT : out STD_LOGIC;
- TTC0_WAVE2_OUT : out STD_LOGIC;
- USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
- USB0_VBUS_PWRSELECT : out STD_LOGIC;
- USB0_VBUS_PWRFAULT : in STD_LOGIC;
- S_AXI_HP0_ARREADY : out STD_LOGIC;
- S_AXI_HP0_AWREADY : out STD_LOGIC;
- S_AXI_HP0_BVALID : out STD_LOGIC;
- S_AXI_HP0_RLAST : out STD_LOGIC;
- S_AXI_HP0_RVALID : out STD_LOGIC;
- S_AXI_HP0_WREADY : out STD_LOGIC;
- S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
- S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
- S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_ACLK : in STD_LOGIC;
- S_AXI_HP0_ARVALID : in STD_LOGIC;
- S_AXI_HP0_AWVALID : in STD_LOGIC;
- S_AXI_HP0_BREADY : in STD_LOGIC;
- S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
- S_AXI_HP0_RREADY : in STD_LOGIC;
- S_AXI_HP0_WLAST : in STD_LOGIC;
- S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
- S_AXI_HP0_WVALID : in STD_LOGIC;
- S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
- S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
- S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
- S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
- IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
- FCLK_CLK0 : out STD_LOGIC;
- FCLK_CLK1 : out STD_LOGIC;
- FCLK_CLK2 : out STD_LOGIC;
- FCLK_CLK3 : out STD_LOGIC;
- FCLK_RESET0_N : out STD_LOGIC;
- MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- DDR_CAS_n : inout STD_LOGIC;
- DDR_CKE : inout STD_LOGIC;
- DDR_Clk_n : inout STD_LOGIC;
- DDR_Clk : inout STD_LOGIC;
- DDR_CS_n : inout STD_LOGIC;
- DDR_DRSTB : inout STD_LOGIC;
- DDR_ODT : inout STD_LOGIC;
- DDR_RAS_n : inout STD_LOGIC;
- DDR_WEB : inout STD_LOGIC;
- DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_VRN : inout STD_LOGIC;
- DDR_VRP : inout STD_LOGIC;
- DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- PS_SRSTB : inout STD_LOGIC;
- PS_CLK : inout STD_LOGIC;
- PS_PORB : inout STD_LOGIC
- );
- end component crc_axi_master_syn_HP_Port_processing_system7_0_0;
- component crc_axi_master_syn_HP_Port_xlconstant_0_0 is
- port (
- dout : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component crc_axi_master_syn_HP_Port_xlconstant_0_0;
- component crc_axi_master_syn_HP_Port_rst_ps7_0_100M_0 is
- port (
- slowest_sync_clk : in STD_LOGIC;
- ext_reset_in : in STD_LOGIC;
- aux_reset_in : in STD_LOGIC;
- mb_debug_sys_rst : in STD_LOGIC;
- dcm_locked : in STD_LOGIC;
- mb_reset : out STD_LOGIC;
- bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
- peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
- interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
- peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component crc_axi_master_syn_HP_Port_rst_ps7_0_100M_0;
- signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
- signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
- signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG : string;
- attribute DEBUG of crc_axi_master_0_M_AXI_ARADDR : signal is "true";
- signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARBURST : signal is "true";
- signal crc_axi_master_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARCACHE : signal is "true";
- signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARID : signal is "true";
- signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARLEN : signal is "true";
- signal crc_axi_master_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARPROT : signal is "true";
- signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_ARREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_ARSIZE : signal is "true";
- signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_ARVALID : signal is "true";
- signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWADDR : signal is "true";
- signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWBURST : signal is "true";
- signal crc_axi_master_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWCACHE : signal is "true";
- signal crc_axi_master_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWID : signal is "true";
- signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWLEN : signal is "true";
- signal crc_axi_master_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWPROT : signal is "true";
- signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_AWREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_AWSIZE : signal is "true";
- signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_AWVALID : signal is "true";
- signal crc_axi_master_0_M_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_BID : signal is "true";
- signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_BREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_BRESP : signal is "true";
- signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_BVALID : signal is "true";
- signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_RDATA : signal is "true";
- signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_RID : signal is "true";
- signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_RLAST : signal is "true";
- signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_RREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_RRESP : signal is "true";
- signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_RVALID : signal is "true";
- signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_WDATA : signal is "true";
- signal crc_axi_master_0_M_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_WID : signal is "true";
- signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_WLAST : signal is "true";
- signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_WREADY : signal is "true";
- signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_M_AXI_WSTRB : signal is "true";
- signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_M_AXI_WVALID : signal is "true";
- signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
- signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_CKE : STD_LOGIC;
- signal processing_system7_0_DDR_CK_N : STD_LOGIC;
- signal processing_system7_0_DDR_CK_P : STD_LOGIC;
- signal processing_system7_0_DDR_CS_N : STD_LOGIC;
- signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_ODT : STD_LOGIC;
- signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
- signal processing_system7_0_DDR_WE_N : STD_LOGIC;
- signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
- signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
- signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
- signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
- signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
- signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_rst_ps7_0_100M_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- FCLK_CLK0 <= processing_system7_0_FCLK_CLK0;
- S00_ARESETN(0) <= rst_ps7_0_100M_peripheral_aresetn(0);
- S00_AXI_arready <= crc_axi_master_0_M_AXI_ARREADY;
- S00_AXI_awready <= crc_axi_master_0_M_AXI_AWREADY;
- S00_AXI_bid(5 downto 0) <= crc_axi_master_0_M_AXI_BID(5 downto 0);
- S00_AXI_bresp(1 downto 0) <= crc_axi_master_0_M_AXI_BRESP(1 downto 0);
- S00_AXI_bvalid <= crc_axi_master_0_M_AXI_BVALID;
- S00_AXI_rdata(31 downto 0) <= crc_axi_master_0_M_AXI_RDATA(31 downto 0);
- S00_AXI_rid(5 downto 0) <= crc_axi_master_0_M_AXI_RID(5 downto 0);
- S00_AXI_rlast <= crc_axi_master_0_M_AXI_RLAST;
- S00_AXI_rresp(1 downto 0) <= crc_axi_master_0_M_AXI_RRESP(1 downto 0);
- S00_AXI_rvalid <= crc_axi_master_0_M_AXI_RVALID;
- S00_AXI_wready <= crc_axi_master_0_M_AXI_WREADY;
- crc_axi_master_0_M_AXI_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
- crc_axi_master_0_M_AXI_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
- crc_axi_master_0_M_AXI_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
- crc_axi_master_0_M_AXI_ARID(0) <= S00_AXI_arid(0);
- crc_axi_master_0_M_AXI_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
- crc_axi_master_0_M_AXI_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
- crc_axi_master_0_M_AXI_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
- crc_axi_master_0_M_AXI_ARVALID <= S00_AXI_arvalid;
- crc_axi_master_0_M_AXI_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
- crc_axi_master_0_M_AXI_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
- crc_axi_master_0_M_AXI_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
- crc_axi_master_0_M_AXI_AWID(0) <= S00_AXI_awid(0);
- crc_axi_master_0_M_AXI_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
- crc_axi_master_0_M_AXI_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
- crc_axi_master_0_M_AXI_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
- crc_axi_master_0_M_AXI_AWVALID <= S00_AXI_awvalid;
- crc_axi_master_0_M_AXI_BREADY <= S00_AXI_bready;
- crc_axi_master_0_M_AXI_RREADY <= S00_AXI_rready;
- crc_axi_master_0_M_AXI_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
- crc_axi_master_0_M_AXI_WID(31 downto 0) <= S00_AXI_wid(31 downto 0);
- crc_axi_master_0_M_AXI_WLAST <= S00_AXI_wlast;
- crc_axi_master_0_M_AXI_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
- crc_axi_master_0_M_AXI_WVALID <= S00_AXI_wvalid;
-axi_mem_intercon: entity work.crc_axi_master_syn_HP_Port_axi_mem_intercon_0
- port map (
- ACLK => processing_system7_0_FCLK_CLK0,
- ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
- M00_ACLK => processing_system7_0_FCLK_CLK0,
- M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
- M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
- M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
- M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
- M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
- M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
- M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
- M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
- M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
- M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
- M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
- M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
- M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
- M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
- M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
- M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
- M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
- M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
- M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
- M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
- M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
- M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
- M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
- M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
- M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
- M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
- M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
- M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
- M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
- M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
- M00_AXI_wid(31 downto 0) => axi_mem_intercon_M00_AXI_WID(31 downto 0),
- M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
- M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
- M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
- M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
- S00_ACLK => processing_system7_0_FCLK_CLK0,
- S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
- S00_AXI_araddr(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- S00_AXI_arburst(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- S00_AXI_arcache(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
- S00_AXI_arid(0) => crc_axi_master_0_M_AXI_ARID(0),
- S00_AXI_arlen(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- S00_AXI_arprot(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
- S00_AXI_arready => crc_axi_master_0_M_AXI_ARREADY,
- S00_AXI_arsize(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- S00_AXI_arvalid => crc_axi_master_0_M_AXI_ARVALID,
- S00_AXI_awaddr(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- S00_AXI_awburst(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- S00_AXI_awcache(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
- S00_AXI_awid(0) => crc_axi_master_0_M_AXI_AWID(0),
- S00_AXI_awlen(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- S00_AXI_awprot(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
- S00_AXI_awready => crc_axi_master_0_M_AXI_AWREADY,
- S00_AXI_awsize(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- S00_AXI_awvalid => crc_axi_master_0_M_AXI_AWVALID,
- S00_AXI_bid(5 downto 0) => crc_axi_master_0_M_AXI_BID(5 downto 0),
- S00_AXI_bready => crc_axi_master_0_M_AXI_BREADY,
- S00_AXI_bresp(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- S00_AXI_bvalid => crc_axi_master_0_M_AXI_BVALID,
- S00_AXI_rdata(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- S00_AXI_rid(5 downto 0) => crc_axi_master_0_M_AXI_RID(5 downto 0),
- S00_AXI_rlast => crc_axi_master_0_M_AXI_RLAST,
- S00_AXI_rready => crc_axi_master_0_M_AXI_RREADY,
- S00_AXI_rresp(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- S00_AXI_rvalid => crc_axi_master_0_M_AXI_RVALID,
- S00_AXI_wdata(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- S00_AXI_wid(31 downto 0) => crc_axi_master_0_M_AXI_WID(31 downto 0),
- S00_AXI_wlast => crc_axi_master_0_M_AXI_WLAST,
- S00_AXI_wready => crc_axi_master_0_M_AXI_WREADY,
- S00_AXI_wstrb(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- S00_AXI_wvalid => crc_axi_master_0_M_AXI_WVALID
- );
-processing_system7_0: component crc_axi_master_syn_HP_Port_processing_system7_0_0
- port map (
- DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
- DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
- DDR_CAS_n => DDR_cas_n,
- DDR_CKE => DDR_cke,
- DDR_CS_n => DDR_cs_n,
- DDR_Clk => DDR_ck_p,
- DDR_Clk_n => DDR_ck_n,
- DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
- DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
- DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
- DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
- DDR_DRSTB => DDR_reset_n,
- DDR_ODT => DDR_odt,
- DDR_RAS_n => DDR_ras_n,
- DDR_VRN => FIXED_IO_ddr_vrn,
- DDR_VRP => FIXED_IO_ddr_vrp,
- DDR_WEB => DDR_we_n,
- FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
- FCLK_CLK1 => NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED,
- FCLK_CLK2 => NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED,
- FCLK_CLK3 => NLW_processing_system7_0_FCLK_CLK3_UNCONNECTED,
- FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
- IRQ_F2P(0) => '0',
- MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
- PS_CLK => FIXED_IO_ps_clk,
- PS_PORB => FIXED_IO_ps_porb,
- PS_SRSTB => FIXED_IO_ps_srstb,
- SDIO0_WP => xlconstant_0_dout(0),
- S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
- S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
- S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
- S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
- S_AXI_HP0_ARID(5 downto 1) => B"00000",
- S_AXI_HP0_ARID(0) => axi_mem_intercon_M00_AXI_ARID(0),
- S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
- S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
- S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
- S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
- S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
- S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
- S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
- S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
- S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
- S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
- S_AXI_HP0_AWID(5 downto 1) => B"00000",
- S_AXI_HP0_AWID(0) => axi_mem_intercon_M00_AXI_AWID(0),
- S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
- S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
- S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
- S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
- S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
- S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
- S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
- S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
- S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
- S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
- S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
- S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
- S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
- S_AXI_HP0_RDATA(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
- S_AXI_HP0_RDISSUECAP1_EN => '0',
- S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
- S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
- S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
- S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
- S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
- S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
- S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
- S_AXI_HP0_WDATA(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
- S_AXI_HP0_WID(5 downto 0) => axi_mem_intercon_M00_AXI_WID(5 downto 0),
- S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
- S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
- S_AXI_HP0_WRISSUECAP1_EN => '0',
- S_AXI_HP0_WSTRB(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
- S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
- TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
- TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
- TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
- USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
- USB0_VBUS_PWRFAULT => '0',
- USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
- );
-rst_ps7_0_100M: component crc_axi_master_syn_HP_Port_rst_ps7_0_100M_0
- port map (
- aux_reset_in => '1',
- bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0),
- dcm_locked => '1',
- ext_reset_in => processing_system7_0_FCLK_RESET0_N,
- interconnect_aresetn(0) => NLW_rst_ps7_0_100M_interconnect_aresetn_UNCONNECTED(0),
- mb_debug_sys_rst => '0',
- mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED,
- peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0),
- peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0),
- slowest_sync_clk => processing_system7_0_FCLK_CLK0
- );
-xlconstant_0: component crc_axi_master_syn_HP_Port_xlconstant_0_0
- port map (
- dout(0) => xlconstant_0_dout(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity crc_axi_master_syn_HP_Port is
- port (
- DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_cas_n : inout STD_LOGIC;
- DDR_ck_n : inout STD_LOGIC;
- DDR_ck_p : inout STD_LOGIC;
- DDR_cke : inout STD_LOGIC;
- DDR_cs_n : inout STD_LOGIC;
- DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_odt : inout STD_LOGIC;
- DDR_ras_n : inout STD_LOGIC;
- DDR_reset_n : inout STD_LOGIC;
- DDR_we_n : inout STD_LOGIC;
- FIXED_IO_ddr_vrn : inout STD_LOGIC;
- FIXED_IO_ddr_vrp : inout STD_LOGIC;
- FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- FIXED_IO_ps_clk : inout STD_LOGIC;
- FIXED_IO_ps_porb : inout STD_LOGIC;
- FIXED_IO_ps_srstb : inout STD_LOGIC
- );
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of crc_axi_master_syn_HP_Port : entity is "crc_axi_master_syn_HP_Port,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_syn_HP_Port,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=10,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=3,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=1,da_clkrst_cnt=2,synth_mode=OOC_per_IP}";
- attribute HW_HANDOFF : string;
- attribute HW_HANDOFF of crc_axi_master_syn_HP_Port : entity is "crc_axi_master_syn_HP_Port.hwdef";
-end crc_axi_master_syn_HP_Port;
-
-architecture STRUCTURE of crc_axi_master_syn_HP_Port is
- component crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0 is
- port (
- clk : in STD_LOGIC;
- resetn : in STD_LOGIC;
- finished : out STD_LOGIC;
- start : out STD_LOGIC;
- write : out STD_LOGIC;
- addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
- size : out STD_LOGIC_VECTOR ( 3 downto 0 );
- axi_idle : in STD_LOGIC
- );
- end component crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0;
- component crc_axi_master_syn_HP_Port_system_ila_0_0 is
- port (
- clk : in STD_LOGIC;
- probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
- probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
- probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
- probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe6 : in STD_LOGIC_VECTOR ( 31 downto 0 );
- probe7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
- probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
- probe10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- SLOT_0_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- SLOT_0_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_awvalid : in STD_LOGIC;
- SLOT_0_AXI_awready : in STD_LOGIC;
- SLOT_0_AXI_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_wlast : in STD_LOGIC;
- SLOT_0_AXI_wvalid : in STD_LOGIC;
- SLOT_0_AXI_wready : in STD_LOGIC;
- SLOT_0_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_bvalid : in STD_LOGIC;
- SLOT_0_AXI_bready : in STD_LOGIC;
- SLOT_0_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- SLOT_0_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- SLOT_0_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
- SLOT_0_AXI_arvalid : in STD_LOGIC;
- SLOT_0_AXI_arready : in STD_LOGIC;
- SLOT_0_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
- SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
- SLOT_0_AXI_rlast : in STD_LOGIC;
- SLOT_0_AXI_rvalid : in STD_LOGIC;
- SLOT_0_AXI_rready : in STD_LOGIC;
- resetn : in STD_LOGIC
- );
- end component crc_axi_master_syn_HP_Port_system_ila_0_0;
- component crc_axi_master_syn_HP_Port_crc_axi_ram_0_0 is
- port (
- waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
- wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- we : in STD_LOGIC;
- raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
- rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- re : in STD_LOGIC
- );
- end component crc_axi_master_syn_HP_Port_crc_axi_ram_0_0;
- component crc_axi_master_syn_HP_Port_crc_axi_master_0_0 is
- port (
- CLK : in STD_LOGIC;
- RESETN : in STD_LOGIC;
- start : in STD_LOGIC;
- write : in STD_LOGIC;
- addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
- size : in STD_LOGIC_VECTOR ( 3 downto 0 );
- ip_idle : out STD_LOGIC;
- waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
- wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- we : out STD_LOGIC;
- raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
- rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- re : out STD_LOGIC;
- M_AXI_ARREADY : in STD_LOGIC;
- M_AXI_ARVALID : out STD_LOGIC;
- M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_RREADY : out STD_LOGIC;
- M_AXI_RVALID : in STD_LOGIC;
- M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_RLAST : in STD_LOGIC;
- M_AXI_AWREADY : in STD_LOGIC;
- M_AXI_AWVALID : out STD_LOGIC;
- M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
- M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_WREADY : in STD_LOGIC;
- M_AXI_WVALID : out STD_LOGIC;
- M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_WLAST : out STD_LOGIC;
- M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_BREADY : out STD_LOGIC;
- M_AXI_BVALID : in STD_LOGIC;
- M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
- );
- end component crc_axi_master_syn_HP_Port_crc_axi_master_0_0;
- signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO : string;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARADDR : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARADDR";
- attribute DEBUG : string;
- attribute DEBUG of crc_axi_master_0_M_AXI_ARADDR : signal is "true";
- attribute MARK_DEBUG : boolean;
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARADDR : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARBURST : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARBURST";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARBURST : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARBURST : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARCACHE : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARCACHE";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARCACHE : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARCACHE : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARID";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARLEN : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARLEN";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARLEN : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARLEN : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARPROT : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARPROT";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARPROT : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARPROT : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARSIZE : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARSIZE";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARSIZE : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARSIZE : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_ARVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 ARVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_ARVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_ARVALID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWADDR : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWADDR";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWADDR : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWADDR : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWBURST : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWBURST";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWBURST : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWBURST : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWCACHE : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWCACHE";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWCACHE : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWCACHE : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWID";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWLEN : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWLEN";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWLEN : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWLEN : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWPROT : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWPROT";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWPROT : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWPROT : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWSIZE : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWSIZE";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWSIZE : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWSIZE : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_AWVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 AWVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_AWVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_AWVALID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_BID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 BID";
- attribute DEBUG of crc_axi_master_0_M_AXI_BID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_BID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_BREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 BREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_BREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_BREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_BRESP : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 BRESP";
- attribute DEBUG of crc_axi_master_0_M_AXI_BRESP : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_BRESP : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_BVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 BVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_BVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_BVALID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RDATA : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RDATA";
- attribute DEBUG of crc_axi_master_0_M_AXI_RDATA : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RDATA : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RID";
- attribute DEBUG of crc_axi_master_0_M_AXI_RID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RLAST : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RLAST";
- attribute DEBUG of crc_axi_master_0_M_AXI_RLAST : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RLAST : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_RREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RRESP : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RRESP";
- attribute DEBUG of crc_axi_master_0_M_AXI_RRESP : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RRESP : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_RVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 RVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_RVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_RVALID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WDATA : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WDATA";
- attribute DEBUG of crc_axi_master_0_M_AXI_WDATA : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WDATA : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WID";
- attribute DEBUG of crc_axi_master_0_M_AXI_WID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WID : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WLAST : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WLAST";
- attribute DEBUG of crc_axi_master_0_M_AXI_WLAST : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WLAST : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WREADY : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WREADY";
- attribute DEBUG of crc_axi_master_0_M_AXI_WREADY : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WREADY : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WSTRB : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WSTRB";
- attribute DEBUG of crc_axi_master_0_M_AXI_WSTRB : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WSTRB : signal is std.standard.true;
- signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
- attribute CONN_BUS_INFO of crc_axi_master_0_M_AXI_WVALID : signal is "crc_axi_master_0_M_AXI xilinx.com:interface:aximm:1.0 AXI3 WVALID";
- attribute DEBUG of crc_axi_master_0_M_AXI_WVALID : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_M_AXI_WVALID : signal is std.standard.true;
- signal crc_axi_master_0_ip_idle : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_ip_idle : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_ip_idle : signal is std.standard.true;
- signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_raddr : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_raddr : signal is std.standard.true;
- signal crc_axi_master_0_re : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_re : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_re : signal is std.standard.true;
- signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_0_waddr : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_waddr : signal is std.standard.true;
- signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_0_wdata : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_wdata : signal is std.standard.true;
- signal crc_axi_master_0_we : STD_LOGIC;
- attribute DEBUG of crc_axi_master_0_we : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_0_we : signal is std.standard.true;
- signal crc_axi_master_contr_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_master_contr_0_addr : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_contr_0_addr : signal is std.standard.true;
- signal crc_axi_master_contr_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute DEBUG of crc_axi_master_contr_0_size : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_contr_0_size : signal is std.standard.true;
- signal crc_axi_master_contr_0_start : STD_LOGIC;
- attribute DEBUG of crc_axi_master_contr_0_start : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_contr_0_start : signal is std.standard.true;
- signal crc_axi_master_contr_0_write : STD_LOGIC;
- attribute DEBUG of crc_axi_master_contr_0_write : signal is "true";
- attribute MARK_DEBUG of crc_axi_master_contr_0_write : signal is std.standard.true;
- signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- attribute DEBUG of crc_axi_ram_0_rdata : signal is "true";
- attribute MARK_DEBUG of crc_axi_ram_0_rdata : signal is std.standard.true;
- signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
- signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_CKE : STD_LOGIC;
- signal processing_system7_0_DDR_CK_N : STD_LOGIC;
- signal processing_system7_0_DDR_CK_P : STD_LOGIC;
- signal processing_system7_0_DDR_CS_N : STD_LOGIC;
- signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_ODT : STD_LOGIC;
- signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
- signal processing_system7_0_DDR_WE_N : STD_LOGIC;
- signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
- signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
- signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_crc_axi_master_contr_0_finished_UNCONNECTED : STD_LOGIC;
- attribute X_INTERFACE_INFO : string;
- attribute X_INTERFACE_INFO of DDR_cas_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
- attribute X_INTERFACE_INFO of DDR_ck_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
- attribute X_INTERFACE_INFO of DDR_ck_p : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
- attribute X_INTERFACE_INFO of DDR_cke : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
- attribute X_INTERFACE_INFO of DDR_cs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
- attribute X_INTERFACE_INFO of DDR_odt : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
- attribute X_INTERFACE_INFO of DDR_ras_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
- attribute X_INTERFACE_INFO of DDR_reset_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
- attribute X_INTERFACE_INFO of DDR_we_n : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrn : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
- attribute X_INTERFACE_PARAMETER : string;
- attribute X_INTERFACE_PARAMETER of FIXED_IO_ddr_vrn : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrp : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_clk : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_porb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_srstb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
- attribute X_INTERFACE_INFO of DDR_addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
- attribute X_INTERFACE_PARAMETER of DDR_addr : signal is "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250";
- attribute X_INTERFACE_INFO of DDR_ba : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
- attribute X_INTERFACE_INFO of DDR_dm : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
- attribute X_INTERFACE_INFO of DDR_dq : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
- attribute X_INTERFACE_INFO of DDR_dqs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
- attribute X_INTERFACE_INFO of DDR_dqs_p : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
- attribute X_INTERFACE_INFO of FIXED_IO_mio : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
-begin
-PS: entity work.PS_imp_1MAYGMX
- port map (
- DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
- DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
- DDR_cas_n => DDR_cas_n,
- DDR_ck_n => DDR_ck_n,
- DDR_ck_p => DDR_ck_p,
- DDR_cke => DDR_cke,
- DDR_cs_n => DDR_cs_n,
- DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
- DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
- DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
- DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
- DDR_odt => DDR_odt,
- DDR_ras_n => DDR_ras_n,
- DDR_reset_n => DDR_reset_n,
- DDR_we_n => DDR_we_n,
- FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
- FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
- FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
- FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
- FIXED_IO_ps_clk => FIXED_IO_ps_clk,
- FIXED_IO_ps_porb => FIXED_IO_ps_porb,
- FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
- S00_ARESETN(0) => rst_ps7_0_100M_peripheral_aresetn(0),
- S00_AXI_araddr(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- S00_AXI_arburst(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- S00_AXI_arcache(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
- S00_AXI_arid(0) => crc_axi_master_0_M_AXI_ARID(0),
- S00_AXI_arlen(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- S00_AXI_arprot(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
- S00_AXI_arready => crc_axi_master_0_M_AXI_ARREADY,
- S00_AXI_arsize(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- S00_AXI_arvalid => crc_axi_master_0_M_AXI_ARVALID,
- S00_AXI_awaddr(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- S00_AXI_awburst(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- S00_AXI_awcache(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
- S00_AXI_awid(0) => crc_axi_master_0_M_AXI_AWID(0),
- S00_AXI_awlen(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- S00_AXI_awprot(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
- S00_AXI_awready => crc_axi_master_0_M_AXI_AWREADY,
- S00_AXI_awsize(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- S00_AXI_awvalid => crc_axi_master_0_M_AXI_AWVALID,
- S00_AXI_bid(5 downto 0) => crc_axi_master_0_M_AXI_BID(5 downto 0),
- S00_AXI_bready => crc_axi_master_0_M_AXI_BREADY,
- S00_AXI_bresp(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- S00_AXI_bvalid => crc_axi_master_0_M_AXI_BVALID,
- S00_AXI_rdata(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- S00_AXI_rid(5 downto 0) => crc_axi_master_0_M_AXI_RID(5 downto 0),
- S00_AXI_rlast => crc_axi_master_0_M_AXI_RLAST,
- S00_AXI_rready => crc_axi_master_0_M_AXI_RREADY,
- S00_AXI_rresp(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- S00_AXI_rvalid => crc_axi_master_0_M_AXI_RVALID,
- S00_AXI_wdata(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- S00_AXI_wid(31 downto 0) => crc_axi_master_0_M_AXI_WID(31 downto 0),
- S00_AXI_wlast => crc_axi_master_0_M_AXI_WLAST,
- S00_AXI_wready => crc_axi_master_0_M_AXI_WREADY,
- S00_AXI_wstrb(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- S00_AXI_wvalid => crc_axi_master_0_M_AXI_WVALID
- );
-crc_axi_master_0: component crc_axi_master_syn_HP_Port_crc_axi_master_0_0
- port map (
- CLK => processing_system7_0_FCLK_CLK0,
- M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- M_AXI_ARCACHE(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
- M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
- M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- M_AXI_ARPROT(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
- M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
- M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
- M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- M_AXI_AWCACHE(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
- M_AXI_AWID(0) => crc_axi_master_0_M_AXI_AWID(0),
- M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- M_AXI_AWPROT(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
- M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
- M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
- M_AXI_BID(31 downto 6) => B"00000000000000000000000000",
- M_AXI_BID(5 downto 0) => crc_axi_master_0_M_AXI_BID(5 downto 0),
- M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
- M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
- M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
- M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
- M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
- M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
- M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- M_AXI_WID(31 downto 0) => crc_axi_master_0_M_AXI_WID(31 downto 0),
- M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
- M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
- M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
- RESETN => rst_ps7_0_100M_peripheral_aresetn(0),
- addr_axi(31 downto 0) => crc_axi_master_contr_0_addr(31 downto 0),
- ip_idle => crc_axi_master_0_ip_idle,
- raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- re => crc_axi_master_0_re,
- size(3 downto 0) => crc_axi_master_contr_0_size(3 downto 0),
- start => crc_axi_master_contr_0_start,
- waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- we => crc_axi_master_0_we,
- write => crc_axi_master_contr_0_write
- );
-crc_axi_master_contr_0: component crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0
- port map (
- addr(31 downto 0) => crc_axi_master_contr_0_addr(31 downto 0),
- axi_idle => crc_axi_master_0_ip_idle,
- clk => processing_system7_0_FCLK_CLK0,
- finished => NLW_crc_axi_master_contr_0_finished_UNCONNECTED,
- resetn => rst_ps7_0_100M_peripheral_aresetn(0),
- size(3 downto 0) => crc_axi_master_contr_0_size(3 downto 0),
- start => crc_axi_master_contr_0_start,
- write => crc_axi_master_contr_0_write
- );
-crc_axi_ram_0: component crc_axi_master_syn_HP_Port_crc_axi_ram_0_0
- port map (
- raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- re => crc_axi_master_0_re,
- waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- we => crc_axi_master_0_we
- );
-system_ila_0: component crc_axi_master_syn_HP_Port_system_ila_0_0
- port map (
- SLOT_0_AXI_araddr(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
- SLOT_0_AXI_arburst(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
- SLOT_0_AXI_arcache(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
- SLOT_0_AXI_arid(0) => crc_axi_master_0_M_AXI_ARID(0),
- SLOT_0_AXI_arlen(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
- SLOT_0_AXI_arlock(1 downto 0) => B"00",
- SLOT_0_AXI_arprot(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
- SLOT_0_AXI_arqos(3 downto 0) => B"0000",
- SLOT_0_AXI_arready => crc_axi_master_0_M_AXI_ARREADY,
- SLOT_0_AXI_arsize(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
- SLOT_0_AXI_arvalid => crc_axi_master_0_M_AXI_ARVALID,
- SLOT_0_AXI_awaddr(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
- SLOT_0_AXI_awburst(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
- SLOT_0_AXI_awcache(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
- SLOT_0_AXI_awid(0) => crc_axi_master_0_M_AXI_AWID(0),
- SLOT_0_AXI_awlen(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
- SLOT_0_AXI_awlock(1 downto 0) => B"00",
- SLOT_0_AXI_awprot(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
- SLOT_0_AXI_awqos(3 downto 0) => B"0000",
- SLOT_0_AXI_awready => crc_axi_master_0_M_AXI_AWREADY,
- SLOT_0_AXI_awsize(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
- SLOT_0_AXI_awvalid => crc_axi_master_0_M_AXI_AWVALID,
- SLOT_0_AXI_bid(0) => crc_axi_master_0_M_AXI_BID(0),
- SLOT_0_AXI_bready => crc_axi_master_0_M_AXI_BREADY,
- SLOT_0_AXI_bresp(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
- SLOT_0_AXI_bvalid => crc_axi_master_0_M_AXI_BVALID,
- SLOT_0_AXI_rdata(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
- SLOT_0_AXI_rid(0) => crc_axi_master_0_M_AXI_RID(0),
- SLOT_0_AXI_rlast => crc_axi_master_0_M_AXI_RLAST,
- SLOT_0_AXI_rready => crc_axi_master_0_M_AXI_RREADY,
- SLOT_0_AXI_rresp(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
- SLOT_0_AXI_rvalid => crc_axi_master_0_M_AXI_RVALID,
- SLOT_0_AXI_wdata(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
- SLOT_0_AXI_wid(0) => crc_axi_master_0_M_AXI_WID(0),
- SLOT_0_AXI_wlast => crc_axi_master_0_M_AXI_WLAST,
- SLOT_0_AXI_wready => crc_axi_master_0_M_AXI_WREADY,
- SLOT_0_AXI_wstrb(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
- SLOT_0_AXI_wvalid => crc_axi_master_0_M_AXI_WVALID,
- clk => processing_system7_0_FCLK_CLK0,
- probe0(0) => crc_axi_master_0_ip_idle,
- probe1(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
- probe10(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
- probe2(0) => crc_axi_master_0_re,
- probe3(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
- probe4(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
- probe5(0) => crc_axi_master_0_we,
- probe6(31 downto 0) => crc_axi_master_contr_0_addr(31 downto 0),
- probe7(3 downto 0) => crc_axi_master_contr_0_size(3 downto 0),
- probe8(0) => crc_axi_master_contr_0_start,
- probe9(0) => crc_axi_master_contr_0_write,
- resetn => rst_ps7_0_100M_peripheral_aresetn(0)
- );
-end STRUCTURE;
diff --git a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/mref/crc_axi_master/component.xml b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/mref/crc_axi_master/component.xml
index 1ba21a8..951788f 100644
--- a/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/mref/crc_axi_master/component.xml
+++ b/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/mref/crc_axi_master/component.xml
@@ -355,7 +355,7 @@
viewChecksum
- 8177cd08
+ 27642c7b
@@ -368,7 +368,7 @@
viewChecksum
- 8177cd08
+ 27642c7b
@@ -1231,7 +1231,7 @@
IPI
1
- 2025-01-31T00:46:10Z
+ 2025-01-31T15:09:11Z
2023.1
diff --git a/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bd b/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bd
index a881b8c..6dbb873 100644
--- a/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bd
+++ b/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bd
@@ -7,8 +7,7 @@
"name": "crc_axi_master_sim",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None",
- "tool_version": "2023.1",
- "validated": "true"
+ "tool_version": "2023.1"
},
"design_tree": {
"clk_rst_generator_0": "",
diff --git a/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xci b/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xci
index 4caa1da..325d0d2 100644
--- a/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xci
+++ b/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xci
@@ -81,10 +81,10 @@
"mode": "slave",
"memory_map_ref": "S_AXI",
"parameters": {
- "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
diff --git a/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ui/bd_384b0fb2.ui b/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ui/bd_384b0fb2.ui
index f44aeae..5a5dd66 100644
--- a/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ui/bd_384b0fb2.ui
+++ b/Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ui/bd_384b0fb2.ui
@@ -7,22 +7,22 @@
# -string -flagsOSRD
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 90 -y 160 -defaultsOSRD
preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 1070 -y 10 -defaultsOSRD
-preplace inst crc_axi_master_sim_c_0 -pg 1 -lvl 2 -x 400 -y 170 -defaultsOSRD
+preplace inst crc_axi_master_sim_c_0 -pg 1 -lvl 2 -x 400 -y 180 -defaultsOSRD
preplace inst crc_axi_ram_0 -pg 1 -lvl 2 -x 400 -y 420 -defaultsOSRD
preplace inst crc_axi_master_0 -pg 1 -lvl 3 -x 770 -y 0 -defaultsOSRD
-preplace netloc clk_rst_generator_0_clk 1 1 3 200 10 540 -120 960
-preplace netloc clk_rst_generator_0_rst_n 1 1 3 210 30 640 120 960
-preplace netloc crc_axi_master_0_idle 1 1 3 250 60 590J 130 930
-preplace netloc crc_axi_master_0_raddr 1 1 3 220 40 610J 140 910
-preplace netloc crc_axi_master_0_re 1 1 3 240 50 580J 150 900
-preplace netloc crc_axi_master_0_waddr 1 1 3 260 70 560J 160 940
-preplace netloc crc_axi_master_0_wdata 1 1 3 230 -130 NJ -130 900
-preplace netloc crc_axi_master_0_we 1 1 3 270 80 530J 170 920
+preplace netloc clk_rst_generator_0_clk 1 1 3 200 10 550 -120 960
+preplace netloc clk_rst_generator_0_rst_n 1 1 3 210 40 610 120 960
+preplace netloc crc_axi_master_0_idle 1 1 3 240 60 620J 130 930
+preplace netloc crc_axi_master_0_raddr 1 1 3 250 70 580J 140 910
+preplace netloc crc_axi_master_0_re 1 1 3 230 50 590J 150 900
+preplace netloc crc_axi_master_0_waddr 1 1 3 260 80 550J 160 940
+preplace netloc crc_axi_master_0_wdata 1 1 3 220 -130 NJ -130 900
+preplace netloc crc_axi_master_0_we 1 1 3 270 90 540J 170 920
preplace netloc crc_axi_master_sim_c_0_addr 1 2 1 600 20n
-preplace netloc crc_axi_master_sim_c_0_size 1 2 1 620 40n
+preplace netloc crc_axi_master_sim_c_0_size 1 2 1 630 40n
preplace netloc crc_axi_master_sim_c_0_start 1 2 1 570 -20n
-preplace netloc crc_axi_master_sim_c_0_write 1 2 1 550 0n
-preplace netloc crc_axi_ram_0_rdata 1 2 1 630 60n
+preplace netloc crc_axi_master_sim_c_0_write 1 2 1 530 0n
+preplace netloc crc_axi_ram_0_rdata 1 2 1 640 60n
preplace netloc crc_axi_master_0_M_AXI 1 3 1 950 -60n
levelinfo -pg 1 -20 90 400 770 1070 1170
pagesize -pg 1 -db -bbox -sgen -20 -150 1280 530
diff --git a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_auto_us_0/crc_axi_master_syn_auto_us_0.xci b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_auto_us_0/crc_axi_master_syn_auto_us_0.xci
index 846aa0c..4037f2a 100644
--- a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_auto_us_0/crc_axi_master_syn_auto_us_0.xci
+++ b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_auto_us_0/crc_axi_master_syn_auto_us_0.xci
@@ -145,26 +145,26 @@
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "slave",
"parameters": {
- "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "PROTOCOL": [ { "value": "AXI3", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "PROTOCOL": [ { "value": "AXI3", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ID_WIDTH": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ADDR_WIDTH": [ { "value": "32", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ID_WIDTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -222,7 +222,7 @@
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "master",
"parameters": {
- "DATA_WIDTH": [ { "value": "64", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "DATA_WIDTH": [ { "value": "64", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -315,7 +315,7 @@
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
- "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+ "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axi_aresetn" } ]
diff --git a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xci b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xci
index beff907..4ddc6a1 100644
--- a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xci
+++ b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xci
@@ -1131,22 +1131,22 @@
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ID_WIDTH": [ { "value": "3", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "AWUSER_WIDTH": [ { "value": "5", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ARUSER_WIDTH": [ { "value": "5", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "AWUSER_WIDTH": [ { "value": "5", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ARUSER_WIDTH": [ { "value": "5", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
diff --git a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port.bd b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port.bd
index 0ccfc0f..a56735e 100644
--- a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port.bd
+++ b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/crc_axi_master_syn_HP_Port.bd
@@ -7,8 +7,7 @@
"name": "crc_axi_master_syn_HP_Port",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
- "tool_version": "2023.1",
- "validated": "true"
+ "tool_version": "2023.1"
},
"design_tree": {
"crc_axi_master_contr_0": "",
@@ -1956,10 +1955,6 @@
"MAX_BURST_LENGTH": {
"value": "16",
"value_src": "auto"
- },
- "CLK_DOMAIN": {
- "value": "crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0",
- "value_src": "default_prop"
}
},
"address_space_ref": "M_AXI",
@@ -2164,10 +2159,6 @@
"ASSOCIATED_RESET": {
"value": "RESETN",
"value_src": "constant"
- },
- "CLK_DOMAIN": {
- "value": "crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0",
- "value_src": "default_prop"
}
}
},
diff --git a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.xci b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.xci
index 4b22e9c..ec995e0 100644
--- a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.xci
+++ b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.xci
@@ -126,7 +126,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
- "CLK_DOMAIN": [ { "value": "crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -192,7 +192,7 @@
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
- "CLK_DOMAIN": [ { "value": "crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
diff --git a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/ui/bd_495c8fc.ui b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/ui/bd_495c8fc.ui
index eeab22d..5a4936b 100644
--- a/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/ui/bd_495c8fc.ui
+++ b/Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn_HP_Port/ui/bd_495c8fc.ui
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.21552",
- "Default View_TopLeft":"5,0",
+ "Default View_TopLeft":"5,-2",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
diff --git a/Hardware/crc_axi_master/crc_axi_master.xpr b/Hardware/crc_axi_master/crc_axi_master.xpr
index 530c3b8..bf8798e 100644
--- a/Hardware/crc_axi_master/crc_axi_master.xpr
+++ b/Hardware/crc_axi_master/crc_axi_master.xpr
@@ -119,9 +119,6 @@
-
-
-
@@ -138,12 +135,12 @@
-
-
-
+
+
+
@@ -159,14 +156,14 @@
-
-
+
+
-
-
+
+
@@ -324,12 +321,6 @@
-
-
-
-
-
-
@@ -425,7 +416,7 @@
-
+
@@ -445,21 +436,7 @@
-
- Vivado Synthesis Defaults
-
-
-
-
-
-
-
-
-
-
-
- Vivado Synthesis Defaults
-
+
@@ -469,9 +446,7 @@
-
- Vivado Synthesis Defaults
-
+
@@ -596,58 +571,58 @@
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
@@ -656,50 +631,50 @@
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
@@ -733,28 +708,7 @@
-
- Default settings for Implementation.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- Default settings for Implementation.
-
+
@@ -771,9 +725,7 @@
-
- Default settings for Implementation.
-
+