es-abschlussprojekt/Hardware/axis_crc_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity axis_crc_tb is
end entity;

architecture testbench of axis_crc_tb is

    -- Signal Definitions
    signal CLK             : std_logic := '0';
    signal RESETN          : std_logic := '0';

    signal initialValue    : std_logic_vector(31 downto 0) := x"FFFFFFFF";
    signal polynomial      : std_logic_vector(31 downto 0) := x"F4ACFB13"; -- Standard CRC-32 Poly
    signal finalXOR        : std_logic_vector(31 downto 0) := x"00000000";
    signal inOutReflected  : std_logic_vector( 1 downto 0) := "00";

    -- AXIS Input Signals (Stimulus)
    signal S_AXIS_TVALID   : std_logic := '0';
    signal S_AXIS_TDATA    : std_logic_vector(31 downto 0) := (others => '0');
    signal S_AXIS_TLAST    : std_logic := '0';
    signal S_AXIS_TREADY   : std_logic;

    -- AXIS Output Signals (DUT Response)
    signal M_AXIS_TVALID   : std_logic;
    signal M_AXIS_TDATA    : std_logic_vector(31 downto 0);
    signal M_AXIS_TLAST    : std_logic;
    signal M_AXIS_TREADY   : std_logic := '1';

    -- Clock Process (100 MHz)
    constant CLK_PERIOD : time := 10 ns;
    signal done : boolean := false;

    type word_array is array (natural range<>) of std_logic_vector(31 downto 0);

    -- ASCII-Testdaten: "Hello World!"
    constant test_data : word_array := (
        x"6C6C6548", x"6F57206F", x"21646C72"
    );

    constant polynomials : word_array := (
        x"04C11DB7", x"814141AB", x"F4ACFB13"
    );

    constant initialValues : word_array := (
        x"00000000", x"FFFFFFFF"
    );

    constant finalXORS : word_array := (
        x"00000000", x"FFFFFFFF"
    );

    -- Kontroll-Pruefsummen. Berechnet mit crc.c
    constant crcs : word_array := (
        x"9d79d770", x"67fcdacc", x"6286288f", x"98032533",
        x"94e58351", x"e3d6e35c", x"6b1a7cae", x"1c291ca3",
        x"007c2675", x"c58ee9d1", x"ff83d98a", x"3a71162e",
        x"96b242cd", x"d8a89ab8", x"694dbd32", x"27576547",
        x"b1034672", x"ab94fcab", x"4efcb98d", x"546b0354",
        x"d5e8a88a", x"b4e32b8d", x"2a175775", x"4b1cd472"
    );

    -- type inOutReflected_t is array (natural range<>) of std_logic_vector(1 downto 0);
    -- constant inOutReflecteds : inOutReflected_t := ();

begin

    -- DUT Instantiation
    uut: entity work.axis_crc
    port map (
        CLK             => CLK,
        RESETN          => RESETN,
        initialValue    => initialValue,
        polynomial      => polynomial,
        finalXOR        => finalXOR,
        inOutReflected  => inOutReflected,

        -- AXI Streaming Target (Input)
        S_AXIS_TVALID   => S_AXIS_TVALID,
        S_AXIS_TDATA    => S_AXIS_TDATA,
        S_AXIS_TLAST    => S_AXIS_TLAST,
        S_AXIS_TREADY   => S_AXIS_TREADY,

        -- AXI Streaming Initiator (Output)
        M_AXIS_TVALID   => M_AXIS_TVALID,
        M_AXIS_TDATA    => M_AXIS_TDATA,
        M_AXIS_TLAST    => M_AXIS_TLAST,
        M_AXIS_TREADY   => M_AXIS_TREADY
    );

    -- Clock Process
    clk_process : process
    begin
        while not done loop
            CLK <= '0';
            wait for CLK_PERIOD / 2;
            CLK <= '1';
            wait for CLK_PERIOD / 2;
        end loop;
        wait;
    end process;

    -- Test Process
    stim : process
    begin
        -- Reset Sequence
        RESETN <= '0';
        wait for 50 ns;
        RESETN <= '1';
        wait for 50 ns;

        -- Send Data over S_AXIS
        for p in polynomials'range loop
            polynomial <= polynomials(p);

            for i in initialValues'range loop
                initialValue <= initialValues(i);

                for f in finalXORS'range loop
                    finalXOR <= finalXORS(f);

                    for r in 0 to 1 loop
                        if r = 1 then
                            inOutReflected <= "11";
                        else
                            inOutReflected <= "00";
                        end if;

                            for b in test_data'range loop
                                S_AXIS_TDATA  <= test_data(b);
                                S_AXIS_TVALID <= '1';

                                if b = test_data'length-1 then
                                    S_AXIS_TLAST <= '1';
                                else
                                    S_AXIS_TLAST <= '0';
                                end if;

                                wait until rising_edge(CLK) and S_AXIS_TREADY = '1';
                                S_AXIS_TVALID <= '0';
                            end loop;

                            wait until rising_edge(CLK) and M_AXIS_TVALID = '1' and M_AXIS_TLAST = '1';

                            S_AXIS_TLAST  <= '0';
                            wait until rising_edge(CLK);
                        end loop;
                end loop;
            end loop;
        end loop;
        wait;
    end process;

    process
    begin
        for c in crcs'range loop
            -- Wait for M_AXIS Data
            for i in test_data'range loop
                wait until rising_edge(CLK) and M_AXIS_TVALID = '1';
                assert M_AXIS_TDATA = test_data(i) report "ERROR: Mismatched Data at index " & integer'image(i) severity warning;
            end loop;

            -- Wait for CRC
            wait until rising_edge(CLK) and M_AXIS_TVALID = '1' and M_AXIS_TLAST = '1';
            assert M_AXIS_TDATA = crcs(c) report "ERROR: Wrong CRC" severity WARNING;
        end loop;

        report "ALL TEST FINISHED!";

        done <= true;
        wait;
    end process;

end architecture;