Matthias Biermann
149 lines
5.3 KiB
VHDL
149 lines
5.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axis_crc is
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port (
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CLK : in std_logic;
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RESETN : in std_logic;
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-- for crc calculation
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initial_value : in std_logic_vector(31 downto 0);
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polynomial : in std_logic_vector(31 downto 0);
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-- AXI Streaming Target Port
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S_AXIS_TVALID : in std_logic;
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S_AXIS_TDATA : in std_logic_vector(31 downto 0);
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S_AXIS_TLAST : in std_logic := '0';
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S_AXIS_TREADY : out std_logic;
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-- AXI Streaming Initiator Port
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M_AXIS_TVALID : out std_logic;
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M_AXIS_TDATA : out std_logic_vector(31 downto 0);
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M_AXIS_TLAST : out std_logic;
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M_AXIS_TREADY : in std_logic
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);
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end entity;
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architecture rtl of axis_crc is
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type state_t is (IDLE, SECOND_HALF, PROVIDE_DATA, CHECKSUM);
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signal state : state_t := IDLE;
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signal crc_sig : std_logic_vector(31 downto 0);
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begin
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process
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-- fuer CRC-Berechnung
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variable CRC : std_logic_vector(31 downto 0);
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variable MSB : std_logic;
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variable data : std_logic_vector(31 downto 0);
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variable last : std_logic;
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begin
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wait until rising_edge(CLK);
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if RESETN = '0' then
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state <= IDLE;
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S_AXIS_TREADY <= '1';
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M_AXIS_TVALID <= '0';
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M_AXIS_TLAST <= '0';
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crc_sig <= initial_value;
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else
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case state is
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when IDLE =>
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if S_AXIS_TVALID = '1' then
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data := S_AXIS_TDATA;
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last := S_AXIS_TLAST;
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CRC := crc_sig;
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-- Board speichert Daten mit LITTLE ENDIAN
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-- -> Die Daten aus dem Speicher sollen aufsteigend
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-- in die CRC-Summe reingerechnet werden
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-- Daher: Erst untere 16 Bit in die CRC Summe reinrechnen
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-- Erstes byte reinrechnen
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CRC := CRC xor (data(7 downto 0) & (23 downto 0 =>'0'));
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for i in 0 to 7 loop
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if CRC(31) = '1' then
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CRC := (CRC(30 downto 0) & '0') xor polynomial;
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else
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CRC := CRC(30 downto 0) & '0';
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end if;
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end loop;
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-- Zweites byte reinrechnen
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CRC := CRC xor (data(15 downto 8) & (23 downto 0 =>'0'));
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for i in 0 to 7 loop
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if CRC(31) = '1' then
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CRC := (CRC(30 downto 0) & '0') xor polynomial;
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else
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CRC := CRC(30 downto 0) & '0';
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end if;
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end loop;
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S_AXIS_TREADY <= '0';
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state <= SECOND_HALF;
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end if;
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when SECOND_HALF =>
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-- Dann obere 16 Bit in die CRC Summe reinrechnen
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-- Drittes byte reinrechnen
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CRC := CRC xor (data(23 downto 16) & (23 downto 0 =>'0'));
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for i in 0 to 7 loop
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if CRC(31) = '1' then
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CRC := (CRC(30 downto 0) & '0') xor polynomial;
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else
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CRC := CRC(30 downto 0) & '0';
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end if;
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end loop;
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-- Viertes byte reinrechnen
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CRC := CRC xor (data(31 downto 24) & (23 downto 0 =>'0'));
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for i in 0 to 7 loop
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if CRC(31) = '1' then
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CRC := (CRC(30 downto 0) & '0') xor polynomial;
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else
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CRC := CRC(30 downto 0) & '0';
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end if;
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end loop;
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crc_sig <= CRC;
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-- Daten an M_AXIS ausgeben
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M_AXIS_TVALID <= '1';
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M_AXIS_TDATA <= data;
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state <= PROVIDE_DATA;
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when PROVIDE_DATA =>
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if M_AXIS_TREADY = '1' then
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if last = '1' then
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M_AXIS_TLAST <= '1';
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M_AXIS_TDATA <= crc_sig;
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state <= CHECKSUM;
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else
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S_AXIS_TREADY <= '1';
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M_AXIS_TVALID <= '0';
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state <= IDLE;
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end if;
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end if;
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when CHECKSUM =>
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if M_AXIS_TREADY = '1' then
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S_AXIS_TREADY <= '1';
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M_AXIS_TVALID <= '0';
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M_AXIS_TLAST <= '0';
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crc_sig <= initial_value;
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state <= IDLE;
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end if;
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when others => null;
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end case;
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end if;
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end process;
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end architecture; |