Matthias Biermann
137 lines
5.3 KiB
VHDL
137 lines
5.3 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity axi3_slave_verif is
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generic (
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DWIDTH : positive := 32;
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IDWIDTH : positive := 1;
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MAX_BURSTLEN : positive := 16
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);
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port (
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CLK : in std_logic;
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RESETN : in std_logic;
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-- AXI Read Address Channel
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S_AXI_ARVALID : in std_logic;
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S_AXI_ARREADY : out std_logic := '0';
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S_AXI_ARADDR : in std_logic_vector(31 downto 0);
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S_AXI_ARID : in std_logic_vector(IDWIDTH-1 downto 0);
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S_AXI_ARLEN : in std_logic_vector( 3 downto 0);
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S_AXI_ARSIZE : in std_logic_vector( 2 downto 0);
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S_AXI_ARBURST : in std_logic_vector( 1 downto 0);
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-- AXI Read Data Channel
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S_AXI_RVALID : out std_logic := '0';
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S_AXI_RREADY : in std_logic;
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S_AXI_RDATA : out std_logic_vector(DWIDTH-1 downto 0);
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S_AXI_RRESP : out std_logic_vector( 1 downto 0);
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S_AXI_RID : out std_logic_vector(IDWIDTH-1 downto 0);
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S_AXI_RLAST : out std_logic := '0';
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-- AXI Write Address Channel
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S_AXI_AWVALID : in std_logic;
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S_AXI_AWREADY : out std_logic := '0';
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S_AXI_AWADDR : in std_logic_vector(31 downto 0);
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S_AXI_AWLEN : in std_logic_vector( 3 downto 0);
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S_AXI_AWSIZE : in std_logic_vector( 2 downto 0);
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S_AXI_AWBURST : in std_logic_vector( 1 downto 0);
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-- AXI Write Data Channel
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S_AXI_WVALID : in std_logic;
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S_AXI_WREADY : out std_logic := '0';
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S_AXI_WDATA : in std_logic_vector(DWIDTH-1 downto 0);
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S_AXI_WSTRB : in std_logic_vector(DWIDTH/8-1 downto 0);
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S_AXI_WLAST : in std_logic;
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-- AXI Write Response Channel
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S_AXI_BVALID : out std_logic := '0';
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S_AXI_BREADY : in std_logic;
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S_AXI_BRESP : out std_logic_vector( 1 downto 0)
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);
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end axi3_slave_verif;
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architecture Behavioral of axi3_slave_verif is
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type state_type is (IDLE, READ_RESP, WRITE_WAIT, WRITE_RESP_1, WRITE_RESP_2);
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signal state : state_type := IDLE;
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signal read_addr : std_logic_vector(31 downto 0);
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signal write_addr : std_logic_vector(31 downto 0);
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begin
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process(CLK)
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variable burst_count : integer range 0 to MAX_BURSTLEN := 0;
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begin
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if rising_edge(CLK) then
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if RESETN = '0' then
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-- Reset aller Signale
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state <= IDLE;
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S_AXI_ARREADY <= '0';
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S_AXI_RVALID <= '0';
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S_AXI_AWREADY <= '0';
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S_AXI_WREADY <= '0';
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S_AXI_BVALID <= '0';
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else
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case state is
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-- IDLE: Warten auf Read oder Write Request
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when IDLE =>
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S_AXI_ARREADY <= '1';
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S_AXI_AWREADY <= '1';
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burst_count := to_integer(unsigned(S_AXI_ARLEN)) + 1;
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if S_AXI_ARVALID = '1' then
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read_addr <= S_AXI_ARADDR;
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state <= READ_RESP;
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S_AXI_ARREADY <= '0';
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elsif S_AXI_AWVALID = '1' then
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write_addr <= S_AXI_AWADDR;
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state <= WRITE_WAIT;
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S_AXI_AWREADY <= '0';
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end if;
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-- READ RESPONSE Phase
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when READ_RESP =>
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S_AXI_RVALID <= '1';
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S_AXI_RDATA <= std_logic_vector(to_unsigned(burst_count, DWIDTH)); -- Dummy Daten
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S_AXI_RRESP <= "00"; -- OKAY response
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if S_AXI_RREADY = '1' then
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if burst_count > 0 then
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if burst_count = 1 then
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S_AXI_RLAST <= '1';
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end if;
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burst_count := burst_count - 1;
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else
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S_AXI_RVALID <= '0';
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S_AXI_RLAST <= '0';
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state <= IDLE;
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end if;
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end if;
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-- WRITE WAIT Phase: Daten empfangen
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when WRITE_WAIT =>
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S_AXI_WREADY <= '1';
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if S_AXI_WVALID = '1' then
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if S_AXI_WLAST = '1' then
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S_AXI_WREADY <= '0';
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state <= WRITE_RESP_1;
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end if;
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end if;
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-- WRITE RESPONSE Phase
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when WRITE_RESP_1 =>
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S_AXI_BVALID <= '1';
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S_AXI_BRESP <= "00"; -- OKAY response
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state <= WRITE_RESP_2;
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when WRITE_RESP_2 =>
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if S_AXI_BREADY = '1' then
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S_AXI_BVALID <= '0';
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state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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