Matthias Biermann
106 lines
4.4 KiB
VHDL
106 lines
4.4 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity axi_crc is
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generic (
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DATA_WIDTH : integer := 32; -- Datenwortbreite
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ID_WIDTH : integer := 4 -- AXI ID Wortbreite
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);
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port (
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CLK : in std_logic;
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RESETN : in std_logic;
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INTERRUPT : out std_logic;
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-- AXI Master Interface (Memory)
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M_AXI_ARREADY : in std_logic := '1';
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M_AXI_ARVALID : out std_logic;
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M_AXI_ARADDR : out std_logic_vector(31 downto 0);
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M_AXI_ARID : out std_logic_vector(ID_WIDTH-1 downto 0);
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M_AXI_ARLEN : out std_logic_vector( 3 downto 0);
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M_AXI_ARSIZE : out std_logic_vector( 2 downto 0);
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M_AXI_ARBURST : out std_logic_vector( 1 downto 0);
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M_AXI_ARPROT : out std_logic_vector( 2 downto 0);
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M_AXI_ARCACHE : out std_logic_vector( 3 downto 0);
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M_AXI_RREADY : out std_logic;
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M_AXI_RVALID : in std_logic;
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M_AXI_RDATA : in std_logic_vector(DATA_WIDTH-1 downto 0);
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M_AXI_RRESP : in std_logic_vector( 1 downto 0);
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M_AXI_RID : in std_logic_vector(ID_WIDTH-1 downto 0);
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M_AXI_RLAST : in std_logic;
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M_AXI_AWREADY : in std_logic := '0';
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M_AXI_AWVALID : out std_logic;
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M_AXI_AWADDR : out std_logic_vector(31 downto 0);
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M_AXI_AWLEN : out std_logic_vector( 3 downto 0);
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M_AXI_AWSIZE : out std_logic_vector( 2 downto 0);
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M_AXI_AWID : out std_logic_vector(ID_WIDTH-1 downto 0);
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M_AXI_AWBURST : out std_logic_vector( 1 downto 0);
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M_AXI_AWPROT : out std_logic_vector( 2 downto 0);
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M_AXI_AWCACHE : out std_logic_vector( 3 downto 0);
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M_AXI_WREADY : in std_logic := '0';
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M_AXI_WVALID : out std_logic;
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M_AXI_WDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
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M_AXI_WSTRB : out std_logic_vector(DATA_WIDTH/8-1 downto 0);
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M_AXI_WLAST : out std_logic;
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M_AXI_WID : out std_logic_vector(ID_WIDTH-1 downto 0);
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M_AXI_BREADY : out std_logic;
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M_AXI_BVALID : in std_logic := '0';
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M_AXI_BID : in std_logic_vector( ID_WIDTH-1 downto 0);
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M_AXI_BRESP : in std_logic_vector( 1 downto 0);
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-- AXI-Lite Slave Interface
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S_AXIL_AWADDR : in std_logic_vector(7 downto 0);
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S_AXIL_AWVALID : in std_logic;
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S_AXIL_AWREADY : out std_logic;
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S_AXIL_WDATA : in std_logic_vector(31 downto 0);
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S_AXIL_WVALID : in std_logic;
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S_AXIL_WREADY : out std_logic;
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S_AXIL_WSTRB : in std_logic_vector((32/8)-1 downto 0);
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S_AXIL_BVALID : out std_logic;
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S_AXIL_BREADY : in std_logic;
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S_AXIL_BRESP : out std_logic_vector(1 downto 0);
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S_AXIL_ARADDR : in std_logic_vector(7 downto 0);
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S_AXIL_ARVALID : in std_logic;
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S_AXIL_ARREADY : out std_logic;
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S_AXIL_RDATA : out std_logic_vector(31 downto 0);
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S_AXIL_RVALID : out std_logic;
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S_AXIL_RREADY : in std_logic;
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S_AXIL_RRESP : out std_logic_vector(1 downto 0)
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);
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end axi_crc;
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architecture rtl of axi_crc is
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-- AXIL Registers
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-- signal
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begin
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----------------------------------------------------------------------------
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-- AXIL Interface
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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-- AXI Master Interface to Memory
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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-- CRC Calculation component
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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-- Main control state machine
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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-- Block RAM Memory
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----------------------------------------------------------------------------
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end Behavioral;
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