Matthias Biermann
64 lines
1.8 KiB
VHDL
64 lines
1.8 KiB
VHDL
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.NUMERIC_STD.ALL;
|
|
|
|
entity crc is
|
|
generic (
|
|
crcLength : positive;
|
|
inDataLength : positive
|
|
);
|
|
port (
|
|
clk : in std_logic;
|
|
-- Kontrollsignale
|
|
reset : in std_logic;
|
|
enable : in std_logic;
|
|
initialValue : in std_logic_vector(crcLength-1 downto 0);
|
|
polynomial : in std_logic_vector(crcLength-1 downto 0);
|
|
-- Datensignale
|
|
inData : in std_logic_vector(inDataLength-1 downto 0);
|
|
checksum : out std_logic_vector(crcLength-1 downto 0)
|
|
);
|
|
end crc;
|
|
|
|
architecture Behavioral of crc is
|
|
|
|
-- Interne Signale fuer CRC Pruefsumme
|
|
signal checksum_i : std_logic_vector(crcLength-1 downto 0);
|
|
signal nextChecksum : std_logic_vector(crcLength-1 downto 0);
|
|
|
|
begin
|
|
-- Kombinatorik fuer CRC-Berechnung
|
|
ProcNextCRC: process (inData, checksum_i)
|
|
variable mix: std_logic_vector(crcLength-1 downto 0);
|
|
variable MSB : std_logic;
|
|
begin
|
|
mix := checksum_i;
|
|
for i in inData'range loop
|
|
-- Pruefen ob MSB gesetzt ist
|
|
MSB := mix(mix'length-1);
|
|
-- neues Bit reinschieben
|
|
mix := mix(mix'length-2 downto 0) & inData(i);
|
|
-- XOR Verknuepfung
|
|
if MSB = '1' then
|
|
mix := mix XOR polynomial;
|
|
end if;
|
|
end loop;
|
|
nextChecksum <= mix;
|
|
end process;
|
|
|
|
-- Register zum Speichern der CRC-Pruefsumme
|
|
Reg: process (clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if reset = '1' then
|
|
checksum_i <= initialValue;
|
|
elsif enable = '1' then
|
|
checksum_i <= nextChecksum;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
checksum <= checksum_i;
|
|
|
|
end Behavioral;
|