Matthias Biermann
83 lines
2.9 KiB
VHDL
83 lines
2.9 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity crc_axi_control is
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generic (
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LUTRAM_AWIDTH : positive := 4;
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PACKET_SIZE_WIDTH : positive := 16;
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PACKET_NUM_WIDTH : positive := 16;
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MAX_BURSTLEN : positive := 16;
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);
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port (
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CLK : in std_logic;
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RESETN : in std_logic;
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-- AXIL Registers
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start_ip : in std_logic;
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stop_ip : in std_logic;
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status : out std_logic;
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interrupt_enable : in std_logic;
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interrupt_status : out std_logic;
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interrupt_reset : in std_logic;
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raddr : in std_logic_vector(31 downto 0);
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waddr : in std_logic_vector(31 downto 0);
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packet_size : in std_logic_vector(PACKET_SIZE_WIDTH-1 downto 0);
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packet_number : in std_logic_vector(PACKET_NUM_WIDTH-1 downto 0);
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-- Interface to Block-RAM
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ram_sel : out std_logic;
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ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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ram_we : out std_logic;
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ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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ram_re : out std_logic;
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-- Interface to AXI Master component
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axi_start : out std_logic;
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axi_write : out std_logic;
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axi_addr : out std_logic_vector(31 downto 0);
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axi_size : out std_logic_vector(3 downto 0);
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axi_idle : in std_logic;
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-- Control signals for CRC component
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crc_en : out std_logic;
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cec_rst : out std_logic;
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byte_sel : out std_logic_vector(1 downto 0);
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);
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end entity;
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architecture rtl of crc_axi_control is
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type state_t is (IDLE, READ_DATA);
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signal state : state_t := IDLE;
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signal packets_cnt : unsigned(PACKET_NUM_WIDTH-1 downto 0) := (others=>'0');
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signal data_cnt : unsigned(PACKET_SIZE_WIDTH+PACKET_NUM_WIDTH-1 downto 0) := (others=>'0');
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signal read_addr : unsigned(31 downto 0) := (others=>'0');
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signal write_addr : unsigned(31 downto 0) := (others=>'0');
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begin
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process
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begin
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wait until rising_edge(CLK);
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if RESETN = '0' then
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state <= IDLE;
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else
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case state is
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when IDLE =>
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if start_ip = '1' then
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packets_cnt <= unsigned(packet_number);
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data_cnt <= unsigned(packet_size);
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read_addr <= unsigned(raddr);
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write_addr <= unsigned(waddr);
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end if;
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when others =>
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null;
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end case;
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end if;
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end process;
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end architecture; |