es-abschlussprojekt/Archiv/Hardware/crc_axi_lite.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity crc_axi_lite is
    generic (
        polynomial_default    : std_logic_vector(31 downto 0) := x"04C11DB7";
        initial_value_default : std_logic_vector(31 downto 0) := x"00000000"
    );
    port (
        AXI_ACLK                       : in  std_logic;
        AXI_ARESETN                    : in  std_logic;

        -- AXIL Slave Interface
        S_AXIL_AWADDR                  : in  std_logic_vector(7 downto 0);
        S_AXIL_AWVALID                 : in  std_logic;
        S_AXIL_AWREADY                 : out std_logic;
        S_AXIL_WDATA                   : in  std_logic_vector(31 downto 0);
        S_AXIL_WVALID                  : in  std_logic;
        S_AXIL_WREADY                  : out std_logic;
        S_AXIL_WSTRB                   : in  std_logic_vector((32/8)-1 downto 0);
        S_AXIL_BVALID                  : out std_logic;
        S_AXIL_BREADY                  : in  std_logic;
        S_AXIL_BRESP                   : out std_logic_vector(1 downto 0);
        S_AXIL_ARADDR                  : in  std_logic_vector(7 downto 0);
        S_AXIL_ARVALID                 : in  std_logic;
        S_AXIL_ARREADY                 : out std_logic;
        S_AXIL_RDATA                   : out std_logic_vector(31 downto 0);
        S_AXIL_RVALID                  : out std_logic;
        S_AXIL_RREADY                  : in  std_logic;
        S_AXIL_RRESP                   : out std_logic_vector(1 downto 0);

        -- Eingaenge
        status                         : in  std_logic;
        interrupt_status               : in  std_logic;

        -- Ausgaenge
        start_ip                       : out std_logic;
        stop_ip                        : out std_logic;
        interrupt_reset                : out std_logic;
        interrupt_enable               : out std_logic;
        raddr                          : out std_logic_vector(31 downto 0);
        waddr                          : out std_logic_vector(31 downto 0);
        packet_size                    : out std_logic_vector(15 downto 0);
        packet_number                  : out std_logic_vector(15 downto 0);
        polynomial                     : out std_logic_vector(31 downto 0);
        initial_value                  : out std_logic_vector(31 downto 0)
    );
end;

architecture rtl of crc_axi_lite is

    -- AXIL Register
    signal interrupt_enable_reg : std_logic;
    signal read_address_reg     : std_logic_vector(31 downto 0);
    signal write_address_reg    : std_logic_vector(31 downto 0);
    signal packet_size_reg      : std_logic_vector(15 downto 0);
    signal packet_number_reg    : std_logic_vector(15 downto 0);
    signal polynomial_reg       : std_logic_vector(31 downto 0);
    signal initial_value_reg    : std_logic_vector(31 downto 0);

begin
    -- AXI-Lite Register nach aussen fuehren
    interrupt_enable <= interrupt_enable_reg;
    raddr            <= read_address_reg;
    waddr            <= write_address_reg;
    packet_size      <= packet_size_reg;
    packet_number    <= packet_number_reg;
    polynomial       <= polynomial_reg;
    initial_value    <= initial_value_reg;


    -- Fuer AXI-Lite Schnittstelle
    S_AXIL_BRESP   <= (others=>'0');    -- No write errors
    S_AXIL_RRESP   <= (others=>'0');    -- No read errors
    S_AXIL_ARREADY <= '1';              -- IP is always ready
    S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
    S_AXIL_WREADY  <= S_AXIL_AWVALID and S_AXIL_WVALID;

    process
    begin
        wait until rising_edge(AXI_ACLK);

        -- AXI-Lite Schnittstelle
        if AXI_ARESETN = '0' then
            S_AXIL_BVALID  <= '0';
            S_AXIL_RVALID  <= '0';

            -- AXIL-Register zuruecksetzen
            interrupt_enable_reg  <= '0';
            read_address_reg      <= (others => '0');
            write_address_reg     <= (others => '0');
            packet_number_reg     <= (others => '0');
            packet_number_reg     <= (others => '0');
            polynomial_reg        <= polynomial_default;
            initial_value_reg     <= initial_value_default;
        else
            -- Lesezugriff
            if S_AXIL_RREADY = '1' then
                S_AXIL_RVALID <= '0';
            end if;

            if S_AXIL_ARVALID = '1' then
                S_AXIL_RDATA   <= (others=>'0');
                if    S_AXIL_ARADDR(7 downto 0) = x"00" then
                    S_AXIL_RDATA(0) <= status;
                    S_AXIL_RDATA(1) <= interrupt_enable_reg;
                elsif S_AXIL_ARADDR(7 downto 0) = x"04" then
                    S_AXIL_RDATA(0) <= interrupt_status;
                elsif S_AXIL_ARADDR(7 downto 0) = x"08" then
                    S_AXIL_RDATA <= read_address_reg;
                elsif S_AXIL_ARADDR(7 downto 0) = x"0C" then
                    S_AXIL_RDATA <= write_address_reg;
                elsif S_AXIL_ARADDR(7 downto 0) = x"10" then
                    S_AXIL_RDATA(15 downto 0) <= packet_size_reg;
                elsif S_AXIL_ARADDR(7 downto 0) = x"14" then
                    S_AXIL_RDATA(15 downto 0) <= packet_number_reg;
                elsif S_AXIL_ARADDR(7 downto 0) = x"18" then
                    S_AXIL_RDATA <= polynomial_reg;
                elsif S_AXIL_ARADDR(7 downto 0) = x"1C" then
                    S_AXIL_RDATA <= initial_value_reg;
                end if;
                S_AXIL_RVALID  <= '1';
            end if;

            -- Schreibzugriff
            interrupt_reset <= '0';
            start_ip <= '0';
            stop_ip <= '0';

            if S_AXIL_BREADY = '1' then
                S_AXIL_BVALID  <= '0';
            end if;

            if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
                S_AXIL_BVALID <= '1';

                -- Register schreiben
                if S_AXIL_AWADDR = x"00" then
                    if S_AXIL_WSTRB(0) = '1' then
                        if S_AXIL_WDATA(0) = '1' then
                            start_ip <= '1';
                        elsif S_AXIL_WDATA(0) = '0' then
                            stop_ip <= '1';
                        end if;
                        interrupt_enable_reg <= S_AXIL_WDATA(1);
                    end if;
                elsif S_AXIL_AWADDR = x"04" then
                    if S_AXIL_WSTRB(0) = '1' then
                        if S_AXIL_WDATA(0) = '0' then
                            interrupt_reset <= '1';
                        end if;
                    end if;
                elsif S_AXIL_AWADDR = x"08" then
                    if S_AXIL_WSTRB = "1111" then
                        read_address_reg <= S_AXIL_WDATA;
                    end if;
                elsif S_AXIL_AWADDR = x"0C" then
                    if S_AXIL_WSTRB = "1111" then
                        write_address_reg <= S_AXIL_WDATA;
                    end if;
                elsif S_AXIL_AWADDR = x"10" then
                    if S_AXIL_WSTRB(1 downto 0) = "11" then
                        packet_size_reg <= S_AXIL_WDATA(15 downto 0);
                    end if;
                elsif S_AXIL_AWADDR = x"14" then
                    if S_AXIL_WSTRB(1 downto 0) = "11" then
                        packet_number_reg <= S_AXIL_WDATA(15 downto 0);
                    end if;
                elsif S_AXIL_AWADDR = x"18" then
                    if S_AXIL_WSTRB = "1111" then
                        polynomial_reg <= S_AXIL_WDATA;
                    end if;
                elsif S_AXIL_AWADDR = x"1C" then
                    if S_AXIL_WSTRB = "1111" then
                        initial_value_reg <= S_AXIL_WDATA;
                    end if;
                end if;
            end if;
        end if;
    end process;
end architecture;