Matthias Biermann
209 lines
7.8 KiB
VHDL
209 lines
7.8 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity crc_axi_master is
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generic (
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DWIDTH : positive := 32;
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IDWIDTH : positive := 1;
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MAX_BURSTLEN : positive := 16;
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LUTRAM_AWIDTH : positive := 4
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);
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port (
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CLK : in std_logic;
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RESETN : in std_logic;
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-- Control signals
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start : in std_logic;
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write : in std_logic;
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addr_axi : in std_logic_vector(DWIDTH-1 downto 0);
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size : in std_logic_vector(3 downto 0);
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ip_idle : out std_logic;
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-- Interface to LUTRAM
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waddr : out std_logic_vector(LUTRAM_AWIDTH-1 downto 0);
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wdata : out std_logic_vector(DWIDTH-1 downto 0);
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we : out std_logic;
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raddr : out std_logic_vector(LUTRAM_AWIDTH-1 downto 0);
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rdata : in std_logic_vector(DWIDTH-1 downto 0);
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re : out std_logic;
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-- AXI Master Interface (Memory)
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M_AXI_ARREADY : in std_logic;
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M_AXI_ARVALID : out std_logic := '0';
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M_AXI_ARADDR : out std_logic_vector(31 downto 0);
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M_AXI_ARID : out std_logic_vector(IDWIDTH-1 downto 0);
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M_AXI_ARLEN : out std_logic_vector( 3 downto 0);
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M_AXI_ARSIZE : out std_logic_vector( 2 downto 0);
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M_AXI_ARBURST : out std_logic_vector( 1 downto 0);
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M_AXI_ARPROT : out std_logic_vector( 2 downto 0);
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M_AXI_ARCACHE : out std_logic_vector( 3 downto 0);
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M_AXI_RREADY : out std_logic;
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M_AXI_RVALID : in std_logic;
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M_AXI_RDATA : in std_logic_vector(DWIDTH-1 downto 0);
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M_AXI_RRESP : in std_logic_vector( 1 downto 0);
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M_AXI_RID : in std_logic_vector(IDWIDTH-1 downto 0);
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M_AXI_RLAST : in std_logic;
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M_AXI_AWREADY : in std_logic := '0';
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M_AXI_AWVALID : out std_logic := '0';
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M_AXI_AWADDR : out std_logic_vector(31 downto 0);
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M_AXI_AWLEN : out std_logic_vector( 3 downto 0);
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M_AXI_AWSIZE : out std_logic_vector( 2 downto 0);
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M_AXI_AWID : out std_logic_vector(IDWIDTH-1 downto 0);
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M_AXI_AWBURST : out std_logic_vector( 1 downto 0);
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M_AXI_AWPROT : out std_logic_vector( 2 downto 0);
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M_AXI_AWCACHE : out std_logic_vector( 3 downto 0);
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M_AXI_WREADY : in std_logic := '0';
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M_AXI_WVALID : out std_logic := '0';
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M_AXI_WDATA : out std_logic_vector(DWIDTH-1 downto 0);
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M_AXI_WSTRB : out std_logic_vector(DWIDTH/8-1 downto 0);
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M_AXI_WLAST : out std_logic;
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M_AXI_WID : out std_logic_vector(DWIDTH-1 downto 0);
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M_AXI_BREADY : out std_logic;
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M_AXI_BVALID : in std_logic := '0';
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M_AXI_BID : in std_logic_vector( DWIDTH-1 downto 0);
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M_AXI_BRESP : in std_logic_vector( 1 downto 0)
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);
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end entity;
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architecture rtl of crc_axi_master is
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type state_t is (IDLE, R_REQ, R_WAIT_REQ_ACCEPT, READ_DATA, W_REQ, W_WAIT_REQ_ACCEPT, GET_FIRST_WORD, WRITE_DATA);
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signal state : state_t := IDLE;
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signal addr_LUTRAM : unsigned(LUTRAM_AWIDTH-1 downto 0) := (others=>'0');
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signal addr_mem : unsigned(31 downto 0) := (others=>'0');
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begin
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--------------------------------
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-- AXI Read/Write Request Engine
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--------------------------------
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-- static outputs
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M_AXI_ARSIZE <= "010" when DWIDTH=32 else "011"; -- Data width 32/64
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M_AXI_ARBURST <= "01";
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M_AXI_ARPROT <= "000";
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M_AXI_ARCACHE <= "0000";
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M_AXI_ARID <= (others=>'0');
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M_AXI_RREADY <= '1';
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M_AXI_AWSIZE <= "010" when DWIDTH=32 else "011"; -- Data width 32/64
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M_AXI_AWBURST <= "01";
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M_AXI_AWPROT <= "000";
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M_AXI_AWCACHE <= "0000";
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M_AXI_BREADY <= '1';
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M_AXI_WSTRB <= (others=>'1');
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M_AXI_AWID <= (others=>'0');
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M_AXI_WID <= (others=>'0');
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-- Interface to LUT Ram
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M_AXI_WDATA <= rdata;
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raddr <= std_logic_vector(addr_LUTRAM);
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re <= '1' when (state = WRITE_DATA) else '0';
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waddr <= std_logic_vector(addr_LUTRAM);
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wdata <= M_AXI_RDATA;
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we <= M_AXI_RVALID;
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process
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variable data_cnt : integer range 0 to MAX_BURSTLEN := 0;
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begin
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wait until rising_edge(CLK);
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if RESETN = '0' then
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M_AXI_ARVALID <= '0';
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M_AXI_ARADDR <= (others=>'0');
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M_AXI_ARLEN <= (others=>'0');
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M_AXI_WVALID <= '0';
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M_AXI_AWVALID <= '0';
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M_AXI_AWADDR <= (others=>'0');
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M_AXI_AWLEN <= (others=>'0');
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M_AXI_WLAST <= '0';
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state <= IDLE;
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else
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case state is
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when IDLE =>
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if start = '1' then
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addr_LUTRAM <= (others=>'0');
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addr_mem <= unsigned(addr_axi);
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data_cnt := to_integer(unsigned(size))+1;
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ip_idle <= '0';
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if write = '0' then
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state <= R_REQ;
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else
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state <= W_REQ;
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end if;
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end if;
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when R_REQ =>
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M_AXI_ARADDR <= std_logic_vector(addr_mem);
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M_AXI_ARLEN <= size;
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M_AXI_ARVALID <= '1';
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state <= R_WAIT_REQ_ACCEPT;
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when R_WAIT_REQ_ACCEPT =>
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if M_AXI_ARREADY = '1' then
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M_AXI_ARVALID <= '0';
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state <= READ_DATA;
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end if;
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when READ_DATA =>
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if M_AXI_RVALID = '1' then
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addr_LUTRAM <= addr_LUTRAM + 1;
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if M_AXI_RLAST = '1' then
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ip_idle <= '1';
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state <= IDLE;
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end if;
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end if;
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when W_REQ =>
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M_AXI_AWVALID <= '1';
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M_AXI_AWADDR <= std_logic_vector(addr_mem);
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M_AXI_AWLEN <= size;
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state <= W_WAIT_REQ_ACCEPT;
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when W_WAIT_REQ_ACCEPT =>
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if M_AXI_AWREADY = '1' then
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M_AXI_AWVALID <= '0';
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if data_cnt = 1 then
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M_AXI_WLAST <= '1';
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end if;
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M_AXI_WVALID <= '1';
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-- re <= '1';
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state <= WRITE_DATA;
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end if;
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when WRITE_DATA =>
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if M_AXI_WREADY = '1' then
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-- get next word from Block RAM
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data_cnt := data_cnt - 1;
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addr_LUTRAM <= addr_LUTRAM + 1;
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if data_cnt = 1 then
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M_AXI_WLAST <= '1';
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end if;
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if data_cnt = 0 then
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M_AXI_WLAST <= '0';
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M_AXI_WVALID <= '0';
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-- re <= '0';
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ip_idle <= '1';
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state <= IDLE;
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end if;
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end if;
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when others => null;
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end case;
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end if;
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end process;
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end architecture; |