Matthias Biermann
64 lines
1.8 KiB
VHDL
64 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity crc is
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generic (
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CRC_WIDTH : positive;
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DWIDTH : positive
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);
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port (
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clk : in std_logic;
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-- Kontrollsignale
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reset : in std_logic;
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enable : in std_logic;
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initial_value : in std_logic_vector(CRC_WIDTH-1 downto 0);
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polynomial : in std_logic_vector(CRC_WIDTH-1 downto 0);
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-- Datensignale
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data : in std_logic_vector(DWIDTH-1 downto 0);
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checksum : out std_logic_vector(CRC_WIDTH-1 downto 0)
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);
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end crc;
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architecture rtl of crc is
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-- Interne Signale fuer CRC Pruefsumme
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signal checksum_i : std_logic_vector(CRC_WIDTH-1 downto 0);
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signal nextChecksum : std_logic_vector(CRC_WIDTH-1 downto 0);
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begin
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-- Kombinatorik fuer CRC-Berechnung
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ProcNextCRC: process (data, checksum_i)
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variable mix: std_logic_vector(CRC_WIDTH-1 downto 0);
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variable MSB : std_logic;
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begin
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mix := checksum_i;
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for i in data'range loop
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-- Pruefen ob MSB gesetzt ist
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MSB := mix(mix'length-1);
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-- neues Bit reinschieben
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mix := mix(mix'length-2 downto 0) & data(i);
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-- XOR Verknuepfung
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if MSB = '1' then
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mix := mix XOR polynomial;
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end if;
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end loop;
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nextChecksum <= mix;
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end process;
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-- Register zum Speichern der CRC-Pruefsumme
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Reg: process (clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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checksum_i <= initial_value;
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elsif enable = '1' then
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checksum_i <= nextChecksum;
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end if;
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end if;
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end process;
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checksum <= checksum_i;
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end architecture;
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