Matthias Biermann
195 lines
6.9 KiB
VHDL
195 lines
6.9 KiB
VHDL
------------------------------------------------------------------------------
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--
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-- File: HandshakeData.vhd
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-- Author: Elod Gyorgy
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-- Original Project: Atlys2 User Demo
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-- Date: 29 June 20116
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--
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-------------------------------------------------------------------------------
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-- (c) 2016 Copyright Digilent Incorporated
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-- All Rights Reserved
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--
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-- This program is free software; distributed under the terms of BSD 3-clause
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-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice, this
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-- list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright notice,
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-- this list of conditions and the following disclaimer in the documentation
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-- and/or other materials provided with the distribution.
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-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
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-- of its contributors may be used to endorse or promote products derived
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-- from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-------------------------------------------------------------------------------
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--
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-- Purpose:
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-- This module passes parallel data from the input clock domain (InClk) to the
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-- output clock domain (OutClk) by the means of handshake signals. A
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-- low-to-high transition on iPush will register iData inside the module
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-- and will start propagating the handshake signals towards the output domain.
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-- The data will appear on oData and is valid when oValid pulses high.
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-- The reception of data by the receiver on the OutClk domain is signaled
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-- by a pulse on oAck. This will propagate back to the input domain and
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-- assert iRdy signaling to the sender that a new data can be pushed though.
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-- If oData is always read when oValid pulses, oAck may be tied permanently
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-- high.
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-- Only assert iPush when iRdy is high!
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--
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-- Changelog:
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-- 2016-Jun-29: Fixed oValid not being a pulse.
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity HandshakeData is
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Generic (
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kDataWidth : natural := 8);
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Port (
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InClk : in STD_LOGIC;
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OutClk : in STD_LOGIC;
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iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
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oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
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iPush : in STD_LOGIC;
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iRdy : out STD_LOGIC;
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oAck : in STD_LOGIC := '1';
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oValid : out STD_LOGIC;
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aReset : in std_logic);
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end HandshakeData;
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architecture Behavioral of HandshakeData is
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signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
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signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
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signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
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attribute DONT_TOUCH : string;
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attribute DONT_TOUCH of aReset: signal is "TRUE";
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begin
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DetectPush: process(aReset, InClk)
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begin
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if (aReset = '1') then
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iPush_q <= '0';
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elsif Rising_Edge(InClk) then
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iPush_q <= iPush;
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end if;
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end process DetectPush;
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iPushRising <= iPush and not iPush_q;
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-- Register data when iPush is rising and toggle internal flag
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LatchData: process(aReset, InClk)
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begin
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if (aReset = '1') then
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iData_int <= (others => '0');
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iPushT <= '0';
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elsif Rising_Edge(InClk) then
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if (iPushRising = '1') then
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iData_int <= iData;
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iPushT <= not iPushT;
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end if;
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end if;
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end process;
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-- Cross toggle flag through synchronizer
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SyncAsyncPushT: entity work.SyncAsync
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generic map (
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kResetTo => '0',
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kStages => 2)
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port map (
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aReset => aReset,
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aIn => iPushT,
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OutClk => OutClk,
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oOut => oPushT);
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-- Detect a push edge in the OutClk domain
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-- If receiver acknowledges receipt, we can propagate the push signal back
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-- towards the input, where it will be used to generate iRdy
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DetectToggle: process(aReset, OutClk)
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begin
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if (aReset = '1') then
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oPushT_q <= '0';
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oPushTBack <= '0';
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elsif Rising_Edge(OutClk) then
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oPushT_q <= oPushT;
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if (oAck = '1') then
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oPushTBack <= oPushT_q;
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end if;
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end if;
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end process DetectToggle;
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oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
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-- Cross data from InClk domain reg (iData_in) to OutClk domain
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-- The enable for this register is the propagated and sync'd to the OutClk domain
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-- We assume here that the time it took iPush to propagate to oPushTChanged is
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-- more than the time it takes iData_int to propagate to the oData register's D pin
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OutputData: process (aReset, OutClk)
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begin
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if (aReset = '1') then
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oData <= (others => '0');
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oValid <= '0';
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elsif Rising_Edge(OutClk) then
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if (oPushTChanged = '1') then
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oData <= iData_int;
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end if;
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oValid <= oPushTChanged;
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end if;
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end process OutputData;
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-- Cross toggle flag back through synchronizer
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SyncAsyncPushTBack: entity work.SyncAsync
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generic map (
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kResetTo => '0',
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kStages => 2)
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port map (
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aReset => aReset,
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aIn => oPushTBack,
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OutClk => InClk,
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oOut => iPushTBack);
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-- Synchronize aReset into the InClk domain
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-- We need it to keep iRdy low, when aReset de-asserts
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SyncReset: entity work.ResetBridge
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generic map (
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kPolarity => '1')
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port map (
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aRst => aReset,
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OutClk => InClk,
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oRst => iReset);
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ReadySignal: process(aReset, InClk)
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begin
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if (aReset = '1') then
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iRdy <= '0';
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elsif Rising_Edge(InClk) then
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iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
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end if;
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end process ReadySignal;
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end Behavioral;
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