Matthias Biermann
2475 lines
109 KiB
XML
2475 lines
109 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>digilentinc.com</spirit:vendor>
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<spirit:library>ip</spirit:library>
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<spirit:name>MIPI_D_PHY_RX</spirit:name>
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<spirit:version>1.3</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>S_AXI_LITE</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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<spirit:slave>
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<spirit:memoryMapRef spirit:memoryMapRef="S_AXI_LITE"/>
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</spirit:slave>
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<spirit:connectionRequired>true</spirit:connectionRequired>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_awaddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_awprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_awvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_awready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_wdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WSTRB</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_wstrb</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_wvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_wready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_bresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_bvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_bready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_araddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_arprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_arvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_arready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_rdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_rresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_rvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_lite_rready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>WIZ_DATA_WIDTH</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>WIZ_NUM_REG</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">4</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:busInterfaceInfo>
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_LITE" xilinx:dependency="$kGenerateAXIL">false</xilinx:isEnabled>
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</xilinx:enablement>
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</xilinx:busInterfaceInfo>
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</spirit:vendorExtensions>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>dphy_hs_clock</spirit:name>
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<spirit:displayName>D-PHY HS Clock</spirit:displayName>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_P</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>dphy_clk_hs_p</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_N</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>dphy_clk_hs_n</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>RefClk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>RefClk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.REFCLK.ASSOCIATED_RESET">aRst</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>D_PHY_PPI</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="rx_mipi_ppi_if" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="rx_mipi_ppi_if_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL1_RXACTIVEHS</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>rbD1RxActiveHS</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL1_RXLPDTESC</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>aD1RxLpdtEsc</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL1_ERRESC</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>aD1ErrEsc</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CL_ENABLE</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>aClkEnable</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL1_RXDATAHS</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>rbD1RxDataHS</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL0_ERRESC</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>aD0ErrEsc</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL0_ERRSOTHS</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>rbD0ErrSotHS</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL1_RXULPSESC</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>aD1RxUlpsEsc</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL1_ERRSOTSYNCHS</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>rbD1ErrSotSyncHS</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL0_RXVALIDESC</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>aD0RxValidEsc</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL0_STOPSTATE</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>aD0Stopstate</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>DL0_ULPSACTIVENOT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>aD0UlpsActiveNot</spirit:name>
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</spirit:physicalPort>
|
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</spirit:portMap>
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<spirit:portMap>
|
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<spirit:logicalPort>
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<spirit:name>CL_ULPSACTIVENOT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>aClkUlpsActiveNot</spirit:name>
|
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</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_RXSYNCHS</spirit:name>
|
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</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
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<spirit:name>rbD0RxSyncHS</spirit:name>
|
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</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
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|
<spirit:name>DL0_ERRSOTSYNCHS</spirit:name>
|
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</spirit:logicalPort>
|
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<spirit:physicalPort>
|
|
<spirit:name>rbD0ErrSotSyncHS</spirit:name>
|
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</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
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|
<spirit:name>DL0_ERRCONTROL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD0ErrControl</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_ENABLE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD0Enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_RXCLKESC</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>D1RxClkEsc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_ENABLE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD1Enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_RXVALIDHS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbD0RxValidHS</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_RXDATAESC</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD0RxDataEsc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CL_RXULPSCLKNOT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aRxUlpsClkNot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CL_STOPSTATE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aClkStopstate</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_ERRCONTROL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD1ErrControl</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_RXLPDTESC</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD0RxLpdtEsc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_ERRSOTHS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbD1ErrSotHS</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_RXULPSESC</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD0RxUlpsEsc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_RXTRIGGERESC</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD1RxTriggerEsc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_RXTRIGGERESC</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD0RxTriggerEsc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_RXVALIDHS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbD1RxValidHS</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_STOPSTATE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD1Stopstate</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_RXACTIVEHS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbD0RxActiveHS</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_ULPSACTIVENOT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD1UlpsActiveNot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_RXSYNCHS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbD1RxSyncHS</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CL_RXCLKACTIVEHS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aRxClkActiveHS</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_RXDATAESC</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD1RxDataEsc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_RXDATAHS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbD0RxDataHS</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_RXCLKESC</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>D0RxClkEsc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_FORCERXMODE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD1ForceRxmode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL1_RXVALIDESC</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD1RxValidEsc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DL0_FORCERXMODE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aD0ForceRxmode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>s_axi_lite_aclk</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:connectionRequired>true</spirit:connectionRequired>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_lite_aclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.ASSOCIATED_RESET">s_axi_lite_aresetn</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.ASSOCIATED_BUSIF">S_AXI_LITE</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_lite_aclk" xilinx:dependency="$kGenerateAXIL">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>s_axi_lite_aresetn</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_lite_aresetn</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>POLARITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_lite_aresetn" xilinx:dependency="$kGenerateAXIL">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>RxByteClkHS</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>RxByteClkHS</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.RXBYTECLKHS.FREQ_HZ"/>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.RXBYTECLKHS.ASSOCIATED_BUSIF">D_PHY_PPI</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>aRst</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>aRst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
</spirit:busInterfaces>
|
|
<spirit:memoryMaps>
|
|
<spirit:memoryMap>
|
|
<spirit:name>S_AXI_LITE</spirit:name>
|
|
<spirit:addressBlock>
|
|
<spirit:name>S_AXI_LITE_reg</spirit:name>
|
|
<spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
|
|
<spirit:range spirit:format="long">4096</spirit:range>
|
|
<spirit:width spirit:format="long">32</spirit:width>
|
|
<spirit:usage>register</spirit:usage>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_LITE.S_AXI_LITE_REG.OFFSET_BASE_PARAM">C_S_AXI_LITE_BASEADDR</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_LITE.S_AXI_LITE_REG.OFFSET_HIGH_PARAM">C_S_AXI_LITE_HIGHADDR</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:addressBlock>
|
|
</spirit:memoryMap>
|
|
</spirit:memoryMaps>
|
|
<spirit:model>
|
|
<spirit:views>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_softwaredriver</spirit:name>
|
|
<spirit:displayName>Software Driver</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>c772c813</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_xpgui</spirit:name>
|
|
<spirit:displayName>UI Layout</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>c803790e</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>bd_tcl</spirit:name>
|
|
<spirit:displayName>Block Diagram</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>bd_tcl_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>4de054d7</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
|
<spirit:displayName>Synthesis</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
|
<spirit:modelName>MIPI_DPHY_Receiver</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>c8634fe7</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
|
<spirit:displayName>Simulation</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
|
<spirit:modelName>MIPI_DPHY_Receiver</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>bf6fda23</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_testbench</spirit:name>
|
|
<spirit:displayName>Test Bench</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:simulation.testbench</spirit:envIdentifier>
|
|
<spirit:modelName>tb_MIPI_DPHY_Receiver</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_testbench_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>07087a35</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_productguide</spirit:name>
|
|
<spirit:displayName>Product Guide</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:docs.productguide</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_productguide_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>c527113a</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_utilityxitfiles</spirit:name>
|
|
<spirit:displayName>Utility XIT/TTCL</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:xit.util</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_utilityxitfiles_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>15cac246</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
</spirit:views>
|
|
<spirit:ports>
|
|
<spirit:port>
|
|
<spirit:name>dphy_clk_hs_p</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dphy_clk_hs_n</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dphy_clk_lp_p</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dphy_clk_lp_n</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dphy_data_hs_p</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.kNoOfDataLanes')) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dphy_data_hs_n</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.kNoOfDataLanes')) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dphy_data_lp_p</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.kNoOfDataLanes')) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dphy_data_lp_n</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.kNoOfDataLanes')) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>RefClk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aRst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rDlyCtrlLockedIn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rDlyCtrlLockedIn" xilinx:dependency="not ($kSharedLogic)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rDlyCtrlLockedOut</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rDlyCtrlLockedOut" xilinx:dependency="$kSharedLogic">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>RxDDRClkHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aRxClkActiveHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aClkStopstate</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aClkEnable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aClkUlpsActiveNot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aRxUlpsClkNot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aClkForceRxmode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aClkErrControl</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>RxByteClkHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0Stopstate</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0Enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0UlpsActiveNot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD0RxDataHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD0RxValidHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD0RxActiveHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD0RxSyncHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD0ErrSotHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD0ErrSotSyncHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0ForceRxmode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>D0RxClkEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0RxDataEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0RxValidEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0RxLpdtEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0RxUlpsEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0RxTriggerEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0ErrEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD0ErrControl</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1Stopstate</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1Enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1UlpsActiveNot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD1RxDataHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD1RxValidHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD1RxActiveHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD1RxSyncHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD1ErrSotHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbD1ErrSotSyncHS</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1ForceRxmode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>D1RxClkEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1RxDataEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1RxValidEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1RxLpdtEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1RxUlpsEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1RxTriggerEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1ErrEsc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>aD1ErrControl</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_awaddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_LITE_ADDR_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_awprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_awvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_awready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_wdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_LITE_DATA_WIDTH')) - 1)">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_wstrb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_LITE_DATA_WIDTH')) / 8) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_wvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_wready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_bresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_bvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_bready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_araddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_LITE_ADDR_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_arprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_arvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_arready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_rdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_LITE_DATA_WIDTH')) - 1)">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_rresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_rvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_rready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_aclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_lite_aresetn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
</spirit:ports>
|
|
<spirit:modelParameters>
|
|
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
|
<spirit:name>C_S_AXI_LITE_DATA_WIDTH</spirit:name>
|
|
<spirit:displayName>C S AXI LITE DATA WIDTH</spirit:displayName>
|
|
<spirit:description>Width of S_AXI data bus</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_LITE_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S_AXI_LITE_ADDR_WIDTH</spirit:name>
|
|
<spirit:displayName>C S AXI LITE ADDR WIDTH</spirit:displayName>
|
|
<spirit:description>Width of S_AXI address bus</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_LITE_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>kVersionMajor</spirit:name>
|
|
<spirit:displayName>Kversionmajor</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kVersionMajor" spirit:minimum="0" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>kVersionMinor</spirit:name>
|
|
<spirit:displayName>Kversionminor</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kVersionMinor" spirit:minimum="0" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>kNoOfDataLanes</spirit:name>
|
|
<spirit:displayName>Knoofdatalanes</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kNoOfDataLanes" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="boolean">
|
|
<spirit:name>kGenerateMMCM</spirit:name>
|
|
<spirit:displayName>Kgeneratemmcm</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kGenerateMMCM">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="boolean">
|
|
<spirit:name>kGenerateAXIL</spirit:name>
|
|
<spirit:displayName>Kgenerateaxil</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kGenerateAXIL">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>kAddDelayClk_ps</spirit:name>
|
|
<spirit:displayName>Kadddelayclk Ps</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kAddDelayClk_ps">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>kAddDelayData0_ps</spirit:name>
|
|
<spirit:displayName>Kadddelaydata0 Ps</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kAddDelayData0_ps">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>kAddDelayData1_ps</spirit:name>
|
|
<spirit:displayName>Kadddelaydata1 Ps</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kAddDelayData1_ps">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>kRefClkFreqHz</spirit:name>
|
|
<spirit:displayName>Krefclkfreqhz</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kRefClkFreqHz">200000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="boolean">
|
|
<spirit:name>kDebug</spirit:name>
|
|
<spirit:displayName>Kdebug</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kDebug">true</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S_AXI_LITE_FREQ_HZ</spirit:name>
|
|
<spirit:displayName>C S Axi Lite Freq Hz</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_LITE_FREQ_HZ">100000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="boolean">
|
|
<spirit:name>kLPFromLane0</spirit:name>
|
|
<spirit:displayName>Klpfromlane0</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kLPFromLane0">true</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="boolean">
|
|
<spirit:name>kSharedLogic</spirit:name>
|
|
<spirit:displayName>Ksharedlogic</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.kSharedLogic">true</spirit:value>
|
|
</spirit:modelParameter>
|
|
</spirit:modelParameters>
|
|
</spirit:model>
|
|
<spirit:choices>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_6fc15197</spirit:name>
|
|
<spirit:enumeration>32</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_8aad6ae4</spirit:name>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_pairs_ce1226b1</spirit:name>
|
|
<spirit:enumeration spirit:text="true">1</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="false">0</spirit:enumeration>
|
|
</spirit:choice>
|
|
</spirit:choices>
|
|
<spirit:fileSets>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>drivers/MIPI_D_PHY_RX_v1_0/data/MIPI_D_PHY_RX.mdd</spirit:name>
|
|
<spirit:userFileType>mdd</spirit:userFileType>
|
|
<spirit:userFileType>driver_mdd</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/MIPI_D_PHY_RX_v1_0/data/MIPI_D_PHY_RX.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
<spirit:userFileType>driver_tcl</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/MIPI_D_PHY_RX_v1_0/src/Makefile</spirit:name>
|
|
<spirit:userFileType>driver_src</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/MIPI_D_PHY_RX_v1_0/src/MIPI_D_PHY_RX.h</spirit:name>
|
|
<spirit:fileType>cSource</spirit:fileType>
|
|
<spirit:userFileType>driver_src</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/MIPI_D_PHY_RX_v1_0/src/MIPI_D_PHY_RX.c</spirit:name>
|
|
<spirit:fileType>cSource</spirit:fileType>
|
|
<spirit:userFileType>driver_src</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/MIPI_D_PHY_RX_v1_0/src/MIPI_D_PHY_RX_selftest.c</spirit:name>
|
|
<spirit:fileType>cSource</spirit:fileType>
|
|
<spirit:userFileType>driver_src</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xgui/MIPI_D_PHY_RX_v1_3.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
<spirit:userFileType>CHECKSUM_c803790e</spirit:userFileType>
|
|
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>bd_tcl_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>bd/bd.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>hdl/MIPI_DPHY_Receiver.xdc</spirit:name>
|
|
<spirit:userFileType>xdc</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/MIPI_DPHY_Receiver_clocks.xdc</spirit:name>
|
|
<spirit:userFileType>xdc</spirit:userFileType>
|
|
<spirit:define>
|
|
<spirit:name>processing_order</spirit:name>
|
|
<spirit:value>late</spirit:value>
|
|
</spirit:define>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/MIPI_DPHY_Receiver_ooc.xdc</spirit:name>
|
|
<spirit:userFileType>xdc</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/SyncAsync.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/DPHY_Pkg.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/SyncAsyncReset.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/DebugLib.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/HS_Deserializer.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/GlitchFilter.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/HS_Clocking.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/InputBuffer.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/DPHY_LaneSFEN.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/DPHY_LaneSCNN.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/S_AXI_Lite.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/ila_sfen_rxclk/ila_sfen_rxclk.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/ila_sfen_refclk/ila_sfen_refclk.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/ila_scnn_refclk/ila_scnn_refclk.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/MIPI_DPHY_Receiver.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
<spirit:userFileType>CHECKSUM_fdc2d378</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xsi:type="xilinx:componentRefType" xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="ila" xilinx:version="6.2">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>hdl/SyncAsync.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/DPHY_Pkg.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/SyncAsyncReset.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/DebugLib.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/HS_Deserializer.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/GlitchFilter.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/HS_Clocking.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/InputBuffer.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/DPHY_LaneSFEN.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/DPHY_LaneSCNN.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/S_AXI_Lite.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/MIPI_DPHY_Receiver.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="ila" xilinx:version="6.2">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_testbench_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>tb/MIPI_DPHY_Receiver_behav.wcfg</spirit:name>
|
|
<spirit:fileType>unknown</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_testbench</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>tb/tb_MIPI_DPHY_Receiver.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_testbench</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_productguide_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>docs/mipi_d_phy_rx.pdf</spirit:name>
|
|
<spirit:userFileType>pdf</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>gui/MIPI_D_PHY_RX_v1_2.gtcl</spirit:name>
|
|
<spirit:userFileType>GTCL</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
</spirit:fileSets>
|
|
<spirit:description>MIPI Alliance D-PHY Receiver Physical Layer</spirit:description>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S_AXI_LITE_DATA_WIDTH</spirit:name>
|
|
<spirit:displayName>C S AXI LITE DATA WIDTH</spirit:displayName>
|
|
<spirit:description>Width of S_AXI data bus</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_LITE_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S_AXI_LITE_DATA_WIDTH">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S_AXI_LITE_ADDR_WIDTH</spirit:name>
|
|
<spirit:displayName>C S AXI LITE ADDR WIDTH</spirit:displayName>
|
|
<spirit:description>Width of S_AXI address bus</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_LITE_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S_AXI_LITE_ADDR_WIDTH">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S_AXI_LITE_BASEADDR</spirit:name>
|
|
<spirit:displayName>C S AXI LITE BASEADDR</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_LITE_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S_AXI_LITE_BASEADDR">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S_AXI_LITE_HIGHADDR</spirit:name>
|
|
<spirit:displayName>C S AXI LITE HIGHADDR</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_LITE_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S_AXI_LITE_HIGHADDR">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">MIPI_D_PHY_RX_v1_0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kVersionMajor</spirit:name>
|
|
<spirit:displayName>Kversionmajor</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.kVersionMajor">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kVersionMinor</spirit:name>
|
|
<spirit:displayName>Kversionminor</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.kVersionMinor">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kNoOfDataLanes</spirit:name>
|
|
<spirit:displayName>Number of Data Lanes</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.kNoOfDataLanes" spirit:choiceRef="choice_list_8aad6ae4">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kGenerateMMCM</spirit:name>
|
|
<spirit:displayName>Generate MMCM</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.kGenerateMMCM">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.kGenerateMMCM">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kGenerateAXIL</spirit:name>
|
|
<spirit:displayName>AXI-Lite Interface</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.kGenerateAXIL">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kAddDelayClk_ps</spirit:name>
|
|
<spirit:displayName>Additional Delay for Clock Lane (in ps)</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.kAddDelayClk_ps" spirit:minimum="-1000" spirit:maximum="1000" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kAddDelayData0_ps</spirit:name>
|
|
<spirit:displayName>Additional Delay for Data Lane 0 (in ps)</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.kAddDelayData0_ps" spirit:minimum="-1000" spirit:maximum="1000" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kAddDelayData1_ps</spirit:name>
|
|
<spirit:displayName>Additional Delay for Data Lane 1 (in ps)</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.kAddDelayData1_ps" spirit:minimum="-1000" spirit:maximum="1000" spirit:rangeType="long">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.kAddDelayData1_ps">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kRefClkFreqHz</spirit:name>
|
|
<spirit:displayName>Reference Clock (RefClk) Frequency (Auto)</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.kRefClkFreqHz">200000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.kRefClkFreqHz">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kDebug</spirit:name>
|
|
<spirit:displayName>Debug Module</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.kDebug">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S_AXI_LITE_FREQ_HZ</spirit:name>
|
|
<spirit:displayName>AXI-Lite Clock (s_axi_lite_aclk) Frequency (Auto)</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_LITE_FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S_AXI_LITE_FREQ_HZ">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kLPFromLane0</spirit:name>
|
|
<spirit:displayName>LP signals from Lane 0</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.kLPFromLane0">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.kLPFromLane0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>kSharedLogic</spirit:name>
|
|
<spirit:displayName>Shared Logic included in IP</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.kSharedLogic">true</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:coreExtensions>
|
|
<xilinx:supportedFamilies>
|
|
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
|
|
</xilinx:supportedFamilies>
|
|
<xilinx:taxonomies>
|
|
<xilinx:taxonomy>/Video_&_Image_Processing</xilinx:taxonomy>
|
|
</xilinx:taxonomies>
|
|
<xilinx:displayName>MIPI_D_PHY_RX_v1.0</xilinx:displayName>
|
|
<xilinx:vendorDisplayName>Digilent, Inc.</xilinx:vendorDisplayName>
|
|
<xilinx:vendorURL>http://www.digilentinc.com</xilinx:vendorURL>
|
|
<xilinx:coreRevision>4</xilinx:coreRevision>
|
|
<xilinx:upgrades>
|
|
<xilinx:canUpgradeFrom>digilentinc.com:ip:MIPI_D_PHY_RX:1.0</xilinx:canUpgradeFrom>
|
|
<xilinx:canUpgradeFrom>digilentinc.com:ip:MIPI_D_PHY_RX:1.2</xilinx:canUpgradeFrom>
|
|
</xilinx:upgrades>
|
|
<xilinx:coreCreationDateTime>2019-02-28T14:30:47Z</xilinx:coreCreationDateTime>
|
|
<xilinx:tags>
|
|
<xilinx:tag xilinx:name="natinst.com:user:MIPI_D_PHY_RX:1.0_ARCHIVE_LOCATION">c:/git/pcam/common-repo/vivado-library/ip/MIPI_D_PHY_RX_1.0</xilinx:tag>
|
|
<xilinx:tag xilinx:name="digilentinc.com:user:MIPI_D_PHY_RX:1.0_ARCHIVE_LOCATION">c:/git/pcam/common-repo/vivado-library/ip/MIPI_D_PHY_RX_1.0</xilinx:tag>
|
|
<xilinx:tag xilinx:name="digilentinc.com:ip:MIPI_D_PHY_RX:1.0_ARCHIVE_LOCATION">c:/Users/rogyorge/Desktop/mi_pi_zybo_7/proto_cam/repo/vivado-library/ip/MIPI_D_PHY_RX</xilinx:tag>
|
|
<xilinx:tag xilinx:name="digilentinc.com:ip:MIPI_D_PHY_RX:1.1_ARCHIVE_LOCATION">c:/Users/rogyorge/Desktop/mi_pi_zybo_7/proto_cam/repo/vivado-library/ip/MIPI_D_PHY_RX</xilinx:tag>
|
|
<xilinx:tag xilinx:name="digilentinc.com:ip:MIPI_D_PHY_RX:1.2_ARCHIVE_LOCATION">c:/git/fmc_pcam/repo/vivado-library/ip/MIPI_D_PHY_RX</xilinx:tag>
|
|
<xilinx:tag xilinx:name="digilentinc.com:ip:MIPI_D_PHY_RX:1.3_ARCHIVE_LOCATION">c:/git/Zybo-Z7-20-pcam-5c/repo/vivado-library/ip/MIPI_D_PHY_RX</xilinx:tag>
|
|
</xilinx:tags>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2018.2</xilinx:xilinxVersion>
|
|
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9231af9e"/>
|
|
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="a8980953"/>
|
|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2243ddc3"/>
|
|
<xilinx:checksum xilinx:scope="ports" xilinx:value="2225505a"/>
|
|
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="47d69848"/>
|
|
<xilinx:checksum xilinx:scope="parameters" xilinx:value="ccd8f029"/>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|