Matthias Biermann
81 lines
3.6 KiB
C
81 lines
3.6 KiB
C
#ifndef AXI_CRC_DMA_H_
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#define AXI_CRC_DMA_H_
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#include <stdint.h>
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#include <stdbool.h>
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// -------------------------------------------------------------------------------------------------
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// 0x00 - Control Register:
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// 0 : Run
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// 1 : Interrupt Enable
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// 31..2 : Reserved
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// -------------------------------------------------------------------------------------------------
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// 0x04 - Interrupt Status Register:
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// 0 : Interrupt Status
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// 31..1 : Reserved
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// -------------------------------------------------------------------------------------------------
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// 0x08 - Read Address Register:
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// 31..0 : First address of data packets
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// -------------------------------------------------------------------------------------------------
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// 0x0C - Write Address Register:
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// 31..0 : Address to write packets + checksum to
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// -------------------------------------------------------------------------------------------------
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// 0x10 - Packet Size Register:
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// 15.. 0 : Packets Size in words minus 1
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// 31..16 : Reserved
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// -------------------------------------------------------------------------------------------------
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// 0x14 - Number Packets Register:
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// 15.. 0 : Number of packets minus 1
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// 31..16 : Reserved
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// -------------------------------------------------------------------------------------------------
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// 0x18 - Polynomial Register:
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// 31..0 : Polynomial
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// -------------------------------------------------------------------------------------------------
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// 0x1C - Initial Value Register:
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// 31..0 : Initial Value
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// -------------------------------------------------------------------------------------------------
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// 0x20 - Final XOR Register:
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// 31..0 : Final XOR Value
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// -------------------------------------------------------------------------------------------------
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// 0x24 - InOutReflected Register:
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// 0 : Input Reflected
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// 1 : Output Reflected
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// 31..2 : Reserved
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// -------------------------------------------------------------------------------------------------
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// 0x28 - AxCache Register:
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// 3.. 0 : AWCache for M_AXI Write
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// 7.. 4 : ARCache for M_AXI Read
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// 31..8 : Reserved
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// -------------------------------------------------------------------------------------------------
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typedef struct
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{
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volatile uint32_t Control; // [0] Run, [1] INT Enable
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volatile uint32_t InterruptStatus; // [0] INT Status
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volatile uint32_t ReadAddress; // [31:0] Read Address of Data
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volatile uint32_t WriteAddress; // [31:0] Write Address of Data + CRC Checksums
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volatile uint32_t PacketSize; // [15:0] Size of Packets Minus 1 in 32 Bit words
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volatile uint32_t NumberPackets; // [15:0] Number of Packets Minus 1
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volatile uint32_t Polynomial; // [31:0] Polynomial for CRC Calculation
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volatile uint32_t InitialValue; // [31:0] Initial Value of CRC Calculation
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volatile uint32_t FinalXOR; // [31:0] Final XOR Value
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volatile uint32_t InOutReflected; // [0] Input Reflected, [1] Output Reflected
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volatile uint32_t AxCache; // [3:0] M_AXI AWCache, [7:4] M_AXI ARCache
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} CRC_DMA_Typedef;
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typedef CRC_DMA_Typedef *PCRC_DMA_Typedef;
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typedef struct
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{
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uint32_t Polynomial;
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uint32_t InitalValue;
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uint32_t FinalXOR;
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bool InputReflected;
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bool OutputReflected;
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} CrcParameterSet;
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// load a specific set of CRC parameters into Hardware
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void CRC_DMA_set_parameters(PCRC_DMA_Typedef baseAddr, const CrcParameterSet* parameterSet);
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#endif /* AXI_CRC_DMA_H_ */
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