From 154b3545390218be222c9dfcfb866ae46784fb84 Mon Sep 17 00:00:00 2001 From: Matthias Biermann Date: Tue, 10 Dec 2024 19:01:12 +0100 Subject: [PATCH] =?UTF-8?q?M6:=20Blockdesign=20f=C3=BCr=20Synthese?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../sources_1/bd/design_1/design_1.bxml | 55 +- .../design_1_axis_video_filter_1_1.xml | 102 +- .../sources_1/bd/design_1/sim/design_1.vhd | 469 - .../sources_1/bd/design_1/synth/design_1.vhd | 469 - .../sources_1/bd/design_2/design_2.bxml | 8 +- .../design_2_processing_system7_0_0.xml | 22 +- .../sources_1/bd/design_3/design_3.bxml | 11 + .../design_3_ooc.xdc} | 4 + .../bd/design_3/hdl/design_3_wrapper.vhd | 116 + .../design_3_auto_pc_0/design_3_auto_pc_0.xml | 4016 ++ .../design_3_auto_us_0/design_3_auto_us_0.xml | 3739 ++ .../design_3_auto_us_1/design_3_auto_us_1.xml | 3739 ++ .../design_3_axi_2d_mmvs_0_0.xml | 3933 ++ .../design_3_axi_interconnect_0_0.xml | 1644 + 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b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml index a86951e..6b62b2c 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml @@ -2,55 +2,10 @@ Composite Fileset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml index 36a14fe..9eaf8b4 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml @@ -893,40 +893,6 @@ - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - axis_video_filter - - - outputProductCRC - 9:8c885d99 - - - - - xilinx_vhdlsimulationwrapper - VHDL Simulation Wrapper - vhdlSource:vivado.xilinx.com:simulation.wrapper - vhdl - design_1_axis_video_filter_1_1 - - xilinx_vhdlsimulationwrapper_view_fileset - - - - GENtimestamp - Tue Dec 10 17:13:22 UTC 2024 - - - outputProductCRC - 9:8c885d99 - - - - ACLK @@ -935,7 +901,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -947,7 +913,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -959,7 +925,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -978,7 +944,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -993,7 +959,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1008,7 +974,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1024,7 +990,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1039,7 +1005,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1055,7 +1021,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1067,7 +1033,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1079,7 +1045,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1094,7 +1060,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1110,7 +1076,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1125,7 +1091,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1140,7 +1106,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1156,7 +1122,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1171,7 +1137,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1186,7 +1152,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1202,7 +1168,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1217,7 +1183,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1229,7 +1195,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1248,7 +1214,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1264,7 +1230,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1279,7 +1245,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1294,7 +1260,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1310,7 +1276,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1322,7 +1288,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1334,7 +1300,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1353,7 +1319,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1374,16 +1340,6 @@ ACTIVE_LOW - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/design_1_axis_video_filter_1_1.vhd - vhdlSource - xil_defaultlib - - - xilinx.com:module_ref:axis_video_filter:1.0 diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.vhd deleted file mode 100644 index 98274f7..0000000 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.vhd +++ /dev/null @@ -1,469 +0,0 @@ ---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- ---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Tue Dec 10 18:13:22 2024 ---Host : BiermannSurface running 64-bit major release (build 9200) ---Command : generate_target design_1.bd ---Design : design_1 ---Purpose : IP block netlist ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity SIM_Enviroment_imp_14W2BPY is - port ( - M_AXIL_ACLK : out STD_LOGIC; - M_AXIL_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_arready : in STD_LOGIC; - M_AXIL_arvalid : out STD_LOGIC; - M_AXIL_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_awready : in STD_LOGIC; - M_AXIL_awvalid : out STD_LOGIC; - M_AXIL_bready : out STD_LOGIC; - M_AXIL_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); - M_AXIL_bvalid : in STD_LOGIC; - M_AXIL_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_rready : out STD_LOGIC; - M_AXIL_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); - M_AXIL_rvalid : in STD_LOGIC; - M_AXIL_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_wready : in STD_LOGIC; - M_AXIL_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); - M_AXIL_wvalid : out STD_LOGIC; - M_AXIS_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_tlast : out STD_LOGIC; - M_AXIS_tready : in STD_LOGIC; - M_AXIS_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - M_AXIS_tvalid : out STD_LOGIC; - S_AXIS_ARESETN : out STD_LOGIC; - S_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_tlast : in STD_LOGIC; - S_AXIS_tready : out STD_LOGIC; - S_AXIS_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - S_AXIS_tvalid : in STD_LOGIC - ); -end SIM_Enviroment_imp_14W2BPY; - -architecture STRUCTURE of SIM_Enviroment_imp_14W2BPY is - component design_1_clk_rst_generator_0_0 is - port ( - clk : out STD_LOGIC; - rst_n : out STD_LOGIC; - stop_simulation : in STD_LOGIC - ); - end component design_1_clk_rst_generator_0_0; - component design_1_axis_master_simmodel_0_0 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - FINISHED : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - end component design_1_axis_master_simmodel_0_0; - component design_1_axis_slave_simmodel_0_0 is - port ( - FINISHED : out STD_LOGIC; - S_AXIS_ACLK : in STD_LOGIC; - S_AXIS_ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - end component design_1_axis_slave_simmodel_0_0; - component design_1_axil_master_with_rom_0_0 is - port ( - M_AXIL_ACLK : in STD_LOGIC; - M_AXIL_ARESETN : in STD_LOGIC; - M_AXIL_ARREADY : in STD_LOGIC; - M_AXIL_ARVALID : out STD_LOGIC; - M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); - M_AXIL_RREADY : out STD_LOGIC; - M_AXIL_RVALID : in STD_LOGIC; - M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); - M_AXIL_AWREADY : in STD_LOGIC; - M_AXIL_AWVALID : out STD_LOGIC; - M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); - M_AXIL_WREADY : in STD_LOGIC; - M_AXIL_WVALID : out STD_LOGIC; - M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); - M_AXIL_BREADY : out STD_LOGIC; - M_AXIL_BVALID : in STD_LOGIC; - M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ) - ); - end component design_1_axil_master_with_rom_0_0; - signal Net : STD_LOGIC; - signal Net1 : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); - signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_slave_simmodel_0_FINISHED : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); - signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; - signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_axis_master_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC; -begin - M_AXIL_ACLK <= Net; - M_AXIL_araddr(31 downto 0) <= axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0); - M_AXIL_arvalid <= axil_master_with_rom_0_M_AXIL_ARVALID; - M_AXIL_awaddr(31 downto 0) <= axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0); - M_AXIL_awvalid <= axil_master_with_rom_0_M_AXIL_AWVALID; - M_AXIL_bready <= axil_master_with_rom_0_M_AXIL_BREADY; - M_AXIL_rready <= axil_master_with_rom_0_M_AXIL_RREADY; - M_AXIL_wdata(31 downto 0) <= axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0); - M_AXIL_wstrb(3 downto 0) <= axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0); - M_AXIL_wvalid <= axil_master_with_rom_0_M_AXIL_WVALID; - M_AXIS_tdata(31 downto 0) <= axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0); - M_AXIS_tlast <= axis_master_simmodel_0_M_AXIS_TLAST; - M_AXIS_tuser(0) <= axis_master_simmodel_0_M_AXIS_TUSER(0); - M_AXIS_tvalid <= axis_master_simmodel_0_M_AXIS_TVALID; - S_AXIS_ARESETN <= Net1; - S_AXIS_tready <= axis_upsizer_0_M_AXIS_TREADY; - axil_master_with_rom_0_M_AXIL_ARREADY <= M_AXIL_arready; - axil_master_with_rom_0_M_AXIL_AWREADY <= M_AXIL_awready; - axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0) <= M_AXIL_bresp(1 downto 0); - axil_master_with_rom_0_M_AXIL_BVALID <= M_AXIL_bvalid; - axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0) <= M_AXIL_rdata(31 downto 0); - axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0) <= M_AXIL_rresp(1 downto 0); - axil_master_with_rom_0_M_AXIL_RVALID <= M_AXIL_rvalid; - axil_master_with_rom_0_M_AXIL_WREADY <= M_AXIL_wready; - axis_master_simmodel_0_M_AXIS_TREADY <= M_AXIS_tready; - axis_upsizer_0_M_AXIS_TDATA(31 downto 0) <= S_AXIS_tdata(31 downto 0); - axis_upsizer_0_M_AXIS_TLAST <= S_AXIS_tlast; - axis_upsizer_0_M_AXIS_TUSER(0) <= S_AXIS_tuser(0); - axis_upsizer_0_M_AXIS_TVALID <= S_AXIS_tvalid; -axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0 - port map ( - M_AXIL_ACLK => Net, - M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0), - M_AXIL_ARESETN => Net1, - M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0), - M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY, - M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID, - M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0), - M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0), - M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY, - M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID, - M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY, - M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), - M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID, - M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), - M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY, - M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), - M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID, - M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), - M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY, - M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), - M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID - ); -axis_master_simmodel_0: component design_1_axis_master_simmodel_0_0 - port map ( - ACLK => Net, - ARESETN => Net1, - FINISHED => NLW_axis_master_simmodel_0_FINISHED_UNCONNECTED, - M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, - M_AXIS_TUSER(0) => axis_master_simmodel_0_M_AXIS_TUSER(0), - M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID - ); -axis_slave_simmodel_0: component design_1_axis_slave_simmodel_0_0 - port map ( - FINISHED => axis_slave_simmodel_0_FINISHED, - S_AXIS_ACLK => Net, - S_AXIS_ARESETN => Net1, - S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, - S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, - S_AXIS_TUSER(0) => axis_upsizer_0_M_AXIS_TUSER(0), - S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID - ); -clk_rst_generator_0: component design_1_clk_rst_generator_0_0 - port map ( - clk => Net, - rst_n => Net1, - stop_simulation => axis_slave_simmodel_0_FINISHED - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity design_1 is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; - attribute HW_HANDOFF : string; - attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef"; -end design_1; - -architecture STRUCTURE of design_1 is - component design_1_axis_downsizer_0_0 is - port ( - AXIS_ACLK : in STD_LOGIC; - AXIS_ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC - ); - end component design_1_axis_downsizer_0_0; - component design_1_axis_linemem_single_0_0 is - port ( - aclk : in STD_LOGIC; - aresetn : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axis_tlast : in STD_LOGIC; - s_axis_tready : out STD_LOGIC; - s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tvalid : out STD_LOGIC; - m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); - m_axis_tlast : out STD_LOGIC; - m_axis_tready : in STD_LOGIC; - m_axis_tuser : out STD_LOGIC_VECTOR ( 2 downto 0 ) - ); - end component design_1_axis_linemem_single_0_0; - component design_1_axis_upsizer_0_0 is - port ( - AXIS_ACLK : in STD_LOGIC; - AXIS_ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC - ); - end component design_1_axis_upsizer_0_0; - component design_1_axis_video_filter_1_1 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 2 downto 0 ); - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC; - S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 14 downto 0 ); - S_AXIL_AWVALID : in STD_LOGIC; - S_AXIL_AWREADY : out STD_LOGIC; - S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIL_WVALID : in STD_LOGIC; - S_AXIL_WREADY : out STD_LOGIC; - S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); - S_AXIL_BVALID : out STD_LOGIC; - S_AXIL_BREADY : in STD_LOGIC; - S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); - S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 14 downto 0 ); - S_AXIL_ARVALID : in STD_LOGIC; - S_AXIL_ARREADY : out STD_LOGIC; - S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIL_RVALID : out STD_LOGIC; - S_AXIL_RREADY : in STD_LOGIC; - S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ) - ); - end component design_1_axis_video_filter_1_1; - signal Net : STD_LOGIC; - signal Net1 : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC; - signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_downsizer_0_M_AXIS_TUSER : STD_LOGIC; - signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_linemem_single_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 23 downto 0 ); - signal axis_linemem_single_0_m_axis_TLAST : STD_LOGIC; - signal axis_linemem_single_0_m_axis_TREADY : STD_LOGIC; - signal axis_linemem_single_0_m_axis_TUSER : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal axis_linemem_single_0_m_axis_TVALID : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); - signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_video_filter_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal axis_video_filter_1_M_AXIS_TLAST : STD_LOGIC; - signal axis_video_filter_1_M_AXIS_TREADY : STD_LOGIC; - signal axis_video_filter_1_M_AXIS_TUSER : STD_LOGIC; - signal axis_video_filter_1_M_AXIS_TVALID : STD_LOGIC; -begin -SIM_Enviroment: entity work.SIM_Enviroment_imp_14W2BPY - port map ( - M_AXIL_ACLK => Net, - M_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0), - M_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY, - M_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID, - M_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0), - M_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY, - M_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID, - M_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY, - M_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), - M_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID, - M_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), - M_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY, - M_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), - M_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID, - M_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), - M_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY, - M_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), - M_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID, - M_AXIS_tdata(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_tlast => axis_master_simmodel_0_M_AXIS_TLAST, - M_AXIS_tready => axis_master_simmodel_0_M_AXIS_TREADY, - M_AXIS_tuser(0) => axis_master_simmodel_0_M_AXIS_TUSER(0), - M_AXIS_tvalid => axis_master_simmodel_0_M_AXIS_TVALID, - S_AXIS_ARESETN => Net1, - S_AXIS_tdata(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_tlast => axis_upsizer_0_M_AXIS_TLAST, - S_AXIS_tready => axis_upsizer_0_M_AXIS_TREADY, - S_AXIS_tuser(0) => axis_upsizer_0_M_AXIS_TUSER, - S_AXIS_tvalid => axis_upsizer_0_M_AXIS_TVALID - ); -axis_downsizer_0: component design_1_axis_downsizer_0_0 - port map ( - AXIS_ACLK => Net, - AXIS_ARESETN => Net1, - M_AXIS_TDATA(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0), - M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY, - M_AXIS_TUSER => axis_downsizer_0_M_AXIS_TUSER, - M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID, - S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, - S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, - S_AXIS_TUSER => axis_master_simmodel_0_M_AXIS_TUSER(0), - S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID - ); -axis_linemem_single_0: component design_1_axis_linemem_single_0_0 - port map ( - aclk => Net, - aresetn => Net1, - m_axis_tdata(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0), - m_axis_tlast => axis_linemem_single_0_m_axis_TLAST, - m_axis_tready => axis_linemem_single_0_m_axis_TREADY, - m_axis_tuser(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0), - m_axis_tvalid => axis_linemem_single_0_m_axis_TVALID, - s_axis_tdata(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0), - s_axis_tlast => axis_downsizer_0_M_AXIS_TLAST, - s_axis_tready => axis_downsizer_0_M_AXIS_TREADY, - s_axis_tuser(0) => axis_downsizer_0_M_AXIS_TUSER, - s_axis_tvalid => axis_downsizer_0_M_AXIS_TVALID - ); -axis_upsizer_0: component design_1_axis_upsizer_0_0 - port map ( - AXIS_ACLK => Net, - AXIS_ARESETN => Net1, - M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, - M_AXIS_TUSER => axis_upsizer_0_M_AXIS_TUSER, - M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, - S_AXIS_TDATA(7 downto 0) => axis_video_filter_1_M_AXIS_TDATA(7 downto 0), - S_AXIS_TLAST => axis_video_filter_1_M_AXIS_TLAST, - S_AXIS_TREADY => axis_video_filter_1_M_AXIS_TREADY, - S_AXIS_TUSER => axis_video_filter_1_M_AXIS_TUSER, - S_AXIS_TVALID => axis_video_filter_1_M_AXIS_TVALID - ); -axis_video_filter_1: component design_1_axis_video_filter_1_1 - port map ( - ACLK => Net, - ARESETN => Net1, - M_AXIS_TDATA(7 downto 0) => axis_video_filter_1_M_AXIS_TDATA(7 downto 0), - M_AXIS_TLAST => axis_video_filter_1_M_AXIS_TLAST, - M_AXIS_TREADY => axis_video_filter_1_M_AXIS_TREADY, - M_AXIS_TUSER => axis_video_filter_1_M_AXIS_TUSER, - M_AXIS_TVALID => axis_video_filter_1_M_AXIS_TVALID, - S_AXIL_ARADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(14 downto 0), - S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY, - S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID, - S_AXIL_AWADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(14 downto 0), - S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY, - S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID, - S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY, - S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), - S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID, - S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), - S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY, - S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), - S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID, - S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), - S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY, - S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), - S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID, - S_AXIS_TDATA(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0), - S_AXIS_TLAST => axis_linemem_single_0_m_axis_TLAST, - S_AXIS_TREADY => axis_linemem_single_0_m_axis_TREADY, - S_AXIS_TUSER(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0), - S_AXIS_TVALID => axis_linemem_single_0_m_axis_TVALID - ); -end STRUCTURE; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.vhd deleted file mode 100644 index 98274f7..0000000 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.vhd +++ /dev/null @@ -1,469 +0,0 @@ ---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- ---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Tue Dec 10 18:13:22 2024 ---Host : BiermannSurface running 64-bit major release (build 9200) ---Command : generate_target design_1.bd ---Design : design_1 ---Purpose : IP block netlist ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity SIM_Enviroment_imp_14W2BPY is - port ( - M_AXIL_ACLK : out STD_LOGIC; - M_AXIL_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_arready : in STD_LOGIC; - M_AXIL_arvalid : out STD_LOGIC; - M_AXIL_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_awready : in STD_LOGIC; - M_AXIL_awvalid : out STD_LOGIC; - M_AXIL_bready : out STD_LOGIC; - M_AXIL_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); - M_AXIL_bvalid : in STD_LOGIC; - M_AXIL_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_rready : out STD_LOGIC; - M_AXIL_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); - M_AXIL_rvalid : in STD_LOGIC; - M_AXIL_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_wready : in STD_LOGIC; - M_AXIL_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); - M_AXIL_wvalid : out STD_LOGIC; - M_AXIS_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_tlast : out STD_LOGIC; - M_AXIS_tready : in STD_LOGIC; - M_AXIS_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - M_AXIS_tvalid : out STD_LOGIC; - S_AXIS_ARESETN : out STD_LOGIC; - S_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_tlast : in STD_LOGIC; - S_AXIS_tready : out STD_LOGIC; - S_AXIS_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - S_AXIS_tvalid : in STD_LOGIC - ); -end SIM_Enviroment_imp_14W2BPY; - -architecture STRUCTURE of SIM_Enviroment_imp_14W2BPY is - component design_1_clk_rst_generator_0_0 is - port ( - clk : out STD_LOGIC; - rst_n : out STD_LOGIC; - stop_simulation : in STD_LOGIC - ); - end component design_1_clk_rst_generator_0_0; - component design_1_axis_master_simmodel_0_0 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - FINISHED : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - end component design_1_axis_master_simmodel_0_0; - component design_1_axis_slave_simmodel_0_0 is - port ( - FINISHED : out STD_LOGIC; - S_AXIS_ACLK : in STD_LOGIC; - S_AXIS_ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - end component design_1_axis_slave_simmodel_0_0; - component design_1_axil_master_with_rom_0_0 is - port ( - M_AXIL_ACLK : in STD_LOGIC; - M_AXIL_ARESETN : in STD_LOGIC; - M_AXIL_ARREADY : in STD_LOGIC; - M_AXIL_ARVALID : out STD_LOGIC; - M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); - M_AXIL_RREADY : out STD_LOGIC; - M_AXIL_RVALID : in STD_LOGIC; - M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); - M_AXIL_AWREADY : in STD_LOGIC; - M_AXIL_AWVALID : out STD_LOGIC; - M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); - M_AXIL_WREADY : in STD_LOGIC; - M_AXIL_WVALID : out STD_LOGIC; - M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); - M_AXIL_BREADY : out STD_LOGIC; - M_AXIL_BVALID : in STD_LOGIC; - M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ) - ); - end component design_1_axil_master_with_rom_0_0; - signal Net : STD_LOGIC; - signal Net1 : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); - signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_slave_simmodel_0_FINISHED : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); - signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; - signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_axis_master_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC; -begin - M_AXIL_ACLK <= Net; - M_AXIL_araddr(31 downto 0) <= axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0); - M_AXIL_arvalid <= axil_master_with_rom_0_M_AXIL_ARVALID; - M_AXIL_awaddr(31 downto 0) <= axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0); - M_AXIL_awvalid <= axil_master_with_rom_0_M_AXIL_AWVALID; - M_AXIL_bready <= axil_master_with_rom_0_M_AXIL_BREADY; - M_AXIL_rready <= axil_master_with_rom_0_M_AXIL_RREADY; - M_AXIL_wdata(31 downto 0) <= axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0); - M_AXIL_wstrb(3 downto 0) <= axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0); - M_AXIL_wvalid <= axil_master_with_rom_0_M_AXIL_WVALID; - M_AXIS_tdata(31 downto 0) <= axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0); - M_AXIS_tlast <= axis_master_simmodel_0_M_AXIS_TLAST; - M_AXIS_tuser(0) <= axis_master_simmodel_0_M_AXIS_TUSER(0); - M_AXIS_tvalid <= axis_master_simmodel_0_M_AXIS_TVALID; - S_AXIS_ARESETN <= Net1; - S_AXIS_tready <= axis_upsizer_0_M_AXIS_TREADY; - axil_master_with_rom_0_M_AXIL_ARREADY <= M_AXIL_arready; - axil_master_with_rom_0_M_AXIL_AWREADY <= M_AXIL_awready; - axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0) <= M_AXIL_bresp(1 downto 0); - axil_master_with_rom_0_M_AXIL_BVALID <= M_AXIL_bvalid; - axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0) <= M_AXIL_rdata(31 downto 0); - axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0) <= M_AXIL_rresp(1 downto 0); - axil_master_with_rom_0_M_AXIL_RVALID <= M_AXIL_rvalid; - axil_master_with_rom_0_M_AXIL_WREADY <= M_AXIL_wready; - axis_master_simmodel_0_M_AXIS_TREADY <= M_AXIS_tready; - axis_upsizer_0_M_AXIS_TDATA(31 downto 0) <= S_AXIS_tdata(31 downto 0); - axis_upsizer_0_M_AXIS_TLAST <= S_AXIS_tlast; - axis_upsizer_0_M_AXIS_TUSER(0) <= S_AXIS_tuser(0); - axis_upsizer_0_M_AXIS_TVALID <= S_AXIS_tvalid; -axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0 - port map ( - M_AXIL_ACLK => Net, - M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0), - M_AXIL_ARESETN => Net1, - M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0), - M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY, - M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID, - M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0), - M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0), - M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY, - M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID, - M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY, - M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), - M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID, - M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), - M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY, - M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), - M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID, - M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), - M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY, - M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), - M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID - ); -axis_master_simmodel_0: component design_1_axis_master_simmodel_0_0 - port map ( - ACLK => Net, - ARESETN => Net1, - FINISHED => NLW_axis_master_simmodel_0_FINISHED_UNCONNECTED, - M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, - M_AXIS_TUSER(0) => axis_master_simmodel_0_M_AXIS_TUSER(0), - M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID - ); -axis_slave_simmodel_0: component design_1_axis_slave_simmodel_0_0 - port map ( - FINISHED => axis_slave_simmodel_0_FINISHED, - S_AXIS_ACLK => Net, - S_AXIS_ARESETN => Net1, - S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, - S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, - S_AXIS_TUSER(0) => axis_upsizer_0_M_AXIS_TUSER(0), - S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID - ); -clk_rst_generator_0: component design_1_clk_rst_generator_0_0 - port map ( - clk => Net, - rst_n => Net1, - stop_simulation => axis_slave_simmodel_0_FINISHED - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity design_1 is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; - attribute HW_HANDOFF : string; - attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef"; -end design_1; - -architecture STRUCTURE of design_1 is - component design_1_axis_downsizer_0_0 is - port ( - AXIS_ACLK : in STD_LOGIC; - AXIS_ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC - ); - end component design_1_axis_downsizer_0_0; - component design_1_axis_linemem_single_0_0 is - port ( - aclk : in STD_LOGIC; - aresetn : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axis_tlast : in STD_LOGIC; - s_axis_tready : out STD_LOGIC; - s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tvalid : out STD_LOGIC; - m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); - m_axis_tlast : out STD_LOGIC; - m_axis_tready : in STD_LOGIC; - m_axis_tuser : out STD_LOGIC_VECTOR ( 2 downto 0 ) - ); - end component design_1_axis_linemem_single_0_0; - component design_1_axis_upsizer_0_0 is - port ( - AXIS_ACLK : in STD_LOGIC; - AXIS_ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC - ); - end component design_1_axis_upsizer_0_0; - component design_1_axis_video_filter_1_1 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 2 downto 0 ); - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC; - M_AXIS_TUSER : out STD_LOGIC; - S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 14 downto 0 ); - S_AXIL_AWVALID : in STD_LOGIC; - S_AXIL_AWREADY : out STD_LOGIC; - S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIL_WVALID : in STD_LOGIC; - S_AXIL_WREADY : out STD_LOGIC; - S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); - S_AXIL_BVALID : out STD_LOGIC; - S_AXIL_BREADY : in STD_LOGIC; - S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); - S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 14 downto 0 ); - S_AXIL_ARVALID : in STD_LOGIC; - S_AXIL_ARREADY : out STD_LOGIC; - S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIL_RVALID : out STD_LOGIC; - S_AXIL_RREADY : in STD_LOGIC; - S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ) - ); - end component design_1_axis_video_filter_1_1; - signal Net : STD_LOGIC; - signal Net1 : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC; - signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC; - signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_downsizer_0_M_AXIS_TUSER : STD_LOGIC; - signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_linemem_single_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 23 downto 0 ); - signal axis_linemem_single_0_m_axis_TLAST : STD_LOGIC; - signal axis_linemem_single_0_m_axis_TREADY : STD_LOGIC; - signal axis_linemem_single_0_m_axis_TUSER : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal axis_linemem_single_0_m_axis_TVALID : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); - signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC; - signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_video_filter_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal axis_video_filter_1_M_AXIS_TLAST : STD_LOGIC; - signal axis_video_filter_1_M_AXIS_TREADY : STD_LOGIC; - signal axis_video_filter_1_M_AXIS_TUSER : STD_LOGIC; - signal axis_video_filter_1_M_AXIS_TVALID : STD_LOGIC; -begin -SIM_Enviroment: entity work.SIM_Enviroment_imp_14W2BPY - port map ( - M_AXIL_ACLK => Net, - M_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0), - M_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY, - M_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID, - M_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0), - M_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY, - M_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID, - M_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY, - M_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), - M_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID, - M_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), - M_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY, - M_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), - M_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID, - M_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), - M_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY, - M_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), - M_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID, - M_AXIS_tdata(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_tlast => axis_master_simmodel_0_M_AXIS_TLAST, - M_AXIS_tready => axis_master_simmodel_0_M_AXIS_TREADY, - M_AXIS_tuser(0) => axis_master_simmodel_0_M_AXIS_TUSER(0), - M_AXIS_tvalid => axis_master_simmodel_0_M_AXIS_TVALID, - S_AXIS_ARESETN => Net1, - S_AXIS_tdata(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_tlast => axis_upsizer_0_M_AXIS_TLAST, - S_AXIS_tready => axis_upsizer_0_M_AXIS_TREADY, - S_AXIS_tuser(0) => axis_upsizer_0_M_AXIS_TUSER, - S_AXIS_tvalid => axis_upsizer_0_M_AXIS_TVALID - ); -axis_downsizer_0: component design_1_axis_downsizer_0_0 - port map ( - AXIS_ACLK => Net, - AXIS_ARESETN => Net1, - M_AXIS_TDATA(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0), - M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY, - M_AXIS_TUSER => axis_downsizer_0_M_AXIS_TUSER, - M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID, - S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST, - S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY, - S_AXIS_TUSER => axis_master_simmodel_0_M_AXIS_TUSER(0), - S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID - ); -axis_linemem_single_0: component design_1_axis_linemem_single_0_0 - port map ( - aclk => Net, - aresetn => Net1, - m_axis_tdata(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0), - m_axis_tlast => axis_linemem_single_0_m_axis_TLAST, - m_axis_tready => axis_linemem_single_0_m_axis_TREADY, - m_axis_tuser(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0), - m_axis_tvalid => axis_linemem_single_0_m_axis_TVALID, - s_axis_tdata(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0), - s_axis_tlast => axis_downsizer_0_M_AXIS_TLAST, - s_axis_tready => axis_downsizer_0_M_AXIS_TREADY, - s_axis_tuser(0) => axis_downsizer_0_M_AXIS_TUSER, - s_axis_tvalid => axis_downsizer_0_M_AXIS_TVALID - ); -axis_upsizer_0: component design_1_axis_upsizer_0_0 - port map ( - AXIS_ACLK => Net, - AXIS_ARESETN => Net1, - M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, - M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, - M_AXIS_TUSER => axis_upsizer_0_M_AXIS_TUSER, - M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, - S_AXIS_TDATA(7 downto 0) => axis_video_filter_1_M_AXIS_TDATA(7 downto 0), - S_AXIS_TLAST => axis_video_filter_1_M_AXIS_TLAST, - S_AXIS_TREADY => axis_video_filter_1_M_AXIS_TREADY, - S_AXIS_TUSER => axis_video_filter_1_M_AXIS_TUSER, - S_AXIS_TVALID => axis_video_filter_1_M_AXIS_TVALID - ); -axis_video_filter_1: component design_1_axis_video_filter_1_1 - port map ( - ACLK => Net, - ARESETN => Net1, - M_AXIS_TDATA(7 downto 0) => axis_video_filter_1_M_AXIS_TDATA(7 downto 0), - M_AXIS_TLAST => axis_video_filter_1_M_AXIS_TLAST, - M_AXIS_TREADY => axis_video_filter_1_M_AXIS_TREADY, - M_AXIS_TUSER => axis_video_filter_1_M_AXIS_TUSER, - M_AXIS_TVALID => axis_video_filter_1_M_AXIS_TVALID, - S_AXIL_ARADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(14 downto 0), - S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY, - S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID, - S_AXIL_AWADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(14 downto 0), - S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY, - S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID, - S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY, - S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0), - S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID, - S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0), - S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY, - S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0), - S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID, - S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0), - S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY, - S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0), - S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID, - S_AXIS_TDATA(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0), - S_AXIS_TLAST => axis_linemem_single_0_m_axis_TLAST, - S_AXIS_TREADY => axis_linemem_single_0_m_axis_TREADY, - S_AXIS_TUSER(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0), - S_AXIS_TVALID => axis_linemem_single_0_m_axis_TVALID - ); -end STRUCTURE; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml index e900603..5a41a9a 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xml index bc24951..20f54aa 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xml +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xml @@ -9107,7 +9107,7 @@ FREQ_HZ - 100000000 + 1e+08 FREQ_TOLERANCE_HZ @@ -9199,7 +9199,7 @@ FREQ_HZ - 125000000 + 1.25e+08 FREQ_TOLERANCE_HZ @@ -9291,7 +9291,7 @@ FREQ_HZ - 200000000 + 2e+08 FREQ_TOLERANCE_HZ @@ -9383,7 +9383,7 @@ FREQ_HZ - 66666672 + 6.66667e+07 FREQ_TOLERANCE_HZ @@ -36541,13 +36541,6 @@ PCW_ENET0_RESET_IO <Select> - - - - false - - - PCW_ENET1_PERIPHERAL_ENABLE @@ -37339,13 +37332,6 @@ PCW_I2C0_RESET_IO <Select> - - - - false - - - PCW_I2C1_PERIPHERAL_ENABLE diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/design_3.bxml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/design_3.bxml new file mode 100644 index 0000000..2d8b041 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/design_3.bxml @@ -0,0 +1,11 @@ + + + + Composite Fileset + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1_ooc.xdc b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/design_3_ooc.xdc similarity index 55% rename from Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1_ooc.xdc rename to Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/design_3_ooc.xdc index 7fac2b2..5ee9a4d 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1_ooc.xdc +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/design_3_ooc.xdc @@ -6,5 +6,9 @@ # This constraints file is not used in normal top-down synthesis (default flow # of Vivado) ################################################################################ +create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 10 [get_pins PS/processing_system7_0/FCLK_CLK0] +create_clock -name PS_processing_system7_0_FCLK_CLK1 -period 8 [get_pins PS/processing_system7_0/FCLK_CLK1] +create_clock -name PS_processing_system7_0_FCLK_CLK2 -period 5 [get_pins PS/processing_system7_0/FCLK_CLK2] +create_clock -name PS_processing_system7_0_FCLK_CLK3 -period 15 [get_pins PS/processing_system7_0/FCLK_CLK3] ################################################################################ \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/hdl/design_3_wrapper.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/hdl/design_3_wrapper.vhd new file mode 100644 index 0000000..abb4cdd --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/hdl/design_3_wrapper.vhd @@ -0,0 +1,116 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Tue Dec 10 18:59:40 2024 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target design_3_wrapper.bd +--Design : design_3_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_3_wrapper is + port ( + BUTTON : in STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_cas_n : inout STD_LOGIC; + DDR_ck_n : inout STD_LOGIC; + DDR_ck_p : inout STD_LOGIC; + DDR_cke : inout STD_LOGIC; + DDR_cs_n : inout STD_LOGIC; + DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_odt : inout STD_LOGIC; + DDR_ras_n : inout STD_LOGIC; + DDR_reset_n : inout STD_LOGIC; + DDR_we_n : inout STD_LOGIC; + FIXED_IO_ddr_vrn : inout STD_LOGIC; + FIXED_IO_ddr_vrp : inout STD_LOGIC; + FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + FIXED_IO_ps_clk : inout STD_LOGIC; + FIXED_IO_ps_porb : inout STD_LOGIC; + FIXED_IO_ps_srstb : inout STD_LOGIC; + HDMI_CLK_N : out STD_LOGIC; + HDMI_CLK_P : out STD_LOGIC; + HDMI_DATA_N : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_DATA_P : out STD_LOGIC_VECTOR ( 2 downto 0 ); + LED : out STD_LOGIC_VECTOR ( 3 downto 0 ); + RGB_LED : out STD_LOGIC_VECTOR ( 5 downto 0 ); + SWITCH : in STD_LOGIC_VECTOR ( 3 downto 0 ) + ); +end design_3_wrapper; + +architecture STRUCTURE of design_3_wrapper is + component design_3 is + port ( + BUTTON : in STD_LOGIC_VECTOR ( 3 downto 0 ); + HDMI_CLK_N : out STD_LOGIC; + HDMI_CLK_P : out STD_LOGIC; + HDMI_DATA_N : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_DATA_P : out STD_LOGIC_VECTOR ( 2 downto 0 ); + LED : out STD_LOGIC_VECTOR ( 3 downto 0 ); + RGB_LED : out STD_LOGIC_VECTOR ( 5 downto 0 ); + SWITCH : in STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_cas_n : inout STD_LOGIC; + DDR_cke : inout STD_LOGIC; + DDR_ck_n : inout STD_LOGIC; + DDR_ck_p : inout STD_LOGIC; + DDR_cs_n : inout STD_LOGIC; + DDR_reset_n : inout STD_LOGIC; + DDR_odt : inout STD_LOGIC; + DDR_ras_n : inout STD_LOGIC; + DDR_we_n : inout STD_LOGIC; + DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + FIXED_IO_ddr_vrn : inout STD_LOGIC; + FIXED_IO_ddr_vrp : inout STD_LOGIC; + FIXED_IO_ps_srstb : inout STD_LOGIC; + FIXED_IO_ps_clk : inout STD_LOGIC; + FIXED_IO_ps_porb : inout STD_LOGIC + ); + end component design_3; +begin +design_3_i: component design_3 + port map ( + BUTTON(3 downto 0) => BUTTON(3 downto 0), + DDR_addr(14 downto 0) => DDR_addr(14 downto 0), + DDR_ba(2 downto 0) => DDR_ba(2 downto 0), + DDR_cas_n => DDR_cas_n, + DDR_ck_n => DDR_ck_n, + DDR_ck_p => DDR_ck_p, + DDR_cke => DDR_cke, + DDR_cs_n => DDR_cs_n, + DDR_dm(3 downto 0) => DDR_dm(3 downto 0), + DDR_dq(31 downto 0) => DDR_dq(31 downto 0), + DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), + DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), + DDR_odt => DDR_odt, + DDR_ras_n => DDR_ras_n, + DDR_reset_n => DDR_reset_n, + DDR_we_n => DDR_we_n, + FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, + FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), + FIXED_IO_ps_clk => FIXED_IO_ps_clk, + FIXED_IO_ps_porb => FIXED_IO_ps_porb, + FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, + HDMI_CLK_N => HDMI_CLK_N, + HDMI_CLK_P => HDMI_CLK_P, + HDMI_DATA_N(2 downto 0) => HDMI_DATA_N(2 downto 0), + HDMI_DATA_P(2 downto 0) => HDMI_DATA_P(2 downto 0), + LED(3 downto 0) => LED(3 downto 0), + RGB_LED(5 downto 0) => RGB_LED(5 downto 0), + SWITCH(3 downto 0) => SWITCH(3 downto 0) + ); +end STRUCTURE; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_auto_pc_0/design_3_auto_pc_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_auto_pc_0/design_3_auto_pc_0.xml new file mode 100644 index 0000000..efb7c1e --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_auto_pc_0/design_3_auto_pc_0.xml @@ -0,0 +1,4016 @@ + + + xilinx.com + customized_ip + design_3_auto_pc_0 + 1.0 + + + S_AXI + S_AXI + + + + + + + AWID + + + s_axi_awid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWLEN + + + s_axi_awlen + + + + + AWSIZE + + + s_axi_awsize + + + + + AWBURST + + + s_axi_awburst + + + + + AWLOCK + + + s_axi_awlock + + + + + AWCACHE + + + s_axi_awcache + + + + + AWPROT + + + s_axi_awprot + + + + + AWREGION + + + s_axi_awregion + + + + + AWQOS + + + s_axi_awqos + + + + + AWUSER + + + s_axi_awuser + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WID + + + s_axi_wid + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WLAST + + + s_axi_wlast + + + + + WUSER + + + s_axi_wuser + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BID + + + s_axi_bid + + + + + BRESP + + + s_axi_bresp + + + + + BUSER + + + s_axi_buser + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARID + + + s_axi_arid + + + + + ARADDR + + + s_axi_araddr + + + + + ARLEN + + + s_axi_arlen + + + + + ARSIZE + + + s_axi_arsize + + + + + ARBURST + + + s_axi_arburst + + + + + ARLOCK + + + s_axi_arlock + + + + + ARCACHE + + + s_axi_arcache + + + + + ARPROT + + + s_axi_arprot + + + + + ARREGION + + + s_axi_arregion + + + + + ARQOS + + + s_axi_arqos + + + + + ARUSER + + + s_axi_aruser + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RID + + + s_axi_rid + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RLAST + + + s_axi_rlast + + + + + RUSER + + + s_axi_ruser + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + DATA_WIDTH + 32 + + + simulation.tlm + + + + + PROTOCOL + AXI3 + + + simulation.tlm + + + + + FREQ_HZ + 100000000 + + + simulation.tlm + + + + + ID_WIDTH + 12 + + + simulation.tlm + + + + + ADDR_WIDTH + 32 + + + simulation.tlm + + + + + AWUSER_WIDTH + 0 + + + simulation.tlm + + + + + ARUSER_WIDTH + 0 + + + simulation.tlm + + + + + WUSER_WIDTH + 0 + + + simulation.tlm + + + + + RUSER_WIDTH + 0 + + + simulation.tlm + + + + + BUSER_WIDTH + 0 + + + simulation.tlm + + + + + READ_WRITE_MODE + READ_WRITE + + + simulation.tlm + + + + + HAS_BURST + 1 + + + simulation.tlm + + + + + HAS_LOCK + 1 + + + simulation.tlm + + + + + HAS_PROT + 1 + + + simulation.tlm + + + + + HAS_CACHE + 1 + + + simulation.tlm + + + + + HAS_QOS + 1 + + + simulation.tlm + + + + + HAS_REGION + 0 + + + simulation.tlm + + + + + HAS_WSTRB + 1 + + + simulation.tlm + + + + + HAS_BRESP + 1 + + + simulation.tlm + + + + + HAS_RRESP + 1 + + + simulation.tlm + + + + + SUPPORTS_NARROW_BURST + 0 + + + simulation.tlm + + + + + NUM_READ_OUTSTANDING + 8 + + + simulation.tlm + + + + + NUM_WRITE_OUTSTANDING + 8 + + + simulation.tlm + + + + + MAX_BURST_LENGTH + 16 + + + simulation.tlm + + + + + PHASE + 0.0 + + + simulation.tlm + + + + + CLK_DOMAIN + design_3_processing_system7_0_0_FCLK_CLK0 + + + simulation.tlm + + + + + NUM_READ_THREADS + 4 + + + simulation.tlm + + + + + NUM_WRITE_THREADS + 4 + + + simulation.tlm + + + + + RUSER_BITS_PER_BYTE + 0 + + + simulation.tlm + + + + + WUSER_BITS_PER_BYTE + 0 + + + simulation.tlm + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + M_AXI + M_AXI + + + + + + + AWID + + + m_axi_awid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWLEN + + + m_axi_awlen + + + + + AWSIZE + + + m_axi_awsize + + + + + AWBURST + + + m_axi_awburst + + + + + AWLOCK + + + m_axi_awlock + + + + + AWCACHE + + + m_axi_awcache + + + + + AWPROT + + + m_axi_awprot + + + + + AWREGION + + + m_axi_awregion + + + + + AWQOS + + + m_axi_awqos + + + + + AWUSER + + + m_axi_awuser + + + + + AWVALID + + + m_axi_awvalid + + + + + AWREADY + + + m_axi_awready + + + + + WID + + + m_axi_wid + + + + + WDATA + + + m_axi_wdata + + + + + WSTRB + + + m_axi_wstrb + + + + + WLAST + + + m_axi_wlast + + + + + WUSER + + + m_axi_wuser + + + + + WVALID + + + m_axi_wvalid + + + + + WREADY + + + m_axi_wready + + + + + BID + + + m_axi_bid + + + + + BRESP + + + m_axi_bresp + + + + + BUSER + + + m_axi_buser + + + + + BVALID + + + m_axi_bvalid + + + + + BREADY + + + m_axi_bready + + + + + ARID + + + m_axi_arid + + + + + ARADDR + + + m_axi_araddr + + + + + ARLEN + + + m_axi_arlen + + + + + ARSIZE + + + m_axi_arsize + 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It will convert between AXI4->AXI3/AXI4-Lite, AXI3->AXI4/AXI4-Lite, AXI4-Lite->AXI4/AXI3. + + + SI_PROTOCOL + SI PROTOCOL + AXI3 + + + MI_PROTOCOL + MI PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE Mode + READ_WRITE + + + TRANSLATION_MODE + Translation Mode + 2 + + + ADDR_WIDTH + Address Width + 32 + + + DATA_WIDTH + Data Width + 32 + + + ID_WIDTH + ID Width + 12 + + + AWUSER_WIDTH + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + ARUSER_WIDTH + 0 + + + RUSER_WIDTH + RUSER_WIDTH + 0 + + + WUSER_WIDTH + WUSER_WIDTH + 0 + + + BUSER_WIDTH + BUSER_WIDTH + 0 + + + Component_Name + design_3_auto_pc_0 + + + + + AXI Protocol Converter + + xtlm + + 28 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_auto_us_0/design_3_auto_us_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_auto_us_0/design_3_auto_us_0.xml new file mode 100644 index 0000000..4c116b2 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_auto_us_0/design_3_auto_us_0.xml @@ -0,0 +1,3739 @@ + + + xilinx.com + customized_ip + design_3_auto_us_0 + 1.0 + + + S_AXI + S_AXI + + + + + + + AWID + + + s_axi_awid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWLEN + + + s_axi_awlen + + + + + AWSIZE + + + s_axi_awsize + + + + + AWBURST + + + s_axi_awburst + + + + + AWLOCK + + + s_axi_awlock + + + + + AWCACHE + + + s_axi_awcache + + + + + AWPROT + + + s_axi_awprot + + + + + AWREGION + + + s_axi_awregion + + + + + AWQOS + + + s_axi_awqos + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WLAST + + + s_axi_wlast + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BID 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Default Mm2vs Reg Ctrl Num Buff + 1 + + + DEFAULT_MM2VS_REG_CTRL_AxCACHE + Default Mm2vs Reg Ctrl Axcache + 0 + + + DEFAULT_VS2MM_REG_CTRL_RUN + Default Vs2mm Reg Ctrl Run + 0 + + + DEFAULT_VS2MM_REG_CTRL_SYNC_SOF + Default Vs2mm Reg Ctrl Sync Sof + 0 + + + DEFAULT_VS2MM_REG_CTRL_NUM_BUFF + Default Vs2mm Reg Ctrl Num Buff + 1 + + + DEFAULT_VS2MM_REG_CTRL_AxCACHE + Default Vs2mm Reg Ctrl Axcache + 0 + + + MM2VS_VS2MM_IDWIDTH + Mm2vs Vs2mm Idwidth + 1 + + + HAS_INTERRUPT_OUTPUT + Has Interrupt Output + true + + + HAS_FINISHED_OUTPUT + Has Finished Output + false + + + SINGLE_CLOCK_AND_RESETN + Single Clock And Resetn + true + + + + + + choice_list_51d58f04 + 1 + 2 + 3 + 4 + 5 + + + choice_list_7c7a0a9d + 16 + 8 + 4 + 2 + 1 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_99a1d2b9 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_list_b7b7c380 + 14 + 13 + 12 + 11 + 10 + 9 + 8 + 7 + + + axi_2d_mmvs + + + AXIL_ENABLE + AXI Lite Interface Enable + true + + + MM2VS_VS2MM_DWIDTH + Data Width + 32 + + + MM2VS_ENABLE + MM2VS Enable + true + + + MM2VS_MAX_BURSTLEN + MM2VS: Maximum Burst Length + 16 + + + MM2VS_MAX_PIPELINED_BURSTS + MM2VS: Maximum Additional Pipelined Bursts + 3 + + + MM2VS_FIFO_AWIDTH + MM2VS: FIFO Adress Width + 12 + + + DEFAULT_MM2VS_REG_STARTADDR + MM2VS: Startaddress + 0x38000000 + + + DEFAULT_MM2VS_REG_HOR_BYTES + MM2VS: Horizontal Size [Bytes] + 1024 + + + DEFAULT_MM2VS_REG_STRIDE + MM2VS: Stride [Bytes] + 1024 + + + DEFAULT_MM2VS_REG_VER_LINES + MM2VS: Vertical Size [Lines] + 1024 + + + DEFAULT_MM2VS_REG_INT_LINE + MM2VS INT Line + 0 + + + VS2MM_ENABLE + VS2MM Enable + true + + + VS2MM_MAX_BURSTLEN + VS2MM: Maximum Burst Length + 16 + + + VS2MM_FIFO_AWIDTH + VS2MM: FIFO Adress Width + 12 + + + DEFAULT_VS2MM_REG_STARTADDR + VS2MM: Startaddress + 0x38000000 + + + DEFAULT_VS2MM_REG_HOR_BYTES + VS2MM: Horizontal Size [Bytes] + 1024 + + + DEFAULT_VS2MM_REG_STRIDE + VS2MM: Stride [Bytes] + 1024 + + + DEFAULT_VS2MM_REG_VER_LINES + VS2MM: Vertical Size [Lines] + 1024 + + + DEFAULT_VS2MM_REG_INT_LINE + VS2MM INT Line + 0 + + + DEFAULT_REG_INT_ENABLE + INT Enable Register + 0 + + + Component_Name + design_3_axi_2d_mmvs_0_0 + + + DEFAULT_MM2VS_REG_CTRL_RUN + MM2VS: Run + 0 + + + DEFAULT_MM2VS_REG_CTRL_SYNC_SOF + MM2VS: Synchronisation with Start of Frame (SOF) + 0 + + + DEFAULT_MM2VS_REG_CTRL_NUM_BUFF + MM2VS: Number of additional (Frame) Buffers + 1 + + + DEFAULT_MM2VS_REG_CTRL_AxCACHE + MM2VS: AxCACHE Setting + 0 + + + DEFAULT_VS2MM_REG_CTRL_RUN + VS2MM: Run + 0 + + + DEFAULT_VS2MM_REG_CTRL_SYNC_SOF + VS2MM: Synchronisation with Start of Frame (SOF) + 0 + + + DEFAULT_VS2MM_REG_CTRL_NUM_BUFF + VS2MM: Number of additional (Frame) Buffers + 1 + + + DEFAULT_VS2MM_REG_CTRL_AxCACHE + VS2MM: AxCACHE Setting + 0 + + + MM2VS_VS2MM_IDWIDTH + ID width + 1 + + + HAS_INTERRUPT_OUTPUT + Interrupt Outputs present + true + + + HAS_FINISHED_OUTPUT + Finished Pulse Outputs present + false + + + SINGLE_CLOCK_AND_RESETN + Single Clock And Resetn + true + + + + + axi_2d_mmvs + 44 + + d:/Projekte/edvs/vivado/vivado/ip_projects/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + 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d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_axi_interconnect_0_0/design_3_axi_interconnect_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_axi_interconnect_0_0/design_3_axi_interconnect_0_0.xml new file mode 100644 index 0000000..128befe --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_axi_interconnect_0_0/design_3_axi_interconnect_0_0.xml @@ -0,0 +1,1644 @@ + + + xilinx.com + customized_ip + design_3_axi_interconnect_0_0 + 1.0 + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_661c4a03 + 2 + 4 + 8 + 16 + 32 + 64 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_76d086ea + 0 + 1 + 2 + + + choice_pairs_ab2668a2 + 0 + 1 + 2 + + + choice_pairs_b6c9535e + 0 + 1 + 3 + 4 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 1 + + + NUM_MI + Number of Master Interfaces + 1 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 3 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 0 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 0 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_SECURE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_SECURE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_SECURE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_SECURE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_SECURE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_SECURE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_SECURE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_SECURE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_SECURE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_SECURE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_SECURE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_SECURE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_SECURE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_SECURE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_SECURE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_SECURE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_SECURE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_SECURE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_SECURE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_SECURE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_SECURE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_SECURE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_SECURE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_SECURE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_SECURE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_SECURE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_SECURE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_SECURE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_SECURE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_SECURE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_SECURE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_SECURE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_SECURE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_SECURE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_SECURE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_SECURE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_SECURE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_SECURE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_SECURE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_SECURE + Incicates whether M63_AXI connects to a secure slave + 0 + + + S00_ARB_PRIORITY + Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S01_ARB_PRIORITY + Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S02_ARB_PRIORITY + Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S03_ARB_PRIORITY + Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S04_ARB_PRIORITY + Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S05_ARB_PRIORITY + Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S06_ARB_PRIORITY + Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S07_ARB_PRIORITY + Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S08_ARB_PRIORITY + Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S09_ARB_PRIORITY + Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S10_ARB_PRIORITY + Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S11_ARB_PRIORITY + Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S12_ARB_PRIORITY + Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S13_ARB_PRIORITY + Controls S13_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S14_ARB_PRIORITY + Controls S14_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S15_ARB_PRIORITY + Controls S15_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + Component_Name + design_3_axi_interconnect_0_0 + + + + + AXI Interconnect + 29 + + + + + + + + 2023.1 + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_axi_mem_intercon_0/design_3_axi_mem_intercon_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_axi_mem_intercon_0/design_3_axi_mem_intercon_0.xml new file mode 100644 index 0000000..8bf6ce8 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_axi_mem_intercon_0/design_3_axi_mem_intercon_0.xml @@ -0,0 +1,1644 @@ + + + xilinx.com + customized_ip + design_3_axi_mem_intercon_0 + 1.0 + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_661c4a03 + 2 + 4 + 8 + 16 + 32 + 64 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_76d086ea + 0 + 1 + 2 + + + choice_pairs_ab2668a2 + 0 + 1 + 2 + + + choice_pairs_b6c9535e + 0 + 1 + 3 + 4 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 1 + + + NUM_MI + Number of Master Interfaces + 1 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 3 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 0 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 0 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI 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0 + + + + std_logic_vector + dummy_view + + + + + + + + COEFF_WIDTH + Coeff Width + 8 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + xilinx.com:module_ref:axis_video_filter:1.0 + + + COEFF_WIDTH + Coeff Width + 8 + + + Component_Name + design_3_axis_video_filter_0_0 + + + + + axis_video_filter_v1_0 + module_ref + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/design_3_processing_system7_0_0.xdc b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/design_3_processing_system7_0_0.xdc new file mode 100644 index 0000000..ec8cf3f --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/design_3_processing_system7_0_0.xdc @@ -0,0 +1,710 @@ +############################################################################ +## +## Xilinx, Inc. 2006 www.xilinx.com +############################################################################ +## File name : ps7_constraints.xdc +## +## Details : Constraints file +## FPGA family: zynq +## FPGA: xc7z020clg400-1 +## Device Size: xc7z020 +## Package: clg400 +## Speedgrade: -1 +## +## +############################################################################ +############################################################################ +############################################################################ +# Clock constraints # +############################################################################ +create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"] +set_input_jitter clk_fpga_0 0.3 +#The clocks are asynchronous, user should constrain them appropriately.# +create_clock -name clk_fpga_1 -period "8" [get_pins "PS7_i/FCLKCLK[1]"] +set_input_jitter clk_fpga_1 0.24 +#The clocks are asynchronous, user should constrain them appropriately.# +create_clock -name clk_fpga_3 -period "14.999" [get_pins "PS7_i/FCLKCLK[3]"] +set_input_jitter clk_fpga_3 0.44997 +#The clocks are asynchronous, user should constrain them appropriately.# +create_clock -name clk_fpga_2 -period "5" [get_pins "PS7_i/FCLKCLK[2]"] +set_input_jitter clk_fpga_2 0.15 +#The clocks are asynchronous, user should constrain them appropriately.# + + +############################################################################ +# I/O STANDARDS and Location Constraints # +############################################################################ + +# Enet 0 / mdio / MIO[53] +set_property iostandard "LVCMOS18" [get_ports "MIO[53]"] +set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"] +set_property slew "slow" [get_ports "MIO[53]"] +set_property drive "8" [get_ports "MIO[53]"] +set_property pullup "TRUE" [get_ports "MIO[53]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"] +# Enet 0 / mdc / MIO[52] +set_property iostandard "LVCMOS18" [get_ports "MIO[52]"] +set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"] +set_property slew "slow" [get_ports "MIO[52]"] +set_property drive "8" [get_ports "MIO[52]"] +set_property pullup "TRUE" [get_ports "MIO[52]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"] +# GPIO / gpio[51] / MIO[51] +set_property iostandard "LVCMOS18" [get_ports "MIO[51]"] +set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"] +set_property slew "slow" [get_ports "MIO[51]"] +set_property drive "8" [get_ports "MIO[51]"] +set_property pullup "TRUE" [get_ports "MIO[51]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"] +# GPIO / gpio[50] / MIO[50] +set_property iostandard "LVCMOS18" [get_ports "MIO[50]"] +set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"] +set_property slew "slow" [get_ports "MIO[50]"] +set_property drive "8" [get_ports "MIO[50]"] +set_property pullup "TRUE" [get_ports "MIO[50]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"] +# UART 1 / rx / MIO[49] +set_property iostandard "LVCMOS18" [get_ports "MIO[49]"] +set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"] +set_property slew "slow" [get_ports "MIO[49]"] +set_property drive "8" [get_ports "MIO[49]"] +set_property pullup "TRUE" [get_ports "MIO[49]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"] +# UART 1 / tx / MIO[48] +set_property iostandard "LVCMOS18" [get_ports "MIO[48]"] +set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"] +set_property slew "slow" [get_ports "MIO[48]"] +set_property drive "8" [get_ports "MIO[48]"] +set_property pullup "TRUE" [get_ports "MIO[48]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"] +# SD 0 / cd / MIO[47] +set_property iostandard "LVCMOS18" [get_ports "MIO[47]"] +set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"] +set_property slew "slow" [get_ports "MIO[47]"] +set_property drive "8" [get_ports "MIO[47]"] +set_property pullup "TRUE" [get_ports "MIO[47]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"] +# USB Reset / reset / MIO[46] +set_property iostandard "LVCMOS18" [get_ports "MIO[46]"] +set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"] +set_property slew "slow" [get_ports "MIO[46]"] +set_property drive "8" [get_ports "MIO[46]"] +set_property pullup "TRUE" [get_ports "MIO[46]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[46]"] +# SD 0 / data[3] / MIO[45] +set_property iostandard "LVCMOS18" [get_ports "MIO[45]"] +set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"] +set_property slew "slow" [get_ports "MIO[45]"] +set_property drive "8" [get_ports "MIO[45]"] +set_property pullup "TRUE" [get_ports "MIO[45]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"] +# SD 0 / data[2] / MIO[44] +set_property iostandard "LVCMOS18" [get_ports "MIO[44]"] +set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"] +set_property slew "slow" [get_ports "MIO[44]"] +set_property drive "8" [get_ports "MIO[44]"] +set_property pullup "TRUE" [get_ports "MIO[44]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"] +# SD 0 / data[1] / MIO[43] +set_property iostandard "LVCMOS18" [get_ports "MIO[43]"] +set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"] +set_property slew "slow" [get_ports "MIO[43]"] +set_property drive "8" [get_ports "MIO[43]"] +set_property pullup "TRUE" [get_ports "MIO[43]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"] +# SD 0 / data[0] / MIO[42] +set_property iostandard "LVCMOS18" [get_ports "MIO[42]"] +set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"] +set_property slew "slow" [get_ports "MIO[42]"] +set_property drive "8" [get_ports "MIO[42]"] +set_property pullup "TRUE" [get_ports "MIO[42]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"] +# SD 0 / cmd / MIO[41] +set_property iostandard "LVCMOS18" [get_ports "MIO[41]"] +set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"] +set_property slew "slow" [get_ports "MIO[41]"] +set_property drive "8" [get_ports "MIO[41]"] +set_property pullup "TRUE" [get_ports "MIO[41]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"] +# SD 0 / clk / MIO[40] +set_property iostandard "LVCMOS18" [get_ports "MIO[40]"] +set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"] +set_property slew "slow" [get_ports "MIO[40]"] +set_property drive "8" [get_ports "MIO[40]"] +set_property pullup "TRUE" [get_ports "MIO[40]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"] +# USB 0 / data[7] / MIO[39] +set_property iostandard "LVCMOS18" [get_ports "MIO[39]"] +set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"] +set_property slew "fast" [get_ports "MIO[39]"] +set_property drive "8" [get_ports "MIO[39]"] +set_property pullup "TRUE" [get_ports "MIO[39]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"] +# USB 0 / data[6] / MIO[38] +set_property iostandard "LVCMOS18" [get_ports "MIO[38]"] +set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"] +set_property slew "fast" [get_ports "MIO[38]"] +set_property drive "8" [get_ports "MIO[38]"] +set_property pullup "TRUE" [get_ports "MIO[38]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"] +# USB 0 / data[5] / MIO[37] +set_property iostandard "LVCMOS18" [get_ports "MIO[37]"] +set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"] +set_property slew "fast" [get_ports "MIO[37]"] +set_property drive "8" [get_ports "MIO[37]"] +set_property pullup "TRUE" [get_ports "MIO[37]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"] +# USB 0 / clk / MIO[36] +set_property iostandard "LVCMOS18" [get_ports "MIO[36]"] +set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"] +set_property slew "fast" [get_ports "MIO[36]"] +set_property drive "8" [get_ports "MIO[36]"] +set_property pullup "TRUE" [get_ports "MIO[36]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"] +# USB 0 / data[3] / MIO[35] +set_property iostandard "LVCMOS18" [get_ports "MIO[35]"] +set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"] +set_property slew "fast" [get_ports "MIO[35]"] +set_property drive "8" [get_ports "MIO[35]"] +set_property pullup "TRUE" [get_ports "MIO[35]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"] +# USB 0 / data[2] / MIO[34] +set_property iostandard "LVCMOS18" [get_ports "MIO[34]"] +set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"] +set_property slew "fast" [get_ports "MIO[34]"] +set_property drive "8" [get_ports "MIO[34]"] +set_property pullup "TRUE" [get_ports "MIO[34]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"] +# USB 0 / data[1] / MIO[33] +set_property iostandard "LVCMOS18" [get_ports "MIO[33]"] +set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"] +set_property slew "fast" [get_ports "MIO[33]"] +set_property drive "8" [get_ports "MIO[33]"] +set_property pullup "TRUE" [get_ports "MIO[33]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"] +# USB 0 / data[0] / MIO[32] +set_property iostandard "LVCMOS18" [get_ports "MIO[32]"] +set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"] +set_property slew "fast" [get_ports "MIO[32]"] +set_property drive "8" [get_ports "MIO[32]"] +set_property pullup "TRUE" [get_ports "MIO[32]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"] +# USB 0 / nxt / MIO[31] +set_property iostandard "LVCMOS18" [get_ports "MIO[31]"] +set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"] +set_property slew "fast" [get_ports "MIO[31]"] +set_property drive "8" [get_ports "MIO[31]"] +set_property pullup "TRUE" [get_ports "MIO[31]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"] +# USB 0 / stp / MIO[30] +set_property iostandard "LVCMOS18" [get_ports "MIO[30]"] +set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"] +set_property slew "fast" [get_ports "MIO[30]"] +set_property drive "8" [get_ports "MIO[30]"] +set_property pullup "TRUE" [get_ports "MIO[30]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"] +# USB 0 / dir / MIO[29] +set_property iostandard "LVCMOS18" [get_ports "MIO[29]"] +set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"] +set_property slew "fast" [get_ports "MIO[29]"] +set_property drive "8" [get_ports "MIO[29]"] +set_property pullup "TRUE" [get_ports "MIO[29]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"] +# USB 0 / data[4] / MIO[28] +set_property iostandard "LVCMOS18" [get_ports "MIO[28]"] +set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"] +set_property slew "fast" [get_ports "MIO[28]"] +set_property drive "8" [get_ports "MIO[28]"] +set_property pullup "TRUE" [get_ports "MIO[28]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"] +# Enet 0 / rx_ctl / MIO[27] +set_property iostandard "LVCMOS18" [get_ports "MIO[27]"] +set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"] +set_property slew "fast" [get_ports "MIO[27]"] +set_property drive "8" [get_ports "MIO[27]"] +set_property pullup "TRUE" [get_ports "MIO[27]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"] +# Enet 0 / rxd[3] / MIO[26] +set_property iostandard "LVCMOS18" [get_ports "MIO[26]"] +set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"] +set_property slew "fast" [get_ports "MIO[26]"] +set_property drive "8" [get_ports "MIO[26]"] +set_property pullup "TRUE" [get_ports "MIO[26]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"] +# Enet 0 / rxd[2] / MIO[25] +set_property iostandard "LVCMOS18" [get_ports "MIO[25]"] +set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"] +set_property slew "fast" [get_ports "MIO[25]"] +set_property drive "8" [get_ports "MIO[25]"] +set_property pullup "TRUE" [get_ports "MIO[25]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"] +# Enet 0 / rxd[1] / MIO[24] +set_property iostandard "LVCMOS18" [get_ports "MIO[24]"] +set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"] +set_property slew "fast" [get_ports "MIO[24]"] +set_property drive "8" [get_ports "MIO[24]"] +set_property pullup "TRUE" [get_ports "MIO[24]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"] +# Enet 0 / rxd[0] / MIO[23] +set_property iostandard "LVCMOS18" [get_ports "MIO[23]"] +set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"] +set_property slew "fast" [get_ports "MIO[23]"] +set_property drive "8" [get_ports "MIO[23]"] +set_property pullup "TRUE" [get_ports "MIO[23]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"] +# Enet 0 / rx_clk / MIO[22] +set_property iostandard "LVCMOS18" [get_ports "MIO[22]"] +set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"] +set_property slew "fast" [get_ports "MIO[22]"] +set_property drive "8" [get_ports "MIO[22]"] +set_property pullup "TRUE" [get_ports "MIO[22]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"] +# Enet 0 / tx_ctl / MIO[21] +set_property iostandard "LVCMOS18" [get_ports "MIO[21]"] +set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"] +set_property slew "fast" [get_ports "MIO[21]"] +set_property drive "8" [get_ports "MIO[21]"] +set_property pullup "TRUE" [get_ports "MIO[21]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"] +# Enet 0 / txd[3] / MIO[20] +set_property iostandard "LVCMOS18" [get_ports "MIO[20]"] +set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"] +set_property slew "fast" [get_ports "MIO[20]"] +set_property drive "8" [get_ports "MIO[20]"] +set_property pullup "TRUE" [get_ports "MIO[20]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"] +# Enet 0 / txd[2] / MIO[19] +set_property iostandard "LVCMOS18" [get_ports "MIO[19]"] +set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"] +set_property slew "fast" [get_ports "MIO[19]"] +set_property drive "8" [get_ports "MIO[19]"] +set_property pullup "TRUE" [get_ports "MIO[19]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"] +# Enet 0 / txd[1] / MIO[18] +set_property iostandard "LVCMOS18" [get_ports "MIO[18]"] +set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"] +set_property slew "fast" [get_ports "MIO[18]"] +set_property drive "8" [get_ports "MIO[18]"] +set_property pullup "TRUE" [get_ports "MIO[18]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"] +# Enet 0 / txd[0] / MIO[17] +set_property iostandard "LVCMOS18" [get_ports "MIO[17]"] +set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"] +set_property slew "fast" [get_ports "MIO[17]"] +set_property drive "8" [get_ports "MIO[17]"] +set_property pullup "TRUE" [get_ports "MIO[17]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"] +# Enet 0 / tx_clk / MIO[16] +set_property iostandard "LVCMOS18" [get_ports "MIO[16]"] +set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"] +set_property slew "fast" [get_ports "MIO[16]"] +set_property drive "8" [get_ports "MIO[16]"] +set_property pullup "TRUE" [get_ports "MIO[16]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"] +# I2C 0 / sda / MIO[15] +set_property iostandard "LVCMOS33" [get_ports "MIO[15]"] +set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"] +set_property slew "slow" [get_ports "MIO[15]"] +set_property drive "8" [get_ports "MIO[15]"] +set_property pullup "TRUE" [get_ports "MIO[15]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"] +# I2C 0 / scl / MIO[14] +set_property iostandard "LVCMOS33" [get_ports "MIO[14]"] +set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"] +set_property slew "slow" [get_ports "MIO[14]"] +set_property drive "8" [get_ports "MIO[14]"] +set_property pullup "TRUE" [get_ports "MIO[14]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"] +# I2C 1 / sda / MIO[13] +set_property iostandard "LVCMOS33" [get_ports "MIO[13]"] +set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"] +set_property slew "slow" [get_ports "MIO[13]"] +set_property drive "8" [get_ports "MIO[13]"] +set_property pullup "TRUE" [get_ports "MIO[13]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"] +# I2C 1 / scl / MIO[12] +set_property iostandard "LVCMOS33" [get_ports "MIO[12]"] +set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"] +set_property slew "slow" [get_ports "MIO[12]"] +set_property drive "8" [get_ports "MIO[12]"] +set_property pullup "TRUE" [get_ports "MIO[12]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"] +# UART 0 / tx / MIO[11] +set_property iostandard "LVCMOS33" [get_ports "MIO[11]"] +set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"] +set_property slew "slow" [get_ports "MIO[11]"] +set_property drive "8" [get_ports "MIO[11]"] +set_property pullup "TRUE" [get_ports "MIO[11]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[11]"] +# UART 0 / rx / MIO[10] +set_property iostandard "LVCMOS33" [get_ports "MIO[10]"] +set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"] +set_property slew "slow" [get_ports "MIO[10]"] +set_property drive "8" [get_ports "MIO[10]"] +set_property pullup "TRUE" [get_ports "MIO[10]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[10]"] +# GPIO / gpio[9] / MIO[9] +set_property iostandard "LVCMOS33" [get_ports "MIO[9]"] +set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"] +set_property slew "slow" [get_ports "MIO[9]"] +set_property drive "8" [get_ports "MIO[9]"] +set_property pullup "TRUE" [get_ports "MIO[9]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"] +# Quad SPI Flash / qspi_fbclk / MIO[8] +set_property iostandard "LVCMOS33" [get_ports "MIO[8]"] +set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"] +set_property slew "slow" [get_ports "MIO[8]"] +set_property drive "8" [get_ports "MIO[8]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"] +# GPIO / gpio[7] / MIO[7] +set_property iostandard "LVCMOS33" [get_ports "MIO[7]"] +set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"] +set_property slew "slow" [get_ports "MIO[7]"] +set_property drive "8" [get_ports "MIO[7]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"] +# Quad SPI Flash / qspi0_sclk / MIO[6] +set_property iostandard "LVCMOS33" [get_ports "MIO[6]"] +set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"] +set_property slew "slow" [get_ports "MIO[6]"] +set_property drive "8" [get_ports "MIO[6]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"] +# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5] +set_property iostandard "LVCMOS33" [get_ports "MIO[5]"] +set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"] +set_property slew "slow" [get_ports "MIO[5]"] +set_property drive "8" [get_ports "MIO[5]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"] +# Quad SPI Flash / qspi0_io[2] / MIO[4] +set_property iostandard "LVCMOS33" [get_ports "MIO[4]"] +set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"] +set_property slew "slow" [get_ports "MIO[4]"] +set_property drive "8" [get_ports "MIO[4]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"] +# Quad SPI Flash / qspi0_io[1] / MIO[3] +set_property iostandard "LVCMOS33" [get_ports "MIO[3]"] +set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"] +set_property slew "slow" [get_ports "MIO[3]"] +set_property drive "8" [get_ports "MIO[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"] +# Quad SPI Flash / qspi0_io[0] / MIO[2] +set_property iostandard "LVCMOS33" [get_ports "MIO[2]"] +set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"] +set_property slew "slow" [get_ports "MIO[2]"] +set_property drive "8" [get_ports "MIO[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"] +# Quad SPI Flash / qspi0_ss_b / MIO[1] +set_property iostandard "LVCMOS33" [get_ports "MIO[1]"] +set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"] +set_property slew "slow" [get_ports "MIO[1]"] +set_property drive "8" [get_ports "MIO[1]"] +set_property pullup "TRUE" [get_ports "MIO[1]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"] +# GPIO / gpio[0] / MIO[0] +set_property iostandard "LVCMOS33" [get_ports "MIO[0]"] +set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"] +set_property slew "slow" [get_ports "MIO[0]"] +set_property drive "8" [get_ports "MIO[0]"] +set_property pullup "TRUE" [get_ports "MIO[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRP"] +set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"] +set_property slew "FAST" [get_ports "DDR_VRP"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRN"] +set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"] +set_property slew "FAST" [get_ports "DDR_VRN"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"] +set_property iostandard "SSTL135" [get_ports "DDR_WEB"] +set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"] +set_property slew "SLOW" [get_ports "DDR_WEB"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"] +set_property iostandard "SSTL135" [get_ports "DDR_RAS_n"] +set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"] +set_property slew "SLOW" [get_ports "DDR_RAS_n"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"] +set_property iostandard "SSTL135" [get_ports "DDR_ODT"] +set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"] +set_property slew "SLOW" [get_ports "DDR_ODT"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"] +set_property iostandard "SSTL135" [get_ports "DDR_DRSTB"] +set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"] +set_property slew "FAST" [get_ports "DDR_DRSTB"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[3]"] +set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"] +set_property slew "FAST" [get_ports "DDR_DQS[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[2]"] +set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"] +set_property slew "FAST" [get_ports "DDR_DQS[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[1]"] +set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"] +set_property slew "FAST" [get_ports "DDR_DQS[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[0]"] +set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"] +set_property slew "FAST" [get_ports "DDR_DQS[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[3]"] +set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[2]"] +set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[1]"] +set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[0]"] +set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[9]"] +set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"] +set_property slew "FAST" [get_ports "DDR_DQ[9]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[8]"] +set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"] +set_property slew "FAST" [get_ports "DDR_DQ[8]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[7]"] +set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"] +set_property slew "FAST" [get_ports "DDR_DQ[7]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[6]"] +set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"] +set_property slew "FAST" [get_ports "DDR_DQ[6]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[5]"] +set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"] +set_property slew "FAST" [get_ports "DDR_DQ[5]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[4]"] +set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"] +set_property slew "FAST" [get_ports "DDR_DQ[4]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[3]"] +set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"] +set_property slew "FAST" [get_ports "DDR_DQ[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[31]"] +set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"] +set_property slew "FAST" [get_ports "DDR_DQ[31]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[30]"] +set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"] +set_property slew "FAST" [get_ports "DDR_DQ[30]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[2]"] +set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"] +set_property slew "FAST" [get_ports "DDR_DQ[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[29]"] +set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"] +set_property slew "FAST" [get_ports "DDR_DQ[29]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[28]"] +set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"] +set_property slew "FAST" [get_ports "DDR_DQ[28]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[27]"] +set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"] +set_property slew "FAST" [get_ports "DDR_DQ[27]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[26]"] +set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"] +set_property slew "FAST" [get_ports "DDR_DQ[26]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[25]"] +set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"] +set_property slew "FAST" [get_ports "DDR_DQ[25]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[24]"] +set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"] +set_property slew "FAST" [get_ports "DDR_DQ[24]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[23]"] +set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"] +set_property slew "FAST" [get_ports "DDR_DQ[23]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[22]"] +set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"] +set_property slew "FAST" [get_ports "DDR_DQ[22]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[21]"] +set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"] +set_property slew "FAST" [get_ports "DDR_DQ[21]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[20]"] +set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"] +set_property slew "FAST" [get_ports "DDR_DQ[20]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[1]"] +set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"] +set_property slew "FAST" [get_ports "DDR_DQ[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[19]"] +set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"] +set_property slew "FAST" [get_ports "DDR_DQ[19]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[18]"] +set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"] +set_property slew "FAST" [get_ports "DDR_DQ[18]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[17]"] +set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"] +set_property slew "FAST" [get_ports "DDR_DQ[17]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[16]"] +set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"] +set_property slew "FAST" [get_ports "DDR_DQ[16]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[15]"] +set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"] +set_property slew "FAST" [get_ports "DDR_DQ[15]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[14]"] +set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"] +set_property slew "FAST" [get_ports "DDR_DQ[14]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[13]"] +set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"] +set_property slew "FAST" [get_ports "DDR_DQ[13]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[12]"] +set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"] +set_property slew "FAST" [get_ports "DDR_DQ[12]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[11]"] +set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"] +set_property slew "FAST" [get_ports "DDR_DQ[11]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[10]"] +set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"] +set_property slew "FAST" [get_ports "DDR_DQ[10]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[0]"] +set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"] +set_property slew "FAST" [get_ports "DDR_DQ[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[3]"] +set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"] +set_property slew "FAST" [get_ports "DDR_DM[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[2]"] +set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"] +set_property slew "FAST" [get_ports "DDR_DM[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[1]"] +set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"] +set_property slew "FAST" [get_ports "DDR_DM[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[0]"] +set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"] +set_property slew "FAST" [get_ports "DDR_DM[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"] +set_property iostandard "SSTL135" [get_ports "DDR_CS_n"] +set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"] +set_property slew "SLOW" [get_ports "DDR_CS_n"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"] +set_property iostandard "SSTL135" [get_ports "DDR_CKE"] +set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"] +set_property slew "SLOW" [get_ports "DDR_CKE"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"] +set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk"] +set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"] +set_property slew "FAST" [get_ports "DDR_Clk"] +set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"] +set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk_n"] +set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"] +set_property slew "FAST" [get_ports "DDR_Clk_n"] +set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"] +set_property iostandard "SSTL135" [get_ports "DDR_CAS_n"] +set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"] +set_property slew "SLOW" [get_ports "DDR_CAS_n"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"] +set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[2]"] +set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"] +set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"] +set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[1]"] +set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"] +set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"] +set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[0]"] +set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"] +set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[9]"] +set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"] +set_property slew "SLOW" [get_ports "DDR_Addr[9]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[8]"] +set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"] +set_property slew "SLOW" [get_ports "DDR_Addr[8]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[7]"] +set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"] +set_property slew "SLOW" [get_ports "DDR_Addr[7]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[6]"] +set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"] +set_property slew "SLOW" [get_ports "DDR_Addr[6]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[5]"] +set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"] +set_property slew "SLOW" [get_ports "DDR_Addr[5]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[4]"] +set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"] +set_property slew "SLOW" [get_ports "DDR_Addr[4]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[3]"] +set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"] +set_property slew "SLOW" [get_ports "DDR_Addr[3]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[2]"] +set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"] +set_property slew "SLOW" [get_ports "DDR_Addr[2]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[1]"] +set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"] +set_property slew "SLOW" [get_ports "DDR_Addr[1]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[14]"] +set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"] +set_property slew "SLOW" [get_ports "DDR_Addr[14]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[13]"] +set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"] +set_property slew "SLOW" [get_ports "DDR_Addr[13]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[12]"] +set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"] +set_property slew "SLOW" [get_ports "DDR_Addr[12]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[11]"] +set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"] +set_property slew "SLOW" [get_ports "DDR_Addr[11]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[10]"] +set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"] +set_property slew "SLOW" [get_ports "DDR_Addr[10]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[0]"] +set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"] +set_property slew "SLOW" [get_ports "DDR_Addr[0]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"] +set_property iostandard "LVCMOS33" [get_ports "PS_PORB"] +set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"] +set_property slew "fast" [get_ports "PS_PORB"] +set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"] +set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"] +set_property slew "fast" [get_ports "PS_SRSTB"] +set_property iostandard "LVCMOS33" [get_ports "PS_CLK"] +set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"] +set_property slew "fast" [get_ports "PS_CLK"] + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/design_3_processing_system7_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/design_3_processing_system7_0_0.xml new file mode 100644 index 0000000..3fbed33 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/design_3_processing_system7_0_0.xml @@ -0,0 +1,40131 @@ + + + xilinx.com + customized_ip + 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DDR3_1066G + DDR3_1333F + DDR3_1333G + DDR3_1333H + DDR3_1333J + DDR3_1600G + DDR3_1600H + DDR3_1600J + DDR3_1600K + + + choice_list_bc805c93 + <Select> + x1 + x2 + x4 + + + choice_list_bd8e4b31 + 6:2:1 + 4:2:1 + + + choice_list_be8ca58c + MT41J128M8 JP-125 + MT41J128M8 JP-15E + MT41J64M16 JT-125G + MT41J64M16 JT-15E + MT41J256M8 DA-107 + MT41K128M16 JT-125 + MT41J256M8 HX-125 + MT41J256M8 HX-15E + MT41J256M8 HX-187E + MT41J128M16 HA-107G + MT41J128M16 HA-125 + MT41J128M16 HA-15E + MT41J128M16 HA-187E + MT41J512M8 RA-15E + MT41K128M16 HA-15E + MT41K256M16 RE-125 + MT41K256M16 RE-15E + MT41K256M8 DA-125 + MT41K256M8 DA-15E + MT41K256M8 HX-15E + MT41J256M16 RE-125 + Custom + + + choice_list_bed41605 + PRODUCTION + + + choice_list_c11320b6 + 0x3FFFFFFF + + + choice_list_c4046e95 + 0xE0100FFF + + + choice_list_c543d218 + 0xE0101FFF + + + choice_list_c5ebb0ea + LPDDR 2 + DDR 2 + DDR 3 + DDR 3 (Low Voltage) + + + choice_list_ca108395 + 2 + 4 + 8 + 16 + 32 + + + choice_list_cbbe7bdf + MIO 1 .. 6 + + + choice_list_ce2e47bd + Share reset pin + + + choice_list_d0304fb3 + 0xE0009000 + + + choice_list_d10f4555 + FALSE + TRUE + + + choice_list_d177f33e + 0xE0008000 + + + choice_list_d282f9a2 + <Select> + EMIO + MIO 16 .. 17 + MIO 28 .. 29 + MIO 40 .. 41 + + + choice_list_d2a5f697 + CPU_1X + External + + + choice_list_d2f51b63 + <Select> + MIO 0 9 .. 13 + + + choice_list_d525dd8e + 0xFCFFFFFF + + + choice_list_d679c87d + <Select> + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choice_list_da0dabdb + 0xE0001000 + + + choice_list_db4a1756 + 0xE0000000 + + + choice_list_dc85a6c5 + ARM PLL + DDR PLL + External + IO PLL + + + choice_list_dcdb9c78 + 0xE0006000 + + + choice_list_dd9c20f5 + 0xE0007000 + + + choice_list_de54e562 + 0xE0004000 + + + choice_list_df1359ef + 0xE0005000 + + + choice_list_e14dbfa8 + <Select> + MIO 0 + + + choice_list_e4dab0ce + 0xE000AFFF + + + choice_list_e655c9d4 + 0xE000CFFF + + + choice_list_e7127559 + 0xE000BFFF + + + choice_list_e743b0fa + DDR PLL + + + choice_list_ea556125 + ARM PLL + DDR PLL + IO PLL + + + choice_list_eaad72ce + 8 Bits + 16 Bits + 32 Bits + + + choice_list_f192fb1e + <Select> + EMIO + MIO 19 + MIO 31 + MIO 43 + + + choice_list_f585525a + 110 + 300 + 1200 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 128000 + 230400 + 460800 + 921600 + + + choice_list_f591e16e + DDR PLL + ARM PLL + IO PLL + + + choice_list_f5e7200e + 6 + 12 + + + choice_list_f632ce2e + EMIO + MIO 10 .. 11 + MIO 14 .. 15 + MIO 18 .. 19 + MIO 22 .. 23 + MIO 26 .. 27 + MIO 30 .. 31 + MIO 34 .. 35 + MIO 38 .. 39 + MIO 42 .. 43 + MIO 46 .. 47 + MIO 50 .. 51 + + + choice_list_f7022b26 + <Select> + EMIO + MIO 10 .. 15 + MIO 22 .. 27 + MIO 34 .. 39 + MIO 46 .. 51 + + + choice_list_f7b6ff1b + <Select> + EMIO + + + choice_list_fb1b25ef + <Select> + MIO 16 .. 23 + + + choice_list_fc3456a9 + Disabled + Enabled + + + choice_list_fd37a6fb + 4 + 8 + + + + + CPU0_A9 + + + + is_visible + FALSE + + + processor_type + ARM + + + + + CPU1_A9 + + + + is_visible + FALSE + + + processor_type + ARM + + + + + Arm dual core SOC with Zynq fpga + + + PCW_DDR_RAM_BASEADDR + PCW DDR RAM BASEADDR + 0x00100000 + + + + true + + + + + + PCW_DDR_RAM_HIGHADDR + PCW DDR RAM HIGHADDR + 0x3FFFFFFF + + + + true + + + + + + PCW_UART0_BASEADDR + PCW UART0 BASEADDR + 0xE0000000 + + + + true + + + + + + PCW_UART0_HIGHADDR + PCW UART0 HIGHADDR + 0xE0000FFF + + + + true + + + + + + PCW_UART1_BASEADDR + PCW UART1 BASEADDR + 0xE0001000 + + + + true + + + + + + PCW_UART1_HIGHADDR + PCW UART1 HIGHADDR + 0xE0001FFF + + + + true + + + + + + PCW_I2C0_BASEADDR + PCW I2C0 BASEADDR + 0xE0004000 + + + + true + + + + + + PCW_I2C0_HIGHADDR + PCW I2C0 HIGHADDR + 0xE0004FFF + + + + true + + + + + + PCW_I2C1_BASEADDR + PCW I2C1 BASEADDR + 0xE0005000 + + + + true + + + + + + PCW_I2C1_HIGHADDR + PCW I2C1 HIGHADDR + 0xE0005FFF + + + + true + + + + + + PCW_SPI0_BASEADDR + PCW SPI0 BASEADDR + 0xE0006000 + + + + false + + + + + + PCW_SPI0_HIGHADDR + PCW SPI0 HIGHADDR + 0xE0006FFF + + + + false + + + + + + PCW_SPI1_BASEADDR + PCW SPI1 BASEADDR + 0xE0007000 + + + + false + + + + + + PCW_SPI1_HIGHADDR + PCW SPI1 HIGHADDR + 0xE0007FFF + + + + false + + + + + + PCW_CAN0_BASEADDR + PCW CAN0 BASEADDR + 0xE0008000 + + + + false + + + + + + PCW_CAN0_HIGHADDR + PCW CAN0 HIGHADDR + 0xE0008FFF + + + + false + + + + + + PCW_CAN1_BASEADDR + PCW CAN1 BASEADDR + 0xE0009000 + + + + false + + + + + + PCW_CAN1_HIGHADDR + PCW CAN1 HIGHADDR + 0xE0009FFF + + + + false + + + + + + PCW_GPIO_BASEADDR + PCW GPIO BASEADDR + 0xE000A000 + + + + true + + + + + + PCW_GPIO_HIGHADDR + PCW GPIO HIGHADDR + 0xE000AFFF + + + + true + + + + + + PCW_ENET0_BASEADDR + PCW ENET0 BASEADDR + 0xE000B000 + + + + true + + + + + + PCW_ENET0_HIGHADDR + PCW ENET0 HIGHADDR + 0xE000BFFF + + + + true + + + + + + PCW_ENET1_BASEADDR + PCW ENET1 BASEADDR + 0xE000C000 + + + + false + + + + + + PCW_ENET1_HIGHADDR + PCW ENET1 HIGHADDR + 0xE000CFFF + + + + false + + + + + + PCW_SDIO0_BASEADDR + PCW SDIO0 BASEADDR + 0xE0100000 + + + + true + + + + + + PCW_SDIO0_HIGHADDR + PCW SDIO0 HIGHADDR + 0xE0100FFF + + + + true + + + + + + PCW_SDIO1_BASEADDR + PCW SDIO1 BASEADDR + 0xE0101000 + + + + false + + + + + + PCW_SDIO1_HIGHADDR + PCW SDIO1 HIGHADDR + 0xE0101FFF + + + + false + + + + + + PCW_USB0_BASEADDR + PCW USB0 BASEADDR + 0xE0102000 + + + + true + + + + + + PCW_USB0_HIGHADDR + PCW USB0 HIGHADDR + 0xE0102fff + + + + true + + + + + + PCW_USB1_BASEADDR + PCW USB1 BASEADDR + 0xE0103000 + + + + false + + + + + + PCW_USB1_HIGHADDR + PCW USB1 HIGHADDR + 0xE0103fff + + + + false + + + + + + PCW_TTC0_BASEADDR + PCW TTC0 BASEADDR + 0xE0104000 + + + + true + + + + + + PCW_TTC0_HIGHADDR + PCW TTC0 HIGHADDR + 0xE0104fff + + + + true + + + + + + PCW_TTC1_BASEADDR + PCW TTC1 BASEADDR + 0xE0105000 + + + + false + + + + + + PCW_TTC1_HIGHADDR + PCW TTC1 HIGHADDR + 0xE0105fff + + + + false + + + + + + PCW_FCLK_CLK0_BUF + PCW FCLK CLK0 BUF + TRUE + + + + true + + + + + + PCW_FCLK_CLK1_BUF + PCW FCLK CLK1 BUF + TRUE + + + + true + + + + + + PCW_FCLK_CLK2_BUF + PCW FCLK CLK2 BUF + TRUE + + + + true + + + + + + PCW_FCLK_CLK3_BUF + PCW FCLK CLK3 BUF + TRUE + + + + true + + + + + + PCW_UIPARAM_DDR_FREQ_MHZ + PCW UIPARAM DDR FREQ MHZ + 533.333333 + + + PCW_UIPARAM_DDR_BANK_ADDR_COUNT + PCW UIPARAM DDR BANK ADDR COUNT + 3 + + + + false + + + + + + PCW_UIPARAM_DDR_ROW_ADDR_COUNT + PCW UIPARAM DDR ROW ADDR COUNT + 15 + + + + false + + + + + + PCW_UIPARAM_DDR_COL_ADDR_COUNT + PCW UIPARAM DDR COL ADDR COUNT + 10 + + + + false + + + + + + PCW_UIPARAM_DDR_CL + PCW UIPARAM DDR CL + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_CWL + PCW UIPARAM DDR CWL + 6 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RCD + PCW UIPARAM DDR T RCD + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RP + PCW UIPARAM DDR T RP + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RC + PCW UIPARAM DDR T RC + 48.75 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RAS_MIN + PCW UIPARAM DDR T RAS MIN + 35.0 + + + + false + + + + + + PCW_UIPARAM_DDR_T_FAW + PCW UIPARAM DDR T FAW + 40.0 + + + + false + + + + + + PCW_UIPARAM_DDR_AL + PCW UIPARAM DDR AL + 0 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 + PCW UIPARAM DDR DQS TO CLK DELAY 0 + -0.050 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 + PCW UIPARAM DDR DQS TO CLK DELAY 1 + -0.044 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 + PCW UIPARAM DDR DQS TO CLK DELAY 2 + -0.035 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 + PCW UIPARAM DDR DQS TO CLK DELAY 3 + -0.100 + + + PCW_UIPARAM_DDR_BOARD_DELAY0 + PCW UIPARAM DDR BOARD DELAY0 + 0.221 + + + PCW_UIPARAM_DDR_BOARD_DELAY1 + PCW UIPARAM DDR BOARD DELAY1 + 0.222 + + + PCW_UIPARAM_DDR_BOARD_DELAY2 + PCW UIPARAM DDR BOARD DELAY2 + 0.217 + + + PCW_UIPARAM_DDR_BOARD_DELAY3 + PCW UIPARAM DDR BOARD DELAY3 + 0.244 + + + PCW_UIPARAM_DDR_DQS_0_LENGTH_MM + PCW UIPARAM DDR DQS 0 LENGTH MM + 22.8 + + + PCW_UIPARAM_DDR_DQS_1_LENGTH_MM + PCW UIPARAM DDR DQS 1 LENGTH MM + 27.9 + + + PCW_UIPARAM_DDR_DQS_2_LENGTH_MM + PCW UIPARAM DDR DQS 2 LENGTH MM + 22.9 + + + PCW_UIPARAM_DDR_DQS_3_LENGTH_MM + PCW UIPARAM DDR DQS 3 LENGTH MM + 29.4 + + + PCW_UIPARAM_DDR_DQ_0_LENGTH_MM + PCW UIPARAM DDR DQ 0 LENGTH MM + 22.8 + + + PCW_UIPARAM_DDR_DQ_1_LENGTH_MM + PCW UIPARAM DDR DQ 1 LENGTH MM + 27.9 + + + PCW_UIPARAM_DDR_DQ_2_LENGTH_MM + PCW UIPARAM DDR DQ 2 LENGTH MM + 22.9 + + + PCW_UIPARAM_DDR_DQ_3_LENGTH_MM + PCW UIPARAM DDR DQ 3 LENGTH MM + 29.4 + + + PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM + PCW UIPARAM DDR CLOCK 0 LENGTH MM + 18.8 + + + PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM + PCW UIPARAM DDR CLOCK 1 LENGTH MM + 18.8 + + + PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM + PCW UIPARAM DDR CLOCK 2 LENGTH MM + 18.8 + + + PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM + PCW UIPARAM DDR CLOCK 3 LENGTH MM + 18.8 + + + PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 0 PACKAGE LENGTH + 105.056 + + + PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 1 PACKAGE LENGTH + 66.904 + + + PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 2 PACKAGE LENGTH + 89.1715 + + + PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 3 PACKAGE LENGTH + 113.63 + + + PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 0 PACKAGE LENGTH + 98.503 + + + PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 1 PACKAGE LENGTH + 68.5855 + + + PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 2 PACKAGE LENGTH + 90.295 + + + PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 3 PACKAGE LENGTH + 103.977 + + + PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 0 PACKAGE LENGTH + 80.4535 + + + PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 1 PACKAGE LENGTH + 80.4535 + + + PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 2 PACKAGE LENGTH + 80.4535 + + + PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 3 PACKAGE LENGTH + 80.4535 + + + PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 0 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 1 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 2 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 3 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 0 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 1 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 2 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 3 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 0 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 1 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 2 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 3 PROPOGATION DELAY + 160 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 + PCW PACKAGE DDR DQS TO CLK DELAY 0 + -0.050 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 + PCW PACKAGE DDR DQS TO CLK DELAY 1 + -0.044 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 + PCW PACKAGE DDR DQS TO CLK DELAY 2 + -0.035 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 + PCW PACKAGE DDR DQS TO CLK DELAY 3 + -0.100 + + + PCW_PACKAGE_DDR_BOARD_DELAY0 + PCW PACKAGE DDR BOARD DELAY0 + 0.221 + + + PCW_PACKAGE_DDR_BOARD_DELAY1 + PCW PACKAGE DDR BOARD DELAY1 + 0.222 + + + PCW_PACKAGE_DDR_BOARD_DELAY2 + PCW PACKAGE DDR BOARD DELAY2 + 0.217 + + + PCW_PACKAGE_DDR_BOARD_DELAY3 + PCW PACKAGE DDR BOARD DELAY3 + 0.244 + + + PCW_CPU_CPU_6X4X_MAX_RANGE + PCW CPU CPU 6X4X MAX RANGE + 667 + + + PCW_CRYSTAL_PERIPHERAL_FREQMHZ + PCW CRYSTAL PERIPHERAL FREQMHZ + 33.333333 + + + PCW_APU_PERIPHERAL_FREQMHZ + PCW APU PERIPHERAL FREQMHZ + 667 + + + PCW_DCI_PERIPHERAL_FREQMHZ + PCW DCI PERIPHERAL FREQMHZ + 10.159 + + + PCW_QSPI_PERIPHERAL_FREQMHZ + PCW QSPI PERIPHERAL FREQMHZ + 200 + + + PCW_SMC_PERIPHERAL_FREQMHZ + PCW SMC PERIPHERAL FREQMHZ + 100 + + + + false + + + + + + PCW_USB0_PERIPHERAL_FREQMHZ + PCW USB0 PERIPHERAL FREQMHZ + 60 + + + + false + + + + + + PCW_USB1_PERIPHERAL_FREQMHZ + PCW USB1 PERIPHERAL FREQMHZ + 60 + + + + false + + + + + + PCW_SDIO_PERIPHERAL_FREQMHZ + PCW SDIO PERIPHERAL FREQMHZ + 50 + + + PCW_UART_PERIPHERAL_FREQMHZ + PCW UART PERIPHERAL FREQMHZ + 100 + + + PCW_SPI_PERIPHERAL_FREQMHZ + PCW SPI PERIPHERAL FREQMHZ + 166.666666 + + + + false + + + + + + PCW_CAN_PERIPHERAL_FREQMHZ + PCW CAN PERIPHERAL FREQMHZ + 100 + + + + false + + + + + + PCW_CAN0_PERIPHERAL_FREQMHZ + PCW CAN0 PERIPHERAL FREQMHZ + -1 + + + + false + + + + + + PCW_CAN1_PERIPHERAL_FREQMHZ + PCW CAN1 PERIPHERAL FREQMHZ + -1 + + + + false + + + + + + PCW_I2C_PERIPHERAL_FREQMHZ + PCW I2C PERIPHERAL FREQMHZ + 111.111115 + + + PCW_WDT_PERIPHERAL_FREQMHZ + PCW WDT PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC_PERIPHERAL_FREQMHZ + PCW TTC PERIPHERAL FREQMHZ + 50 + + + PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ + PCW TTC0 CLK0 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ + PCW TTC0 CLK1 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ + PCW TTC0 CLK2 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ + PCW TTC1 CLK0 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ + PCW TTC1 CLK1 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ + PCW TTC1 CLK2 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_PCAP_PERIPHERAL_FREQMHZ + PCW PCAP PERIPHERAL FREQMHZ + 200 + + + PCW_TPIU_PERIPHERAL_FREQMHZ + PCW TPIU PERIPHERAL FREQMHZ + 200 + + + + false + + + + + + PCW_FPGA0_PERIPHERAL_FREQMHZ + PCW FPGA0 PERIPHERAL FREQMHZ + 100 + + + PCW_FPGA1_PERIPHERAL_FREQMHZ + PCW FPGA1 PERIPHERAL FREQMHZ + 125 + + + PCW_FPGA2_PERIPHERAL_FREQMHZ + PCW FPGA2 PERIPHERAL FREQMHZ + 200 + + + PCW_FPGA3_PERIPHERAL_FREQMHZ + PCW FPGA3 PERIPHERAL FREQMHZ + 65 + + + PCW_ACT_APU_PERIPHERAL_FREQMHZ + PCW ACT APU PERIPHERAL FREQMHZ + 666.666687 + + + PCW_UIPARAM_ACT_DDR_FREQ_MHZ + PCW UIPARAM ACT DDR FREQ MHZ + 533.333374 + + + PCW_ACT_DCI_PERIPHERAL_FREQMHZ + PCW ACT DCI PERIPHERAL FREQMHZ + 10.158730 + + + PCW_ACT_QSPI_PERIPHERAL_FREQMHZ + PCW ACT QSPI PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_SMC_PERIPHERAL_FREQMHZ + PCW ACT SMC PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_ENET0_PERIPHERAL_FREQMHZ + PCW ACT ENET0 PERIPHERAL FREQMHZ + 125.000000 + + + PCW_ACT_ENET1_PERIPHERAL_FREQMHZ + PCW ACT ENET1 PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_USB0_PERIPHERAL_FREQMHZ + PCW ACT USB0 PERIPHERAL FREQMHZ + 60 + + + PCW_ACT_USB1_PERIPHERAL_FREQMHZ + PCW ACT USB1 PERIPHERAL FREQMHZ + 60 + + + PCW_ACT_SDIO_PERIPHERAL_FREQMHZ + PCW ACT SDIO PERIPHERAL FREQMHZ + 50.000000 + + + PCW_ACT_UART_PERIPHERAL_FREQMHZ + PCW ACT UART PERIPHERAL FREQMHZ + 100.000000 + + + PCW_ACT_SPI_PERIPHERAL_FREQMHZ + PCW ACT SPI PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_CAN_PERIPHERAL_FREQMHZ + PCW ACT CAN PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_CAN0_PERIPHERAL_FREQMHZ + PCW ACT CAN0 PERIPHERAL FREQMHZ + 23.8095 + + + PCW_ACT_CAN1_PERIPHERAL_FREQMHZ + PCW ACT CAN0 PERIPHERAL FREQMHZ + 23.8095 + + + PCW_ACT_I2C_PERIPHERAL_FREQMHZ + PCW ACT I2C PERIPHERAL FREQMHZ + 50 + + + PCW_ACT_WDT_PERIPHERAL_FREQMHZ + PCW ACT WDT PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC_PERIPHERAL_FREQMHZ + PCW ACT TTC PERIPHERAL FREQMHZ + 50 + + + PCW_ACT_PCAP_PERIPHERAL_FREQMHZ + PCW ACT PCAP PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_TPIU_PERIPHERAL_FREQMHZ + PCW ACT TPIU PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ + PCW ACT FPGA0 PERIPHERAL FREQMHZ + 100.000000 + + + PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ + PCW ACT FPGA1 PERIPHERAL FREQMHZ + 125.000000 + + + PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ + PCW ACT FPGA2 PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ + PCW ACT FPGA3 PERIPHERAL FREQMHZ + 66.666672 + + + PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK0 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK1 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK2 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK0 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK1 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK2 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_CLK0_FREQ + PCW CLK0 FREQ + 100000000 + + + PCW_CLK1_FREQ + PCW CLK1 FREQ + 125000000 + + + PCW_CLK2_FREQ + PCW CLK2 FREQ + 200000000 + + + PCW_CLK3_FREQ + PCW CLK3 FREQ + 66666672 + + + PCW_OVERRIDE_BASIC_CLOCK + PCW OVERRIDE FREQ + 0 + + + PCW_CPU_PERIPHERAL_DIVISOR0 + CLKPARAM + 2 + + + + false + + + + + + PCW_DDR_PERIPHERAL_DIVISOR0 + CLKPARAM + 2 + + + + false + + + + + + PCW_SMC_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_QSPI_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_SDIO_PERIPHERAL_DIVISOR0 + CLKPARAM + 20 + + + + false + + + + + + PCW_UART_PERIPHERAL_DIVISOR0 + CLKPARAM + 10 + + + + false + + + + + + PCW_SPI_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_CAN_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_CAN_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_FCLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 4 + + + + false + + + + + + PCW_FCLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_FCLK3_PERIPHERAL_DIVISOR0 + CLKPARAM + 15 + + + + false + + + + + + PCW_FCLK0_PERIPHERAL_DIVISOR1 + CLKPARAM + 2 + + + + false + + + + + + PCW_FCLK1_PERIPHERAL_DIVISOR1 + CLKPARAM + 2 + + + + false + + + + + + PCW_FCLK2_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK3_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET0_PERIPHERAL_DIVISOR0 + CLKPARAM + 8 + + + + false + + + + + + PCW_ENET1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET0_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET1_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_TPIU_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_DCI_PERIPHERAL_DIVISOR0 + CLKPARAM + 15 + + + + false + + + + + + PCW_DCI_PERIPHERAL_DIVISOR1 + CLKPARAM + 7 + + + + false + + + + + + PCW_PCAP_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_WDT_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_ARMPLL_CTRL_FBDIV + CLKPARAM + 40 + + + + false + + + + + + PCW_IOPLL_CTRL_FBDIV + CLKPARAM + 30 + + + + false + + + + + + PCW_DDRPLL_CTRL_FBDIV + CLKPARAM + 32 + + + + false + + + + + + PCW_CPU_CPU_PLL_FREQMHZ + CLKPARAM + 1333.333 + + + + false + + + + + + PCW_IO_IO_PLL_FREQMHZ + CLKPARAM + 1000.000 + + + + false + + + + + + PCW_DDR_DDR_PLL_FREQMHZ + CLKPARAM + 1066.667 + + + + false + + + + + + PCW_SMC_PERIPHERAL_VALID + PCW SMC PERIPHERAL VALID + 0 + + + PCW_SDIO_PERIPHERAL_VALID + PCW SDIO PERIPHERAL VALID + 1 + + + PCW_SPI_PERIPHERAL_VALID + PCW SPI PERIPHERAL VALID + 0 + + + PCW_CAN_PERIPHERAL_VALID + PCW CAN PERIPHERAL VALID + 0 + + + PCW_UART_PERIPHERAL_VALID + PCW UART PERIPHERAL VALID + 1 + + + PCW_EN_EMIO_CAN0 + PCW EN EMIO CAN0 + 0 + + + PCW_EN_EMIO_CAN1 + PCW EN EMIO CAN1 + 0 + + + PCW_EN_EMIO_ENET0 + PCW EN EMIO ENET0 + 0 + + + PCW_EN_EMIO_ENET1 + PCW EN EMIO ENET1 + 0 + + + PCW_EN_PTP_ENET0 + PCW EN PTP ENET0 + 0 + + + PCW_EN_PTP_ENET1 + PCW EN PTP ENET1 + 0 + + + PCW_EN_EMIO_GPIO + PCW EN EMIO GPIO + 0 + + + PCW_EN_EMIO_I2C0 + PCW EN EMIO I2C0 + 0 + + + PCW_EN_EMIO_I2C1 + PCW EN EMIO I2C1 + 0 + + + PCW_EN_EMIO_PJTAG + PCW EN EMIO PJTAG + 0 + + + PCW_EN_EMIO_SDIO0 + PCW EN EMIO SDIO0 + 0 + + + PCW_EN_EMIO_CD_SDIO0 + PCW EN EMIO CD SDIO0 + 0 + + + PCW_EN_EMIO_WP_SDIO0 + PCW EN EMIO WP SDIO0 + 1 + + + PCW_EN_EMIO_SDIO1 + PCW EN EMIO SDIO1 + 0 + + + PCW_EN_EMIO_CD_SDIO1 + PCW EN EMIO CD SDIO1 + 0 + + + PCW_EN_EMIO_WP_SDIO1 + PCW EN EMIO WP SDIO1 + 0 + + + PCW_EN_EMIO_SPI0 + PCW EN EMIO SPI0 + 0 + + + PCW_EN_EMIO_SPI1 + PCW EN EMIO SPI1 + 0 + + + PCW_EN_EMIO_UART0 + PCW EN EMIO UART0 + 0 + + + PCW_EN_EMIO_UART1 + PCW EN EMIO UART1 + 0 + + + PCW_EN_EMIO_MODEM_UART0 + PCW EN EMIO MODEM UART0 + 0 + + + PCW_EN_EMIO_MODEM_UART1 + PCW EN EMIO MODEM UART1 + 0 + + + PCW_EN_EMIO_TTC0 + PCW EN EMIO TTC0 + 1 + + + PCW_EN_EMIO_TTC1 + PCW EN EMIO TTC1 + 0 + + + PCW_EN_EMIO_WDT + PCW EN EMIO WDT + 0 + + + PCW_EN_EMIO_TRACE + PCW EN EMIO TRACE + 0 + + + PCW_USE_AXI_NONSECURE + PCW USE AXI NON SECURE + 0 + + + PCW_USE_M_AXI_GP0 + PCW USE M AXI GP0 + 1 + + + PCW_USE_M_AXI_GP1 + PCW USE M AXI GP1 + 0 + + + PCW_USE_S_AXI_GP0 + PCW USE S AXI GP0 + 0 + + + PCW_USE_S_AXI_GP1 + PCW USE S AXI GP1 + 0 + + + PCW_USE_S_AXI_ACP + PCW USE S AXI ACP + 1 + + + PCW_USE_S_AXI_HP0 + PCW USE S AXI HP0 + 1 + + + PCW_USE_S_AXI_HP1 + PCW USE S AXI HP1 + 0 + + + PCW_USE_S_AXI_HP2 + PCW USE S AXI HP2 + 0 + + + PCW_USE_S_AXI_HP3 + PCW USE S AXI HP3 + 0 + + + PCW_M_AXI_GP0_FREQMHZ + PCW M AXI GP0 FREQMHZ + 100 + + + + true + + + + + + PCW_M_AXI_GP1_FREQMHZ + PCW M AXI GP1 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_GP0_FREQMHZ + PCW S AXI GP0 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_GP1_FREQMHZ + PCW S AXI GP1 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_ACP_FREQMHZ + PCW S AXI ACP FREQMHZ + 100 + + + + true + + + + + + PCW_S_AXI_HP0_FREQMHZ + PCW S AXI HP0 FREQMHZ + 100 + + + + true + + + + + + PCW_S_AXI_HP1_FREQMHZ + PCW S AXI HP1 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_HP2_FREQMHZ + PCW S AXI HP2 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_HP3_FREQMHZ + PCW S AXI HP3 FREQMHZ + 10 + + + + false + + + + + + PCW_USE_DMA0 + PCW USE DMA0 + 0 + + + PCW_USE_DMA1 + PCW USE DMA1 + 0 + + + PCW_USE_DMA2 + PCW USE DMA2 + 0 + + + PCW_USE_DMA3 + PCW USE DMA3 + 0 + + + PCW_USE_TRACE + PCW USE TRACE + Enable FTM Trace interface used to capture data from PL to PS debug system + 0 + + + PCW_TRACE_PIPELINE_WIDTH + PCW TRACE PIPELINE WIDTH + 8 + + + + false + + + + + + PCW_INCLUDE_TRACE_BUFFER + PCW INCLUDE TRACE BUFFER + 0 + + + + false + + + + + + PCW_TRACE_BUFFER_FIFO_SIZE + PCW TRACE BUFFER FIFO SIZE + 128 + + + + false + + + + + + PCW_USE_TRACE_DATA_EDGE_DETECTOR + PCW USE TRACE DATA EDGE DETECTOR + 0 + + + + false + + + + + + PCW_TRACE_BUFFER_CLOCK_DELAY + PCW TRACE BUFFER CLOCK DELAY + 12 + + + + false + + + + + + PCW_USE_CROSS_TRIGGER + PCW USE CROSS TRIGGER + 0 + + + PCW_FTM_CTI_IN0 + <Select> + + + + false + + + + + + PCW_FTM_CTI_IN1 + <Select> + + + + false + + + + + + PCW_FTM_CTI_IN2 + <Select> + + + + false + + + + + + PCW_FTM_CTI_IN3 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT0 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT1 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT2 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT3 + <Select> + + + + false + + + + + + PCW_USE_DEBUG + PCW USE DEBUG + 0 + + + PCW_USE_CR_FABRIC + PCW USE CR FABRIC + 1 + + + PCW_USE_AXI_FABRIC_IDLE + PCW USE AXI FABRIC IDLE + Enables idle AXI signal to the PS used to indicate that there are no outstanding AXI transactions in the PL + 0 + + + PCW_USE_DDR_BYPASS + PCW USE DDR BYPASS + Enables DDR urgent/arb signal used to signal a critical memory starvation situation to the DDR arbitration for the four AXI ports of the PS DDR memory controller + 0 + + + PCW_USE_FABRIC_INTERRUPT + PCW USE FABRIC INTERRUPT + 1 + + + PCW_USE_PROC_EVENT_BUS + PCW USE PROC EVENT BUS + 0 + + + PCW_USE_EXPANDED_IOP + PCW USE EXPANDED IOP + 0 + + + PCW_USE_HIGH_OCM + PCW USE HIGH OCM + 0 + + + PCW_USE_PS_SLCR_REGISTERS + PCW USE PS SLCR REGISTERS + 0 + + + PCW_USE_EXPANDED_PS_SLCR_REGISTERS + PCW USE EXPANDED PS SLCR REGISTERS + 0 + + + + false + + + + + + PCW_USE_CORESIGHT + PCW USE CORESIGHT + 0 + + + PCW_EN_EMIO_SRAM_INT + PCW EN EMIO SRAM INT + 0 + + + PCW_GPIO_EMIO_GPIO_WIDTH + PCW EMIO GPIO WIDTH + 64 + + + + false + + + + + + PCW_GP0_NUM_WRITE_THREADS + GP0 NUM WRITE THREADS + 4 + + + PCW_GP0_NUM_READ_THREADS + GP0 NUM READ THREADS + 4 + + + PCW_GP1_NUM_WRITE_THREADS + GP1 NUM WRITE THREADS + 4 + + + PCW_GP1_NUM_READ_THREADS + GP1 NUM READ THREADS + 4 + + + PCW_UART0_BAUD_RATE + PCW UART0 BAUD RATE + Configure baud rate to determine UART0 operating frequency + 115200 + + + + true + + + + + + PCW_UART1_BAUD_RATE + PCW UART1 BAUD RATE + Configure baud rate to determine UART1 operating frequency + 115200 + + + + true + + + + + + PCW_EN_4K_TIMER + PCW EN 4K TIMER + 0 + + + PCW_M_AXI_GP0_ID_WIDTH + PCW M AXI GP0 ID WIDTH + 12 + + + + true + + + + + + PCW_M_AXI_GP0_ENABLE_STATIC_REMAP + PCW M AXI GP0 ENABLE STATIC REMAP + 0 + + + + true + + + + + + PCW_M_AXI_GP0_SUPPORT_NARROW_BURST + PCW M AXI GP0 SUPPORT NARROW BURST + 0 + + + + true + + + + + + PCW_M_AXI_GP0_THREAD_ID_WIDTH + PCW M AXI GP0 THREAD ID WIDTH + 12 + + + + true + + + + + + PCW_M_AXI_GP1_ID_WIDTH + PCW M AXI GP1 ID WIDTH + 12 + + + + false + + + + + + PCW_M_AXI_GP1_ENABLE_STATIC_REMAP + PCW M AXI GP1 ENABLE STATIC REMAP + 0 + + + + false + + + + + + PCW_M_AXI_GP1_SUPPORT_NARROW_BURST + PCW M AXI GP1 SUPPORT NARROW BURST + 0 + + + + false + + + + + + PCW_M_AXI_GP1_THREAD_ID_WIDTH + PCW M AXI GP1 THREAD ID WIDTH + 12 + + + + false + + + + + + PCW_S_AXI_GP0_ID_WIDTH + PCW S AXI GP0 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_GP1_ID_WIDTH + PCW S AXI GP1 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_ACP_ID_WIDTH + PCW S AXI ACP ID WIDTH + 3 + + + + true + + + + + + PCW_INCLUDE_ACP_TRANS_CHECK + PCW INCLUDE ACP TRANS CHECK + 0 + + + PCW_USE_DEFAULT_ACP_USER_VAL + PCW USE DEFAULT ACP USER VAL + 1 + + + + true + + + + + + PCW_S_AXI_ACP_ARUSER_VAL + PCW S AXI ACP ARUSER VAL + 31 + + + + true + + + + + + PCW_S_AXI_ACP_AWUSER_VAL + PCW S AXI ACP AWUSER VAL + 31 + + + + true + + + + + + PCW_S_AXI_HP0_ID_WIDTH + PCW S AXI HP0 ID WIDTH + 6 + + + + true + + + + + + PCW_S_AXI_HP0_DATA_WIDTH + PCW S AXI HP0 DATA WIDTH + 64 + + + + true + + + + + + PCW_S_AXI_HP1_ID_WIDTH + PCW S AXI HP1 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP1_DATA_WIDTH + PCW S AXI HP1 DATA WIDTH + 64 + + + + true + + + + + + PCW_S_AXI_HP2_ID_WIDTH + PCW S AXI HP2 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP2_DATA_WIDTH + PCW S AXI HP2 DATA WIDTH + 64 + + + + true + + + + + + PCW_S_AXI_HP3_ID_WIDTH + PCW S AXI HP3 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP3_DATA_WIDTH + PCW S AXI HP3 DATA WIDTH + 64 + + + + true + + + + + + PCW_NUM_F2P_INTR_INPUTS + PCW NUM F2P INTR INPUTS + 2 + + + + true + + + + + + PCW_EN_DDR + PCW EN DDR + 1 + + + PCW_EN_SMC + PCW EN SMC + 0 + + + PCW_EN_QSPI + PCW EN QSPI + 1 + + + PCW_EN_CAN0 + PCW EN CAN0 + 0 + + + PCW_EN_CAN1 + PCW EN CAN1 + 0 + + + PCW_EN_ENET0 + PCW EN ENET0 + 1 + + + PCW_EN_ENET1 + PCW EN ENET1 + 0 + + + PCW_EN_GPIO + PCW EN GPIO + 1 + + + PCW_EN_I2C0 + PCW EN I2C0 + 1 + + + PCW_EN_I2C1 + PCW EN I2C1 + 1 + + + PCW_EN_PJTAG + PCW EN PJTAG + 0 + + + PCW_EN_SDIO0 + PCW EN SDIO0 + 1 + + + PCW_EN_SDIO1 + PCW EN SDIO1 + 0 + + + PCW_EN_SPI0 + PCW EN SPI0 + 0 + + + PCW_EN_SPI1 + PCW EN SPI1 + 0 + + + PCW_EN_UART0 + PCW EN UART0 + 1 + + + PCW_EN_UART1 + PCW EN UART1 + 1 + + + PCW_EN_MODEM_UART0 + PCW EN MODEM UART0 + 0 + + + PCW_EN_MODEM_UART1 + PCW EN MODEM UART1 + 0 + + + PCW_EN_TTC0 + PCW EN TTC0 + 1 + + + PCW_EN_TTC1 + PCW EN TTC1 + 0 + + + PCW_EN_WDT + PCW EN WDT + 0 + + + PCW_EN_TRACE + PCW EN TRACE + 0 + + + PCW_EN_USB0 + PCW EN USB0 + 1 + + + PCW_EN_USB1 + PCW EN USB1 + 0 + + + PCW_DQ_WIDTH + PCW DQ WIDTH + 32 + + + PCW_DQS_WIDTH + PCW DQS WIDTH + 4 + + + PCW_DM_WIDTH + PCW DM WIDTH + 4 + + + PCW_MIO_PRIMITIVE + PCW MIO PRIMITIVE + 54 + + + PCW_EN_CLK0_PORT + PCW EN CLK0 PORT + 1 + + + + true + + + + + + PCW_EN_CLK1_PORT + PCW EN CLK1 PORT + 1 + + + + true + + + + + + PCW_EN_CLK2_PORT + PCW EN CLK2 PORT + 1 + + + + true + + + + + + PCW_EN_CLK3_PORT + PCW EN CLK3 PORT + 1 + + + + true + + + + + + PCW_EN_RST0_PORT + PCW EN RST0 PORT + Enables general purpose reset signal 0 for PL logic + 1 + + + + true + + + + + + PCW_EN_RST1_PORT + PCW EN RST1 PORT + Enables general purpose reset signal 1 for PL logic + 0 + + + + true + + + + + + PCW_EN_RST2_PORT + PCW EN RST2 PORT + Enables general purpose reset signal 2 for PL logic + 0 + + + + true + + + + + + PCW_EN_RST3_PORT + PCW EN RST3 PORT + Enables general purpose reset signal 3 for PL logic + 0 + + + + true + + + + + + PCW_EN_CLKTRIG0_PORT + PCW EN CLKTRIG0 PORT + Enables PL clock trigger signal 0 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_EN_CLKTRIG1_PORT + PCW EN CLKTRIG1 PORT + Enables PL clock trigger signal 1 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_EN_CLKTRIG2_PORT + PCW EN CLKTRIG2 PORT + Enables PL clock trigger signal 2 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_EN_CLKTRIG3_PORT + PCW EN CLKTRIG3 PORT + Enables PL clock trigger signal 3 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_P2F_DMAC_ABORT_INTR + PCW P2F DMAC ABORT INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC0_INTR + PCW P2F DMAC0 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC1_INTR + PCW P2F DMAC1 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC2_INTR + PCW P2F DMAC2 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC3_INTR + PCW P2F DMAC3 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC4_INTR + PCW P2F DMAC4 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC5_INTR + PCW P2F DMAC5 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC6_INTR + PCW P2F DMAC6 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC7_INTR + PCW P2F DMAC7 INTR + 0 + + + + false + + + + + + PCW_P2F_SMC_INTR + PCW P2F SMC INTR + 0 + + + + false + + + + + + PCW_P2F_QSPI_INTR + PCW P2F QSPI INTR + 0 + + + + true + + + + + + PCW_P2F_CTI_INTR + PCW P2F CTI INTR + 0 + + + + false + + + + + + PCW_P2F_GPIO_INTR + PCW P2F GPIO INTR + 0 + + + + true + + + + + + PCW_P2F_USB0_INTR + PCW P2F USB0 INTR + 0 + + + + true + + + + + + PCW_P2F_ENET0_INTR + PCW P2F ENET0 INTR + 0 + + + + true + + + + + + PCW_P2F_SDIO0_INTR + PCW P2F SDIO0 INTR + 0 + + + + true + + + + + + PCW_P2F_I2C0_INTR + PCW P2F I2C0 INTR + 0 + + + + true + + + + + + PCW_P2F_SPI0_INTR + PCW P2F SPI0 INTR + 0 + + + + false + + + + + + PCW_P2F_UART0_INTR + PCW P2F UART0 INTR + 0 + + + + true + + + + + + PCW_P2F_CAN0_INTR + PCW P2F CAN0 INTR + 0 + + + + false + + + + + + PCW_P2F_USB1_INTR + PCW P2F USB1 INTR + 0 + + + + false + + + + + + PCW_P2F_ENET1_INTR + PCW P2F ENET1 INTR + 0 + + + + false + + + + + + PCW_P2F_SDIO1_INTR + PCW P2F SDIO1 INTR + 0 + + + + false + + + + + + PCW_P2F_I2C1_INTR + PCW P2F I2C1 INTR + 0 + + + + true + + + + + + PCW_P2F_SPI1_INTR + PCW P2F SPI1 INTR + 0 + + + + false + + + + + + PCW_P2F_UART1_INTR + PCW P2F UART1 INTR + 0 + + + + true + + + + + + PCW_P2F_CAN1_INTR + PCW P2F CAN1 INTR + 0 + + + + false + + + + + + PCW_IRQ_F2P_INTR + PCW IRQ F2P INTR + 1 + + + + true + + + + + + PCW_IRQ_F2P_MODE + PCW IRQ F2P MODE + DIRECT + + + + true + + + + + + PCW_CORE0_FIQ_INTR + PCW CORE0 FIQ INTR + 0 + + + + true + + + + + + PCW_CORE0_IRQ_INTR + PCW CORE0 IRQ INTR + 0 + + + + true + + + + + + PCW_CORE1_FIQ_INTR + PCW CORE1 FIQ INTR + 0 + + + + true + + + + + + PCW_CORE1_IRQ_INTR + PCW CORE1 IRQ INTR + 0 + + + + true + + + + + + PCW_VALUE_SILVERSION + PCW VALUE SILVERSION + 3 + + + PCW_GP0_EN_MODIFIABLE_TXN + PCW GP0 EN MODIFIABLE TXN + 1 + + + PCW_GP1_EN_MODIFIABLE_TXN + PCW GP1 EN MODIFIABLE TXN + 1 + + + PCW_IMPORT_BOARD_PRESET + PCW IMPORT BOARD PRESET + None + + + PCW_PERIPHERAL_BOARD_PRESET + PCW PERIPHERAL BOARD PRESET + None + + + PCW_PRESET_BANK0_VOLTAGE + PCW PRESET BANK0 VOLTAGE + LVCMOS 3.3V + + + PCW_PRESET_BANK1_VOLTAGE + PCW PRESET BANK1 VOLTAGE + LVCMOS 1.8V + + + PCW_UIPARAM_DDR_ENABLE + PCW UIPARAM DDR ENABLE + 1 + + + PCW_UIPARAM_DDR_ADV_ENABLE + PCW UIPARAM DDR ADV ENABLE + 0 + + + PCW_UIPARAM_DDR_MEMORY_TYPE + PCW UIPARAM DDR MEMORY TYPE + DDR 3 (Low Voltage) + + + PCW_UIPARAM_DDR_ECC + PCW UIPARAM DDR ECC + Disabled + + + + false + + + + + + PCW_UIPARAM_DDR_BUS_WIDTH + PCW UIPARAM DDR BUS WIDTH + 32 Bit + + + PCW_UIPARAM_DDR_BL + PCW UIPARAM DDR BL + 8 + + + PCW_UIPARAM_DDR_HIGH_TEMP + PCW UIPARAM DDR HIGH TEMP + Normal (0-85) + + + PCW_UIPARAM_DDR_PARTNO + PCW UIPARAM DDR PARTNO + MT41K256M16 RE-125 + + + PCW_UIPARAM_DDR_DRAM_WIDTH + PCW UIPARAM DDR DRAM WIDTH + 16 Bits + + + + false + + + + + + PCW_UIPARAM_DDR_DEVICE_CAPACITY + PCW UIPARAM DDR DEVICE CAPACITY + 4096 MBits + + + + false + + + + + + PCW_UIPARAM_DDR_SPEED_BIN + PCW UIPARAM DDR SPEED BIN + DDR3_1066F + + + + false + + + + + + PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL + PCW UIPARAM DDR TRAIN WRITE LEVEL + 1 + + + PCW_UIPARAM_DDR_TRAIN_READ_GATE + PCW UIPARAM DDR TRAIN READ GATE + 1 + + + PCW_UIPARAM_DDR_TRAIN_DATA_EYE + PCW UIPARAM DDR TRAIN DATA EYE + 1 + + + PCW_UIPARAM_DDR_CLOCK_STOP_EN + PCW UIPARAM DDR CLOCK STOP EN + 0 + + + PCW_UIPARAM_DDR_USE_INTERNAL_VREF + PCW UIPARAM DDR USE INTERNAL VREF + 0 + + + PCW_DDR_PRIORITY_WRITEPORT_0 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_1 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_2 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_3 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_0 + PCW DDR PRIORITY READPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_1 + PCW DDR PRIORITY READPORT 1 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_2 + PCW DDR PRIORITY READPORT 2 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_3 + PCW DDR PRIORITY READPORT 3 + <Select> + + + + false + + + + + + PCW_DDR_PORT0_HPR_ENABLE + PCW DDR PORT0 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT1_HPR_ENABLE + PCW DDR PORT1 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT2_HPR_ENABLE + PCW DDR PORT2 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT3_HPR_ENABLE + PCW DDR PORT3 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_HPRLPR_QUEUE_PARTITION + PCW DDR HPRLPR QUEUE PARTITION + HPR(0)/LPR(32) + + + + false + + + + + + PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR LPR TO CRITICAL PRIORITY LEVEL + 2 + + + + false + + + + + + PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR HPR TO CRITICAL PRIORITY LEVEL + 15 + + + + false + + + + + + PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR WRITE TO CRITICAL PRIORITY LEVEL + 2 + + + + false + + + + + + PCW_NAND_PERIPHERAL_ENABLE + PCW NAND PERIPHERAL ENABLE + 0 + + + + false + + + + + + PCW_NAND_NAND_IO + PCW NAND NAND IO + <Select> + + + + false + + + + + + PCW_NAND_GRP_D8_ENABLE + 0 + + + + false + + + + + + PCW_NAND_GRP_D8_IO + PCW NAND GRP D8 IO + <Select> + + + + false + + + + + + PCW_NOR_PERIPHERAL_ENABLE + PCW NOR PERIPHERAL ENABLE + 0 + + + + false + + + + + + PCW_NOR_NOR_IO + PCW NOR NOR IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_A25_ENABLE + PCW NOR GRP A25 IO + 0 + + + + false + + + + + + PCW_NOR_GRP_A25_IO + PCW NOR GRP CS0 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_CS0_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_CS0_IO + PCW NOR GRP CS1 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS0_ENABLE + PCW NOR GRP SRAM CS0 ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS0_IO + PCW NOR GRP SRAM CS1 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_CS1_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_CS1_IO + PCW NOR GRP SRAM CS0 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS1_ENABLE + PCW NOR GRP SRAM CS1 ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS1_IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_INT_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_INT_IO + <Select> + + + + false + + + + + + PCW_QSPI_PERIPHERAL_ENABLE + PCW QSPI PERIPHERAL ENABLE + 1 + + + PCW_QSPI_QSPI_IO + PCW QSPI QSPI IO + MIO 1 .. 6 + + + PCW_QSPI_GRP_SINGLE_SS_ENABLE + PCW QSPI GRP SINGLE SS ENABLE + 1 + + + PCW_QSPI_GRP_SINGLE_SS_IO + PCW QSPI GRP SINGLE SS IO + MIO 1 .. 6 + + + PCW_QSPI_GRP_SS1_ENABLE + 0 + + + PCW_QSPI_GRP_SS1_IO + PCW QSPI GRP SS1 IO + <Select> + + + + false + + + + + + PCW_SINGLE_QSPI_DATA_MODE + Single QSPI Data Mode + x4 + + + PCW_DUAL_STACK_QSPI_DATA_MODE + Dual Stack QSPI Data Mode + <Select> + + + + false + + + + + + PCW_DUAL_PARALLEL_QSPI_DATA_MODE + Dual Parallel QSPI Data Mode + <Select> + + + + false + + + + + + PCW_QSPI_GRP_IO1_ENABLE + 0 + + + PCW_QSPI_GRP_IO1_IO + PCW QSPI GRP IO1 IO + <Select> + + + + false + + + + + + PCW_QSPI_GRP_FBCLK_ENABLE + 1 + + + PCW_QSPI_GRP_FBCLK_IO + PCW QSPI GRP FBCLK IO + MIO 8 + + + PCW_QSPI_INTERNAL_HIGHADDRESS + PCW QSPI INTERNAL HIGHADDRESS + 0xFCFFFFFF + + + PCW_ENET0_PERIPHERAL_ENABLE + PCW ENET0 PERIPHERAL ENABLE + 1 + + + PCW_ENET0_ENET0_IO + PCW ENET0 ENET0 IO + MIO 16 .. 27 + + + PCW_ENET0_GRP_MDIO_ENABLE + 1 + + + PCW_ENET0_GRP_MDIO_IO + PCW ENET0 GRP MDIO IO + MIO 52 .. 53 + + + PCW_ENET_RESET_ENABLE + 1 + + + PCW_ENET_RESET_SELECT + Share reset pin + + + PCW_ENET0_RESET_ENABLE + 0 + + + PCW_ENET0_RESET_IO + <Select> + + + + false + + + + + + PCW_ENET1_PERIPHERAL_ENABLE + PCW ENET1 PERIPHERAL ENABLE + 0 + + + PCW_ENET1_ENET1_IO + PCW ENET1 ENET1 IO + <Select> + + + + false + + + + + + PCW_ENET1_GRP_MDIO_ENABLE + 0 + + + + false + + + + + + PCW_ENET1_GRP_MDIO_IO + PCW ENET1 GRP MDIO IO + <Select> + + + + false + + + + + + PCW_ENET1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_ENET1_RESET_IO + <Select> + + + + false + + + + + + PCW_SD0_PERIPHERAL_ENABLE + PCW SD0 PERIPHERAL ENABLE + 1 + + + PCW_SD0_SD0_IO + PCW SD0 SD0 IO + MIO 40 .. 45 + + + PCW_SD0_GRP_CD_ENABLE + 1 + + + PCW_SD0_GRP_CD_IO + PCW SD0 GRP CD IO + MIO 47 + + + PCW_SD0_GRP_WP_ENABLE + 1 + + + PCW_SD0_GRP_WP_IO + PCW SD0 GRP WP IO + EMIO + + + PCW_SD0_GRP_POW_ENABLE + 0 + + + PCW_SD0_GRP_POW_IO + PCW SD0 GRP POW IO + <Select> + + + + false + + + + + + PCW_SD1_PERIPHERAL_ENABLE + PCW SD1 PERIPHERAL ENABLE + 0 + + + PCW_SD1_SD1_IO + PCW SD1 SD1 IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_CD_ENABLE + 0 + + + + false + + + + + + PCW_SD1_GRP_CD_IO + PCW SD1 GRP CD IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_WP_ENABLE + 0 + + + + false + + + + + + PCW_SD1_GRP_WP_IO + PCW SD1 GRP WP IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_POW_ENABLE + 0 + + + + false + + + + + + PCW_SD1_GRP_POW_IO + PCW SD1 GRP POW IO + <Select> + + + + false + + + + + + PCW_UART0_PERIPHERAL_ENABLE + PCW UART0 PERIPHERAL ENABLE + 1 + + + PCW_UART0_UART0_IO + PCW UART0 UART0 IO + MIO 10 .. 11 + + + PCW_UART0_GRP_FULL_ENABLE + 0 + + + PCW_UART0_GRP_FULL_IO + <Select> + + + + false + + + + + + PCW_UART1_PERIPHERAL_ENABLE + PCW UART1 PERIPHERAL ENABLE + 1 + + + PCW_UART1_UART1_IO + PCW UART1 UART1 IO + MIO 48 .. 49 + + + PCW_UART1_GRP_FULL_ENABLE + 0 + + + PCW_UART1_GRP_FULL_IO + <Select> + + + + false + + + + + + PCW_SPI0_PERIPHERAL_ENABLE + PCW SPI0 PERIPHERAL ENABLE + 0 + + + PCW_SPI0_SPI0_IO + PCW SPI0 SPI0 IO + <Select> + + + + false + + + + + + PCW_SPI0_GRP_SS0_ENABLE + 0 + + + + false + + + + + + PCW_SPI0_GRP_SS0_IO + PCW SPI0 GRP SS0 IO + <Select> + + + + false + + + + + + PCW_SPI0_GRP_SS1_ENABLE + 0 + + + + false + + + + + + PCW_SPI0_GRP_SS1_IO + PCW SPI0 GRP SS1 IO + <Select> + + + + false + + + + + + PCW_SPI0_GRP_SS2_ENABLE + 0 + + + + false + + + + + + PCW_SPI0_GRP_SS2_IO + PCW SPI0 GRP SS2 IO + <Select> + + + + false + + + + + + PCW_SPI1_PERIPHERAL_ENABLE + PCW SPI1 PERIPHERAL ENABLE + 0 + + + PCW_SPI1_SPI1_IO + PCW SPI1 SPI1 IO + <Select> + + + + false + + + + + + PCW_SPI1_GRP_SS0_ENABLE + 0 + + + + false + + + + + + PCW_SPI1_GRP_SS0_IO + PCW SPI1 GRP SS0 IO + <Select> + + + + false + + + + + + PCW_SPI1_GRP_SS1_ENABLE + 0 + + + + false + + + + + + PCW_SPI1_GRP_SS1_IO + PCW SPI1 GRP SS1 IO + <Select> + + + + false + + + + + + PCW_SPI1_GRP_SS2_ENABLE + 0 + + + + false + + + + + + PCW_SPI1_GRP_SS2_IO + PCW SPI1 GRP SS2 IO + <Select> + + + + false + + + + + + PCW_CAN0_PERIPHERAL_ENABLE + PCW CAN0 PERIPHERAL ENABLE + 0 + + + PCW_CAN0_CAN0_IO + PCW CAN0 CAN0 IO + <Select> + + + + false + + + + + + PCW_CAN0_GRP_CLK_ENABLE + 0 + + + + false + + + + + + PCW_CAN0_GRP_CLK_IO + PCW CAN0 GRP CLK IO + <Select> + + + + false + + + + + + PCW_CAN1_PERIPHERAL_ENABLE + PCW CAN1 PERIPHERAL ENABLE + 0 + + + PCW_CAN1_CAN1_IO + PCW CAN1 CAN1 IO + <Select> + + + + false + + + + + + PCW_CAN1_GRP_CLK_ENABLE + 0 + + + + false + + + + + + PCW_CAN1_GRP_CLK_IO + PCW CAN1 GRP CLK IO + <Select> + + + + false + + + + + + PCW_TRACE_PERIPHERAL_ENABLE + PCW TRACE PERIPHERAL ENABLE + 0 + + + PCW_TRACE_TRACE_IO + PCW TRACE TRACE IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_2BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_2BIT_IO + PCW TRACE GRP 2BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_4BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_4BIT_IO + PCW TRACE GRP 4BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_8BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_8BIT_IO + PCW TRACE GRP 8BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_16BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_16BIT_IO + PCW TRACE GRP 16BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_32BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_32BIT_IO + PCW TRACE GRP 32BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_INTERNAL_WIDTH + PCW TRACE INTERNAL WIDTH + 2 + + + PCW_WDT_PERIPHERAL_ENABLE + PCW WDT PERIPHERAL ENABLE + 0 + + + PCW_WDT_WDT_IO + PCW WDT WDT IO + <Select> + + + + false + + + + + + PCW_TTC0_PERIPHERAL_ENABLE + PCW TTC0 PERIPHERAL ENABLE + 1 + + + PCW_TTC0_TTC0_IO + PCW TTC0 TTC0 IO + EMIO + + + PCW_TTC1_PERIPHERAL_ENABLE + PCW TTC1 PERIPHERAL ENABLE + 0 + + + PCW_TTC1_TTC1_IO + PCW TTC1 TTC1 IO + <Select> + + + + false + + + + + + PCW_PJTAG_PERIPHERAL_ENABLE + PCW PJTAG PERIPHERAL ENABLE + 0 + + + PCW_PJTAG_PJTAG_IO + PCW PJTAG PJTAG IO + <Select> + + + + false + + + + + + PCW_USB0_PERIPHERAL_ENABLE + PCW USB0 PERIPHERAL ENABLE + 1 + + + PCW_USB0_USB0_IO + PCW USB0 USB0 IO + MIO 28 .. 39 + + + PCW_USB_RESET_ENABLE + 1 + + + PCW_USB_RESET_SELECT + Share reset pin + + + PCW_USB0_RESET_ENABLE + 1 + + + PCW_USB0_RESET_IO + MIO 46 + + + PCW_USB1_PERIPHERAL_ENABLE + PCW USB1 PERIPHERAL ENABLE + 0 + + + PCW_USB1_USB1_IO + PCW USB1 USB1 IO + <Select> + + + + false + + + + + + PCW_USB1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_USB1_RESET_IO + <Select> + + + + false + + + + + + PCW_I2C0_PERIPHERAL_ENABLE + PCW I2C0 PERIPHERAL ENABLE + 1 + + + PCW_I2C0_I2C0_IO + PCW I2C0 I2C0 IO + MIO 14 .. 15 + + + PCW_I2C0_GRP_INT_ENABLE + 0 + + + PCW_I2C0_GRP_INT_IO + PCW I2C0 GRP INT IO + <Select> + + + + false + + + + + + PCW_I2C0_RESET_ENABLE + 0 + + + PCW_I2C0_RESET_IO + <Select> + + + + false + + + + + + PCW_I2C1_PERIPHERAL_ENABLE + PCW I2C1 PERIPHERAL ENABLE + 1 + + + PCW_I2C1_I2C1_IO + PCW I2C1 I2C1 IO + MIO 12 .. 13 + + + PCW_I2C1_GRP_INT_ENABLE + 0 + + + PCW_I2C1_GRP_INT_IO + PCW I2C1 GRP INT IO + <Select> + + + + false + + + + + + PCW_I2C_RESET_ENABLE + 1 + + + PCW_I2C_RESET_SELECT + Share reset pin + + + PCW_I2C1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_I2C1_RESET_IO + <Select> + + + + false + + + + + + PCW_GPIO_PERIPHERAL_ENABLE + PCW GPIO PERIPHERAL ENABLE + 0 + + + PCW_GPIO_MIO_GPIO_ENABLE + 1 + + + PCW_GPIO_MIO_GPIO_IO + PCW GPIO MIO GPIO IO + MIO + + + PCW_GPIO_EMIO_GPIO_ENABLE + PCW GPIO EMIO GPIO ENABLE + 0 + + + PCW_GPIO_EMIO_GPIO_IO + PCW GPIO EMIO GPIO IO + <Select> + + + + false + + + + + + PCW_APU_CLK_RATIO_ENABLE + PCW APU CLK RATIO ENABLE + 6:2:1 + + + PCW_ENET0_PERIPHERAL_FREQMHZ + PCW ENET0 PERIPHERAL FREQMHZ + 1000 Mbps + + + PCW_ENET1_PERIPHERAL_FREQMHZ + PCW ENET1 PERIPHERAL FREQMHZ + 1000 Mbps + + + + false + + + + + + PCW_CPU_PERIPHERAL_CLKSRC + PCW CPU PERIPHERAL CLKSRC + ARM PLL + + + PCW_DDR_PERIPHERAL_CLKSRC + PCW DDR PERIPHERAL CLKSRC + DDR PLL + + + PCW_SMC_PERIPHERAL_CLKSRC + PCW SMC PERIPHERAL CLKSRC + IO PLL + + + PCW_QSPI_PERIPHERAL_CLKSRC + PCW QSPI PERIPHERAL CLKSRC + IO PLL + + + PCW_SDIO_PERIPHERAL_CLKSRC + PCW SDIO PERIPHERAL CLKSRC + IO PLL + + + PCW_UART_PERIPHERAL_CLKSRC + PCW UART PERIPHERAL CLKSRC + IO PLL + + + PCW_SPI_PERIPHERAL_CLKSRC + PCW SPI PERIPHERAL CLKSRC + IO PLL + + + PCW_CAN_PERIPHERAL_CLKSRC + PCW CAN PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK0_PERIPHERAL_CLKSRC + PCW FCLK0 PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK1_PERIPHERAL_CLKSRC + PCW FCLK1 PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK2_PERIPHERAL_CLKSRC + PCW FCLK2 PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK3_PERIPHERAL_CLKSRC + PCW FCLK3 PERIPHERAL CLKSRC + IO PLL + + + PCW_ENET0_PERIPHERAL_CLKSRC + PCW ENET0 PERIPHERAL CLKSRC + IO PLL + + + PCW_ENET1_PERIPHERAL_CLKSRC + PCW ENET1 PERIPHERAL CLKSRC + IO PLL + + + PCW_CAN0_PERIPHERAL_CLKSRC + PCW CAN0 PERIPHERAL CLKSRC + External + + + PCW_CAN1_PERIPHERAL_CLKSRC + PCW CAN1 PERIPHERAL CLKSRC + External + + + PCW_TPIU_PERIPHERAL_CLKSRC + PCW TPIU PERIPHERAL CLKSRC + External + + + PCW_TTC0_CLK0_PERIPHERAL_CLKSRC + PCW TTC0 CLK0 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC0_CLK1_PERIPHERAL_CLKSRC + PCW TTC0 CLK1 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC0_CLK2_PERIPHERAL_CLKSRC + PCW TTC0 CLK2 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC1_CLK0_PERIPHERAL_CLKSRC + PCW TTC1 CLK0 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC1_CLK1_PERIPHERAL_CLKSRC + PCW TTC1 CLK1 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC1_CLK2_PERIPHERAL_CLKSRC + PCW TTC1 CLK2 PERIPHERAL CLKSRC + CPU_1X + + + PCW_WDT_PERIPHERAL_CLKSRC + PCW WDT PERIPHERAL CLKSRC + CPU_1X + + + PCW_DCI_PERIPHERAL_CLKSRC + PCW DCI PERIPHERAL CLKSRC + DDR PLL + + + PCW_PCAP_PERIPHERAL_CLKSRC + PCW PCAP PERIPHERAL CLKSRC + IO PLL + + + PCW_USB_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + PCW_ENET_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + PCW_I2C_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + PCW_MIO_0_PULLUP + PCW MIO 0 PULLUP + enabled + + + PCW_MIO_0_IOTYPE + PCW MIO 0 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_0_DIRECTION + PCW MIO 0 DIRECTION + inout + + + + false + + + + + + PCW_MIO_0_SLEW + PCW MIO 0 SLEW + slow + + + PCW_MIO_1_PULLUP + PCW MIO 1 PULLUP + enabled + + + PCW_MIO_1_IOTYPE + PCW MIO 1 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_1_DIRECTION + PCW MIO 1 DIRECTION + out + + + + false + + + + + + PCW_MIO_1_SLEW + PCW MIO 1 SLEW + slow + + + PCW_MIO_2_PULLUP + PCW MIO 2 PULLUP + disabled + + + + false + + + + + + PCW_MIO_2_IOTYPE + PCW MIO 2 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_2_DIRECTION + PCW MIO 2 DIRECTION + inout + + + + false + + + + + + PCW_MIO_2_SLEW + PCW MIO 2 SLEW + slow + + + PCW_MIO_3_PULLUP + PCW MIO 3 PULLUP + disabled + + + + false + + + + + + PCW_MIO_3_IOTYPE + PCW MIO 3 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_3_DIRECTION + PCW MIO 3 DIRECTION + inout + + + + false + + + + + + PCW_MIO_3_SLEW + PCW MIO 3 SLEW + slow + + + PCW_MIO_4_PULLUP + PCW MIO 4 PULLUP + disabled + + + + false + + + + + + PCW_MIO_4_IOTYPE + PCW MIO 4 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_4_DIRECTION + PCW MIO 4 DIRECTION + inout + + + + false + + + + + + PCW_MIO_4_SLEW + PCW MIO 4 SLEW + slow + + + PCW_MIO_5_PULLUP + PCW MIO 5 PULLUP + disabled + + + + false + + + + + + PCW_MIO_5_IOTYPE + PCW MIO 5 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_5_DIRECTION + PCW MIO 5 DIRECTION + inout + + + + false + + + + + + PCW_MIO_5_SLEW + PCW MIO 5 SLEW + slow + + + PCW_MIO_6_PULLUP + PCW MIO 6 PULLUP + disabled + + + + false + + + + + + PCW_MIO_6_IOTYPE + PCW MIO 6 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_6_DIRECTION + PCW MIO 6 DIRECTION + out + + + + false + + + + + + PCW_MIO_6_SLEW + PCW MIO 6 SLEW + slow + + + PCW_MIO_7_PULLUP + PCW MIO 7 PULLUP + disabled + + + + false + + + + + + PCW_MIO_7_IOTYPE + PCW MIO 7 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_7_DIRECTION + PCW MIO 7 DIRECTION + out + + + + false + + + + + + PCW_MIO_7_SLEW + PCW MIO 7 SLEW + slow + + + PCW_MIO_8_PULLUP + PCW MIO 8 PULLUP + disabled + + + + false + + + + + + PCW_MIO_8_IOTYPE + PCW MIO 8 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_8_DIRECTION + PCW MIO 8 DIRECTION + out + + + + false + + + + + + PCW_MIO_8_SLEW + PCW MIO 8 SLEW + slow + + + PCW_MIO_9_PULLUP + PCW MIO 9 PULLUP + enabled + + + PCW_MIO_9_IOTYPE + PCW MIO 9 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_9_DIRECTION + PCW MIO 9 DIRECTION + inout + + + + false + + + + + + PCW_MIO_9_SLEW + PCW MIO 9 SLEW + slow + + + PCW_MIO_10_PULLUP + PCW MIO 10 PULLUP + enabled + + + PCW_MIO_10_IOTYPE + PCW MIO 10 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_10_DIRECTION + PCW MIO 10 DIRECTION + in + + + + false + + + + + + PCW_MIO_10_SLEW + PCW MIO 10 SLEW + slow + + + PCW_MIO_11_PULLUP + PCW MIO 11 PULLUP + enabled + + + PCW_MIO_11_IOTYPE + PCW MIO 11 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_11_DIRECTION + PCW MIO 11 DIRECTION + out + + + + false + + + + + + PCW_MIO_11_SLEW + PCW MIO 11 SLEW + slow + + + PCW_MIO_12_PULLUP + PCW MIO 12 PULLUP + enabled + + + PCW_MIO_12_IOTYPE + PCW MIO 12 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_12_DIRECTION + PCW MIO 12 DIRECTION + inout + + + + false + + + + + + PCW_MIO_12_SLEW + PCW MIO 12 SLEW + slow + + + PCW_MIO_13_PULLUP + PCW MIO 13 PULLUP + enabled + + + PCW_MIO_13_IOTYPE + PCW MIO 13 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_13_DIRECTION + PCW MIO 13 DIRECTION + inout + + + + false + + + + + + PCW_MIO_13_SLEW + PCW MIO 13 SLEW + slow + + + PCW_MIO_14_PULLUP + PCW MIO 14 PULLUP + enabled + + + PCW_MIO_14_IOTYPE + PCW MIO 14 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_14_DIRECTION + PCW MIO 14 DIRECTION + inout + + + + false + + + + + + PCW_MIO_14_SLEW + PCW MIO 14 SLEW + slow + + + PCW_MIO_15_PULLUP + PCW MIO 15 PULLUP + enabled + + + PCW_MIO_15_IOTYPE + PCW MIO 15 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_15_DIRECTION + PCW MIO 15 DIRECTION + inout + + + + false + + + + + + PCW_MIO_15_SLEW + PCW MIO 15 SLEW + slow + + + PCW_MIO_16_PULLUP + PCW MIO 16 PULLUP + enabled + + + PCW_MIO_16_IOTYPE + PCW MIO 16 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_16_DIRECTION + PCW MIO 16 DIRECTION + out + + + + false + + + + + + PCW_MIO_16_SLEW + PCW MIO 16 SLEW + fast + + + PCW_MIO_17_PULLUP + PCW MIO 17 PULLUP + enabled + + + PCW_MIO_17_IOTYPE + PCW MIO 17 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_17_DIRECTION + PCW MIO 17 DIRECTION + out + + + + false + + + + + + PCW_MIO_17_SLEW + PCW MIO 17 SLEW + fast + + + PCW_MIO_18_PULLUP + PCW MIO 18 PULLUP + enabled + + + PCW_MIO_18_IOTYPE + PCW MIO 18 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_18_DIRECTION + PCW MIO 18 DIRECTION + out + + + + false + + + + + + PCW_MIO_18_SLEW + PCW MIO 18 SLEW + fast + + + PCW_MIO_19_PULLUP + PCW MIO 19 PULLUP + enabled + + + PCW_MIO_19_IOTYPE + PCW MIO 19 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_19_DIRECTION + PCW MIO 19 DIRECTION + out + + + + false + + + + + + PCW_MIO_19_SLEW + PCW MIO 19 SLEW + fast + + + PCW_MIO_20_PULLUP + PCW MIO 20 PULLUP + enabled + + + PCW_MIO_20_IOTYPE + PCW MIO 20 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_20_DIRECTION + PCW MIO 20 DIRECTION + out + + + + false + + + + + + PCW_MIO_20_SLEW + PCW MIO 20 SLEW + fast + + + PCW_MIO_21_PULLUP + PCW MIO 21 PULLUP + enabled + + + PCW_MIO_21_IOTYPE + PCW MIO 21 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_21_DIRECTION + PCW MIO 21 DIRECTION + out + + + + false + + + + + + PCW_MIO_21_SLEW + PCW MIO 21 SLEW + fast + + + PCW_MIO_22_PULLUP + PCW MIO 22 PULLUP + enabled + + + PCW_MIO_22_IOTYPE + PCW MIO 22 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_22_DIRECTION + PCW MIO 22 DIRECTION + in + + + + false + + + + + + PCW_MIO_22_SLEW + PCW MIO 22 SLEW + fast + + + PCW_MIO_23_PULLUP + PCW MIO 23 PULLUP + enabled + + + PCW_MIO_23_IOTYPE + PCW MIO 23 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_23_DIRECTION + PCW MIO 23 DIRECTION + in + + + + false + + + + + + PCW_MIO_23_SLEW + PCW MIO 23 SLEW + fast + + + PCW_MIO_24_PULLUP + PCW MIO 24 PULLUP + enabled + + + PCW_MIO_24_IOTYPE + PCW MIO 24 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_24_DIRECTION + PCW MIO 24 DIRECTION + in + + + + false + + + + + + PCW_MIO_24_SLEW + PCW MIO 24 SLEW + fast + + + PCW_MIO_25_PULLUP + PCW MIO 25 PULLUP + enabled + + + PCW_MIO_25_IOTYPE + PCW MIO 25 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_25_DIRECTION + PCW MIO 25 DIRECTION + in + + + + false + + + + + + PCW_MIO_25_SLEW + PCW MIO 25 SLEW + fast + + + PCW_MIO_26_PULLUP + PCW MIO 26 PULLUP + enabled + + + PCW_MIO_26_IOTYPE + PCW MIO 26 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_26_DIRECTION + PCW MIO 26 DIRECTION + in + + + + false + + + + + + PCW_MIO_26_SLEW + PCW MIO 26 SLEW + fast + + + PCW_MIO_27_PULLUP + PCW MIO 27 PULLUP + enabled + + + PCW_MIO_27_IOTYPE + PCW MIO 27 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_27_DIRECTION + PCW MIO 27 DIRECTION + in + + + + false + + + + + + PCW_MIO_27_SLEW + PCW MIO 27 SLEW + fast + + + PCW_MIO_28_PULLUP + PCW MIO 28 PULLUP + enabled + + + PCW_MIO_28_IOTYPE + PCW MIO 28 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_28_DIRECTION + PCW MIO 28 DIRECTION + inout + + + + false + + + + + + PCW_MIO_28_SLEW + PCW MIO 28 SLEW + fast + + + PCW_MIO_29_PULLUP + PCW MIO 29 PULLUP + enabled + + + PCW_MIO_29_IOTYPE + PCW MIO 29 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_29_DIRECTION + PCW MIO 29 DIRECTION + in + + + + false + + + + + + PCW_MIO_29_SLEW + PCW MIO 29 SLEW + fast + + + PCW_MIO_30_PULLUP + PCW MIO 30 PULLUP + enabled + + + PCW_MIO_30_IOTYPE + PCW MIO 30 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_30_DIRECTION + PCW MIO 30 DIRECTION + out + + + + false + + + + + + PCW_MIO_30_SLEW + PCW MIO 30 SLEW + fast + + + PCW_MIO_31_PULLUP + PCW MIO 31 PULLUP + enabled + + + PCW_MIO_31_IOTYPE + PCW MIO 31 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_31_DIRECTION + PCW MIO 31 DIRECTION + in + + + + false + + + + + + PCW_MIO_31_SLEW + PCW MIO 31 SLEW + fast + + + PCW_MIO_32_PULLUP + PCW MIO 32 PULLUP + enabled + + + PCW_MIO_32_IOTYPE + PCW MIO 32 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_32_DIRECTION + PCW MIO 32 DIRECTION + inout + + + + false + + + + + + PCW_MIO_32_SLEW + PCW MIO 32 SLEW + fast + + + PCW_MIO_33_PULLUP + PCW MIO 33 PULLUP + enabled + + + PCW_MIO_33_IOTYPE + PCW MIO 33 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_33_DIRECTION + PCW MIO 33 DIRECTION + inout + + + + false + + + + + + PCW_MIO_33_SLEW + PCW MIO 33 SLEW + fast + + + PCW_MIO_34_PULLUP + PCW MIO 34 PULLUP + enabled + + + PCW_MIO_34_IOTYPE + PCW MIO 34 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_34_DIRECTION + PCW MIO 34 DIRECTION + inout + + + + false + + + + + + PCW_MIO_34_SLEW + PCW MIO 34 SLEW + fast + + + PCW_MIO_35_PULLUP + PCW MIO 35 PULLUP + enabled + + + PCW_MIO_35_IOTYPE + PCW MIO 35 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_35_DIRECTION + PCW MIO 35 DIRECTION + inout + + + + false + + + + + + PCW_MIO_35_SLEW + PCW MIO 35 SLEW + fast + + + PCW_MIO_36_PULLUP + PCW MIO 36 PULLUP + enabled + + + PCW_MIO_36_IOTYPE + PCW MIO 36 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_36_DIRECTION + PCW MIO 36 DIRECTION + in + + + + false + + + + + + PCW_MIO_36_SLEW + PCW MIO 36 SLEW + fast + + + PCW_MIO_37_PULLUP + PCW MIO 37 PULLUP + enabled + + + PCW_MIO_37_IOTYPE + PCW MIO 37 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_37_DIRECTION + PCW MIO 37 DIRECTION + inout + + + + false + + + + + + PCW_MIO_37_SLEW + PCW MIO 37 SLEW + fast + + + PCW_MIO_38_PULLUP + PCW MIO 38 PULLUP + enabled + + + PCW_MIO_38_IOTYPE + PCW MIO 38 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_38_DIRECTION + PCW MIO 38 DIRECTION + inout + + + + false + + + + + + PCW_MIO_38_SLEW + PCW MIO 38 SLEW + fast + + + PCW_MIO_39_PULLUP + PCW MIO 39 PULLUP + enabled + + + PCW_MIO_39_IOTYPE + PCW MIO 39 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_39_DIRECTION + PCW MIO 39 DIRECTION + inout + + + + false + + + + + + PCW_MIO_39_SLEW + PCW MIO 39 SLEW + fast + + + PCW_MIO_40_PULLUP + PCW MIO 40 PULLUP + enabled + + + PCW_MIO_40_IOTYPE + PCW MIO 40 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_40_DIRECTION + PCW MIO 40 DIRECTION + inout + + + + false + + + + + + PCW_MIO_40_SLEW + PCW MIO 40 SLEW + slow + + + PCW_MIO_41_PULLUP + PCW MIO 41 PULLUP + enabled + + + PCW_MIO_41_IOTYPE + PCW MIO 41 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_41_DIRECTION + PCW MIO 41 DIRECTION + inout + + + + false + + + + + + PCW_MIO_41_SLEW + PCW MIO 41 SLEW + slow + + + PCW_MIO_42_PULLUP + PCW MIO 42 PULLUP + enabled + + + PCW_MIO_42_IOTYPE + PCW MIO 42 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_42_DIRECTION + PCW MIO 42 DIRECTION + inout + + + + false + + + + + + PCW_MIO_42_SLEW + PCW MIO 42 SLEW + slow + + + PCW_MIO_43_PULLUP + PCW MIO 43 PULLUP + enabled + + + PCW_MIO_43_IOTYPE + PCW MIO 43 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_43_DIRECTION + PCW MIO 43 DIRECTION + inout + + + + false + + + + + + PCW_MIO_43_SLEW + PCW MIO 43 SLEW + slow + + + PCW_MIO_44_PULLUP + PCW MIO 44 PULLUP + enabled + + + PCW_MIO_44_IOTYPE + PCW MIO 44 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_44_DIRECTION + PCW MIO 44 DIRECTION + inout + + + + false + + + + + + PCW_MIO_44_SLEW + PCW MIO 44 SLEW + slow + + + PCW_MIO_45_PULLUP + PCW MIO 45 PULLUP + enabled + + + PCW_MIO_45_IOTYPE + PCW MIO 45 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_45_DIRECTION + PCW MIO 45 DIRECTION + inout + + + + false + + + + + + PCW_MIO_45_SLEW + PCW MIO 45 SLEW + slow + + + PCW_MIO_46_PULLUP + PCW MIO 46 PULLUP + enabled + + + PCW_MIO_46_IOTYPE + PCW MIO 46 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_46_DIRECTION + PCW MIO 46 DIRECTION + out + + + + false + + + + + + PCW_MIO_46_SLEW + PCW MIO 46 SLEW + slow + + + PCW_MIO_47_PULLUP + PCW MIO 47 PULLUP + enabled + + + PCW_MIO_47_IOTYPE + PCW MIO 47 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_47_DIRECTION + PCW MIO 47 DIRECTION + in + + + + false + + + + + + PCW_MIO_47_SLEW + PCW MIO 47 SLEW + slow + + + PCW_MIO_48_PULLUP + PCW MIO 48 PULLUP + enabled + + + PCW_MIO_48_IOTYPE + PCW MIO 48 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_48_DIRECTION + PCW MIO 48 DIRECTION + out + + + + false + + + + + + PCW_MIO_48_SLEW + PCW MIO 48 SLEW + slow + + + PCW_MIO_49_PULLUP + PCW MIO 49 PULLUP + enabled + + + PCW_MIO_49_IOTYPE + PCW MIO 49 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_49_DIRECTION + PCW MIO 49 DIRECTION + in + + + + false + + + + + + PCW_MIO_49_SLEW + PCW MIO 49 SLEW + slow + + + PCW_MIO_50_PULLUP + PCW MIO 50 PULLUP + enabled + + + PCW_MIO_50_IOTYPE + PCW MIO 50 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_50_DIRECTION + PCW MIO 50 DIRECTION + inout + + + + false + + + + + + PCW_MIO_50_SLEW + PCW MIO 50 SLEW + slow + + + PCW_MIO_51_PULLUP + PCW MIO 51 PULLUP + enabled + + + PCW_MIO_51_IOTYPE + PCW MIO 51 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_51_DIRECTION + PCW MIO 51 DIRECTION + inout + + + + false + + + + + + PCW_MIO_51_SLEW + PCW MIO 51 SLEW + slow + + + PCW_MIO_52_PULLUP + PCW MIO 52 PULLUP + enabled + + + PCW_MIO_52_IOTYPE + PCW MIO 52 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_52_DIRECTION + PCW MIO 52 DIRECTION + out + + + + false + + + + + + PCW_MIO_52_SLEW + PCW MIO 52 SLEW + slow + + + PCW_MIO_53_PULLUP + PCW MIO 53 PULLUP + enabled + + + PCW_MIO_53_IOTYPE + PCW MIO 53 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_53_DIRECTION + PCW MIO 53 DIRECTION + inout + + + + false + + + + + + PCW_MIO_53_SLEW + PCW MIO 53 SLEW + slow + + + preset + preset + None + + + PCW_UIPARAM_GENERATE_SUMMARY + PCW UIPARAM GENERATE SUMMARY + NA + + + PCW_MIO_TREE_PERIPHERALS + PCW MIO TREE PERIPHERALS + GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#UART 0#UART 0#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0 + + + PCW_MIO_TREE_SIGNALS + PCW MIO TREE SIGNALS + gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#rx#tx#scl#sda#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio + + + PCW_PS7_SI_REV + PCW PS7 SI REV + PRODUCTION + + + PCW_FPGA_FCLK0_ENABLE + PCW FPGA FCLK0 ENABLE + 1 + + + + true + + + + + + PCW_FPGA_FCLK1_ENABLE + PCW FPGA FCLK1 ENABLE + 1 + + + + true + + + + + + PCW_FPGA_FCLK2_ENABLE + PCW FPGA FCLK2 ENABLE + 1 + + + + true + + + + + + PCW_FPGA_FCLK3_ENABLE + PCW FPGA FCLK3 ENABLE + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS0_T_TR + PCW NOR SRAM CS0 T TR + 1 + + + PCW_NOR_SRAM_CS0_T_PC + PCW NOR SRAM CS0 T PC + 1 + + + PCW_NOR_SRAM_CS0_T_WP + PCW NOR SRAM CS0 T WP + 1 + + + PCW_NOR_SRAM_CS0_T_CEOE + PCW NOR SRAM CS0 T CEOE + 1 + + + PCW_NOR_SRAM_CS0_T_WC + PCW NOR SRAM CS0 T WC + 11 + + + PCW_NOR_SRAM_CS0_T_RC + PCW NOR SRAM CS0 T RC + 11 + + + PCW_NOR_SRAM_CS0_WE_TIME + PCW NOR SRAM CS0 WE TIME + 0 + + + PCW_NOR_SRAM_CS1_T_TR + PCW NOR SRAM CS1 T TR + 1 + + + PCW_NOR_SRAM_CS1_T_PC + PCW NOR SRAM CS1 T PC + 1 + + + PCW_NOR_SRAM_CS1_T_WP + PCW NOR SRAM CS1 T WP + 1 + + + PCW_NOR_SRAM_CS1_T_CEOE + PCW NOR SRAM CS1 T CEOE + 1 + + + PCW_NOR_SRAM_CS1_T_WC + PCW NOR SRAM CS1 T WC + 11 + + + PCW_NOR_SRAM_CS1_T_RC + PCW NOR SRAM CS1 T RC + 11 + + + PCW_NOR_SRAM_CS1_WE_TIME + PCW NOR SRAM CS1 WE TIME + 0 + + + PCW_NOR_CS0_T_TR + PCW NOR CS0 T TR + 1 + + + PCW_NOR_CS0_T_PC + PCW NOR CS0 T PC + 1 + + + PCW_NOR_CS0_T_WP + PCW NOR CS0 T WP + 1 + + + PCW_NOR_CS0_T_CEOE + PCW NOR CS0 T CEOE + 1 + + + PCW_NOR_CS0_T_WC + PCW NOR CS0 T WC + 11 + + + PCW_NOR_CS0_T_RC + PCW NOR CS0 T RC + 11 + + + PCW_NOR_CS0_WE_TIME + PCW NOR CS0 WE TIME + 0 + + + PCW_NOR_CS1_T_TR + PCW NOR CS1 T TR + 1 + + + PCW_NOR_CS1_T_PC + PCW NOR CS1 T PC + 1 + + + PCW_NOR_CS1_T_WP + PCW NOR CS1 T WP + 1 + + + PCW_NOR_CS1_T_CEOE + PCW NOR CS1 T CEOE + 1 + + + PCW_NOR_CS1_T_WC + PCW NOR CS1 T WC + 11 + + + PCW_NOR_CS1_T_RC + PCW NOR CS1 T RC + 11 + + + PCW_NOR_CS1_WE_TIME + PCW NOR CS1 WE TIME + 0 + + + PCW_NAND_CYCLES_T_RR + PCW NAND CYCLES T RR + 1 + + + PCW_NAND_CYCLES_T_AR + PCW NAND CYCLES T AR + 1 + + + PCW_NAND_CYCLES_T_CLR + PCW NAND CYCLES T CLR + 1 + + + PCW_NAND_CYCLES_T_WP + PCW NAND CYCLES T WP + 1 + + + PCW_NAND_CYCLES_T_REA + PCW NAND CYCLES T REA + 1 + + + PCW_NAND_CYCLES_T_WC + PCW NAND CYCLES T WC + 11 + + + PCW_NAND_CYCLES_T_RC + PCW NAND CYCLES T RC + 11 + + + PCW_SMC_CYCLE_T0 + PCW SMC CYCLE T0 + NA + + + PCW_SMC_CYCLE_T1 + PCW SMC CYCLE T1 + NA + + + PCW_SMC_CYCLE_T2 + PCW SMC CYCLE T2 + NA + + + PCW_SMC_CYCLE_T3 + PCW SMC CYCLE T3 + NA + + + PCW_SMC_CYCLE_T4 + PCW SMC CYCLE T4 + NA + + + PCW_SMC_CYCLE_T5 + PCW SMC CYCLE T5 + NA + + + PCW_SMC_CYCLE_T6 + PCW SMC CYCLE T6 + NA + + + PCW_PACKAGE_NAME + PCW PACKAGE NAME + clg400 + + + PCW_PLL_BYPASSMODE_ENABLE + PCW PLL BYPASSMODE ENABLE + 0 + + + Component_Name + design_3_processing_system7_0_0 + + + + + ZYNQ7 Processing System + + remote_port_c_v4 + remote_port_sc_v4 + xtlm + + 6 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v new file mode 100644 index 0000000..0715556 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v @@ -0,0 +1,3934 @@ + +//----------------------------------------------------------------------------- +// processing_system7 +// processor sub system wrapper +//----------------------------------------------------------------------------- +// +// ************************************************************************ +// ** DISCLAIMER OF LIABILITY ** +// ** ** +// ** This file contains proprietary and confidential information of ** +// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +// ** from Xilinx, and may be used, copied and/or diSCLosed only ** +// ** pursuant to the terms of a valid license agreement with Xilinx. ** +// ** ** +// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +// ** does not warrant that functions included in the Materials will ** +// ** meet the requirements of Licensee, or that the operation of the ** +// ** Materials will be uninterrupted or error-free, or that defects ** +// ** in the Materials will be corrected. Furthermore, Xilinx does ** +// ** not warrant or make any representations regarding use, or the ** +// ** results of the use, of the Materials in terms of correctness, ** +// ** accuracy, reliability or otherwise. ** +// ** ** +// ** Xilinx products are not designed or intended to be fail-safe, ** +// ** or for use in any application requiring fail-safe performance, ** +// ** such as life-support or safety devices or systems, Class III ** +// ** medical devices, nuclear facilities, applications related to ** +// ** the deployment of airbags, or any other applications that could ** +// ** lead to death, personal injury or severe property or ** +// ** environmental damage (individually and collectively, "critical ** +// ** applications"). Customer assumes the sole risk and liability ** +// ** of any use of Xilinx products in critical applications, ** +// ** subject only to applicable laws and regulations governing ** +// ** limitations on product liability. ** +// ** ** +// ** Copyright 2010 Xilinx, Inc. ** +// ** All rights reserved. ** +// ** ** +// ** This disclaimer and copyright notice must be retained as part ** +// ** of this file at all times. ** +// ************************************************************************ +// +//----------------------------------------------------------------------------- +// Filename: processing_system7_v5_5_processing_system7.v +// Version: v1.00.a +// Description: This is the wrapper file for PSS. +//----------------------------------------------------------------------------- +// Structure: This section shows the hierarchical structure of +// pss_wrapper. +// +// --processing_system7_v5_5_processing_system7.v +// --PS7.v - Unisim component +//----------------------------------------------------------------------------- +// Author: SD +// +// History: +// +// SD 09/20/11 -- First version +// ~~~~~~ +// Created the first version v2.00.a +// ^^^^^^ +//------------------------------------------------------------------------------ +// ^^^^^^ +// SR 11/25/11 -- v3.00.a version +// ~~~~~~~ +// Key changes are +// 1. Changed all clock, reset and clktrig ports to be individual +// signals instead of vectors. This is required for modeling of tools. +// 2. Interrupts are now defined as individual signals as well. +// 3. Added Clk buffer logic for FCLK_CLK +// 4. Includes the ACP related changes done +// +// TODO: +// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the +// number of interrupt ports connected for IRQ_F2P. +// +//------------------------------------------------------------------------------ +// ^^^^^^ +// KP 12/07/11 -- v3.00.a version +// ~~~~~~~ +// Key changes are +// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 12/09/11 -- v3.00.a version +// ~~~~~~~ +// Key changes are +// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated +// to STRING and fix for CR 640523 +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 12/13/11 -- v3.00.a version +// ~~~~~~~ +// Key changes are +// Updated IRQ_F2P logic to address CR 641523. +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 02/01/12 -- v3.01.a version +// ~~~~~~~ +// Key changes are +// Updated SDIO logic to address CR 636210. +// | +// Added C_PS7_SI_REV parameter to track SI Rev +// Removed compress/decompress logic to address CR 642527. +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 02/27/12 -- v3.01.a version +// ~~~~~~~ +// Key changes are +// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual +// ports as fix for CR 646379 +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 03/05/12 -- v3.01.a version +// ~~~~~~~ +// Key changes are +// Added/updated compress/decompress logic to address 648393 +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 03/14/12 -- v4.00.a version +// ~~~~~~~ +// Unused parameters deleted CR 651120 +// Addressed CR 651751 +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 04/17/12 -- v4.01.a version +// ~~~~~~~ +// Added FTM trace buffer functionality +// Added support for ACP AxUSER ports local update +//------------------------------------------------------------------------------ +// ^^^^^^ +// VR 05/18/12 -- v4.01.a version +// ~~~~~~~ +// Fixed CR#659157 +//------------------------------------------------------------------------------ +// ^^^^^^ +// VR 07/25/12 -- v4.01.a version +// ~~~~~~~ +// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model +// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model +//------------------------------------------------------------------------------ +// ^^^^^^ +// VR 11/06/12 -- v5.00 version +// ~~~~~~~ +// CR #682573 +// Added BIBUF to fixed IO ports and IBUF to fixed input ports +//------------------------------------------------------------------------------ +(*POWER= "/>" *) +(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.050, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.044, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.035, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.100, PCW_UIPARAM_DDR_BOARD_DELAY0=0.221, PCW_UIPARAM_DDR_BOARD_DELAY1=0.222, PCW_UIPARAM_DDR_BOARD_DELAY2=0.217, PCW_UIPARAM_DDR_BOARD_DELAY3=0.244, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=22.8, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=27.9, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=22.9, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=29.4, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=22.8, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=27.9, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=22.9, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=29.4, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=18.8, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=18.8, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=18.8, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=18.8, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=105.056, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=66.904, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=89.1715, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=113.63, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=98.503, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=68.5855, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=90.295, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=103.977, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\ +, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=125, PCW_FPGA2_PERIPHERAL_FREQMHZ=200, PCW_FPGA3_PERIPHERAL_FREQMHZ=65, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=1, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100\ +, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=100, PCW_S_AXI_HP0_FREQMHZ=100, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0\ +, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=EMIO, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=MIO 10 .. 11, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0\ +, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 46, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=MIO 14 .. 15, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=1, PCW_I2C1_I2C1_IO=MIO 12 .. 13, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X\ +, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=1, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *) +(* HW_HANDOFF = "design_3_processing_system7_0_0.hwdef" *) + +module processing_system7_v5_5_processing_system7 + +#( + parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1, + parameter integer C_S_AXI_ACP_ARUSER_VAL = 31, + parameter integer C_S_AXI_ACP_AWUSER_VAL = 31, + parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12, + parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12, + parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1, + parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1, + parameter integer C_M_AXI_GP0_ID_WIDTH = 12, + parameter integer C_M_AXI_GP1_ID_WIDTH = 12, + parameter integer C_S_AXI_GP0_ID_WIDTH = 6, + parameter integer C_S_AXI_GP1_ID_WIDTH = 6, + parameter integer C_S_AXI_HP0_ID_WIDTH = 6, + parameter integer C_S_AXI_HP1_ID_WIDTH = 6, + parameter integer C_S_AXI_HP2_ID_WIDTH = 6, + parameter integer C_S_AXI_HP3_ID_WIDTH = 6, + parameter integer C_S_AXI_ACP_ID_WIDTH = 3, + parameter integer C_S_AXI_HP0_DATA_WIDTH = 64, + parameter integer C_S_AXI_HP1_DATA_WIDTH = 64, + parameter integer C_S_AXI_HP2_DATA_WIDTH = 64, + parameter integer C_S_AXI_HP3_DATA_WIDTH = 64, + parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0, + parameter integer C_NUM_F2P_INTR_INPUTS = 1, + parameter C_FCLK_CLK0_BUF = "TRUE", + parameter C_FCLK_CLK1_BUF = "TRUE", + parameter C_FCLK_CLK2_BUF = "TRUE", + parameter C_FCLK_CLK3_BUF = "TRUE", + parameter integer C_EMIO_GPIO_WIDTH = 64, + parameter integer C_INCLUDE_TRACE_BUFFER = 0, + parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128, + parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12, + parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0, + parameter integer C_TRACE_PIPELINE_WIDTH = 8, + parameter C_PS7_SI_REV = "PRODUCTION", + parameter integer C_EN_EMIO_ENET0 = 0, + parameter integer C_EN_EMIO_ENET1 = 0, + parameter integer C_EN_EMIO_TRACE = 0, + parameter integer C_DQ_WIDTH = 32, + parameter integer C_DQS_WIDTH = 4, + parameter integer C_DM_WIDTH = 4, + parameter integer C_MIO_PRIMITIVE = 54, + parameter C_PACKAGE_NAME = "clg484", + parameter C_IRQ_F2P_MODE = "DIRECT", + parameter C_TRACE_INTERNAL_WIDTH = 32, + parameter integer C_EN_EMIO_PJTAG = 0, + + // Enable and disable AFI Secure transaction + parameter C_USE_AXI_NONSECURE = 0, + + //parameters for HP enable ports + parameter C_USE_S_AXI_HP0 = 0, + parameter C_USE_S_AXI_HP1 = 0, + parameter C_USE_S_AXI_HP2 = 0, + parameter C_USE_S_AXI_HP3 = 0, + + //parameters for GP and ACP enable ports */ + parameter C_USE_M_AXI_GP0 = 0, + parameter C_USE_M_AXI_GP1 = 0, + parameter C_USE_S_AXI_GP0 = 0, + parameter C_USE_S_AXI_GP1 = 0, + parameter C_USE_S_AXI_ACP = 0, + parameter C_GP0_EN_MODIFIABLE_TXN=0, + parameter C_GP1_EN_MODIFIABLE_TXN=0 + +) +( + //FMIO ========================================= + + //FMIO CAN0 + output CAN0_PHY_TX, + input CAN0_PHY_RX, + + //FMIO CAN1 + output CAN1_PHY_TX, + input CAN1_PHY_RX, + + //FMIO ENET0 + output reg ENET0_GMII_TX_EN = 'b0, + output reg ENET0_GMII_TX_ER = 'b0, + output ENET0_MDIO_MDC, + output ENET0_MDIO_O, + output ENET0_MDIO_T, + output ENET0_PTP_DELAY_REQ_RX, + output ENET0_PTP_DELAY_REQ_TX, + output ENET0_PTP_PDELAY_REQ_RX, + output ENET0_PTP_PDELAY_REQ_TX, + output ENET0_PTP_PDELAY_RESP_RX, + output ENET0_PTP_PDELAY_RESP_TX, + output ENET0_PTP_SYNC_FRAME_RX, + output ENET0_PTP_SYNC_FRAME_TX, + output ENET0_SOF_RX, + output ENET0_SOF_TX, + + + output reg [7:0] ENET0_GMII_TXD, + + + input ENET0_GMII_COL, + input ENET0_GMII_CRS, + input ENET0_GMII_RX_CLK, + input ENET0_GMII_RX_DV, + input ENET0_GMII_RX_ER, + input ENET0_GMII_TX_CLK, + input ENET0_MDIO_I, + input ENET0_EXT_INTIN, + input [7:0] ENET0_GMII_RXD, + + //FMIO ENET1 + output reg ENET1_GMII_TX_EN = 'b0, + output reg ENET1_GMII_TX_ER = 'b0, + output ENET1_MDIO_MDC, + output ENET1_MDIO_O, + output ENET1_MDIO_T, + output ENET1_PTP_DELAY_REQ_RX, + output ENET1_PTP_DELAY_REQ_TX, + output ENET1_PTP_PDELAY_REQ_RX, + output ENET1_PTP_PDELAY_REQ_TX, + output ENET1_PTP_PDELAY_RESP_RX, + output ENET1_PTP_PDELAY_RESP_TX, + output ENET1_PTP_SYNC_FRAME_RX, + output ENET1_PTP_SYNC_FRAME_TX, + output ENET1_SOF_RX, + output ENET1_SOF_TX, + output reg [7:0] ENET1_GMII_TXD, + + input ENET1_GMII_COL, + input ENET1_GMII_CRS, + input ENET1_GMII_RX_CLK, + input ENET1_GMII_RX_DV, + input ENET1_GMII_RX_ER, + input ENET1_GMII_TX_CLK, + input ENET1_MDIO_I, + input ENET1_EXT_INTIN, + input [7:0] ENET1_GMII_RXD, + + //FMIO GPIO + input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I, + output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O, + output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T, + + //FMIO I2C0 + input I2C0_SDA_I, + output I2C0_SDA_O, + output I2C0_SDA_T, + input I2C0_SCL_I, + output I2C0_SCL_O, + output I2C0_SCL_T, + + //FMIO I2C1 + input I2C1_SDA_I, + output I2C1_SDA_O, + output I2C1_SDA_T, + input I2C1_SCL_I, + output I2C1_SCL_O, + output I2C1_SCL_T, + + //FMIO PJTAG + input PJTAG_TCK, + input PJTAG_TMS, + input PJTAG_TDI, + output PJTAG_TDO, + + + //FMIO SDIO0 + output SDIO0_CLK, + input SDIO0_CLK_FB, + output SDIO0_CMD_O, + input SDIO0_CMD_I, + output SDIO0_CMD_T, + input [3:0] SDIO0_DATA_I, + output [3:0] SDIO0_DATA_O, + output [3:0] SDIO0_DATA_T, + output SDIO0_LED, + input SDIO0_CDN, + input SDIO0_WP, + output SDIO0_BUSPOW, + output [2:0] SDIO0_BUSVOLT, + + //FMIO SDIO1 + output SDIO1_CLK, + input SDIO1_CLK_FB, + output SDIO1_CMD_O, + input SDIO1_CMD_I, + output SDIO1_CMD_T, + input [3:0] SDIO1_DATA_I, + output [3:0] SDIO1_DATA_O, + output [3:0] SDIO1_DATA_T, + output SDIO1_LED, + input SDIO1_CDN, + input SDIO1_WP, + output SDIO1_BUSPOW, + output [2:0] SDIO1_BUSVOLT, + + //FMIO SPI0 + input SPI0_SCLK_I, + output SPI0_SCLK_O, + output SPI0_SCLK_T, + input SPI0_MOSI_I, + output SPI0_MOSI_O, + output SPI0_MOSI_T, + input SPI0_MISO_I, + output SPI0_MISO_O, + output SPI0_MISO_T, + input SPI0_SS_I, + output SPI0_SS_O, + output SPI0_SS1_O, + output SPI0_SS2_O, + output SPI0_SS_T, + + //FMIO SPI1 + input SPI1_SCLK_I, + output SPI1_SCLK_O, + output SPI1_SCLK_T, + input SPI1_MOSI_I, + output SPI1_MOSI_O, + output SPI1_MOSI_T, + input SPI1_MISO_I, + output SPI1_MISO_O, + output SPI1_MISO_T, + input SPI1_SS_I, + output SPI1_SS_O, + output SPI1_SS1_O, + output SPI1_SS2_O, + output SPI1_SS_T, + + //FMIO UART0 + output UART0_DTRN, + output UART0_RTSN, + output UART0_TX, + input UART0_CTSN, + input UART0_DCDN, + input UART0_DSRN, + input UART0_RIN, + input UART0_RX, + + //FMIO UART1 + output UART1_DTRN, + output UART1_RTSN, + output UART1_TX, + input UART1_CTSN, + input UART1_DCDN, + input UART1_DSRN, + input UART1_RIN, + input UART1_RX, + + //FMIO TTC0 + output TTC0_WAVE0_OUT, + output TTC0_WAVE1_OUT, + output TTC0_WAVE2_OUT, + input TTC0_CLK0_IN, + input TTC0_CLK1_IN, + input TTC0_CLK2_IN, + + //FMIO TTC1 + output TTC1_WAVE0_OUT, + output TTC1_WAVE1_OUT, + output TTC1_WAVE2_OUT, + input TTC1_CLK0_IN, + input TTC1_CLK1_IN, + input TTC1_CLK2_IN, + + //WDT + input WDT_CLK_IN, + output WDT_RST_OUT, + + //FTPORT + input TRACE_CLK, + output TRACE_CTL, + output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA, + output reg TRACE_CLK_OUT, + + // USB + output [1:0] USB0_PORT_INDCTL, + output USB0_VBUS_PWRSELECT, + input USB0_VBUS_PWRFAULT, + + output [1:0] USB1_PORT_INDCTL, + output USB1_VBUS_PWRSELECT, + input USB1_VBUS_PWRFAULT, + + input SRAM_INTIN, + + //AIO =================================================== + + //M_AXI_GP0 + + // -- Output + + output M_AXI_GP0_ARESETN, + output M_AXI_GP0_ARVALID, + output M_AXI_GP0_AWVALID, + output M_AXI_GP0_BREADY, + output M_AXI_GP0_RREADY, + output M_AXI_GP0_WLAST, + output M_AXI_GP0_WVALID, + output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID, + output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID, + output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID, + output [1:0] M_AXI_GP0_ARBURST, + output [1:0] M_AXI_GP0_ARLOCK, + output [2:0] M_AXI_GP0_ARSIZE, + output [1:0] M_AXI_GP0_AWBURST, + output [1:0] M_AXI_GP0_AWLOCK, + output [2:0] M_AXI_GP0_AWSIZE, + output [2:0] M_AXI_GP0_ARPROT, + output [2:0] M_AXI_GP0_AWPROT, + output [31:0] M_AXI_GP0_ARADDR, + output [31:0] M_AXI_GP0_AWADDR, + output [31:0] M_AXI_GP0_WDATA, + output [3:0] M_AXI_GP0_ARCACHE, + output [3:0] M_AXI_GP0_ARLEN, + output [3:0] M_AXI_GP0_ARQOS, + output [3:0] M_AXI_GP0_AWCACHE, + output [3:0] M_AXI_GP0_AWLEN, + output [3:0] M_AXI_GP0_AWQOS, + output [3:0] M_AXI_GP0_WSTRB, + + // -- Input + + input M_AXI_GP0_ACLK, + input M_AXI_GP0_ARREADY, + input M_AXI_GP0_AWREADY, + input M_AXI_GP0_BVALID, + input M_AXI_GP0_RLAST, + input M_AXI_GP0_RVALID, + input M_AXI_GP0_WREADY, + input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID, + input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID, + input [1:0] M_AXI_GP0_BRESP, + input [1:0] M_AXI_GP0_RRESP, + input [31:0] M_AXI_GP0_RDATA, + + + //M_AXI_GP1 + + // -- Output + + output M_AXI_GP1_ARESETN, + output M_AXI_GP1_ARVALID, + output M_AXI_GP1_AWVALID, + output M_AXI_GP1_BREADY, + output M_AXI_GP1_RREADY, + output M_AXI_GP1_WLAST, + output M_AXI_GP1_WVALID, + output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID, + output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID, + output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID, + output [1:0] M_AXI_GP1_ARBURST, + output [1:0] M_AXI_GP1_ARLOCK, + output [2:0] M_AXI_GP1_ARSIZE, + output [1:0] M_AXI_GP1_AWBURST, + output [1:0] M_AXI_GP1_AWLOCK, + output [2:0] M_AXI_GP1_AWSIZE, + output [2:0] M_AXI_GP1_ARPROT, + output [2:0] M_AXI_GP1_AWPROT, + output [31:0] M_AXI_GP1_ARADDR, + output [31:0] M_AXI_GP1_AWADDR, + output [31:0] M_AXI_GP1_WDATA, + output [3:0] M_AXI_GP1_ARCACHE, + output [3:0] M_AXI_GP1_ARLEN, + output [3:0] M_AXI_GP1_ARQOS, + output [3:0] M_AXI_GP1_AWCACHE, + output [3:0] M_AXI_GP1_AWLEN, + output [3:0] M_AXI_GP1_AWQOS, + output [3:0] M_AXI_GP1_WSTRB, + + // -- Input + + input M_AXI_GP1_ACLK, + input M_AXI_GP1_ARREADY, + input M_AXI_GP1_AWREADY, + input M_AXI_GP1_BVALID, + input M_AXI_GP1_RLAST, + input M_AXI_GP1_RVALID, + input M_AXI_GP1_WREADY, + input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID, + input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID, + input [1:0] M_AXI_GP1_BRESP, + input [1:0] M_AXI_GP1_RRESP, + input [31:0] M_AXI_GP1_RDATA, + + + // S_AXI_GP0 + + // -- Output + + output S_AXI_GP0_ARESETN, + output S_AXI_GP0_ARREADY, + output S_AXI_GP0_AWREADY, + output S_AXI_GP0_BVALID, + output S_AXI_GP0_RLAST, + output S_AXI_GP0_RVALID, + output S_AXI_GP0_WREADY, + output [1:0] S_AXI_GP0_BRESP, + output [1:0] S_AXI_GP0_RRESP, + output [31:0] S_AXI_GP0_RDATA, + output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID, + output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID, + + // -- Input + input S_AXI_GP0_ACLK, + input S_AXI_GP0_ARVALID, + input S_AXI_GP0_AWVALID, + input S_AXI_GP0_BREADY, + input S_AXI_GP0_RREADY, + input S_AXI_GP0_WLAST, + input S_AXI_GP0_WVALID, + input [1:0] S_AXI_GP0_ARBURST, + input [1:0] S_AXI_GP0_ARLOCK, + input [2:0] S_AXI_GP0_ARSIZE, + input [1:0] S_AXI_GP0_AWBURST, + input [1:0] S_AXI_GP0_AWLOCK, + input [2:0] S_AXI_GP0_AWSIZE, + input [2:0] S_AXI_GP0_ARPROT, + input [2:0] S_AXI_GP0_AWPROT, + input [31:0] S_AXI_GP0_ARADDR, + input [31:0] S_AXI_GP0_AWADDR, + input [31:0] S_AXI_GP0_WDATA, + input [3:0] S_AXI_GP0_ARCACHE, + input [3:0] S_AXI_GP0_ARLEN, + input [3:0] S_AXI_GP0_ARQOS, + input [3:0] S_AXI_GP0_AWCACHE, + input [3:0] S_AXI_GP0_AWLEN, + input [3:0] S_AXI_GP0_AWQOS, + input [3:0] S_AXI_GP0_WSTRB, + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID, + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID, + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID, + + // S_AXI_GP1 + + // -- Output + output S_AXI_GP1_ARESETN, + output S_AXI_GP1_ARREADY, + output S_AXI_GP1_AWREADY, + output S_AXI_GP1_BVALID, + output S_AXI_GP1_RLAST, + output S_AXI_GP1_RVALID, + output S_AXI_GP1_WREADY, + output [1:0] S_AXI_GP1_BRESP, + output [1:0] S_AXI_GP1_RRESP, + output [31:0] S_AXI_GP1_RDATA, + output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID, + output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID, + + // -- Input + input S_AXI_GP1_ACLK, + input S_AXI_GP1_ARVALID, + input S_AXI_GP1_AWVALID, + input S_AXI_GP1_BREADY, + input S_AXI_GP1_RREADY, + input S_AXI_GP1_WLAST, + input S_AXI_GP1_WVALID, + input [1:0] S_AXI_GP1_ARBURST, + input [1:0] S_AXI_GP1_ARLOCK, + input [2:0] S_AXI_GP1_ARSIZE, + input [1:0] S_AXI_GP1_AWBURST, + input [1:0] S_AXI_GP1_AWLOCK, + input [2:0] S_AXI_GP1_AWSIZE, + input [2:0] S_AXI_GP1_ARPROT, + input [2:0] S_AXI_GP1_AWPROT, + input [31:0] S_AXI_GP1_ARADDR, + input [31:0] S_AXI_GP1_AWADDR, + input [31:0] S_AXI_GP1_WDATA, + input [3:0] S_AXI_GP1_ARCACHE, + input [3:0] S_AXI_GP1_ARLEN, + input [3:0] S_AXI_GP1_ARQOS, + input [3:0] S_AXI_GP1_AWCACHE, + input [3:0] S_AXI_GP1_AWLEN, + input [3:0] S_AXI_GP1_AWQOS, + input [3:0] S_AXI_GP1_WSTRB, + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID, + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID, + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID, + + //S_AXI_ACP + + // -- Output + + output S_AXI_ACP_ARESETN, + output S_AXI_ACP_ARREADY, + output S_AXI_ACP_AWREADY, + output S_AXI_ACP_BVALID, + output S_AXI_ACP_RLAST, + output S_AXI_ACP_RVALID, + output S_AXI_ACP_WREADY, + output [1:0] S_AXI_ACP_BRESP, + output [1:0] S_AXI_ACP_RRESP, + output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID, + output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID, + output [63:0] S_AXI_ACP_RDATA, + + // -- Input + + input S_AXI_ACP_ACLK, + input S_AXI_ACP_ARVALID, + input S_AXI_ACP_AWVALID, + input S_AXI_ACP_BREADY, + input S_AXI_ACP_RREADY, + input S_AXI_ACP_WLAST, + input S_AXI_ACP_WVALID, + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID, + input [2:0] S_AXI_ACP_ARPROT, + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID, + input [2:0] S_AXI_ACP_AWPROT, + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID, + input [31:0] S_AXI_ACP_ARADDR, + input [31:0] S_AXI_ACP_AWADDR, + input [3:0] S_AXI_ACP_ARCACHE, + input [3:0] S_AXI_ACP_ARLEN, + input [3:0] S_AXI_ACP_ARQOS, + input [3:0] S_AXI_ACP_AWCACHE, + input [3:0] S_AXI_ACP_AWLEN, + input [3:0] S_AXI_ACP_AWQOS, + input [1:0] S_AXI_ACP_ARBURST, + input [1:0] S_AXI_ACP_ARLOCK, + input [2:0] S_AXI_ACP_ARSIZE, + input [1:0] S_AXI_ACP_AWBURST, + input [1:0] S_AXI_ACP_AWLOCK, + input [2:0] S_AXI_ACP_AWSIZE, + input [4:0] S_AXI_ACP_ARUSER, + input [4:0] S_AXI_ACP_AWUSER, + input [63:0] S_AXI_ACP_WDATA, + input [7:0] S_AXI_ACP_WSTRB, + + // S_AXI_HP_0 + + // -- Output + output S_AXI_HP0_ARESETN, + output S_AXI_HP0_ARREADY, + output S_AXI_HP0_AWREADY, + output S_AXI_HP0_BVALID, + output S_AXI_HP0_RLAST, + output S_AXI_HP0_RVALID, + output S_AXI_HP0_WREADY, + output [1:0] S_AXI_HP0_BRESP, + output [1:0] S_AXI_HP0_RRESP, + output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID, + output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID, + output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA, + output [7:0] S_AXI_HP0_RCOUNT, + output [7:0] S_AXI_HP0_WCOUNT, + output [2:0] S_AXI_HP0_RACOUNT, + output [5:0] S_AXI_HP0_WACOUNT, + + // -- Input + input S_AXI_HP0_ACLK, + input S_AXI_HP0_ARVALID, + input S_AXI_HP0_AWVALID, + input S_AXI_HP0_BREADY, + input S_AXI_HP0_RDISSUECAP1_EN, + input S_AXI_HP0_RREADY, + input S_AXI_HP0_WLAST, + input S_AXI_HP0_WRISSUECAP1_EN, + input S_AXI_HP0_WVALID, + input [1:0] S_AXI_HP0_ARBURST, + input [1:0] S_AXI_HP0_ARLOCK, + input [2:0] S_AXI_HP0_ARSIZE, + input [1:0] S_AXI_HP0_AWBURST, + input [1:0] S_AXI_HP0_AWLOCK, + input [2:0] S_AXI_HP0_AWSIZE, + input [2:0] S_AXI_HP0_ARPROT, + input [2:0] S_AXI_HP0_AWPROT, + input [31:0] S_AXI_HP0_ARADDR, + input [31:0] S_AXI_HP0_AWADDR, + input [3:0] S_AXI_HP0_ARCACHE, + input [3:0] S_AXI_HP0_ARLEN, + input [3:0] S_AXI_HP0_ARQOS, + input [3:0] S_AXI_HP0_AWCACHE, + input [3:0] S_AXI_HP0_AWLEN, + input [3:0] S_AXI_HP0_AWQOS, + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID, + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID, + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID, + input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA, + input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB, + + // S_AXI_HP1 + // -- Output + output S_AXI_HP1_ARESETN, + output S_AXI_HP1_ARREADY, + output S_AXI_HP1_AWREADY, + output S_AXI_HP1_BVALID, + output S_AXI_HP1_RLAST, + output S_AXI_HP1_RVALID, + output S_AXI_HP1_WREADY, + output [1:0] S_AXI_HP1_BRESP, + output [1:0] S_AXI_HP1_RRESP, + output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID, + output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID, + output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA, + output [7:0] S_AXI_HP1_RCOUNT, + output [7:0] S_AXI_HP1_WCOUNT, + output [2:0] S_AXI_HP1_RACOUNT, + output [5:0] S_AXI_HP1_WACOUNT, + + + // -- Input + input S_AXI_HP1_ACLK, + input S_AXI_HP1_ARVALID, + input S_AXI_HP1_AWVALID, + input S_AXI_HP1_BREADY, + input S_AXI_HP1_RDISSUECAP1_EN, + input S_AXI_HP1_RREADY, + input S_AXI_HP1_WLAST, + input S_AXI_HP1_WRISSUECAP1_EN, + input S_AXI_HP1_WVALID, + input [1:0] S_AXI_HP1_ARBURST, + input [1:0] S_AXI_HP1_ARLOCK, + input [2:0] S_AXI_HP1_ARSIZE, + input [1:0] S_AXI_HP1_AWBURST, + input [1:0] S_AXI_HP1_AWLOCK, + input [2:0] S_AXI_HP1_AWSIZE, + input [2:0] S_AXI_HP1_ARPROT, + input [2:0] S_AXI_HP1_AWPROT, + input [31:0] S_AXI_HP1_ARADDR, + input [31:0] S_AXI_HP1_AWADDR, + input [3:0] S_AXI_HP1_ARCACHE, + input [3:0] S_AXI_HP1_ARLEN, + input [3:0] S_AXI_HP1_ARQOS, + input [3:0] S_AXI_HP1_AWCACHE, + input [3:0] S_AXI_HP1_AWLEN, + input [3:0] S_AXI_HP1_AWQOS, + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID, + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID, + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID, + input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA, + input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB, + + // S_AXI_HP2 + // -- Output + output S_AXI_HP2_ARESETN, + output S_AXI_HP2_ARREADY, + output S_AXI_HP2_AWREADY, + output S_AXI_HP2_BVALID, + output S_AXI_HP2_RLAST, + output S_AXI_HP2_RVALID, + output S_AXI_HP2_WREADY, + output [1:0] S_AXI_HP2_BRESP, + output [1:0] S_AXI_HP2_RRESP, + output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID, + output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID, + output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA, + output [7:0] S_AXI_HP2_RCOUNT, + output [7:0] S_AXI_HP2_WCOUNT, + output [2:0] S_AXI_HP2_RACOUNT, + output [5:0] S_AXI_HP2_WACOUNT, + + + // -- Input + input S_AXI_HP2_ACLK, + input S_AXI_HP2_ARVALID, + input S_AXI_HP2_AWVALID, + input S_AXI_HP2_BREADY, + input S_AXI_HP2_RDISSUECAP1_EN, + input S_AXI_HP2_RREADY, + input S_AXI_HP2_WLAST, + input S_AXI_HP2_WRISSUECAP1_EN, + input S_AXI_HP2_WVALID, + input [1:0] S_AXI_HP2_ARBURST, + input [1:0] S_AXI_HP2_ARLOCK, + input [2:0] S_AXI_HP2_ARSIZE, + input [1:0] S_AXI_HP2_AWBURST, + input [1:0] S_AXI_HP2_AWLOCK, + input [2:0] S_AXI_HP2_AWSIZE, + input [2:0] S_AXI_HP2_ARPROT, + input [2:0] S_AXI_HP2_AWPROT, + input [31:0] S_AXI_HP2_ARADDR, + input [31:0] S_AXI_HP2_AWADDR, + input [3:0] S_AXI_HP2_ARCACHE, + input [3:0] S_AXI_HP2_ARLEN, + input [3:0] S_AXI_HP2_ARQOS, + input [3:0] S_AXI_HP2_AWCACHE, + input [3:0] S_AXI_HP2_AWLEN, + input [3:0] S_AXI_HP2_AWQOS, + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID, + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID, + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID, + input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA, + input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB, + + // S_AXI_HP_3 + + // -- Output + output S_AXI_HP3_ARESETN, + output S_AXI_HP3_ARREADY, + output S_AXI_HP3_AWREADY, + output S_AXI_HP3_BVALID, + output S_AXI_HP3_RLAST, + output S_AXI_HP3_RVALID, + output S_AXI_HP3_WREADY, + output [1:0] S_AXI_HP3_BRESP, + output [1:0] S_AXI_HP3_RRESP, + output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID, + output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID, + output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA, + output [7:0] S_AXI_HP3_RCOUNT, + output [7:0] S_AXI_HP3_WCOUNT, + output [2:0] S_AXI_HP3_RACOUNT, + output [5:0] S_AXI_HP3_WACOUNT, + + + // -- Input + input S_AXI_HP3_ACLK, + input S_AXI_HP3_ARVALID, + input S_AXI_HP3_AWVALID, + input S_AXI_HP3_BREADY, + input S_AXI_HP3_RDISSUECAP1_EN, + input S_AXI_HP3_RREADY, + input S_AXI_HP3_WLAST, + input S_AXI_HP3_WRISSUECAP1_EN, + input S_AXI_HP3_WVALID, + input [1:0] S_AXI_HP3_ARBURST, + input [1:0] S_AXI_HP3_ARLOCK, + input [2:0] S_AXI_HP3_ARSIZE, + input [1:0] S_AXI_HP3_AWBURST, + input [1:0] S_AXI_HP3_AWLOCK, + input [2:0] S_AXI_HP3_AWSIZE, + input [2:0] S_AXI_HP3_ARPROT, + input [2:0] S_AXI_HP3_AWPROT, + input [31:0] S_AXI_HP3_ARADDR, + input [31:0] S_AXI_HP3_AWADDR, + input [3:0] S_AXI_HP3_ARCACHE, + input [3:0] S_AXI_HP3_ARLEN, + input [3:0] S_AXI_HP3_ARQOS, + input [3:0] S_AXI_HP3_AWCACHE, + input [3:0] S_AXI_HP3_AWLEN, + input [3:0] S_AXI_HP3_AWQOS, + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID, + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID, + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID, + input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA, + input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB, + + //FIO ======================================== + + //IRQ + //output [28:0] IRQ_P2F, + output IRQ_P2F_DMAC_ABORT , + output IRQ_P2F_DMAC0, + output IRQ_P2F_DMAC1, + output IRQ_P2F_DMAC2, + output IRQ_P2F_DMAC3, + output IRQ_P2F_DMAC4, + output IRQ_P2F_DMAC5, + output IRQ_P2F_DMAC6, + output IRQ_P2F_DMAC7, + output IRQ_P2F_SMC, + output IRQ_P2F_QSPI, + output IRQ_P2F_CTI, + output IRQ_P2F_GPIO, + output IRQ_P2F_USB0, + output IRQ_P2F_ENET0, + output IRQ_P2F_ENET_WAKE0, + output IRQ_P2F_SDIO0, + output IRQ_P2F_I2C0, + output IRQ_P2F_SPI0, + output IRQ_P2F_UART0, + output IRQ_P2F_CAN0, + output IRQ_P2F_USB1, + output IRQ_P2F_ENET1, + output IRQ_P2F_ENET_WAKE1, + output IRQ_P2F_SDIO1, + output IRQ_P2F_I2C1, + output IRQ_P2F_SPI1, + output IRQ_P2F_UART1, + output IRQ_P2F_CAN1, + input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P, + input Core0_nFIQ, + input Core0_nIRQ, + input Core1_nFIQ, + input Core1_nIRQ, + + //DMA + + output [1:0] DMA0_DATYPE, + output DMA0_DAVALID, + output DMA0_DRREADY, + output DMA0_RSTN, + output [1:0] DMA1_DATYPE, + output DMA1_DAVALID, + output DMA1_DRREADY, + output DMA1_RSTN, + output [1:0] DMA2_DATYPE, + output DMA2_DAVALID, + output DMA2_DRREADY, + output DMA2_RSTN, + output [1:0] DMA3_DATYPE, + output DMA3_DAVALID, + output DMA3_DRREADY, + output DMA3_RSTN, + input DMA0_ACLK, + input DMA0_DAREADY, + input DMA0_DRLAST, + input DMA0_DRVALID, + input DMA1_ACLK, + input DMA1_DAREADY, + input DMA1_DRLAST, + input DMA1_DRVALID, + input DMA2_ACLK, + input DMA2_DAREADY, + input DMA2_DRLAST, + input DMA2_DRVALID, + input DMA3_ACLK, + input DMA3_DAREADY, + input DMA3_DRLAST, + input DMA3_DRVALID, + input [1:0] DMA0_DRTYPE, + input [1:0] DMA1_DRTYPE, + input [1:0] DMA2_DRTYPE, + input [1:0] DMA3_DRTYPE, + + //FCLK + output FCLK_CLK3, + output FCLK_CLK2, + output FCLK_CLK1, + output FCLK_CLK0, + + input FCLK_CLKTRIG3_N, + input FCLK_CLKTRIG2_N, + input FCLK_CLKTRIG1_N, + input FCLK_CLKTRIG0_N, + + output FCLK_RESET3_N, + output FCLK_RESET2_N, + output FCLK_RESET1_N, + output FCLK_RESET0_N, + + //FTMD + input [31:0] FTMD_TRACEIN_DATA, + input FTMD_TRACEIN_VALID, + input FTMD_TRACEIN_CLK, + input [3:0] FTMD_TRACEIN_ATID, + + //FTMT + input FTMT_F2P_TRIG_0, + output FTMT_F2P_TRIGACK_0, + input FTMT_F2P_TRIG_1, + output FTMT_F2P_TRIGACK_1, + input FTMT_F2P_TRIG_2, + output FTMT_F2P_TRIGACK_2, + input FTMT_F2P_TRIG_3, + output FTMT_F2P_TRIGACK_3, + input [31:0] FTMT_F2P_DEBUG, + input FTMT_P2F_TRIGACK_0, + output FTMT_P2F_TRIG_0, + input FTMT_P2F_TRIGACK_1, + output FTMT_P2F_TRIG_1, + input FTMT_P2F_TRIGACK_2, + output FTMT_P2F_TRIG_2, + input FTMT_P2F_TRIGACK_3, + output FTMT_P2F_TRIG_3, + output [31:0] FTMT_P2F_DEBUG, + + //FIDLE + input FPGA_IDLE_N, + + //EVENT + + output EVENT_EVENTO, + output [1:0] EVENT_STANDBYWFE, + output [1:0] EVENT_STANDBYWFI, + input EVENT_EVENTI, + + + //DARB + input [3:0] DDR_ARB, + inout [C_MIO_PRIMITIVE - 1:0] MIO, + + //DDR + inout DDR_CAS_n, // CASB + inout DDR_CKE, // CKE + inout DDR_Clk_n, // CKN + inout DDR_Clk, // CKP + inout DDR_CS_n, // CSB + inout DDR_DRSTB, // DDR_DRSTB + inout DDR_ODT, // ODT + inout DDR_RAS_n, // RASB + inout DDR_WEB, + inout [2:0] DDR_BankAddr, // BA + inout [14:0] DDR_Addr, // A + + inout DDR_VRN, + inout DDR_VRP, + inout [C_DM_WIDTH - 1:0] DDR_DM, // DM + inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ + inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN + inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP + + inout PS_SRSTB, // SRSTB + inout PS_CLK, // CLK + inout PS_PORB // PORB + + +); + +wire [11:0] M_AXI_GP0_AWID_FULL; +wire [11:0] M_AXI_GP0_WID_FULL; +wire [11:0] M_AXI_GP0_ARID_FULL; + +wire [11:0] M_AXI_GP0_BID_FULL; +wire [11:0] M_AXI_GP0_RID_FULL; + +wire [11:0] M_AXI_GP1_AWID_FULL; +wire [11:0] M_AXI_GP1_WID_FULL; +wire [11:0] M_AXI_GP1_ARID_FULL; + +wire [11:0] M_AXI_GP1_BID_FULL; +wire [11:0] M_AXI_GP1_RID_FULL; + +wire [3:0] M_AXI_GP0_ARCACHE_t; +wire [3:0] M_AXI_GP1_ARCACHE_t; +wire [3:0] M_AXI_GP0_AWCACHE_t; +wire [3:0] M_AXI_GP1_AWCACHE_t; + + +// Wires for connecting to the PS7 +wire ENET0_GMII_TX_EN_i; +wire ENET0_GMII_TX_ER_i; +reg ENET0_GMII_COL_i; +reg ENET0_GMII_CRS_i; +reg ENET0_GMII_RX_DV_i; +reg ENET0_GMII_RX_ER_i; +reg [7:0] ENET0_GMII_RXD_i; +wire [7:0] ENET0_GMII_TXD_i; + +wire ENET1_GMII_TX_EN_i; +wire ENET1_GMII_TX_ER_i; +reg ENET1_GMII_COL_i; +reg ENET1_GMII_CRS_i; +reg ENET1_GMII_RX_DV_i; +reg ENET1_GMII_RX_ER_i; +reg [7:0] ENET1_GMII_RXD_i; +wire [7:0] ENET1_GMII_TXD_i; + +reg [31:0] FTMD_TRACEIN_DATA_notracebuf; +reg FTMD_TRACEIN_VALID_notracebuf; +reg [3:0] FTMD_TRACEIN_ATID_notracebuf; + +wire [31:0] FTMD_TRACEIN_DATA_i; +wire FTMD_TRACEIN_VALID_i; +wire [3:0] FTMD_TRACEIN_ATID_i; + +wire [31:0] FTMD_TRACEIN_DATA_tracebuf; +wire FTMD_TRACEIN_VALID_tracebuf; +wire [3:0] FTMD_TRACEIN_ATID_tracebuf; + +wire [5:0] S_AXI_GP0_BID_out; +wire [5:0] S_AXI_GP0_RID_out; +wire [5:0] S_AXI_GP0_ARID_in; +wire [5:0] S_AXI_GP0_AWID_in; +wire [5:0] S_AXI_GP0_WID_in; + +wire [5:0] S_AXI_GP1_BID_out; +wire [5:0] S_AXI_GP1_RID_out; +wire [5:0] S_AXI_GP1_ARID_in; +wire [5:0] S_AXI_GP1_AWID_in; +wire [5:0] S_AXI_GP1_WID_in; + +wire [5:0] S_AXI_HP0_BID_out; +wire [5:0] S_AXI_HP0_RID_out; +wire [5:0] S_AXI_HP0_ARID_in; +wire [5:0] S_AXI_HP0_AWID_in; +wire [5:0] S_AXI_HP0_WID_in; + +wire [5:0] S_AXI_HP1_BID_out; +wire [5:0] S_AXI_HP1_RID_out; +wire [5:0] S_AXI_HP1_ARID_in; +wire [5:0] S_AXI_HP1_AWID_in; +wire [5:0] S_AXI_HP1_WID_in; + +wire [5:0] S_AXI_HP2_BID_out; +wire [5:0] S_AXI_HP2_RID_out; +wire [5:0] S_AXI_HP2_ARID_in; +wire [5:0] S_AXI_HP2_AWID_in; +wire [5:0] S_AXI_HP2_WID_in; + +wire [5:0] S_AXI_HP3_BID_out; +wire [5:0] S_AXI_HP3_RID_out; +wire [5:0] S_AXI_HP3_ARID_in; +wire [5:0] S_AXI_HP3_AWID_in; +wire [5:0] S_AXI_HP3_WID_in; + +wire [2:0] S_AXI_ACP_BID_out; +wire [2:0] S_AXI_ACP_RID_out; +wire [2:0] S_AXI_ACP_ARID_in; +wire [2:0] S_AXI_ACP_AWID_in; +wire [2:0] S_AXI_ACP_WID_in; + +wire [63:0] S_AXI_HP0_WDATA_in; +wire [7:0] S_AXI_HP0_WSTRB_in; +wire [63:0] S_AXI_HP0_RDATA_out; + +wire [63:0] S_AXI_HP1_WDATA_in; +wire [7:0] S_AXI_HP1_WSTRB_in; +wire [63:0] S_AXI_HP1_RDATA_out; + +wire [63:0] S_AXI_HP2_WDATA_in; +wire [7:0] S_AXI_HP2_WSTRB_in; +wire [63:0] S_AXI_HP2_RDATA_out; + +wire [63:0] S_AXI_HP3_WDATA_in; +wire [7:0] S_AXI_HP3_WSTRB_in; +wire [63:0] S_AXI_HP3_RDATA_out; + +wire [1:0] M_AXI_GP0_ARSIZE_i; +wire [1:0] M_AXI_GP0_AWSIZE_i; + +wire [1:0] M_AXI_GP1_ARSIZE_i; +wire [1:0] M_AXI_GP1_AWSIZE_i; + +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W; + + +wire SAXIACPARREADY_W; +wire SAXIACPAWREADY_W; +wire SAXIACPBVALID_W; +wire SAXIACPRLAST_W; +wire SAXIACPRVALID_W; +wire SAXIACPWREADY_W; +wire [1:0] SAXIACPBRESP_W; +wire [1:0] SAXIACPRRESP_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID; +wire [63:0] SAXIACPRDATA_W; + +wire S_AXI_ATC_ARVALID; +wire S_AXI_ATC_AWVALID; +wire S_AXI_ATC_BREADY; +wire S_AXI_ATC_RREADY; +wire S_AXI_ATC_WLAST; +wire S_AXI_ATC_WVALID; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID; +wire [2:0] S_AXI_ATC_ARPROT; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID; +wire [2:0] S_AXI_ATC_AWPROT; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID; +wire [31:0] S_AXI_ATC_ARADDR; +wire [31:0] S_AXI_ATC_AWADDR; +wire [3:0] S_AXI_ATC_ARCACHE; +wire [3:0] S_AXI_ATC_ARLEN; +wire [3:0] S_AXI_ATC_ARQOS; +wire [3:0] S_AXI_ATC_AWCACHE; +wire [3:0] S_AXI_ATC_AWLEN; +wire [3:0] S_AXI_ATC_AWQOS; +wire [1:0] S_AXI_ATC_ARBURST; +wire [1:0] S_AXI_ATC_ARLOCK; +wire [2:0] S_AXI_ATC_ARSIZE; +wire [1:0] S_AXI_ATC_AWBURST; +wire [1:0] S_AXI_ATC_AWLOCK; +wire [2:0] S_AXI_ATC_AWSIZE; +wire [4:0] S_AXI_ATC_ARUSER; +wire [4:0] S_AXI_ATC_AWUSER; +wire [63:0] S_AXI_ATC_WDATA; +wire [7:0] S_AXI_ATC_WSTRB; + + +wire SAXIACPARVALID_W; +wire SAXIACPAWVALID_W; +wire SAXIACPBREADY_W; +wire SAXIACPRREADY_W; +wire SAXIACPWLAST_W; +wire SAXIACPWVALID_W; +wire [2:0] SAXIACPARPROT_W; +wire [2:0] SAXIACPAWPROT_W; +wire [31:0] SAXIACPARADDR_W; +wire [31:0] SAXIACPAWADDR_W; +wire [3:0] SAXIACPARCACHE_W; +wire [3:0] SAXIACPARLEN_W; +wire [3:0] SAXIACPARQOS_W; +wire [3:0] SAXIACPAWCACHE_W; +wire [3:0] SAXIACPAWLEN_W; +wire [3:0] SAXIACPAWQOS_W; +wire [1:0] SAXIACPARBURST_W; +wire [1:0] SAXIACPARLOCK_W; +wire [2:0] SAXIACPARSIZE_W; +wire [1:0] SAXIACPAWBURST_W; +wire [1:0] SAXIACPAWLOCK_W; +wire [2:0] SAXIACPAWSIZE_W; +wire [4:0] SAXIACPARUSER_W; +wire [4:0] SAXIACPAWUSER_W; +wire [63:0] SAXIACPWDATA_W; +wire [7:0] SAXIACPWSTRB_W; + +// AxUSER signal update +wire [4:0] param_aruser; +wire [4:0] param_awuser; + +// Added to address CR 651751 +wire [3:0] fclk_clktrig_gnd = 4'h0; + + +wire [19:0] irq_f2p_i; +wire [15:0] irq_f2p_null = 16'h0000; + +// EMIO I2C0 +wire I2C0_SDA_T_n; +wire I2C0_SCL_T_n; +// EMIO I2C1 +wire I2C1_SDA_T_n; +wire I2C1_SCL_T_n; +// EMIO SPI0 +wire SPI0_SCLK_T_n; +wire SPI0_MOSI_T_n; +wire SPI0_MISO_T_n; +wire SPI0_SS_T_n; +// EMIO SPI1 +wire SPI1_SCLK_T_n; +wire SPI1_MOSI_T_n; +wire SPI1_MISO_T_n; +wire SPI1_SS_T_n; + +// EMIO GEM0 +wire ENET0_MDIO_T_n; + +// EMIO GEM1 +wire ENET1_MDIO_T_n; + +// EMIO GPIO +wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n; + +wire [63:0] gpio_out_t_n; +wire [63:0] gpio_out; +wire [63:0] gpio_in63_0; + +//For Clock buffering +wire [3:0] FCLK_CLK_unbuffered; +wire [3:0] FCLK_CLK_buffered; +wire FCLK_CLK0_temp; + +// EMIO PJTAG +wire PJTAG_TDO_O; +wire PJTAG_TDO_T; +wire PJTAG_TDO_T_n; + +// EMIO SDIO0 +wire SDIO0_CMD_T_n; +wire [3:0] SDIO0_DATA_T_n; + +// EMIO SDIO1 +wire SDIO1_CMD_T_n; +wire [3:0] SDIO1_DATA_T_n; + +// buffered IO +wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO; +wire buffered_DDR_WEB; +wire buffered_DDR_CAS_n; +wire buffered_DDR_CKE; +wire buffered_DDR_Clk_n; +wire buffered_DDR_Clk; +wire buffered_DDR_CS_n; +wire buffered_DDR_DRSTB; +wire buffered_DDR_ODT; +wire buffered_DDR_RAS_n; +wire [2:0] buffered_DDR_BankAddr; +wire [14:0] buffered_DDR_Addr; + +wire buffered_DDR_VRN; +wire buffered_DDR_VRP; +wire [C_DM_WIDTH - 1:0] buffered_DDR_DM; +wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ; +wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n; +wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS; + +wire buffered_PS_SRSTB; +wire buffered_PS_CLK; +wire buffered_PS_PORB; + +wire S_AXI_HP0_ACLK_temp; +wire S_AXI_HP1_ACLK_temp; +wire S_AXI_HP2_ACLK_temp; +wire S_AXI_HP3_ACLK_temp; +wire M_AXI_GP0_ACLK_temp; +wire M_AXI_GP1_ACLK_temp; +wire S_AXI_GP0_ACLK_temp; +wire S_AXI_GP1_ACLK_temp; +wire S_AXI_ACP_ACLK_temp; + +wire [31:0] TRACE_DATA_i; +wire TRACE_CTL_i; +(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0]; +(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0]; + +// fixed CR #665394 +integer j; +generate + if (C_EN_EMIO_TRACE == 1) begin + always @(posedge TRACE_CLK) + begin + TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i; + TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0]; + for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin + TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j]; + TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j]; + end + TRACE_CLK_OUT <= ~TRACE_CLK_OUT; + end + end +else +begin +always @* +begin +TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0; + TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0; + for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin + TRACE_CTL_PIPE[j-1] <= 1'b0; + TRACE_DATA_PIPE[j-1] <= 1'b0; + end + TRACE_CLK_OUT <= 1'b0; + end +end +endgenerate + +assign TRACE_CTL = TRACE_CTL_PIPE[0]; + +assign TRACE_DATA = TRACE_DATA_PIPE[0]; + +//irq_p2f + +// Updated IRQ_F2P logic to address CR 641523 +generate + if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null + assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]}; + end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all + assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]}; + end else begin : irq_f2p_select + if (C_IRQ_F2P_MODE == "DIRECT") begin + assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, + irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0], + IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]}; + end else begin + assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, + IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0], + irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]}; + end + end +endgenerate + +assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]}; +assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]}; +assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]}; +assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]}; + + + +// Compress Function + + +// Modified as per CR 631955 +//function [11:0] uncompress_id; +// input [5:0] id; +// begin +// case (id[5:0]) +// // dmac0 +// 6'd1 : uncompress_id = 12'b010000_1000_00 ; +// 6'd2 : uncompress_id = 12'b010000_0000_00 ; +// 6'd3 : uncompress_id = 12'b010000_0001_00 ; +// 6'd4 : uncompress_id = 12'b010000_0010_00 ; +// 6'd5 : uncompress_id = 12'b010000_0011_00 ; +// 6'd6 : uncompress_id = 12'b010000_0100_00 ; +// 6'd7 : uncompress_id = 12'b010000_0101_00 ; +// 6'd8 : uncompress_id = 12'b010000_0110_00 ; +// 6'd9 : uncompress_id = 12'b010000_0111_00 ; +// // ioum +// 6'd10 : uncompress_id = 12'b0100000_000_01 ; +// 6'd11 : uncompress_id = 12'b0100000_001_01 ; +// 6'd12 : uncompress_id = 12'b0100000_010_01 ; +// 6'd13 : uncompress_id = 12'b0100000_011_01 ; +// 6'd14 : uncompress_id = 12'b0100000_100_01 ; +// 6'd15 : uncompress_id = 12'b0100000_101_01 ; +// // devci +// 6'd16 : uncompress_id = 12'b1000_0000_0000 ; +// // dap +// 6'd17 : uncompress_id = 12'b1000_0000_0001 ; +// // l2m1 (CPU000) +// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ; +// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ; +// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ; +// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ; +// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ; +// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ; +// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ; +// // l2m1 (CPU001) +// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ; +// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ; +// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ; +// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ; +// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ; +// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ; +// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ; +// // l2m1 (L2CC) +// 6'd32 : uncompress_id = 12'b11_000_00101_00 ; +// 6'd33 : uncompress_id = 12'b11_000_01001_00 ; +// 6'd34 : uncompress_id = 12'b11_000_01101_00 ; +// 6'd35 : uncompress_id = 12'b11_000_10011_00 ; +// 6'd36 : uncompress_id = 12'b11_000_10111_00 ; +// 6'd37 : uncompress_id = 12'b11_000_11011_00 ; +// 6'd38 : uncompress_id = 12'b11_000_11111_00 ; +// 6'd39 : uncompress_id = 12'b11_000_00011_00 ; +// 6'd40 : uncompress_id = 12'b11_000_00111_00 ; +// 6'd41 : uncompress_id = 12'b11_000_01011_00 ; +// 6'd42 : uncompress_id = 12'b11_000_01111_00 ; +// 6'd43 : uncompress_id = 12'b11_000_00001_00 ; +// // l2m1 (ACP) +// 6'd44 : uncompress_id = 12'b11_000_10000_00 ; +// 6'd45 : uncompress_id = 12'b11_001_10000_00 ; +// 6'd46 : uncompress_id = 12'b11_010_10000_00 ; +// 6'd47 : uncompress_id = 12'b11_011_10000_00 ; +// 6'd48 : uncompress_id = 12'b11_100_10000_00 ; +// 6'd49 : uncompress_id = 12'b11_101_10000_00 ; +// 6'd50 : uncompress_id = 12'b11_110_10000_00 ; +// 6'd51 : uncompress_id = 12'b11_111_10000_00 ; +// default : uncompress_id = ~0; +// endcase +// end +//endfunction +// +//function [5:0] compress_id; +// input [11:0] id; +// begin +// case (id[11:0]) +// // dmac0 +// 12'b010000_1000_00 : compress_id = 'd1 ; +// 12'b010000_0000_00 : compress_id = 'd2 ; +// 12'b010000_0001_00 : compress_id = 'd3 ; +// 12'b010000_0010_00 : compress_id = 'd4 ; +// 12'b010000_0011_00 : compress_id = 'd5 ; +// 12'b010000_0100_00 : compress_id = 'd6 ; +// 12'b010000_0101_00 : compress_id = 'd7 ; +// 12'b010000_0110_00 : compress_id = 'd8 ; +// 12'b010000_0111_00 : compress_id = 'd9 ; +// // ioum +// 12'b0100000_000_01 : compress_id = 'd10 ; +// 12'b0100000_001_01 : compress_id = 'd11 ; +// 12'b0100000_010_01 : compress_id = 'd12 ; +// 12'b0100000_011_01 : compress_id = 'd13 ; +// 12'b0100000_100_01 : compress_id = 'd14 ; +// 12'b0100000_101_01 : compress_id = 'd15 ; +// // devci +// 12'b1000_0000_0000 : compress_id = 'd16 ; +// // dap +// 12'b1000_0000_0001 : compress_id = 'd17 ; +// // l2m1 (CPU000) +// 12'b11_000_000_00_00 : compress_id = 'd18 ; +// 12'b11_010_000_00_00 : compress_id = 'd19 ; +// 12'b11_011_000_00_00 : compress_id = 'd20 ; +// 12'b11_100_000_00_00 : compress_id = 'd21 ; +// 12'b11_101_000_00_00 : compress_id = 'd22 ; +// 12'b11_110_000_00_00 : compress_id = 'd23 ; +// 12'b11_111_000_00_00 : compress_id = 'd24 ; +// // l2m1 (CPU001) +// 12'b11_000_001_00_00 : compress_id = 'd25 ; +// 12'b11_010_001_00_00 : compress_id = 'd26 ; +// 12'b11_011_001_00_00 : compress_id = 'd27 ; +// 12'b11_100_001_00_00 : compress_id = 'd28 ; +// 12'b11_101_001_00_00 : compress_id = 'd29 ; +// 12'b11_110_001_00_00 : compress_id = 'd30 ; +// 12'b11_111_001_00_00 : compress_id = 'd31 ; +// // l2m1 (L2CC) +// 12'b11_000_00101_00 : compress_id = 'd32 ; +// 12'b11_000_01001_00 : compress_id = 'd33 ; +// 12'b11_000_01101_00 : compress_id = 'd34 ; +// 12'b11_000_10011_00 : compress_id = 'd35 ; +// 12'b11_000_10111_00 : compress_id = 'd36 ; +// 12'b11_000_11011_00 : compress_id = 'd37 ; +// 12'b11_000_11111_00 : compress_id = 'd38 ; +// 12'b11_000_00011_00 : compress_id = 'd39 ; +// 12'b11_000_00111_00 : compress_id = 'd40 ; +// 12'b11_000_01011_00 : compress_id = 'd41 ; +// 12'b11_000_01111_00 : compress_id = 'd42 ; +// 12'b11_000_00001_00 : compress_id = 'd43 ; +// // l2m1 (ACP) +// 12'b11_000_10000_00 : compress_id = 'd44 ; +// 12'b11_001_10000_00 : compress_id = 'd45 ; +// 12'b11_010_10000_00 : compress_id = 'd46 ; +// 12'b11_011_10000_00 : compress_id = 'd47 ; +// 12'b11_100_10000_00 : compress_id = 'd48 ; +// 12'b11_101_10000_00 : compress_id = 'd49 ; +// 12'b11_110_10000_00 : compress_id = 'd50 ; +// 12'b11_111_10000_00 : compress_id = 'd51 ; +// default: compress_id = ~0; +// endcase +// end +//endfunction + +// Modified as per CR 648393 + + function [5:0] compress_id; + input [11:0] id; + begin + compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]); + compress_id[1] = id[8] | id[5] | (~id[11] & id[3]); + compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]); + compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]); + compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]); + compress_id[5] = id[11] & id[10] & ~id[3]; + end + endfunction + + function [11:0] uncompress_id; + input [5:0] id; + begin + case (id[5:0]) + // dmac0 + 6'b000_010 : uncompress_id = 12'b010000_1000_00 ; + 6'b001_000 : uncompress_id = 12'b010000_0000_00 ; + 6'b001_001 : uncompress_id = 12'b010000_0001_00 ; + 6'b001_010 : uncompress_id = 12'b010000_0010_00 ; + 6'b001_011 : uncompress_id = 12'b010000_0011_00 ; + 6'b001_100 : uncompress_id = 12'b010000_0100_00 ; + 6'b001_101 : uncompress_id = 12'b010000_0101_00 ; + 6'b001_110 : uncompress_id = 12'b010000_0110_00 ; + 6'b001_111 : uncompress_id = 12'b010000_0111_00 ; + // ioum + 6'b010_000 : uncompress_id = 12'b0100000_000_01 ; + 6'b010_001 : uncompress_id = 12'b0100000_001_01 ; + 6'b010_010 : uncompress_id = 12'b0100000_010_01 ; + 6'b010_011 : uncompress_id = 12'b0100000_011_01 ; + 6'b010_100 : uncompress_id = 12'b0100000_100_01 ; + 6'b010_101 : uncompress_id = 12'b0100000_101_01 ; + // devci + 6'b000_000 : uncompress_id = 12'b1000_0000_0000 ; + // dap + 6'b000_001 : uncompress_id = 12'b1000_0000_0001 ; + // l2m1 (CPU000) + 6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ; + 6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ; + 6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ; + 6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ; + 6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ; + 6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ; + 6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ; + // l2m1 (CPU001) + 6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ; + 6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ; + 6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ; + 6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ; + 6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ; + 6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ; + 6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ; + // l2m1 (L2CC) + 6'b101_001 : uncompress_id = 12'b11_000_00101_00 ; + 6'b101_010 : uncompress_id = 12'b11_000_01001_00 ; + 6'b101_011 : uncompress_id = 12'b11_000_01101_00 ; + 6'b011_100 : uncompress_id = 12'b11_000_10011_00 ; + 6'b011_101 : uncompress_id = 12'b11_000_10111_00 ; + 6'b011_110 : uncompress_id = 12'b11_000_11011_00 ; + 6'b011_111 : uncompress_id = 12'b11_000_11111_00 ; + 6'b011_000 : uncompress_id = 12'b11_000_00011_00 ; + 6'b011_001 : uncompress_id = 12'b11_000_00111_00 ; + 6'b011_010 : uncompress_id = 12'b11_000_01011_00 ; + 6'b011_011 : uncompress_id = 12'b11_000_01111_00 ; + 6'b101_000 : uncompress_id = 12'b11_000_00001_00 ; + // l2m1 (ACP) + 6'b100_000 : uncompress_id = 12'b11_000_10000_00 ; + 6'b100_001 : uncompress_id = 12'b11_001_10000_00 ; + 6'b100_010 : uncompress_id = 12'b11_010_10000_00 ; + 6'b100_011 : uncompress_id = 12'b11_011_10000_00 ; + 6'b100_100 : uncompress_id = 12'b11_100_10000_00 ; + 6'b100_101 : uncompress_id = 12'b11_101_10000_00 ; + 6'b100_110 : uncompress_id = 12'b11_110_10000_00 ; + 6'b100_111 : uncompress_id = 12'b11_111_10000_00 ; + default : uncompress_id = 12'hx ; + endcase + end + endfunction + + +// Static Remap logic Enablement and Disablement for C_M_AXI0 port + + assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; + assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; + assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; + assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; + assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; + + // Static Remap logic Enablement and Disablement for C_M_AXI1 port + + assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; + assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; + assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; + assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; + assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; + + +//// Compress_id and uncompress_id has been removed to address CR 642527 +//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression. +// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL; +// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL; +// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL; +// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID; +// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID; +// +// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL; +// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL; +// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL; +// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID; +// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID; + + +// Pipeline Stage for ENET0 + +generate + if (C_EN_EMIO_ENET0 == 1) begin + always @(posedge ENET0_GMII_TX_CLK) + begin + ENET0_GMII_TXD <= ENET0_GMII_TXD_i; + ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i; + ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i; + ENET0_GMII_COL_i <= ENET0_GMII_COL; + ENET0_GMII_CRS_i <= ENET0_GMII_CRS; + end + end + else + always@* + begin + ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i; + ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i; + ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i; + ENET0_GMII_COL_i <= 'b0; + ENET0_GMII_CRS_i <= 'b0; + end +endgenerate + +generate + if (C_EN_EMIO_ENET0 == 1) begin + always @(posedge ENET0_GMII_RX_CLK) + begin + ENET0_GMII_RXD_i <= ENET0_GMII_RXD; + ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV; + ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER; + end + end + else + begin + always @* + begin + ENET0_GMII_RXD_i <= 0; + ENET0_GMII_RX_DV_i <= 0; + ENET0_GMII_RX_ER_i <= 0; + end + end +endgenerate + +// Pipeline Stage for ENET1 + +generate + if (C_EN_EMIO_ENET1 == 1) begin + always @(posedge ENET1_GMII_TX_CLK) + begin + ENET1_GMII_TXD <= ENET1_GMII_TXD_i; + ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i; + ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i; + ENET1_GMII_COL_i <= ENET1_GMII_COL; + ENET1_GMII_CRS_i <= ENET1_GMII_CRS; + end + end + else + begin + always@* + begin + ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i; + ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i; + ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i; + ENET1_GMII_COL_i <= 0; + ENET1_GMII_CRS_i <= 0; + end + end +endgenerate + +generate + if (C_EN_EMIO_ENET1 == 1) begin + always @(posedge ENET1_GMII_RX_CLK) + begin + ENET1_GMII_RXD_i <= ENET1_GMII_RXD; + ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV; + ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER; + end + end +else + begin + always @* + begin + ENET1_GMII_RXD_i <= 'b0; + ENET1_GMII_RX_DV_i <= 'b0; + ENET1_GMII_RX_ER_i <= 'b0; + end + end +endgenerate + +// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1. + +generate + if (C_EN_EMIO_TRACE == 1) begin + if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer + + // Pipeline Stage for Traceport ATID + always @(posedge FTMD_TRACEIN_CLK) + begin + FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA; + FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID; + FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID; + end + + assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf; + assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf; + assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf; + + end else begin : gen_trace_buffer + + processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE), + .USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR), + .C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY) + ) + trace_buffer_i ( + .TRACE_CLK(FTMD_TRACEIN_CLK), + .RST(~FCLK_RESET0_N), + .TRACE_VALID_IN(FTMD_TRACEIN_VALID), + .TRACE_DATA_IN(FTMD_TRACEIN_DATA), + .TRACE_ATID_IN(FTMD_TRACEIN_ATID), + .TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf), + .TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf), + .TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf) + ); + + assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf; + assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf; + assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf; + + end + end + else + begin + assign FTMD_TRACEIN_DATA_i = 1'b0; + assign FTMD_TRACEIN_VALID_i = 1'b0; + assign FTMD_TRACEIN_ATID_i = 1'b0; + end +endgenerate + + + // ID Width Control on AXI Slave ports + // S_AXI_GP0 + + function [5:0] id_in_gp0; + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in; + begin + case (C_S_AXI_GP0_ID_WIDTH) + 1: id_in_gp0 = {5'b0, axi_id_gp0_in}; + 2: id_in_gp0 = {4'b0, axi_id_gp0_in}; + 3: id_in_gp0 = {3'b0, axi_id_gp0_in}; + 4: id_in_gp0 = {2'b0, axi_id_gp0_in}; + 5: id_in_gp0 = {1'b0, axi_id_gp0_in}; + 6: id_in_gp0 = axi_id_gp0_in; + default : id_in_gp0 = axi_id_gp0_in; + endcase + end + endfunction + + assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID); + assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID); + assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID); + + function [5:0] id_out_gp0; + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out; + begin + case (C_S_AXI_GP0_ID_WIDTH) + 1: id_out_gp0 = axi_id_gp0_out[0]; + 2: id_out_gp0 = axi_id_gp0_out[1:0]; + 3: id_out_gp0 = axi_id_gp0_out[2:0]; + 4: id_out_gp0 = axi_id_gp0_out[3:0]; + 5: id_out_gp0 = axi_id_gp0_out[4:0]; + 6: id_out_gp0 = axi_id_gp0_out; + default : id_out_gp0 = axi_id_gp0_out; + endcase + end + endfunction + + assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out); + assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out); + + // S_AXI_GP1 + + function [5:0] id_in_gp1; + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in; + begin + case (C_S_AXI_GP1_ID_WIDTH) + 1: id_in_gp1 = {5'b0, axi_id_gp1_in}; + 2: id_in_gp1 = {4'b0, axi_id_gp1_in}; + 3: id_in_gp1 = {3'b0, axi_id_gp1_in}; + 4: id_in_gp1 = {2'b0, axi_id_gp1_in}; + 5: id_in_gp1 = {1'b0, axi_id_gp1_in}; + 6: id_in_gp1 = axi_id_gp1_in; + default : id_in_gp1 = axi_id_gp1_in; + endcase + end + endfunction + + assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID); + assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID); + assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID); + + function [5:0] id_out_gp1; + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out; + begin + case (C_S_AXI_GP1_ID_WIDTH) + 1: id_out_gp1 = axi_id_gp1_out[0]; + 2: id_out_gp1 = axi_id_gp1_out[1:0]; + 3: id_out_gp1 = axi_id_gp1_out[2:0]; + 4: id_out_gp1 = axi_id_gp1_out[3:0]; + 5: id_out_gp1 = axi_id_gp1_out[4:0]; + 6: id_out_gp1 = axi_id_gp1_out; + default : id_out_gp1 = axi_id_gp1_out; + endcase + end + endfunction + + assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out); + assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out); + +// S_AXI_HP0 + + function [5:0] id_in_hp0; + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in; + begin + case (C_S_AXI_HP0_ID_WIDTH) + 1: id_in_hp0 = {5'b0, axi_id_hp0_in}; + 2: id_in_hp0 = {4'b0, axi_id_hp0_in}; + 3: id_in_hp0 = {3'b0, axi_id_hp0_in}; + 4: id_in_hp0 = {2'b0, axi_id_hp0_in}; + 5: id_in_hp0 = {1'b0, axi_id_hp0_in}; + 6: id_in_hp0 = axi_id_hp0_in; + default : id_in_hp0 = axi_id_hp0_in; + endcase + end + endfunction + + assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID); + assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID); + assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID); + + function [5:0] id_out_hp0; + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out; + begin + case (C_S_AXI_HP0_ID_WIDTH) + 1: id_out_hp0 = axi_id_hp0_out[0]; + 2: id_out_hp0 = axi_id_hp0_out[1:0]; + 3: id_out_hp0 = axi_id_hp0_out[2:0]; + 4: id_out_hp0 = axi_id_hp0_out[3:0]; + 5: id_out_hp0 = axi_id_hp0_out[4:0]; + 6: id_out_hp0 = axi_id_hp0_out; + default : id_out_hp0 = axi_id_hp0_out; + endcase + end + endfunction + + assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out); + assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out); + + assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA}; + assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB}; + assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0]; + +// S_AXI_HP1 + + function [5:0] id_in_hp1; + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in; + begin + case (C_S_AXI_HP1_ID_WIDTH) + 1: id_in_hp1 = {5'b0, axi_id_hp1_in}; + 2: id_in_hp1 = {4'b0, axi_id_hp1_in}; + 3: id_in_hp1 = {3'b0, axi_id_hp1_in}; + 4: id_in_hp1 = {2'b0, axi_id_hp1_in}; + 5: id_in_hp1 = {1'b0, axi_id_hp1_in}; + 6: id_in_hp1 = axi_id_hp1_in; + default : id_in_hp1 = axi_id_hp1_in; + endcase + end + endfunction + + + + assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID); + assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID); + assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID); + + function [5:0] id_out_hp1; + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out; + begin + case (C_S_AXI_HP1_ID_WIDTH) + 1: id_out_hp1 = axi_id_hp1_out[0]; + 2: id_out_hp1 = axi_id_hp1_out[1:0]; + 3: id_out_hp1 = axi_id_hp1_out[2:0]; + 4: id_out_hp1 = axi_id_hp1_out[3:0]; + 5: id_out_hp1 = axi_id_hp1_out[4:0]; + 6: id_out_hp1 = axi_id_hp1_out; + default : id_out_hp1 = axi_id_hp1_out; + endcase + end + endfunction + + assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out); + assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out); + + assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA}; + assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB}; + assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0]; + + +// S_AXI_HP2 + + function [5:0] id_in_hp2; + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in; + begin + case (C_S_AXI_HP2_ID_WIDTH) + 1: id_in_hp2 = {5'b0, axi_id_hp2_in}; + 2: id_in_hp2 = {4'b0, axi_id_hp2_in}; + 3: id_in_hp2 = {3'b0, axi_id_hp2_in}; + 4: id_in_hp2 = {2'b0, axi_id_hp2_in}; + 5: id_in_hp2 = {1'b0, axi_id_hp2_in}; + 6: id_in_hp2 = axi_id_hp2_in; + default : id_in_hp2 = axi_id_hp2_in; + endcase + end + endfunction + + assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID); + assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID); + assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID); + + + function [5:0] id_out_hp2; + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out; + begin + case (C_S_AXI_HP2_ID_WIDTH) + 1: id_out_hp2 = axi_id_hp2_out[0]; + 2: id_out_hp2 = axi_id_hp2_out[1:0]; + 3: id_out_hp2 = axi_id_hp2_out[2:0]; + 4: id_out_hp2 = axi_id_hp2_out[3:0]; + 5: id_out_hp2 = axi_id_hp2_out[4:0]; + 6: id_out_hp2 = axi_id_hp2_out; + default : id_out_hp2 = axi_id_hp2_out; + endcase + end + endfunction + + assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out); + assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out); + + assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA}; + assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB}; + assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0]; + + +// S_AXI_HP3 + + function [5:0] id_in_hp3; + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in; + begin + case (C_S_AXI_HP3_ID_WIDTH) + 1: id_in_hp3 = {5'b0, axi_id_hp3_in}; + 2: id_in_hp3 = {4'b0, axi_id_hp3_in}; + 3: id_in_hp3 = {3'b0, axi_id_hp3_in}; + 4: id_in_hp3 = {2'b0, axi_id_hp3_in}; + 5: id_in_hp3 = {1'b0, axi_id_hp3_in}; + 6: id_in_hp3 = axi_id_hp3_in; + default : id_in_hp3 = axi_id_hp3_in; + endcase + end + endfunction + + assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID); + assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID); + assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID); + + + + function [5:0] id_out_hp3; + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out; + begin + case (C_S_AXI_HP3_ID_WIDTH) + 1: id_out_hp3 = axi_id_hp3_out[0]; + 2: id_out_hp3 = axi_id_hp3_out[1:0]; + 3: id_out_hp3 = axi_id_hp3_out[2:0]; + 4: id_out_hp3 = axi_id_hp3_out[3:0]; + 5: id_out_hp3 = axi_id_hp3_out[4:0]; + 6: id_out_hp3 = axi_id_hp3_out; + default : id_out_hp3 = axi_id_hp3_out; + endcase + end + endfunction + + assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out); + assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out); + + assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA}; + assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB}; + assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0]; + + +// S_AXI_ACP + + function [2:0] id_in_acp; + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in; + begin + case (C_S_AXI_ACP_ID_WIDTH) + 1: id_in_acp = {2'b0, axi_id_acp_in}; + 2: id_in_acp = {1'b0, axi_id_acp_in}; + 3: id_in_acp = axi_id_acp_in; + default : id_in_acp = axi_id_acp_in; + endcase + end + endfunction + + assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W); + assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W); + assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W); + + function [2:0] id_out_acp; + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out; + begin + case (C_S_AXI_ACP_ID_WIDTH) + 1: id_out_acp = axi_id_acp_out[0]; + 2: id_out_acp = axi_id_acp_out[1:0]; + 3: id_out_acp = axi_id_acp_out; + default : id_out_acp = axi_id_acp_out; + endcase + end + endfunction + + assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out); + assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out); + +// FMIO Tristate Inversion logic + +//FMIO I2C0 +assign I2C0_SDA_T = ~ I2C0_SDA_T_n; +assign I2C0_SCL_T = ~ I2C0_SCL_T_n; +//FMIO I2C1 +assign I2C1_SDA_T = ~ I2C1_SDA_T_n; +assign I2C1_SCL_T = ~ I2C1_SCL_T_n; +//FMIO SPI0 +assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n; +assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n; +assign SPI0_MISO_T = ~ SPI0_MISO_T_n; +assign SPI0_SS_T = ~ SPI0_SS_T_n; +//FMIO SPI1 +assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n; +assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n; +assign SPI1_MISO_T = ~ SPI1_MISO_T_n; +assign SPI1_SS_T = ~ SPI1_SS_T_n; + + + +// EMIO GEM0 MDIO +assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n; + +// EMIO GEM1 MDIO +assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n; + +// EMIO GPIO +assign GPIO_T = ~ GPIO_T_n; + +// EMIO GPIO Width Control + + function [63:0] gpio_width_adjust_in; + input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in; + begin + case (C_EMIO_GPIO_WIDTH) + 1: gpio_width_adjust_in = {63'b0, gpio_in}; + 2: gpio_width_adjust_in = {62'b0, gpio_in}; + 3: gpio_width_adjust_in = {61'b0, gpio_in}; + 4: gpio_width_adjust_in = {60'b0, gpio_in}; + 5: gpio_width_adjust_in = {59'b0, gpio_in}; + 6: gpio_width_adjust_in = {58'b0, gpio_in}; + 7: gpio_width_adjust_in = {57'b0, gpio_in}; + 8: gpio_width_adjust_in = {56'b0, gpio_in}; + 9: gpio_width_adjust_in = {55'b0, gpio_in}; + 10: gpio_width_adjust_in = {54'b0, gpio_in}; + 11: gpio_width_adjust_in = {53'b0, gpio_in}; + 12: gpio_width_adjust_in = {52'b0, gpio_in}; + 13: gpio_width_adjust_in = {51'b0, gpio_in}; + 14: gpio_width_adjust_in = {50'b0, gpio_in}; + 15: gpio_width_adjust_in = {49'b0, gpio_in}; + 16: gpio_width_adjust_in = {48'b0, gpio_in}; + 17: gpio_width_adjust_in = {47'b0, gpio_in}; + 18: gpio_width_adjust_in = {46'b0, gpio_in}; + 19: gpio_width_adjust_in = {45'b0, gpio_in}; + 20: gpio_width_adjust_in = {44'b0, gpio_in}; + 21: gpio_width_adjust_in = {43'b0, gpio_in}; + 22: gpio_width_adjust_in = {42'b0, gpio_in}; + 23: gpio_width_adjust_in = {41'b0, gpio_in}; + 24: gpio_width_adjust_in = {40'b0, gpio_in}; + 25: gpio_width_adjust_in = {39'b0, gpio_in}; + 26: gpio_width_adjust_in = {38'b0, gpio_in}; + 27: gpio_width_adjust_in = {37'b0, gpio_in}; + 28: gpio_width_adjust_in = {36'b0, gpio_in}; + 29: gpio_width_adjust_in = {35'b0, gpio_in}; + 30: gpio_width_adjust_in = {34'b0, gpio_in}; + 31: gpio_width_adjust_in = {33'b0, gpio_in}; + 32: gpio_width_adjust_in = {32'b0, gpio_in}; + 33: gpio_width_adjust_in = {31'b0, gpio_in}; + 34: gpio_width_adjust_in = {30'b0, gpio_in}; + 35: gpio_width_adjust_in = {29'b0, gpio_in}; + 36: gpio_width_adjust_in = {28'b0, gpio_in}; + 37: gpio_width_adjust_in = {27'b0, gpio_in}; + 38: gpio_width_adjust_in = {26'b0, gpio_in}; + 39: gpio_width_adjust_in = {25'b0, gpio_in}; + 40: gpio_width_adjust_in = {24'b0, gpio_in}; + 41: gpio_width_adjust_in = {23'b0, gpio_in}; + 42: gpio_width_adjust_in = {22'b0, gpio_in}; + 43: gpio_width_adjust_in = {21'b0, gpio_in}; + 44: gpio_width_adjust_in = {20'b0, gpio_in}; + 45: gpio_width_adjust_in = {19'b0, gpio_in}; + 46: gpio_width_adjust_in = {18'b0, gpio_in}; + 47: gpio_width_adjust_in = {17'b0, gpio_in}; + 48: gpio_width_adjust_in = {16'b0, gpio_in}; + 49: gpio_width_adjust_in = {15'b0, gpio_in}; + 50: gpio_width_adjust_in = {14'b0, gpio_in}; + 51: gpio_width_adjust_in = {13'b0, gpio_in}; + 52: gpio_width_adjust_in = {12'b0, gpio_in}; + 53: gpio_width_adjust_in = {11'b0, gpio_in}; + 54: gpio_width_adjust_in = {10'b0, gpio_in}; + 55: gpio_width_adjust_in = {9'b0, gpio_in}; + 56: gpio_width_adjust_in = {8'b0, gpio_in}; + 57: gpio_width_adjust_in = {7'b0, gpio_in}; + 58: gpio_width_adjust_in = {6'b0, gpio_in}; + 59: gpio_width_adjust_in = {5'b0, gpio_in}; + 60: gpio_width_adjust_in = {4'b0, gpio_in}; + 61: gpio_width_adjust_in = {3'b0, gpio_in}; + 62: gpio_width_adjust_in = {2'b0, gpio_in}; + 63: gpio_width_adjust_in = {1'b0, gpio_in}; + 64: gpio_width_adjust_in = gpio_in; + default : gpio_width_adjust_in = gpio_in; + endcase + end + endfunction + + assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I); + + + function [63:0] gpio_width_adjust_out; + input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o; + begin + case (C_EMIO_GPIO_WIDTH) + 1: gpio_width_adjust_out = gpio_o[0]; + 2: gpio_width_adjust_out = gpio_o[1:0]; + 3: gpio_width_adjust_out = gpio_o[2:0]; + 4: gpio_width_adjust_out = gpio_o[3:0]; + 5: gpio_width_adjust_out = gpio_o[4:0]; + 6: gpio_width_adjust_out = gpio_o[5:0]; + 7: gpio_width_adjust_out = gpio_o[6:0]; + 8: gpio_width_adjust_out = gpio_o[7:0]; + 9: gpio_width_adjust_out = gpio_o[8:0]; + 10: gpio_width_adjust_out = gpio_o[9:0]; + 11: gpio_width_adjust_out = gpio_o[10:0]; + 12: gpio_width_adjust_out = gpio_o[11:0]; + 13: gpio_width_adjust_out = gpio_o[12:0]; + 14: gpio_width_adjust_out = gpio_o[13:0]; + 15: gpio_width_adjust_out = gpio_o[14:0]; + 16: gpio_width_adjust_out = gpio_o[15:0]; + 17: gpio_width_adjust_out = gpio_o[16:0]; + 18: gpio_width_adjust_out = gpio_o[17:0]; + 19: gpio_width_adjust_out = gpio_o[18:0]; + 20: gpio_width_adjust_out = gpio_o[19:0]; + 21: gpio_width_adjust_out = gpio_o[20:0]; + 22: gpio_width_adjust_out = gpio_o[21:0]; + 23: gpio_width_adjust_out = gpio_o[22:0]; + 24: gpio_width_adjust_out = gpio_o[23:0]; + 25: gpio_width_adjust_out = gpio_o[24:0]; + 26: gpio_width_adjust_out = gpio_o[25:0]; + 27: gpio_width_adjust_out = gpio_o[26:0]; + 28: gpio_width_adjust_out = gpio_o[27:0]; + 29: gpio_width_adjust_out = gpio_o[28:0]; + 30: gpio_width_adjust_out = gpio_o[29:0]; + 31: gpio_width_adjust_out = gpio_o[30:0]; + 32: gpio_width_adjust_out = gpio_o[31:0]; + 33: gpio_width_adjust_out = gpio_o[32:0]; + 34: gpio_width_adjust_out = gpio_o[33:0]; + 35: gpio_width_adjust_out = gpio_o[34:0]; + 36: gpio_width_adjust_out = gpio_o[35:0]; + 37: gpio_width_adjust_out = gpio_o[36:0]; + 38: gpio_width_adjust_out = gpio_o[37:0]; + 39: gpio_width_adjust_out = gpio_o[38:0]; + 40: gpio_width_adjust_out = gpio_o[39:0]; + 41: gpio_width_adjust_out = gpio_o[40:0]; + 42: gpio_width_adjust_out = gpio_o[41:0]; + 43: gpio_width_adjust_out = gpio_o[42:0]; + 44: gpio_width_adjust_out = gpio_o[43:0]; + 45: gpio_width_adjust_out = gpio_o[44:0]; + 46: gpio_width_adjust_out = gpio_o[45:0]; + 47: gpio_width_adjust_out = gpio_o[46:0]; + 48: gpio_width_adjust_out = gpio_o[47:0]; + 49: gpio_width_adjust_out = gpio_o[48:0]; + 50: gpio_width_adjust_out = gpio_o[49:0]; + 51: gpio_width_adjust_out = gpio_o[50:0]; + 52: gpio_width_adjust_out = gpio_o[51:0]; + 53: gpio_width_adjust_out = gpio_o[52:0]; + 54: gpio_width_adjust_out = gpio_o[53:0]; + 55: gpio_width_adjust_out = gpio_o[54:0]; + 56: gpio_width_adjust_out = gpio_o[55:0]; + 57: gpio_width_adjust_out = gpio_o[56:0]; + 58: gpio_width_adjust_out = gpio_o[57:0]; + 59: gpio_width_adjust_out = gpio_o[58:0]; + 60: gpio_width_adjust_out = gpio_o[59:0]; + 61: gpio_width_adjust_out = gpio_o[60:0]; + 62: gpio_width_adjust_out = gpio_o[61:0]; + 63: gpio_width_adjust_out = gpio_o[62:0]; + 64: gpio_width_adjust_out = gpio_o; + default : gpio_width_adjust_out = gpio_o; + endcase + end + endfunction + + assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out); + assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n); + +// Adding OBUFT to JTAG out port +generate + if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE + OBUFT jtag_obuft_inst ( + .O(PJTAG_TDO), + .I(PJTAG_TDO_O), + .T(PJTAG_TDO_T) + ); + end + else + begin + assign PJTAG_TDO = 1'b0; + end +endgenerate +// ------- +// EMIO PJTAG +assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n; + +// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon, +// FOR Other SI REV, inversion is required + +assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n); +assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]); + +// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon, +// FOR Other SI REV, inversion is required +assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n); +assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]); + +// FCLK_CLK optional clock buffers + +generate + if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0 + BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0])); + end + if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1 + BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1])); + end + if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2 + BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2])); + end + if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3 + BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3])); + end +endgenerate + +assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0]; +assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1]; +assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2]; +assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3]; + +assign FCLK_CLK0 = FCLK_CLK0_temp; + +// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports + +BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n)); +BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE)); +BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n)); +BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk)); +BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n)); +BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB)); +BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT)); +BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n)); +BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB)); +BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN)); +BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP)); +BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB)); +BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK)); +BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB)); + +genvar i; +generate + for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin + BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i])); + end +endgenerate + +generate + for (i=0; i < 3; i=i+1) begin + BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i])); + end +endgenerate + +generate + for (i=0; i < 15; i=i+1) begin + BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i])); + end +endgenerate + +generate + for (i=0; i < C_DM_WIDTH; i=i+1) begin + BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i])); + end +endgenerate + +generate + for (i=0; i < C_DQ_WIDTH; i=i+1) begin + BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i])); + end +endgenerate + +generate + for (i=0; i < C_DQS_WIDTH; i=i+1) begin + BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i])); + end +endgenerate + +generate + for (i=0; i < C_DQS_WIDTH; i=i+1) begin + BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i])); + end +endgenerate + +// Connect FCLK in case of disable the AXI port for non Secure Transaction +//Start + + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin + assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin + assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin + assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin + assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK; + end +endgenerate + +//Start + + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin + assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin + assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin + assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin + assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin + assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK; + end +endgenerate + +assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ; +assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ; +assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ; +assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ; + + +//END +//==================== +//PSS TOP +//==================== +generate +if (C_PACKAGE_NAME == "clg225" ) begin + wire [21:0] dummy; + PS7 PS7_i ( + .DMA0DATYPE (DMA0_DATYPE ), + .DMA0DAVALID (DMA0_DAVALID), + .DMA0DRREADY (DMA0_DRREADY), + .DMA0RSTN (DMA0_RSTN ), + .DMA1DATYPE (DMA1_DATYPE ), + .DMA1DAVALID (DMA1_DAVALID), + .DMA1DRREADY (DMA1_DRREADY), + .DMA1RSTN (DMA1_RSTN ), + .DMA2DATYPE (DMA2_DATYPE ), + .DMA2DAVALID (DMA2_DAVALID), + .DMA2DRREADY (DMA2_DRREADY), + .DMA2RSTN (DMA2_RSTN ), + .DMA3DATYPE (DMA3_DATYPE ), + .DMA3DAVALID (DMA3_DAVALID), + .DMA3DRREADY (DMA3_DRREADY), + .DMA3RSTN (DMA3_RSTN ), + .EMIOCAN0PHYTX (CAN0_PHY_TX ), + .EMIOCAN1PHYTX (CAN1_PHY_TX ), + .EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ), + .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i), + .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i), + .EMIOENET0MDIOMDC (ENET0_MDIO_MDC), + .EMIOENET0MDIOO (ENET0_MDIO_O ), + .EMIOENET0MDIOTN (ENET0_MDIO_T_n ), + .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX), + .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX), + .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX), + .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX), + .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX), + .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX), + .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX), + .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX), + .EMIOENET0SOFRX (ENET0_SOF_RX), + .EMIOENET0SOFTX (ENET0_SOF_TX), + .EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i), + .EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i), + .EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i), + .EMIOENET1MDIOMDC (ENET1_MDIO_MDC), + .EMIOENET1MDIOO (ENET1_MDIO_O), + .EMIOENET1MDIOTN (ENET1_MDIO_T_n), + .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX), + .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX), + .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX), + .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX), + .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX), + .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX), + .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX), + .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX), + .EMIOENET1SOFRX (ENET1_SOF_RX), + .EMIOENET1SOFTX (ENET1_SOF_TX), + .EMIOGPIOO (gpio_out), + .EMIOGPIOTN (gpio_out_t_n), + .EMIOI2C0SCLO (I2C0_SCL_O), + .EMIOI2C0SCLTN (I2C0_SCL_T_n), + .EMIOI2C0SDAO (I2C0_SDA_O), + .EMIOI2C0SDATN (I2C0_SDA_T_n), + .EMIOI2C1SCLO (I2C1_SCL_O), + .EMIOI2C1SCLTN (I2C1_SCL_T_n), + .EMIOI2C1SDAO (I2C1_SDA_O), + .EMIOI2C1SDATN (I2C1_SDA_T_n), + .EMIOPJTAGTDO (PJTAG_TDO_O), + .EMIOPJTAGTDTN (PJTAG_TDO_T_n), + .EMIOSDIO0BUSPOW (SDIO0_BUSPOW), + .EMIOSDIO0CLK (SDIO0_CLK ), + .EMIOSDIO0CMDO (SDIO0_CMD_O ), + .EMIOSDIO0CMDTN (SDIO0_CMD_T_n ), + .EMIOSDIO0DATAO (SDIO0_DATA_O), + .EMIOSDIO0DATATN (SDIO0_DATA_T_n), + .EMIOSDIO0LED (SDIO0_LED), + .EMIOSDIO1BUSPOW (SDIO1_BUSPOW), + .EMIOSDIO1CLK (SDIO1_CLK ), + .EMIOSDIO1CMDO (SDIO1_CMD_O ), + .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ), + .EMIOSDIO1DATAO (SDIO1_DATA_O), + .EMIOSDIO1DATATN (SDIO1_DATA_T_n), + .EMIOSDIO1LED (SDIO1_LED), + .EMIOSPI0MO (SPI0_MOSI_O), + .EMIOSPI0MOTN (SPI0_MOSI_T_n), + .EMIOSPI0SCLKO (SPI0_SCLK_O), + .EMIOSPI0SCLKTN (SPI0_SCLK_T_n), + .EMIOSPI0SO (SPI0_MISO_O), + .EMIOSPI0STN (SPI0_MISO_T_n), + .EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}), + .EMIOSPI0SSNTN (SPI0_SS_T_n), + .EMIOSPI1MO (SPI1_MOSI_O), + .EMIOSPI1MOTN (SPI1_MOSI_T_n), + .EMIOSPI1SCLKO (SPI1_SCLK_O), + .EMIOSPI1SCLKTN (SPI1_SCLK_T_n), + .EMIOSPI1SO (SPI1_MISO_O), + .EMIOSPI1STN (SPI1_MISO_T_n), + .EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}), + .EMIOSPI1SSNTN (SPI1_SS_T_n), + .EMIOTRACECTL (TRACE_CTL_i), + .EMIOTRACEDATA (TRACE_DATA_i), + .EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}), + .EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}), + .EMIOUART0DTRN (UART0_DTRN), + .EMIOUART0RTSN (UART0_RTSN), + .EMIOUART0TX (UART0_TX ), + .EMIOUART1DTRN (UART1_DTRN), + .EMIOUART1RTSN (UART1_RTSN), + .EMIOUART1TX (UART1_TX ), + .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL), + .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT), + .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL), + .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT), + .EMIOWDTRSTO (WDT_RST_OUT), + .EVENTEVENTO (EVENT_EVENTO), + .EVENTSTANDBYWFE (EVENT_STANDBYWFE), + .EVENTSTANDBYWFI (EVENT_STANDBYWFI), + .FCLKCLK (FCLK_CLK_unbuffered), + .FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}), + .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT), + .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT), + .FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}), + .FTMTP2FDEBUG (FTMT_P2F_DEBUG ), + .FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), + .IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}), + .MAXIGP0ARADDR (M_AXI_GP0_ARADDR), + .MAXIGP0ARBURST (M_AXI_GP0_ARBURST), + .MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t), + .MAXIGP0ARESETN (M_AXI_GP0_ARESETN), + .MAXIGP0ARID (M_AXI_GP0_ARID_FULL ), + .MAXIGP0ARLEN (M_AXI_GP0_ARLEN ), + .MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ), + .MAXIGP0ARPROT (M_AXI_GP0_ARPROT ), + .MAXIGP0ARQOS (M_AXI_GP0_ARQOS ), + .MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ), + .MAXIGP0ARVALID (M_AXI_GP0_ARVALID), + .MAXIGP0AWADDR (M_AXI_GP0_AWADDR ), + .MAXIGP0AWBURST (M_AXI_GP0_AWBURST), + .MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t), + .MAXIGP0AWID (M_AXI_GP0_AWID_FULL ), + .MAXIGP0AWLEN (M_AXI_GP0_AWLEN ), + .MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ), + .MAXIGP0AWPROT (M_AXI_GP0_AWPROT ), + .MAXIGP0AWQOS (M_AXI_GP0_AWQOS ), + .MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ), + .MAXIGP0AWVALID (M_AXI_GP0_AWVALID), + .MAXIGP0BREADY (M_AXI_GP0_BREADY ), + .MAXIGP0RREADY (M_AXI_GP0_RREADY ), + .MAXIGP0WDATA (M_AXI_GP0_WDATA ), + .MAXIGP0WID (M_AXI_GP0_WID_FULL ), + .MAXIGP0WLAST (M_AXI_GP0_WLAST ), + .MAXIGP0WSTRB (M_AXI_GP0_WSTRB ), + .MAXIGP0WVALID (M_AXI_GP0_WVALID ), + .MAXIGP1ARADDR (M_AXI_GP1_ARADDR ), + .MAXIGP1ARBURST (M_AXI_GP1_ARBURST), + .MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t), + .MAXIGP1ARESETN (M_AXI_GP1_ARESETN), + .MAXIGP1ARID (M_AXI_GP1_ARID_FULL ), + .MAXIGP1ARLEN (M_AXI_GP1_ARLEN ), + .MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ), + .MAXIGP1ARPROT (M_AXI_GP1_ARPROT ), + .MAXIGP1ARQOS (M_AXI_GP1_ARQOS ), + .MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ), + .MAXIGP1ARVALID (M_AXI_GP1_ARVALID), + .MAXIGP1AWADDR (M_AXI_GP1_AWADDR ), + .MAXIGP1AWBURST (M_AXI_GP1_AWBURST), + .MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t), + .MAXIGP1AWID (M_AXI_GP1_AWID_FULL ), + .MAXIGP1AWLEN (M_AXI_GP1_AWLEN ), + .MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ), + .MAXIGP1AWPROT (M_AXI_GP1_AWPROT ), + .MAXIGP1AWQOS (M_AXI_GP1_AWQOS ), + .MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ), + .MAXIGP1AWVALID (M_AXI_GP1_AWVALID), + .MAXIGP1BREADY (M_AXI_GP1_BREADY ), + .MAXIGP1RREADY (M_AXI_GP1_RREADY ), + .MAXIGP1WDATA (M_AXI_GP1_WDATA ), + .MAXIGP1WID (M_AXI_GP1_WID_FULL ), + .MAXIGP1WLAST (M_AXI_GP1_WLAST ), + .MAXIGP1WSTRB (M_AXI_GP1_WSTRB ), + .MAXIGP1WVALID (M_AXI_GP1_WVALID ), + .SAXIACPARESETN (S_AXI_ACP_ARESETN), + .SAXIACPARREADY (SAXIACPARREADY_W), + .SAXIACPAWREADY (SAXIACPAWREADY_W), + .SAXIACPBID (S_AXI_ACP_BID_out ), + .SAXIACPBRESP (SAXIACPBRESP_W ), + .SAXIACPBVALID (SAXIACPBVALID_W ), + .SAXIACPRDATA (SAXIACPRDATA_W ), + .SAXIACPRID (S_AXI_ACP_RID_out), + .SAXIACPRLAST (SAXIACPRLAST_W ), + .SAXIACPRRESP (SAXIACPRRESP_W ), + .SAXIACPRVALID (SAXIACPRVALID_W ), + .SAXIACPWREADY (SAXIACPWREADY_W ), + .SAXIGP0ARESETN (S_AXI_GP0_ARESETN), + .SAXIGP0ARREADY (S_AXI_GP0_ARREADY), + .SAXIGP0AWREADY (S_AXI_GP0_AWREADY), + .SAXIGP0BID (S_AXI_GP0_BID_out), + .SAXIGP0BRESP (S_AXI_GP0_BRESP ), + .SAXIGP0BVALID (S_AXI_GP0_BVALID ), + .SAXIGP0RDATA (S_AXI_GP0_RDATA ), + .SAXIGP0RID (S_AXI_GP0_RID_out ), + .SAXIGP0RLAST (S_AXI_GP0_RLAST ), + .SAXIGP0RRESP (S_AXI_GP0_RRESP ), + .SAXIGP0RVALID (S_AXI_GP0_RVALID ), + .SAXIGP0WREADY (S_AXI_GP0_WREADY ), + .SAXIGP1ARESETN (S_AXI_GP1_ARESETN), + .SAXIGP1ARREADY (S_AXI_GP1_ARREADY), + .SAXIGP1AWREADY (S_AXI_GP1_AWREADY), + .SAXIGP1BID (S_AXI_GP1_BID_out ), + .SAXIGP1BRESP (S_AXI_GP1_BRESP ), + .SAXIGP1BVALID (S_AXI_GP1_BVALID ), + .SAXIGP1RDATA (S_AXI_GP1_RDATA ), + .SAXIGP1RID (S_AXI_GP1_RID_out ), + .SAXIGP1RLAST (S_AXI_GP1_RLAST ), + .SAXIGP1RRESP (S_AXI_GP1_RRESP ), + .SAXIGP1RVALID (S_AXI_GP1_RVALID ), + .SAXIGP1WREADY (S_AXI_GP1_WREADY ), + .SAXIHP0ARESETN (S_AXI_HP0_ARESETN), + .SAXIHP0ARREADY (S_AXI_HP0_ARREADY), + .SAXIHP0AWREADY (S_AXI_HP0_AWREADY), + .SAXIHP0BID (S_AXI_HP0_BID_out ), + .SAXIHP0BRESP (S_AXI_HP0_BRESP ), + .SAXIHP0BVALID (S_AXI_HP0_BVALID ), + .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT), + .SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT), + .SAXIHP0RDATA (S_AXI_HP0_RDATA_out), + .SAXIHP0RID (S_AXI_HP0_RID_out ), + .SAXIHP0RLAST (S_AXI_HP0_RLAST), + .SAXIHP0RRESP (S_AXI_HP0_RRESP), + .SAXIHP0RVALID (S_AXI_HP0_RVALID), + .SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT), + .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT), + .SAXIHP0WREADY (S_AXI_HP0_WREADY), + .SAXIHP1ARESETN (S_AXI_HP1_ARESETN), + .SAXIHP1ARREADY (S_AXI_HP1_ARREADY), + .SAXIHP1AWREADY (S_AXI_HP1_AWREADY), + .SAXIHP1BID (S_AXI_HP1_BID_out ), + .SAXIHP1BRESP (S_AXI_HP1_BRESP ), + .SAXIHP1BVALID (S_AXI_HP1_BVALID ), + .SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ), + .SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ), + .SAXIHP1RDATA (S_AXI_HP1_RDATA_out), + .SAXIHP1RID (S_AXI_HP1_RID_out ), + .SAXIHP1RLAST (S_AXI_HP1_RLAST ), + .SAXIHP1RRESP (S_AXI_HP1_RRESP ), + .SAXIHP1RVALID (S_AXI_HP1_RVALID), + .SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT), + .SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT), + .SAXIHP1WREADY (S_AXI_HP1_WREADY), + .SAXIHP2ARESETN (S_AXI_HP2_ARESETN), + .SAXIHP2ARREADY (S_AXI_HP2_ARREADY), + .SAXIHP2AWREADY (S_AXI_HP2_AWREADY), + .SAXIHP2BID (S_AXI_HP2_BID_out ), + .SAXIHP2BRESP (S_AXI_HP2_BRESP), + .SAXIHP2BVALID (S_AXI_HP2_BVALID), + .SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT), + .SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT), + .SAXIHP2RDATA (S_AXI_HP2_RDATA_out), + .SAXIHP2RID (S_AXI_HP2_RID_out ), + .SAXIHP2RLAST (S_AXI_HP2_RLAST), + .SAXIHP2RRESP (S_AXI_HP2_RRESP), + .SAXIHP2RVALID (S_AXI_HP2_RVALID), + .SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT), + .SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT), + .SAXIHP2WREADY (S_AXI_HP2_WREADY), + .SAXIHP3ARESETN (S_AXI_HP3_ARESETN), + .SAXIHP3ARREADY (S_AXI_HP3_ARREADY), + .SAXIHP3AWREADY (S_AXI_HP3_AWREADY), + .SAXIHP3BID (S_AXI_HP3_BID_out), + .SAXIHP3BRESP (S_AXI_HP3_BRESP), + .SAXIHP3BVALID (S_AXI_HP3_BVALID), + .SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT), + .SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT), + .SAXIHP3RDATA (S_AXI_HP3_RDATA_out), + .SAXIHP3RID (S_AXI_HP3_RID_out), + .SAXIHP3RLAST (S_AXI_HP3_RLAST), + .SAXIHP3RRESP (S_AXI_HP3_RRESP), + .SAXIHP3RVALID (S_AXI_HP3_RVALID), + .SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT), + .SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT), + .SAXIHP3WREADY (S_AXI_HP3_WREADY), + .DDRARB (DDR_ARB), + .DMA0ACLK (DMA0_ACLK ), + .DMA0DAREADY (DMA0_DAREADY), + .DMA0DRLAST (DMA0_DRLAST ), + .DMA0DRTYPE (DMA0_DRTYPE), + .DMA0DRVALID (DMA0_DRVALID), + .DMA1ACLK (DMA1_ACLK ), + .DMA1DAREADY (DMA1_DAREADY), + .DMA1DRLAST (DMA1_DRLAST ), + .DMA1DRTYPE (DMA1_DRTYPE), + .DMA1DRVALID (DMA1_DRVALID), + .DMA2ACLK (DMA2_ACLK ), + .DMA2DAREADY (DMA2_DAREADY), + .DMA2DRLAST (DMA2_DRLAST ), + .DMA2DRTYPE (DMA2_DRTYPE), + .DMA2DRVALID (DMA2_DRVALID), + .DMA3ACLK (DMA3_ACLK ), + .DMA3DAREADY (DMA3_DAREADY), + .DMA3DRLAST (DMA3_DRLAST ), + .DMA3DRTYPE (DMA3_DRTYPE), + .DMA3DRVALID (DMA3_DRVALID), + .EMIOCAN0PHYRX (CAN0_PHY_RX), + .EMIOCAN1PHYRX (CAN1_PHY_RX), + .EMIOENET0EXTINTIN (ENET0_EXT_INTIN), + .EMIOENET0GMIICOL (ENET0_GMII_COL_i), + .EMIOENET0GMIICRS (ENET0_GMII_CRS_i), + .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK), + .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i), + .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i), + .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i), + .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK), + .EMIOENET0MDIOI (ENET0_MDIO_I), + .EMIOENET1EXTINTIN (ENET1_EXT_INTIN), + .EMIOENET1GMIICOL (ENET1_GMII_COL_i), + .EMIOENET1GMIICRS (ENET1_GMII_CRS_i), + .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK), + .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i), + .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i), + .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i), + .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK), + .EMIOENET1MDIOI (ENET1_MDIO_I), + .EMIOGPIOI (gpio_in63_0 ), + .EMIOI2C0SCLI (I2C0_SCL_I), + .EMIOI2C0SDAI (I2C0_SDA_I), + .EMIOI2C1SCLI (I2C1_SCL_I), + .EMIOI2C1SDAI (I2C1_SDA_I), + .EMIOPJTAGTCK (PJTAG_TCK), + .EMIOPJTAGTDI (PJTAG_TDI), + .EMIOPJTAGTMS (PJTAG_TMS), + .EMIOSDIO0CDN (SDIO0_CDN), + .EMIOSDIO0CLKFB (SDIO0_CLK_FB ), + .EMIOSDIO0CMDI (SDIO0_CMD_I ), + .EMIOSDIO0DATAI (SDIO0_DATA_I ), + .EMIOSDIO0WP (SDIO0_WP), + .EMIOSDIO1CDN (SDIO1_CDN), + .EMIOSDIO1CLKFB (SDIO1_CLK_FB ), + .EMIOSDIO1CMDI (SDIO1_CMD_I ), + .EMIOSDIO1DATAI (SDIO1_DATA_I ), + .EMIOSDIO1WP (SDIO1_WP), + .EMIOSPI0MI (SPI0_MISO_I), + .EMIOSPI0SCLKI (SPI0_SCLK_I), + .EMIOSPI0SI (SPI0_MOSI_I), + .EMIOSPI0SSIN (SPI0_SS_I), + .EMIOSPI1MI (SPI1_MISO_I), + .EMIOSPI1SCLKI (SPI1_SCLK_I), + .EMIOSPI1SI (SPI1_MOSI_I), + .EMIOSPI1SSIN (SPI1_SS_I), + .EMIOSRAMINTIN (SRAM_INTIN), + .EMIOTRACECLK (TRACE_CLK), + .EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}), + .EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}), + .EMIOUART0CTSN (UART0_CTSN), + .EMIOUART0DCDN (UART0_DCDN), + .EMIOUART0DSRN (UART0_DSRN), + .EMIOUART0RIN (UART0_RIN ), + .EMIOUART0RX (UART0_RX ), + .EMIOUART1CTSN (UART1_CTSN), + .EMIOUART1DCDN (UART1_DCDN), + .EMIOUART1DSRN (UART1_DSRN), + .EMIOUART1RIN (UART1_RIN ), + .EMIOUART1RX (UART1_RX ), + .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT), + .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT), + .EMIOWDTCLKI (WDT_CLK_IN), + .EVENTEVENTI (EVENT_EVENTI), + .FCLKCLKTRIGN (fclk_clktrig_gnd), + .FPGAIDLEN (FPGA_IDLE_N), + .FTMDTRACEINATID (FTMD_TRACEIN_ATID_i), + .FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK), + .FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i), + .FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i), + .FTMTF2PDEBUG (FTMT_F2P_DEBUG ), + .FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}), + .FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), + .IRQF2P (irq_f2p_i), + .MAXIGP0ACLK (M_AXI_GP0_ACLK_temp), + .MAXIGP0ARREADY (M_AXI_GP0_ARREADY), + .MAXIGP0AWREADY (M_AXI_GP0_AWREADY), + .MAXIGP0BID (M_AXI_GP0_BID_FULL ), + .MAXIGP0BRESP (M_AXI_GP0_BRESP ), + .MAXIGP0BVALID (M_AXI_GP0_BVALID ), + .MAXIGP0RDATA (M_AXI_GP0_RDATA ), + .MAXIGP0RID (M_AXI_GP0_RID_FULL ), + .MAXIGP0RLAST (M_AXI_GP0_RLAST ), + .MAXIGP0RRESP (M_AXI_GP0_RRESP ), + .MAXIGP0RVALID (M_AXI_GP0_RVALID ), + .MAXIGP0WREADY (M_AXI_GP0_WREADY ), + .MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ), + .MAXIGP1ARREADY (M_AXI_GP1_ARREADY), + .MAXIGP1AWREADY (M_AXI_GP1_AWREADY), + .MAXIGP1BID (M_AXI_GP1_BID_FULL ), + .MAXIGP1BRESP (M_AXI_GP1_BRESP ), + .MAXIGP1BVALID (M_AXI_GP1_BVALID ), + .MAXIGP1RDATA (M_AXI_GP1_RDATA ), + .MAXIGP1RID (M_AXI_GP1_RID_FULL ), + .MAXIGP1RLAST (M_AXI_GP1_RLAST ), + .MAXIGP1RRESP (M_AXI_GP1_RRESP ), + .MAXIGP1RVALID (M_AXI_GP1_RVALID ), + .MAXIGP1WREADY (M_AXI_GP1_WREADY ), + .SAXIACPACLK (S_AXI_ACP_ACLK_temp ), + .SAXIACPARADDR (SAXIACPARADDR_W ), + .SAXIACPARBURST (SAXIACPARBURST_W), + .SAXIACPARCACHE (SAXIACPARCACHE_W), + .SAXIACPARID (S_AXI_ACP_ARID_in ), + .SAXIACPARLEN (SAXIACPARLEN_W ), + .SAXIACPARLOCK (SAXIACPARLOCK_W ), + .SAXIACPARPROT (SAXIACPARPROT_W ), + .SAXIACPARQOS (S_AXI_ACP_ARQOS ), + .SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ), + .SAXIACPARUSER (SAXIACPARUSER_W ), + .SAXIACPARVALID (SAXIACPARVALID_W), + .SAXIACPAWADDR (SAXIACPAWADDR_W ), + .SAXIACPAWBURST (SAXIACPAWBURST_W), + .SAXIACPAWCACHE (SAXIACPAWCACHE_W), + .SAXIACPAWID (S_AXI_ACP_AWID_in ), + .SAXIACPAWLEN (SAXIACPAWLEN_W ), + .SAXIACPAWLOCK (SAXIACPAWLOCK_W ), + .SAXIACPAWPROT (SAXIACPAWPROT_W ), + .SAXIACPAWQOS (S_AXI_ACP_AWQOS ), + .SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ), + .SAXIACPAWUSER (SAXIACPAWUSER_W ), + .SAXIACPAWVALID (SAXIACPAWVALID_W), + .SAXIACPBREADY (SAXIACPBREADY_W ), + .SAXIACPRREADY (SAXIACPRREADY_W ), + .SAXIACPWDATA (SAXIACPWDATA_W ), + .SAXIACPWID (S_AXI_ACP_WID_in ), + .SAXIACPWLAST (SAXIACPWLAST_W ), + .SAXIACPWSTRB (SAXIACPWSTRB_W ), + .SAXIACPWVALID (SAXIACPWVALID_W ), + .SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ), + .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ), + .SAXIGP0ARBURST (S_AXI_GP0_ARBURST), + .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE), + .SAXIGP0ARID (S_AXI_GP0_ARID_in ), + .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ), + .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ), + .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ), + .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ), + .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ), + .SAXIGP0ARVALID (S_AXI_GP0_ARVALID), + .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ), + .SAXIGP0AWBURST (S_AXI_GP0_AWBURST), + .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE), + .SAXIGP0AWID (S_AXI_GP0_AWID_in ), + .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ), + .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ), + .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ), + .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ), + .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ), + .SAXIGP0AWVALID (S_AXI_GP0_AWVALID), + .SAXIGP0BREADY (S_AXI_GP0_BREADY ), + .SAXIGP0RREADY (S_AXI_GP0_RREADY ), + .SAXIGP0WDATA (S_AXI_GP0_WDATA ), + .SAXIGP0WID (S_AXI_GP0_WID_in ), + .SAXIGP0WLAST (S_AXI_GP0_WLAST ), + .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ), + .SAXIGP0WVALID (S_AXI_GP0_WVALID ), + .SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ), + .SAXIGP1ARADDR (S_AXI_GP1_ARADDR ), + .SAXIGP1ARBURST (S_AXI_GP1_ARBURST), + .SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE), + .SAXIGP1ARID (S_AXI_GP1_ARID_in ), + .SAXIGP1ARLEN (S_AXI_GP1_ARLEN ), + .SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ), + .SAXIGP1ARPROT (S_AXI_GP1_ARPROT ), + .SAXIGP1ARQOS (S_AXI_GP1_ARQOS ), + .SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ), + .SAXIGP1ARVALID (S_AXI_GP1_ARVALID), + .SAXIGP1AWADDR (S_AXI_GP1_AWADDR ), + .SAXIGP1AWBURST (S_AXI_GP1_AWBURST), + .SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE), + .SAXIGP1AWID (S_AXI_GP1_AWID_in ), + .SAXIGP1AWLEN (S_AXI_GP1_AWLEN ), + .SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ), + .SAXIGP1AWPROT (S_AXI_GP1_AWPROT ), + .SAXIGP1AWQOS (S_AXI_GP1_AWQOS ), + .SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ), + .SAXIGP1AWVALID (S_AXI_GP1_AWVALID), + .SAXIGP1BREADY (S_AXI_GP1_BREADY ), + .SAXIGP1RREADY (S_AXI_GP1_RREADY ), + .SAXIGP1WDATA (S_AXI_GP1_WDATA ), + .SAXIGP1WID (S_AXI_GP1_WID_in ), + .SAXIGP1WLAST (S_AXI_GP1_WLAST ), + .SAXIGP1WSTRB (S_AXI_GP1_WSTRB ), + .SAXIGP1WVALID (S_AXI_GP1_WVALID ), + .SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ), + .SAXIHP0ARADDR (S_AXI_HP0_ARADDR), + .SAXIHP0ARBURST (S_AXI_HP0_ARBURST), + .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE), + .SAXIHP0ARID (S_AXI_HP0_ARID_in), + .SAXIHP0ARLEN (S_AXI_HP0_ARLEN), + .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK), + .SAXIHP0ARPROT (S_AXI_HP0_ARPROT), + .SAXIHP0ARQOS (S_AXI_HP0_ARQOS), + .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]), + .SAXIHP0ARVALID (S_AXI_HP0_ARVALID), + .SAXIHP0AWADDR (S_AXI_HP0_AWADDR), + .SAXIHP0AWBURST (S_AXI_HP0_AWBURST), + .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE), + .SAXIHP0AWID (S_AXI_HP0_AWID_in), + .SAXIHP0AWLEN (S_AXI_HP0_AWLEN), + .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK), + .SAXIHP0AWPROT (S_AXI_HP0_AWPROT), + .SAXIHP0AWQOS (S_AXI_HP0_AWQOS), + .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]), + .SAXIHP0AWVALID (S_AXI_HP0_AWVALID), + .SAXIHP0BREADY (S_AXI_HP0_BREADY), + .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN), + .SAXIHP0RREADY (S_AXI_HP0_RREADY), + .SAXIHP0WDATA (S_AXI_HP0_WDATA_in), + .SAXIHP0WID (S_AXI_HP0_WID_in), + .SAXIHP0WLAST (S_AXI_HP0_WLAST), + .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN), + .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in), + .SAXIHP0WVALID (S_AXI_HP0_WVALID), + .SAXIHP1ACLK (S_AXI_HP1_ACLK_temp), + .SAXIHP1ARADDR (S_AXI_HP1_ARADDR), + .SAXIHP1ARBURST (S_AXI_HP1_ARBURST), + .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE), + .SAXIHP1ARID (S_AXI_HP1_ARID_in), + .SAXIHP1ARLEN (S_AXI_HP1_ARLEN), + .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK), + .SAXIHP1ARPROT (S_AXI_HP1_ARPROT), + .SAXIHP1ARQOS (S_AXI_HP1_ARQOS), + .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]), + .SAXIHP1ARVALID (S_AXI_HP1_ARVALID), + .SAXIHP1AWADDR (S_AXI_HP1_AWADDR), + .SAXIHP1AWBURST (S_AXI_HP1_AWBURST), + .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE), + .SAXIHP1AWID (S_AXI_HP1_AWID_in), + .SAXIHP1AWLEN (S_AXI_HP1_AWLEN), + .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK), + .SAXIHP1AWPROT (S_AXI_HP1_AWPROT), + .SAXIHP1AWQOS (S_AXI_HP1_AWQOS), + .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]), + .SAXIHP1AWVALID (S_AXI_HP1_AWVALID), + .SAXIHP1BREADY (S_AXI_HP1_BREADY), + .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN), + .SAXIHP1RREADY (S_AXI_HP1_RREADY), + .SAXIHP1WDATA (S_AXI_HP1_WDATA_in), + .SAXIHP1WID (S_AXI_HP1_WID_in), + .SAXIHP1WLAST (S_AXI_HP1_WLAST), + .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN), + .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in), + .SAXIHP1WVALID (S_AXI_HP1_WVALID), + .SAXIHP2ACLK (S_AXI_HP2_ACLK_temp), + .SAXIHP2ARADDR (S_AXI_HP2_ARADDR), + .SAXIHP2ARBURST (S_AXI_HP2_ARBURST), + .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE), + .SAXIHP2ARID (S_AXI_HP2_ARID_in), + .SAXIHP2ARLEN (S_AXI_HP2_ARLEN), + .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK), + .SAXIHP2ARPROT (S_AXI_HP2_ARPROT), + .SAXIHP2ARQOS (S_AXI_HP2_ARQOS), + .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]), + .SAXIHP2ARVALID (S_AXI_HP2_ARVALID), + .SAXIHP2AWADDR (S_AXI_HP2_AWADDR), + .SAXIHP2AWBURST (S_AXI_HP2_AWBURST), + .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE), + .SAXIHP2AWID (S_AXI_HP2_AWID_in), + .SAXIHP2AWLEN (S_AXI_HP2_AWLEN), + .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK), + .SAXIHP2AWPROT (S_AXI_HP2_AWPROT), + .SAXIHP2AWQOS (S_AXI_HP2_AWQOS), + .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]), + .SAXIHP2AWVALID (S_AXI_HP2_AWVALID), + .SAXIHP2BREADY (S_AXI_HP2_BREADY), + .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN), + .SAXIHP2RREADY (S_AXI_HP2_RREADY), + .SAXIHP2WDATA (S_AXI_HP2_WDATA_in), + .SAXIHP2WID (S_AXI_HP2_WID_in), + .SAXIHP2WLAST (S_AXI_HP2_WLAST), + .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN), + .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in), + .SAXIHP2WVALID (S_AXI_HP2_WVALID), + .SAXIHP3ACLK (S_AXI_HP3_ACLK_temp), + .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ), + .SAXIHP3ARBURST (S_AXI_HP3_ARBURST), + .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE), + .SAXIHP3ARID (S_AXI_HP3_ARID_in ), + .SAXIHP3ARLEN (S_AXI_HP3_ARLEN), + .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK), + .SAXIHP3ARPROT (S_AXI_HP3_ARPROT), + .SAXIHP3ARQOS (S_AXI_HP3_ARQOS), + .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]), + .SAXIHP3ARVALID (S_AXI_HP3_ARVALID), + .SAXIHP3AWADDR (S_AXI_HP3_AWADDR), + .SAXIHP3AWBURST (S_AXI_HP3_AWBURST), + .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE), + .SAXIHP3AWID (S_AXI_HP3_AWID_in), + .SAXIHP3AWLEN (S_AXI_HP3_AWLEN), + .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK), + .SAXIHP3AWPROT (S_AXI_HP3_AWPROT), + .SAXIHP3AWQOS (S_AXI_HP3_AWQOS), + .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]), + .SAXIHP3AWVALID (S_AXI_HP3_AWVALID), + .SAXIHP3BREADY (S_AXI_HP3_BREADY), + .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN), + .SAXIHP3RREADY (S_AXI_HP3_RREADY), + .SAXIHP3WDATA (S_AXI_HP3_WDATA_in), + .SAXIHP3WID (S_AXI_HP3_WID_in), + .SAXIHP3WLAST (S_AXI_HP3_WLAST), + .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN), + .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in), + .SAXIHP3WVALID (S_AXI_HP3_WVALID), + .DDRA (buffered_DDR_Addr), + .DDRBA (buffered_DDR_BankAddr), + .DDRCASB (buffered_DDR_CAS_n), + .DDRCKE (buffered_DDR_CKE), + .DDRCKN (buffered_DDR_Clk_n), + .DDRCKP (buffered_DDR_Clk), + .DDRCSB (buffered_DDR_CS_n), + .DDRDM (buffered_DDR_DM), + .DDRDQ (buffered_DDR_DQ), + .DDRDQSN (buffered_DDR_DQS_n), + .DDRDQSP (buffered_DDR_DQS), + .DDRDRSTB (buffered_DDR_DRSTB), + .DDRODT (buffered_DDR_ODT), + .DDRRASB (buffered_DDR_RAS_n), + .DDRVRN (buffered_DDR_VRN), + .DDRVRP (buffered_DDR_VRP), + .DDRWEB (buffered_DDR_WEB), + .MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}), + .PSCLK (buffered_PS_CLK), + .PSPORB (buffered_PS_PORB), + .PSSRSTB (buffered_PS_SRSTB) + + +); + end + else begin + PS7 PS7_i ( + .DMA0DATYPE (DMA0_DATYPE ), + .DMA0DAVALID (DMA0_DAVALID), + .DMA0DRREADY (DMA0_DRREADY), + .DMA0RSTN (DMA0_RSTN ), + .DMA1DATYPE (DMA1_DATYPE ), + .DMA1DAVALID (DMA1_DAVALID), + .DMA1DRREADY (DMA1_DRREADY), + .DMA1RSTN (DMA1_RSTN ), + .DMA2DATYPE (DMA2_DATYPE ), + .DMA2DAVALID (DMA2_DAVALID), + .DMA2DRREADY (DMA2_DRREADY), + .DMA2RSTN (DMA2_RSTN ), + .DMA3DATYPE (DMA3_DATYPE ), + .DMA3DAVALID (DMA3_DAVALID), + .DMA3DRREADY (DMA3_DRREADY), + .DMA3RSTN (DMA3_RSTN ), + .EMIOCAN0PHYTX (CAN0_PHY_TX ), + .EMIOCAN1PHYTX (CAN1_PHY_TX ), + .EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ), + .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i), + .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i), + .EMIOENET0MDIOMDC (ENET0_MDIO_MDC), + .EMIOENET0MDIOO (ENET0_MDIO_O ), + .EMIOENET0MDIOTN (ENET0_MDIO_T_n ), + .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX), + .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX), + .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX), + .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX), + .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX), + .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX), + .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX), + .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX), + .EMIOENET0SOFRX (ENET0_SOF_RX), + .EMIOENET0SOFTX (ENET0_SOF_TX), + .EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i), + .EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i), + .EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i), + .EMIOENET1MDIOMDC (ENET1_MDIO_MDC), + .EMIOENET1MDIOO (ENET1_MDIO_O ), + .EMIOENET1MDIOTN (ENET1_MDIO_T_n), + .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX), + .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX), + .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX), + .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX), + .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX), + .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX), + .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX), + .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX), + .EMIOENET1SOFRX (ENET1_SOF_RX), + .EMIOENET1SOFTX (ENET1_SOF_TX), + .EMIOGPIOO (gpio_out), + .EMIOGPIOTN (gpio_out_t_n), + .EMIOI2C0SCLO (I2C0_SCL_O), + .EMIOI2C0SCLTN (I2C0_SCL_T_n), + .EMIOI2C0SDAO (I2C0_SDA_O), + .EMIOI2C0SDATN (I2C0_SDA_T_n), + .EMIOI2C1SCLO (I2C1_SCL_O), + .EMIOI2C1SCLTN (I2C1_SCL_T_n), + .EMIOI2C1SDAO (I2C1_SDA_O), + .EMIOI2C1SDATN (I2C1_SDA_T_n), + .EMIOPJTAGTDO (PJTAG_TDO_O), + .EMIOPJTAGTDTN (PJTAG_TDO_T_n), + .EMIOSDIO0BUSPOW (SDIO0_BUSPOW), + .EMIOSDIO0CLK (SDIO0_CLK ), + .EMIOSDIO0CMDO (SDIO0_CMD_O ), + .EMIOSDIO0CMDTN (SDIO0_CMD_T_n ), + .EMIOSDIO0DATAO (SDIO0_DATA_O), + .EMIOSDIO0DATATN (SDIO0_DATA_T_n), + .EMIOSDIO0LED (SDIO0_LED), + .EMIOSDIO1BUSPOW (SDIO1_BUSPOW), + .EMIOSDIO1CLK (SDIO1_CLK ), + .EMIOSDIO1CMDO (SDIO1_CMD_O ), + .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ), + .EMIOSDIO1DATAO (SDIO1_DATA_O), + .EMIOSDIO1DATATN (SDIO1_DATA_T_n), + .EMIOSDIO1LED (SDIO1_LED), + .EMIOSPI0MO (SPI0_MOSI_O), + .EMIOSPI0MOTN (SPI0_MOSI_T_n), + .EMIOSPI0SCLKO (SPI0_SCLK_O), + .EMIOSPI0SCLKTN (SPI0_SCLK_T_n), + .EMIOSPI0SO (SPI0_MISO_O), + .EMIOSPI0STN (SPI0_MISO_T_n), + .EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}), + .EMIOSPI0SSNTN (SPI0_SS_T_n), + .EMIOSPI1MO (SPI1_MOSI_O), + .EMIOSPI1MOTN (SPI1_MOSI_T_n), + .EMIOSPI1SCLKO (SPI1_SCLK_O), + .EMIOSPI1SCLKTN (SPI1_SCLK_T_n), + .EMIOSPI1SO (SPI1_MISO_O), + .EMIOSPI1STN (SPI1_MISO_T_n), + .EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}), + .EMIOSPI1SSNTN (SPI1_SS_T_n), + .EMIOTRACECTL (TRACE_CTL_i), + .EMIOTRACEDATA (TRACE_DATA_i), + .EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}), + .EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}), + .EMIOUART0DTRN (UART0_DTRN), + .EMIOUART0RTSN (UART0_RTSN), + .EMIOUART0TX (UART0_TX ), + .EMIOUART1DTRN (UART1_DTRN), + .EMIOUART1RTSN (UART1_RTSN), + .EMIOUART1TX (UART1_TX ), + .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL), + .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT), + .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL), + .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT), + .EMIOWDTRSTO (WDT_RST_OUT), + .EVENTEVENTO (EVENT_EVENTO), + .EVENTSTANDBYWFE (EVENT_STANDBYWFE), + .EVENTSTANDBYWFI (EVENT_STANDBYWFI), + .FCLKCLK (FCLK_CLK_unbuffered), + .FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}), + .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT), + .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT), + .FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}), + .FTMTP2FDEBUG (FTMT_P2F_DEBUG ), + .FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), + .IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}), + .MAXIGP0ARADDR (M_AXI_GP0_ARADDR), + .MAXIGP0ARBURST (M_AXI_GP0_ARBURST), + .MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t), + .MAXIGP0ARESETN (M_AXI_GP0_ARESETN), + .MAXIGP0ARID (M_AXI_GP0_ARID_FULL ), + .MAXIGP0ARLEN (M_AXI_GP0_ARLEN ), + .MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ), + .MAXIGP0ARPROT (M_AXI_GP0_ARPROT ), + .MAXIGP0ARQOS (M_AXI_GP0_ARQOS ), + .MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ), + .MAXIGP0ARVALID (M_AXI_GP0_ARVALID), + .MAXIGP0AWADDR (M_AXI_GP0_AWADDR ), + .MAXIGP0AWBURST (M_AXI_GP0_AWBURST), + .MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t), + .MAXIGP0AWID (M_AXI_GP0_AWID_FULL ), + .MAXIGP0AWLEN (M_AXI_GP0_AWLEN ), + .MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ), + .MAXIGP0AWPROT (M_AXI_GP0_AWPROT ), + .MAXIGP0AWQOS (M_AXI_GP0_AWQOS ), + .MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ), + .MAXIGP0AWVALID (M_AXI_GP0_AWVALID), + .MAXIGP0BREADY (M_AXI_GP0_BREADY ), + .MAXIGP0RREADY (M_AXI_GP0_RREADY ), + .MAXIGP0WDATA (M_AXI_GP0_WDATA ), + .MAXIGP0WID (M_AXI_GP0_WID_FULL ), + .MAXIGP0WLAST (M_AXI_GP0_WLAST ), + .MAXIGP0WSTRB (M_AXI_GP0_WSTRB ), + .MAXIGP0WVALID (M_AXI_GP0_WVALID ), + .MAXIGP1ARADDR (M_AXI_GP1_ARADDR ), + .MAXIGP1ARBURST (M_AXI_GP1_ARBURST), + .MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t), + .MAXIGP1ARESETN (M_AXI_GP1_ARESETN), + .MAXIGP1ARID (M_AXI_GP1_ARID_FULL ), + .MAXIGP1ARLEN (M_AXI_GP1_ARLEN ), + .MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ), + .MAXIGP1ARPROT (M_AXI_GP1_ARPROT ), + .MAXIGP1ARQOS (M_AXI_GP1_ARQOS ), + .MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ), + .MAXIGP1ARVALID (M_AXI_GP1_ARVALID), + .MAXIGP1AWADDR (M_AXI_GP1_AWADDR ), + .MAXIGP1AWBURST (M_AXI_GP1_AWBURST), + .MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t), + .MAXIGP1AWID (M_AXI_GP1_AWID_FULL ), + .MAXIGP1AWLEN (M_AXI_GP1_AWLEN ), + .MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ), + .MAXIGP1AWPROT (M_AXI_GP1_AWPROT ), + .MAXIGP1AWQOS (M_AXI_GP1_AWQOS ), + .MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ), + .MAXIGP1AWVALID (M_AXI_GP1_AWVALID), + .MAXIGP1BREADY (M_AXI_GP1_BREADY ), + .MAXIGP1RREADY (M_AXI_GP1_RREADY ), + .MAXIGP1WDATA (M_AXI_GP1_WDATA ), + .MAXIGP1WID (M_AXI_GP1_WID_FULL ), + .MAXIGP1WLAST (M_AXI_GP1_WLAST ), + .MAXIGP1WSTRB (M_AXI_GP1_WSTRB ), + .MAXIGP1WVALID (M_AXI_GP1_WVALID ), + .SAXIACPARESETN (S_AXI_ACP_ARESETN), + .SAXIACPARREADY (SAXIACPARREADY_W), + .SAXIACPAWREADY (SAXIACPAWREADY_W), + .SAXIACPBID (S_AXI_ACP_BID_out ), + .SAXIACPBRESP (SAXIACPBRESP_W ), + .SAXIACPBVALID (SAXIACPBVALID_W ), + .SAXIACPRDATA (SAXIACPRDATA_W ), + .SAXIACPRID (S_AXI_ACP_RID_out), + .SAXIACPRLAST (SAXIACPRLAST_W ), + .SAXIACPRRESP (SAXIACPRRESP_W ), + .SAXIACPRVALID (SAXIACPRVALID_W ), + .SAXIACPWREADY (SAXIACPWREADY_W ), + .SAXIGP0ARESETN (S_AXI_GP0_ARESETN), + .SAXIGP0ARREADY (S_AXI_GP0_ARREADY), + .SAXIGP0AWREADY (S_AXI_GP0_AWREADY), + .SAXIGP0BID (S_AXI_GP0_BID_out), + .SAXIGP0BRESP (S_AXI_GP0_BRESP ), + .SAXIGP0BVALID (S_AXI_GP0_BVALID ), + .SAXIGP0RDATA (S_AXI_GP0_RDATA ), + .SAXIGP0RID (S_AXI_GP0_RID_out ), + .SAXIGP0RLAST (S_AXI_GP0_RLAST ), + .SAXIGP0RRESP (S_AXI_GP0_RRESP ), + .SAXIGP0RVALID (S_AXI_GP0_RVALID ), + .SAXIGP0WREADY (S_AXI_GP0_WREADY ), + .SAXIGP1ARESETN (S_AXI_GP1_ARESETN), + .SAXIGP1ARREADY (S_AXI_GP1_ARREADY), + .SAXIGP1AWREADY (S_AXI_GP1_AWREADY), + .SAXIGP1BID (S_AXI_GP1_BID_out ), + .SAXIGP1BRESP (S_AXI_GP1_BRESP ), + .SAXIGP1BVALID (S_AXI_GP1_BVALID ), + .SAXIGP1RDATA (S_AXI_GP1_RDATA ), + .SAXIGP1RID (S_AXI_GP1_RID_out ), + .SAXIGP1RLAST (S_AXI_GP1_RLAST ), + .SAXIGP1RRESP (S_AXI_GP1_RRESP ), + .SAXIGP1RVALID (S_AXI_GP1_RVALID ), + .SAXIGP1WREADY (S_AXI_GP1_WREADY ), + .SAXIHP0ARESETN (S_AXI_HP0_ARESETN), + .SAXIHP0ARREADY (S_AXI_HP0_ARREADY), + .SAXIHP0AWREADY (S_AXI_HP0_AWREADY), + .SAXIHP0BID (S_AXI_HP0_BID_out ), + .SAXIHP0BRESP (S_AXI_HP0_BRESP ), + .SAXIHP0BVALID (S_AXI_HP0_BVALID ), + .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT), + .SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT), + .SAXIHP0RDATA (S_AXI_HP0_RDATA_out), + .SAXIHP0RID (S_AXI_HP0_RID_out ), + .SAXIHP0RLAST (S_AXI_HP0_RLAST), + .SAXIHP0RRESP (S_AXI_HP0_RRESP), + .SAXIHP0RVALID (S_AXI_HP0_RVALID), + .SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT), + .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT), + .SAXIHP0WREADY (S_AXI_HP0_WREADY), + .SAXIHP1ARESETN (S_AXI_HP1_ARESETN), + .SAXIHP1ARREADY (S_AXI_HP1_ARREADY), + .SAXIHP1AWREADY (S_AXI_HP1_AWREADY), + .SAXIHP1BID (S_AXI_HP1_BID_out ), + .SAXIHP1BRESP (S_AXI_HP1_BRESP ), + .SAXIHP1BVALID (S_AXI_HP1_BVALID ), + .SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ), + .SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ), + .SAXIHP1RDATA (S_AXI_HP1_RDATA_out), + .SAXIHP1RID (S_AXI_HP1_RID_out ), + .SAXIHP1RLAST (S_AXI_HP1_RLAST ), + .SAXIHP1RRESP (S_AXI_HP1_RRESP ), + .SAXIHP1RVALID (S_AXI_HP1_RVALID), + .SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT), + .SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT), + .SAXIHP1WREADY (S_AXI_HP1_WREADY), + .SAXIHP2ARESETN (S_AXI_HP2_ARESETN), + .SAXIHP2ARREADY (S_AXI_HP2_ARREADY), + .SAXIHP2AWREADY (S_AXI_HP2_AWREADY), + .SAXIHP2BID (S_AXI_HP2_BID_out ), + .SAXIHP2BRESP (S_AXI_HP2_BRESP), + .SAXIHP2BVALID (S_AXI_HP2_BVALID), + .SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT), + .SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT), + .SAXIHP2RDATA (S_AXI_HP2_RDATA_out), + .SAXIHP2RID (S_AXI_HP2_RID_out ), + .SAXIHP2RLAST (S_AXI_HP2_RLAST), + .SAXIHP2RRESP (S_AXI_HP2_RRESP), + .SAXIHP2RVALID (S_AXI_HP2_RVALID), + .SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT), + .SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT), + .SAXIHP2WREADY (S_AXI_HP2_WREADY), + .SAXIHP3ARESETN (S_AXI_HP3_ARESETN), + .SAXIHP3ARREADY (S_AXI_HP3_ARREADY), + .SAXIHP3AWREADY (S_AXI_HP3_AWREADY), + .SAXIHP3BID (S_AXI_HP3_BID_out), + .SAXIHP3BRESP (S_AXI_HP3_BRESP), + .SAXIHP3BVALID (S_AXI_HP3_BVALID), + .SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT), + .SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT), + .SAXIHP3RDATA (S_AXI_HP3_RDATA_out), + .SAXIHP3RID (S_AXI_HP3_RID_out), + .SAXIHP3RLAST (S_AXI_HP3_RLAST), + .SAXIHP3RRESP (S_AXI_HP3_RRESP), + .SAXIHP3RVALID (S_AXI_HP3_RVALID), + .SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT), + .SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT), + .SAXIHP3WREADY (S_AXI_HP3_WREADY), + .DDRARB (DDR_ARB), + .DMA0ACLK (DMA0_ACLK ), + .DMA0DAREADY (DMA0_DAREADY), + .DMA0DRLAST (DMA0_DRLAST ), + .DMA0DRTYPE (DMA0_DRTYPE), + .DMA0DRVALID (DMA0_DRVALID), + .DMA1ACLK (DMA1_ACLK ), + .DMA1DAREADY (DMA1_DAREADY), + .DMA1DRLAST (DMA1_DRLAST ), + .DMA1DRTYPE (DMA1_DRTYPE), + .DMA1DRVALID (DMA1_DRVALID), + .DMA2ACLK (DMA2_ACLK ), + .DMA2DAREADY (DMA2_DAREADY), + .DMA2DRLAST (DMA2_DRLAST ), + .DMA2DRTYPE (DMA2_DRTYPE), + .DMA2DRVALID (DMA2_DRVALID), + .DMA3ACLK (DMA3_ACLK ), + .DMA3DAREADY (DMA3_DAREADY), + .DMA3DRLAST (DMA3_DRLAST ), + .DMA3DRTYPE (DMA3_DRTYPE), + .DMA3DRVALID (DMA3_DRVALID), + .EMIOCAN0PHYRX (CAN0_PHY_RX), + .EMIOCAN1PHYRX (CAN1_PHY_RX), + .EMIOENET0EXTINTIN (ENET0_EXT_INTIN), + .EMIOENET0GMIICOL (ENET0_GMII_COL_i), + .EMIOENET0GMIICRS (ENET0_GMII_CRS_i), + .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK), + .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i), + .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i), + .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i), + .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK), + .EMIOENET0MDIOI (ENET0_MDIO_I), + .EMIOENET1EXTINTIN (ENET1_EXT_INTIN), + .EMIOENET1GMIICOL (ENET1_GMII_COL_i), + .EMIOENET1GMIICRS (ENET1_GMII_CRS_i), + .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK), + .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i), + .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i), + .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i), + .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK), + .EMIOENET1MDIOI (ENET1_MDIO_I), + .EMIOGPIOI (gpio_in63_0 ), + .EMIOI2C0SCLI (I2C0_SCL_I), + .EMIOI2C0SDAI (I2C0_SDA_I), + .EMIOI2C1SCLI (I2C1_SCL_I), + .EMIOI2C1SDAI (I2C1_SDA_I), + .EMIOPJTAGTCK (PJTAG_TCK), + .EMIOPJTAGTDI (PJTAG_TDI), + .EMIOPJTAGTMS (PJTAG_TMS), + .EMIOSDIO0CDN (SDIO0_CDN), + .EMIOSDIO0CLKFB (SDIO0_CLK_FB ), + .EMIOSDIO0CMDI (SDIO0_CMD_I ), + .EMIOSDIO0DATAI (SDIO0_DATA_I ), + .EMIOSDIO0WP (SDIO0_WP), + .EMIOSDIO1CDN (SDIO1_CDN), + .EMIOSDIO1CLKFB (SDIO1_CLK_FB ), + .EMIOSDIO1CMDI (SDIO1_CMD_I ), + .EMIOSDIO1DATAI (SDIO1_DATA_I ), + .EMIOSDIO1WP (SDIO1_WP), + .EMIOSPI0MI (SPI0_MISO_I), + .EMIOSPI0SCLKI (SPI0_SCLK_I), + .EMIOSPI0SI (SPI0_MOSI_I), + .EMIOSPI0SSIN (SPI0_SS_I), + .EMIOSPI1MI (SPI1_MISO_I), + .EMIOSPI1SCLKI (SPI1_SCLK_I), + .EMIOSPI1SI (SPI1_MOSI_I), + .EMIOSPI1SSIN (SPI1_SS_I), + .EMIOSRAMINTIN (SRAM_INTIN), + .EMIOTRACECLK (TRACE_CLK), + .EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}), + .EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}), + .EMIOUART0CTSN (UART0_CTSN), + .EMIOUART0DCDN (UART0_DCDN), + .EMIOUART0DSRN (UART0_DSRN), + .EMIOUART0RIN (UART0_RIN ), + .EMIOUART0RX (UART0_RX ), + .EMIOUART1CTSN (UART1_CTSN), + .EMIOUART1DCDN (UART1_DCDN), + .EMIOUART1DSRN (UART1_DSRN), + .EMIOUART1RIN (UART1_RIN ), + .EMIOUART1RX (UART1_RX ), + .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT), + .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT), + .EMIOWDTCLKI (WDT_CLK_IN), + .EVENTEVENTI (EVENT_EVENTI), + .FCLKCLKTRIGN (fclk_clktrig_gnd), + .FPGAIDLEN (FPGA_IDLE_N), + .FTMDTRACEINATID (FTMD_TRACEIN_ATID_i), + .FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK), + .FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i), + .FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i), + .FTMTF2PDEBUG (FTMT_F2P_DEBUG ), + .FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}), + .FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), + .IRQF2P (irq_f2p_i), + .MAXIGP0ACLK (M_AXI_GP0_ACLK_temp), + .MAXIGP0ARREADY (M_AXI_GP0_ARREADY), + .MAXIGP0AWREADY (M_AXI_GP0_AWREADY), + .MAXIGP0BID (M_AXI_GP0_BID_FULL ), + .MAXIGP0BRESP (M_AXI_GP0_BRESP ), + .MAXIGP0BVALID (M_AXI_GP0_BVALID ), + .MAXIGP0RDATA (M_AXI_GP0_RDATA ), + .MAXIGP0RID (M_AXI_GP0_RID_FULL ), + .MAXIGP0RLAST (M_AXI_GP0_RLAST ), + .MAXIGP0RRESP (M_AXI_GP0_RRESP ), + .MAXIGP0RVALID (M_AXI_GP0_RVALID ), + .MAXIGP0WREADY (M_AXI_GP0_WREADY ), + .MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ), + .MAXIGP1ARREADY (M_AXI_GP1_ARREADY), + .MAXIGP1AWREADY (M_AXI_GP1_AWREADY), + .MAXIGP1BID (M_AXI_GP1_BID_FULL ), + .MAXIGP1BRESP (M_AXI_GP1_BRESP ), + .MAXIGP1BVALID (M_AXI_GP1_BVALID ), + .MAXIGP1RDATA (M_AXI_GP1_RDATA ), + .MAXIGP1RID (M_AXI_GP1_RID_FULL ), + .MAXIGP1RLAST (M_AXI_GP1_RLAST ), + .MAXIGP1RRESP (M_AXI_GP1_RRESP ), + .MAXIGP1RVALID (M_AXI_GP1_RVALID ), + .MAXIGP1WREADY (M_AXI_GP1_WREADY ), + .SAXIACPACLK (S_AXI_ACP_ACLK_temp), + .SAXIACPARADDR (SAXIACPARADDR_W ), + .SAXIACPARBURST (SAXIACPARBURST_W), + .SAXIACPARCACHE (SAXIACPARCACHE_W), + .SAXIACPARID (S_AXI_ACP_ARID_in ), + .SAXIACPARLEN (SAXIACPARLEN_W ), + .SAXIACPARLOCK (SAXIACPARLOCK_W ), + .SAXIACPARPROT (SAXIACPARPROT_W ), + .SAXIACPARQOS (S_AXI_ACP_ARQOS ), + .SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ), + .SAXIACPARUSER (SAXIACPARUSER_W ), + .SAXIACPARVALID (SAXIACPARVALID_W), + .SAXIACPAWADDR (SAXIACPAWADDR_W ), + .SAXIACPAWBURST (SAXIACPAWBURST_W), + .SAXIACPAWCACHE (SAXIACPAWCACHE_W), + .SAXIACPAWID (S_AXI_ACP_AWID_in ), + .SAXIACPAWLEN (SAXIACPAWLEN_W ), + .SAXIACPAWLOCK (SAXIACPAWLOCK_W ), + .SAXIACPAWPROT (SAXIACPAWPROT_W ), + .SAXIACPAWQOS (S_AXI_ACP_AWQOS ), + .SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ), + .SAXIACPAWUSER (SAXIACPAWUSER_W ), + .SAXIACPAWVALID (SAXIACPAWVALID_W), + .SAXIACPBREADY (SAXIACPBREADY_W ), + .SAXIACPRREADY (SAXIACPRREADY_W ), + .SAXIACPWDATA (SAXIACPWDATA_W ), + .SAXIACPWID (S_AXI_ACP_WID_in ), + .SAXIACPWLAST (SAXIACPWLAST_W ), + .SAXIACPWSTRB (SAXIACPWSTRB_W ), + .SAXIACPWVALID (SAXIACPWVALID_W ), + .SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ), + .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ), + .SAXIGP0ARBURST (S_AXI_GP0_ARBURST), + .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE), + .SAXIGP0ARID (S_AXI_GP0_ARID_in ), + .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ), + .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ), + .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ), + .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ), + .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ), + .SAXIGP0ARVALID (S_AXI_GP0_ARVALID), + .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ), + .SAXIGP0AWBURST (S_AXI_GP0_AWBURST), + .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE), + .SAXIGP0AWID (S_AXI_GP0_AWID_in ), + .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ), + .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ), + .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ), + .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ), + .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ), + .SAXIGP0AWVALID (S_AXI_GP0_AWVALID), + .SAXIGP0BREADY (S_AXI_GP0_BREADY ), + .SAXIGP0RREADY (S_AXI_GP0_RREADY ), + .SAXIGP0WDATA (S_AXI_GP0_WDATA ), + .SAXIGP0WID (S_AXI_GP0_WID_in ), + .SAXIGP0WLAST (S_AXI_GP0_WLAST ), + .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ), + .SAXIGP0WVALID (S_AXI_GP0_WVALID ), + .SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ), + .SAXIGP1ARADDR (S_AXI_GP1_ARADDR ), + .SAXIGP1ARBURST (S_AXI_GP1_ARBURST), + .SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE), + .SAXIGP1ARID (S_AXI_GP1_ARID_in ), + .SAXIGP1ARLEN (S_AXI_GP1_ARLEN ), + .SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ), + .SAXIGP1ARPROT (S_AXI_GP1_ARPROT ), + .SAXIGP1ARQOS (S_AXI_GP1_ARQOS ), + .SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ), + .SAXIGP1ARVALID (S_AXI_GP1_ARVALID), + .SAXIGP1AWADDR (S_AXI_GP1_AWADDR ), + .SAXIGP1AWBURST (S_AXI_GP1_AWBURST), + .SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE), + .SAXIGP1AWID (S_AXI_GP1_AWID_in ), + .SAXIGP1AWLEN (S_AXI_GP1_AWLEN ), + .SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ), + .SAXIGP1AWPROT (S_AXI_GP1_AWPROT ), + .SAXIGP1AWQOS (S_AXI_GP1_AWQOS ), + .SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ), + .SAXIGP1AWVALID (S_AXI_GP1_AWVALID), + .SAXIGP1BREADY (S_AXI_GP1_BREADY ), + .SAXIGP1RREADY (S_AXI_GP1_RREADY ), + .SAXIGP1WDATA (S_AXI_GP1_WDATA ), + .SAXIGP1WID (S_AXI_GP1_WID_in ), + .SAXIGP1WLAST (S_AXI_GP1_WLAST ), + .SAXIGP1WSTRB (S_AXI_GP1_WSTRB ), + .SAXIGP1WVALID (S_AXI_GP1_WVALID ), + .SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ), + .SAXIHP0ARADDR (S_AXI_HP0_ARADDR), + .SAXIHP0ARBURST (S_AXI_HP0_ARBURST), + .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE), + .SAXIHP0ARID (S_AXI_HP0_ARID_in), + .SAXIHP0ARLEN (S_AXI_HP0_ARLEN), + .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK), + .SAXIHP0ARPROT (S_AXI_HP0_ARPROT), + .SAXIHP0ARQOS (S_AXI_HP0_ARQOS), + .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]), + .SAXIHP0ARVALID (S_AXI_HP0_ARVALID), + .SAXIHP0AWADDR (S_AXI_HP0_AWADDR), + .SAXIHP0AWBURST (S_AXI_HP0_AWBURST), + .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE), + .SAXIHP0AWID (S_AXI_HP0_AWID_in), + .SAXIHP0AWLEN (S_AXI_HP0_AWLEN), + .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK), + .SAXIHP0AWPROT (S_AXI_HP0_AWPROT), + .SAXIHP0AWQOS (S_AXI_HP0_AWQOS), + .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]), + .SAXIHP0AWVALID (S_AXI_HP0_AWVALID), + .SAXIHP0BREADY (S_AXI_HP0_BREADY), + .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN), + .SAXIHP0RREADY (S_AXI_HP0_RREADY), + .SAXIHP0WDATA (S_AXI_HP0_WDATA_in), + .SAXIHP0WID (S_AXI_HP0_WID_in), + .SAXIHP0WLAST (S_AXI_HP0_WLAST), + .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN), + .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in), + .SAXIHP0WVALID (S_AXI_HP0_WVALID), + .SAXIHP1ACLK (S_AXI_HP1_ACLK_temp), + .SAXIHP1ARADDR (S_AXI_HP1_ARADDR), + .SAXIHP1ARBURST (S_AXI_HP1_ARBURST), + .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE), + .SAXIHP1ARID (S_AXI_HP1_ARID_in), + .SAXIHP1ARLEN (S_AXI_HP1_ARLEN), + .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK), + .SAXIHP1ARPROT (S_AXI_HP1_ARPROT), + .SAXIHP1ARQOS (S_AXI_HP1_ARQOS), + .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]), + .SAXIHP1ARVALID (S_AXI_HP1_ARVALID), + .SAXIHP1AWADDR (S_AXI_HP1_AWADDR), + .SAXIHP1AWBURST (S_AXI_HP1_AWBURST), + .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE), + .SAXIHP1AWID (S_AXI_HP1_AWID_in), + .SAXIHP1AWLEN (S_AXI_HP1_AWLEN), + .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK), + .SAXIHP1AWPROT (S_AXI_HP1_AWPROT), + .SAXIHP1AWQOS (S_AXI_HP1_AWQOS), + .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]), + .SAXIHP1AWVALID (S_AXI_HP1_AWVALID), + .SAXIHP1BREADY (S_AXI_HP1_BREADY), + .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN), + .SAXIHP1RREADY (S_AXI_HP1_RREADY), + .SAXIHP1WDATA (S_AXI_HP1_WDATA_in), + .SAXIHP1WID (S_AXI_HP1_WID_in), + .SAXIHP1WLAST (S_AXI_HP1_WLAST), + .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN), + .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in), + .SAXIHP1WVALID (S_AXI_HP1_WVALID), + .SAXIHP2ACLK (S_AXI_HP2_ACLK_temp), + .SAXIHP2ARADDR (S_AXI_HP2_ARADDR), + .SAXIHP2ARBURST (S_AXI_HP2_ARBURST), + .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE), + .SAXIHP2ARID (S_AXI_HP2_ARID_in), + .SAXIHP2ARLEN (S_AXI_HP2_ARLEN), + .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK), + .SAXIHP2ARPROT (S_AXI_HP2_ARPROT), + .SAXIHP2ARQOS (S_AXI_HP2_ARQOS), + .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]), + .SAXIHP2ARVALID (S_AXI_HP2_ARVALID), + .SAXIHP2AWADDR (S_AXI_HP2_AWADDR), + .SAXIHP2AWBURST (S_AXI_HP2_AWBURST), + .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE), + .SAXIHP2AWID (S_AXI_HP2_AWID_in), + .SAXIHP2AWLEN (S_AXI_HP2_AWLEN), + .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK), + .SAXIHP2AWPROT (S_AXI_HP2_AWPROT), + .SAXIHP2AWQOS (S_AXI_HP2_AWQOS), + .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]), + .SAXIHP2AWVALID (S_AXI_HP2_AWVALID), + .SAXIHP2BREADY (S_AXI_HP2_BREADY), + .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN), + .SAXIHP2RREADY (S_AXI_HP2_RREADY), + .SAXIHP2WDATA (S_AXI_HP2_WDATA_in), + .SAXIHP2WID (S_AXI_HP2_WID_in), + .SAXIHP2WLAST (S_AXI_HP2_WLAST), + .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN), + .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in), + .SAXIHP2WVALID (S_AXI_HP2_WVALID), + .SAXIHP3ACLK (S_AXI_HP3_ACLK_temp), + .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ), + .SAXIHP3ARBURST (S_AXI_HP3_ARBURST), + .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE), + .SAXIHP3ARID (S_AXI_HP3_ARID_in ), + .SAXIHP3ARLEN (S_AXI_HP3_ARLEN), + .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK), + .SAXIHP3ARPROT (S_AXI_HP3_ARPROT), + .SAXIHP3ARQOS (S_AXI_HP3_ARQOS), + .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]), + .SAXIHP3ARVALID (S_AXI_HP3_ARVALID), + .SAXIHP3AWADDR (S_AXI_HP3_AWADDR), + .SAXIHP3AWBURST (S_AXI_HP3_AWBURST), + .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE), + .SAXIHP3AWID (S_AXI_HP3_AWID_in), + .SAXIHP3AWLEN (S_AXI_HP3_AWLEN), + .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK), + .SAXIHP3AWPROT (S_AXI_HP3_AWPROT), + .SAXIHP3AWQOS (S_AXI_HP3_AWQOS), + .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]), + .SAXIHP3AWVALID (S_AXI_HP3_AWVALID), + .SAXIHP3BREADY (S_AXI_HP3_BREADY), + .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN), + .SAXIHP3RREADY (S_AXI_HP3_RREADY), + .SAXIHP3WDATA (S_AXI_HP3_WDATA_in), + .SAXIHP3WID (S_AXI_HP3_WID_in), + .SAXIHP3WLAST (S_AXI_HP3_WLAST), + .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN), + .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in), + .SAXIHP3WVALID (S_AXI_HP3_WVALID), + .DDRA (buffered_DDR_Addr), + .DDRBA (buffered_DDR_BankAddr), + .DDRCASB (buffered_DDR_CAS_n), + .DDRCKE (buffered_DDR_CKE), + .DDRCKN (buffered_DDR_Clk_n), + .DDRCKP (buffered_DDR_Clk), + .DDRCSB (buffered_DDR_CS_n), + .DDRDM (buffered_DDR_DM), + .DDRDQ (buffered_DDR_DQ), + .DDRDQSN (buffered_DDR_DQS_n), + .DDRDQSP (buffered_DDR_DQS), + .DDRDRSTB (buffered_DDR_DRSTB), + .DDRODT (buffered_DDR_ODT), + .DDRRASB (buffered_DDR_RAS_n), + .DDRVRN (buffered_DDR_VRN), + .DDRVRP (buffered_DDR_VRP), + .DDRWEB (buffered_DDR_WEB), + .MIO (buffered_MIO), + .PSCLK (buffered_PS_CLK), + .PSPORB (buffered_PS_PORB), + .PSSRSTB (buffered_PS_SRSTB) + + + ); + + end + endgenerate + + +// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled. +// Otherwise a master connected to the ACP port will drive the AxUSER Ports +assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER; +assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER; + + assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR; + assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST; + assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE; + assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN; + assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK; + assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT; + assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE; + //assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER; + assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser; + + assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ; + assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR; + assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST; + + + assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE; + assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN; + assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK; + assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT; + assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE; + //assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER; + assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser; + assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID; + assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY; + assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY; + assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA; + assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST; + assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB; + assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID; + + assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID; + assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID; + assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID; + + + generate + if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc + + assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W; + assign S_AXI_ACP_WREADY = SAXIACPWREADY_W; + assign S_AXI_ACP_BID = SAXIACPBID_W; + assign S_AXI_ACP_BRESP = SAXIACPBRESP_W; + assign S_AXI_ACP_BVALID = SAXIACPBVALID_W; + assign S_AXI_ACP_RDATA = SAXIACPRDATA_W; + assign S_AXI_ACP_RID = SAXIACPRID_W; + assign S_AXI_ACP_RLAST = SAXIACPRLAST_W; + assign S_AXI_ACP_RRESP = SAXIACPRRESP_W; + assign S_AXI_ACP_RVALID = SAXIACPRVALID_W; + assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W; + + + end else begin : gen_atc + + processing_system7_v5_5_atc #( + .C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH), + .C_AXI_AWUSER_WIDTH (5), + .C_AXI_ARUSER_WIDTH (5) + ) + + atc_i ( + + // Global Signals + .ACLK (S_AXI_ACP_ACLK_temp), + .ARESETN (S_AXI_ACP_ARESETN), + + // Slave Interface Write Address Ports + .S_AXI_AWID (S_AXI_ACP_AWID), + .S_AXI_AWADDR (S_AXI_ACP_AWADDR), + .S_AXI_AWLEN (S_AXI_ACP_AWLEN), + .S_AXI_AWSIZE (S_AXI_ACP_AWSIZE), + .S_AXI_AWBURST (S_AXI_ACP_AWBURST), + .S_AXI_AWLOCK (S_AXI_ACP_AWLOCK), + .S_AXI_AWCACHE (S_AXI_ACP_AWCACHE), + .S_AXI_AWPROT (S_AXI_ACP_AWPROT), + //.S_AXI_AWUSER (S_AXI_ACP_AWUSER), + .S_AXI_AWUSER (param_awuser), + .S_AXI_AWVALID (S_AXI_ACP_AWVALID), + .S_AXI_AWREADY (S_AXI_ACP_AWREADY), + // Slave Interface Write Data Ports + .S_AXI_WID (S_AXI_ACP_WID), + .S_AXI_WDATA (S_AXI_ACP_WDATA), + .S_AXI_WSTRB (S_AXI_ACP_WSTRB), + .S_AXI_WLAST (S_AXI_ACP_WLAST), + .S_AXI_WUSER (), + .S_AXI_WVALID (S_AXI_ACP_WVALID), + .S_AXI_WREADY (S_AXI_ACP_WREADY), + // Slave Interface Write Response Ports + .S_AXI_BID (S_AXI_ACP_BID), + .S_AXI_BRESP (S_AXI_ACP_BRESP), + .S_AXI_BUSER (), + .S_AXI_BVALID (S_AXI_ACP_BVALID), + .S_AXI_BREADY (S_AXI_ACP_BREADY), + // Slave Interface Read Address Ports + .S_AXI_ARID (S_AXI_ACP_ARID), + .S_AXI_ARADDR (S_AXI_ACP_ARADDR), + .S_AXI_ARLEN (S_AXI_ACP_ARLEN), + .S_AXI_ARSIZE (S_AXI_ACP_ARSIZE), + .S_AXI_ARBURST (S_AXI_ACP_ARBURST), + .S_AXI_ARLOCK (S_AXI_ACP_ARLOCK), + .S_AXI_ARCACHE (S_AXI_ACP_ARCACHE), + .S_AXI_ARPROT (S_AXI_ACP_ARPROT), + //.S_AXI_ARUSER (S_AXI_ACP_ARUSER), + .S_AXI_ARUSER (param_aruser), + .S_AXI_ARVALID (S_AXI_ACP_ARVALID), + .S_AXI_ARREADY (S_AXI_ACP_ARREADY), + // Slave Interface Read Data Ports + .S_AXI_RID (S_AXI_ACP_RID), + .S_AXI_RDATA (S_AXI_ACP_RDATA), + .S_AXI_RRESP (S_AXI_ACP_RRESP), + .S_AXI_RLAST (S_AXI_ACP_RLAST), + .S_AXI_RUSER (), + .S_AXI_RVALID (S_AXI_ACP_RVALID), + .S_AXI_RREADY (S_AXI_ACP_RREADY), + + // Slave Interface Write Address Ports + .M_AXI_AWID (S_AXI_ATC_AWID), + .M_AXI_AWADDR (S_AXI_ATC_AWADDR), + .M_AXI_AWLEN (S_AXI_ATC_AWLEN), + .M_AXI_AWSIZE (S_AXI_ATC_AWSIZE), + .M_AXI_AWBURST (S_AXI_ATC_AWBURST), + .M_AXI_AWLOCK (S_AXI_ATC_AWLOCK), + .M_AXI_AWCACHE (S_AXI_ATC_AWCACHE), + .M_AXI_AWPROT (S_AXI_ATC_AWPROT), + .M_AXI_AWUSER (S_AXI_ATC_AWUSER), + .M_AXI_AWVALID (S_AXI_ATC_AWVALID), + .M_AXI_AWREADY (SAXIACPAWREADY_W), + // Slave Interface Write Data Ports + .M_AXI_WID (S_AXI_ATC_WID), + .M_AXI_WDATA (S_AXI_ATC_WDATA), + .M_AXI_WSTRB (S_AXI_ATC_WSTRB), + .M_AXI_WLAST (S_AXI_ATC_WLAST), + .M_AXI_WUSER (), + .M_AXI_WVALID (S_AXI_ATC_WVALID), + .M_AXI_WREADY (SAXIACPWREADY_W), + // Slave Interface Write Response Ports + .M_AXI_BID (SAXIACPBID_W), + .M_AXI_BRESP (SAXIACPBRESP_W), + .M_AXI_BUSER (), + .M_AXI_BVALID (SAXIACPBVALID_W), + .M_AXI_BREADY (S_AXI_ATC_BREADY), + // Slave Interface Read Address Ports + .M_AXI_ARID (S_AXI_ATC_ARID), + .M_AXI_ARADDR (S_AXI_ATC_ARADDR), + .M_AXI_ARLEN (S_AXI_ATC_ARLEN), + .M_AXI_ARSIZE (S_AXI_ATC_ARSIZE), + .M_AXI_ARBURST (S_AXI_ATC_ARBURST), + .M_AXI_ARLOCK (S_AXI_ATC_ARLOCK), + .M_AXI_ARCACHE (S_AXI_ATC_ARCACHE), + .M_AXI_ARPROT (S_AXI_ATC_ARPROT), + .M_AXI_ARUSER (S_AXI_ATC_ARUSER), + .M_AXI_ARVALID (S_AXI_ATC_ARVALID), + .M_AXI_ARREADY (SAXIACPARREADY_W), + // Slave Interface Read Data Ports + .M_AXI_RID (SAXIACPRID_W), + .M_AXI_RDATA (SAXIACPRDATA_W), + .M_AXI_RRESP (SAXIACPRRESP_W), + .M_AXI_RLAST (SAXIACPRLAST_W), + .M_AXI_RUSER (), + .M_AXI_RVALID (SAXIACPRVALID_W), + .M_AXI_RREADY (S_AXI_ATC_RREADY), + + + .ERROR_TRIGGER(), + .ERROR_TRANSACTION_ID() + ); + + + + end + endgenerate + + + + +endmodule + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init.c b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init.c new file mode 100644 index 0000000..5047c33 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init.c @@ -0,0 +1,12598 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000180[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000190[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xf + // .. .. ==> 0XF80001A0[13:8] = 0x0000000FU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100F00U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF800612C[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF8006130[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9b + // .. .. ==> 0XF8006134[19:10] = 0x0000009BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa2 + // .. .. ==> 0XF8006138[19:10] = 0x000000A2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006154[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006158[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF800615C[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x73 + // .. .. ==> 0XF8006160[9:0] = 0x00000073U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF8006168[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF800616C[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf0 + // .. .. ==> 0XF8006170[10:0] = 0x000000F0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf7 + // .. .. ==> 0XF8006174[10:0] = 0x000000F7U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF800617C[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF8006180[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006184[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xb3 + // .. .. ==> 0XF8006188[9:0] = 0x000000B3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000728[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800072C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000730[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000734[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000770[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000774[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000778[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800077C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000780[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000784[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000788[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800078C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000790[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000794[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000798[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800079C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 47 + // .. ==> 0XF8000830[21:16] = 0x0000002FU + // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000180[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000190[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xf + // .. .. ==> 0XF80001A0[13:8] = 0x0000000FU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100F00U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF800612C[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF8006130[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9b + // .. .. ==> 0XF8006134[19:10] = 0x0000009BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa2 + // .. .. ==> 0XF8006138[19:10] = 0x000000A2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006154[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006158[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF800615C[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x73 + // .. .. ==> 0XF8006160[9:0] = 0x00000073U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF8006168[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF800616C[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf0 + // .. .. ==> 0XF8006170[10:0] = 0x000000F0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf7 + // .. .. ==> 0XF8006174[10:0] = 0x000000F7U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF800617C[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF8006180[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006184[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xb3 + // .. .. ==> 0XF8006188[9:0] = 0x000000B3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000728[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800072C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000730[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000734[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000770[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000774[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000778[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800077C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000780[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000784[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000788[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800078C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000790[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000794[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000798[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800079C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 47 + // .. ==> 0XF8000830[21:16] = 0x0000002FU + // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000180[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000190[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xf + // .. .. ==> 0XF80001A0[13:8] = 0x0000000FU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100F00U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF800612C[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF8006130[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9b + // .. .. ==> 0XF8006134[19:10] = 0x0000009BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa2 + // .. .. ==> 0XF8006138[19:10] = 0x000000A2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006154[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006158[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF800615C[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x73 + // .. .. ==> 0XF8006160[9:0] = 0x00000073U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF8006168[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF800616C[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf0 + // .. .. ==> 0XF8006170[10:0] = 0x000000F0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf7 + // .. .. ==> 0XF8006174[10:0] = 0x000000F7U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF800617C[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF8006180[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006184[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xb3 + // .. .. ==> 0XF8006188[9:0] = 0x000000B3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000728[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800072C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000730[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000734[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000770[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000774[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000778[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800077C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000780[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000784[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000788[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800078C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000790[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000794[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000798[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800079C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 47 + // .. ==> 0XF8000830[21:16] = 0x0000002FU + // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + { + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init.h b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init.h new file mode 100644 index 0000000..408d5b9 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 125000000 +#define FPGA2_FREQ 200000000 +#define FPGA3_FREQ 66666672 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init.tcl b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init.tcl new file mode 100644 index 0000000..f485f9f --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init.tcl @@ -0,0 +1,853 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00000A03 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00200500 + mask_write 0XF8000180 0x03F03F30 0x00200400 + mask_write 0XF8000190 0x03F03F30 0x00100500 + mask_write 0XF80001A0 0x03F03F30 0x00100F00 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01FC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00027000 + mask_write 0XF8006130 0x000FFFFF 0x00027000 + mask_write 0XF8006134 0x000FFFFF 0x00026C00 + mask_write 0XF8006138 0x000FFFFF 0x00028800 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x0000007A + mask_write 0XF8006158 0x000FFFFF 0x0000007A + mask_write 0XF800615C 0x000FFFFF 0x0000007C + mask_write 0XF8006160 0x000FFFFF 0x00000073 + mask_write 0XF8006168 0x001FFFFF 0x000000F1 + mask_write 0XF800616C 0x001FFFFF 0x000000F1 + mask_write 0XF8006170 0x001FFFFF 0x000000F0 + mask_write 0XF8006174 0x001FFFFF 0x000000F7 + mask_write 0XF800617C 0x000FFFFF 0x000000BA + mask_write 0XF8006180 0x000FFFFF 0x000000BA + mask_write 0XF8006184 0x000FFFFF 0x000000BC + mask_write 0XF8006188 0x000FFFFF 0x000000B3 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068 + mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x000016E1 + mask_write 0XF800072C 0x00003FFF 0x000016E0 + mask_write 0XF8000730 0x00003FFF 0x00001640 + mask_write 0XF8000734 0x00003FFF 0x00001640 + mask_write 0XF8000738 0x00003FFF 0x00001640 + mask_write 0XF800073C 0x00003FFF 0x00001640 + mask_write 0XF8000740 0x00003FFF 0x00001302 + mask_write 0XF8000744 0x00003FFF 0x00001302 + mask_write 0XF8000748 0x00003FFF 0x00001302 + mask_write 0XF800074C 0x00003FFF 0x00001302 + mask_write 0XF8000750 0x00003FFF 0x00001302 + mask_write 0XF8000754 0x00003FFF 0x00001302 + mask_write 0XF8000758 0x00003FFF 0x00001303 + mask_write 0XF800075C 0x00003FFF 0x00001303 + mask_write 0XF8000760 0x00003FFF 0x00001303 + mask_write 0XF8000764 0x00003FFF 0x00001303 + mask_write 0XF8000768 0x00003FFF 0x00001303 + mask_write 0XF800076C 0x00003FFF 0x00001303 + mask_write 0XF8000770 0x00003FFF 0x00001304 + mask_write 0XF8000774 0x00003FFF 0x00001305 + mask_write 0XF8000778 0x00003FFF 0x00001304 + mask_write 0XF800077C 0x00003FFF 0x00001305 + mask_write 0XF8000780 0x00003FFF 0x00001304 + mask_write 0XF8000784 0x00003FFF 0x00001304 + mask_write 0XF8000788 0x00003FFF 0x00001304 + mask_write 0XF800078C 0x00003FFF 0x00001304 + mask_write 0XF8000790 0x00003FFF 0x00001305 + mask_write 0XF8000794 0x00003FFF 0x00001304 + mask_write 0XF8000798 0x00003FFF 0x00001304 + mask_write 0XF800079C 0x00003FFF 0x00001304 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A244 0x003FFFFF 0x00004000 + mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000 + mask_write 0XE000A248 0x003FFFFF 0x00004000 + mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00000A03 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00200500 + mask_write 0XF8000180 0x03F03F30 0x00200400 + mask_write 0XF8000190 0x03F03F30 0x00100500 + mask_write 0XF80001A0 0x03F03F30 0x00100F00 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01FC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00027000 + mask_write 0XF8006130 0x000FFFFF 0x00027000 + mask_write 0XF8006134 0x000FFFFF 0x00026C00 + mask_write 0XF8006138 0x000FFFFF 0x00028800 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x0000007A + mask_write 0XF8006158 0x000FFFFF 0x0000007A + mask_write 0XF800615C 0x000FFFFF 0x0000007C + mask_write 0XF8006160 0x000FFFFF 0x00000073 + mask_write 0XF8006168 0x001FFFFF 0x000000F1 + mask_write 0XF800616C 0x001FFFFF 0x000000F1 + mask_write 0XF8006170 0x001FFFFF 0x000000F0 + mask_write 0XF8006174 0x001FFFFF 0x000000F7 + mask_write 0XF800617C 0x000FFFFF 0x000000BA + mask_write 0XF8006180 0x000FFFFF 0x000000BA + mask_write 0XF8006184 0x000FFFFF 0x000000BC + mask_write 0XF8006188 0x000FFFFF 0x000000B3 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068 + mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x000016E1 + mask_write 0XF800072C 0x00003FFF 0x000016E0 + mask_write 0XF8000730 0x00003FFF 0x00001640 + mask_write 0XF8000734 0x00003FFF 0x00001640 + mask_write 0XF8000738 0x00003FFF 0x00001640 + mask_write 0XF800073C 0x00003FFF 0x00001640 + mask_write 0XF8000740 0x00003FFF 0x00001302 + mask_write 0XF8000744 0x00003FFF 0x00001302 + mask_write 0XF8000748 0x00003FFF 0x00001302 + mask_write 0XF800074C 0x00003FFF 0x00001302 + mask_write 0XF8000750 0x00003FFF 0x00001302 + mask_write 0XF8000754 0x00003FFF 0x00001302 + mask_write 0XF8000758 0x00003FFF 0x00001303 + mask_write 0XF800075C 0x00003FFF 0x00001303 + mask_write 0XF8000760 0x00003FFF 0x00001303 + mask_write 0XF8000764 0x00003FFF 0x00001303 + mask_write 0XF8000768 0x00003FFF 0x00001303 + mask_write 0XF800076C 0x00003FFF 0x00001303 + mask_write 0XF8000770 0x00003FFF 0x00001304 + mask_write 0XF8000774 0x00003FFF 0x00001305 + mask_write 0XF8000778 0x00003FFF 0x00001304 + mask_write 0XF800077C 0x00003FFF 0x00001305 + mask_write 0XF8000780 0x00003FFF 0x00001304 + mask_write 0XF8000784 0x00003FFF 0x00001304 + mask_write 0XF8000788 0x00003FFF 0x00001304 + mask_write 0XF800078C 0x00003FFF 0x00001304 + mask_write 0XF8000790 0x00003FFF 0x00001305 + mask_write 0XF8000794 0x00003FFF 0x00001304 + mask_write 0XF8000798 0x00003FFF 0x00001304 + mask_write 0XF800079C 0x00003FFF 0x00001304 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A244 0x003FFFFF 0x00004000 + mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000 + mask_write 0XE000A248 0x003FFFFF 0x00004000 + mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00000A03 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00200500 + mask_write 0XF8000180 0x03F03F30 0x00200400 + mask_write 0XF8000190 0x03F03F30 0x00100500 + mask_write 0XF80001A0 0x03F03F30 0x00100F00 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01FC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00027000 + mask_write 0XF8006130 0x000FFFFF 0x00027000 + mask_write 0XF8006134 0x000FFFFF 0x00026C00 + mask_write 0XF8006138 0x000FFFFF 0x00028800 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x0000007A + mask_write 0XF8006158 0x000FFFFF 0x0000007A + mask_write 0XF800615C 0x000FFFFF 0x0000007C + mask_write 0XF8006160 0x000FFFFF 0x00000073 + mask_write 0XF8006168 0x001FFFFF 0x000000F1 + mask_write 0XF800616C 0x001FFFFF 0x000000F1 + mask_write 0XF8006170 0x001FFFFF 0x000000F0 + mask_write 0XF8006174 0x001FFFFF 0x000000F7 + mask_write 0XF800617C 0x000FFFFF 0x000000BA + mask_write 0XF8006180 0x000FFFFF 0x000000BA + mask_write 0XF8006184 0x000FFFFF 0x000000BC + mask_write 0XF8006188 0x000FFFFF 0x000000B3 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068 + mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x000016E1 + mask_write 0XF800072C 0x00003FFF 0x000016E0 + mask_write 0XF8000730 0x00003FFF 0x00001640 + mask_write 0XF8000734 0x00003FFF 0x00001640 + mask_write 0XF8000738 0x00003FFF 0x00001640 + mask_write 0XF800073C 0x00003FFF 0x00001640 + mask_write 0XF8000740 0x00003FFF 0x00001302 + mask_write 0XF8000744 0x00003FFF 0x00001302 + mask_write 0XF8000748 0x00003FFF 0x00001302 + mask_write 0XF800074C 0x00003FFF 0x00001302 + mask_write 0XF8000750 0x00003FFF 0x00001302 + mask_write 0XF8000754 0x00003FFF 0x00001302 + mask_write 0XF8000758 0x00003FFF 0x00001303 + mask_write 0XF800075C 0x00003FFF 0x00001303 + mask_write 0XF8000760 0x00003FFF 0x00001303 + mask_write 0XF8000764 0x00003FFF 0x00001303 + mask_write 0XF8000768 0x00003FFF 0x00001303 + mask_write 0XF800076C 0x00003FFF 0x00001303 + mask_write 0XF8000770 0x00003FFF 0x00001304 + mask_write 0XF8000774 0x00003FFF 0x00001305 + mask_write 0XF8000778 0x00003FFF 0x00001304 + mask_write 0XF800077C 0x00003FFF 0x00001305 + mask_write 0XF8000780 0x00003FFF 0x00001304 + mask_write 0XF8000784 0x00003FFF 0x00001304 + mask_write 0XF8000788 0x00003FFF 0x00001304 + mask_write 0XF800078C 0x00003FFF 0x00001304 + mask_write 0XF8000790 0x00003FFF 0x00001305 + mask_write 0XF8000794 0x00003FFF 0x00001304 + mask_write 0XF8000798 0x00003FFF 0x00001304 + mask_write 0XF800079C 0x00003FFF 0x00001304 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A244 0x003FFFFF 0x00004000 + mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000 + mask_write 0XE000A248 0x003FFFFF 0x00004000 + mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 667000000 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init_gpl.c b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init_gpl.c new file mode 100644 index 0000000..99c594e --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init_gpl.c @@ -0,0 +1,12611 @@ +/****************************************************************************** +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000180[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000190[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xf + // .. .. ==> 0XF80001A0[13:8] = 0x0000000FU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100F00U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF800612C[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF8006130[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9b + // .. .. ==> 0XF8006134[19:10] = 0x0000009BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa2 + // .. .. ==> 0XF8006138[19:10] = 0x000000A2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006154[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006158[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF800615C[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x73 + // .. .. ==> 0XF8006160[9:0] = 0x00000073U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF8006168[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF800616C[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf0 + // .. .. ==> 0XF8006170[10:0] = 0x000000F0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf7 + // .. .. ==> 0XF8006174[10:0] = 0x000000F7U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF800617C[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF8006180[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006184[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xb3 + // .. .. ==> 0XF8006188[9:0] = 0x000000B3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000728[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800072C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000730[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000734[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000770[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000774[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000778[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800077C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000780[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000784[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000788[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800078C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000790[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000794[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000798[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800079C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 47 + // .. ==> 0XF8000830[21:16] = 0x0000002FU + // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000180[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000190[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xf + // .. .. ==> 0XF80001A0[13:8] = 0x0000000FU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100F00U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF800612C[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF8006130[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9b + // .. .. ==> 0XF8006134[19:10] = 0x0000009BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa2 + // .. .. ==> 0XF8006138[19:10] = 0x000000A2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006154[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006158[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF800615C[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x73 + // .. .. ==> 0XF8006160[9:0] = 0x00000073U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF8006168[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF800616C[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf0 + // .. .. ==> 0XF8006170[10:0] = 0x000000F0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf7 + // .. .. ==> 0XF8006174[10:0] = 0x000000F7U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF800617C[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF8006180[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006184[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xb3 + // .. .. ==> 0XF8006188[9:0] = 0x000000B3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000728[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800072C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000730[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000734[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000770[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000774[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000778[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800077C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000780[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000784[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000788[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800078C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000790[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000794[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000798[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800079C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 47 + // .. ==> 0XF8000830[21:16] = 0x0000002FU + // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000180[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000190[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xf + // .. .. ==> 0XF80001A0[13:8] = 0x0000000FU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100F00U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF800612C[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9c + // .. .. ==> 0XF8006130[19:10] = 0x0000009CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00027000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00027000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0x9b + // .. .. ==> 0XF8006134[19:10] = 0x0000009BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00026C00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00026C00U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa2 + // .. .. ==> 0XF8006138[19:10] = 0x000000A2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028800U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006154[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7a + // .. .. ==> 0XF8006158[9:0] = 0x0000007AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007AU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007AU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF800615C[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x73 + // .. .. ==> 0XF8006160[9:0] = 0x00000073U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000073U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000073U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF8006168[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf1 + // .. .. ==> 0XF800616C[10:0] = 0x000000F1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F1U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf0 + // .. .. ==> 0XF8006170[10:0] = 0x000000F0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf7 + // .. .. ==> 0XF8006174[10:0] = 0x000000F7U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F7U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF800617C[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xba + // .. .. ==> 0XF8006180[9:0] = 0x000000BAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BAU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006184[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xb3 + // .. .. ==> 0XF8006188[9:0] = 0x000000B3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B3U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000728[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800072C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000730[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000734[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000770[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000774[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000778[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800077C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000780[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000784[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000788[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800078C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000790[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000794[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000798[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800079C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 47 + // .. ==> 0XF8000830[21:16] = 0x0000002FU + // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + { + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init_gpl.h b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init_gpl.h new file mode 100644 index 0000000..7f3b64d --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 125000000 +#define FPGA2_FREQ 200000000 +#define FPGA3_FREQ 66666672 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_parameters.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_parameters.xml new file mode 100644 index 0000000..880eae6 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/ps7_parameters.xml @@ -0,0 +1,643 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/synth/design_3_processing_system7_0_0.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/synth/design_3_processing_system7_0_0.v new file mode 100644 index 0000000..64d5933 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/synth/design_3_processing_system7_0_0.v @@ -0,0 +1,1286 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:processing_system7:5.5 +// IP Revision: 6 + +(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2023.1" *) +(* CHECK_LICENSE_TYPE = "design_3_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) +(* CORE_GENERATION_INFO = "design_3_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK\ +=0,C_USE_DEFAULT_ACP_USER_VAL=1,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_\ +AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=2,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=1,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=TRUE,C_FCLK_CLK2_BUF=TRUE,C_FCLK_CLK3_BUF=TRUE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_TXN=1,C_\ +GP1_EN_MODIFIABLE_TXN=1}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_3_processing_system7_0_0 ( + SDIO0_WP, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + S_AXI_ACP_ARREADY, + S_AXI_ACP_AWREADY, + S_AXI_ACP_BVALID, + S_AXI_ACP_RLAST, + S_AXI_ACP_RVALID, + S_AXI_ACP_WREADY, + S_AXI_ACP_BRESP, + S_AXI_ACP_RRESP, + S_AXI_ACP_BID, + S_AXI_ACP_RID, + S_AXI_ACP_RDATA, + S_AXI_ACP_ACLK, + S_AXI_ACP_ARVALID, + S_AXI_ACP_AWVALID, + S_AXI_ACP_BREADY, + S_AXI_ACP_RREADY, + S_AXI_ACP_WLAST, + S_AXI_ACP_WVALID, + S_AXI_ACP_ARID, + S_AXI_ACP_ARPROT, + S_AXI_ACP_AWID, + S_AXI_ACP_AWPROT, + S_AXI_ACP_WID, + S_AXI_ACP_ARADDR, + S_AXI_ACP_AWADDR, + S_AXI_ACP_ARCACHE, + S_AXI_ACP_ARLEN, + S_AXI_ACP_ARQOS, + S_AXI_ACP_AWCACHE, + S_AXI_ACP_AWLEN, + S_AXI_ACP_AWQOS, + S_AXI_ACP_ARBURST, + S_AXI_ACP_ARLOCK, + S_AXI_ACP_ARSIZE, + S_AXI_ACP_AWBURST, + S_AXI_ACP_AWLOCK, + S_AXI_ACP_AWSIZE, + S_AXI_ACP_ARUSER, + S_AXI_ACP_AWUSER, + S_AXI_ACP_WDATA, + S_AXI_ACP_WSTRB, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + IRQ_F2P, + FCLK_CLK0, + FCLK_CLK1, + FCLK_CLK2, + FCLK_CLK3, + FCLK_RESET0_N, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB +); + +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *) +input wire SDIO0_WP; +output wire TTC0_WAVE0_OUT; +output wire TTC0_WAVE1_OUT; +output wire TTC0_WAVE2_OUT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) +output wire [1 : 0] USB0_PORT_INDCTL; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) +output wire USB0_VBUS_PWRSELECT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) +input wire USB0_VBUS_PWRFAULT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) +output wire M_AXI_GP0_ARVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) +output wire M_AXI_GP0_AWVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) +output wire M_AXI_GP0_BREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) +output wire M_AXI_GP0_RREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) +output wire M_AXI_GP0_WLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) +output wire M_AXI_GP0_WVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) +output wire [11 : 0] M_AXI_GP0_ARID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) +output wire [11 : 0] M_AXI_GP0_AWID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) +output wire [11 : 0] M_AXI_GP0_WID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) +output wire [1 : 0] M_AXI_GP0_ARBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) +output wire [1 : 0] M_AXI_GP0_ARLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) +output wire [2 : 0] M_AXI_GP0_ARSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) +output wire [1 : 0] M_AXI_GP0_AWBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) +output wire [1 : 0] M_AXI_GP0_AWLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) +output wire [2 : 0] M_AXI_GP0_AWSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) +output wire [2 : 0] M_AXI_GP0_ARPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) +output wire [2 : 0] M_AXI_GP0_AWPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) +output wire [31 : 0] M_AXI_GP0_ARADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) +output wire [31 : 0] M_AXI_GP0_AWADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) +output wire [31 : 0] M_AXI_GP0_WDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) +output wire [3 : 0] M_AXI_GP0_ARCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) +output wire [3 : 0] M_AXI_GP0_ARLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) +output wire [3 : 0] M_AXI_GP0_ARQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) +output wire [3 : 0] M_AXI_GP0_AWCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) +output wire [3 : 0] M_AXI_GP0_AWLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) +output wire [3 : 0] M_AXI_GP0_AWQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) +output wire [3 : 0] M_AXI_GP0_WSTRB; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) +input wire M_AXI_GP0_ACLK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) +input wire M_AXI_GP0_ARREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) +input wire M_AXI_GP0_AWREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) +input wire M_AXI_GP0_BVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) +input wire M_AXI_GP0_RLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) +input wire M_AXI_GP0_RVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) +input wire M_AXI_GP0_WREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) +input wire [11 : 0] M_AXI_GP0_BID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) +input wire [11 : 0] M_AXI_GP0_RID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) +input wire [1 : 0] M_AXI_GP0_BRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) +input wire [1 : 0] M_AXI_GP0_RRESP; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\ +S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) +input wire [31 : 0] M_AXI_GP0_RDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARREADY" *) +output wire S_AXI_ACP_ARREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWREADY" *) +output wire S_AXI_ACP_AWREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP BVALID" *) +output wire S_AXI_ACP_BVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP RLAST" *) +output wire S_AXI_ACP_RLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP RVALID" *) +output wire S_AXI_ACP_RVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WREADY" *) +output wire S_AXI_ACP_WREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP BRESP" *) +output wire [1 : 0] S_AXI_ACP_BRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP RRESP" *) +output wire [1 : 0] S_AXI_ACP_RRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP BID" *) +output wire [2 : 0] S_AXI_ACP_BID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP RID" *) +output wire [2 : 0] S_AXI_ACP_RID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP RDATA" *) +output wire [63 : 0] S_AXI_ACP_RDATA; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP_ACLK, ASSOCIATED_BUSIF S_AXI_ACP, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_ACP_ACLK CLK" *) +input wire S_AXI_ACP_ACLK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARVALID" *) +input wire S_AXI_ACP_ARVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWVALID" *) +input wire S_AXI_ACP_AWVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP BREADY" *) +input wire S_AXI_ACP_BREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP RREADY" *) +input wire S_AXI_ACP_RREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WLAST" *) +input wire S_AXI_ACP_WLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WVALID" *) +input wire S_AXI_ACP_WVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARID" *) +input wire [2 : 0] S_AXI_ACP_ARID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARPROT" *) +input wire [2 : 0] S_AXI_ACP_ARPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWID" *) +input wire [2 : 0] S_AXI_ACP_AWID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWPROT" *) +input wire [2 : 0] S_AXI_ACP_AWPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WID" *) +input wire [2 : 0] S_AXI_ACP_WID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARADDR" *) +input wire [31 : 0] S_AXI_ACP_ARADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWADDR" *) +input wire [31 : 0] S_AXI_ACP_AWADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARCACHE" *) +input wire [3 : 0] S_AXI_ACP_ARCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARLEN" *) +input wire [3 : 0] S_AXI_ACP_ARLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARQOS" *) +input wire [3 : 0] S_AXI_ACP_ARQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWCACHE" *) +input wire [3 : 0] S_AXI_ACP_AWCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWLEN" *) +input wire [3 : 0] S_AXI_ACP_AWLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWQOS" *) +input wire [3 : 0] S_AXI_ACP_AWQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARBURST" *) +input wire [1 : 0] S_AXI_ACP_ARBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARLOCK" *) +input wire [1 : 0] S_AXI_ACP_ARLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARSIZE" *) +input wire [2 : 0] S_AXI_ACP_ARSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWBURST" *) +input wire [1 : 0] S_AXI_ACP_AWBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWLOCK" *) +input wire [1 : 0] S_AXI_ACP_AWLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWSIZE" *) +input wire [2 : 0] S_AXI_ACP_AWSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARUSER" *) +input wire [4 : 0] S_AXI_ACP_ARUSER; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWUSER" *) +input wire [4 : 0] S_AXI_ACP_AWUSER; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WDATA" *) +input wire [63 : 0] S_AXI_ACP_WDATA; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 5, ARUSER_WIDTH 5, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS\ + 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WSTRB" *) +input wire [7 : 0] S_AXI_ACP_WSTRB; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *) +output wire S_AXI_HP0_ARREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *) +output wire S_AXI_HP0_AWREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *) +output wire S_AXI_HP0_BVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *) +output wire S_AXI_HP0_RLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *) +output wire S_AXI_HP0_RVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *) +output wire S_AXI_HP0_WREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *) +output wire [1 : 0] S_AXI_HP0_BRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *) +output wire [1 : 0] S_AXI_HP0_RRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *) +output wire [5 : 0] S_AXI_HP0_BID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *) +output wire [5 : 0] S_AXI_HP0_RID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *) +output wire [63 : 0] S_AXI_HP0_RDATA; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *) +output wire [7 : 0] S_AXI_HP0_RCOUNT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *) +output wire [7 : 0] S_AXI_HP0_WCOUNT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *) +output wire [2 : 0] S_AXI_HP0_RACOUNT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *) +output wire [5 : 0] S_AXI_HP0_WACOUNT; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0_ACLK, ASSOCIATED_BUSIF S_AXI_HP0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *) +input wire S_AXI_HP0_ACLK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *) +input wire S_AXI_HP0_ARVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *) +input wire S_AXI_HP0_AWVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *) +input wire S_AXI_HP0_BREADY; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *) +input wire S_AXI_HP0_RDISSUECAP1_EN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *) +input wire S_AXI_HP0_RREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *) +input wire S_AXI_HP0_WLAST; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *) +input wire S_AXI_HP0_WRISSUECAP1_EN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *) +input wire S_AXI_HP0_WVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *) +input wire [1 : 0] S_AXI_HP0_ARBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *) +input wire [1 : 0] S_AXI_HP0_ARLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *) +input wire [2 : 0] S_AXI_HP0_ARSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *) +input wire [1 : 0] S_AXI_HP0_AWBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *) +input wire [1 : 0] S_AXI_HP0_AWLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *) +input wire [2 : 0] S_AXI_HP0_AWSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *) +input wire [2 : 0] S_AXI_HP0_ARPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *) +input wire [2 : 0] S_AXI_HP0_AWPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *) +input wire [31 : 0] S_AXI_HP0_ARADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *) +input wire [31 : 0] S_AXI_HP0_AWADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *) +input wire [3 : 0] S_AXI_HP0_ARCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *) +input wire [3 : 0] S_AXI_HP0_ARLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *) +input wire [3 : 0] S_AXI_HP0_ARQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *) +input wire [3 : 0] S_AXI_HP0_AWCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *) +input wire [3 : 0] S_AXI_HP0_AWLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *) +input wire [3 : 0] S_AXI_HP0_AWQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *) +input wire [5 : 0] S_AXI_HP0_ARID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *) +input wire [5 : 0] S_AXI_HP0_AWID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *) +input wire [5 : 0] S_AXI_HP0_WID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *) +input wire [63 : 0] S_AXI_HP0_WDATA; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS\ + 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *) +input wire [7 : 0] S_AXI_HP0_WSTRB; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:NULL, PortWidth 2" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) +input wire [1 : 0] IRQ_F2P; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) +output wire FCLK_CLK0; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) +output wire FCLK_CLK1; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *) +output wire FCLK_CLK2; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_3_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *) +output wire FCLK_CLK3; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) +output wire FCLK_RESET0_N; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) +inout wire [53 : 0] MIO; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) +inout wire DDR_CAS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) +inout wire DDR_CKE; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) +inout wire DDR_Clk_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) +inout wire DDR_Clk; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) +inout wire DDR_CS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) +inout wire DDR_DRSTB; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) +inout wire DDR_ODT; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) +inout wire DDR_RAS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) +inout wire DDR_WEB; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) +inout wire [2 : 0] DDR_BankAddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) +inout wire [14 : 0] DDR_Addr; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) +inout wire DDR_VRN; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) +inout wire DDR_VRP; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) +inout wire [3 : 0] DDR_DM; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) +inout wire [31 : 0] DDR_DQ; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) +inout wire [3 : 0] DDR_DQS_n; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) +inout wire [3 : 0] DDR_DQS; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) +inout wire PS_SRSTB; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) +inout wire PS_CLK; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) +inout wire PS_PORB; + + processing_system7_v5_5_processing_system7 #( + .C_EN_EMIO_PJTAG(0), + .C_EN_EMIO_ENET0(0), + .C_EN_EMIO_ENET1(0), + .C_EN_EMIO_TRACE(0), + .C_INCLUDE_TRACE_BUFFER(0), + .C_TRACE_BUFFER_FIFO_SIZE(128), + .USE_TRACE_DATA_EDGE_DETECTOR(0), + .C_TRACE_PIPELINE_WIDTH(8), + .C_TRACE_BUFFER_CLOCK_DELAY(12), + .C_EMIO_GPIO_WIDTH(64), + .C_INCLUDE_ACP_TRANS_CHECK(0), + .C_USE_DEFAULT_ACP_USER_VAL(1), + .C_S_AXI_ACP_ARUSER_VAL(31), + .C_S_AXI_ACP_AWUSER_VAL(31), + .C_M_AXI_GP0_ID_WIDTH(12), + .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP1_ID_WIDTH(12), + .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0), + .C_S_AXI_GP0_ID_WIDTH(6), + .C_S_AXI_GP1_ID_WIDTH(6), + .C_S_AXI_ACP_ID_WIDTH(3), + .C_S_AXI_HP0_ID_WIDTH(6), + .C_S_AXI_HP0_DATA_WIDTH(64), + .C_S_AXI_HP1_ID_WIDTH(6), + .C_S_AXI_HP1_DATA_WIDTH(64), + .C_S_AXI_HP2_ID_WIDTH(6), + .C_S_AXI_HP2_DATA_WIDTH(64), + .C_S_AXI_HP3_ID_WIDTH(6), + .C_S_AXI_HP3_DATA_WIDTH(64), + .C_M_AXI_GP0_THREAD_ID_WIDTH(12), + .C_M_AXI_GP1_THREAD_ID_WIDTH(12), + .C_NUM_F2P_INTR_INPUTS(2), + .C_IRQ_F2P_MODE("DIRECT"), + .C_DQ_WIDTH(32), + .C_DQS_WIDTH(4), + .C_DM_WIDTH(4), + .C_MIO_PRIMITIVE(54), + .C_TRACE_INTERNAL_WIDTH(2), + .C_USE_AXI_NONSECURE(0), + .C_USE_M_AXI_GP0(1), + .C_USE_M_AXI_GP1(0), + .C_USE_S_AXI_GP0(0), + .C_USE_S_AXI_GP1(0), + .C_USE_S_AXI_HP0(1), + .C_USE_S_AXI_HP1(0), + .C_USE_S_AXI_HP2(0), + .C_USE_S_AXI_HP3(0), + .C_USE_S_AXI_ACP(1), + .C_PS7_SI_REV("PRODUCTION"), + .C_FCLK_CLK0_BUF("TRUE"), + .C_FCLK_CLK1_BUF("TRUE"), + .C_FCLK_CLK2_BUF("TRUE"), + .C_FCLK_CLK3_BUF("TRUE"), + .C_PACKAGE_NAME("clg400"), + .C_GP0_EN_MODIFIABLE_TXN(1), + .C_GP1_EN_MODIFIABLE_TXN(1) + ) inst ( + .CAN0_PHY_TX(), + .CAN0_PHY_RX(1'B0), + .CAN1_PHY_TX(), + .CAN1_PHY_RX(1'B0), + .ENET0_GMII_TX_EN(), + .ENET0_GMII_TX_ER(), + .ENET0_MDIO_MDC(), + .ENET0_MDIO_O(), + .ENET0_MDIO_T(), + .ENET0_PTP_DELAY_REQ_RX(), + .ENET0_PTP_DELAY_REQ_TX(), + .ENET0_PTP_PDELAY_REQ_RX(), + .ENET0_PTP_PDELAY_REQ_TX(), + .ENET0_PTP_PDELAY_RESP_RX(), + .ENET0_PTP_PDELAY_RESP_TX(), + .ENET0_PTP_SYNC_FRAME_RX(), + .ENET0_PTP_SYNC_FRAME_TX(), + .ENET0_SOF_RX(), + .ENET0_SOF_TX(), + .ENET0_GMII_TXD(), + .ENET0_GMII_COL(1'B0), + .ENET0_GMII_CRS(1'B0), + .ENET0_GMII_RX_CLK(1'B0), + .ENET0_GMII_RX_DV(1'B0), + .ENET0_GMII_RX_ER(1'B0), + .ENET0_GMII_TX_CLK(1'B0), + .ENET0_MDIO_I(1'B0), + .ENET0_EXT_INTIN(1'B0), + .ENET0_GMII_RXD(8'B0), + .ENET1_GMII_TX_EN(), + .ENET1_GMII_TX_ER(), + .ENET1_MDIO_MDC(), + .ENET1_MDIO_O(), + .ENET1_MDIO_T(), + .ENET1_PTP_DELAY_REQ_RX(), + .ENET1_PTP_DELAY_REQ_TX(), + .ENET1_PTP_PDELAY_REQ_RX(), + .ENET1_PTP_PDELAY_REQ_TX(), + .ENET1_PTP_PDELAY_RESP_RX(), + .ENET1_PTP_PDELAY_RESP_TX(), + .ENET1_PTP_SYNC_FRAME_RX(), + .ENET1_PTP_SYNC_FRAME_TX(), + .ENET1_SOF_RX(), + .ENET1_SOF_TX(), + .ENET1_GMII_TXD(), + .ENET1_GMII_COL(1'B0), + .ENET1_GMII_CRS(1'B0), + .ENET1_GMII_RX_CLK(1'B0), + .ENET1_GMII_RX_DV(1'B0), + .ENET1_GMII_RX_ER(1'B0), + .ENET1_GMII_TX_CLK(1'B0), + .ENET1_MDIO_I(1'B0), + .ENET1_EXT_INTIN(1'B0), + .ENET1_GMII_RXD(8'B0), + .GPIO_I(64'B0), + .GPIO_O(), + .GPIO_T(), + .I2C0_SDA_I(1'B0), + .I2C0_SDA_O(), + .I2C0_SDA_T(), + .I2C0_SCL_I(1'B0), + .I2C0_SCL_O(), + .I2C0_SCL_T(), + .I2C1_SDA_I(1'B0), + .I2C1_SDA_O(), + .I2C1_SDA_T(), + .I2C1_SCL_I(1'B0), + .I2C1_SCL_O(), + .I2C1_SCL_T(), + .PJTAG_TCK(1'B0), + .PJTAG_TMS(1'B0), + .PJTAG_TDI(1'B0), + .PJTAG_TDO(), + .SDIO0_CLK(), + .SDIO0_CLK_FB(1'B0), + .SDIO0_CMD_O(), + .SDIO0_CMD_I(1'B0), + .SDIO0_CMD_T(), + .SDIO0_DATA_I(4'B0), + .SDIO0_DATA_O(), + .SDIO0_DATA_T(), + .SDIO0_LED(), + .SDIO0_CDN(1'B0), + .SDIO0_WP(SDIO0_WP), + .SDIO0_BUSPOW(), + .SDIO0_BUSVOLT(), + .SDIO1_CLK(), + .SDIO1_CLK_FB(1'B0), + .SDIO1_CMD_O(), + .SDIO1_CMD_I(1'B0), + .SDIO1_CMD_T(), + .SDIO1_DATA_I(4'B0), + .SDIO1_DATA_O(), + .SDIO1_DATA_T(), + .SDIO1_LED(), + .SDIO1_CDN(1'B0), + .SDIO1_WP(1'B0), + .SDIO1_BUSPOW(), + .SDIO1_BUSVOLT(), + .SPI0_SCLK_I(1'B0), + .SPI0_SCLK_O(), + .SPI0_SCLK_T(), + .SPI0_MOSI_I(1'B0), + .SPI0_MOSI_O(), + .SPI0_MOSI_T(), + .SPI0_MISO_I(1'B0), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_SS_I(1'B0), + .SPI0_SS_O(), + .SPI0_SS1_O(), + .SPI0_SS2_O(), + .SPI0_SS_T(), + .SPI1_SCLK_I(1'B0), + .SPI1_SCLK_O(), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'B0), + .SPI1_MOSI_O(), + .SPI1_MOSI_T(), + .SPI1_MISO_I(1'B0), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'B0), + .SPI1_SS_O(), + .SPI1_SS1_O(), + .SPI1_SS2_O(), + .SPI1_SS_T(), + .UART0_DTRN(), + .UART0_RTSN(), + .UART0_TX(), + .UART0_CTSN(1'B0), + .UART0_DCDN(1'B0), + .UART0_DSRN(1'B0), + .UART0_RIN(1'B0), + .UART0_RX(1'B1), + .UART1_DTRN(), + .UART1_RTSN(), + .UART1_TX(), + .UART1_CTSN(1'B0), + .UART1_DCDN(1'B0), + .UART1_DSRN(1'B0), + .UART1_RIN(1'B0), + .UART1_RX(1'B1), + .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT), + .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT), + .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT), + .TTC0_CLK0_IN(1'B0), + .TTC0_CLK1_IN(1'B0), + .TTC0_CLK2_IN(1'B0), + .TTC1_WAVE0_OUT(), + .TTC1_WAVE1_OUT(), + .TTC1_WAVE2_OUT(), + .TTC1_CLK0_IN(1'B0), + .TTC1_CLK1_IN(1'B0), + .TTC1_CLK2_IN(1'B0), + .WDT_CLK_IN(1'B0), + .WDT_RST_OUT(), + .TRACE_CLK(1'B0), + .TRACE_CLK_OUT(), + .TRACE_CTL(), + .TRACE_DATA(), + .USB0_PORT_INDCTL(USB0_PORT_INDCTL), + .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), + .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), + .USB1_PORT_INDCTL(), + .USB1_VBUS_PWRSELECT(), + .USB1_VBUS_PWRFAULT(1'B0), + .SRAM_INTIN(1'B0), + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP1_ARVALID(), + .M_AXI_GP1_AWVALID(), + .M_AXI_GP1_BREADY(), + .M_AXI_GP1_RREADY(), + .M_AXI_GP1_WLAST(), + .M_AXI_GP1_WVALID(), + .M_AXI_GP1_ARID(), + .M_AXI_GP1_AWID(), + .M_AXI_GP1_WID(), + .M_AXI_GP1_ARBURST(), + .M_AXI_GP1_ARLOCK(), + .M_AXI_GP1_ARSIZE(), + .M_AXI_GP1_AWBURST(), + .M_AXI_GP1_AWLOCK(), + .M_AXI_GP1_AWSIZE(), + .M_AXI_GP1_ARPROT(), + .M_AXI_GP1_AWPROT(), + .M_AXI_GP1_ARADDR(), + .M_AXI_GP1_AWADDR(), + .M_AXI_GP1_WDATA(), + .M_AXI_GP1_ARCACHE(), + .M_AXI_GP1_ARLEN(), + .M_AXI_GP1_ARQOS(), + .M_AXI_GP1_AWCACHE(), + .M_AXI_GP1_AWLEN(), + .M_AXI_GP1_AWQOS(), + .M_AXI_GP1_WSTRB(), + .M_AXI_GP1_ACLK(1'B0), + .M_AXI_GP1_ARREADY(1'B0), + .M_AXI_GP1_AWREADY(1'B0), + .M_AXI_GP1_BVALID(1'B0), + .M_AXI_GP1_RLAST(1'B0), + .M_AXI_GP1_RVALID(1'B0), + .M_AXI_GP1_WREADY(1'B0), + .M_AXI_GP1_BID(12'B0), + .M_AXI_GP1_RID(12'B0), + .M_AXI_GP1_BRESP(2'B0), + .M_AXI_GP1_RRESP(2'B0), + .M_AXI_GP1_RDATA(32'B0), + .S_AXI_GP0_ARREADY(), + .S_AXI_GP0_AWREADY(), + .S_AXI_GP0_BVALID(), + .S_AXI_GP0_RLAST(), + .S_AXI_GP0_RVALID(), + .S_AXI_GP0_WREADY(), + .S_AXI_GP0_BRESP(), + .S_AXI_GP0_RRESP(), + .S_AXI_GP0_RDATA(), + .S_AXI_GP0_BID(), + .S_AXI_GP0_RID(), + .S_AXI_GP0_ACLK(1'B0), + .S_AXI_GP0_ARVALID(1'B0), + .S_AXI_GP0_AWVALID(1'B0), + .S_AXI_GP0_BREADY(1'B0), + .S_AXI_GP0_RREADY(1'B0), + .S_AXI_GP0_WLAST(1'B0), + .S_AXI_GP0_WVALID(1'B0), + .S_AXI_GP0_ARBURST(2'B0), + .S_AXI_GP0_ARLOCK(2'B0), + .S_AXI_GP0_ARSIZE(3'B0), + .S_AXI_GP0_AWBURST(2'B0), + .S_AXI_GP0_AWLOCK(2'B0), + .S_AXI_GP0_AWSIZE(3'B0), + .S_AXI_GP0_ARPROT(3'B0), + .S_AXI_GP0_AWPROT(3'B0), + .S_AXI_GP0_ARADDR(32'B0), + .S_AXI_GP0_AWADDR(32'B0), + .S_AXI_GP0_WDATA(32'B0), + .S_AXI_GP0_ARCACHE(4'B0), + .S_AXI_GP0_ARLEN(4'B0), + .S_AXI_GP0_ARQOS(4'B0), + .S_AXI_GP0_AWCACHE(4'B0), + .S_AXI_GP0_AWLEN(4'B0), + .S_AXI_GP0_AWQOS(4'B0), + .S_AXI_GP0_WSTRB(4'B0), + .S_AXI_GP0_ARID(6'B0), + .S_AXI_GP0_AWID(6'B0), + .S_AXI_GP0_WID(6'B0), + .S_AXI_GP1_ARREADY(), + .S_AXI_GP1_AWREADY(), + .S_AXI_GP1_BVALID(), + .S_AXI_GP1_RLAST(), + .S_AXI_GP1_RVALID(), + .S_AXI_GP1_WREADY(), + .S_AXI_GP1_BRESP(), + .S_AXI_GP1_RRESP(), + .S_AXI_GP1_RDATA(), + .S_AXI_GP1_BID(), + .S_AXI_GP1_RID(), + .S_AXI_GP1_ACLK(1'B0), + .S_AXI_GP1_ARVALID(1'B0), + .S_AXI_GP1_AWVALID(1'B0), + .S_AXI_GP1_BREADY(1'B0), + .S_AXI_GP1_RREADY(1'B0), + .S_AXI_GP1_WLAST(1'B0), + .S_AXI_GP1_WVALID(1'B0), + .S_AXI_GP1_ARBURST(2'B0), + .S_AXI_GP1_ARLOCK(2'B0), + .S_AXI_GP1_ARSIZE(3'B0), + .S_AXI_GP1_AWBURST(2'B0), + .S_AXI_GP1_AWLOCK(2'B0), + .S_AXI_GP1_AWSIZE(3'B0), + .S_AXI_GP1_ARPROT(3'B0), + .S_AXI_GP1_AWPROT(3'B0), + .S_AXI_GP1_ARADDR(32'B0), + .S_AXI_GP1_AWADDR(32'B0), + .S_AXI_GP1_WDATA(32'B0), + .S_AXI_GP1_ARCACHE(4'B0), + .S_AXI_GP1_ARLEN(4'B0), + .S_AXI_GP1_ARQOS(4'B0), + .S_AXI_GP1_AWCACHE(4'B0), + .S_AXI_GP1_AWLEN(4'B0), + .S_AXI_GP1_AWQOS(4'B0), + .S_AXI_GP1_WSTRB(4'B0), + .S_AXI_GP1_ARID(6'B0), + .S_AXI_GP1_AWID(6'B0), + .S_AXI_GP1_WID(6'B0), + .S_AXI_ACP_ARREADY(S_AXI_ACP_ARREADY), + .S_AXI_ACP_AWREADY(S_AXI_ACP_AWREADY), + .S_AXI_ACP_BVALID(S_AXI_ACP_BVALID), + .S_AXI_ACP_RLAST(S_AXI_ACP_RLAST), + .S_AXI_ACP_RVALID(S_AXI_ACP_RVALID), + .S_AXI_ACP_WREADY(S_AXI_ACP_WREADY), + .S_AXI_ACP_BRESP(S_AXI_ACP_BRESP), + .S_AXI_ACP_RRESP(S_AXI_ACP_RRESP), + .S_AXI_ACP_BID(S_AXI_ACP_BID), + .S_AXI_ACP_RID(S_AXI_ACP_RID), + .S_AXI_ACP_RDATA(S_AXI_ACP_RDATA), + .S_AXI_ACP_ACLK(S_AXI_ACP_ACLK), + .S_AXI_ACP_ARVALID(S_AXI_ACP_ARVALID), + .S_AXI_ACP_AWVALID(S_AXI_ACP_AWVALID), + .S_AXI_ACP_BREADY(S_AXI_ACP_BREADY), + .S_AXI_ACP_RREADY(S_AXI_ACP_RREADY), + .S_AXI_ACP_WLAST(S_AXI_ACP_WLAST), + .S_AXI_ACP_WVALID(S_AXI_ACP_WVALID), + .S_AXI_ACP_ARID(S_AXI_ACP_ARID), + .S_AXI_ACP_ARPROT(S_AXI_ACP_ARPROT), + .S_AXI_ACP_AWID(S_AXI_ACP_AWID), + .S_AXI_ACP_AWPROT(S_AXI_ACP_AWPROT), + .S_AXI_ACP_WID(S_AXI_ACP_WID), + .S_AXI_ACP_ARADDR(S_AXI_ACP_ARADDR), + .S_AXI_ACP_AWADDR(S_AXI_ACP_AWADDR), + .S_AXI_ACP_ARCACHE(S_AXI_ACP_ARCACHE), + .S_AXI_ACP_ARLEN(S_AXI_ACP_ARLEN), + .S_AXI_ACP_ARQOS(S_AXI_ACP_ARQOS), + .S_AXI_ACP_AWCACHE(S_AXI_ACP_AWCACHE), + .S_AXI_ACP_AWLEN(S_AXI_ACP_AWLEN), + .S_AXI_ACP_AWQOS(S_AXI_ACP_AWQOS), + .S_AXI_ACP_ARBURST(S_AXI_ACP_ARBURST), + .S_AXI_ACP_ARLOCK(S_AXI_ACP_ARLOCK), + .S_AXI_ACP_ARSIZE(S_AXI_ACP_ARSIZE), + .S_AXI_ACP_AWBURST(S_AXI_ACP_AWBURST), + .S_AXI_ACP_AWLOCK(S_AXI_ACP_AWLOCK), + .S_AXI_ACP_AWSIZE(S_AXI_ACP_AWSIZE), + .S_AXI_ACP_ARUSER(S_AXI_ACP_ARUSER), + .S_AXI_ACP_AWUSER(S_AXI_ACP_AWUSER), + .S_AXI_ACP_WDATA(S_AXI_ACP_WDATA), + .S_AXI_ACP_WSTRB(S_AXI_ACP_WSTRB), + .S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY), + .S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY), + .S_AXI_HP0_BVALID(S_AXI_HP0_BVALID), + .S_AXI_HP0_RLAST(S_AXI_HP0_RLAST), + .S_AXI_HP0_RVALID(S_AXI_HP0_RVALID), + .S_AXI_HP0_WREADY(S_AXI_HP0_WREADY), + .S_AXI_HP0_BRESP(S_AXI_HP0_BRESP), + .S_AXI_HP0_RRESP(S_AXI_HP0_RRESP), + .S_AXI_HP0_BID(S_AXI_HP0_BID), + .S_AXI_HP0_RID(S_AXI_HP0_RID), + .S_AXI_HP0_RDATA(S_AXI_HP0_RDATA), + .S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT), + .S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT), + .S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT), + .S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT), + .S_AXI_HP0_ACLK(S_AXI_HP0_ACLK), + .S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID), + .S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID), + .S_AXI_HP0_BREADY(S_AXI_HP0_BREADY), + .S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN), + .S_AXI_HP0_RREADY(S_AXI_HP0_RREADY), + .S_AXI_HP0_WLAST(S_AXI_HP0_WLAST), + .S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN), + .S_AXI_HP0_WVALID(S_AXI_HP0_WVALID), + .S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST), + .S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK), + .S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST), + .S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK), + .S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT), + .S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT), + .S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR), + .S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR), + .S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN), + .S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS), + .S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN), + .S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS), + .S_AXI_HP0_ARID(S_AXI_HP0_ARID), + .S_AXI_HP0_AWID(S_AXI_HP0_AWID), + .S_AXI_HP0_WID(S_AXI_HP0_WID), + .S_AXI_HP0_WDATA(S_AXI_HP0_WDATA), + .S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB), + .S_AXI_HP1_ARREADY(), + .S_AXI_HP1_AWREADY(), + .S_AXI_HP1_BVALID(), + .S_AXI_HP1_RLAST(), + .S_AXI_HP1_RVALID(), + .S_AXI_HP1_WREADY(), + .S_AXI_HP1_BRESP(), + .S_AXI_HP1_RRESP(), + .S_AXI_HP1_BID(), + .S_AXI_HP1_RID(), + .S_AXI_HP1_RDATA(), + .S_AXI_HP1_RCOUNT(), + .S_AXI_HP1_WCOUNT(), + .S_AXI_HP1_RACOUNT(), + .S_AXI_HP1_WACOUNT(), + .S_AXI_HP1_ACLK(1'B0), + .S_AXI_HP1_ARVALID(1'B0), + .S_AXI_HP1_AWVALID(1'B0), + .S_AXI_HP1_BREADY(1'B0), + .S_AXI_HP1_RDISSUECAP1_EN(1'B0), + .S_AXI_HP1_RREADY(1'B0), + .S_AXI_HP1_WLAST(1'B0), + .S_AXI_HP1_WRISSUECAP1_EN(1'B0), + .S_AXI_HP1_WVALID(1'B0), + .S_AXI_HP1_ARBURST(2'B0), + .S_AXI_HP1_ARLOCK(2'B0), + .S_AXI_HP1_ARSIZE(3'B0), + .S_AXI_HP1_AWBURST(2'B0), + .S_AXI_HP1_AWLOCK(2'B0), + .S_AXI_HP1_AWSIZE(3'B0), + .S_AXI_HP1_ARPROT(3'B0), + .S_AXI_HP1_AWPROT(3'B0), + .S_AXI_HP1_ARADDR(32'B0), + .S_AXI_HP1_AWADDR(32'B0), + .S_AXI_HP1_ARCACHE(4'B0), + .S_AXI_HP1_ARLEN(4'B0), + .S_AXI_HP1_ARQOS(4'B0), + .S_AXI_HP1_AWCACHE(4'B0), + .S_AXI_HP1_AWLEN(4'B0), + .S_AXI_HP1_AWQOS(4'B0), + .S_AXI_HP1_ARID(6'B0), + .S_AXI_HP1_AWID(6'B0), + .S_AXI_HP1_WID(6'B0), + .S_AXI_HP1_WDATA(64'B0), + .S_AXI_HP1_WSTRB(8'B0), + .S_AXI_HP2_ARREADY(), + .S_AXI_HP2_AWREADY(), + .S_AXI_HP2_BVALID(), + .S_AXI_HP2_RLAST(), + .S_AXI_HP2_RVALID(), + .S_AXI_HP2_WREADY(), + .S_AXI_HP2_BRESP(), + .S_AXI_HP2_RRESP(), + .S_AXI_HP2_BID(), + .S_AXI_HP2_RID(), + .S_AXI_HP2_RDATA(), + .S_AXI_HP2_RCOUNT(), + .S_AXI_HP2_WCOUNT(), + .S_AXI_HP2_RACOUNT(), + .S_AXI_HP2_WACOUNT(), + .S_AXI_HP2_ACLK(1'B0), + .S_AXI_HP2_ARVALID(1'B0), + .S_AXI_HP2_AWVALID(1'B0), + .S_AXI_HP2_BREADY(1'B0), + .S_AXI_HP2_RDISSUECAP1_EN(1'B0), + .S_AXI_HP2_RREADY(1'B0), + .S_AXI_HP2_WLAST(1'B0), + .S_AXI_HP2_WRISSUECAP1_EN(1'B0), + .S_AXI_HP2_WVALID(1'B0), + .S_AXI_HP2_ARBURST(2'B0), + .S_AXI_HP2_ARLOCK(2'B0), + .S_AXI_HP2_ARSIZE(3'B0), + .S_AXI_HP2_AWBURST(2'B0), + .S_AXI_HP2_AWLOCK(2'B0), + .S_AXI_HP2_AWSIZE(3'B0), + .S_AXI_HP2_ARPROT(3'B0), + .S_AXI_HP2_AWPROT(3'B0), + .S_AXI_HP2_ARADDR(32'B0), + .S_AXI_HP2_AWADDR(32'B0), + .S_AXI_HP2_ARCACHE(4'B0), + .S_AXI_HP2_ARLEN(4'B0), + .S_AXI_HP2_ARQOS(4'B0), + .S_AXI_HP2_AWCACHE(4'B0), + .S_AXI_HP2_AWLEN(4'B0), + .S_AXI_HP2_AWQOS(4'B0), + .S_AXI_HP2_ARID(6'B0), + .S_AXI_HP2_AWID(6'B0), + .S_AXI_HP2_WID(6'B0), + .S_AXI_HP2_WDATA(64'B0), + .S_AXI_HP2_WSTRB(8'B0), + .S_AXI_HP3_ARREADY(), + .S_AXI_HP3_AWREADY(), + .S_AXI_HP3_BVALID(), + .S_AXI_HP3_RLAST(), + .S_AXI_HP3_RVALID(), + .S_AXI_HP3_WREADY(), + .S_AXI_HP3_BRESP(), + .S_AXI_HP3_RRESP(), + .S_AXI_HP3_BID(), + .S_AXI_HP3_RID(), + .S_AXI_HP3_RDATA(), + .S_AXI_HP3_RCOUNT(), + .S_AXI_HP3_WCOUNT(), + .S_AXI_HP3_RACOUNT(), + .S_AXI_HP3_WACOUNT(), + .S_AXI_HP3_ACLK(1'B0), + .S_AXI_HP3_ARVALID(1'B0), + .S_AXI_HP3_AWVALID(1'B0), + .S_AXI_HP3_BREADY(1'B0), + .S_AXI_HP3_RDISSUECAP1_EN(1'B0), + .S_AXI_HP3_RREADY(1'B0), + .S_AXI_HP3_WLAST(1'B0), + .S_AXI_HP3_WRISSUECAP1_EN(1'B0), + .S_AXI_HP3_WVALID(1'B0), + .S_AXI_HP3_ARBURST(2'B0), + .S_AXI_HP3_ARLOCK(2'B0), + .S_AXI_HP3_ARSIZE(3'B0), + .S_AXI_HP3_AWBURST(2'B0), + .S_AXI_HP3_AWLOCK(2'B0), + .S_AXI_HP3_AWSIZE(3'B0), + .S_AXI_HP3_ARPROT(3'B0), + .S_AXI_HP3_AWPROT(3'B0), + .S_AXI_HP3_ARADDR(32'B0), + .S_AXI_HP3_AWADDR(32'B0), + .S_AXI_HP3_ARCACHE(4'B0), + .S_AXI_HP3_ARLEN(4'B0), + .S_AXI_HP3_ARQOS(4'B0), + .S_AXI_HP3_AWCACHE(4'B0), + .S_AXI_HP3_AWLEN(4'B0), + .S_AXI_HP3_AWQOS(4'B0), + .S_AXI_HP3_ARID(6'B0), + .S_AXI_HP3_AWID(6'B0), + .S_AXI_HP3_WID(6'B0), + .S_AXI_HP3_WDATA(64'B0), + .S_AXI_HP3_WSTRB(8'B0), + .IRQ_P2F_DMAC_ABORT(), + .IRQ_P2F_DMAC0(), + .IRQ_P2F_DMAC1(), + .IRQ_P2F_DMAC2(), + .IRQ_P2F_DMAC3(), + .IRQ_P2F_DMAC4(), + .IRQ_P2F_DMAC5(), + .IRQ_P2F_DMAC6(), + .IRQ_P2F_DMAC7(), + .IRQ_P2F_SMC(), + .IRQ_P2F_QSPI(), + .IRQ_P2F_CTI(), + .IRQ_P2F_GPIO(), + .IRQ_P2F_USB0(), + .IRQ_P2F_ENET0(), + .IRQ_P2F_ENET_WAKE0(), + .IRQ_P2F_SDIO0(), + .IRQ_P2F_I2C0(), + .IRQ_P2F_SPI0(), + .IRQ_P2F_UART0(), + .IRQ_P2F_CAN0(), + .IRQ_P2F_USB1(), + .IRQ_P2F_ENET1(), + .IRQ_P2F_ENET_WAKE1(), + .IRQ_P2F_SDIO1(), + .IRQ_P2F_I2C1(), + .IRQ_P2F_SPI1(), + .IRQ_P2F_UART1(), + .IRQ_P2F_CAN1(), + .IRQ_F2P(IRQ_F2P), + .Core0_nFIQ(1'B0), + .Core0_nIRQ(1'B0), + .Core1_nFIQ(1'B0), + .Core1_nIRQ(1'B0), + .DMA0_DATYPE(), + .DMA0_DAVALID(), + .DMA0_DRREADY(), + .DMA1_DATYPE(), + .DMA1_DAVALID(), + .DMA1_DRREADY(), + .DMA2_DATYPE(), + .DMA2_DAVALID(), + .DMA2_DRREADY(), + .DMA3_DATYPE(), + .DMA3_DAVALID(), + .DMA3_DRREADY(), + .DMA0_ACLK(1'B0), + .DMA0_DAREADY(1'B0), + .DMA0_DRLAST(1'B0), + .DMA0_DRVALID(1'B0), + .DMA1_ACLK(1'B0), + .DMA1_DAREADY(1'B0), + .DMA1_DRLAST(1'B0), + .DMA1_DRVALID(1'B0), + .DMA2_ACLK(1'B0), + .DMA2_DAREADY(1'B0), + .DMA2_DRLAST(1'B0), + .DMA2_DRVALID(1'B0), + .DMA3_ACLK(1'B0), + .DMA3_DAREADY(1'B0), + .DMA3_DRLAST(1'B0), + .DMA3_DRVALID(1'B0), + .DMA0_DRTYPE(2'B0), + .DMA1_DRTYPE(2'B0), + .DMA2_DRTYPE(2'B0), + .DMA3_DRTYPE(2'B0), + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_CLK3(FCLK_CLK3), + .FCLK_CLKTRIG0_N(1'B0), + .FCLK_CLKTRIG1_N(1'B0), + .FCLK_CLKTRIG2_N(1'B0), + .FCLK_CLKTRIG3_N(1'B0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(), + .FCLK_RESET2_N(), + .FCLK_RESET3_N(), + .FTMD_TRACEIN_DATA(32'B0), + .FTMD_TRACEIN_VALID(1'B0), + .FTMD_TRACEIN_CLK(1'B0), + .FTMD_TRACEIN_ATID(4'B0), + .FTMT_F2P_TRIG_0(1'B0), + .FTMT_F2P_TRIGACK_0(), + .FTMT_F2P_TRIG_1(1'B0), + .FTMT_F2P_TRIGACK_1(), + .FTMT_F2P_TRIG_2(1'B0), + .FTMT_F2P_TRIGACK_2(), + .FTMT_F2P_TRIG_3(1'B0), + .FTMT_F2P_TRIGACK_3(), + .FTMT_F2P_DEBUG(32'B0), + .FTMT_P2F_TRIGACK_0(1'B0), + .FTMT_P2F_TRIG_0(), + .FTMT_P2F_TRIGACK_1(1'B0), + .FTMT_P2F_TRIG_1(), + .FTMT_P2F_TRIGACK_2(1'B0), + .FTMT_P2F_TRIG_2(), + .FTMT_P2F_TRIGACK_3(1'B0), + .FTMT_P2F_TRIG_3(), + .FTMT_P2F_DEBUG(), + .FPGA_IDLE_N(1'B0), + .EVENT_EVENTO(), + .EVENT_STANDBYWFE(), + .EVENT_STANDBYWFI(), + .EVENT_EVENTI(1'B0), + .DDR_ARB(4'B0), + .MIO(MIO), + .DDR_CAS_n(DDR_CAS_n), + .DDR_CKE(DDR_CKE), + .DDR_Clk_n(DDR_Clk_n), + .DDR_Clk(DDR_Clk), + .DDR_CS_n(DDR_CS_n), + .DDR_DRSTB(DDR_DRSTB), + .DDR_ODT(DDR_ODT), + .DDR_RAS_n(DDR_RAS_n), + .DDR_WEB(DDR_WEB), + .DDR_BankAddr(DDR_BankAddr), + .DDR_Addr(DDR_Addr), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_DM(DDR_DM), + .DDR_DQ(DDR_DQ), + .DDR_DQS_n(DDR_DQS_n), + .DDR_DQS(DDR_DQS), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); +endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_ps7_0_axi_periph_0/design_3_ps7_0_axi_periph_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_ps7_0_axi_periph_0/design_3_ps7_0_axi_periph_0.xml new file mode 100644 index 0000000..3b589e4 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ip/design_3_ps7_0_axi_periph_0/design_3_ps7_0_axi_periph_0.xml @@ -0,0 +1,1644 @@ + + + xilinx.com + customized_ip + design_3_ps7_0_axi_periph_0 + 1.0 + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_661c4a03 + 2 + 4 + 8 + 16 + 32 + 64 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_76d086ea + 0 + 1 + 2 + + + choice_pairs_ab2668a2 + 0 + 1 + 2 + + + choice_pairs_b6c9535e + 0 + 1 + 3 + 4 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 1 + + + NUM_MI + Number of Master Interfaces + 3 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 3 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 0 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 0 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_SECURE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_SECURE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_SECURE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_SECURE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_SECURE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_SECURE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_SECURE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_SECURE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_SECURE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_SECURE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_SECURE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_SECURE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_SECURE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_SECURE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_SECURE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_SECURE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_SECURE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_SECURE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_SECURE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_SECURE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_SECURE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_SECURE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_SECURE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_SECURE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_SECURE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_SECURE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_SECURE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_SECURE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_SECURE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_SECURE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_SECURE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_SECURE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_SECURE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_SECURE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_SECURE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_SECURE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_SECURE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_SECURE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_SECURE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_SECURE + Incicates whether M63_AXI connects to a secure slave + 0 + + + S00_ARB_PRIORITY + Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S01_ARB_PRIORITY + Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S02_ARB_PRIORITY + Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S03_ARB_PRIORITY + Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S04_ARB_PRIORITY + Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S05_ARB_PRIORITY + Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S06_ARB_PRIORITY + Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S07_ARB_PRIORITY + Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S08_ARB_PRIORITY + Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S09_ARB_PRIORITY + Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S10_ARB_PRIORITY + Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S11_ARB_PRIORITY + Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S12_ARB_PRIORITY + Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S13_ARB_PRIORITY + Controls S13_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S14_ARB_PRIORITY + Controls S14_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S15_ARB_PRIORITY + Controls S15_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + Component_Name + design_3_ps7_0_axi_periph_0 + + + + + AXI Interconnect + 29 + + + + + + + + 2023.1 + + + + + diff --git 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xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + initiator_6_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + initiator_6_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + initiator_7_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + initiator_7_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + initiator_8_wr_socket + AXIMM Write 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true + + + + + + M04_A05_ADDR_WIDTH + My M04_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A06_ADDR_WIDTH + My M04_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A07_ADDR_WIDTH + My M04_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A08_ADDR_WIDTH + My M04_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A09_ADDR_WIDTH + My M04_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A10_ADDR_WIDTH + My M04_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A11_ADDR_WIDTH + My M04_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A12_ADDR_WIDTH + My M04_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A13_ADDR_WIDTH + My M04_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A14_ADDR_WIDTH + My M04_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A15_ADDR_WIDTH + My M04_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A00_ADDR_WIDTH + My M05_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A01_ADDR_WIDTH + My M05_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A02_ADDR_WIDTH + My M05_A02_ADDR_WIDTH + 0 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M06_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A01_ADDR_WIDTH + My M06_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A02_ADDR_WIDTH + My M06_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A03_ADDR_WIDTH + My M06_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A04_ADDR_WIDTH + My M06_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A05_ADDR_WIDTH + My M06_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A06_ADDR_WIDTH + My M06_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A07_ADDR_WIDTH + My M06_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A08_ADDR_WIDTH + My M06_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A09_ADDR_WIDTH + My M06_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A10_ADDR_WIDTH + My M06_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A11_ADDR_WIDTH + My M06_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A12_ADDR_WIDTH + My M06_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A13_ADDR_WIDTH + My M06_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A14_ADDR_WIDTH + My M06_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A15_ADDR_WIDTH + My M06_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A00_ADDR_WIDTH + My M07_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A01_ADDR_WIDTH + My M07_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A02_ADDR_WIDTH + My M07_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A03_ADDR_WIDTH + My M07_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A04_ADDR_WIDTH + My M07_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A05_ADDR_WIDTH + My M07_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A06_ADDR_WIDTH + My M07_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A07_ADDR_WIDTH + My M07_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A08_ADDR_WIDTH + My M07_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A09_ADDR_WIDTH + My M07_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A10_ADDR_WIDTH + My M07_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A11_ADDR_WIDTH + My M07_A11_ADDR_WIDTH + 0 + + + + true + + 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d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v new file mode 100644 index 0000000..98caca1 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v @@ -0,0 +1,409 @@ +//----------------------------------------------------------------------------- +//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved. +//-- +//-- This file contains confidential and proprietary information +//-- of Xilinx, Inc. and is protected under U.S. and +//-- international copyright and other intellectual property +//-- laws. +//-- +//-- DISCLAIMER +//-- This disclaimer is not a license and does not grant any +//-- rights to the materials distributed herewith. Except as +//-- otherwise provided in a valid license issued to you by +//-- Xilinx, and to the maximum extent permitted by applicable +//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +//-- (2) Xilinx shall not be liable (whether in contract or tort, +//-- including negligence, or under any other theory of +//-- liability) for any loss or damage of any kind or nature +//-- related to, arising under or in connection with these +//-- materials, including for any direct, or any indirect, +//-- special, incidental, or consequential loss or damage +//-- (including loss of data, profits, goodwill, or any type of +//-- loss or damage suffered as a result of any action brought +//-- by a third party) even if such damage or loss was +//-- reasonably foreseeable or Xilinx had been advised of the +//-- possibility of the same. +//-- +//-- CRITICAL APPLICATIONS +//-- Xilinx products are not designed or intended to be fail- +//-- safe, or for use in any application requiring fail-safe +//-- performance, such as life-support or safety devices or +//-- systems, Class III medical devices, nuclear facilities, +//-- applications related to the deployment of airbags, or any +//-- other applications that could lead to death, personal +//-- injury, or severe property or environmental damage +//-- (individually and collectively, "Critical +//-- Applications"). Customer assumes the sole risk and +//-- liability of any use of Xilinx products in Critical +//-- Applications, subject only to applicable laws and +//-- regulations governing limitations on product liability. +//-- +//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +//-- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: ACP Transaction Checker +// +// Check for optimized ACP transactions and flag if they are broken. +// +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// atc +// aw_atc +// w_atc +// b_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps +`default_nettype none + +module processing_system7_v5_5_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_ADDR_WIDTH = 32, + // Width of all ADDR signals on SI and MI side of checker. + // Range: 32. + parameter integer C_AXI_DATA_WIDTH = 64, + // Width of all DATA signals on SI and MI side of checker. + // Range: 64. + parameter integer C_AXI_AWUSER_WIDTH = 1, + // Width of AWUSER signals. + // Range: >= 1. + parameter integer C_AXI_ARUSER_WIDTH = 1, + // Width of ARUSER signals. + // Range: >= 1. + parameter integer C_AXI_WUSER_WIDTH = 1, + // Width of WUSER signals. + // Range: >= 1. + parameter integer C_AXI_RUSER_WIDTH = 1, + // Width of RUSER signals. + // Range: >= 1. + parameter integer C_AXI_BUSER_WIDTH = 1 + // Width of BUSER signals. + // Range: >= 1. + ) + ( + // Global Signals + input wire ACLK, + input wire ARESETN, + + // Slave Interface Write Address Ports + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, + input wire [4-1:0] S_AXI_AWLEN, + input wire [3-1:0] S_AXI_AWSIZE, + input wire [2-1:0] S_AXI_AWBURST, + input wire [2-1:0] S_AXI_AWLOCK, + input wire [4-1:0] S_AXI_AWCACHE, + input wire [3-1:0] S_AXI_AWPROT, + input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, + input wire S_AXI_AWVALID, + output wire S_AXI_AWREADY, + // Slave Interface Write Data Ports + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID, + input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, + input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, + input wire S_AXI_WLAST, + input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, + input wire S_AXI_WVALID, + output wire S_AXI_WREADY, + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, + output wire [2-1:0] S_AXI_BRESP, + output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, + output wire S_AXI_BVALID, + input wire S_AXI_BREADY, + // Slave Interface Read Address Ports + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, + input wire [4-1:0] S_AXI_ARLEN, + input wire [3-1:0] S_AXI_ARSIZE, + input wire [2-1:0] S_AXI_ARBURST, + input wire [2-1:0] S_AXI_ARLOCK, + input wire [4-1:0] S_AXI_ARCACHE, + input wire [3-1:0] S_AXI_ARPROT, + input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, + input wire S_AXI_ARVALID, + output wire S_AXI_ARREADY, + // Slave Interface Read Data Ports + output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, + output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, + output wire [2-1:0] S_AXI_RRESP, + output wire S_AXI_RLAST, + output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, + output wire S_AXI_RVALID, + input wire S_AXI_RREADY, + + // Master Interface Write Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, + output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, + output wire [4-1:0] M_AXI_AWLEN, + output wire [3-1:0] M_AXI_AWSIZE, + output wire [2-1:0] M_AXI_AWBURST, + output wire [2-1:0] M_AXI_AWLOCK, + output wire [4-1:0] M_AXI_AWCACHE, + output wire [3-1:0] M_AXI_AWPROT, + output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, + output wire M_AXI_AWVALID, + input wire M_AXI_AWREADY, + // Master Interface Write Data Ports + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, + output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, + output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, + output wire M_AXI_WLAST, + output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, + output wire M_AXI_WVALID, + input wire M_AXI_WREADY, + // Master Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, + input wire [2-1:0] M_AXI_BRESP, + input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, + input wire M_AXI_BVALID, + output wire M_AXI_BREADY, + // Master Interface Read Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID, + output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, + output wire [4-1:0] M_AXI_ARLEN, + output wire [3-1:0] M_AXI_ARSIZE, + output wire [2-1:0] M_AXI_ARBURST, + output wire [2-1:0] M_AXI_ARLOCK, + output wire [4-1:0] M_AXI_ARCACHE, + output wire [3-1:0] M_AXI_ARPROT, + output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, + output wire M_AXI_ARVALID, + input wire M_AXI_ARREADY, + // Master Interface Read Data Ports + input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, + input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, + input wire [2-1:0] M_AXI_RRESP, + input wire M_AXI_RLAST, + input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, + input wire M_AXI_RVALID, + output wire M_AXI_RREADY, + + output wire ERROR_TRIGGER, + output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + localparam C_FIFO_DEPTH_LOG = 4; + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Internal reset. + reg ARESET; + + // AW->W command queue signals. + wire cmd_w_valid; + wire cmd_w_check; + wire [C_AXI_ID_WIDTH-1:0] cmd_w_id; + wire cmd_w_ready; + + // W->B command queue signals. + wire cmd_b_push; + wire cmd_b_error; + wire [C_AXI_ID_WIDTH-1:0] cmd_b_id; + wire cmd_b_full; + wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr; + wire cmd_b_ready; + + + ///////////////////////////////////////////////////////////////////////////// + // Handle Internal Reset + ///////////////////////////////////////////////////////////////////////////// + always @ (posedge ACLK) begin + ARESET <= !ARESETN; + end + + + ///////////////////////////////////////////////////////////////////////////// + // Handle Write Channels (AW/W/B) + ///////////////////////////////////////////////////////////////////////////// + + // Write Address Channel. + processing_system7_v5_5_aw_atc # + ( + .C_FAMILY (C_FAMILY), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), + .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), + .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG) + ) write_addr_inst + ( + // Global Signals + .ARESET (ARESET), + .ACLK (ACLK), + + // Command Interface (Out) + .cmd_w_valid (cmd_w_valid), + .cmd_w_check (cmd_w_check), + .cmd_w_id (cmd_w_id), + .cmd_w_ready (cmd_w_ready), + .cmd_b_addr (cmd_b_addr), + .cmd_b_ready (cmd_b_ready), + + // Slave Interface Write Address Ports + .S_AXI_AWID (S_AXI_AWID), + .S_AXI_AWADDR (S_AXI_AWADDR), + .S_AXI_AWLEN (S_AXI_AWLEN), + .S_AXI_AWSIZE (S_AXI_AWSIZE), + .S_AXI_AWBURST (S_AXI_AWBURST), + .S_AXI_AWLOCK (S_AXI_AWLOCK), + .S_AXI_AWCACHE (S_AXI_AWCACHE), + .S_AXI_AWPROT (S_AXI_AWPROT), + .S_AXI_AWUSER (S_AXI_AWUSER), + .S_AXI_AWVALID (S_AXI_AWVALID), + .S_AXI_AWREADY (S_AXI_AWREADY), + + // Master Interface Write Address Port + .M_AXI_AWID (M_AXI_AWID), + .M_AXI_AWADDR (M_AXI_AWADDR), + .M_AXI_AWLEN (M_AXI_AWLEN), + .M_AXI_AWSIZE (M_AXI_AWSIZE), + .M_AXI_AWBURST (M_AXI_AWBURST), + .M_AXI_AWLOCK (M_AXI_AWLOCK), + .M_AXI_AWCACHE (M_AXI_AWCACHE), + .M_AXI_AWPROT (M_AXI_AWPROT), + .M_AXI_AWUSER (M_AXI_AWUSER), + .M_AXI_AWVALID (M_AXI_AWVALID), + .M_AXI_AWREADY (M_AXI_AWREADY) + ); + + // Write Data channel. + processing_system7_v5_5_w_atc # + ( + .C_FAMILY (C_FAMILY), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), + .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH) + ) write_data_inst + ( + // Global Signals + .ARESET (ARESET), + .ACLK (ACLK), + + // Command Interface (In) + .cmd_w_valid (cmd_w_valid), + .cmd_w_check (cmd_w_check), + .cmd_w_id (cmd_w_id), + .cmd_w_ready (cmd_w_ready), + + // Command Interface (Out) + .cmd_b_push (cmd_b_push), + .cmd_b_error (cmd_b_error), + .cmd_b_id (cmd_b_id), + .cmd_b_full (cmd_b_full), + + // Slave Interface Write Data Ports + .S_AXI_WID (S_AXI_WID), + .S_AXI_WDATA (S_AXI_WDATA), + .S_AXI_WSTRB (S_AXI_WSTRB), + .S_AXI_WLAST (S_AXI_WLAST), + .S_AXI_WUSER (S_AXI_WUSER), + .S_AXI_WVALID (S_AXI_WVALID), + .S_AXI_WREADY (S_AXI_WREADY), + + // Master Interface Write Data Ports + .M_AXI_WID (M_AXI_WID), + .M_AXI_WDATA (M_AXI_WDATA), + .M_AXI_WSTRB (M_AXI_WSTRB), + .M_AXI_WLAST (M_AXI_WLAST), + .M_AXI_WUSER (M_AXI_WUSER), + .M_AXI_WVALID (M_AXI_WVALID), + .M_AXI_WREADY (M_AXI_WREADY) + ); + + // Write Response channel. + processing_system7_v5_5_b_atc # + ( + .C_FAMILY (C_FAMILY), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), + .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG) + ) write_response_inst + ( + // Global Signals + .ARESET (ARESET), + .ACLK (ACLK), + + // Command Interface (In) + .cmd_b_push (cmd_b_push), + .cmd_b_error (cmd_b_error), + .cmd_b_id (cmd_b_id), + .cmd_b_full (cmd_b_full), + .cmd_b_addr (cmd_b_addr), + .cmd_b_ready (cmd_b_ready), + + // Slave Interface Write Response Ports + .S_AXI_BID (S_AXI_BID), + .S_AXI_BRESP (S_AXI_BRESP), + .S_AXI_BUSER (S_AXI_BUSER), + .S_AXI_BVALID (S_AXI_BVALID), + .S_AXI_BREADY (S_AXI_BREADY), + + // Master Interface Write Response Ports + .M_AXI_BID (M_AXI_BID), + .M_AXI_BRESP (M_AXI_BRESP), + .M_AXI_BUSER (M_AXI_BUSER), + .M_AXI_BVALID (M_AXI_BVALID), + .M_AXI_BREADY (M_AXI_BREADY), + + // Trigger detection + .ERROR_TRIGGER (ERROR_TRIGGER), + .ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID) + ); + + + + ///////////////////////////////////////////////////////////////////////////// + // Handle Read Channels (AR/R) + ///////////////////////////////////////////////////////////////////////////// + // Read Address Port + assign M_AXI_ARID = S_AXI_ARID; + assign M_AXI_ARADDR = S_AXI_ARADDR; + assign M_AXI_ARLEN = S_AXI_ARLEN; + assign M_AXI_ARSIZE = S_AXI_ARSIZE; + assign M_AXI_ARBURST = S_AXI_ARBURST; + assign M_AXI_ARLOCK = S_AXI_ARLOCK; + assign M_AXI_ARCACHE = S_AXI_ARCACHE; + assign M_AXI_ARPROT = S_AXI_ARPROT; + assign M_AXI_ARUSER = S_AXI_ARUSER; + assign M_AXI_ARVALID = S_AXI_ARVALID; + assign S_AXI_ARREADY = M_AXI_ARREADY; + + // Read Data Port + assign S_AXI_RID = M_AXI_RID; + assign S_AXI_RDATA = M_AXI_RDATA; + assign S_AXI_RRESP = M_AXI_RRESP; + assign S_AXI_RLAST = M_AXI_RLAST; + assign S_AXI_RUSER = M_AXI_RUSER; + assign S_AXI_RVALID = M_AXI_RVALID; + assign M_AXI_RREADY = S_AXI_RREADY; + + +endmodule +`default_nettype wire diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v new file mode 100644 index 0000000..25bbc9d --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v @@ -0,0 +1,298 @@ +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Address Write Channel for ATC +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// aw_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + + +module processing_system7_v5_5_aw_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_ADDR_WIDTH = 32, + // Width of all ADDR signals on SI and MI side of checker. + // Range: 32. + parameter integer C_AXI_AWUSER_WIDTH = 1, + // Width of AWUSER signals. + // Range: >= 1. + parameter integer C_FIFO_DEPTH_LOG = 4 + ) + ( + // Global Signals + input wire ARESET, + input wire ACLK, + + // Command Interface + output reg cmd_w_valid, + output wire cmd_w_check, + output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, + input wire cmd_w_ready, + input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, + input wire cmd_b_ready, + + // Slave Interface Write Address Port + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, + input wire [4-1:0] S_AXI_AWLEN, + input wire [3-1:0] S_AXI_AWSIZE, + input wire [2-1:0] S_AXI_AWBURST, + input wire [2-1:0] S_AXI_AWLOCK, + input wire [4-1:0] S_AXI_AWCACHE, + input wire [3-1:0] S_AXI_AWPROT, + input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, + input wire S_AXI_AWVALID, + output wire S_AXI_AWREADY, + + // Master Interface Write Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, + output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, + output wire [4-1:0] M_AXI_AWLEN, + output wire [3-1:0] M_AXI_AWSIZE, + output wire [2-1:0] M_AXI_AWBURST, + output wire [2-1:0] M_AXI_AWLOCK, + output wire [4-1:0] M_AXI_AWCACHE, + output wire [3-1:0] M_AXI_AWPROT, + output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, + output wire M_AXI_AWVALID, + input wire M_AXI_AWREADY + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + // Constants for burst types. + localparam [2-1:0] C_FIX_BURST = 2'b00; + localparam [2-1:0] C_INCR_BURST = 2'b01; + localparam [2-1:0] C_WRAP_BURST = 2'b10; + + // Constants for size. + localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011; + + // Constants for length. + localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011; + + // Constants for cacheline address. + localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0; + + // Command FIFO settings + localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; + localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + ///////////////////////////////////////////////////////////////////////////// + + integer index; + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Transaction properties. + wire access_is_incr; + wire access_is_wrap; + wire access_is_coherent; + wire access_optimized_size; + wire incr_addr_boundary; + wire incr_is_optimized; + wire wrap_is_optimized; + wire access_is_optimized; + + // Command FIFO. + wire cmd_w_push; + reg cmd_full; + reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; + wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr; + reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Decode: + // + // Detect if transaction is of correct typ, size and length to qualify as + // an optimized transaction that has to be checked for errors. + // + ///////////////////////////////////////////////////////////////////////////// + + // Transaction burst type. + assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST ); + assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST ); + + // Transaction has to be Coherent. + assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) & + ( S_AXI_AWCACHE[1] == 1'b1 ); + + // Transaction cacheline boundary address. + assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET ); + + // Transaction length & size. + assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & + ( S_AXI_AWLEN == C_OPTIMIZED_LEN ); + + // Transaction is optimized. + assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary; + assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size; + assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized ); + + + ///////////////////////////////////////////////////////////////////////////// + // Command FIFO: + // + // Since supported write interleaving is only 1, it is safe to use only a + // simple SRL based FIFO as a command queue. + // + ///////////////////////////////////////////////////////////////////////////// + + // Determine when transaction infromation is pushed to the FIFO. + assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full; + + // SRL FIFO Pointer. + always @ (posedge ACLK) begin + if (ARESET) begin + addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; + end else begin + if ( cmd_w_push & ~cmd_w_ready ) begin + addr_ptr <= addr_ptr + 1; + end else if ( ~cmd_w_push & cmd_w_ready ) begin + addr_ptr <= addr_ptr - 1; + end + end + end + + // Total number of buffered commands. + assign all_addr_ptr = addr_ptr + cmd_b_addr + 2; + + // FIFO Flags. + always @ (posedge ACLK) begin + if (ARESET) begin + cmd_full <= 1'b0; + cmd_w_valid <= 1'b0; + end else begin + if ( cmd_w_push & ~cmd_w_ready ) begin + cmd_w_valid <= 1'b1; + end else if ( ~cmd_w_push & cmd_w_ready ) begin + cmd_w_valid <= ( addr_ptr != 0 ); + end + if ( cmd_w_push & ~cmd_b_ready ) begin + // Going to full. + cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 ); + end else if ( ~cmd_w_push & cmd_b_ready ) begin + // Pop in middle of queue doesn't affect full status. + cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 ); + end + end + end + + // Infere SRL for storage. + always @ (posedge ACLK) begin + if ( cmd_w_push ) begin + for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin + data_srl[index+1] <= data_srl[index]; + end + data_srl[0] <= {access_is_optimized, S_AXI_AWID}; + end + end + + // Get current transaction info. + assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr]; + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Throttling: + // + // Stall commands if FIFO is full. + // + ///////////////////////////////////////////////////////////////////////////// + + // Propagate masked valid. + assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full; + + // Return ready with push back. + assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full; + + + ///////////////////////////////////////////////////////////////////////////// + // Address Write propagation: + // + // All information is simply forwarded on from the SI- to MI-Side untouched. + // + ///////////////////////////////////////////////////////////////////////////// + + // 1:1 mapping. + assign M_AXI_AWID = S_AXI_AWID; + assign M_AXI_AWADDR = S_AXI_AWADDR; + assign M_AXI_AWLEN = S_AXI_AWLEN; + assign M_AXI_AWSIZE = S_AXI_AWSIZE; + assign M_AXI_AWBURST = S_AXI_AWBURST; + assign M_AXI_AWLOCK = S_AXI_AWLOCK; + assign M_AXI_AWCACHE = S_AXI_AWCACHE; + assign M_AXI_AWPROT = S_AXI_AWPROT; + assign M_AXI_AWUSER = S_AXI_AWUSER; + + +endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v new file mode 100644 index 0000000..36f280f --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v @@ -0,0 +1,413 @@ +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Write Response Channel for ATC +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// b_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + + +module processing_system7_v5_5_b_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_BUSER_WIDTH = 1, + // Width of AWUSER signals. + // Range: >= 1. + parameter integer C_FIFO_DEPTH_LOG = 4 + ) + ( + // Global Signals + input wire ARESET, + input wire ACLK, + + // Command Interface + input wire cmd_b_push, + input wire cmd_b_error, + input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id, + output wire cmd_b_ready, + output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, + output reg cmd_b_full, + + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, + output reg [2-1:0] S_AXI_BRESP, + output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, + output wire S_AXI_BVALID, + input wire S_AXI_BREADY, + + // Master Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, + input wire [2-1:0] M_AXI_BRESP, + input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, + input wire M_AXI_BVALID, + output wire M_AXI_BREADY, + + // Trigger detection + output reg ERROR_TRIGGER, + output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + // Constants for packing levels. + localparam [2-1:0] C_RESP_OKAY = 2'b00; + localparam [2-1:0] C_RESP_EXOKAY = 2'b01; + localparam [2-1:0] C_RESP_SLVERROR = 2'b10; + localparam [2-1:0] C_RESP_DECERR = 2'b11; + + // Command FIFO settings + localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; + localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + ///////////////////////////////////////////////////////////////////////////// + + integer index; + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Command Queue. + reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; + reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; + reg cmd_b_valid; + wire cmd_b_ready_i; + wire inject_error; + wire [C_AXI_ID_WIDTH-1:0] current_id; + + // Search command. + wire found_match; + wire use_match; + wire matching_id; + + // Manage valid command. + wire write_valid_cmd; + reg [C_FIFO_DEPTH-2:0] valid_cmd; + reg [C_FIFO_DEPTH-2:0] updated_valid_cmd; + reg [C_FIFO_DEPTH-2:0] next_valid_cmd; + reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr; + reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr; + + // Pipelined data + reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I; + reg [2-1:0] M_AXI_BRESP_I; + reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I; + reg M_AXI_BVALID_I; + wire M_AXI_BREADY_I; + + + ///////////////////////////////////////////////////////////////////////////// + // Command Queue: + // + // Keep track of depth of Queue to generate full flag. + // + // Also generate valid to mark pressence of commands in Queue. + // + // Maintain Queue and extract data from currently searched entry. + // + ///////////////////////////////////////////////////////////////////////////// + + // SRL FIFO Pointer. + always @ (posedge ACLK) begin + if (ARESET) begin + addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; + end else begin + if ( cmd_b_push & ~cmd_b_ready_i ) begin + // Pushing data increase length/addr. + addr_ptr <= addr_ptr + 1; + end else if ( cmd_b_ready_i ) begin + // Collapse addr when data is popped. + addr_ptr <= collapsed_addr_ptr; + end + end + end + + // FIFO Flags. + always @ (posedge ACLK) begin + if (ARESET) begin + cmd_b_full <= 1'b0; + cmd_b_valid <= 1'b0; + end else begin + if ( cmd_b_push & ~cmd_b_ready_i ) begin + cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 ); + cmd_b_valid <= 1'b1; + end else if ( ~cmd_b_push & cmd_b_ready_i ) begin + cmd_b_full <= 1'b0; + cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 ); + end + end + end + + // Infere SRL for storage. + always @ (posedge ACLK) begin + if ( cmd_b_push ) begin + for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin + data_srl[index+1] <= data_srl[index]; + end + data_srl[0] <= {cmd_b_error, cmd_b_id}; + end + end + + // Get current transaction info. + assign {inject_error, current_id} = data_srl[search_addr_ptr]; + + // Assign outputs. + assign cmd_b_addr = collapsed_addr_ptr; + + + ///////////////////////////////////////////////////////////////////////////// + // Search Command Queue: + // + // Search for matching valid command in queue. + // + // A command is found when an valid entry with correct ID is found. The queue + // is search from the oldest entry, i.e. from a high value. + // When new commands are pushed the search address has to be updated to always + // start the search from the oldest available. + // + ///////////////////////////////////////////////////////////////////////////// + + // Handle search addr. + always @ (posedge ACLK) begin + if (ARESET) begin + search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; + end else begin + if ( cmd_b_ready_i ) begin + // Collapse addr when data is popped. + search_addr_ptr <= collapsed_addr_ptr; + + end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin + // Skip non valid command. + search_addr_ptr <= search_addr_ptr - 1; + + end else if ( cmd_b_push ) begin + search_addr_ptr <= search_addr_ptr + 1; + + end + end + end + + // Check if searched command is valid and match ID (for existing response on MI side). + assign matching_id = ( M_AXI_BID_I == current_id ); + assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I; + assign use_match = found_match & S_AXI_BREADY; + + + ///////////////////////////////////////////////////////////////////////////// + // Track Used Commands: + // + // Actions that affect Valid Command: + // * When a new command is pushed + // => Shift valid vector one step + // * When a command is used + // => Clear corresponding valid bit + // + ///////////////////////////////////////////////////////////////////////////// + + // Valid command status is updated when a command is used or a new one is pushed. + assign write_valid_cmd = cmd_b_push | cmd_b_ready_i; + + // Update the used command valid bit. + always @ * + begin + updated_valid_cmd = valid_cmd; + updated_valid_cmd[search_addr_ptr] = ~use_match; + end + + // Shift valid vector when command is pushed. + always @ * + begin + if ( cmd_b_push ) begin + next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1}; + end else begin + next_valid_cmd = updated_valid_cmd; + end + end + + // Valid signals for next cycle. + always @ (posedge ACLK) begin + if (ARESET) begin + valid_cmd <= {C_FIFO_WIDTH{1'b0}}; + end else if ( write_valid_cmd ) begin + valid_cmd <= next_valid_cmd; + end + end + + // Detect oldest available command in Queue. + always @ * + begin + // Default to empty. + collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}}; + + for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin + if ( next_valid_cmd[index] ) begin + collapsed_addr_ptr = index; + end + end + end + + + ///////////////////////////////////////////////////////////////////////////// + // Pipe incoming data: + // + // The B channel is piped to improve timing and avoid impact in search + // mechanism due to late arriving signals. + // + ///////////////////////////////////////////////////////////////////////////// + + // Clock data. + always @ (posedge ACLK) begin + if (ARESET) begin + M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}}; + M_AXI_BRESP_I <= 2'b00; + M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}}; + M_AXI_BVALID_I <= 1'b0; + end else begin + if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin + M_AXI_BVALID_I <= 1'b0; + end + if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin + M_AXI_BID_I <= M_AXI_BID; + M_AXI_BRESP_I <= M_AXI_BRESP; + M_AXI_BUSER_I <= M_AXI_BUSER; + M_AXI_BVALID_I <= 1'b1; + end + end + end + + // Generate ready to get new transaction. + assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I; + + + ///////////////////////////////////////////////////////////////////////////// + // Inject Error: + // + // BRESP is modified according to command information. + // + ///////////////////////////////////////////////////////////////////////////// + + // Inject error in response. + always @ * + begin + if ( inject_error ) begin + S_AXI_BRESP = C_RESP_SLVERROR; + end else begin + S_AXI_BRESP = M_AXI_BRESP_I; + end + end + + // Handle interrupt generation. + always @ (posedge ACLK) begin + if (ARESET) begin + ERROR_TRIGGER <= 1'b0; + ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}}; + end else begin + if ( inject_error & cmd_b_ready_i ) begin + ERROR_TRIGGER <= 1'b1; + ERROR_TRANSACTION_ID <= M_AXI_BID_I; + end else begin + ERROR_TRIGGER <= 1'b0; + end + end + end + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Throttling: + // + // Response is passed forward when a matching entry has been found in queue. + // Both ready and valid are set when the command is completed. + // + ///////////////////////////////////////////////////////////////////////////// + + // Propagate masked valid. + assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match; + + // Return ready with push back. + assign M_AXI_BREADY_I = cmd_b_valid & use_match; + + // Command has been handled. + assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match; + assign cmd_b_ready = cmd_b_ready_i; + + + ///////////////////////////////////////////////////////////////////////////// + // Write Response Propagation: + // + // All information is simply forwarded on from MI- to SI-Side untouched. + // + ///////////////////////////////////////////////////////////////////////////// + + // 1:1 mapping. + assign S_AXI_BID = M_AXI_BID_I; + assign S_AXI_BUSER = M_AXI_BUSER_I; + + +endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v new file mode 100644 index 0000000..0c776b3 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v @@ -0,0 +1,310 @@ +// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// Filename: trace_buffer.v +// Description: Trace port buffer +//----------------------------------------------------------------------------- +// Structure: This section shows the hierarchical structure of +// pss_wrapper. +// +// --processing_system7 +// | +// --trace_buffer +//----------------------------------------------------------------------------- + + +module processing_system7_v5_5_trace_buffer # + ( + parameter integer FIFO_SIZE = 128, + parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0, + parameter integer C_DELAY_CLKS = 12 + ) + ( + input wire TRACE_CLK, + input wire RST, + input wire TRACE_VALID_IN, + input wire [3:0] TRACE_ATID_IN, + input wire [31:0] TRACE_DATA_IN, + output wire TRACE_VALID_OUT, + output wire [3:0] TRACE_ATID_OUT, + output wire [31:0] TRACE_DATA_OUT + ); + +//------------------------------------------------------------ +// Architecture section +//------------------------------------------------------------ + +// function called clogb2 that returns an integer which has the +// value of the ceiling of the log base 2. + +function integer clogb2 (input integer bit_depth); + integer i; + integer temp_log; + begin + temp_log = 0; + for(i=bit_depth; i > 0; i = i>>1) + clogb2 = temp_log; + temp_log=temp_log+1; + end +endfunction + +localparam DEPTH = clogb2(FIFO_SIZE-1); + +wire [31:0] reset_zeros; +reg [31:0] trace_pedge; // write enable for FIFO +reg [31:0] ti; +reg [31:0] tom; + +reg [3:0] atid; + +reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory + +reg [4:0] dly_ctr; +reg [DEPTH-1:0] fifo_wp; +reg [DEPTH-1:0] fifo_rp; + +reg fifo_re; +wire fifo_empty; +wire fifo_full; +reg fifo_full_reg; + +assign reset_zeros = 32'h0; + + +// Pipeline Stage for Traceport ATID ports + always @(posedge TRACE_CLK) begin + // process pedge_ti + // rising clock edge + if((RST == 1'b1)) begin + atid <= reset_zeros; + end + else begin + atid <= TRACE_ATID_IN; + end + end + + assign TRACE_ATID_OUT = atid; + + ///////////////////////////////////////////// + // Generate FIFO data based on TRACE_VALID_IN + ///////////////////////////////////////////// + generate + if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector + ///////////////////////////////////////////// + + // memory update process + // Update memory when positive edge detected and FIFO not full + always @(posedge TRACE_CLK) begin + if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin + trace_fifo[fifo_wp] <= TRACE_DATA_IN; + end + end + + // fifo write pointer + always @(posedge TRACE_CLK) begin + // process + if(RST == 1'b1) begin + fifo_wp <= {DEPTH{1'b0}}; + end + else if(TRACE_VALID_IN ) begin + if(fifo_wp == (FIFO_SIZE - 1)) begin + if (fifo_empty) begin + fifo_wp <= {DEPTH{1'b0}}; + end + end + else begin + fifo_wp <= fifo_wp + 1; + end + end + end + + + ///////////////////////////////////////////// + // Generate FIFO data based on data edge + ///////////////////////////////////////////// + end else begin : gen_data_edge_detector + ///////////////////////////////////////////// + + + // purpose: check for pos edge on any trace input + always @(posedge TRACE_CLK) begin + // process pedge_ti + // rising clock edge + if((RST == 1'b1)) begin + ti <= reset_zeros; + trace_pedge <= reset_zeros; + end + else begin + ti <= TRACE_DATA_IN; + trace_pedge <= (~ti & TRACE_DATA_IN); + //trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti; + // posedge only + end + end + + // memory update process + // Update memory when positive edge detected and FIFO not full + always @(posedge TRACE_CLK) begin + if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin + trace_fifo[fifo_wp] <= trace_pedge; + end + end + + // fifo write pointer + always @(posedge TRACE_CLK) begin + // process + if(RST == 1'b1) begin + fifo_wp <= {DEPTH{1'b0}}; + end + else if(|(trace_pedge) == 1'b1) begin + if(fifo_wp == (FIFO_SIZE - 1)) begin + if (fifo_empty) begin + fifo_wp <= {DEPTH{1'b0}}; + end + end + else begin + fifo_wp <= fifo_wp + 1; + end + end + end + + + end + endgenerate + + + always @(posedge TRACE_CLK) begin + tom <= trace_fifo[fifo_rp] ; + end + + +// // fifo write pointer +// always @(posedge TRACE_CLK) begin +// // process +// if(RST == 1'b1) begin +// fifo_wp <= {DEPTH{1'b0}}; +// end +// else if(|(trace_pedge) == 1'b1) begin +// if(fifo_wp == (FIFO_SIZE - 1)) begin +// fifo_wp <= {DEPTH{1'b0}}; +// end +// else begin +// fifo_wp <= fifo_wp + 1; +// end +// end +// end + + + // fifo read pointer update + always @(posedge TRACE_CLK) begin + if(RST == 1'b1) begin + fifo_rp <= {DEPTH{1'b0}}; + fifo_re <= 1'b0; + end + else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin + fifo_re <= 1'b1; + if(fifo_rp == (FIFO_SIZE - 1)) begin + fifo_rp <= {DEPTH{1'b0}}; + end + else begin + fifo_rp <= fifo_rp + 1; + end + end + else begin + fifo_re <= 1'b0; + end + end + + // delay counter update + always @(posedge TRACE_CLK) begin + if(RST == 1'b1) begin + dly_ctr <= 5'h0; + end + else if (fifo_re == 1'b1) begin + dly_ctr <= C_DELAY_CLKS-1; + end + else if(dly_ctr != 5'h0) begin + dly_ctr <= dly_ctr - 1; + end + end + + // fifo empty update + assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0; + + // fifo full update + assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0; + + always @(posedge TRACE_CLK) begin + if(RST == 1'b1) begin + fifo_full_reg <= 1'b0; + end + else if (fifo_empty) begin + fifo_full_reg <= 1'b0; + end else begin + fifo_full_reg <= fifo_full; + end + end + +// always @(posedge TRACE_CLK) begin +// if(RST == 1'b1) begin +// fifo_full_reg <= 1'b0; +// end +// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin +// fifo_full_reg <= 1'b1; +// end +// else begin +// fifo_full_reg <= 1'b0; +// end +// end +// + assign TRACE_DATA_OUT = tom; + + assign TRACE_VALID_OUT = fifo_re; + + + + +endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v new file mode 100644 index 0000000..8b19a70 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v @@ -0,0 +1,244 @@ +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Write Channel for ATC +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// w_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + + +module processing_system7_v5_5_w_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_DATA_WIDTH = 64, + // Width of all DATA signals on SI and MI side of checker. + // Range: 64. + parameter integer C_AXI_WUSER_WIDTH = 1 + // Width of AWUSER signals. + // Range: >= 1. + ) + ( + // Global Signals + input wire ARESET, + input wire ACLK, + + // Command Interface (In) + input wire cmd_w_valid, + input wire cmd_w_check, + input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, + output wire cmd_w_ready, + + // Command Interface (Out) + output wire cmd_b_push, + output wire cmd_b_error, + output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id, + input wire cmd_b_full, + + // Slave Interface Write Port + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID, + input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, + input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, + input wire S_AXI_WLAST, + input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, + input wire S_AXI_WVALID, + output wire S_AXI_WREADY, + + // Master Interface Write Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, + output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, + output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, + output wire M_AXI_WLAST, + output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, + output wire M_AXI_WVALID, + input wire M_AXI_WREADY + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Detecttion. + wire any_strb_deasserted; + wire incoming_strb_issue; + reg first_word; + reg strb_issue; + + // Data flow. + wire data_pop; + wire cmd_b_push_blocked; + reg cmd_b_push_i; + + + ///////////////////////////////////////////////////////////////////////////// + // Detect error: + // + // Detect and accumulate error when a transaction shall be scanned for + // potential issues. + // Accumulation of error is restarted for each ne transaction. + // + ///////////////////////////////////////////////////////////////////////////// + + // Check stobe information + assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} ); + assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted; + + // Keep track of first word in a transaction. + always @ (posedge ACLK) begin + if (ARESET) begin + first_word <= 1'b1; + end else if ( data_pop ) begin + first_word <= S_AXI_WLAST; + end + end + + // Keep track of error status. + always @ (posedge ACLK) begin + if (ARESET) begin + strb_issue <= 1'b0; + cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}}; + end else if ( data_pop ) begin + if ( first_word ) begin + strb_issue <= incoming_strb_issue; + end else begin + strb_issue <= incoming_strb_issue | strb_issue; + end + cmd_b_id <= cmd_w_id; + end + end + + assign cmd_b_error = strb_issue; + + + ///////////////////////////////////////////////////////////////////////////// + // Control command queue to B: + // + // Push command to B queue when all data for the transaction has flowed + // through. + // Delay pipelined command until there is room in the Queue. + // + ///////////////////////////////////////////////////////////////////////////// + + // Detect when data is popped. + assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; + + // Push command when last word in transfered (pipelined). + always @ (posedge ACLK) begin + if (ARESET) begin + cmd_b_push_i <= 1'b0; + end else begin + cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked; + end + end + + // Detect if pipelined push is blocked. + assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full; + + // Assign output. + assign cmd_b_push = cmd_b_push_i & ~cmd_b_full; + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Throttling: + // + // Stall commands if FIFO is full or there is no valid command information + // from AW. + // + ///////////////////////////////////////////////////////////////////////////// + + // Propagate masked valid. + assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; + + // Return ready with push back. + assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; + + // End of burst. + assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST; + + + ///////////////////////////////////////////////////////////////////////////// + // Write propagation: + // + // All information is simply forwarded on from the SI- to MI-Side untouched. + // + ///////////////////////////////////////////////////////////////////////////// + + // 1:1 mapping. + assign M_AXI_WID = S_AXI_WID; + assign M_AXI_WDATA = S_AXI_WDATA; + assign M_AXI_WSTRB = S_AXI_WSTRB; + assign M_AXI_WLAST = S_AXI_WLAST; + assign M_AXI_WUSER = S_AXI_WUSER; + + +endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_local_params.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_local_params.v new file mode 100644 index 0000000..4a72e86 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_local_params.v @@ -0,0 +1,244 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_local_params.v + * + * Date : 2012-11 + * + * Description : Parameters used in Zynq VIP + * + *****************************************************************************/ + + +/* local */ +parameter m_axi_gp0_baseaddr = 32'h4000_0000; +parameter m_axi_gp1_baseaddr = 32'h8000_0000; +parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF; +parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF; + +parameter addr_width = 32; // maximum address width +parameter data_width = 32; // maximum data width. +parameter max_chars = 128; // max characters for file name +parameter mem_width = data_width/8; /// memory width in bytes +parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted +parameter int_width = 32; //integre width + +/* for internal read/write APIs used for data transfers */ +parameter max_burst_len = 16; /// maximum brst length on axi +parameter max_data_width = 64; // maximum data width for internal AXI bursts +parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts +parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer +parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts + +parameter max_registers = 32; +parameter max_regs_width = clogb2(max_registers); + +parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11; + +/* Interrupt bits supported */ +parameter irq_width = 16; + +/* GP Master0 & Master1 address decode */ +parameter GP_M0 = 2'b01; +parameter GP_M1 = 2'b10; + +parameter ALL_RANDOM= 2'b00; +parameter ALL_ZEROS = 2'b01; +parameter ALL_ONES = 2'b10; + +parameter ddr_start_addr = 32'h0008_0000; +parameter ddr_end_addr = 32'h7FFF_FFFF; + +parameter ocm_start_addr = 32'h0000_0000; +parameter ocm_end_addr = 32'h0003_FFFF; +parameter high_ocm_start_addr = 32'hFFFC_0000; +parameter high_ocm_end_addr = 32'hFFFF_FFFF; +parameter ocm_low_addr = 32'hFFFF_0000; + +parameter reg_start_addr = 32'hE000_0000; +parameter reg_end_addr = 32'hF8F0_2F80; + + +/* for Master port APIs and AXI protocol related signal widths*/ +parameter axi_burst_len = 16; +parameter axi_len_width = clogb2(axi_burst_len); +parameter axi_size_width = 3; +parameter axi_brst_type_width = 2; +parameter axi_lock_width = 2; +parameter axi_cache_width = 4; +parameter axi_prot_width = 3; +parameter axi_rsp_width = 2; +parameter axi_mgp_data_width = 32; +parameter axi_mgp_id_width = 12; +parameter axi_mgp_outstanding = 8; +parameter axi_mgp_wr_id = 12'hC00; +parameter axi_mgp_rd_id = 12'hC0C; +parameter axi_mgp0_name = "M_AXI_GP0"; +parameter axi_mgp1_name = "M_AXI_GP1"; +parameter axi_qos_width = 4; +parameter max_transfer_bytes = 256; // For Master APIs. +parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs. + + +/* for GP slave ports*/ +parameter axi_sgp_data_width = 32; +parameter axi_sgp_id_width = 6; +parameter axi_sgp_rd_outstanding = 8; +parameter axi_sgp_wr_outstanding = 8; +parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding; +parameter axi_sgp0_name = "S_AXI_GP0"; +parameter axi_sgp1_name = "S_AXI_GP1"; + +/* for ACP slave ports*/ +parameter axi_acp_data_width = 64; +parameter axi_acp_id_width = 3; +parameter axi_acp_rd_outstanding = 7; +parameter axi_acp_wr_outstanding = 3; +parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding; +parameter axi_acp_name = "S_AXI_ACP"; + +/* for HP slave ports*/ +parameter axi_hp_id_width = 6; +parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT .. +parameter axi_hp0_name = "S_AXI_HP0"; +parameter axi_hp1_name = "S_AXI_HP1"; +parameter axi_hp2_name = "S_AXI_HP2"; +parameter axi_hp3_name = "S_AXI_HP3"; + + +parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported +parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported + +/* AXI transfer types */ +parameter AXI_FIXED = 2'b00; +parameter AXI_INCR = 2'b01; +parameter AXI_WRAP = 2'b10; + +/* Exclusive Access */ +parameter AXI_NRML = 2'b00; +parameter AXI_EXCL = 2'b01; +parameter AXI_LOCK = 2'b10; + +/* AXI Response types */ +parameter AXI_OK = 2'b00; +parameter AXI_EXCL_OK = 2'b01; +parameter AXI_SLV_ERR = 2'b10; +parameter AXI_DEC_ERR = 2'b11; + +function automatic integer clogb2; + input [31:0] value; + begin + value = value - 1; + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin + value = value >> 1; + end + end +endfunction + +/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */ + /* WR FIFO data */ + // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1); + // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1); + // parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1); + // parameter wr_bytes_lsb = 0; + // parameter wr_bytes_msb = max_burst_bytes_width; + // parameter wr_addr_lsb = wr_bytes_msb + 1; + // parameter wr_addr_msb = wr_addr_lsb + addr_width-1; + // parameter wr_data_lsb = wr_addr_msb + 1; + // parameter wr_data_msb = wr_data_lsb + max_burst_bits-1; + // parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1; + // parameter wr_qos_lsb = wr_data_msb + 1; + // `parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; + + /* WR AFI FIFO data */ + /* ID - 1071:1066 + Resp - 1065:1064 + data - 1063:40 + address - 39:8 + valid_bytes - 7:0 + */ + // parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1); + // parameter wr_afi_bytes_lsb = 0; + // parameter wr_afi_bytes_msb = max_burst_bytes_width; + // parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1; + // parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1; + // parameter wr_afi_data_lsb = wr_afi_addr_msb + 1; + // parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1; + // parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1; + // parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1; + // parameter wr_afi_ln_lsb = wr_afi_id_msb + 1; + // parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1; + // parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1; + // parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1; + + + parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes + parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes) + parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location + +/* for interconnect fifo models */ + parameter intr_max_outstanding = 8; + parameter intr_cnt_width = clogb2(intr_max_outstanding)+1; + parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1); + parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ; + + //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes + parameter rd_afi_bytes_lsb = 0; + parameter rd_afi_bytes_msb = max_burst_bytes_width; + parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1; + parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1; + parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1; + parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1; + parameter rd_afi_ln_lsb = rd_afi_id_msb + 1; + parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1; + parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1; + parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1; + parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1; + parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1; + parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1; + parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1; + parameter rd_afi_data_lsb = rd_afi_addr_msb + 1; + parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1; + + +/* Latency types */ + parameter BEST_CASE = 0; + parameter AVG_CASE = 1; + parameter WORST_CASE = 2; + parameter RANDOM_CASE = 3; + +/* Latency Parameters ACP */ + parameter acp_wr_min = 21; + parameter acp_wr_avg = 16; + parameter acp_wr_max = 27; + parameter acp_rd_min = 34; + parameter acp_rd_avg = 125; + parameter acp_rd_max = 130; + +/* Latency Parameters GP */ + parameter gp_wr_min = 21; + parameter gp_wr_avg = 16; + parameter gp_wr_max = 46; + parameter gp_rd_min = 38; + parameter gp_rd_avg = 125; + parameter gp_rd_max = 130; + +/* Latency Parameters HP */ + parameter afi_wr_min = 37; + parameter afi_wr_avg = 41; + parameter afi_wr_max = 42; + parameter afi_rd_min = 41; + parameter afi_rd_avg = 221; + parameter afi_rd_max = 229; + +/* ID VALID and INVALID */ + parameter secure_access_enabled = 0; + parameter id_invalid = 0; + parameter id_valid = 1; + +/* Display */ + parameter DISP_INFO = "*ZYNQ_VIP_INFO"; + parameter DISP_WARN = "*ZYNQ_VIP_WARNING"; + parameter DISP_ERR = "*ZYNQ_VIP_ERROR"; + parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO"; + + parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_reg_init.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_reg_init.v new file mode 100644 index 0000000..73bb4a7 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_reg_init.v @@ -0,0 +1,2924 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_reg_init.v + * + * Date : 2012-11 + * + * Description : Initialize register default values. + * + *****************************************************************************/ + +// Register default value info for chip pele_ps +// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 +// 54 modules, 2532 registers. + + +// ************************************************************ +// Module afi0 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi0__AFI_RDCHAN_CTRL, val_afi0__AFI_RDCHAN_CTRL); +set_reset_data( afi0__AFI_RDCHAN_ISSUINGCAP, val_afi0__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi0__AFI_RDQOS, val_afi0__AFI_RDQOS); +set_reset_data( afi0__AFI_RDDATAFIFO_LEVEL, val_afi0__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi0__AFI_RDDEBUG, val_afi0__AFI_RDDEBUG); +set_reset_data( afi0__AFI_WRCHAN_CTRL, val_afi0__AFI_WRCHAN_CTRL); +set_reset_data( afi0__AFI_WRCHAN_ISSUINGCAP, val_afi0__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi0__AFI_WRQOS, val_afi0__AFI_WRQOS); +set_reset_data( afi0__AFI_WRDATAFIFO_LEVEL, val_afi0__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi0__AFI_WRDEBUG, val_afi0__AFI_WRDEBUG); + +// ************************************************************ +// Module afi1 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi1__AFI_RDCHAN_CTRL, val_afi1__AFI_RDCHAN_CTRL); +set_reset_data( afi1__AFI_RDCHAN_ISSUINGCAP, val_afi1__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi1__AFI_RDQOS, val_afi1__AFI_RDQOS); +set_reset_data( afi1__AFI_RDDATAFIFO_LEVEL, val_afi1__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi1__AFI_RDDEBUG, val_afi1__AFI_RDDEBUG); +set_reset_data( afi1__AFI_WRCHAN_CTRL, val_afi1__AFI_WRCHAN_CTRL); +set_reset_data( afi1__AFI_WRCHAN_ISSUINGCAP, val_afi1__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi1__AFI_WRQOS, val_afi1__AFI_WRQOS); +set_reset_data( afi1__AFI_WRDATAFIFO_LEVEL, val_afi1__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi1__AFI_WRDEBUG, val_afi1__AFI_WRDEBUG); + +// ************************************************************ +// Module afi2 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi2__AFI_RDCHAN_CTRL, val_afi2__AFI_RDCHAN_CTRL); +set_reset_data( afi2__AFI_RDCHAN_ISSUINGCAP, val_afi2__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi2__AFI_RDQOS, val_afi2__AFI_RDQOS); +set_reset_data( afi2__AFI_RDDATAFIFO_LEVEL, val_afi2__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi2__AFI_RDDEBUG, val_afi2__AFI_RDDEBUG); +set_reset_data( afi2__AFI_WRCHAN_CTRL, val_afi2__AFI_WRCHAN_CTRL); +set_reset_data( afi2__AFI_WRCHAN_ISSUINGCAP, val_afi2__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi2__AFI_WRQOS, val_afi2__AFI_WRQOS); +set_reset_data( afi2__AFI_WRDATAFIFO_LEVEL, val_afi2__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi2__AFI_WRDEBUG, val_afi2__AFI_WRDEBUG); + +// ************************************************************ +// Module afi3 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi3__AFI_RDCHAN_CTRL, val_afi3__AFI_RDCHAN_CTRL); +set_reset_data( afi3__AFI_RDCHAN_ISSUINGCAP, val_afi3__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi3__AFI_RDQOS, val_afi3__AFI_RDQOS); +set_reset_data( afi3__AFI_RDDATAFIFO_LEVEL, val_afi3__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi3__AFI_RDDEBUG, val_afi3__AFI_RDDEBUG); +set_reset_data( afi3__AFI_WRCHAN_CTRL, val_afi3__AFI_WRCHAN_CTRL); +set_reset_data( afi3__AFI_WRCHAN_ISSUINGCAP, val_afi3__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi3__AFI_WRQOS, val_afi3__AFI_WRQOS); +set_reset_data( afi3__AFI_WRDATAFIFO_LEVEL, val_afi3__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi3__AFI_WRDEBUG, val_afi3__AFI_WRDEBUG); + +// ************************************************************ +// Module can0 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( can0__SRR, val_can0__SRR); +set_reset_data( can0__MSR, val_can0__MSR); +set_reset_data( can0__BRPR, val_can0__BRPR); +set_reset_data( can0__BTR, val_can0__BTR); +set_reset_data( can0__ECR, val_can0__ECR); +set_reset_data( can0__ESR, val_can0__ESR); +set_reset_data( can0__SR, val_can0__SR); +set_reset_data( can0__ISR, val_can0__ISR); +set_reset_data( can0__IER, val_can0__IER); +set_reset_data( can0__ICR, val_can0__ICR); +set_reset_data( can0__TCR, val_can0__TCR); +set_reset_data( can0__WIR, val_can0__WIR); +set_reset_data( can0__TXFIFO_ID, val_can0__TXFIFO_ID); +set_reset_data( can0__TXFIFO_DLC, val_can0__TXFIFO_DLC); +set_reset_data( can0__TXFIFO_DATA1, val_can0__TXFIFO_DATA1); +set_reset_data( can0__TXFIFO_DATA2, val_can0__TXFIFO_DATA2); +set_reset_data( can0__TXHPB_ID, val_can0__TXHPB_ID); +set_reset_data( can0__TXHPB_DLC, val_can0__TXHPB_DLC); +set_reset_data( can0__TXHPB_DATA1, val_can0__TXHPB_DATA1); +set_reset_data( can0__TXHPB_DATA2, val_can0__TXHPB_DATA2); +set_reset_data( can0__RXFIFO_ID, val_can0__RXFIFO_ID); +set_reset_data( can0__RXFIFO_DLC, val_can0__RXFIFO_DLC); +set_reset_data( can0__RXFIFO_DATA1, val_can0__RXFIFO_DATA1); +set_reset_data( can0__RXFIFO_DATA2, val_can0__RXFIFO_DATA2); +set_reset_data( can0__AFR, val_can0__AFR); +set_reset_data( can0__AFMR1, val_can0__AFMR1); +set_reset_data( can0__AFIR1, val_can0__AFIR1); +set_reset_data( can0__AFMR2, val_can0__AFMR2); +set_reset_data( can0__AFIR2, val_can0__AFIR2); +set_reset_data( can0__AFMR3, val_can0__AFMR3); +set_reset_data( can0__AFIR3, val_can0__AFIR3); +set_reset_data( can0__AFMR4, val_can0__AFMR4); +set_reset_data( can0__AFIR4, val_can0__AFIR4); + +// ************************************************************ +// Module can1 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( can1__SRR, val_can1__SRR); +set_reset_data( can1__MSR, val_can1__MSR); +set_reset_data( can1__BRPR, val_can1__BRPR); +set_reset_data( can1__BTR, val_can1__BTR); +set_reset_data( can1__ECR, val_can1__ECR); +set_reset_data( can1__ESR, val_can1__ESR); +set_reset_data( can1__SR, val_can1__SR); +set_reset_data( can1__ISR, val_can1__ISR); +set_reset_data( can1__IER, val_can1__IER); +set_reset_data( can1__ICR, val_can1__ICR); +set_reset_data( can1__TCR, val_can1__TCR); +set_reset_data( can1__WIR, val_can1__WIR); +set_reset_data( can1__TXFIFO_ID, val_can1__TXFIFO_ID); +set_reset_data( can1__TXFIFO_DLC, val_can1__TXFIFO_DLC); +set_reset_data( can1__TXFIFO_DATA1, val_can1__TXFIFO_DATA1); +set_reset_data( can1__TXFIFO_DATA2, val_can1__TXFIFO_DATA2); +set_reset_data( can1__TXHPB_ID, val_can1__TXHPB_ID); +set_reset_data( can1__TXHPB_DLC, val_can1__TXHPB_DLC); +set_reset_data( can1__TXHPB_DATA1, val_can1__TXHPB_DATA1); +set_reset_data( can1__TXHPB_DATA2, val_can1__TXHPB_DATA2); +set_reset_data( can1__RXFIFO_ID, val_can1__RXFIFO_ID); +set_reset_data( can1__RXFIFO_DLC, val_can1__RXFIFO_DLC); +set_reset_data( can1__RXFIFO_DATA1, val_can1__RXFIFO_DATA1); +set_reset_data( can1__RXFIFO_DATA2, val_can1__RXFIFO_DATA2); +set_reset_data( can1__AFR, val_can1__AFR); +set_reset_data( can1__AFMR1, val_can1__AFMR1); +set_reset_data( can1__AFIR1, val_can1__AFIR1); +set_reset_data( can1__AFMR2, val_can1__AFMR2); +set_reset_data( can1__AFIR2, val_can1__AFIR2); +set_reset_data( can1__AFMR3, val_can1__AFMR3); +set_reset_data( can1__AFIR3, val_can1__AFIR3); +set_reset_data( can1__AFMR4, val_can1__AFMR4); +set_reset_data( can1__AFIR4, val_can1__AFIR4); + +// ************************************************************ +// Module ddrc ddrc +// doc version: 1.25 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ddrc__ddrc_ctrl, val_ddrc__ddrc_ctrl); +set_reset_data( ddrc__Two_rank_cfg, val_ddrc__Two_rank_cfg); +set_reset_data( ddrc__HPR_reg, val_ddrc__HPR_reg); +set_reset_data( ddrc__LPR_reg, val_ddrc__LPR_reg); +set_reset_data( ddrc__WR_reg, val_ddrc__WR_reg); +set_reset_data( ddrc__DRAM_param_reg0, val_ddrc__DRAM_param_reg0); +set_reset_data( ddrc__DRAM_param_reg1, val_ddrc__DRAM_param_reg1); +set_reset_data( ddrc__DRAM_param_reg2, val_ddrc__DRAM_param_reg2); +set_reset_data( ddrc__DRAM_param_reg3, val_ddrc__DRAM_param_reg3); +set_reset_data( ddrc__DRAM_param_reg4, val_ddrc__DRAM_param_reg4); +set_reset_data( ddrc__DRAM_init_param, val_ddrc__DRAM_init_param); +set_reset_data( ddrc__DRAM_EMR_reg, val_ddrc__DRAM_EMR_reg); +set_reset_data( ddrc__DRAM_EMR_MR_reg, val_ddrc__DRAM_EMR_MR_reg); +set_reset_data( ddrc__DRAM_burst8_rdwr, val_ddrc__DRAM_burst8_rdwr); +set_reset_data( ddrc__DRAM_disable_DQ, val_ddrc__DRAM_disable_DQ); +set_reset_data( ddrc__DRAM_addr_map_bank, val_ddrc__DRAM_addr_map_bank); +set_reset_data( ddrc__DRAM_addr_map_col, val_ddrc__DRAM_addr_map_col); +set_reset_data( ddrc__DRAM_addr_map_row, val_ddrc__DRAM_addr_map_row); +set_reset_data( ddrc__DRAM_ODT_reg, val_ddrc__DRAM_ODT_reg); +set_reset_data( ddrc__phy_dbg_reg, val_ddrc__phy_dbg_reg); +set_reset_data( ddrc__phy_cmd_timeout_rddata_cpt, val_ddrc__phy_cmd_timeout_rddata_cpt); +set_reset_data( ddrc__mode_sts_reg, val_ddrc__mode_sts_reg); +set_reset_data( ddrc__DLL_calib, val_ddrc__DLL_calib); +set_reset_data( ddrc__ODT_delay_hold, val_ddrc__ODT_delay_hold); +set_reset_data( ddrc__ctrl_reg1, val_ddrc__ctrl_reg1); +set_reset_data( ddrc__ctrl_reg2, val_ddrc__ctrl_reg2); +set_reset_data( ddrc__ctrl_reg3, val_ddrc__ctrl_reg3); +set_reset_data( ddrc__ctrl_reg4, val_ddrc__ctrl_reg4); +set_reset_data( ddrc__ctrl_reg5, val_ddrc__ctrl_reg5); +set_reset_data( ddrc__ctrl_reg6, val_ddrc__ctrl_reg6); +set_reset_data( ddrc__CHE_REFRESH_TIMER01, val_ddrc__CHE_REFRESH_TIMER01); +set_reset_data( ddrc__CHE_T_ZQ, val_ddrc__CHE_T_ZQ); +set_reset_data( ddrc__CHE_T_ZQ_Short_Interval_Reg, val_ddrc__CHE_T_ZQ_Short_Interval_Reg); +set_reset_data( ddrc__deep_pwrdwn_reg, val_ddrc__deep_pwrdwn_reg); +set_reset_data( ddrc__reg_2c, val_ddrc__reg_2c); +set_reset_data( ddrc__reg_2d, val_ddrc__reg_2d); +set_reset_data( ddrc__dfi_timing, val_ddrc__dfi_timing); +set_reset_data( ddrc__refresh_timer_2, val_ddrc__refresh_timer_2); +set_reset_data( ddrc__nc_timing, val_ddrc__nc_timing); +set_reset_data( ddrc__CHE_ECC_CONTROL_REG_OFFSET, val_ddrc__CHE_ECC_CONTROL_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET); +set_reset_data( ddrc__CHE_ECC_STATS_REG_OFFSET, val_ddrc__CHE_ECC_STATS_REG_OFFSET); +set_reset_data( ddrc__ECC_scrub, val_ddrc__ECC_scrub); +set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET); +set_reset_data( ddrc__phy_rcvr_enable, val_ddrc__phy_rcvr_enable); +set_reset_data( ddrc__PHY_Config0, val_ddrc__PHY_Config0); +set_reset_data( ddrc__PHY_Config1, val_ddrc__PHY_Config1); +set_reset_data( ddrc__PHY_Config2, val_ddrc__PHY_Config2); +set_reset_data( ddrc__PHY_Config3, val_ddrc__PHY_Config3); +set_reset_data( ddrc__phy_init_ratio0, val_ddrc__phy_init_ratio0); +set_reset_data( ddrc__phy_init_ratio1, val_ddrc__phy_init_ratio1); +set_reset_data( ddrc__phy_init_ratio2, val_ddrc__phy_init_ratio2); +set_reset_data( ddrc__phy_init_ratio3, val_ddrc__phy_init_ratio3); +set_reset_data( ddrc__phy_rd_dqs_cfg0, val_ddrc__phy_rd_dqs_cfg0); +set_reset_data( ddrc__phy_rd_dqs_cfg1, val_ddrc__phy_rd_dqs_cfg1); +set_reset_data( ddrc__phy_rd_dqs_cfg2, val_ddrc__phy_rd_dqs_cfg2); +set_reset_data( ddrc__phy_rd_dqs_cfg3, val_ddrc__phy_rd_dqs_cfg3); +set_reset_data( ddrc__phy_wr_dqs_cfg0, val_ddrc__phy_wr_dqs_cfg0); +set_reset_data( ddrc__phy_wr_dqs_cfg1, val_ddrc__phy_wr_dqs_cfg1); +set_reset_data( ddrc__phy_wr_dqs_cfg2, val_ddrc__phy_wr_dqs_cfg2); +set_reset_data( ddrc__phy_wr_dqs_cfg3, val_ddrc__phy_wr_dqs_cfg3); +set_reset_data( ddrc__phy_we_cfg0, val_ddrc__phy_we_cfg0); +set_reset_data( ddrc__phy_we_cfg1, val_ddrc__phy_we_cfg1); +set_reset_data( ddrc__phy_we_cfg2, val_ddrc__phy_we_cfg2); +set_reset_data( ddrc__phy_we_cfg3, val_ddrc__phy_we_cfg3); +set_reset_data( ddrc__wr_data_slv0, val_ddrc__wr_data_slv0); +set_reset_data( ddrc__wr_data_slv1, val_ddrc__wr_data_slv1); +set_reset_data( ddrc__wr_data_slv2, val_ddrc__wr_data_slv2); +set_reset_data( ddrc__wr_data_slv3, val_ddrc__wr_data_slv3); +set_reset_data( ddrc__reg_64, val_ddrc__reg_64); +set_reset_data( ddrc__reg_65, val_ddrc__reg_65); +set_reset_data( ddrc__reg69_6a0, val_ddrc__reg69_6a0); +set_reset_data( ddrc__reg69_6a1, val_ddrc__reg69_6a1); +set_reset_data( ddrc__reg6c_6d2, val_ddrc__reg6c_6d2); +set_reset_data( ddrc__reg6c_6d3, val_ddrc__reg6c_6d3); +set_reset_data( ddrc__reg6e_710, val_ddrc__reg6e_710); +set_reset_data( ddrc__reg6e_711, val_ddrc__reg6e_711); +set_reset_data( ddrc__reg6e_712, val_ddrc__reg6e_712); +set_reset_data( ddrc__reg6e_713, val_ddrc__reg6e_713); +set_reset_data( ddrc__phy_dll_sts0, val_ddrc__phy_dll_sts0); +set_reset_data( ddrc__phy_dll_sts1, val_ddrc__phy_dll_sts1); +set_reset_data( ddrc__phy_dll_sts2, val_ddrc__phy_dll_sts2); +set_reset_data( ddrc__phy_dll_sts3, val_ddrc__phy_dll_sts3); +set_reset_data( ddrc__dll_lock_sts, val_ddrc__dll_lock_sts); +set_reset_data( ddrc__phy_ctrl_sts, val_ddrc__phy_ctrl_sts); +set_reset_data( ddrc__phy_ctrl_sts_reg2, val_ddrc__phy_ctrl_sts_reg2); +set_reset_data( ddrc__axi_id, val_ddrc__axi_id); +set_reset_data( ddrc__page_mask, val_ddrc__page_mask); +set_reset_data( ddrc__axi_priority_wr_port0, val_ddrc__axi_priority_wr_port0); +set_reset_data( ddrc__axi_priority_wr_port1, val_ddrc__axi_priority_wr_port1); +set_reset_data( ddrc__axi_priority_wr_port2, val_ddrc__axi_priority_wr_port2); +set_reset_data( ddrc__axi_priority_wr_port3, val_ddrc__axi_priority_wr_port3); +set_reset_data( ddrc__axi_priority_rd_port0, val_ddrc__axi_priority_rd_port0); +set_reset_data( ddrc__axi_priority_rd_port1, val_ddrc__axi_priority_rd_port1); +set_reset_data( ddrc__axi_priority_rd_port2, val_ddrc__axi_priority_rd_port2); +set_reset_data( ddrc__axi_priority_rd_port3, val_ddrc__axi_priority_rd_port3); +set_reset_data( ddrc__AHB_priority_cfg0, val_ddrc__AHB_priority_cfg0); +set_reset_data( ddrc__AHB_priority_cfg1, val_ddrc__AHB_priority_cfg1); +set_reset_data( ddrc__AHB_priority_cfg2, val_ddrc__AHB_priority_cfg2); +set_reset_data( ddrc__AHB_priority_cfg3, val_ddrc__AHB_priority_cfg3); +set_reset_data( ddrc__perf_mon0, val_ddrc__perf_mon0); +set_reset_data( ddrc__perf_mon1, val_ddrc__perf_mon1); +set_reset_data( ddrc__perf_mon2, val_ddrc__perf_mon2); +set_reset_data( ddrc__perf_mon3, val_ddrc__perf_mon3); +set_reset_data( ddrc__perf_mon20, val_ddrc__perf_mon20); +set_reset_data( ddrc__perf_mon21, val_ddrc__perf_mon21); +set_reset_data( ddrc__perf_mon22, val_ddrc__perf_mon22); +set_reset_data( ddrc__perf_mon23, val_ddrc__perf_mon23); +set_reset_data( ddrc__perf_mon30, val_ddrc__perf_mon30); +set_reset_data( ddrc__perf_mon31, val_ddrc__perf_mon31); +set_reset_data( ddrc__perf_mon32, val_ddrc__perf_mon32); +set_reset_data( ddrc__perf_mon33, val_ddrc__perf_mon33); +set_reset_data( ddrc__trusted_mem_cfg, val_ddrc__trusted_mem_cfg); +set_reset_data( ddrc__excl_access_cfg0, val_ddrc__excl_access_cfg0); +set_reset_data( ddrc__excl_access_cfg1, val_ddrc__excl_access_cfg1); +set_reset_data( ddrc__excl_access_cfg2, val_ddrc__excl_access_cfg2); +set_reset_data( ddrc__excl_access_cfg3, val_ddrc__excl_access_cfg3); +set_reset_data( ddrc__mode_reg_read, val_ddrc__mode_reg_read); +set_reset_data( ddrc__lpddr_ctrl0, val_ddrc__lpddr_ctrl0); +set_reset_data( ddrc__lpddr_ctrl1, val_ddrc__lpddr_ctrl1); +set_reset_data( ddrc__lpddr_ctrl2, val_ddrc__lpddr_ctrl2); +set_reset_data( ddrc__lpddr_ctrl3, val_ddrc__lpddr_ctrl3); +set_reset_data( ddrc__phy_wr_lvl_fsm, val_ddrc__phy_wr_lvl_fsm); +set_reset_data( ddrc__phy_rd_lvl_fsm, val_ddrc__phy_rd_lvl_fsm); +set_reset_data( ddrc__phy_gate_lvl_fsm, val_ddrc__phy_gate_lvl_fsm); + +// ************************************************************ +// Module debug_axim axim +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_axim__GLOBAL_CTRL, val_debug_axim__GLOBAL_CTRL); +set_reset_data( debug_axim__GLOBAL_STATUS, val_debug_axim__GLOBAL_STATUS); +set_reset_data( debug_axim__FILTER_CTRL, val_debug_axim__FILTER_CTRL); +set_reset_data( debug_axim__TRIGGER_CTRL, val_debug_axim__TRIGGER_CTRL); +set_reset_data( debug_axim__TRIGGER_STATUS, val_debug_axim__TRIGGER_STATUS); +set_reset_data( debug_axim__PACKET_CTRL, val_debug_axim__PACKET_CTRL); +set_reset_data( debug_axim__TOUT_CTRL, val_debug_axim__TOUT_CTRL); +set_reset_data( debug_axim__TOUT_THRESH, val_debug_axim__TOUT_THRESH); +set_reset_data( debug_axim__FIFO_CURRENT, val_debug_axim__FIFO_CURRENT); +set_reset_data( debug_axim__FIFO_HYSTER, val_debug_axim__FIFO_HYSTER); +set_reset_data( debug_axim__SYNC_CURRENT, val_debug_axim__SYNC_CURRENT); +set_reset_data( debug_axim__SYNC_RELOAD, val_debug_axim__SYNC_RELOAD); +set_reset_data( debug_axim__TSTMP_CURRENT, val_debug_axim__TSTMP_CURRENT); +set_reset_data( debug_axim__ADDR0_MASK, val_debug_axim__ADDR0_MASK); +set_reset_data( debug_axim__ADDR0_LOWER, val_debug_axim__ADDR0_LOWER); +set_reset_data( debug_axim__ADDR0_UPPER, val_debug_axim__ADDR0_UPPER); +set_reset_data( debug_axim__ADDR0_MISC, val_debug_axim__ADDR0_MISC); +set_reset_data( debug_axim__ADDR1_MASK, val_debug_axim__ADDR1_MASK); +set_reset_data( debug_axim__ADDR1_LOWER, val_debug_axim__ADDR1_LOWER); +set_reset_data( debug_axim__ADDR1_UPPER, val_debug_axim__ADDR1_UPPER); +set_reset_data( debug_axim__ADDR1_MISC, val_debug_axim__ADDR1_MISC); +set_reset_data( debug_axim__ADDR2_MASK, val_debug_axim__ADDR2_MASK); +set_reset_data( debug_axim__ADDR2_LOWER, val_debug_axim__ADDR2_LOWER); +set_reset_data( debug_axim__ADDR2_UPPER, val_debug_axim__ADDR2_UPPER); +set_reset_data( debug_axim__ADDR2_MISC, val_debug_axim__ADDR2_MISC); +set_reset_data( debug_axim__ADDR3_MASK, val_debug_axim__ADDR3_MASK); +set_reset_data( debug_axim__ADDR3_LOWER, val_debug_axim__ADDR3_LOWER); +set_reset_data( debug_axim__ADDR3_UPPER, val_debug_axim__ADDR3_UPPER); +set_reset_data( debug_axim__ADDR3_MISC, val_debug_axim__ADDR3_MISC); +set_reset_data( debug_axim__ID0_MASK, val_debug_axim__ID0_MASK); +set_reset_data( debug_axim__ID0_LOWER, val_debug_axim__ID0_LOWER); +set_reset_data( debug_axim__ID0_UPPER, val_debug_axim__ID0_UPPER); +set_reset_data( debug_axim__ID0_MISC, val_debug_axim__ID0_MISC); +set_reset_data( debug_axim__ID1_MASK, val_debug_axim__ID1_MASK); +set_reset_data( debug_axim__ID1_LOWER, val_debug_axim__ID1_LOWER); +set_reset_data( debug_axim__ID1_UPPER, val_debug_axim__ID1_UPPER); +set_reset_data( debug_axim__ID1_MISC, val_debug_axim__ID1_MISC); +set_reset_data( debug_axim__ID2_MASK, val_debug_axim__ID2_MASK); +set_reset_data( debug_axim__ID2_LOWER, val_debug_axim__ID2_LOWER); +set_reset_data( debug_axim__ID2_UPPER, val_debug_axim__ID2_UPPER); +set_reset_data( debug_axim__ID2_MISC, val_debug_axim__ID2_MISC); +set_reset_data( debug_axim__ID3_MASK, val_debug_axim__ID3_MASK); +set_reset_data( debug_axim__ID3_LOWER, val_debug_axim__ID3_LOWER); +set_reset_data( debug_axim__ID3_UPPER, val_debug_axim__ID3_UPPER); +set_reset_data( debug_axim__ID3_MISC, val_debug_axim__ID3_MISC); +set_reset_data( debug_axim__AXI_SEL, val_debug_axim__AXI_SEL); +set_reset_data( debug_axim__IT_TRIGOUT, val_debug_axim__IT_TRIGOUT); +set_reset_data( debug_axim__IT_TRIGOUTACK, val_debug_axim__IT_TRIGOUTACK); +set_reset_data( debug_axim__IT_TRIGIN, val_debug_axim__IT_TRIGIN); +set_reset_data( debug_axim__IT_TRIGINACK, val_debug_axim__IT_TRIGINACK); +set_reset_data( debug_axim__IT_ATBDATA, val_debug_axim__IT_ATBDATA); +set_reset_data( debug_axim__IT_ATBSTATUS, val_debug_axim__IT_ATBSTATUS); +set_reset_data( debug_axim__IT_ATBCTRL1, val_debug_axim__IT_ATBCTRL1); +set_reset_data( debug_axim__IT_ATBCTRL0, val_debug_axim__IT_ATBCTRL0); +set_reset_data( debug_axim__IT_CTRL, val_debug_axim__IT_CTRL); +set_reset_data( debug_axim__CLAIM_SET, val_debug_axim__CLAIM_SET); +set_reset_data( debug_axim__CLAIM_CLEAR, val_debug_axim__CLAIM_CLEAR); +set_reset_data( debug_axim__LOCK_ACCESS, val_debug_axim__LOCK_ACCESS); +set_reset_data( debug_axim__LOCK_STATUS, val_debug_axim__LOCK_STATUS); +set_reset_data( debug_axim__AUTH_STATUS, val_debug_axim__AUTH_STATUS); +set_reset_data( debug_axim__DEV_ID, val_debug_axim__DEV_ID); +set_reset_data( debug_axim__DEV_TYPE, val_debug_axim__DEV_TYPE); +set_reset_data( debug_axim__PERIPHID4, val_debug_axim__PERIPHID4); +set_reset_data( debug_axim__PERIPHID5, val_debug_axim__PERIPHID5); +set_reset_data( debug_axim__PERIPHID6, val_debug_axim__PERIPHID6); +set_reset_data( debug_axim__PERIPHID7, val_debug_axim__PERIPHID7); +set_reset_data( debug_axim__PERIPHID0, val_debug_axim__PERIPHID0); +set_reset_data( debug_axim__PERIPHID1, val_debug_axim__PERIPHID1); +set_reset_data( debug_axim__PERIPHID2, val_debug_axim__PERIPHID2); +set_reset_data( debug_axim__PERIPHID3, val_debug_axim__PERIPHID3); +set_reset_data( debug_axim__COMPID0, val_debug_axim__COMPID0); +set_reset_data( debug_axim__COMPID1, val_debug_axim__COMPID1); +set_reset_data( debug_axim__COMPID2, val_debug_axim__COMPID2); +set_reset_data( debug_axim__COMPID3, val_debug_axim__COMPID3); + +// ************************************************************ +// Module debug_cpu_cti0 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_cti0__CTICONTROL, val_debug_cpu_cti0__CTICONTROL); +set_reset_data( debug_cpu_cti0__CTIINTACK, val_debug_cpu_cti0__CTIINTACK); +set_reset_data( debug_cpu_cti0__CTIAPPSET, val_debug_cpu_cti0__CTIAPPSET); +set_reset_data( debug_cpu_cti0__CTIAPPCLEAR, val_debug_cpu_cti0__CTIAPPCLEAR); +set_reset_data( debug_cpu_cti0__CTIAPPPULSE, val_debug_cpu_cti0__CTIAPPPULSE); +set_reset_data( debug_cpu_cti0__CTIINEN0, val_debug_cpu_cti0__CTIINEN0); +set_reset_data( debug_cpu_cti0__CTIINEN1, val_debug_cpu_cti0__CTIINEN1); +set_reset_data( debug_cpu_cti0__CTIINEN2, val_debug_cpu_cti0__CTIINEN2); +set_reset_data( debug_cpu_cti0__CTIINEN3, val_debug_cpu_cti0__CTIINEN3); +set_reset_data( debug_cpu_cti0__CTIINEN4, val_debug_cpu_cti0__CTIINEN4); +set_reset_data( debug_cpu_cti0__CTIINEN5, val_debug_cpu_cti0__CTIINEN5); +set_reset_data( debug_cpu_cti0__CTIINEN6, val_debug_cpu_cti0__CTIINEN6); +set_reset_data( debug_cpu_cti0__CTIINEN7, val_debug_cpu_cti0__CTIINEN7); +set_reset_data( debug_cpu_cti0__CTIOUTEN0, val_debug_cpu_cti0__CTIOUTEN0); +set_reset_data( debug_cpu_cti0__CTIOUTEN1, val_debug_cpu_cti0__CTIOUTEN1); +set_reset_data( debug_cpu_cti0__CTIOUTEN2, val_debug_cpu_cti0__CTIOUTEN2); +set_reset_data( debug_cpu_cti0__CTIOUTEN3, val_debug_cpu_cti0__CTIOUTEN3); +set_reset_data( debug_cpu_cti0__CTIOUTEN4, val_debug_cpu_cti0__CTIOUTEN4); +set_reset_data( debug_cpu_cti0__CTIOUTEN5, val_debug_cpu_cti0__CTIOUTEN5); +set_reset_data( debug_cpu_cti0__CTIOUTEN6, val_debug_cpu_cti0__CTIOUTEN6); +set_reset_data( debug_cpu_cti0__CTIOUTEN7, val_debug_cpu_cti0__CTIOUTEN7); +set_reset_data( debug_cpu_cti0__CTITRIGINSTATUS, val_debug_cpu_cti0__CTITRIGINSTATUS); +set_reset_data( debug_cpu_cti0__CTITRIGOUTSTATUS, val_debug_cpu_cti0__CTITRIGOUTSTATUS); +set_reset_data( debug_cpu_cti0__CTICHINSTATUS, val_debug_cpu_cti0__CTICHINSTATUS); +set_reset_data( debug_cpu_cti0__CTICHOUTSTATUS, val_debug_cpu_cti0__CTICHOUTSTATUS); +set_reset_data( debug_cpu_cti0__CTIGATE, val_debug_cpu_cti0__CTIGATE); +set_reset_data( debug_cpu_cti0__ASICCTL, val_debug_cpu_cti0__ASICCTL); +set_reset_data( debug_cpu_cti0__ITCHINACK, val_debug_cpu_cti0__ITCHINACK); +set_reset_data( debug_cpu_cti0__ITTRIGINACK, val_debug_cpu_cti0__ITTRIGINACK); +set_reset_data( debug_cpu_cti0__ITCHOUT, val_debug_cpu_cti0__ITCHOUT); +set_reset_data( debug_cpu_cti0__ITTRIGOUT, val_debug_cpu_cti0__ITTRIGOUT); +set_reset_data( debug_cpu_cti0__ITCHOUTACK, val_debug_cpu_cti0__ITCHOUTACK); +set_reset_data( debug_cpu_cti0__ITTRIGOUTACK, val_debug_cpu_cti0__ITTRIGOUTACK); +set_reset_data( debug_cpu_cti0__ITCHIN, val_debug_cpu_cti0__ITCHIN); +set_reset_data( debug_cpu_cti0__ITTRIGIN, val_debug_cpu_cti0__ITTRIGIN); +set_reset_data( debug_cpu_cti0__ITCTRL, val_debug_cpu_cti0__ITCTRL); +set_reset_data( debug_cpu_cti0__CTSR, val_debug_cpu_cti0__CTSR); +set_reset_data( debug_cpu_cti0__CTCR, val_debug_cpu_cti0__CTCR); +set_reset_data( debug_cpu_cti0__LAR, val_debug_cpu_cti0__LAR); +set_reset_data( debug_cpu_cti0__LSR, val_debug_cpu_cti0__LSR); +set_reset_data( debug_cpu_cti0__ASR, val_debug_cpu_cti0__ASR); +set_reset_data( debug_cpu_cti0__DEVID, val_debug_cpu_cti0__DEVID); +set_reset_data( debug_cpu_cti0__DTIR, val_debug_cpu_cti0__DTIR); +set_reset_data( debug_cpu_cti0__PERIPHID4, val_debug_cpu_cti0__PERIPHID4); +set_reset_data( debug_cpu_cti0__PERIPHID5, val_debug_cpu_cti0__PERIPHID5); +set_reset_data( debug_cpu_cti0__PERIPHID6, val_debug_cpu_cti0__PERIPHID6); +set_reset_data( debug_cpu_cti0__PERIPHID7, val_debug_cpu_cti0__PERIPHID7); +set_reset_data( debug_cpu_cti0__PERIPHID0, val_debug_cpu_cti0__PERIPHID0); +set_reset_data( debug_cpu_cti0__PERIPHID1, val_debug_cpu_cti0__PERIPHID1); +set_reset_data( debug_cpu_cti0__PERIPHID2, val_debug_cpu_cti0__PERIPHID2); +set_reset_data( debug_cpu_cti0__PERIPHID3, val_debug_cpu_cti0__PERIPHID3); +set_reset_data( debug_cpu_cti0__COMPID0, val_debug_cpu_cti0__COMPID0); +set_reset_data( debug_cpu_cti0__COMPID1, val_debug_cpu_cti0__COMPID1); +set_reset_data( debug_cpu_cti0__COMPID2, val_debug_cpu_cti0__COMPID2); +set_reset_data( debug_cpu_cti0__COMPID3, val_debug_cpu_cti0__COMPID3); + +// ************************************************************ +// Module debug_cpu_cti1 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_cti1__CTICONTROL, val_debug_cpu_cti1__CTICONTROL); +set_reset_data( debug_cpu_cti1__CTIINTACK, val_debug_cpu_cti1__CTIINTACK); +set_reset_data( debug_cpu_cti1__CTIAPPSET, val_debug_cpu_cti1__CTIAPPSET); +set_reset_data( debug_cpu_cti1__CTIAPPCLEAR, val_debug_cpu_cti1__CTIAPPCLEAR); +set_reset_data( debug_cpu_cti1__CTIAPPPULSE, val_debug_cpu_cti1__CTIAPPPULSE); +set_reset_data( debug_cpu_cti1__CTIINEN0, val_debug_cpu_cti1__CTIINEN0); +set_reset_data( debug_cpu_cti1__CTIINEN1, val_debug_cpu_cti1__CTIINEN1); +set_reset_data( debug_cpu_cti1__CTIINEN2, val_debug_cpu_cti1__CTIINEN2); +set_reset_data( debug_cpu_cti1__CTIINEN3, val_debug_cpu_cti1__CTIINEN3); +set_reset_data( debug_cpu_cti1__CTIINEN4, val_debug_cpu_cti1__CTIINEN4); +set_reset_data( debug_cpu_cti1__CTIINEN5, val_debug_cpu_cti1__CTIINEN5); +set_reset_data( debug_cpu_cti1__CTIINEN6, val_debug_cpu_cti1__CTIINEN6); +set_reset_data( debug_cpu_cti1__CTIINEN7, val_debug_cpu_cti1__CTIINEN7); +set_reset_data( debug_cpu_cti1__CTIOUTEN0, val_debug_cpu_cti1__CTIOUTEN0); +set_reset_data( debug_cpu_cti1__CTIOUTEN1, val_debug_cpu_cti1__CTIOUTEN1); +set_reset_data( debug_cpu_cti1__CTIOUTEN2, val_debug_cpu_cti1__CTIOUTEN2); +set_reset_data( debug_cpu_cti1__CTIOUTEN3, val_debug_cpu_cti1__CTIOUTEN3); +set_reset_data( debug_cpu_cti1__CTIOUTEN4, val_debug_cpu_cti1__CTIOUTEN4); +set_reset_data( debug_cpu_cti1__CTIOUTEN5, val_debug_cpu_cti1__CTIOUTEN5); +set_reset_data( debug_cpu_cti1__CTIOUTEN6, val_debug_cpu_cti1__CTIOUTEN6); +set_reset_data( debug_cpu_cti1__CTIOUTEN7, val_debug_cpu_cti1__CTIOUTEN7); +set_reset_data( debug_cpu_cti1__CTITRIGINSTATUS, val_debug_cpu_cti1__CTITRIGINSTATUS); +set_reset_data( debug_cpu_cti1__CTITRIGOUTSTATUS, val_debug_cpu_cti1__CTITRIGOUTSTATUS); +set_reset_data( debug_cpu_cti1__CTICHINSTATUS, val_debug_cpu_cti1__CTICHINSTATUS); +set_reset_data( debug_cpu_cti1__CTICHOUTSTATUS, val_debug_cpu_cti1__CTICHOUTSTATUS); +set_reset_data( debug_cpu_cti1__CTIGATE, val_debug_cpu_cti1__CTIGATE); +set_reset_data( debug_cpu_cti1__ASICCTL, val_debug_cpu_cti1__ASICCTL); +set_reset_data( debug_cpu_cti1__ITCHINACK, val_debug_cpu_cti1__ITCHINACK); +set_reset_data( debug_cpu_cti1__ITTRIGINACK, val_debug_cpu_cti1__ITTRIGINACK); +set_reset_data( debug_cpu_cti1__ITCHOUT, val_debug_cpu_cti1__ITCHOUT); +set_reset_data( debug_cpu_cti1__ITTRIGOUT, val_debug_cpu_cti1__ITTRIGOUT); +set_reset_data( debug_cpu_cti1__ITCHOUTACK, val_debug_cpu_cti1__ITCHOUTACK); +set_reset_data( debug_cpu_cti1__ITTRIGOUTACK, val_debug_cpu_cti1__ITTRIGOUTACK); +set_reset_data( debug_cpu_cti1__ITCHIN, val_debug_cpu_cti1__ITCHIN); +set_reset_data( debug_cpu_cti1__ITTRIGIN, val_debug_cpu_cti1__ITTRIGIN); +set_reset_data( debug_cpu_cti1__ITCTRL, val_debug_cpu_cti1__ITCTRL); +set_reset_data( debug_cpu_cti1__CTSR, val_debug_cpu_cti1__CTSR); +set_reset_data( debug_cpu_cti1__CTCR, val_debug_cpu_cti1__CTCR); +set_reset_data( debug_cpu_cti1__LAR, val_debug_cpu_cti1__LAR); +set_reset_data( debug_cpu_cti1__LSR, val_debug_cpu_cti1__LSR); +set_reset_data( debug_cpu_cti1__ASR, val_debug_cpu_cti1__ASR); +set_reset_data( debug_cpu_cti1__DEVID, val_debug_cpu_cti1__DEVID); +set_reset_data( debug_cpu_cti1__DTIR, val_debug_cpu_cti1__DTIR); +set_reset_data( debug_cpu_cti1__PERIPHID4, val_debug_cpu_cti1__PERIPHID4); +set_reset_data( debug_cpu_cti1__PERIPHID5, val_debug_cpu_cti1__PERIPHID5); +set_reset_data( debug_cpu_cti1__PERIPHID6, val_debug_cpu_cti1__PERIPHID6); +set_reset_data( debug_cpu_cti1__PERIPHID7, val_debug_cpu_cti1__PERIPHID7); +set_reset_data( debug_cpu_cti1__PERIPHID0, val_debug_cpu_cti1__PERIPHID0); +set_reset_data( debug_cpu_cti1__PERIPHID1, val_debug_cpu_cti1__PERIPHID1); +set_reset_data( debug_cpu_cti1__PERIPHID2, val_debug_cpu_cti1__PERIPHID2); +set_reset_data( debug_cpu_cti1__PERIPHID3, val_debug_cpu_cti1__PERIPHID3); +set_reset_data( debug_cpu_cti1__COMPID0, val_debug_cpu_cti1__COMPID0); +set_reset_data( debug_cpu_cti1__COMPID1, val_debug_cpu_cti1__COMPID1); +set_reset_data( debug_cpu_cti1__COMPID2, val_debug_cpu_cti1__COMPID2); +set_reset_data( debug_cpu_cti1__COMPID3, val_debug_cpu_cti1__COMPID3); + +// ************************************************************ +// Module debug_cpu_pmu0 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_pmu0__PMXEVCNTR0, val_debug_cpu_pmu0__PMXEVCNTR0); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR1, val_debug_cpu_pmu0__PMXEVCNTR1); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR2, val_debug_cpu_pmu0__PMXEVCNTR2); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR3, val_debug_cpu_pmu0__PMXEVCNTR3); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR4, val_debug_cpu_pmu0__PMXEVCNTR4); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR5, val_debug_cpu_pmu0__PMXEVCNTR5); +set_reset_data( debug_cpu_pmu0__PMCCNTR, val_debug_cpu_pmu0__PMCCNTR); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER0, val_debug_cpu_pmu0__PMXEVTYPER0); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER1, val_debug_cpu_pmu0__PMXEVTYPER1); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER2, val_debug_cpu_pmu0__PMXEVTYPER2); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER3, val_debug_cpu_pmu0__PMXEVTYPER3); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER4, val_debug_cpu_pmu0__PMXEVTYPER4); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER5, val_debug_cpu_pmu0__PMXEVTYPER5); +set_reset_data( debug_cpu_pmu0__PMCNTENSET, val_debug_cpu_pmu0__PMCNTENSET); +set_reset_data( debug_cpu_pmu0__PMCNTENCLR, val_debug_cpu_pmu0__PMCNTENCLR); +set_reset_data( debug_cpu_pmu0__PMINTENSET, val_debug_cpu_pmu0__PMINTENSET); +set_reset_data( debug_cpu_pmu0__PMINTENCLR, val_debug_cpu_pmu0__PMINTENCLR); +set_reset_data( debug_cpu_pmu0__PMOVSR, val_debug_cpu_pmu0__PMOVSR); +set_reset_data( debug_cpu_pmu0__PMSWINC, val_debug_cpu_pmu0__PMSWINC); +set_reset_data( debug_cpu_pmu0__PMCR, val_debug_cpu_pmu0__PMCR); +set_reset_data( debug_cpu_pmu0__PMUSERENR, val_debug_cpu_pmu0__PMUSERENR); + +// ************************************************************ +// Module debug_cpu_pmu1 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_pmu1__PMXEVCNTR0, val_debug_cpu_pmu1__PMXEVCNTR0); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR1, val_debug_cpu_pmu1__PMXEVCNTR1); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR2, val_debug_cpu_pmu1__PMXEVCNTR2); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR3, val_debug_cpu_pmu1__PMXEVCNTR3); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR4, val_debug_cpu_pmu1__PMXEVCNTR4); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR5, val_debug_cpu_pmu1__PMXEVCNTR5); +set_reset_data( debug_cpu_pmu1__PMCCNTR, val_debug_cpu_pmu1__PMCCNTR); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER0, val_debug_cpu_pmu1__PMXEVTYPER0); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER1, val_debug_cpu_pmu1__PMXEVTYPER1); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER2, val_debug_cpu_pmu1__PMXEVTYPER2); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER3, val_debug_cpu_pmu1__PMXEVTYPER3); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER4, val_debug_cpu_pmu1__PMXEVTYPER4); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER5, val_debug_cpu_pmu1__PMXEVTYPER5); +set_reset_data( debug_cpu_pmu1__PMCNTENSET, val_debug_cpu_pmu1__PMCNTENSET); +set_reset_data( debug_cpu_pmu1__PMCNTENCLR, val_debug_cpu_pmu1__PMCNTENCLR); +set_reset_data( debug_cpu_pmu1__PMINTENSET, val_debug_cpu_pmu1__PMINTENSET); +set_reset_data( debug_cpu_pmu1__PMINTENCLR, val_debug_cpu_pmu1__PMINTENCLR); +set_reset_data( debug_cpu_pmu1__PMOVSR, val_debug_cpu_pmu1__PMOVSR); +set_reset_data( debug_cpu_pmu1__PMSWINC, val_debug_cpu_pmu1__PMSWINC); +set_reset_data( debug_cpu_pmu1__PMCR, val_debug_cpu_pmu1__PMCR); +set_reset_data( debug_cpu_pmu1__PMUSERENR, val_debug_cpu_pmu1__PMUSERENR); + +// ************************************************************ +// Module debug_cpu_ptm0 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_ptm0__ETMCR, val_debug_cpu_ptm0__ETMCR); +set_reset_data( debug_cpu_ptm0__ETMCCR, val_debug_cpu_ptm0__ETMCCR); +set_reset_data( debug_cpu_ptm0__ETMTRIGGER, val_debug_cpu_ptm0__ETMTRIGGER); +set_reset_data( debug_cpu_ptm0__ETMSR, val_debug_cpu_ptm0__ETMSR); +set_reset_data( debug_cpu_ptm0__ETMSCR, val_debug_cpu_ptm0__ETMSCR); +set_reset_data( debug_cpu_ptm0__ETMTSSCR, val_debug_cpu_ptm0__ETMTSSCR); +set_reset_data( debug_cpu_ptm0__ETMTECR1, val_debug_cpu_ptm0__ETMTECR1); +set_reset_data( debug_cpu_ptm0__ETMACVR1, val_debug_cpu_ptm0__ETMACVR1); +set_reset_data( debug_cpu_ptm0__ETMACVR2, val_debug_cpu_ptm0__ETMACVR2); +set_reset_data( debug_cpu_ptm0__ETMACVR3, val_debug_cpu_ptm0__ETMACVR3); +set_reset_data( debug_cpu_ptm0__ETMACVR4, val_debug_cpu_ptm0__ETMACVR4); +set_reset_data( debug_cpu_ptm0__ETMACVR5, val_debug_cpu_ptm0__ETMACVR5); +set_reset_data( debug_cpu_ptm0__ETMACVR6, val_debug_cpu_ptm0__ETMACVR6); +set_reset_data( debug_cpu_ptm0__ETMACVR7, val_debug_cpu_ptm0__ETMACVR7); +set_reset_data( debug_cpu_ptm0__ETMACVR8, val_debug_cpu_ptm0__ETMACVR8); +set_reset_data( debug_cpu_ptm0__ETMACTR1, val_debug_cpu_ptm0__ETMACTR1); +set_reset_data( debug_cpu_ptm0__ETMACTR2, val_debug_cpu_ptm0__ETMACTR2); +set_reset_data( debug_cpu_ptm0__ETMACTR3, val_debug_cpu_ptm0__ETMACTR3); +set_reset_data( debug_cpu_ptm0__ETMACTR4, val_debug_cpu_ptm0__ETMACTR4); +set_reset_data( debug_cpu_ptm0__ETMACTR5, val_debug_cpu_ptm0__ETMACTR5); +set_reset_data( debug_cpu_ptm0__ETMACTR6, val_debug_cpu_ptm0__ETMACTR6); +set_reset_data( debug_cpu_ptm0__ETMACTR7, val_debug_cpu_ptm0__ETMACTR7); +set_reset_data( debug_cpu_ptm0__ETMACTR8, val_debug_cpu_ptm0__ETMACTR8); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR1, val_debug_cpu_ptm0__ETMCNTRLDVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR2, val_debug_cpu_ptm0__ETMCNTRLDVR2); +set_reset_data( debug_cpu_ptm0__ETMCNTENR1, val_debug_cpu_ptm0__ETMCNTENR1); +set_reset_data( debug_cpu_ptm0__ETMCNTENR2, val_debug_cpu_ptm0__ETMCNTENR2); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR1, val_debug_cpu_ptm0__ETMCNTRLDEVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR2, val_debug_cpu_ptm0__ETMCNTRLDEVR2); +set_reset_data( debug_cpu_ptm0__ETMCNTVR1, val_debug_cpu_ptm0__ETMCNTVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTVR2, val_debug_cpu_ptm0__ETMCNTVR2); +set_reset_data( debug_cpu_ptm0__ETMSQ12EVR, val_debug_cpu_ptm0__ETMSQ12EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ21EVR, val_debug_cpu_ptm0__ETMSQ21EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ23EVR, val_debug_cpu_ptm0__ETMSQ23EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ31EVR, val_debug_cpu_ptm0__ETMSQ31EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ32EVR, val_debug_cpu_ptm0__ETMSQ32EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ13EVR, val_debug_cpu_ptm0__ETMSQ13EVR); +set_reset_data( debug_cpu_ptm0__ETMSQR, val_debug_cpu_ptm0__ETMSQR); +set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR1, val_debug_cpu_ptm0__ETMEXTOUTEVR1); +set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR2, val_debug_cpu_ptm0__ETMEXTOUTEVR2); +set_reset_data( debug_cpu_ptm0__ETMCIDCVR1, val_debug_cpu_ptm0__ETMCIDCVR1); +set_reset_data( debug_cpu_ptm0__ETMCIDCMR, val_debug_cpu_ptm0__ETMCIDCMR); +set_reset_data( debug_cpu_ptm0__ETMSYNCFR, val_debug_cpu_ptm0__ETMSYNCFR); +set_reset_data( debug_cpu_ptm0__ETMIDR, val_debug_cpu_ptm0__ETMIDR); +set_reset_data( debug_cpu_ptm0__ETMCCER, val_debug_cpu_ptm0__ETMCCER); +set_reset_data( debug_cpu_ptm0__ETMEXTINSELR, val_debug_cpu_ptm0__ETMEXTINSELR); +set_reset_data( debug_cpu_ptm0__ETMAUXCR, val_debug_cpu_ptm0__ETMAUXCR); +set_reset_data( debug_cpu_ptm0__ETMTRACEIDR, val_debug_cpu_ptm0__ETMTRACEIDR); +set_reset_data( debug_cpu_ptm0__OSLSR, val_debug_cpu_ptm0__OSLSR); +set_reset_data( debug_cpu_ptm0__ETMPDSR, val_debug_cpu_ptm0__ETMPDSR); +set_reset_data( debug_cpu_ptm0__ITMISCOUT, val_debug_cpu_ptm0__ITMISCOUT); +set_reset_data( debug_cpu_ptm0__ITMISCIN, val_debug_cpu_ptm0__ITMISCIN); +set_reset_data( debug_cpu_ptm0__ITTRIGGER, val_debug_cpu_ptm0__ITTRIGGER); +set_reset_data( debug_cpu_ptm0__ITATBDATA0, val_debug_cpu_ptm0__ITATBDATA0); +set_reset_data( debug_cpu_ptm0__ITATBCTR2, val_debug_cpu_ptm0__ITATBCTR2); +set_reset_data( debug_cpu_ptm0__ITATBID, val_debug_cpu_ptm0__ITATBID); +set_reset_data( debug_cpu_ptm0__ITATBCTR0, val_debug_cpu_ptm0__ITATBCTR0); +set_reset_data( debug_cpu_ptm0__ETMITCTRL, val_debug_cpu_ptm0__ETMITCTRL); +set_reset_data( debug_cpu_ptm0__CTSR, val_debug_cpu_ptm0__CTSR); +set_reset_data( debug_cpu_ptm0__CTCR, val_debug_cpu_ptm0__CTCR); +set_reset_data( debug_cpu_ptm0__LAR, val_debug_cpu_ptm0__LAR); +set_reset_data( debug_cpu_ptm0__LSR, val_debug_cpu_ptm0__LSR); +set_reset_data( debug_cpu_ptm0__ASR, val_debug_cpu_ptm0__ASR); +set_reset_data( debug_cpu_ptm0__DEVID, val_debug_cpu_ptm0__DEVID); +set_reset_data( debug_cpu_ptm0__DTIR, val_debug_cpu_ptm0__DTIR); +set_reset_data( debug_cpu_ptm0__PERIPHID4, val_debug_cpu_ptm0__PERIPHID4); +set_reset_data( debug_cpu_ptm0__PERIPHID5, val_debug_cpu_ptm0__PERIPHID5); +set_reset_data( debug_cpu_ptm0__PERIPHID6, val_debug_cpu_ptm0__PERIPHID6); +set_reset_data( debug_cpu_ptm0__PERIPHID7, val_debug_cpu_ptm0__PERIPHID7); +set_reset_data( debug_cpu_ptm0__PERIPHID0, val_debug_cpu_ptm0__PERIPHID0); +set_reset_data( debug_cpu_ptm0__PERIPHID1, val_debug_cpu_ptm0__PERIPHID1); +set_reset_data( debug_cpu_ptm0__PERIPHID2, val_debug_cpu_ptm0__PERIPHID2); +set_reset_data( debug_cpu_ptm0__PERIPHID3, val_debug_cpu_ptm0__PERIPHID3); +set_reset_data( debug_cpu_ptm0__COMPID0, val_debug_cpu_ptm0__COMPID0); +set_reset_data( debug_cpu_ptm0__COMPID1, val_debug_cpu_ptm0__COMPID1); +set_reset_data( debug_cpu_ptm0__COMPID2, val_debug_cpu_ptm0__COMPID2); +set_reset_data( debug_cpu_ptm0__COMPID3, val_debug_cpu_ptm0__COMPID3); + +// ************************************************************ +// Module debug_cpu_ptm1 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_ptm1__ETMCR, val_debug_cpu_ptm1__ETMCR); +set_reset_data( debug_cpu_ptm1__ETMCCR, val_debug_cpu_ptm1__ETMCCR); +set_reset_data( debug_cpu_ptm1__ETMTRIGGER, val_debug_cpu_ptm1__ETMTRIGGER); +set_reset_data( debug_cpu_ptm1__ETMSR, val_debug_cpu_ptm1__ETMSR); +set_reset_data( debug_cpu_ptm1__ETMSCR, val_debug_cpu_ptm1__ETMSCR); +set_reset_data( debug_cpu_ptm1__ETMTSSCR, val_debug_cpu_ptm1__ETMTSSCR); +set_reset_data( debug_cpu_ptm1__ETMTECR1, val_debug_cpu_ptm1__ETMTECR1); +set_reset_data( debug_cpu_ptm1__ETMACVR1, val_debug_cpu_ptm1__ETMACVR1); +set_reset_data( debug_cpu_ptm1__ETMACVR2, val_debug_cpu_ptm1__ETMACVR2); +set_reset_data( debug_cpu_ptm1__ETMACVR3, val_debug_cpu_ptm1__ETMACVR3); +set_reset_data( debug_cpu_ptm1__ETMACVR4, val_debug_cpu_ptm1__ETMACVR4); +set_reset_data( debug_cpu_ptm1__ETMACVR5, val_debug_cpu_ptm1__ETMACVR5); +set_reset_data( debug_cpu_ptm1__ETMACVR6, val_debug_cpu_ptm1__ETMACVR6); +set_reset_data( debug_cpu_ptm1__ETMACVR7, val_debug_cpu_ptm1__ETMACVR7); +set_reset_data( debug_cpu_ptm1__ETMACVR8, val_debug_cpu_ptm1__ETMACVR8); +set_reset_data( debug_cpu_ptm1__ETMACTR1, val_debug_cpu_ptm1__ETMACTR1); +set_reset_data( debug_cpu_ptm1__ETMACTR2, val_debug_cpu_ptm1__ETMACTR2); +set_reset_data( debug_cpu_ptm1__ETMACTR3, val_debug_cpu_ptm1__ETMACTR3); +set_reset_data( debug_cpu_ptm1__ETMACTR4, val_debug_cpu_ptm1__ETMACTR4); +set_reset_data( debug_cpu_ptm1__ETMACTR5, val_debug_cpu_ptm1__ETMACTR5); +set_reset_data( debug_cpu_ptm1__ETMACTR6, val_debug_cpu_ptm1__ETMACTR6); +set_reset_data( debug_cpu_ptm1__ETMACTR7, val_debug_cpu_ptm1__ETMACTR7); +set_reset_data( debug_cpu_ptm1__ETMACTR8, val_debug_cpu_ptm1__ETMACTR8); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR1, val_debug_cpu_ptm1__ETMCNTRLDVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR2, val_debug_cpu_ptm1__ETMCNTRLDVR2); +set_reset_data( debug_cpu_ptm1__ETMCNTENR1, val_debug_cpu_ptm1__ETMCNTENR1); +set_reset_data( debug_cpu_ptm1__ETMCNTENR2, val_debug_cpu_ptm1__ETMCNTENR2); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR1, val_debug_cpu_ptm1__ETMCNTRLDEVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR2, val_debug_cpu_ptm1__ETMCNTRLDEVR2); +set_reset_data( debug_cpu_ptm1__ETMCNTVR1, val_debug_cpu_ptm1__ETMCNTVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTVR2, val_debug_cpu_ptm1__ETMCNTVR2); +set_reset_data( debug_cpu_ptm1__ETMSQ12EVR, val_debug_cpu_ptm1__ETMSQ12EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ21EVR, val_debug_cpu_ptm1__ETMSQ21EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ23EVR, val_debug_cpu_ptm1__ETMSQ23EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ31EVR, val_debug_cpu_ptm1__ETMSQ31EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ32EVR, val_debug_cpu_ptm1__ETMSQ32EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ13EVR, val_debug_cpu_ptm1__ETMSQ13EVR); +set_reset_data( debug_cpu_ptm1__ETMSQR, val_debug_cpu_ptm1__ETMSQR); +set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR1, val_debug_cpu_ptm1__ETMEXTOUTEVR1); +set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR2, val_debug_cpu_ptm1__ETMEXTOUTEVR2); +set_reset_data( debug_cpu_ptm1__ETMCIDCVR1, val_debug_cpu_ptm1__ETMCIDCVR1); +set_reset_data( debug_cpu_ptm1__ETMCIDCMR, val_debug_cpu_ptm1__ETMCIDCMR); +set_reset_data( debug_cpu_ptm1__ETMSYNCFR, val_debug_cpu_ptm1__ETMSYNCFR); +set_reset_data( debug_cpu_ptm1__ETMIDR, val_debug_cpu_ptm1__ETMIDR); +set_reset_data( debug_cpu_ptm1__ETMCCER, val_debug_cpu_ptm1__ETMCCER); +set_reset_data( debug_cpu_ptm1__ETMEXTINSELR, val_debug_cpu_ptm1__ETMEXTINSELR); +set_reset_data( debug_cpu_ptm1__ETMAUXCR, val_debug_cpu_ptm1__ETMAUXCR); +set_reset_data( debug_cpu_ptm1__ETMTRACEIDR, val_debug_cpu_ptm1__ETMTRACEIDR); +set_reset_data( debug_cpu_ptm1__OSLSR, val_debug_cpu_ptm1__OSLSR); +set_reset_data( debug_cpu_ptm1__ETMPDSR, val_debug_cpu_ptm1__ETMPDSR); +set_reset_data( debug_cpu_ptm1__ITMISCOUT, val_debug_cpu_ptm1__ITMISCOUT); +set_reset_data( debug_cpu_ptm1__ITMISCIN, val_debug_cpu_ptm1__ITMISCIN); +set_reset_data( debug_cpu_ptm1__ITTRIGGER, val_debug_cpu_ptm1__ITTRIGGER); +set_reset_data( debug_cpu_ptm1__ITATBDATA0, val_debug_cpu_ptm1__ITATBDATA0); +set_reset_data( debug_cpu_ptm1__ITATBCTR2, val_debug_cpu_ptm1__ITATBCTR2); +set_reset_data( debug_cpu_ptm1__ITATBID, val_debug_cpu_ptm1__ITATBID); +set_reset_data( debug_cpu_ptm1__ITATBCTR0, val_debug_cpu_ptm1__ITATBCTR0); +set_reset_data( debug_cpu_ptm1__ETMITCTRL, val_debug_cpu_ptm1__ETMITCTRL); +set_reset_data( debug_cpu_ptm1__CTSR, val_debug_cpu_ptm1__CTSR); +set_reset_data( debug_cpu_ptm1__CTCR, val_debug_cpu_ptm1__CTCR); +set_reset_data( debug_cpu_ptm1__LAR, val_debug_cpu_ptm1__LAR); +set_reset_data( debug_cpu_ptm1__LSR, val_debug_cpu_ptm1__LSR); +set_reset_data( debug_cpu_ptm1__ASR, val_debug_cpu_ptm1__ASR); +set_reset_data( debug_cpu_ptm1__DEVID, val_debug_cpu_ptm1__DEVID); +set_reset_data( debug_cpu_ptm1__DTIR, val_debug_cpu_ptm1__DTIR); +set_reset_data( debug_cpu_ptm1__PERIPHID4, val_debug_cpu_ptm1__PERIPHID4); +set_reset_data( debug_cpu_ptm1__PERIPHID5, val_debug_cpu_ptm1__PERIPHID5); +set_reset_data( debug_cpu_ptm1__PERIPHID6, val_debug_cpu_ptm1__PERIPHID6); +set_reset_data( debug_cpu_ptm1__PERIPHID7, val_debug_cpu_ptm1__PERIPHID7); +set_reset_data( debug_cpu_ptm1__PERIPHID0, val_debug_cpu_ptm1__PERIPHID0); +set_reset_data( debug_cpu_ptm1__PERIPHID1, val_debug_cpu_ptm1__PERIPHID1); +set_reset_data( debug_cpu_ptm1__PERIPHID2, val_debug_cpu_ptm1__PERIPHID2); +set_reset_data( debug_cpu_ptm1__PERIPHID3, val_debug_cpu_ptm1__PERIPHID3); +set_reset_data( debug_cpu_ptm1__COMPID0, val_debug_cpu_ptm1__COMPID0); +set_reset_data( debug_cpu_ptm1__COMPID1, val_debug_cpu_ptm1__COMPID1); +set_reset_data( debug_cpu_ptm1__COMPID2, val_debug_cpu_ptm1__COMPID2); +set_reset_data( debug_cpu_ptm1__COMPID3, val_debug_cpu_ptm1__COMPID3); + +// ************************************************************ +// Module debug_cti_axim cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_axim__CTICONTROL, val_debug_cti_axim__CTICONTROL); +set_reset_data( debug_cti_axim__CTIINTACK, val_debug_cti_axim__CTIINTACK); +set_reset_data( debug_cti_axim__CTIAPPSET, val_debug_cti_axim__CTIAPPSET); +set_reset_data( debug_cti_axim__CTIAPPCLEAR, val_debug_cti_axim__CTIAPPCLEAR); +set_reset_data( debug_cti_axim__CTIAPPPULSE, val_debug_cti_axim__CTIAPPPULSE); +set_reset_data( debug_cti_axim__CTIINEN0, val_debug_cti_axim__CTIINEN0); +set_reset_data( debug_cti_axim__CTIINEN1, val_debug_cti_axim__CTIINEN1); +set_reset_data( debug_cti_axim__CTIINEN2, val_debug_cti_axim__CTIINEN2); +set_reset_data( debug_cti_axim__CTIINEN3, val_debug_cti_axim__CTIINEN3); +set_reset_data( debug_cti_axim__CTIINEN4, val_debug_cti_axim__CTIINEN4); +set_reset_data( debug_cti_axim__CTIINEN5, val_debug_cti_axim__CTIINEN5); +set_reset_data( debug_cti_axim__CTIINEN6, val_debug_cti_axim__CTIINEN6); +set_reset_data( debug_cti_axim__CTIINEN7, val_debug_cti_axim__CTIINEN7); +set_reset_data( debug_cti_axim__CTIOUTEN0, val_debug_cti_axim__CTIOUTEN0); +set_reset_data( debug_cti_axim__CTIOUTEN1, val_debug_cti_axim__CTIOUTEN1); +set_reset_data( debug_cti_axim__CTIOUTEN2, val_debug_cti_axim__CTIOUTEN2); +set_reset_data( debug_cti_axim__CTIOUTEN3, val_debug_cti_axim__CTIOUTEN3); +set_reset_data( debug_cti_axim__CTIOUTEN4, val_debug_cti_axim__CTIOUTEN4); +set_reset_data( debug_cti_axim__CTIOUTEN5, val_debug_cti_axim__CTIOUTEN5); +set_reset_data( debug_cti_axim__CTIOUTEN6, val_debug_cti_axim__CTIOUTEN6); +set_reset_data( debug_cti_axim__CTIOUTEN7, val_debug_cti_axim__CTIOUTEN7); +set_reset_data( debug_cti_axim__CTITRIGINSTATUS, val_debug_cti_axim__CTITRIGINSTATUS); +set_reset_data( debug_cti_axim__CTITRIGOUTSTATUS, val_debug_cti_axim__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_axim__CTICHINSTATUS, val_debug_cti_axim__CTICHINSTATUS); +set_reset_data( debug_cti_axim__CTICHOUTSTATUS, val_debug_cti_axim__CTICHOUTSTATUS); +set_reset_data( debug_cti_axim__CTIGATE, val_debug_cti_axim__CTIGATE); +set_reset_data( debug_cti_axim__ASICCTL, val_debug_cti_axim__ASICCTL); +set_reset_data( debug_cti_axim__ITCHINACK, val_debug_cti_axim__ITCHINACK); +set_reset_data( debug_cti_axim__ITTRIGINACK, val_debug_cti_axim__ITTRIGINACK); +set_reset_data( debug_cti_axim__ITCHOUT, val_debug_cti_axim__ITCHOUT); +set_reset_data( debug_cti_axim__ITTRIGOUT, val_debug_cti_axim__ITTRIGOUT); +set_reset_data( debug_cti_axim__ITCHOUTACK, val_debug_cti_axim__ITCHOUTACK); +set_reset_data( debug_cti_axim__ITTRIGOUTACK, val_debug_cti_axim__ITTRIGOUTACK); +set_reset_data( debug_cti_axim__ITCHIN, val_debug_cti_axim__ITCHIN); +set_reset_data( debug_cti_axim__ITTRIGIN, val_debug_cti_axim__ITTRIGIN); +set_reset_data( debug_cti_axim__ITCTRL, val_debug_cti_axim__ITCTRL); +set_reset_data( debug_cti_axim__CTSR, val_debug_cti_axim__CTSR); +set_reset_data( debug_cti_axim__CTCR, val_debug_cti_axim__CTCR); +set_reset_data( debug_cti_axim__LAR, val_debug_cti_axim__LAR); +set_reset_data( debug_cti_axim__LSR, val_debug_cti_axim__LSR); +set_reset_data( debug_cti_axim__ASR, val_debug_cti_axim__ASR); +set_reset_data( debug_cti_axim__DEVID, val_debug_cti_axim__DEVID); +set_reset_data( debug_cti_axim__DTIR, val_debug_cti_axim__DTIR); +set_reset_data( debug_cti_axim__PERIPHID4, val_debug_cti_axim__PERIPHID4); +set_reset_data( debug_cti_axim__PERIPHID5, val_debug_cti_axim__PERIPHID5); +set_reset_data( debug_cti_axim__PERIPHID6, val_debug_cti_axim__PERIPHID6); +set_reset_data( debug_cti_axim__PERIPHID7, val_debug_cti_axim__PERIPHID7); +set_reset_data( debug_cti_axim__PERIPHID0, val_debug_cti_axim__PERIPHID0); +set_reset_data( debug_cti_axim__PERIPHID1, val_debug_cti_axim__PERIPHID1); +set_reset_data( debug_cti_axim__PERIPHID2, val_debug_cti_axim__PERIPHID2); +set_reset_data( debug_cti_axim__PERIPHID3, val_debug_cti_axim__PERIPHID3); +set_reset_data( debug_cti_axim__COMPID0, val_debug_cti_axim__COMPID0); +set_reset_data( debug_cti_axim__COMPID1, val_debug_cti_axim__COMPID1); +set_reset_data( debug_cti_axim__COMPID2, val_debug_cti_axim__COMPID2); +set_reset_data( debug_cti_axim__COMPID3, val_debug_cti_axim__COMPID3); + +// ************************************************************ +// Module debug_cti_etb_tpiu cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_etb_tpiu__CTICONTROL, val_debug_cti_etb_tpiu__CTICONTROL); +set_reset_data( debug_cti_etb_tpiu__CTIINTACK, val_debug_cti_etb_tpiu__CTIINTACK); +set_reset_data( debug_cti_etb_tpiu__CTIAPPSET, val_debug_cti_etb_tpiu__CTIAPPSET); +set_reset_data( debug_cti_etb_tpiu__CTIAPPCLEAR, val_debug_cti_etb_tpiu__CTIAPPCLEAR); +set_reset_data( debug_cti_etb_tpiu__CTIAPPPULSE, val_debug_cti_etb_tpiu__CTIAPPPULSE); +set_reset_data( debug_cti_etb_tpiu__CTIINEN0, val_debug_cti_etb_tpiu__CTIINEN0); +set_reset_data( debug_cti_etb_tpiu__CTIINEN1, val_debug_cti_etb_tpiu__CTIINEN1); +set_reset_data( debug_cti_etb_tpiu__CTIINEN2, val_debug_cti_etb_tpiu__CTIINEN2); +set_reset_data( debug_cti_etb_tpiu__CTIINEN3, val_debug_cti_etb_tpiu__CTIINEN3); +set_reset_data( debug_cti_etb_tpiu__CTIINEN4, val_debug_cti_etb_tpiu__CTIINEN4); +set_reset_data( debug_cti_etb_tpiu__CTIINEN5, val_debug_cti_etb_tpiu__CTIINEN5); +set_reset_data( debug_cti_etb_tpiu__CTIINEN6, val_debug_cti_etb_tpiu__CTIINEN6); +set_reset_data( debug_cti_etb_tpiu__CTIINEN7, val_debug_cti_etb_tpiu__CTIINEN7); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN0, val_debug_cti_etb_tpiu__CTIOUTEN0); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN1, val_debug_cti_etb_tpiu__CTIOUTEN1); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN2, val_debug_cti_etb_tpiu__CTIOUTEN2); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN3, val_debug_cti_etb_tpiu__CTIOUTEN3); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN4, val_debug_cti_etb_tpiu__CTIOUTEN4); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN5, val_debug_cti_etb_tpiu__CTIOUTEN5); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN6, val_debug_cti_etb_tpiu__CTIOUTEN6); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN7, val_debug_cti_etb_tpiu__CTIOUTEN7); +set_reset_data( debug_cti_etb_tpiu__CTITRIGINSTATUS, val_debug_cti_etb_tpiu__CTITRIGINSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTITRIGOUTSTATUS, val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTICHINSTATUS, val_debug_cti_etb_tpiu__CTICHINSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTICHOUTSTATUS, val_debug_cti_etb_tpiu__CTICHOUTSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTIGATE, val_debug_cti_etb_tpiu__CTIGATE); +set_reset_data( debug_cti_etb_tpiu__ASICCTL, val_debug_cti_etb_tpiu__ASICCTL); +set_reset_data( debug_cti_etb_tpiu__ITCHINACK, val_debug_cti_etb_tpiu__ITCHINACK); +set_reset_data( debug_cti_etb_tpiu__ITTRIGINACK, val_debug_cti_etb_tpiu__ITTRIGINACK); +set_reset_data( debug_cti_etb_tpiu__ITCHOUT, val_debug_cti_etb_tpiu__ITCHOUT); +set_reset_data( debug_cti_etb_tpiu__ITTRIGOUT, val_debug_cti_etb_tpiu__ITTRIGOUT); +set_reset_data( debug_cti_etb_tpiu__ITCHOUTACK, val_debug_cti_etb_tpiu__ITCHOUTACK); +set_reset_data( debug_cti_etb_tpiu__ITTRIGOUTACK, val_debug_cti_etb_tpiu__ITTRIGOUTACK); +set_reset_data( debug_cti_etb_tpiu__ITCHIN, val_debug_cti_etb_tpiu__ITCHIN); +set_reset_data( debug_cti_etb_tpiu__ITTRIGIN, val_debug_cti_etb_tpiu__ITTRIGIN); +set_reset_data( debug_cti_etb_tpiu__ITCTRL, val_debug_cti_etb_tpiu__ITCTRL); +set_reset_data( debug_cti_etb_tpiu__CTSR, val_debug_cti_etb_tpiu__CTSR); +set_reset_data( debug_cti_etb_tpiu__CTCR, val_debug_cti_etb_tpiu__CTCR); +set_reset_data( debug_cti_etb_tpiu__LAR, val_debug_cti_etb_tpiu__LAR); +set_reset_data( debug_cti_etb_tpiu__LSR, val_debug_cti_etb_tpiu__LSR); +set_reset_data( debug_cti_etb_tpiu__ASR, val_debug_cti_etb_tpiu__ASR); +set_reset_data( debug_cti_etb_tpiu__DEVID, val_debug_cti_etb_tpiu__DEVID); +set_reset_data( debug_cti_etb_tpiu__DTIR, val_debug_cti_etb_tpiu__DTIR); +set_reset_data( debug_cti_etb_tpiu__PERIPHID4, val_debug_cti_etb_tpiu__PERIPHID4); +set_reset_data( debug_cti_etb_tpiu__PERIPHID5, val_debug_cti_etb_tpiu__PERIPHID5); +set_reset_data( debug_cti_etb_tpiu__PERIPHID6, val_debug_cti_etb_tpiu__PERIPHID6); +set_reset_data( debug_cti_etb_tpiu__PERIPHID7, val_debug_cti_etb_tpiu__PERIPHID7); +set_reset_data( debug_cti_etb_tpiu__PERIPHID0, val_debug_cti_etb_tpiu__PERIPHID0); +set_reset_data( debug_cti_etb_tpiu__PERIPHID1, val_debug_cti_etb_tpiu__PERIPHID1); +set_reset_data( debug_cti_etb_tpiu__PERIPHID2, val_debug_cti_etb_tpiu__PERIPHID2); +set_reset_data( debug_cti_etb_tpiu__PERIPHID3, val_debug_cti_etb_tpiu__PERIPHID3); +set_reset_data( debug_cti_etb_tpiu__COMPID0, val_debug_cti_etb_tpiu__COMPID0); +set_reset_data( debug_cti_etb_tpiu__COMPID1, val_debug_cti_etb_tpiu__COMPID1); +set_reset_data( debug_cti_etb_tpiu__COMPID2, val_debug_cti_etb_tpiu__COMPID2); +set_reset_data( debug_cti_etb_tpiu__COMPID3, val_debug_cti_etb_tpiu__COMPID3); + +// ************************************************************ +// Module debug_cti_ftm cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_ftm__CTICONTROL, val_debug_cti_ftm__CTICONTROL); +set_reset_data( debug_cti_ftm__CTIINTACK, val_debug_cti_ftm__CTIINTACK); +set_reset_data( debug_cti_ftm__CTIAPPSET, val_debug_cti_ftm__CTIAPPSET); +set_reset_data( debug_cti_ftm__CTIAPPCLEAR, val_debug_cti_ftm__CTIAPPCLEAR); +set_reset_data( debug_cti_ftm__CTIAPPPULSE, val_debug_cti_ftm__CTIAPPPULSE); +set_reset_data( debug_cti_ftm__CTIINEN0, val_debug_cti_ftm__CTIINEN0); +set_reset_data( debug_cti_ftm__CTIINEN1, val_debug_cti_ftm__CTIINEN1); +set_reset_data( debug_cti_ftm__CTIINEN2, val_debug_cti_ftm__CTIINEN2); +set_reset_data( debug_cti_ftm__CTIINEN3, val_debug_cti_ftm__CTIINEN3); +set_reset_data( debug_cti_ftm__CTIINEN4, val_debug_cti_ftm__CTIINEN4); +set_reset_data( debug_cti_ftm__CTIINEN5, val_debug_cti_ftm__CTIINEN5); +set_reset_data( debug_cti_ftm__CTIINEN6, val_debug_cti_ftm__CTIINEN6); +set_reset_data( debug_cti_ftm__CTIINEN7, val_debug_cti_ftm__CTIINEN7); +set_reset_data( debug_cti_ftm__CTIOUTEN0, val_debug_cti_ftm__CTIOUTEN0); +set_reset_data( debug_cti_ftm__CTIOUTEN1, val_debug_cti_ftm__CTIOUTEN1); +set_reset_data( debug_cti_ftm__CTIOUTEN2, val_debug_cti_ftm__CTIOUTEN2); +set_reset_data( debug_cti_ftm__CTIOUTEN3, val_debug_cti_ftm__CTIOUTEN3); +set_reset_data( debug_cti_ftm__CTIOUTEN4, val_debug_cti_ftm__CTIOUTEN4); +set_reset_data( debug_cti_ftm__CTIOUTEN5, val_debug_cti_ftm__CTIOUTEN5); +set_reset_data( debug_cti_ftm__CTIOUTEN6, val_debug_cti_ftm__CTIOUTEN6); +set_reset_data( debug_cti_ftm__CTIOUTEN7, val_debug_cti_ftm__CTIOUTEN7); +set_reset_data( debug_cti_ftm__CTITRIGINSTATUS, val_debug_cti_ftm__CTITRIGINSTATUS); +set_reset_data( debug_cti_ftm__CTITRIGOUTSTATUS, val_debug_cti_ftm__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_ftm__CTICHINSTATUS, val_debug_cti_ftm__CTICHINSTATUS); +set_reset_data( debug_cti_ftm__CTICHOUTSTATUS, val_debug_cti_ftm__CTICHOUTSTATUS); +set_reset_data( debug_cti_ftm__CTIGATE, val_debug_cti_ftm__CTIGATE); +set_reset_data( debug_cti_ftm__ASICCTL, val_debug_cti_ftm__ASICCTL); +set_reset_data( debug_cti_ftm__ITCHINACK, val_debug_cti_ftm__ITCHINACK); +set_reset_data( debug_cti_ftm__ITTRIGINACK, val_debug_cti_ftm__ITTRIGINACK); +set_reset_data( debug_cti_ftm__ITCHOUT, val_debug_cti_ftm__ITCHOUT); +set_reset_data( debug_cti_ftm__ITTRIGOUT, val_debug_cti_ftm__ITTRIGOUT); +set_reset_data( debug_cti_ftm__ITCHOUTACK, val_debug_cti_ftm__ITCHOUTACK); +set_reset_data( debug_cti_ftm__ITTRIGOUTACK, val_debug_cti_ftm__ITTRIGOUTACK); +set_reset_data( debug_cti_ftm__ITCHIN, val_debug_cti_ftm__ITCHIN); +set_reset_data( debug_cti_ftm__ITTRIGIN, val_debug_cti_ftm__ITTRIGIN); +set_reset_data( debug_cti_ftm__ITCTRL, val_debug_cti_ftm__ITCTRL); +set_reset_data( debug_cti_ftm__CTSR, val_debug_cti_ftm__CTSR); +set_reset_data( debug_cti_ftm__CTCR, val_debug_cti_ftm__CTCR); +set_reset_data( debug_cti_ftm__LAR, val_debug_cti_ftm__LAR); +set_reset_data( debug_cti_ftm__LSR, val_debug_cti_ftm__LSR); +set_reset_data( debug_cti_ftm__ASR, val_debug_cti_ftm__ASR); +set_reset_data( debug_cti_ftm__DEVID, val_debug_cti_ftm__DEVID); +set_reset_data( debug_cti_ftm__DTIR, val_debug_cti_ftm__DTIR); +set_reset_data( debug_cti_ftm__PERIPHID4, val_debug_cti_ftm__PERIPHID4); +set_reset_data( debug_cti_ftm__PERIPHID5, val_debug_cti_ftm__PERIPHID5); +set_reset_data( debug_cti_ftm__PERIPHID6, val_debug_cti_ftm__PERIPHID6); +set_reset_data( debug_cti_ftm__PERIPHID7, val_debug_cti_ftm__PERIPHID7); +set_reset_data( debug_cti_ftm__PERIPHID0, val_debug_cti_ftm__PERIPHID0); +set_reset_data( debug_cti_ftm__PERIPHID1, val_debug_cti_ftm__PERIPHID1); +set_reset_data( debug_cti_ftm__PERIPHID2, val_debug_cti_ftm__PERIPHID2); +set_reset_data( debug_cti_ftm__PERIPHID3, val_debug_cti_ftm__PERIPHID3); +set_reset_data( debug_cti_ftm__COMPID0, val_debug_cti_ftm__COMPID0); +set_reset_data( debug_cti_ftm__COMPID1, val_debug_cti_ftm__COMPID1); +set_reset_data( debug_cti_ftm__COMPID2, val_debug_cti_ftm__COMPID2); +set_reset_data( debug_cti_ftm__COMPID3, val_debug_cti_ftm__COMPID3); + +// ************************************************************ +// Module debug_dap_rom dap +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_dap_rom__ROMENTRY00, val_debug_dap_rom__ROMENTRY00); +set_reset_data( debug_dap_rom__ROMENTRY01, val_debug_dap_rom__ROMENTRY01); +set_reset_data( debug_dap_rom__ROMENTRY02, val_debug_dap_rom__ROMENTRY02); +set_reset_data( debug_dap_rom__ROMENTRY03, val_debug_dap_rom__ROMENTRY03); +set_reset_data( debug_dap_rom__ROMENTRY04, val_debug_dap_rom__ROMENTRY04); +set_reset_data( debug_dap_rom__ROMENTRY05, val_debug_dap_rom__ROMENTRY05); +set_reset_data( debug_dap_rom__ROMENTRY06, val_debug_dap_rom__ROMENTRY06); +set_reset_data( debug_dap_rom__ROMENTRY07, val_debug_dap_rom__ROMENTRY07); +set_reset_data( debug_dap_rom__ROMENTRY08, val_debug_dap_rom__ROMENTRY08); +set_reset_data( debug_dap_rom__ROMENTRY09, val_debug_dap_rom__ROMENTRY09); +set_reset_data( debug_dap_rom__ROMENTRY10, val_debug_dap_rom__ROMENTRY10); +set_reset_data( debug_dap_rom__ROMENTRY11, val_debug_dap_rom__ROMENTRY11); +set_reset_data( debug_dap_rom__ROMENTRY12, val_debug_dap_rom__ROMENTRY12); +set_reset_data( debug_dap_rom__ROMENTRY13, val_debug_dap_rom__ROMENTRY13); +set_reset_data( debug_dap_rom__ROMENTRY14, val_debug_dap_rom__ROMENTRY14); +set_reset_data( debug_dap_rom__ROMENTRY15, val_debug_dap_rom__ROMENTRY15); +set_reset_data( debug_dap_rom__PERIPHID4, val_debug_dap_rom__PERIPHID4); +set_reset_data( debug_dap_rom__PERIPHID5, val_debug_dap_rom__PERIPHID5); +set_reset_data( debug_dap_rom__PERIPHID6, val_debug_dap_rom__PERIPHID6); +set_reset_data( debug_dap_rom__PERIPHID7, val_debug_dap_rom__PERIPHID7); +set_reset_data( debug_dap_rom__PERIPHID0, val_debug_dap_rom__PERIPHID0); +set_reset_data( debug_dap_rom__PERIPHID1, val_debug_dap_rom__PERIPHID1); +set_reset_data( debug_dap_rom__PERIPHID2, val_debug_dap_rom__PERIPHID2); +set_reset_data( debug_dap_rom__PERIPHID3, val_debug_dap_rom__PERIPHID3); +set_reset_data( debug_dap_rom__COMPID0, val_debug_dap_rom__COMPID0); +set_reset_data( debug_dap_rom__COMPID1, val_debug_dap_rom__COMPID1); +set_reset_data( debug_dap_rom__COMPID2, val_debug_dap_rom__COMPID2); +set_reset_data( debug_dap_rom__COMPID3, val_debug_dap_rom__COMPID3); + +// ************************************************************ +// Module debug_etb etb +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_etb__RDP, val_debug_etb__RDP); +set_reset_data( debug_etb__STS, val_debug_etb__STS); +set_reset_data( debug_etb__RRD, val_debug_etb__RRD); +set_reset_data( debug_etb__RRP, val_debug_etb__RRP); +set_reset_data( debug_etb__RWP, val_debug_etb__RWP); +set_reset_data( debug_etb__TRG, val_debug_etb__TRG); +set_reset_data( debug_etb__CTL, val_debug_etb__CTL); +set_reset_data( debug_etb__RWD, val_debug_etb__RWD); +set_reset_data( debug_etb__FFSR, val_debug_etb__FFSR); +set_reset_data( debug_etb__FFCR, val_debug_etb__FFCR); +set_reset_data( debug_etb__ITMISCOP0, val_debug_etb__ITMISCOP0); +set_reset_data( debug_etb__ITTRFLINACK, val_debug_etb__ITTRFLINACK); +set_reset_data( debug_etb__ITTRFLIN, val_debug_etb__ITTRFLIN); +set_reset_data( debug_etb__ITATBDATA0, val_debug_etb__ITATBDATA0); +set_reset_data( debug_etb__ITATBCTR2, val_debug_etb__ITATBCTR2); +set_reset_data( debug_etb__ITATBCTR1, val_debug_etb__ITATBCTR1); +set_reset_data( debug_etb__ITATBCTR0, val_debug_etb__ITATBCTR0); +set_reset_data( debug_etb__IMCR, val_debug_etb__IMCR); +set_reset_data( debug_etb__CTSR, val_debug_etb__CTSR); +set_reset_data( debug_etb__CTCR, val_debug_etb__CTCR); +set_reset_data( debug_etb__LAR, val_debug_etb__LAR); +set_reset_data( debug_etb__LSR, val_debug_etb__LSR); +set_reset_data( debug_etb__ASR, val_debug_etb__ASR); +set_reset_data( debug_etb__DEVID, val_debug_etb__DEVID); +set_reset_data( debug_etb__DTIR, val_debug_etb__DTIR); +set_reset_data( debug_etb__PERIPHID4, val_debug_etb__PERIPHID4); +set_reset_data( debug_etb__PERIPHID5, val_debug_etb__PERIPHID5); +set_reset_data( debug_etb__PERIPHID6, val_debug_etb__PERIPHID6); +set_reset_data( debug_etb__PERIPHID7, val_debug_etb__PERIPHID7); +set_reset_data( debug_etb__PERIPHID0, val_debug_etb__PERIPHID0); +set_reset_data( debug_etb__PERIPHID1, val_debug_etb__PERIPHID1); +set_reset_data( debug_etb__PERIPHID2, val_debug_etb__PERIPHID2); +set_reset_data( debug_etb__PERIPHID3, val_debug_etb__PERIPHID3); +set_reset_data( debug_etb__COMPID0, val_debug_etb__COMPID0); +set_reset_data( debug_etb__COMPID1, val_debug_etb__COMPID1); +set_reset_data( debug_etb__COMPID2, val_debug_etb__COMPID2); +set_reset_data( debug_etb__COMPID3, val_debug_etb__COMPID3); + +// ************************************************************ +// Module debug_ftm ftm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_ftm__FTMGLBCTRL, val_debug_ftm__FTMGLBCTRL); +set_reset_data( debug_ftm__FTMSTATUS, val_debug_ftm__FTMSTATUS); +set_reset_data( debug_ftm__FTMCONTROL, val_debug_ftm__FTMCONTROL); +set_reset_data( debug_ftm__FTMP2FDBG0, val_debug_ftm__FTMP2FDBG0); +set_reset_data( debug_ftm__FTMP2FDBG1, val_debug_ftm__FTMP2FDBG1); +set_reset_data( debug_ftm__FTMP2FDBG2, val_debug_ftm__FTMP2FDBG2); +set_reset_data( debug_ftm__FTMP2FDBG3, val_debug_ftm__FTMP2FDBG3); +set_reset_data( debug_ftm__FTMF2PDBG0, val_debug_ftm__FTMF2PDBG0); +set_reset_data( debug_ftm__FTMF2PDBG1, val_debug_ftm__FTMF2PDBG1); +set_reset_data( debug_ftm__FTMF2PDBG2, val_debug_ftm__FTMF2PDBG2); +set_reset_data( debug_ftm__FTMF2PDBG3, val_debug_ftm__FTMF2PDBG3); +set_reset_data( debug_ftm__CYCOUNTPRE, val_debug_ftm__CYCOUNTPRE); +set_reset_data( debug_ftm__FTMSYNCRELOAD, val_debug_ftm__FTMSYNCRELOAD); +set_reset_data( debug_ftm__FTMSYNCCOUT, val_debug_ftm__FTMSYNCCOUT); +set_reset_data( debug_ftm__FTMATID, val_debug_ftm__FTMATID); +set_reset_data( debug_ftm__FTMITTRIGOUTACK, val_debug_ftm__FTMITTRIGOUTACK); +set_reset_data( debug_ftm__FTMITTRIGGER, val_debug_ftm__FTMITTRIGGER); +set_reset_data( debug_ftm__FTMITTRACEDIS, val_debug_ftm__FTMITTRACEDIS); +set_reset_data( debug_ftm__FTMITCYCCOUNT, val_debug_ftm__FTMITCYCCOUNT); +set_reset_data( debug_ftm__FTMITATBDATA0, val_debug_ftm__FTMITATBDATA0); +set_reset_data( debug_ftm__FTMITATBCTR2, val_debug_ftm__FTMITATBCTR2); +set_reset_data( debug_ftm__FTMITATBCTR1, val_debug_ftm__FTMITATBCTR1); +set_reset_data( debug_ftm__FTMITATBCTR0, val_debug_ftm__FTMITATBCTR0); +set_reset_data( debug_ftm__FTMITCR, val_debug_ftm__FTMITCR); +set_reset_data( debug_ftm__CLAIMTAGSET, val_debug_ftm__CLAIMTAGSET); +set_reset_data( debug_ftm__CLAIMTAGCLR, val_debug_ftm__CLAIMTAGCLR); +set_reset_data( debug_ftm__LOCK_ACCESS, val_debug_ftm__LOCK_ACCESS); +set_reset_data( debug_ftm__LOCK_STATUS, val_debug_ftm__LOCK_STATUS); +set_reset_data( debug_ftm__FTMAUTHSTATUS, val_debug_ftm__FTMAUTHSTATUS); +set_reset_data( debug_ftm__FTMDEVID, val_debug_ftm__FTMDEVID); +set_reset_data( debug_ftm__FTMDEV_TYPE, val_debug_ftm__FTMDEV_TYPE); +set_reset_data( debug_ftm__FTMPERIPHID4, val_debug_ftm__FTMPERIPHID4); +set_reset_data( debug_ftm__FTMPERIPHID5, val_debug_ftm__FTMPERIPHID5); +set_reset_data( debug_ftm__FTMPERIPHID6, val_debug_ftm__FTMPERIPHID6); +set_reset_data( debug_ftm__FTMPERIPHID7, val_debug_ftm__FTMPERIPHID7); +set_reset_data( debug_ftm__FTMPERIPHID0, val_debug_ftm__FTMPERIPHID0); +set_reset_data( debug_ftm__FTMPERIPHID1, val_debug_ftm__FTMPERIPHID1); +set_reset_data( debug_ftm__FTMPERIPHID2, val_debug_ftm__FTMPERIPHID2); +set_reset_data( debug_ftm__FTMPERIPHID3, val_debug_ftm__FTMPERIPHID3); +set_reset_data( debug_ftm__FTMCOMPONID0, val_debug_ftm__FTMCOMPONID0); +set_reset_data( debug_ftm__FTMCOMPONID1, val_debug_ftm__FTMCOMPONID1); +set_reset_data( debug_ftm__FTMCOMPONID2, val_debug_ftm__FTMCOMPONID2); +set_reset_data( debug_ftm__FTMCOMPONID3, val_debug_ftm__FTMCOMPONID3); + +// ************************************************************ +// Module debug_funnel funnel +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_funnel__Control, val_debug_funnel__Control); +set_reset_data( debug_funnel__PriControl, val_debug_funnel__PriControl); +set_reset_data( debug_funnel__ITATBDATA0, val_debug_funnel__ITATBDATA0); +set_reset_data( debug_funnel__ITATBCTR2, val_debug_funnel__ITATBCTR2); +set_reset_data( debug_funnel__ITATBCTR1, val_debug_funnel__ITATBCTR1); +set_reset_data( debug_funnel__ITATBCTR0, val_debug_funnel__ITATBCTR0); +set_reset_data( debug_funnel__IMCR, val_debug_funnel__IMCR); +set_reset_data( debug_funnel__CTSR, val_debug_funnel__CTSR); +set_reset_data( debug_funnel__CTCR, val_debug_funnel__CTCR); +set_reset_data( debug_funnel__LAR, val_debug_funnel__LAR); +set_reset_data( debug_funnel__LSR, val_debug_funnel__LSR); +set_reset_data( debug_funnel__ASR, val_debug_funnel__ASR); +set_reset_data( debug_funnel__DEVID, val_debug_funnel__DEVID); +set_reset_data( debug_funnel__DTIR, val_debug_funnel__DTIR); +set_reset_data( debug_funnel__PERIPHID4, val_debug_funnel__PERIPHID4); +set_reset_data( debug_funnel__PERIPHID5, val_debug_funnel__PERIPHID5); +set_reset_data( debug_funnel__PERIPHID6, val_debug_funnel__PERIPHID6); +set_reset_data( debug_funnel__PERIPHID7, val_debug_funnel__PERIPHID7); +set_reset_data( debug_funnel__PERIPHID0, val_debug_funnel__PERIPHID0); +set_reset_data( debug_funnel__PERIPHID1, val_debug_funnel__PERIPHID1); +set_reset_data( debug_funnel__PERIPHID2, val_debug_funnel__PERIPHID2); +set_reset_data( debug_funnel__PERIPHID3, val_debug_funnel__PERIPHID3); +set_reset_data( debug_funnel__COMPID0, val_debug_funnel__COMPID0); +set_reset_data( debug_funnel__COMPID1, val_debug_funnel__COMPID1); +set_reset_data( debug_funnel__COMPID2, val_debug_funnel__COMPID2); +set_reset_data( debug_funnel__COMPID3, val_debug_funnel__COMPID3); + +// ************************************************************ +// Module debug_itm itm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_itm__StimPort00, val_debug_itm__StimPort00); +set_reset_data( debug_itm__StimPort01, val_debug_itm__StimPort01); +set_reset_data( debug_itm__StimPort02, val_debug_itm__StimPort02); +set_reset_data( debug_itm__StimPort03, val_debug_itm__StimPort03); +set_reset_data( debug_itm__StimPort04, val_debug_itm__StimPort04); +set_reset_data( debug_itm__StimPort05, val_debug_itm__StimPort05); +set_reset_data( debug_itm__StimPort06, val_debug_itm__StimPort06); +set_reset_data( debug_itm__StimPort07, val_debug_itm__StimPort07); +set_reset_data( debug_itm__StimPort08, val_debug_itm__StimPort08); +set_reset_data( debug_itm__StimPort09, val_debug_itm__StimPort09); +set_reset_data( debug_itm__StimPort10, val_debug_itm__StimPort10); +set_reset_data( debug_itm__StimPort11, val_debug_itm__StimPort11); +set_reset_data( debug_itm__StimPort12, val_debug_itm__StimPort12); +set_reset_data( debug_itm__StimPort13, val_debug_itm__StimPort13); +set_reset_data( debug_itm__StimPort14, val_debug_itm__StimPort14); +set_reset_data( debug_itm__StimPort15, val_debug_itm__StimPort15); +set_reset_data( debug_itm__StimPort16, val_debug_itm__StimPort16); +set_reset_data( debug_itm__StimPort17, val_debug_itm__StimPort17); +set_reset_data( debug_itm__StimPort18, val_debug_itm__StimPort18); +set_reset_data( debug_itm__StimPort19, val_debug_itm__StimPort19); +set_reset_data( debug_itm__StimPort20, val_debug_itm__StimPort20); +set_reset_data( debug_itm__StimPort21, val_debug_itm__StimPort21); +set_reset_data( debug_itm__StimPort22, val_debug_itm__StimPort22); +set_reset_data( debug_itm__StimPort23, val_debug_itm__StimPort23); +set_reset_data( debug_itm__StimPort24, val_debug_itm__StimPort24); +set_reset_data( debug_itm__StimPort25, val_debug_itm__StimPort25); +set_reset_data( debug_itm__StimPort26, val_debug_itm__StimPort26); +set_reset_data( debug_itm__StimPort27, val_debug_itm__StimPort27); +set_reset_data( debug_itm__StimPort28, val_debug_itm__StimPort28); +set_reset_data( debug_itm__StimPort29, val_debug_itm__StimPort29); +set_reset_data( debug_itm__StimPort30, val_debug_itm__StimPort30); +set_reset_data( debug_itm__StimPort31, val_debug_itm__StimPort31); +set_reset_data( debug_itm__TER, val_debug_itm__TER); +set_reset_data( debug_itm__TTR, val_debug_itm__TTR); +set_reset_data( debug_itm__CR, val_debug_itm__CR); +set_reset_data( debug_itm__SCR, val_debug_itm__SCR); +set_reset_data( debug_itm__ITTRIGOUTACK, val_debug_itm__ITTRIGOUTACK); +set_reset_data( debug_itm__ITTRIGOUT, val_debug_itm__ITTRIGOUT); +set_reset_data( debug_itm__ITATBDATA0, val_debug_itm__ITATBDATA0); +set_reset_data( debug_itm__ITATBCTR2, val_debug_itm__ITATBCTR2); +set_reset_data( debug_itm__ITATABCTR1, val_debug_itm__ITATABCTR1); +set_reset_data( debug_itm__ITATBCTR0, val_debug_itm__ITATBCTR0); +set_reset_data( debug_itm__IMCR, val_debug_itm__IMCR); +set_reset_data( debug_itm__CTSR, val_debug_itm__CTSR); +set_reset_data( debug_itm__CTCR, val_debug_itm__CTCR); +set_reset_data( debug_itm__LAR, val_debug_itm__LAR); +set_reset_data( debug_itm__LSR, val_debug_itm__LSR); +set_reset_data( debug_itm__ASR, val_debug_itm__ASR); +set_reset_data( debug_itm__DEVID, val_debug_itm__DEVID); +set_reset_data( debug_itm__DTIR, val_debug_itm__DTIR); +set_reset_data( debug_itm__PERIPHID4, val_debug_itm__PERIPHID4); +set_reset_data( debug_itm__PERIPHID5, val_debug_itm__PERIPHID5); +set_reset_data( debug_itm__PERIPHID6, val_debug_itm__PERIPHID6); +set_reset_data( debug_itm__PERIPHID7, val_debug_itm__PERIPHID7); +set_reset_data( debug_itm__PERIPHID0, val_debug_itm__PERIPHID0); +set_reset_data( debug_itm__PERIPHID1, val_debug_itm__PERIPHID1); +set_reset_data( debug_itm__PERIPHID2, val_debug_itm__PERIPHID2); +set_reset_data( debug_itm__PERIPHID3, val_debug_itm__PERIPHID3); +set_reset_data( debug_itm__COMPID0, val_debug_itm__COMPID0); +set_reset_data( debug_itm__COMPID1, val_debug_itm__COMPID1); +set_reset_data( debug_itm__COMPID2, val_debug_itm__COMPID2); +set_reset_data( debug_itm__COMPID3, val_debug_itm__COMPID3); + +// ************************************************************ +// Module debug_tpiu tpiu +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_tpiu__SuppSize, val_debug_tpiu__SuppSize); +set_reset_data( debug_tpiu__CurrentSize, val_debug_tpiu__CurrentSize); +set_reset_data( debug_tpiu__SuppTrigMode, val_debug_tpiu__SuppTrigMode); +set_reset_data( debug_tpiu__TrigCount, val_debug_tpiu__TrigCount); +set_reset_data( debug_tpiu__TrigMult, val_debug_tpiu__TrigMult); +set_reset_data( debug_tpiu__SuppTest, val_debug_tpiu__SuppTest); +set_reset_data( debug_tpiu__CurrentTest, val_debug_tpiu__CurrentTest); +set_reset_data( debug_tpiu__TestRepeatCount, val_debug_tpiu__TestRepeatCount); +set_reset_data( debug_tpiu__FFSR, val_debug_tpiu__FFSR); +set_reset_data( debug_tpiu__FFCR, val_debug_tpiu__FFCR); +set_reset_data( debug_tpiu__FormatSyncCount, val_debug_tpiu__FormatSyncCount); +set_reset_data( debug_tpiu__EXTCTLIn, val_debug_tpiu__EXTCTLIn); +set_reset_data( debug_tpiu__EXTCTLOut, val_debug_tpiu__EXTCTLOut); +set_reset_data( debug_tpiu__ITTRFLINACK, val_debug_tpiu__ITTRFLINACK); +set_reset_data( debug_tpiu__ITTRFLIN, val_debug_tpiu__ITTRFLIN); +set_reset_data( debug_tpiu__ITATBDATA0, val_debug_tpiu__ITATBDATA0); +set_reset_data( debug_tpiu__ITATBCTR2, val_debug_tpiu__ITATBCTR2); +set_reset_data( debug_tpiu__ITATBCTR1, val_debug_tpiu__ITATBCTR1); +set_reset_data( debug_tpiu__ITATBCTR0, val_debug_tpiu__ITATBCTR0); +set_reset_data( debug_tpiu__IMCR, val_debug_tpiu__IMCR); +set_reset_data( debug_tpiu__CTSR, val_debug_tpiu__CTSR); +set_reset_data( debug_tpiu__CTCR, val_debug_tpiu__CTCR); +set_reset_data( debug_tpiu__LAR, val_debug_tpiu__LAR); +set_reset_data( debug_tpiu__LSR, val_debug_tpiu__LSR); +set_reset_data( debug_tpiu__ASR, val_debug_tpiu__ASR); +set_reset_data( debug_tpiu__DEVID, val_debug_tpiu__DEVID); +set_reset_data( debug_tpiu__DTIR, val_debug_tpiu__DTIR); +set_reset_data( debug_tpiu__PERIPHID4, val_debug_tpiu__PERIPHID4); +set_reset_data( debug_tpiu__PERIPHID5, val_debug_tpiu__PERIPHID5); +set_reset_data( debug_tpiu__PERIPHID6, val_debug_tpiu__PERIPHID6); +set_reset_data( debug_tpiu__PERIPHID7, val_debug_tpiu__PERIPHID7); +set_reset_data( debug_tpiu__PERIPHID0, val_debug_tpiu__PERIPHID0); +set_reset_data( debug_tpiu__PERIPHID1, val_debug_tpiu__PERIPHID1); +set_reset_data( debug_tpiu__PERIPHID2, val_debug_tpiu__PERIPHID2); +set_reset_data( debug_tpiu__PERIPHID3, val_debug_tpiu__PERIPHID3); +set_reset_data( debug_tpiu__COMPID0, val_debug_tpiu__COMPID0); +set_reset_data( debug_tpiu__COMPID1, val_debug_tpiu__COMPID1); +set_reset_data( debug_tpiu__COMPID2, val_debug_tpiu__COMPID2); +set_reset_data( debug_tpiu__COMPID3, val_debug_tpiu__COMPID3); + +// ************************************************************ +// Module devcfg devcfg +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( devcfg__CTRL, val_devcfg__CTRL); +set_reset_data( devcfg__LOCK, val_devcfg__LOCK); +set_reset_data( devcfg__CFG, val_devcfg__CFG); +set_reset_data( devcfg__INT_STS, val_devcfg__INT_STS); +set_reset_data( devcfg__INT_MASK, val_devcfg__INT_MASK); +set_reset_data( devcfg__STATUS, val_devcfg__STATUS); +set_reset_data( devcfg__DMA_SRC_ADDR, val_devcfg__DMA_SRC_ADDR); +set_reset_data( devcfg__DMA_DST_ADDR, val_devcfg__DMA_DST_ADDR); +set_reset_data( devcfg__DMA_SRC_LEN, val_devcfg__DMA_SRC_LEN); +set_reset_data( devcfg__DMA_DEST_LEN, val_devcfg__DMA_DEST_LEN); +set_reset_data( devcfg__ROM_SHADOW, val_devcfg__ROM_SHADOW); +set_reset_data( devcfg__MULTIBOOT_ADDR, val_devcfg__MULTIBOOT_ADDR); +set_reset_data( devcfg__SW_ID, val_devcfg__SW_ID); +set_reset_data( devcfg__UNLOCK, val_devcfg__UNLOCK); +set_reset_data( devcfg__MCTRL, val_devcfg__MCTRL); +set_reset_data( devcfg__XADCIF_CFG, val_devcfg__XADCIF_CFG); +set_reset_data( devcfg__XADCIF_INT_STS, val_devcfg__XADCIF_INT_STS); +set_reset_data( devcfg__XADCIF_INT_MASK, val_devcfg__XADCIF_INT_MASK); +set_reset_data( devcfg__XADCIF_MSTS, val_devcfg__XADCIF_MSTS); +set_reset_data( devcfg__XADCIF_CMDFIFO, val_devcfg__XADCIF_CMDFIFO); +set_reset_data( devcfg__XADCIF_RDFIFO, val_devcfg__XADCIF_RDFIFO); +set_reset_data( devcfg__XADCIF_MCTL, val_devcfg__XADCIF_MCTL); + +// ************************************************************ +// Module dmac0_ns dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( dmac0_ns__DSR, val_dmac0_ns__DSR); +set_reset_data( dmac0_ns__DPC, val_dmac0_ns__DPC); +set_reset_data( dmac0_ns__INTEN, val_dmac0_ns__INTEN); +set_reset_data( dmac0_ns__INT_EVENT_RIS, val_dmac0_ns__INT_EVENT_RIS); +set_reset_data( dmac0_ns__INTMIS, val_dmac0_ns__INTMIS); +set_reset_data( dmac0_ns__INTCLR, val_dmac0_ns__INTCLR); +set_reset_data( dmac0_ns__FSRD, val_dmac0_ns__FSRD); +set_reset_data( dmac0_ns__FSRC, val_dmac0_ns__FSRC); +set_reset_data( dmac0_ns__FTRD, val_dmac0_ns__FTRD); +set_reset_data( dmac0_ns__FTR0, val_dmac0_ns__FTR0); +set_reset_data( dmac0_ns__FTR1, val_dmac0_ns__FTR1); +set_reset_data( dmac0_ns__FTR2, val_dmac0_ns__FTR2); +set_reset_data( dmac0_ns__FTR3, val_dmac0_ns__FTR3); +set_reset_data( dmac0_ns__FTR4, val_dmac0_ns__FTR4); +set_reset_data( dmac0_ns__FTR5, val_dmac0_ns__FTR5); +set_reset_data( dmac0_ns__FTR6, val_dmac0_ns__FTR6); +set_reset_data( dmac0_ns__FTR7, val_dmac0_ns__FTR7); +set_reset_data( dmac0_ns__CSR0, val_dmac0_ns__CSR0); +set_reset_data( dmac0_ns__CPC0, val_dmac0_ns__CPC0); +set_reset_data( dmac0_ns__CSR1, val_dmac0_ns__CSR1); +set_reset_data( dmac0_ns__CPC1, val_dmac0_ns__CPC1); +set_reset_data( dmac0_ns__CSR2, val_dmac0_ns__CSR2); +set_reset_data( dmac0_ns__CPC2, val_dmac0_ns__CPC2); +set_reset_data( dmac0_ns__CSR3, val_dmac0_ns__CSR3); +set_reset_data( dmac0_ns__CPC3, val_dmac0_ns__CPC3); +set_reset_data( dmac0_ns__CSR4, val_dmac0_ns__CSR4); +set_reset_data( dmac0_ns__CPC4, val_dmac0_ns__CPC4); +set_reset_data( dmac0_ns__CSR5, val_dmac0_ns__CSR5); +set_reset_data( dmac0_ns__CPC5, val_dmac0_ns__CPC5); +set_reset_data( dmac0_ns__CSR6, val_dmac0_ns__CSR6); +set_reset_data( dmac0_ns__CPC6, val_dmac0_ns__CPC6); +set_reset_data( dmac0_ns__CSR7, val_dmac0_ns__CSR7); +set_reset_data( dmac0_ns__CPC7, val_dmac0_ns__CPC7); +set_reset_data( dmac0_ns__SAR0, val_dmac0_ns__SAR0); +set_reset_data( dmac0_ns__DAR0, val_dmac0_ns__DAR0); +set_reset_data( dmac0_ns__CCR0, val_dmac0_ns__CCR0); +set_reset_data( dmac0_ns__LC0_0, val_dmac0_ns__LC0_0); +set_reset_data( dmac0_ns__LC1_0, val_dmac0_ns__LC1_0); +set_reset_data( dmac0_ns__SAR1, val_dmac0_ns__SAR1); +set_reset_data( dmac0_ns__DAR1, val_dmac0_ns__DAR1); +set_reset_data( dmac0_ns__CCR1, val_dmac0_ns__CCR1); +set_reset_data( dmac0_ns__LC0_1, val_dmac0_ns__LC0_1); +set_reset_data( dmac0_ns__LC1_1, val_dmac0_ns__LC1_1); +set_reset_data( dmac0_ns__SAR2, val_dmac0_ns__SAR2); +set_reset_data( dmac0_ns__DAR2, val_dmac0_ns__DAR2); +set_reset_data( dmac0_ns__CCR2, val_dmac0_ns__CCR2); +set_reset_data( dmac0_ns__LC0_2, val_dmac0_ns__LC0_2); +set_reset_data( dmac0_ns__LC1_2, val_dmac0_ns__LC1_2); +set_reset_data( dmac0_ns__SAR3, val_dmac0_ns__SAR3); +set_reset_data( dmac0_ns__DAR3, val_dmac0_ns__DAR3); +set_reset_data( dmac0_ns__CCR3, val_dmac0_ns__CCR3); +set_reset_data( dmac0_ns__LC0_3, val_dmac0_ns__LC0_3); +set_reset_data( dmac0_ns__LC1_3, val_dmac0_ns__LC1_3); +set_reset_data( dmac0_ns__SAR4, val_dmac0_ns__SAR4); +set_reset_data( dmac0_ns__DAR4, val_dmac0_ns__DAR4); +set_reset_data( dmac0_ns__CCR4, val_dmac0_ns__CCR4); +set_reset_data( dmac0_ns__LC0_4, val_dmac0_ns__LC0_4); +set_reset_data( dmac0_ns__LC1_4, val_dmac0_ns__LC1_4); +set_reset_data( dmac0_ns__SAR5, val_dmac0_ns__SAR5); +set_reset_data( dmac0_ns__DAR5, val_dmac0_ns__DAR5); +set_reset_data( dmac0_ns__CCR5, val_dmac0_ns__CCR5); +set_reset_data( dmac0_ns__LC0_5, val_dmac0_ns__LC0_5); +set_reset_data( dmac0_ns__LC1_5, val_dmac0_ns__LC1_5); +set_reset_data( dmac0_ns__SAR6, val_dmac0_ns__SAR6); +set_reset_data( dmac0_ns__DAR6, val_dmac0_ns__DAR6); +set_reset_data( dmac0_ns__CCR6, val_dmac0_ns__CCR6); +set_reset_data( dmac0_ns__LC0_6, val_dmac0_ns__LC0_6); +set_reset_data( dmac0_ns__LC1_6, val_dmac0_ns__LC1_6); +set_reset_data( dmac0_ns__SAR7, val_dmac0_ns__SAR7); +set_reset_data( dmac0_ns__DAR7, val_dmac0_ns__DAR7); +set_reset_data( dmac0_ns__CCR7, val_dmac0_ns__CCR7); +set_reset_data( dmac0_ns__LC0_7, val_dmac0_ns__LC0_7); +set_reset_data( dmac0_ns__LC1_7, val_dmac0_ns__LC1_7); +set_reset_data( dmac0_ns__DBGSTATUS, val_dmac0_ns__DBGSTATUS); +set_reset_data( dmac0_ns__DBGCMD, val_dmac0_ns__DBGCMD); +set_reset_data( dmac0_ns__DBGINST0, val_dmac0_ns__DBGINST0); +set_reset_data( dmac0_ns__DBGINST1, val_dmac0_ns__DBGINST1); +set_reset_data( dmac0_ns__CR0, val_dmac0_ns__CR0); +set_reset_data( dmac0_ns__CR1, val_dmac0_ns__CR1); +set_reset_data( dmac0_ns__CR2, val_dmac0_ns__CR2); +set_reset_data( dmac0_ns__CR3, val_dmac0_ns__CR3); +set_reset_data( dmac0_ns__CR4, val_dmac0_ns__CR4); +set_reset_data( dmac0_ns__CRD, val_dmac0_ns__CRD); +set_reset_data( dmac0_ns__WD, val_dmac0_ns__WD); +set_reset_data( dmac0_ns__periph_id_0, val_dmac0_ns__periph_id_0); +set_reset_data( dmac0_ns__periph_id_1, val_dmac0_ns__periph_id_1); +set_reset_data( dmac0_ns__periph_id_2, val_dmac0_ns__periph_id_2); +set_reset_data( dmac0_ns__periph_id_3, val_dmac0_ns__periph_id_3); +set_reset_data( dmac0_ns__pcell_id_0, val_dmac0_ns__pcell_id_0); +set_reset_data( dmac0_ns__pcell_id_1, val_dmac0_ns__pcell_id_1); +set_reset_data( dmac0_ns__pcell_id_2, val_dmac0_ns__pcell_id_2); +set_reset_data( dmac0_ns__pcell_id_3, val_dmac0_ns__pcell_id_3); + +// ************************************************************ +// Module dmac0_s dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( dmac0_s__DSR, val_dmac0_s__DSR); +set_reset_data( dmac0_s__DPC, val_dmac0_s__DPC); +set_reset_data( dmac0_s__INTEN, val_dmac0_s__INTEN); +set_reset_data( dmac0_s__INT_EVENT_RIS, val_dmac0_s__INT_EVENT_RIS); +set_reset_data( dmac0_s__INTMIS, val_dmac0_s__INTMIS); +set_reset_data( dmac0_s__INTCLR, val_dmac0_s__INTCLR); +set_reset_data( dmac0_s__FSRD, val_dmac0_s__FSRD); +set_reset_data( dmac0_s__FSRC, val_dmac0_s__FSRC); +set_reset_data( dmac0_s__FTRD, val_dmac0_s__FTRD); +set_reset_data( dmac0_s__FTR0, val_dmac0_s__FTR0); +set_reset_data( dmac0_s__FTR1, val_dmac0_s__FTR1); +set_reset_data( dmac0_s__FTR2, val_dmac0_s__FTR2); +set_reset_data( dmac0_s__FTR3, val_dmac0_s__FTR3); +set_reset_data( dmac0_s__FTR4, val_dmac0_s__FTR4); +set_reset_data( dmac0_s__FTR5, val_dmac0_s__FTR5); +set_reset_data( dmac0_s__FTR6, val_dmac0_s__FTR6); +set_reset_data( dmac0_s__FTR7, val_dmac0_s__FTR7); +set_reset_data( dmac0_s__CSR0, val_dmac0_s__CSR0); +set_reset_data( dmac0_s__CPC0, val_dmac0_s__CPC0); +set_reset_data( dmac0_s__CSR1, val_dmac0_s__CSR1); +set_reset_data( dmac0_s__CPC1, val_dmac0_s__CPC1); +set_reset_data( dmac0_s__CSR2, val_dmac0_s__CSR2); +set_reset_data( dmac0_s__CPC2, val_dmac0_s__CPC2); +set_reset_data( dmac0_s__CSR3, val_dmac0_s__CSR3); +set_reset_data( dmac0_s__CPC3, val_dmac0_s__CPC3); +set_reset_data( dmac0_s__CSR4, val_dmac0_s__CSR4); +set_reset_data( dmac0_s__CPC4, val_dmac0_s__CPC4); +set_reset_data( dmac0_s__CSR5, val_dmac0_s__CSR5); +set_reset_data( dmac0_s__CPC5, val_dmac0_s__CPC5); +set_reset_data( dmac0_s__CSR6, val_dmac0_s__CSR6); +set_reset_data( dmac0_s__CPC6, val_dmac0_s__CPC6); +set_reset_data( dmac0_s__CSR7, val_dmac0_s__CSR7); +set_reset_data( dmac0_s__CPC7, val_dmac0_s__CPC7); +set_reset_data( dmac0_s__SAR0, val_dmac0_s__SAR0); +set_reset_data( dmac0_s__DAR0, val_dmac0_s__DAR0); +set_reset_data( dmac0_s__CCR0, val_dmac0_s__CCR0); +set_reset_data( dmac0_s__LC0_0, val_dmac0_s__LC0_0); +set_reset_data( dmac0_s__LC1_0, val_dmac0_s__LC1_0); +set_reset_data( dmac0_s__SAR1, val_dmac0_s__SAR1); +set_reset_data( dmac0_s__DAR1, val_dmac0_s__DAR1); +set_reset_data( dmac0_s__CCR1, val_dmac0_s__CCR1); +set_reset_data( dmac0_s__LC0_1, val_dmac0_s__LC0_1); +set_reset_data( dmac0_s__LC1_1, val_dmac0_s__LC1_1); +set_reset_data( dmac0_s__SAR2, val_dmac0_s__SAR2); +set_reset_data( dmac0_s__DAR2, val_dmac0_s__DAR2); +set_reset_data( dmac0_s__CCR2, val_dmac0_s__CCR2); +set_reset_data( dmac0_s__LC0_2, val_dmac0_s__LC0_2); +set_reset_data( dmac0_s__LC1_2, val_dmac0_s__LC1_2); +set_reset_data( dmac0_s__SAR3, val_dmac0_s__SAR3); +set_reset_data( dmac0_s__DAR3, val_dmac0_s__DAR3); +set_reset_data( dmac0_s__CCR3, val_dmac0_s__CCR3); +set_reset_data( dmac0_s__LC0_3, val_dmac0_s__LC0_3); +set_reset_data( dmac0_s__LC1_3, val_dmac0_s__LC1_3); +set_reset_data( dmac0_s__SAR4, val_dmac0_s__SAR4); +set_reset_data( dmac0_s__DAR4, val_dmac0_s__DAR4); +set_reset_data( dmac0_s__CCR4, val_dmac0_s__CCR4); +set_reset_data( dmac0_s__LC0_4, val_dmac0_s__LC0_4); +set_reset_data( dmac0_s__LC1_4, val_dmac0_s__LC1_4); +set_reset_data( dmac0_s__SAR5, val_dmac0_s__SAR5); +set_reset_data( dmac0_s__DAR5, val_dmac0_s__DAR5); +set_reset_data( dmac0_s__CCR5, val_dmac0_s__CCR5); +set_reset_data( dmac0_s__LC0_5, val_dmac0_s__LC0_5); +set_reset_data( dmac0_s__LC1_5, val_dmac0_s__LC1_5); +set_reset_data( dmac0_s__SAR6, val_dmac0_s__SAR6); +set_reset_data( dmac0_s__DAR6, val_dmac0_s__DAR6); +set_reset_data( dmac0_s__CCR6, val_dmac0_s__CCR6); +set_reset_data( dmac0_s__LC0_6, val_dmac0_s__LC0_6); +set_reset_data( dmac0_s__LC1_6, val_dmac0_s__LC1_6); +set_reset_data( dmac0_s__SAR7, val_dmac0_s__SAR7); +set_reset_data( dmac0_s__DAR7, val_dmac0_s__DAR7); +set_reset_data( dmac0_s__CCR7, val_dmac0_s__CCR7); +set_reset_data( dmac0_s__LC0_7, val_dmac0_s__LC0_7); +set_reset_data( dmac0_s__LC1_7, val_dmac0_s__LC1_7); +set_reset_data( dmac0_s__DBGSTATUS, val_dmac0_s__DBGSTATUS); +set_reset_data( dmac0_s__DBGCMD, val_dmac0_s__DBGCMD); +set_reset_data( dmac0_s__DBGINST0, val_dmac0_s__DBGINST0); +set_reset_data( dmac0_s__DBGINST1, val_dmac0_s__DBGINST1); +set_reset_data( dmac0_s__CR0, val_dmac0_s__CR0); +set_reset_data( dmac0_s__CR1, val_dmac0_s__CR1); +set_reset_data( dmac0_s__CR2, val_dmac0_s__CR2); +set_reset_data( dmac0_s__CR3, val_dmac0_s__CR3); +set_reset_data( dmac0_s__CR4, val_dmac0_s__CR4); +set_reset_data( dmac0_s__CRD, val_dmac0_s__CRD); +set_reset_data( dmac0_s__WD, val_dmac0_s__WD); +set_reset_data( dmac0_s__periph_id_0, val_dmac0_s__periph_id_0); +set_reset_data( dmac0_s__periph_id_1, val_dmac0_s__periph_id_1); +set_reset_data( dmac0_s__periph_id_2, val_dmac0_s__periph_id_2); +set_reset_data( dmac0_s__periph_id_3, val_dmac0_s__periph_id_3); +set_reset_data( dmac0_s__pcell_id_0, val_dmac0_s__pcell_id_0); +set_reset_data( dmac0_s__pcell_id_1, val_dmac0_s__pcell_id_1); +set_reset_data( dmac0_s__pcell_id_2, val_dmac0_s__pcell_id_2); +set_reset_data( dmac0_s__pcell_id_3, val_dmac0_s__pcell_id_3); + +// ************************************************************ +// Module efuse_ctrl efuse_ctrl +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( efuse_ctrl__WR_LOCK, val_efuse_ctrl__WR_LOCK); +set_reset_data( efuse_ctrl__WR_UNLOCK, val_efuse_ctrl__WR_UNLOCK); +set_reset_data( efuse_ctrl__WR_LOCKSTA, val_efuse_ctrl__WR_LOCKSTA); +set_reset_data( efuse_ctrl__CFG, val_efuse_ctrl__CFG); +set_reset_data( efuse_ctrl__STATUS, val_efuse_ctrl__STATUS); +set_reset_data( efuse_ctrl__CONTROL, val_efuse_ctrl__CONTROL); +set_reset_data( efuse_ctrl__PGM_STBW, val_efuse_ctrl__PGM_STBW); +set_reset_data( efuse_ctrl__RD_STBW, val_efuse_ctrl__RD_STBW); + +// ************************************************************ +// Module gem0 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gem0__net_ctrl, val_gem0__net_ctrl); +set_reset_data( gem0__net_cfg, val_gem0__net_cfg); +set_reset_data( gem0__net_status, val_gem0__net_status); +set_reset_data( gem0__user_io, val_gem0__user_io); +set_reset_data( gem0__dma_cfg, val_gem0__dma_cfg); +set_reset_data( gem0__tx_status, val_gem0__tx_status); +set_reset_data( gem0__rx_qbar, val_gem0__rx_qbar); +set_reset_data( gem0__tx_qbar, val_gem0__tx_qbar); +set_reset_data( gem0__rx_status, val_gem0__rx_status); +set_reset_data( gem0__intr_status, val_gem0__intr_status); +set_reset_data( gem0__intr_en, val_gem0__intr_en); +set_reset_data( gem0__intr_dis, val_gem0__intr_dis); +set_reset_data( gem0__intr_mask, val_gem0__intr_mask); +set_reset_data( gem0__phy_maint, val_gem0__phy_maint); +set_reset_data( gem0__rx_pauseq, val_gem0__rx_pauseq); +set_reset_data( gem0__tx_pauseq, val_gem0__tx_pauseq); +set_reset_data( gem0__tx_partial_st_fwd, val_gem0__tx_partial_st_fwd); +set_reset_data( gem0__rx_partial_st_fwd, val_gem0__rx_partial_st_fwd); +set_reset_data( gem0__hash_bot, val_gem0__hash_bot); +set_reset_data( gem0__hash_top, val_gem0__hash_top); +set_reset_data( gem0__spec_addr1_bot, val_gem0__spec_addr1_bot); +set_reset_data( gem0__spec_addr1_top, val_gem0__spec_addr1_top); +set_reset_data( gem0__spec_addr2_bot, val_gem0__spec_addr2_bot); +set_reset_data( gem0__spec_addr2_top, val_gem0__spec_addr2_top); +set_reset_data( gem0__spec_addr3_bot, val_gem0__spec_addr3_bot); +set_reset_data( gem0__spec_addr3_top, val_gem0__spec_addr3_top); +set_reset_data( gem0__spec_addr4_bot, val_gem0__spec_addr4_bot); +set_reset_data( gem0__spec_addr4_top, val_gem0__spec_addr4_top); +set_reset_data( gem0__type_id_match1, val_gem0__type_id_match1); +set_reset_data( gem0__type_id_match2, val_gem0__type_id_match2); +set_reset_data( gem0__type_id_match3, val_gem0__type_id_match3); +set_reset_data( gem0__type_id_match4, val_gem0__type_id_match4); +set_reset_data( gem0__wake_on_lan, val_gem0__wake_on_lan); +set_reset_data( gem0__ipg_stretch, val_gem0__ipg_stretch); +set_reset_data( gem0__stacked_vlan, val_gem0__stacked_vlan); +set_reset_data( gem0__tx_pfc_pause, val_gem0__tx_pfc_pause); +set_reset_data( gem0__spec_addr1_mask_bot, val_gem0__spec_addr1_mask_bot); +set_reset_data( gem0__spec_addr1_mask_top, val_gem0__spec_addr1_mask_top); +set_reset_data( gem0__module_id, val_gem0__module_id); +set_reset_data( gem0__octets_tx_bot, val_gem0__octets_tx_bot); +set_reset_data( gem0__octets_tx_top, val_gem0__octets_tx_top); +set_reset_data( gem0__frames_tx, val_gem0__frames_tx); +set_reset_data( gem0__broadcast_frames_tx, val_gem0__broadcast_frames_tx); +set_reset_data( gem0__multi_frames_tx, val_gem0__multi_frames_tx); +set_reset_data( gem0__pause_frames_tx, val_gem0__pause_frames_tx); +set_reset_data( gem0__frames_64b_tx, val_gem0__frames_64b_tx); +set_reset_data( gem0__frames_65to127b_tx, val_gem0__frames_65to127b_tx); +set_reset_data( gem0__frames_128to255b_tx, val_gem0__frames_128to255b_tx); +set_reset_data( gem0__frames_256to511b_tx, val_gem0__frames_256to511b_tx); +set_reset_data( gem0__frames_512to1023b_tx, val_gem0__frames_512to1023b_tx); +set_reset_data( gem0__frames_1024to1518b_tx, val_gem0__frames_1024to1518b_tx); +set_reset_data( gem0__frames_gt1518b_tx, val_gem0__frames_gt1518b_tx); +set_reset_data( gem0__tx_under_runs, val_gem0__tx_under_runs); +set_reset_data( gem0__single_collisn_frames, val_gem0__single_collisn_frames); +set_reset_data( gem0__multi_collisn_frames, val_gem0__multi_collisn_frames); +set_reset_data( gem0__excessive_collisns, val_gem0__excessive_collisns); +set_reset_data( gem0__late_collisns, val_gem0__late_collisns); +set_reset_data( gem0__deferred_tx_frames, val_gem0__deferred_tx_frames); +set_reset_data( gem0__carrier_sense_errs, val_gem0__carrier_sense_errs); +set_reset_data( gem0__octets_rx_bot, val_gem0__octets_rx_bot); +set_reset_data( gem0__octets_rx_top, val_gem0__octets_rx_top); +set_reset_data( gem0__frames_rx, val_gem0__frames_rx); +set_reset_data( gem0__bdcast_fames_rx, val_gem0__bdcast_fames_rx); +set_reset_data( gem0__multi_frames_rx, val_gem0__multi_frames_rx); +set_reset_data( gem0__pause_rx, val_gem0__pause_rx); +set_reset_data( gem0__frames_64b_rx, val_gem0__frames_64b_rx); +set_reset_data( gem0__frames_65to127b_rx, val_gem0__frames_65to127b_rx); +set_reset_data( gem0__frames_128to255b_rx, val_gem0__frames_128to255b_rx); +set_reset_data( gem0__frames_256to511b_rx, val_gem0__frames_256to511b_rx); +set_reset_data( gem0__frames_512to1023b_rx, val_gem0__frames_512to1023b_rx); +set_reset_data( gem0__frames_1024to1518b_rx, val_gem0__frames_1024to1518b_rx); +set_reset_data( gem0__frames_gt1518b_rx, val_gem0__frames_gt1518b_rx); +set_reset_data( gem0__undersz_rx, val_gem0__undersz_rx); +set_reset_data( gem0__oversz_rx, val_gem0__oversz_rx); +set_reset_data( gem0__jab_rx, val_gem0__jab_rx); +set_reset_data( gem0__fcs_errors, val_gem0__fcs_errors); +set_reset_data( gem0__length_field_errors, val_gem0__length_field_errors); +set_reset_data( gem0__rx_symbol_errors, val_gem0__rx_symbol_errors); +set_reset_data( gem0__align_errors, val_gem0__align_errors); +set_reset_data( gem0__rx_resource_errors, val_gem0__rx_resource_errors); +set_reset_data( gem0__rx_overrun_errors, val_gem0__rx_overrun_errors); +set_reset_data( gem0__ip_hdr_csum_errors, val_gem0__ip_hdr_csum_errors); +set_reset_data( gem0__tcp_csum_errors, val_gem0__tcp_csum_errors); +set_reset_data( gem0__udp_csum_errors, val_gem0__udp_csum_errors); +set_reset_data( gem0__timer_strobe_s, val_gem0__timer_strobe_s); +set_reset_data( gem0__timer_strobe_ns, val_gem0__timer_strobe_ns); +set_reset_data( gem0__timer_s, val_gem0__timer_s); +set_reset_data( gem0__timer_ns, val_gem0__timer_ns); +set_reset_data( gem0__timer_adjust, val_gem0__timer_adjust); +set_reset_data( gem0__timer_incr, val_gem0__timer_incr); +set_reset_data( gem0__ptp_tx_s, val_gem0__ptp_tx_s); +set_reset_data( gem0__ptp_tx_ns, val_gem0__ptp_tx_ns); +set_reset_data( gem0__ptp_rx_s, val_gem0__ptp_rx_s); +set_reset_data( gem0__ptp_rx_ns, val_gem0__ptp_rx_ns); +set_reset_data( gem0__ptp_peer_tx_s, val_gem0__ptp_peer_tx_s); +set_reset_data( gem0__ptp_peer_tx_ns, val_gem0__ptp_peer_tx_ns); +set_reset_data( gem0__ptp_peer_rx_s, val_gem0__ptp_peer_rx_s); +set_reset_data( gem0__ptp_peer_rx_ns, val_gem0__ptp_peer_rx_ns); +set_reset_data( gem0__pcs_ctrl, val_gem0__pcs_ctrl); +set_reset_data( gem0__pcs_status, val_gem0__pcs_status); +set_reset_data( gem0__pcs_upper_phy_id, val_gem0__pcs_upper_phy_id); +set_reset_data( gem0__pcs_lower_phy_id, val_gem0__pcs_lower_phy_id); +set_reset_data( gem0__pcs_autoneg_ad, val_gem0__pcs_autoneg_ad); +set_reset_data( gem0__pcs_autoneg_ability, val_gem0__pcs_autoneg_ability); +set_reset_data( gem0__pcs_autonec_exp, val_gem0__pcs_autonec_exp); +set_reset_data( gem0__pcs_autoneg_next_pg, val_gem0__pcs_autoneg_next_pg); +set_reset_data( gem0__pcs_autoneg_pnext_pg, val_gem0__pcs_autoneg_pnext_pg); +set_reset_data( gem0__pcs_extended_status, val_gem0__pcs_extended_status); +set_reset_data( gem0__design_cfg1, val_gem0__design_cfg1); +set_reset_data( gem0__design_cfg2, val_gem0__design_cfg2); +set_reset_data( gem0__design_cfg3, val_gem0__design_cfg3); +set_reset_data( gem0__design_cfg4, val_gem0__design_cfg4); +set_reset_data( gem0__design_cfg5, val_gem0__design_cfg5); +set_reset_data( gem0__design_cfg6, val_gem0__design_cfg6); +set_reset_data( gem0__design_cfg7, val_gem0__design_cfg7); +set_reset_data( gem0__isr_pq1, val_gem0__isr_pq1); +set_reset_data( gem0__isr_pq2, val_gem0__isr_pq2); +set_reset_data( gem0__isr_pq3, val_gem0__isr_pq3); +set_reset_data( gem0__isr_pq4, val_gem0__isr_pq4); +set_reset_data( gem0__isr_pq5, val_gem0__isr_pq5); +set_reset_data( gem0__isr_pq6, val_gem0__isr_pq6); +set_reset_data( gem0__isr_pq7, val_gem0__isr_pq7); +set_reset_data( gem0__tx_qbar_q1, val_gem0__tx_qbar_q1); +set_reset_data( gem0__tx_qbar_q2, val_gem0__tx_qbar_q2); +set_reset_data( gem0__tx_qbar_q3, val_gem0__tx_qbar_q3); +set_reset_data( gem0__tx_qbar_q4, val_gem0__tx_qbar_q4); +set_reset_data( gem0__tx_qbar_q5, val_gem0__tx_qbar_q5); +set_reset_data( gem0__tx_qbar_q6, val_gem0__tx_qbar_q6); +set_reset_data( gem0__tx_qbar_q7, val_gem0__tx_qbar_q7); +set_reset_data( gem0__rx_qbar_q1, val_gem0__rx_qbar_q1); +set_reset_data( gem0__rx_qbar_q2, val_gem0__rx_qbar_q2); +set_reset_data( gem0__rx_qbar_q3, val_gem0__rx_qbar_q3); +set_reset_data( gem0__rx_qbar_q4, val_gem0__rx_qbar_q4); +set_reset_data( gem0__rx_qbar_q5, val_gem0__rx_qbar_q5); +set_reset_data( gem0__rx_qbar_q6, val_gem0__rx_qbar_q6); +set_reset_data( gem0__rx_qbar_q7, val_gem0__rx_qbar_q7); +set_reset_data( gem0__rx_bufsz_q1, val_gem0__rx_bufsz_q1); +set_reset_data( gem0__rx_bufsz_q2, val_gem0__rx_bufsz_q2); +set_reset_data( gem0__rx_bufsz_q3, val_gem0__rx_bufsz_q3); +set_reset_data( gem0__rx_bufsz_q4, val_gem0__rx_bufsz_q4); +set_reset_data( gem0__rx_bufsz_q5, val_gem0__rx_bufsz_q5); +set_reset_data( gem0__rx_bufsz_q6, val_gem0__rx_bufsz_q6); +set_reset_data( gem0__rx_bufsz_q7, val_gem0__rx_bufsz_q7); +set_reset_data( gem0__screen_t1_r0, val_gem0__screen_t1_r0); +set_reset_data( gem0__screen_t1_r1, val_gem0__screen_t1_r1); +set_reset_data( gem0__screen_t1_r2, val_gem0__screen_t1_r2); +set_reset_data( gem0__screen_t1_r3, val_gem0__screen_t1_r3); +set_reset_data( gem0__screen_t1_r4, val_gem0__screen_t1_r4); +set_reset_data( gem0__screen_t1_r5, val_gem0__screen_t1_r5); +set_reset_data( gem0__screen_t1_r6, val_gem0__screen_t1_r6); +set_reset_data( gem0__screen_t1_r7, val_gem0__screen_t1_r7); +set_reset_data( gem0__screen_t1_r8, val_gem0__screen_t1_r8); +set_reset_data( gem0__screen_t1_r9, val_gem0__screen_t1_r9); +set_reset_data( gem0__screen_t1_r10, val_gem0__screen_t1_r10); +set_reset_data( gem0__screen_t1_r11, val_gem0__screen_t1_r11); +set_reset_data( gem0__screen_t1_r12, val_gem0__screen_t1_r12); +set_reset_data( gem0__screen_t1_r13, val_gem0__screen_t1_r13); +set_reset_data( gem0__screen_t1_r14, val_gem0__screen_t1_r14); +set_reset_data( gem0__screen_t1_r15, val_gem0__screen_t1_r15); +set_reset_data( gem0__screen_t2_r0, val_gem0__screen_t2_r0); +set_reset_data( gem0__screen_t2_r1, val_gem0__screen_t2_r1); +set_reset_data( gem0__screen_t2_r2, val_gem0__screen_t2_r2); +set_reset_data( gem0__screen_t2_r3, val_gem0__screen_t2_r3); +set_reset_data( gem0__screen_t2_r4, val_gem0__screen_t2_r4); +set_reset_data( gem0__screen_t2_r5, val_gem0__screen_t2_r5); +set_reset_data( gem0__screen_t2_r6, val_gem0__screen_t2_r6); +set_reset_data( gem0__screen_t2_r7, val_gem0__screen_t2_r7); +set_reset_data( gem0__screen_t2_r8, val_gem0__screen_t2_r8); +set_reset_data( gem0__screen_t2_r9, val_gem0__screen_t2_r9); +set_reset_data( gem0__screen_t2_r10, val_gem0__screen_t2_r10); +set_reset_data( gem0__screen_t2_r11, val_gem0__screen_t2_r11); +set_reset_data( gem0__screen_t2_r12, val_gem0__screen_t2_r12); +set_reset_data( gem0__screen_t2_r13, val_gem0__screen_t2_r13); +set_reset_data( gem0__screen_t2_r14, val_gem0__screen_t2_r14); +set_reset_data( gem0__screen_t2_r15, val_gem0__screen_t2_r15); +set_reset_data( gem0__intr_en_pq1, val_gem0__intr_en_pq1); +set_reset_data( gem0__intr_en_pq2, val_gem0__intr_en_pq2); +set_reset_data( gem0__intr_en_pq3, val_gem0__intr_en_pq3); +set_reset_data( gem0__intr_en_pq4, val_gem0__intr_en_pq4); +set_reset_data( gem0__intr_en_pq5, val_gem0__intr_en_pq5); +set_reset_data( gem0__intr_en_pq6, val_gem0__intr_en_pq6); +set_reset_data( gem0__intr_en_pq7, val_gem0__intr_en_pq7); +set_reset_data( gem0__intr_dis_pq1, val_gem0__intr_dis_pq1); +set_reset_data( gem0__intr_dis_pq2, val_gem0__intr_dis_pq2); +set_reset_data( gem0__intr_dis_pq3, val_gem0__intr_dis_pq3); +set_reset_data( gem0__intr_dis_pq4, val_gem0__intr_dis_pq4); +set_reset_data( gem0__intr_dis_pq5, val_gem0__intr_dis_pq5); +set_reset_data( gem0__intr_dis_pq6, val_gem0__intr_dis_pq6); +set_reset_data( gem0__intr_dis_pq7, val_gem0__intr_dis_pq7); +set_reset_data( gem0__intr_mask_pq1, val_gem0__intr_mask_pq1); +set_reset_data( gem0__intr_mask_pq2, val_gem0__intr_mask_pq2); +set_reset_data( gem0__intr_mask_pq3, val_gem0__intr_mask_pq3); +set_reset_data( gem0__intr_mask_pq4, val_gem0__intr_mask_pq4); +set_reset_data( gem0__intr_mask_pq5, val_gem0__intr_mask_pq5); +set_reset_data( gem0__intr_mask_pq6, val_gem0__intr_mask_pq6); +set_reset_data( gem0__intr_mask_pq7, val_gem0__intr_mask_pq7); + +// ************************************************************ +// Module gem1 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gem1__net_ctrl, val_gem1__net_ctrl); +set_reset_data( gem1__net_cfg, val_gem1__net_cfg); +set_reset_data( gem1__net_status, val_gem1__net_status); +set_reset_data( gem1__user_io, val_gem1__user_io); +set_reset_data( gem1__dma_cfg, val_gem1__dma_cfg); +set_reset_data( gem1__tx_status, val_gem1__tx_status); +set_reset_data( gem1__rx_qbar, val_gem1__rx_qbar); +set_reset_data( gem1__tx_qbar, val_gem1__tx_qbar); +set_reset_data( gem1__rx_status, val_gem1__rx_status); +set_reset_data( gem1__intr_status, val_gem1__intr_status); +set_reset_data( gem1__intr_en, val_gem1__intr_en); +set_reset_data( gem1__intr_dis, val_gem1__intr_dis); +set_reset_data( gem1__intr_mask, val_gem1__intr_mask); +set_reset_data( gem1__phy_maint, val_gem1__phy_maint); +set_reset_data( gem1__rx_pauseq, val_gem1__rx_pauseq); +set_reset_data( gem1__tx_pauseq, val_gem1__tx_pauseq); +set_reset_data( gem1__tx_partial_st_fwd, val_gem1__tx_partial_st_fwd); +set_reset_data( gem1__rx_partial_st_fwd, val_gem1__rx_partial_st_fwd); +set_reset_data( gem1__hash_bot, val_gem1__hash_bot); +set_reset_data( gem1__hash_top, val_gem1__hash_top); +set_reset_data( gem1__spec_addr1_bot, val_gem1__spec_addr1_bot); +set_reset_data( gem1__spec_addr1_top, val_gem1__spec_addr1_top); +set_reset_data( gem1__spec_addr2_bot, val_gem1__spec_addr2_bot); +set_reset_data( gem1__spec_addr2_top, val_gem1__spec_addr2_top); +set_reset_data( gem1__spec_addr3_bot, val_gem1__spec_addr3_bot); +set_reset_data( gem1__spec_addr3_top, val_gem1__spec_addr3_top); +set_reset_data( gem1__spec_addr4_bot, val_gem1__spec_addr4_bot); +set_reset_data( gem1__spec_addr4_top, val_gem1__spec_addr4_top); +set_reset_data( gem1__type_id_match1, val_gem1__type_id_match1); +set_reset_data( gem1__type_id_match2, val_gem1__type_id_match2); +set_reset_data( gem1__type_id_match3, val_gem1__type_id_match3); +set_reset_data( gem1__type_id_match4, val_gem1__type_id_match4); +set_reset_data( gem1__wake_on_lan, val_gem1__wake_on_lan); +set_reset_data( gem1__ipg_stretch, val_gem1__ipg_stretch); +set_reset_data( gem1__stacked_vlan, val_gem1__stacked_vlan); +set_reset_data( gem1__tx_pfc_pause, val_gem1__tx_pfc_pause); +set_reset_data( gem1__spec_addr1_mask_bot, val_gem1__spec_addr1_mask_bot); +set_reset_data( gem1__spec_addr1_mask_top, val_gem1__spec_addr1_mask_top); +set_reset_data( gem1__module_id, val_gem1__module_id); +set_reset_data( gem1__octets_tx_bot, val_gem1__octets_tx_bot); +set_reset_data( gem1__octets_tx_top, val_gem1__octets_tx_top); +set_reset_data( gem1__frames_tx, val_gem1__frames_tx); +set_reset_data( gem1__broadcast_frames_tx, val_gem1__broadcast_frames_tx); +set_reset_data( gem1__multi_frames_tx, val_gem1__multi_frames_tx); +set_reset_data( gem1__pause_frames_tx, val_gem1__pause_frames_tx); +set_reset_data( gem1__frames_64b_tx, val_gem1__frames_64b_tx); +set_reset_data( gem1__frames_65to127b_tx, val_gem1__frames_65to127b_tx); +set_reset_data( gem1__frames_128to255b_tx, val_gem1__frames_128to255b_tx); +set_reset_data( gem1__frames_256to511b_tx, val_gem1__frames_256to511b_tx); +set_reset_data( gem1__frames_512to1023b_tx, val_gem1__frames_512to1023b_tx); +set_reset_data( gem1__frames_1024to1518b_tx, val_gem1__frames_1024to1518b_tx); +set_reset_data( gem1__frames_gt1518b_tx, val_gem1__frames_gt1518b_tx); +set_reset_data( gem1__tx_under_runs, val_gem1__tx_under_runs); +set_reset_data( gem1__single_collisn_frames, val_gem1__single_collisn_frames); +set_reset_data( gem1__multi_collisn_frames, val_gem1__multi_collisn_frames); +set_reset_data( gem1__excessive_collisns, val_gem1__excessive_collisns); +set_reset_data( gem1__late_collisns, val_gem1__late_collisns); +set_reset_data( gem1__deferred_tx_frames, val_gem1__deferred_tx_frames); +set_reset_data( gem1__carrier_sense_errs, val_gem1__carrier_sense_errs); +set_reset_data( gem1__octets_rx_bot, val_gem1__octets_rx_bot); +set_reset_data( gem1__octets_rx_top, val_gem1__octets_rx_top); +set_reset_data( gem1__frames_rx, val_gem1__frames_rx); +set_reset_data( gem1__bdcast_fames_rx, val_gem1__bdcast_fames_rx); +set_reset_data( gem1__multi_frames_rx, val_gem1__multi_frames_rx); +set_reset_data( gem1__pause_rx, val_gem1__pause_rx); +set_reset_data( gem1__frames_64b_rx, val_gem1__frames_64b_rx); +set_reset_data( gem1__frames_65to127b_rx, val_gem1__frames_65to127b_rx); +set_reset_data( gem1__frames_128to255b_rx, val_gem1__frames_128to255b_rx); +set_reset_data( gem1__frames_256to511b_rx, val_gem1__frames_256to511b_rx); +set_reset_data( gem1__frames_512to1023b_rx, val_gem1__frames_512to1023b_rx); +set_reset_data( gem1__frames_1024to1518b_rx, val_gem1__frames_1024to1518b_rx); +set_reset_data( gem1__frames_gt1518b_rx, val_gem1__frames_gt1518b_rx); +set_reset_data( gem1__undersz_rx, val_gem1__undersz_rx); +set_reset_data( gem1__oversz_rx, val_gem1__oversz_rx); +set_reset_data( gem1__jab_rx, val_gem1__jab_rx); +set_reset_data( gem1__fcs_errors, val_gem1__fcs_errors); +set_reset_data( gem1__length_field_errors, val_gem1__length_field_errors); +set_reset_data( gem1__rx_symbol_errors, val_gem1__rx_symbol_errors); +set_reset_data( gem1__align_errors, val_gem1__align_errors); +set_reset_data( gem1__rx_resource_errors, val_gem1__rx_resource_errors); +set_reset_data( gem1__rx_overrun_errors, val_gem1__rx_overrun_errors); +set_reset_data( gem1__ip_hdr_csum_errors, val_gem1__ip_hdr_csum_errors); +set_reset_data( gem1__tcp_csum_errors, val_gem1__tcp_csum_errors); +set_reset_data( gem1__udp_csum_errors, val_gem1__udp_csum_errors); +set_reset_data( gem1__timer_strobe_s, val_gem1__timer_strobe_s); +set_reset_data( gem1__timer_strobe_ns, val_gem1__timer_strobe_ns); +set_reset_data( gem1__timer_s, val_gem1__timer_s); +set_reset_data( gem1__timer_ns, val_gem1__timer_ns); +set_reset_data( gem1__timer_adjust, val_gem1__timer_adjust); +set_reset_data( gem1__timer_incr, val_gem1__timer_incr); +set_reset_data( gem1__ptp_tx_s, val_gem1__ptp_tx_s); +set_reset_data( gem1__ptp_tx_ns, val_gem1__ptp_tx_ns); +set_reset_data( gem1__ptp_rx_s, val_gem1__ptp_rx_s); +set_reset_data( gem1__ptp_rx_ns, val_gem1__ptp_rx_ns); +set_reset_data( gem1__ptp_peer_tx_s, val_gem1__ptp_peer_tx_s); +set_reset_data( gem1__ptp_peer_tx_ns, val_gem1__ptp_peer_tx_ns); +set_reset_data( gem1__ptp_peer_rx_s, val_gem1__ptp_peer_rx_s); +set_reset_data( gem1__ptp_peer_rx_ns, val_gem1__ptp_peer_rx_ns); +set_reset_data( gem1__pcs_ctrl, val_gem1__pcs_ctrl); +set_reset_data( gem1__pcs_status, val_gem1__pcs_status); +set_reset_data( gem1__pcs_upper_phy_id, val_gem1__pcs_upper_phy_id); +set_reset_data( gem1__pcs_lower_phy_id, val_gem1__pcs_lower_phy_id); +set_reset_data( gem1__pcs_autoneg_ad, val_gem1__pcs_autoneg_ad); +set_reset_data( gem1__pcs_autoneg_ability, val_gem1__pcs_autoneg_ability); +set_reset_data( gem1__pcs_autonec_exp, val_gem1__pcs_autonec_exp); +set_reset_data( gem1__pcs_autoneg_next_pg, val_gem1__pcs_autoneg_next_pg); +set_reset_data( gem1__pcs_autoneg_pnext_pg, val_gem1__pcs_autoneg_pnext_pg); +set_reset_data( gem1__pcs_extended_status, val_gem1__pcs_extended_status); +set_reset_data( gem1__design_cfg1, val_gem1__design_cfg1); +set_reset_data( gem1__design_cfg2, val_gem1__design_cfg2); +set_reset_data( gem1__design_cfg3, val_gem1__design_cfg3); +set_reset_data( gem1__design_cfg4, val_gem1__design_cfg4); +set_reset_data( gem1__design_cfg5, val_gem1__design_cfg5); +set_reset_data( gem1__design_cfg6, val_gem1__design_cfg6); +set_reset_data( gem1__design_cfg7, val_gem1__design_cfg7); +set_reset_data( gem1__isr_pq1, val_gem1__isr_pq1); +set_reset_data( gem1__isr_pq2, val_gem1__isr_pq2); +set_reset_data( gem1__isr_pq3, val_gem1__isr_pq3); +set_reset_data( gem1__isr_pq4, val_gem1__isr_pq4); +set_reset_data( gem1__isr_pq5, val_gem1__isr_pq5); +set_reset_data( gem1__isr_pq6, val_gem1__isr_pq6); +set_reset_data( gem1__isr_pq7, val_gem1__isr_pq7); +set_reset_data( gem1__tx_qbar_q1, val_gem1__tx_qbar_q1); +set_reset_data( gem1__tx_qbar_q2, val_gem1__tx_qbar_q2); +set_reset_data( gem1__tx_qbar_q3, val_gem1__tx_qbar_q3); +set_reset_data( gem1__tx_qbar_q4, val_gem1__tx_qbar_q4); +set_reset_data( gem1__tx_qbar_q5, val_gem1__tx_qbar_q5); +set_reset_data( gem1__tx_qbar_q6, val_gem1__tx_qbar_q6); +set_reset_data( gem1__tx_qbar_q7, val_gem1__tx_qbar_q7); +set_reset_data( gem1__rx_qbar_q1, val_gem1__rx_qbar_q1); +set_reset_data( gem1__rx_qbar_q2, val_gem1__rx_qbar_q2); +set_reset_data( gem1__rx_qbar_q3, val_gem1__rx_qbar_q3); +set_reset_data( gem1__rx_qbar_q4, val_gem1__rx_qbar_q4); +set_reset_data( gem1__rx_qbar_q5, val_gem1__rx_qbar_q5); +set_reset_data( gem1__rx_qbar_q6, val_gem1__rx_qbar_q6); +set_reset_data( gem1__rx_qbar_q7, val_gem1__rx_qbar_q7); +set_reset_data( gem1__rx_bufsz_q1, val_gem1__rx_bufsz_q1); +set_reset_data( gem1__rx_bufsz_q2, val_gem1__rx_bufsz_q2); +set_reset_data( gem1__rx_bufsz_q3, val_gem1__rx_bufsz_q3); +set_reset_data( gem1__rx_bufsz_q4, val_gem1__rx_bufsz_q4); +set_reset_data( gem1__rx_bufsz_q5, val_gem1__rx_bufsz_q5); +set_reset_data( gem1__rx_bufsz_q6, val_gem1__rx_bufsz_q6); +set_reset_data( gem1__rx_bufsz_q7, val_gem1__rx_bufsz_q7); +set_reset_data( gem1__screen_t1_r0, val_gem1__screen_t1_r0); +set_reset_data( gem1__screen_t1_r1, val_gem1__screen_t1_r1); +set_reset_data( gem1__screen_t1_r2, val_gem1__screen_t1_r2); +set_reset_data( gem1__screen_t1_r3, val_gem1__screen_t1_r3); +set_reset_data( gem1__screen_t1_r4, val_gem1__screen_t1_r4); +set_reset_data( gem1__screen_t1_r5, val_gem1__screen_t1_r5); +set_reset_data( gem1__screen_t1_r6, val_gem1__screen_t1_r6); +set_reset_data( gem1__screen_t1_r7, val_gem1__screen_t1_r7); +set_reset_data( gem1__screen_t1_r8, val_gem1__screen_t1_r8); +set_reset_data( gem1__screen_t1_r9, val_gem1__screen_t1_r9); +set_reset_data( gem1__screen_t1_r10, val_gem1__screen_t1_r10); +set_reset_data( gem1__screen_t1_r11, val_gem1__screen_t1_r11); +set_reset_data( gem1__screen_t1_r12, val_gem1__screen_t1_r12); +set_reset_data( gem1__screen_t1_r13, val_gem1__screen_t1_r13); +set_reset_data( gem1__screen_t1_r14, val_gem1__screen_t1_r14); +set_reset_data( gem1__screen_t1_r15, val_gem1__screen_t1_r15); +set_reset_data( gem1__screen_t2_r0, val_gem1__screen_t2_r0); +set_reset_data( gem1__screen_t2_r1, val_gem1__screen_t2_r1); +set_reset_data( gem1__screen_t2_r2, val_gem1__screen_t2_r2); +set_reset_data( gem1__screen_t2_r3, val_gem1__screen_t2_r3); +set_reset_data( gem1__screen_t2_r4, val_gem1__screen_t2_r4); +set_reset_data( gem1__screen_t2_r5, val_gem1__screen_t2_r5); +set_reset_data( gem1__screen_t2_r6, val_gem1__screen_t2_r6); +set_reset_data( gem1__screen_t2_r7, val_gem1__screen_t2_r7); +set_reset_data( gem1__screen_t2_r8, val_gem1__screen_t2_r8); +set_reset_data( gem1__screen_t2_r9, val_gem1__screen_t2_r9); +set_reset_data( gem1__screen_t2_r10, val_gem1__screen_t2_r10); +set_reset_data( gem1__screen_t2_r11, val_gem1__screen_t2_r11); +set_reset_data( gem1__screen_t2_r12, val_gem1__screen_t2_r12); +set_reset_data( gem1__screen_t2_r13, val_gem1__screen_t2_r13); +set_reset_data( gem1__screen_t2_r14, val_gem1__screen_t2_r14); +set_reset_data( gem1__screen_t2_r15, val_gem1__screen_t2_r15); +set_reset_data( gem1__intr_en_pq1, val_gem1__intr_en_pq1); +set_reset_data( gem1__intr_en_pq2, val_gem1__intr_en_pq2); +set_reset_data( gem1__intr_en_pq3, val_gem1__intr_en_pq3); +set_reset_data( gem1__intr_en_pq4, val_gem1__intr_en_pq4); +set_reset_data( gem1__intr_en_pq5, val_gem1__intr_en_pq5); +set_reset_data( gem1__intr_en_pq6, val_gem1__intr_en_pq6); +set_reset_data( gem1__intr_en_pq7, val_gem1__intr_en_pq7); +set_reset_data( gem1__intr_dis_pq1, val_gem1__intr_dis_pq1); +set_reset_data( gem1__intr_dis_pq2, val_gem1__intr_dis_pq2); +set_reset_data( gem1__intr_dis_pq3, val_gem1__intr_dis_pq3); +set_reset_data( gem1__intr_dis_pq4, val_gem1__intr_dis_pq4); +set_reset_data( gem1__intr_dis_pq5, val_gem1__intr_dis_pq5); +set_reset_data( gem1__intr_dis_pq6, val_gem1__intr_dis_pq6); +set_reset_data( gem1__intr_dis_pq7, val_gem1__intr_dis_pq7); +set_reset_data( gem1__intr_mask_pq1, val_gem1__intr_mask_pq1); +set_reset_data( gem1__intr_mask_pq2, val_gem1__intr_mask_pq2); +set_reset_data( gem1__intr_mask_pq3, val_gem1__intr_mask_pq3); +set_reset_data( gem1__intr_mask_pq4, val_gem1__intr_mask_pq4); +set_reset_data( gem1__intr_mask_pq5, val_gem1__intr_mask_pq5); +set_reset_data( gem1__intr_mask_pq6, val_gem1__intr_mask_pq6); +set_reset_data( gem1__intr_mask_pq7, val_gem1__intr_mask_pq7); + +// ************************************************************ +// Module gpio gpio +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpio__MASK_DATA_0_LSW, val_gpio__MASK_DATA_0_LSW); +set_reset_data( gpio__MASK_DATA_0_MSW, val_gpio__MASK_DATA_0_MSW); +set_reset_data( gpio__MASK_DATA_1_LSW, val_gpio__MASK_DATA_1_LSW); +set_reset_data( gpio__MASK_DATA_1_MSW, val_gpio__MASK_DATA_1_MSW); +set_reset_data( gpio__MASK_DATA_2_LSW, val_gpio__MASK_DATA_2_LSW); +set_reset_data( gpio__MASK_DATA_2_MSW, val_gpio__MASK_DATA_2_MSW); +set_reset_data( gpio__MASK_DATA_3_LSW, val_gpio__MASK_DATA_3_LSW); +set_reset_data( gpio__MASK_DATA_3_MSW, val_gpio__MASK_DATA_3_MSW); +set_reset_data( gpio__DATA_0, val_gpio__DATA_0); +set_reset_data( gpio__DATA_1, val_gpio__DATA_1); +set_reset_data( gpio__DATA_2, val_gpio__DATA_2); +set_reset_data( gpio__DATA_3, val_gpio__DATA_3); +set_reset_data( gpio__DATA_0_RO, val_gpio__DATA_0_RO); +set_reset_data( gpio__DATA_1_RO, val_gpio__DATA_1_RO); +set_reset_data( gpio__DATA_2_RO, val_gpio__DATA_2_RO); +set_reset_data( gpio__DATA_3_RO, val_gpio__DATA_3_RO); +set_reset_data( gpio__BYPM_0, val_gpio__BYPM_0); +set_reset_data( gpio__DIRM_0, val_gpio__DIRM_0); +set_reset_data( gpio__OEN_0, val_gpio__OEN_0); +set_reset_data( gpio__INT_MASK_0, val_gpio__INT_MASK_0); +set_reset_data( gpio__INT_EN_0, val_gpio__INT_EN_0); +set_reset_data( gpio__INT_DIS_0, val_gpio__INT_DIS_0); +set_reset_data( gpio__INT_STAT_0, val_gpio__INT_STAT_0); +set_reset_data( gpio__INT_TYPE_0, val_gpio__INT_TYPE_0); +set_reset_data( gpio__INT_POLARITY_0, val_gpio__INT_POLARITY_0); +set_reset_data( gpio__INT_ANY_0, val_gpio__INT_ANY_0); +set_reset_data( gpio__BYPM_1, val_gpio__BYPM_1); +set_reset_data( gpio__DIRM_1, val_gpio__DIRM_1); +set_reset_data( gpio__OEN_1, val_gpio__OEN_1); +set_reset_data( gpio__INT_MASK_1, val_gpio__INT_MASK_1); +set_reset_data( gpio__INT_EN_1, val_gpio__INT_EN_1); +set_reset_data( gpio__INT_DIS_1, val_gpio__INT_DIS_1); +set_reset_data( gpio__INT_STAT_1, val_gpio__INT_STAT_1); +set_reset_data( gpio__INT_TYPE_1, val_gpio__INT_TYPE_1); +set_reset_data( gpio__INT_POLARITY_1, val_gpio__INT_POLARITY_1); +set_reset_data( gpio__INT_ANY_1, val_gpio__INT_ANY_1); +set_reset_data( gpio__BYPM_2, val_gpio__BYPM_2); +set_reset_data( gpio__DIRM_2, val_gpio__DIRM_2); +set_reset_data( gpio__OEN_2, val_gpio__OEN_2); +set_reset_data( gpio__INT_MASK_2, val_gpio__INT_MASK_2); +set_reset_data( gpio__INT_EN_2, val_gpio__INT_EN_2); +set_reset_data( gpio__INT_DIS_2, val_gpio__INT_DIS_2); +set_reset_data( gpio__INT_STAT_2, val_gpio__INT_STAT_2); +set_reset_data( gpio__INT_TYPE_2, val_gpio__INT_TYPE_2); +set_reset_data( gpio__INT_POLARITY_2, val_gpio__INT_POLARITY_2); +set_reset_data( gpio__INT_ANY_2, val_gpio__INT_ANY_2); +set_reset_data( gpio__BYPM_3, val_gpio__BYPM_3); +set_reset_data( gpio__DIRM_3, val_gpio__DIRM_3); +set_reset_data( gpio__OEN_3, val_gpio__OEN_3); +set_reset_data( gpio__INT_MASK_3, val_gpio__INT_MASK_3); +set_reset_data( gpio__INT_EN_3, val_gpio__INT_EN_3); +set_reset_data( gpio__INT_DIS_3, val_gpio__INT_DIS_3); +set_reset_data( gpio__INT_STAT_3, val_gpio__INT_STAT_3); +set_reset_data( gpio__INT_TYPE_3, val_gpio__INT_TYPE_3); +set_reset_data( gpio__INT_POLARITY_3, val_gpio__INT_POLARITY_3); +set_reset_data( gpio__INT_ANY_3, val_gpio__INT_ANY_3); + +// ************************************************************ +// Module gpv_iou_switch gpv_iou_switch +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_iou_switch__Remap, val_gpv_iou_switch__Remap); +set_reset_data( gpv_iou_switch__security2_sdio0, val_gpv_iou_switch__security2_sdio0); +set_reset_data( gpv_iou_switch__security3_sdio1, val_gpv_iou_switch__security3_sdio1); +set_reset_data( gpv_iou_switch__security4_qspi, val_gpv_iou_switch__security4_qspi); +set_reset_data( gpv_iou_switch__security5_miou, val_gpv_iou_switch__security5_miou); +set_reset_data( gpv_iou_switch__security6_apb_slaves, val_gpv_iou_switch__security6_apb_slaves); +set_reset_data( gpv_iou_switch__security7_smc, val_gpv_iou_switch__security7_smc); +set_reset_data( gpv_iou_switch__peripheral_id4, val_gpv_iou_switch__peripheral_id4); +set_reset_data( gpv_iou_switch__peripheral_id5, val_gpv_iou_switch__peripheral_id5); +set_reset_data( gpv_iou_switch__peripheral_id6, val_gpv_iou_switch__peripheral_id6); +set_reset_data( gpv_iou_switch__peripheral_id7, val_gpv_iou_switch__peripheral_id7); +set_reset_data( gpv_iou_switch__peripheral_id0, val_gpv_iou_switch__peripheral_id0); +set_reset_data( gpv_iou_switch__peripheral_id1, val_gpv_iou_switch__peripheral_id1); +set_reset_data( gpv_iou_switch__peripheral_id2, val_gpv_iou_switch__peripheral_id2); +set_reset_data( gpv_iou_switch__peripheral_id3, val_gpv_iou_switch__peripheral_id3); +set_reset_data( gpv_iou_switch__component_id0, val_gpv_iou_switch__component_id0); +set_reset_data( gpv_iou_switch__component_id1, val_gpv_iou_switch__component_id1); +set_reset_data( gpv_iou_switch__component_id2, val_gpv_iou_switch__component_id2); +set_reset_data( gpv_iou_switch__component_id3, val_gpv_iou_switch__component_id3); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio0, val_gpv_iou_switch__fn_mod_bm_iss_sdio0); +set_reset_data( gpv_iou_switch__ahb_cntl_sdio0, val_gpv_iou_switch__ahb_cntl_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio1, val_gpv_iou_switch__fn_mod_bm_iss_sdio1); +set_reset_data( gpv_iou_switch__ahb_cntl_sdio1, val_gpv_iou_switch__ahb_cntl_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_qspi, val_gpv_iou_switch__fn_mod_bm_iss_qspi); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_miou, val_gpv_iou_switch__fn_mod_bm_iss_miou); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_smc, val_gpv_iou_switch__fn_mod_bm_iss_smc); +set_reset_data( gpv_iou_switch__fn_mod_ahb_gem0, val_gpv_iou_switch__fn_mod_ahb_gem0); +set_reset_data( gpv_iou_switch__read_qos_gem0, val_gpv_iou_switch__read_qos_gem0); +set_reset_data( gpv_iou_switch__write_qos_gem0, val_gpv_iou_switch__write_qos_gem0); +set_reset_data( gpv_iou_switch__fn_mod_iss_gem0, val_gpv_iou_switch__fn_mod_iss_gem0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_gem1, val_gpv_iou_switch__fn_mod_ahb_gem1); +set_reset_data( gpv_iou_switch__read_qos_gem1, val_gpv_iou_switch__read_qos_gem1); +set_reset_data( gpv_iou_switch__write_qos_gem1, val_gpv_iou_switch__write_qos_gem1); +set_reset_data( gpv_iou_switch__fn_mod_iss_gem1, val_gpv_iou_switch__fn_mod_iss_gem1); +set_reset_data( gpv_iou_switch__fn_mod_ahb_usb0, val_gpv_iou_switch__fn_mod_ahb_usb0); +set_reset_data( gpv_iou_switch__read_qos_usb0, val_gpv_iou_switch__read_qos_usb0); +set_reset_data( gpv_iou_switch__write_qos_usb0, val_gpv_iou_switch__write_qos_usb0); +set_reset_data( gpv_iou_switch__fn_mod_iss_usb0, val_gpv_iou_switch__fn_mod_iss_usb0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_usb1, val_gpv_iou_switch__fn_mod_ahb_usb1); +set_reset_data( gpv_iou_switch__read_qos_usb1, val_gpv_iou_switch__read_qos_usb1); +set_reset_data( gpv_iou_switch__write_qos_usb1, val_gpv_iou_switch__write_qos_usb1); +set_reset_data( gpv_iou_switch__fn_mod_iss_usb1, val_gpv_iou_switch__fn_mod_iss_usb1); +set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio0, val_gpv_iou_switch__fn_mod_ahb_sdio0); +set_reset_data( gpv_iou_switch__read_qos_sdio0, val_gpv_iou_switch__read_qos_sdio0); +set_reset_data( gpv_iou_switch__write_qos_sdio0, val_gpv_iou_switch__write_qos_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_iss_sdio0, val_gpv_iou_switch__fn_mod_iss_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio1, val_gpv_iou_switch__fn_mod_ahb_sdio1); +set_reset_data( gpv_iou_switch__read_qos_sdio1, val_gpv_iou_switch__read_qos_sdio1); +set_reset_data( gpv_iou_switch__write_qos_sdio1, val_gpv_iou_switch__write_qos_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_iss_sdio1, val_gpv_iou_switch__fn_mod_iss_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_iss_siou, val_gpv_iou_switch__fn_mod_iss_siou); + +// ************************************************************ +// Module gpv_qos301_cpu qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_cpu__qos_cntl, val_gpv_qos301_cpu__qos_cntl); +set_reset_data( gpv_qos301_cpu__max_ot, val_gpv_qos301_cpu__max_ot); +set_reset_data( gpv_qos301_cpu__max_comb_ot, val_gpv_qos301_cpu__max_comb_ot); +set_reset_data( gpv_qos301_cpu__aw_p, val_gpv_qos301_cpu__aw_p); +set_reset_data( gpv_qos301_cpu__aw_b, val_gpv_qos301_cpu__aw_b); +set_reset_data( gpv_qos301_cpu__aw_r, val_gpv_qos301_cpu__aw_r); +set_reset_data( gpv_qos301_cpu__ar_p, val_gpv_qos301_cpu__ar_p); +set_reset_data( gpv_qos301_cpu__ar_b, val_gpv_qos301_cpu__ar_b); +set_reset_data( gpv_qos301_cpu__ar_r, val_gpv_qos301_cpu__ar_r); + +// ************************************************************ +// Module gpv_qos301_dmac qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_dmac__qos_cntl, val_gpv_qos301_dmac__qos_cntl); +set_reset_data( gpv_qos301_dmac__max_ot, val_gpv_qos301_dmac__max_ot); +set_reset_data( gpv_qos301_dmac__max_comb_ot, val_gpv_qos301_dmac__max_comb_ot); +set_reset_data( gpv_qos301_dmac__aw_p, val_gpv_qos301_dmac__aw_p); +set_reset_data( gpv_qos301_dmac__aw_b, val_gpv_qos301_dmac__aw_b); +set_reset_data( gpv_qos301_dmac__aw_r, val_gpv_qos301_dmac__aw_r); +set_reset_data( gpv_qos301_dmac__ar_p, val_gpv_qos301_dmac__ar_p); +set_reset_data( gpv_qos301_dmac__ar_b, val_gpv_qos301_dmac__ar_b); +set_reset_data( gpv_qos301_dmac__ar_r, val_gpv_qos301_dmac__ar_r); + +// ************************************************************ +// Module gpv_qos301_iou qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_iou__qos_cntl, val_gpv_qos301_iou__qos_cntl); +set_reset_data( gpv_qos301_iou__max_ot, val_gpv_qos301_iou__max_ot); +set_reset_data( gpv_qos301_iou__max_comb_ot, val_gpv_qos301_iou__max_comb_ot); +set_reset_data( gpv_qos301_iou__aw_p, val_gpv_qos301_iou__aw_p); +set_reset_data( gpv_qos301_iou__aw_b, val_gpv_qos301_iou__aw_b); +set_reset_data( gpv_qos301_iou__aw_r, val_gpv_qos301_iou__aw_r); +set_reset_data( gpv_qos301_iou__ar_p, val_gpv_qos301_iou__ar_p); +set_reset_data( gpv_qos301_iou__ar_b, val_gpv_qos301_iou__ar_b); +set_reset_data( gpv_qos301_iou__ar_r, val_gpv_qos301_iou__ar_r); + +// ************************************************************ +// Module gpv_trustzone nic301_addr_region_ctrl_registers +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_trustzone__Remap, val_gpv_trustzone__Remap); +set_reset_data( gpv_trustzone__security_fssw_s0, val_gpv_trustzone__security_fssw_s0); +set_reset_data( gpv_trustzone__security_fssw_s1, val_gpv_trustzone__security_fssw_s1); +set_reset_data( gpv_trustzone__security_apb, val_gpv_trustzone__security_apb); + +// ************************************************************ +// Module i2c0 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( i2c0__Control_reg0, val_i2c0__Control_reg0); +set_reset_data( i2c0__Status_reg0, val_i2c0__Status_reg0); +set_reset_data( i2c0__I2C_address_reg0, val_i2c0__I2C_address_reg0); +set_reset_data( i2c0__I2C_data_reg0, val_i2c0__I2C_data_reg0); +set_reset_data( i2c0__Interrupt_status_reg0, val_i2c0__Interrupt_status_reg0); +set_reset_data( i2c0__Transfer_size_reg0, val_i2c0__Transfer_size_reg0); +set_reset_data( i2c0__Slave_mon_pause_reg0, val_i2c0__Slave_mon_pause_reg0); +set_reset_data( i2c0__Time_out_reg0, val_i2c0__Time_out_reg0); +set_reset_data( i2c0__Intrpt_mask_reg0, val_i2c0__Intrpt_mask_reg0); +set_reset_data( i2c0__Intrpt_enable_reg0, val_i2c0__Intrpt_enable_reg0); +set_reset_data( i2c0__Intrpt_disable_reg0, val_i2c0__Intrpt_disable_reg0); + +// ************************************************************ +// Module i2c1 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( i2c1__Control_reg0, val_i2c1__Control_reg0); +set_reset_data( i2c1__Status_reg0, val_i2c1__Status_reg0); +set_reset_data( i2c1__I2C_address_reg0, val_i2c1__I2C_address_reg0); +set_reset_data( i2c1__I2C_data_reg0, val_i2c1__I2C_data_reg0); +set_reset_data( i2c1__Interrupt_status_reg0, val_i2c1__Interrupt_status_reg0); +set_reset_data( i2c1__Transfer_size_reg0, val_i2c1__Transfer_size_reg0); +set_reset_data( i2c1__Slave_mon_pause_reg0, val_i2c1__Slave_mon_pause_reg0); +set_reset_data( i2c1__Time_out_reg0, val_i2c1__Time_out_reg0); +set_reset_data( i2c1__Intrpt_mask_reg0, val_i2c1__Intrpt_mask_reg0); +set_reset_data( i2c1__Intrpt_enable_reg0, val_i2c1__Intrpt_enable_reg0); +set_reset_data( i2c1__Intrpt_disable_reg0, val_i2c1__Intrpt_disable_reg0); + +// ************************************************************ +// Module l2cache L2Cpl310 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( l2cache__reg0_cache_id, val_l2cache__reg0_cache_id); +set_reset_data( l2cache__reg0_cache_type, val_l2cache__reg0_cache_type); +set_reset_data( l2cache__reg1_control, val_l2cache__reg1_control); +set_reset_data( l2cache__reg1_aux_control, val_l2cache__reg1_aux_control); +set_reset_data( l2cache__reg1_tag_ram_control, val_l2cache__reg1_tag_ram_control); +set_reset_data( l2cache__reg1_data_ram_control, val_l2cache__reg1_data_ram_control); +set_reset_data( l2cache__reg2_ev_counter_ctrl, val_l2cache__reg2_ev_counter_ctrl); +set_reset_data( l2cache__reg2_ev_counter1_cfg, val_l2cache__reg2_ev_counter1_cfg); +set_reset_data( l2cache__reg2_ev_counter0_cfg, val_l2cache__reg2_ev_counter0_cfg); +set_reset_data( l2cache__reg2_ev_counter1, val_l2cache__reg2_ev_counter1); +set_reset_data( l2cache__reg2_ev_counter0, val_l2cache__reg2_ev_counter0); +set_reset_data( l2cache__reg2_int_mask, val_l2cache__reg2_int_mask); +set_reset_data( l2cache__reg2_int_mask_status, val_l2cache__reg2_int_mask_status); +set_reset_data( l2cache__reg2_int_raw_status, val_l2cache__reg2_int_raw_status); +set_reset_data( l2cache__reg2_int_clear, val_l2cache__reg2_int_clear); +set_reset_data( l2cache__reg7_cache_sync, val_l2cache__reg7_cache_sync); +set_reset_data( l2cache__reg7_inv_pa, val_l2cache__reg7_inv_pa); +set_reset_data( l2cache__reg7_inv_way, val_l2cache__reg7_inv_way); +set_reset_data( l2cache__reg7_clean_pa, val_l2cache__reg7_clean_pa); +set_reset_data( l2cache__reg7_clean_index, val_l2cache__reg7_clean_index); +set_reset_data( l2cache__reg7_clean_way, val_l2cache__reg7_clean_way); +set_reset_data( l2cache__reg7_clean_inv_pa, val_l2cache__reg7_clean_inv_pa); +set_reset_data( l2cache__reg7_clean_inv_index, val_l2cache__reg7_clean_inv_index); +set_reset_data( l2cache__reg7_clean_inv_way, val_l2cache__reg7_clean_inv_way); +set_reset_data( l2cache__reg9_d_lockdown0, val_l2cache__reg9_d_lockdown0); +set_reset_data( l2cache__reg9_i_lockdown0, val_l2cache__reg9_i_lockdown0); +set_reset_data( l2cache__reg9_d_lockdown1, val_l2cache__reg9_d_lockdown1); +set_reset_data( l2cache__reg9_i_lockdown1, val_l2cache__reg9_i_lockdown1); +set_reset_data( l2cache__reg9_d_lockdown2, val_l2cache__reg9_d_lockdown2); +set_reset_data( l2cache__reg9_i_lockdown2, val_l2cache__reg9_i_lockdown2); +set_reset_data( l2cache__reg9_d_lockdown3, val_l2cache__reg9_d_lockdown3); +set_reset_data( l2cache__reg9_i_lockdown3, val_l2cache__reg9_i_lockdown3); +set_reset_data( l2cache__reg9_d_lockdown4, val_l2cache__reg9_d_lockdown4); +set_reset_data( l2cache__reg9_i_lockdown4, val_l2cache__reg9_i_lockdown4); +set_reset_data( l2cache__reg9_d_lockdown5, val_l2cache__reg9_d_lockdown5); +set_reset_data( l2cache__reg9_i_lockdown5, val_l2cache__reg9_i_lockdown5); +set_reset_data( l2cache__reg9_d_lockdown6, val_l2cache__reg9_d_lockdown6); +set_reset_data( l2cache__reg9_i_lockdown6, val_l2cache__reg9_i_lockdown6); +set_reset_data( l2cache__reg9_d_lockdown7, val_l2cache__reg9_d_lockdown7); +set_reset_data( l2cache__reg9_i_lockdown7, val_l2cache__reg9_i_lockdown7); +set_reset_data( l2cache__reg9_lock_line_en, val_l2cache__reg9_lock_line_en); +set_reset_data( l2cache__reg9_unlock_way, val_l2cache__reg9_unlock_way); +set_reset_data( l2cache__reg12_addr_filtering_start, val_l2cache__reg12_addr_filtering_start); +set_reset_data( l2cache__reg12_addr_filtering_end, val_l2cache__reg12_addr_filtering_end); +set_reset_data( l2cache__reg15_debug_ctrl, val_l2cache__reg15_debug_ctrl); +set_reset_data( l2cache__reg15_prefetch_ctrl, val_l2cache__reg15_prefetch_ctrl); +set_reset_data( l2cache__reg15_power_ctrl, val_l2cache__reg15_power_ctrl); + +// ************************************************************ +// Module mpcore mpcore +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( mpcore__SCU_CONTROL_REGISTER, val_mpcore__SCU_CONTROL_REGISTER); +set_reset_data( mpcore__SCU_CONFIGURATION_REGISTER, val_mpcore__SCU_CONFIGURATION_REGISTER); +set_reset_data( mpcore__SCU_CPU_Power_Status_Register, val_mpcore__SCU_CPU_Power_Status_Register); +set_reset_data( mpcore__SCU_Invalidate_All_Registers_in_Secure_State, val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State); +set_reset_data( mpcore__Filtering_Start_Address_Register, val_mpcore__Filtering_Start_Address_Register); +set_reset_data( mpcore__Filtering_End_Address_Register, val_mpcore__Filtering_End_Address_Register); +set_reset_data( mpcore__SCU_Access_Control_Register_SAC, val_mpcore__SCU_Access_Control_Register_SAC); +set_reset_data( mpcore__SCU_Non_secure_Access_Control_Register, val_mpcore__SCU_Non_secure_Access_Control_Register); +set_reset_data( mpcore__ICCICR, val_mpcore__ICCICR); +set_reset_data( mpcore__ICCPMR, val_mpcore__ICCPMR); +set_reset_data( mpcore__ICCBPR, val_mpcore__ICCBPR); +set_reset_data( mpcore__ICCIAR, val_mpcore__ICCIAR); +set_reset_data( mpcore__ICCEOIR, val_mpcore__ICCEOIR); +set_reset_data( mpcore__ICCRPR, val_mpcore__ICCRPR); +set_reset_data( mpcore__ICCHPIR, val_mpcore__ICCHPIR); +set_reset_data( mpcore__ICCABPR, val_mpcore__ICCABPR); +set_reset_data( mpcore__ICCIDR, val_mpcore__ICCIDR); +set_reset_data( mpcore__Global_Timer_Counter_Register0, val_mpcore__Global_Timer_Counter_Register0); +set_reset_data( mpcore__Global_Timer_Counter_Register1, val_mpcore__Global_Timer_Counter_Register1); +set_reset_data( mpcore__Global_Timer_Control_Register, val_mpcore__Global_Timer_Control_Register); +set_reset_data( mpcore__Global_Timer_Interrupt_Status_Register, val_mpcore__Global_Timer_Interrupt_Status_Register); +set_reset_data( mpcore__Comparator_Value_Register0, val_mpcore__Comparator_Value_Register0); +set_reset_data( mpcore__Comparator_Value_Register1, val_mpcore__Comparator_Value_Register1); +set_reset_data( mpcore__Auto_increment_Register, val_mpcore__Auto_increment_Register); +set_reset_data( mpcore__Private_Timer_Load_Register, val_mpcore__Private_Timer_Load_Register); +set_reset_data( mpcore__Private_Timer_Counter_Register, val_mpcore__Private_Timer_Counter_Register); +set_reset_data( mpcore__Private_Timer_Control_Register, val_mpcore__Private_Timer_Control_Register); +set_reset_data( mpcore__Private_Timer_Interrupt_Status_Register, val_mpcore__Private_Timer_Interrupt_Status_Register); +set_reset_data( mpcore__Watchdog_Load_Register, val_mpcore__Watchdog_Load_Register); +set_reset_data( mpcore__Watchdog_Counter_Register, val_mpcore__Watchdog_Counter_Register); +set_reset_data( mpcore__Watchdog_Control_Register, val_mpcore__Watchdog_Control_Register); +set_reset_data( mpcore__Watchdog_Interrupt_Status_Register, val_mpcore__Watchdog_Interrupt_Status_Register); +set_reset_data( mpcore__Watchdog_Reset_Status_Register, val_mpcore__Watchdog_Reset_Status_Register); +set_reset_data( mpcore__Watchdog_Disable_Register, val_mpcore__Watchdog_Disable_Register); +set_reset_data( mpcore__ICDDCR, val_mpcore__ICDDCR); +set_reset_data( mpcore__ICDICTR, val_mpcore__ICDICTR); +set_reset_data( mpcore__ICDIIDR, val_mpcore__ICDIIDR); +set_reset_data( mpcore__ICDISR0, val_mpcore__ICDISR0); +set_reset_data( mpcore__ICDISR1, val_mpcore__ICDISR1); +set_reset_data( mpcore__ICDISR2, val_mpcore__ICDISR2); +set_reset_data( mpcore__ICDISER0, val_mpcore__ICDISER0); +set_reset_data( mpcore__ICDISER1, val_mpcore__ICDISER1); +set_reset_data( mpcore__ICDISER2, val_mpcore__ICDISER2); +set_reset_data( mpcore__ICDICER0, val_mpcore__ICDICER0); +set_reset_data( mpcore__ICDICER1, val_mpcore__ICDICER1); +set_reset_data( mpcore__ICDICER2, val_mpcore__ICDICER2); +set_reset_data( mpcore__ICDISPR0, val_mpcore__ICDISPR0); +set_reset_data( mpcore__ICDISPR1, val_mpcore__ICDISPR1); +set_reset_data( mpcore__ICDISPR2, val_mpcore__ICDISPR2); +set_reset_data( mpcore__ICDICPR0, val_mpcore__ICDICPR0); +set_reset_data( mpcore__ICDICPR1, val_mpcore__ICDICPR1); +set_reset_data( mpcore__ICDICPR2, val_mpcore__ICDICPR2); +set_reset_data( mpcore__ICDABR0, val_mpcore__ICDABR0); +set_reset_data( mpcore__ICDABR1, val_mpcore__ICDABR1); +set_reset_data( mpcore__ICDABR2, val_mpcore__ICDABR2); +set_reset_data( mpcore__ICDIPR0, val_mpcore__ICDIPR0); +set_reset_data( mpcore__ICDIPR1, val_mpcore__ICDIPR1); +set_reset_data( mpcore__ICDIPR2, val_mpcore__ICDIPR2); +set_reset_data( mpcore__ICDIPR3, val_mpcore__ICDIPR3); +set_reset_data( mpcore__ICDIPR4, val_mpcore__ICDIPR4); +set_reset_data( mpcore__ICDIPR5, val_mpcore__ICDIPR5); +set_reset_data( mpcore__ICDIPR6, val_mpcore__ICDIPR6); +set_reset_data( mpcore__ICDIPR7, val_mpcore__ICDIPR7); +set_reset_data( mpcore__ICDIPR8, val_mpcore__ICDIPR8); +set_reset_data( mpcore__ICDIPR9, val_mpcore__ICDIPR9); +set_reset_data( mpcore__ICDIPR10, val_mpcore__ICDIPR10); +set_reset_data( mpcore__ICDIPR11, val_mpcore__ICDIPR11); +set_reset_data( mpcore__ICDIPR12, val_mpcore__ICDIPR12); +set_reset_data( mpcore__ICDIPR13, val_mpcore__ICDIPR13); +set_reset_data( mpcore__ICDIPR14, val_mpcore__ICDIPR14); +set_reset_data( mpcore__ICDIPR15, val_mpcore__ICDIPR15); +set_reset_data( mpcore__ICDIPR16, val_mpcore__ICDIPR16); +set_reset_data( mpcore__ICDIPR17, val_mpcore__ICDIPR17); +set_reset_data( mpcore__ICDIPR18, val_mpcore__ICDIPR18); +set_reset_data( mpcore__ICDIPR19, val_mpcore__ICDIPR19); +set_reset_data( mpcore__ICDIPR20, val_mpcore__ICDIPR20); +set_reset_data( mpcore__ICDIPR21, val_mpcore__ICDIPR21); +set_reset_data( mpcore__ICDIPR22, val_mpcore__ICDIPR22); +set_reset_data( mpcore__ICDIPR23, val_mpcore__ICDIPR23); +set_reset_data( mpcore__ICDIPTR0, val_mpcore__ICDIPTR0); +set_reset_data( mpcore__ICDIPTR1, val_mpcore__ICDIPTR1); +set_reset_data( mpcore__ICDIPTR2, val_mpcore__ICDIPTR2); +set_reset_data( mpcore__ICDIPTR3, val_mpcore__ICDIPTR3); +set_reset_data( mpcore__ICDIPTR4, val_mpcore__ICDIPTR4); +set_reset_data( mpcore__ICDIPTR5, val_mpcore__ICDIPTR5); +set_reset_data( mpcore__ICDIPTR6, val_mpcore__ICDIPTR6); +set_reset_data( mpcore__ICDIPTR7, val_mpcore__ICDIPTR7); +set_reset_data( mpcore__ICDIPTR8, val_mpcore__ICDIPTR8); +set_reset_data( mpcore__ICDIPTR9, val_mpcore__ICDIPTR9); +set_reset_data( mpcore__ICDIPTR10, val_mpcore__ICDIPTR10); +set_reset_data( mpcore__ICDIPTR11, val_mpcore__ICDIPTR11); +set_reset_data( mpcore__ICDIPTR12, val_mpcore__ICDIPTR12); +set_reset_data( mpcore__ICDIPTR13, val_mpcore__ICDIPTR13); +set_reset_data( mpcore__ICDIPTR14, val_mpcore__ICDIPTR14); +set_reset_data( mpcore__ICDIPTR15, val_mpcore__ICDIPTR15); +set_reset_data( mpcore__ICDIPTR16, val_mpcore__ICDIPTR16); +set_reset_data( mpcore__ICDIPTR17, val_mpcore__ICDIPTR17); +set_reset_data( mpcore__ICDIPTR18, val_mpcore__ICDIPTR18); +set_reset_data( mpcore__ICDIPTR19, val_mpcore__ICDIPTR19); +set_reset_data( mpcore__ICDIPTR20, val_mpcore__ICDIPTR20); +set_reset_data( mpcore__ICDIPTR21, val_mpcore__ICDIPTR21); +set_reset_data( mpcore__ICDIPTR22, val_mpcore__ICDIPTR22); +set_reset_data( mpcore__ICDIPTR23, val_mpcore__ICDIPTR23); +set_reset_data( mpcore__ICDICFR0, val_mpcore__ICDICFR0); +set_reset_data( mpcore__ICDICFR1, val_mpcore__ICDICFR1); +set_reset_data( mpcore__ICDICFR2, val_mpcore__ICDICFR2); +set_reset_data( mpcore__ICDICFR3, val_mpcore__ICDICFR3); +set_reset_data( mpcore__ICDICFR4, val_mpcore__ICDICFR4); +set_reset_data( mpcore__ICDICFR5, val_mpcore__ICDICFR5); +set_reset_data( mpcore__ppi_status, val_mpcore__ppi_status); +set_reset_data( mpcore__spi_status_0, val_mpcore__spi_status_0); +set_reset_data( mpcore__spi_status_1, val_mpcore__spi_status_1); +set_reset_data( mpcore__ICDSGIR, val_mpcore__ICDSGIR); +set_reset_data( mpcore__ICPIDR4, val_mpcore__ICPIDR4); +set_reset_data( mpcore__ICPIDR5, val_mpcore__ICPIDR5); +set_reset_data( mpcore__ICPIDR6, val_mpcore__ICPIDR6); +set_reset_data( mpcore__ICPIDR7, val_mpcore__ICPIDR7); +set_reset_data( mpcore__ICPIDR0, val_mpcore__ICPIDR0); +set_reset_data( mpcore__ICPIDR1, val_mpcore__ICPIDR1); +set_reset_data( mpcore__ICPIDR2, val_mpcore__ICPIDR2); +set_reset_data( mpcore__ICPIDR3, val_mpcore__ICPIDR3); +set_reset_data( mpcore__ICCIDR0, val_mpcore__ICCIDR0); +set_reset_data( mpcore__ICCIDR1, val_mpcore__ICCIDR1); +set_reset_data( mpcore__ICCIDR2, val_mpcore__ICCIDR2); +set_reset_data( mpcore__ICCIDR3, val_mpcore__ICCIDR3); + +// ************************************************************ +// Module ocm ocm +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ocm__OCM_PARITY_CTRL, val_ocm__OCM_PARITY_CTRL); +set_reset_data( ocm__OCM_PARITY_ERRADDRESS, val_ocm__OCM_PARITY_ERRADDRESS); +set_reset_data( ocm__OCM_IRQ_STS, val_ocm__OCM_IRQ_STS); +set_reset_data( ocm__OCM_CONTROL, val_ocm__OCM_CONTROL); + +// ************************************************************ +// Module qspi qspi +// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller +/// Design Specification document +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( qspi__Config_reg, val_qspi__Config_reg); +set_reset_data( qspi__Intr_status_REG, val_qspi__Intr_status_REG); +set_reset_data( qspi__Intrpt_en_REG, val_qspi__Intrpt_en_REG); +set_reset_data( qspi__Intrpt_dis_REG, val_qspi__Intrpt_dis_REG); +set_reset_data( qspi__Intrpt_mask_REG, val_qspi__Intrpt_mask_REG); +set_reset_data( qspi__En_REG, val_qspi__En_REG); +set_reset_data( qspi__Delay_REG, val_qspi__Delay_REG); +set_reset_data( qspi__TXD0, val_qspi__TXD0); +set_reset_data( qspi__Rx_data_REG, val_qspi__Rx_data_REG); +set_reset_data( qspi__Slave_Idle_count_REG, val_qspi__Slave_Idle_count_REG); +set_reset_data( qspi__TX_thres_REG, val_qspi__TX_thres_REG); +set_reset_data( qspi__RX_thres_REG, val_qspi__RX_thres_REG); +set_reset_data( qspi__GPIO, val_qspi__GPIO); +set_reset_data( qspi__LPBK_DLY_ADJ, val_qspi__LPBK_DLY_ADJ); +set_reset_data( qspi__TXD1, val_qspi__TXD1); +set_reset_data( qspi__TXD2, val_qspi__TXD2); +set_reset_data( qspi__TXD3, val_qspi__TXD3); +set_reset_data( qspi__LQSPI_CFG, val_qspi__LQSPI_CFG); +set_reset_data( qspi__LQSPI_STS, val_qspi__LQSPI_STS); +set_reset_data( qspi__MOD_ID, val_qspi__MOD_ID); + +// ************************************************************ +// Module sd0 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( sd0__SDMA_system_address_register, val_sd0__SDMA_system_address_register); +set_reset_data( sd0__Block_Size_Block_Count, val_sd0__Block_Size_Block_Count); +set_reset_data( sd0__Argument, val_sd0__Argument); +set_reset_data( sd0__Transfer_Mode_Command, val_sd0__Transfer_Mode_Command); +set_reset_data( sd0__Response0, val_sd0__Response0); +set_reset_data( sd0__Response1, val_sd0__Response1); +set_reset_data( sd0__Response2, val_sd0__Response2); +set_reset_data( sd0__Response3, val_sd0__Response3); +set_reset_data( sd0__Buffer_Data_Port, val_sd0__Buffer_Data_Port); +set_reset_data( sd0__Present_State, val_sd0__Present_State); +set_reset_data( sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control); +set_reset_data( sd0__Clock_Control_Timeout_control_Software_reset, val_sd0__Clock_Control_Timeout_control_Software_reset); +set_reset_data( sd0__Normal_interrupt_status_Error_interrupt_status, val_sd0__Normal_interrupt_status_Error_interrupt_status); +set_reset_data( sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable); +set_reset_data( sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); +set_reset_data( sd0__Auto_CMD12_error_status, val_sd0__Auto_CMD12_error_status); +set_reset_data( sd0__Capabilities, val_sd0__Capabilities); +set_reset_data( sd0__Maximum_current_capabilities, val_sd0__Maximum_current_capabilities); +set_reset_data( sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); +set_reset_data( sd0__ADMA_error_status, val_sd0__ADMA_error_status); +set_reset_data( sd0__ADMA_system_address, val_sd0__ADMA_system_address); +set_reset_data( sd0__Boot_Timeout_control, val_sd0__Boot_Timeout_control); +set_reset_data( sd0__Debug_Selection, val_sd0__Debug_Selection); +set_reset_data( sd0__SPI_interrupt_support, val_sd0__SPI_interrupt_support); +set_reset_data( sd0__Slot_interrupt_status_Host_controller_version, val_sd0__Slot_interrupt_status_Host_controller_version); + +// ************************************************************ +// Module sd1 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( sd1__SDMA_system_address_register, val_sd1__SDMA_system_address_register); +set_reset_data( sd1__Block_Size_Block_Count, val_sd1__Block_Size_Block_Count); +set_reset_data( sd1__Argument, val_sd1__Argument); +set_reset_data( sd1__Transfer_Mode_Command, val_sd1__Transfer_Mode_Command); +set_reset_data( sd1__Response0, val_sd1__Response0); +set_reset_data( sd1__Response1, val_sd1__Response1); +set_reset_data( sd1__Response2, val_sd1__Response2); +set_reset_data( sd1__Response3, val_sd1__Response3); +set_reset_data( sd1__Buffer_Data_Port, val_sd1__Buffer_Data_Port); +set_reset_data( sd1__Present_State, val_sd1__Present_State); +set_reset_data( sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control); +set_reset_data( sd1__Clock_Control_Timeout_control_Software_reset, val_sd1__Clock_Control_Timeout_control_Software_reset); +set_reset_data( sd1__Normal_interrupt_status_Error_interrupt_status, val_sd1__Normal_interrupt_status_Error_interrupt_status); +set_reset_data( sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable); +set_reset_data( sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); +set_reset_data( sd1__Auto_CMD12_error_status, val_sd1__Auto_CMD12_error_status); +set_reset_data( sd1__Capabilities, val_sd1__Capabilities); +set_reset_data( sd1__Maximum_current_capabilities, val_sd1__Maximum_current_capabilities); +set_reset_data( sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); +set_reset_data( sd1__ADMA_error_status, val_sd1__ADMA_error_status); +set_reset_data( sd1__ADMA_system_address, val_sd1__ADMA_system_address); +set_reset_data( sd1__Boot_Timeout_control, val_sd1__Boot_Timeout_control); +set_reset_data( sd1__Debug_Selection, val_sd1__Debug_Selection); +set_reset_data( sd1__SPI_interrupt_support, val_sd1__SPI_interrupt_support); +set_reset_data( sd1__Slot_interrupt_status_Host_controller_version, val_sd1__Slot_interrupt_status_Host_controller_version); + +// ************************************************************ +// Module slcr slcr +// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( slcr__SCL, val_slcr__SCL); +set_reset_data( slcr__SLCR_LOCK, val_slcr__SLCR_LOCK); +set_reset_data( slcr__SLCR_UNLOCK, val_slcr__SLCR_UNLOCK); +set_reset_data( slcr__SLCR_LOCKSTA, val_slcr__SLCR_LOCKSTA); +set_reset_data( slcr__ARM_PLL_CTRL, val_slcr__ARM_PLL_CTRL); +set_reset_data( slcr__DDR_PLL_CTRL, val_slcr__DDR_PLL_CTRL); +set_reset_data( slcr__IO_PLL_CTRL, val_slcr__IO_PLL_CTRL); +set_reset_data( slcr__PLL_STATUS, val_slcr__PLL_STATUS); +set_reset_data( slcr__ARM_PLL_CFG, val_slcr__ARM_PLL_CFG); +set_reset_data( slcr__DDR_PLL_CFG, val_slcr__DDR_PLL_CFG); +set_reset_data( slcr__IO_PLL_CFG, val_slcr__IO_PLL_CFG); +set_reset_data( slcr__PLL_BG_CTRL, val_slcr__PLL_BG_CTRL); +set_reset_data( slcr__ARM_CLK_CTRL, val_slcr__ARM_CLK_CTRL); +set_reset_data( slcr__DDR_CLK_CTRL, val_slcr__DDR_CLK_CTRL); +set_reset_data( slcr__DCI_CLK_CTRL, val_slcr__DCI_CLK_CTRL); +set_reset_data( slcr__APER_CLK_CTRL, val_slcr__APER_CLK_CTRL); +set_reset_data( slcr__USB0_CLK_CTRL, val_slcr__USB0_CLK_CTRL); +set_reset_data( slcr__USB1_CLK_CTRL, val_slcr__USB1_CLK_CTRL); +set_reset_data( slcr__GEM0_RCLK_CTRL, val_slcr__GEM0_RCLK_CTRL); +set_reset_data( slcr__GEM1_RCLK_CTRL, val_slcr__GEM1_RCLK_CTRL); +set_reset_data( slcr__GEM0_CLK_CTRL, val_slcr__GEM0_CLK_CTRL); +set_reset_data( slcr__GEM1_CLK_CTRL, val_slcr__GEM1_CLK_CTRL); +set_reset_data( slcr__SMC_CLK_CTRL, val_slcr__SMC_CLK_CTRL); +set_reset_data( slcr__LQSPI_CLK_CTRL, val_slcr__LQSPI_CLK_CTRL); +set_reset_data( slcr__SDIO_CLK_CTRL, val_slcr__SDIO_CLK_CTRL); +set_reset_data( slcr__UART_CLK_CTRL, val_slcr__UART_CLK_CTRL); +set_reset_data( slcr__SPI_CLK_CTRL, val_slcr__SPI_CLK_CTRL); +set_reset_data( slcr__CAN_CLK_CTRL, val_slcr__CAN_CLK_CTRL); +set_reset_data( slcr__CAN_MIOCLK_CTRL, val_slcr__CAN_MIOCLK_CTRL); +set_reset_data( slcr__DBG_CLK_CTRL, val_slcr__DBG_CLK_CTRL); +set_reset_data( slcr__PCAP_CLK_CTRL, val_slcr__PCAP_CLK_CTRL); +set_reset_data( slcr__TOPSW_CLK_CTRL, val_slcr__TOPSW_CLK_CTRL); +set_reset_data( slcr__FPGA0_CLK_CTRL, val_slcr__FPGA0_CLK_CTRL); +set_reset_data( slcr__FPGA0_THR_CTRL, val_slcr__FPGA0_THR_CTRL); +set_reset_data( slcr__FPGA0_THR_CNT, val_slcr__FPGA0_THR_CNT); +set_reset_data( slcr__FPGA0_THR_STA, val_slcr__FPGA0_THR_STA); +set_reset_data( slcr__FPGA1_CLK_CTRL, val_slcr__FPGA1_CLK_CTRL); +set_reset_data( slcr__FPGA1_THR_CTRL, val_slcr__FPGA1_THR_CTRL); +set_reset_data( slcr__FPGA1_THR_CNT, val_slcr__FPGA1_THR_CNT); +set_reset_data( slcr__FPGA1_THR_STA, val_slcr__FPGA1_THR_STA); +set_reset_data( slcr__FPGA2_CLK_CTRL, val_slcr__FPGA2_CLK_CTRL); +set_reset_data( slcr__FPGA2_THR_CTRL, val_slcr__FPGA2_THR_CTRL); +set_reset_data( slcr__FPGA2_THR_CNT, val_slcr__FPGA2_THR_CNT); +set_reset_data( slcr__FPGA2_THR_STA, val_slcr__FPGA2_THR_STA); +set_reset_data( slcr__FPGA3_CLK_CTRL, val_slcr__FPGA3_CLK_CTRL); +set_reset_data( slcr__FPGA3_THR_CTRL, val_slcr__FPGA3_THR_CTRL); +set_reset_data( slcr__FPGA3_THR_CNT, val_slcr__FPGA3_THR_CNT); +set_reset_data( slcr__FPGA3_THR_STA, val_slcr__FPGA3_THR_STA); +set_reset_data( slcr__SRST_UART_CTRL, val_slcr__SRST_UART_CTRL); +set_reset_data( slcr__BANDGAP_TRIM, val_slcr__BANDGAP_TRIM); +set_reset_data( slcr__CC_TEST, val_slcr__CC_TEST); +set_reset_data( slcr__PLL_PREDIVISOR, val_slcr__PLL_PREDIVISOR); +set_reset_data( slcr__CLK_621_TRUE, val_slcr__CLK_621_TRUE); +set_reset_data( slcr__PICTURE_DBG, val_slcr__PICTURE_DBG); +set_reset_data( slcr__PICTURE_DBG_UCNT, val_slcr__PICTURE_DBG_UCNT); +set_reset_data( slcr__PICTURE_DBG_LCNT, val_slcr__PICTURE_DBG_LCNT); +set_reset_data( slcr__PSS_RST_CTRL, val_slcr__PSS_RST_CTRL); +set_reset_data( slcr__DDR_RST_CTRL, val_slcr__DDR_RST_CTRL); +set_reset_data( slcr__TOPSW_RST_CTRL, val_slcr__TOPSW_RST_CTRL); +set_reset_data( slcr__DMAC_RST_CTRL, val_slcr__DMAC_RST_CTRL); +set_reset_data( slcr__USB_RST_CTRL, val_slcr__USB_RST_CTRL); +set_reset_data( slcr__GEM_RST_CTRL, val_slcr__GEM_RST_CTRL); +set_reset_data( slcr__SDIO_RST_CTRL, val_slcr__SDIO_RST_CTRL); +set_reset_data( slcr__SPI_RST_CTRL, val_slcr__SPI_RST_CTRL); +set_reset_data( slcr__CAN_RST_CTRL, val_slcr__CAN_RST_CTRL); +set_reset_data( slcr__I2C_RST_CTRL, val_slcr__I2C_RST_CTRL); +set_reset_data( slcr__UART_RST_CTRL, val_slcr__UART_RST_CTRL); +set_reset_data( slcr__GPIO_RST_CTRL, val_slcr__GPIO_RST_CTRL); +set_reset_data( slcr__LQSPI_RST_CTRL, val_slcr__LQSPI_RST_CTRL); +set_reset_data( slcr__SMC_RST_CTRL, val_slcr__SMC_RST_CTRL); +set_reset_data( slcr__OCM_RST_CTRL, val_slcr__OCM_RST_CTRL); +set_reset_data( slcr__DEVCI_RST_CTRL, val_slcr__DEVCI_RST_CTRL); +set_reset_data( slcr__FPGA_RST_CTRL, val_slcr__FPGA_RST_CTRL); +set_reset_data( slcr__A9_CPU_RST_CTRL, val_slcr__A9_CPU_RST_CTRL); +set_reset_data( slcr__RS_AWDT_CTRL, val_slcr__RS_AWDT_CTRL); +set_reset_data( slcr__RST_REASON, val_slcr__RST_REASON); +set_reset_data( slcr__RST_REASON_CLR, val_slcr__RST_REASON_CLR); +set_reset_data( slcr__REBOOT_STATUS, val_slcr__REBOOT_STATUS); +set_reset_data( slcr__BOOT_MODE, val_slcr__BOOT_MODE); +set_reset_data( slcr__APU_CTRL, val_slcr__APU_CTRL); +set_reset_data( slcr__WDT_CLK_SEL, val_slcr__WDT_CLK_SEL); +set_reset_data( slcr__TZ_OCM_RAM0, val_slcr__TZ_OCM_RAM0); +set_reset_data( slcr__TZ_OCM_RAM1, val_slcr__TZ_OCM_RAM1); +set_reset_data( slcr__TZ_OCM_ROM, val_slcr__TZ_OCM_ROM); +set_reset_data( slcr__TZ_DDR_RAM, val_slcr__TZ_DDR_RAM); +set_reset_data( slcr__TZ_DMA_NS, val_slcr__TZ_DMA_NS); +set_reset_data( slcr__TZ_DMA_IRQ_NS, val_slcr__TZ_DMA_IRQ_NS); +set_reset_data( slcr__TZ_DMA_PERIPH_NS, val_slcr__TZ_DMA_PERIPH_NS); +set_reset_data( slcr__TZ_GEM, val_slcr__TZ_GEM); +set_reset_data( slcr__TZ_SDIO, val_slcr__TZ_SDIO); +set_reset_data( slcr__TZ_USB, val_slcr__TZ_USB); +set_reset_data( slcr__TZ_FPGA_M, val_slcr__TZ_FPGA_M); +set_reset_data( slcr__TZ_FPGA_AFI, val_slcr__TZ_FPGA_AFI); +set_reset_data( slcr__DBG_CTRL, val_slcr__DBG_CTRL); +set_reset_data( slcr__PSS_IDCODE, val_slcr__PSS_IDCODE); +set_reset_data( slcr__DDR_URGENT, val_slcr__DDR_URGENT); +set_reset_data( slcr__DDR_CAL_START, val_slcr__DDR_CAL_START); +set_reset_data( slcr__DDR_REF_START, val_slcr__DDR_REF_START); +set_reset_data( slcr__DDR_CMD_STA, val_slcr__DDR_CMD_STA); +set_reset_data( slcr__DDR_URGENT_SEL, val_slcr__DDR_URGENT_SEL); +set_reset_data( slcr__DDR_DFI_STATUS, val_slcr__DDR_DFI_STATUS); +set_reset_data( slcr__MIO_PIN_00, val_slcr__MIO_PIN_00); +set_reset_data( slcr__MIO_PIN_01, val_slcr__MIO_PIN_01); +set_reset_data( slcr__MIO_PIN_02, val_slcr__MIO_PIN_02); +set_reset_data( slcr__MIO_PIN_03, val_slcr__MIO_PIN_03); +set_reset_data( slcr__MIO_PIN_04, val_slcr__MIO_PIN_04); +set_reset_data( slcr__MIO_PIN_05, val_slcr__MIO_PIN_05); +set_reset_data( slcr__MIO_PIN_06, val_slcr__MIO_PIN_06); +set_reset_data( slcr__MIO_PIN_07, val_slcr__MIO_PIN_07); +set_reset_data( slcr__MIO_PIN_08, val_slcr__MIO_PIN_08); +set_reset_data( slcr__MIO_PIN_09, val_slcr__MIO_PIN_09); +set_reset_data( slcr__MIO_PIN_10, val_slcr__MIO_PIN_10); +set_reset_data( slcr__MIO_PIN_11, val_slcr__MIO_PIN_11); +set_reset_data( slcr__MIO_PIN_12, val_slcr__MIO_PIN_12); +set_reset_data( slcr__MIO_PIN_13, val_slcr__MIO_PIN_13); +set_reset_data( slcr__MIO_PIN_14, val_slcr__MIO_PIN_14); +set_reset_data( slcr__MIO_PIN_15, val_slcr__MIO_PIN_15); +set_reset_data( slcr__MIO_PIN_16, val_slcr__MIO_PIN_16); +set_reset_data( slcr__MIO_PIN_17, val_slcr__MIO_PIN_17); +set_reset_data( slcr__MIO_PIN_18, val_slcr__MIO_PIN_18); +set_reset_data( slcr__MIO_PIN_19, val_slcr__MIO_PIN_19); +set_reset_data( slcr__MIO_PIN_20, val_slcr__MIO_PIN_20); +set_reset_data( slcr__MIO_PIN_21, val_slcr__MIO_PIN_21); +set_reset_data( slcr__MIO_PIN_22, val_slcr__MIO_PIN_22); +set_reset_data( slcr__MIO_PIN_23, val_slcr__MIO_PIN_23); +set_reset_data( slcr__MIO_PIN_24, val_slcr__MIO_PIN_24); +set_reset_data( slcr__MIO_PIN_25, val_slcr__MIO_PIN_25); +set_reset_data( slcr__MIO_PIN_26, val_slcr__MIO_PIN_26); +set_reset_data( slcr__MIO_PIN_27, val_slcr__MIO_PIN_27); +set_reset_data( slcr__MIO_PIN_28, val_slcr__MIO_PIN_28); +set_reset_data( slcr__MIO_PIN_29, val_slcr__MIO_PIN_29); +set_reset_data( slcr__MIO_PIN_30, val_slcr__MIO_PIN_30); +set_reset_data( slcr__MIO_PIN_31, val_slcr__MIO_PIN_31); +set_reset_data( slcr__MIO_PIN_32, val_slcr__MIO_PIN_32); +set_reset_data( slcr__MIO_PIN_33, val_slcr__MIO_PIN_33); +set_reset_data( slcr__MIO_PIN_34, val_slcr__MIO_PIN_34); +set_reset_data( slcr__MIO_PIN_35, val_slcr__MIO_PIN_35); +set_reset_data( slcr__MIO_PIN_36, val_slcr__MIO_PIN_36); +set_reset_data( slcr__MIO_PIN_37, val_slcr__MIO_PIN_37); +set_reset_data( slcr__MIO_PIN_38, val_slcr__MIO_PIN_38); +set_reset_data( slcr__MIO_PIN_39, val_slcr__MIO_PIN_39); +set_reset_data( slcr__MIO_PIN_40, val_slcr__MIO_PIN_40); +set_reset_data( slcr__MIO_PIN_41, val_slcr__MIO_PIN_41); +set_reset_data( slcr__MIO_PIN_42, val_slcr__MIO_PIN_42); +set_reset_data( slcr__MIO_PIN_43, val_slcr__MIO_PIN_43); +set_reset_data( slcr__MIO_PIN_44, val_slcr__MIO_PIN_44); +set_reset_data( slcr__MIO_PIN_45, val_slcr__MIO_PIN_45); +set_reset_data( slcr__MIO_PIN_46, val_slcr__MIO_PIN_46); +set_reset_data( slcr__MIO_PIN_47, val_slcr__MIO_PIN_47); +set_reset_data( slcr__MIO_PIN_48, val_slcr__MIO_PIN_48); +set_reset_data( slcr__MIO_PIN_49, val_slcr__MIO_PIN_49); +set_reset_data( slcr__MIO_PIN_50, val_slcr__MIO_PIN_50); +set_reset_data( slcr__MIO_PIN_51, val_slcr__MIO_PIN_51); +set_reset_data( slcr__MIO_PIN_52, val_slcr__MIO_PIN_52); +set_reset_data( slcr__MIO_PIN_53, val_slcr__MIO_PIN_53); +set_reset_data( slcr__MIO_FMIO_GEM_SEL, val_slcr__MIO_FMIO_GEM_SEL); +set_reset_data( slcr__MIO_LOOPBACK, val_slcr__MIO_LOOPBACK); +set_reset_data( slcr__MIO_MST_TRI0, val_slcr__MIO_MST_TRI0); +set_reset_data( slcr__MIO_MST_TRI1, val_slcr__MIO_MST_TRI1); +set_reset_data( slcr__SD0_WP_CD_SEL, val_slcr__SD0_WP_CD_SEL); +set_reset_data( slcr__SD1_WP_CD_SEL, val_slcr__SD1_WP_CD_SEL); +set_reset_data( slcr__LVL_SHFTR_EN, val_slcr__LVL_SHFTR_EN); +set_reset_data( slcr__OCM_CFG, val_slcr__OCM_CFG); +set_reset_data( slcr__CPU0_RAM0, val_slcr__CPU0_RAM0); +set_reset_data( slcr__CPU0_RAM1, val_slcr__CPU0_RAM1); +set_reset_data( slcr__CPU0_RAM2, val_slcr__CPU0_RAM2); +set_reset_data( slcr__CPU1_RAM0, val_slcr__CPU1_RAM0); +set_reset_data( slcr__CPU1_RAM1, val_slcr__CPU1_RAM1); +set_reset_data( slcr__CPU1_RAM2, val_slcr__CPU1_RAM2); +set_reset_data( slcr__SCU_RAM, val_slcr__SCU_RAM); +set_reset_data( slcr__L2C_RAM, val_slcr__L2C_RAM); +set_reset_data( slcr__IOU_RAM_GEM01, val_slcr__IOU_RAM_GEM01); +set_reset_data( slcr__IOU_RAM_USB01, val_slcr__IOU_RAM_USB01); +set_reset_data( slcr__IOU_RAM_SDIO0, val_slcr__IOU_RAM_SDIO0); +set_reset_data( slcr__IOU_RAM_SDIO1, val_slcr__IOU_RAM_SDIO1); +set_reset_data( slcr__IOU_RAM_CAN0, val_slcr__IOU_RAM_CAN0); +set_reset_data( slcr__IOU_RAM_CAN1, val_slcr__IOU_RAM_CAN1); +set_reset_data( slcr__IOU_RAM_LQSPI, val_slcr__IOU_RAM_LQSPI); +set_reset_data( slcr__DMAC_RAM, val_slcr__DMAC_RAM); +set_reset_data( slcr__AFI0_RAM0, val_slcr__AFI0_RAM0); +set_reset_data( slcr__AFI0_RAM1, val_slcr__AFI0_RAM1); +set_reset_data( slcr__AFI0_RAM2, val_slcr__AFI0_RAM2); +set_reset_data( slcr__AFI1_RAM0, val_slcr__AFI1_RAM0); +set_reset_data( slcr__AFI1_RAM1, val_slcr__AFI1_RAM1); +set_reset_data( slcr__AFI1_RAM2, val_slcr__AFI1_RAM2); +set_reset_data( slcr__AFI2_RAM0, val_slcr__AFI2_RAM0); +set_reset_data( slcr__AFI2_RAM1, val_slcr__AFI2_RAM1); +set_reset_data( slcr__AFI2_RAM2, val_slcr__AFI2_RAM2); +set_reset_data( slcr__AFI3_RAM0, val_slcr__AFI3_RAM0); +set_reset_data( slcr__AFI3_RAM1, val_slcr__AFI3_RAM1); +set_reset_data( slcr__AFI3_RAM2, val_slcr__AFI3_RAM2); +set_reset_data( slcr__OCM_RAM, val_slcr__OCM_RAM); +set_reset_data( slcr__OCM_ROM0, val_slcr__OCM_ROM0); +set_reset_data( slcr__OCM_ROM1, val_slcr__OCM_ROM1); +set_reset_data( slcr__DEVCI_RAM, val_slcr__DEVCI_RAM); +set_reset_data( slcr__CSG_RAM, val_slcr__CSG_RAM); +set_reset_data( slcr__GPIOB_CTRL, val_slcr__GPIOB_CTRL); +set_reset_data( slcr__GPIOB_CFG_CMOS18, val_slcr__GPIOB_CFG_CMOS18); +set_reset_data( slcr__GPIOB_CFG_CMOS25, val_slcr__GPIOB_CFG_CMOS25); +set_reset_data( slcr__GPIOB_CFG_CMOS33, val_slcr__GPIOB_CFG_CMOS33); +set_reset_data( slcr__GPIOB_CFG_LVTTL, val_slcr__GPIOB_CFG_LVTTL); +set_reset_data( slcr__GPIOB_CFG_HSTL, val_slcr__GPIOB_CFG_HSTL); +set_reset_data( slcr__GPIOB_DRVR_BIAS_CTRL, val_slcr__GPIOB_DRVR_BIAS_CTRL); +set_reset_data( slcr__DDRIOB_ADDR0, val_slcr__DDRIOB_ADDR0); +set_reset_data( slcr__DDRIOB_ADDR1, val_slcr__DDRIOB_ADDR1); +set_reset_data( slcr__DDRIOB_DATA0, val_slcr__DDRIOB_DATA0); +set_reset_data( slcr__DDRIOB_DATA1, val_slcr__DDRIOB_DATA1); +set_reset_data( slcr__DDRIOB_DIFF0, val_slcr__DDRIOB_DIFF0); +set_reset_data( slcr__DDRIOB_DIFF1, val_slcr__DDRIOB_DIFF1); +set_reset_data( slcr__DDRIOB_CLOCK, val_slcr__DDRIOB_CLOCK); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_ADDR, val_slcr__DDRIOB_DRIVE_SLEW_ADDR); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DATA, val_slcr__DDRIOB_DRIVE_SLEW_DATA); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DIFF, val_slcr__DDRIOB_DRIVE_SLEW_DIFF); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_CLOCK, val_slcr__DDRIOB_DRIVE_SLEW_CLOCK); +set_reset_data( slcr__DDRIOB_DDR_CTRL, val_slcr__DDRIOB_DDR_CTRL); +set_reset_data( slcr__DDRIOB_DCI_CTRL, val_slcr__DDRIOB_DCI_CTRL); +set_reset_data( slcr__DDRIOB_DCI_STATUS, val_slcr__DDRIOB_DCI_STATUS); + +// ************************************************************ +// Module smcc pl353 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( smcc__memc_status, val_smcc__memc_status); +set_reset_data( smcc__memif_cfg, val_smcc__memif_cfg); +set_reset_data( smcc__memc_cfg_set, val_smcc__memc_cfg_set); +set_reset_data( smcc__memc_cfg_clr, val_smcc__memc_cfg_clr); +set_reset_data( smcc__direct_cmd, val_smcc__direct_cmd); +set_reset_data( smcc__set_cycles, val_smcc__set_cycles); +set_reset_data( smcc__set_opmode, val_smcc__set_opmode); +set_reset_data( smcc__refresh_period_0, val_smcc__refresh_period_0); +set_reset_data( smcc__refresh_period_1, val_smcc__refresh_period_1); +set_reset_data( smcc__sram_cycles0_0, val_smcc__sram_cycles0_0); +set_reset_data( smcc__opmode0_0, val_smcc__opmode0_0); +set_reset_data( smcc__sram_cycles0_1, val_smcc__sram_cycles0_1); +set_reset_data( smcc__opmode0_1, val_smcc__opmode0_1); +set_reset_data( smcc__nand_cycles1_0, val_smcc__nand_cycles1_0); +set_reset_data( smcc__opmode1_0, val_smcc__opmode1_0); +set_reset_data( smcc__user_status, val_smcc__user_status); +set_reset_data( smcc__user_config, val_smcc__user_config); +set_reset_data( smcc__ecc_status_0, val_smcc__ecc_status_0); +set_reset_data( smcc__ecc_memcfg_0, val_smcc__ecc_memcfg_0); +set_reset_data( smcc__ecc_memcommand1_0, val_smcc__ecc_memcommand1_0); +set_reset_data( smcc__ecc_memcommand2_0, val_smcc__ecc_memcommand2_0); +set_reset_data( smcc__ecc_addr0_0, val_smcc__ecc_addr0_0); +set_reset_data( smcc__ecc_addr1_0, val_smcc__ecc_addr1_0); +set_reset_data( smcc__ecc_value0_0, val_smcc__ecc_value0_0); +set_reset_data( smcc__ecc_value1_0, val_smcc__ecc_value1_0); +set_reset_data( smcc__ecc_value2_0, val_smcc__ecc_value2_0); +set_reset_data( smcc__ecc_value3_0, val_smcc__ecc_value3_0); +set_reset_data( smcc__ecc_status_1, val_smcc__ecc_status_1); +set_reset_data( smcc__ecc_memcfg_1, val_smcc__ecc_memcfg_1); +set_reset_data( smcc__ecc_memcommand1_1, val_smcc__ecc_memcommand1_1); +set_reset_data( smcc__ecc_memcommand2_1, val_smcc__ecc_memcommand2_1); +set_reset_data( smcc__ecc_addr0_1, val_smcc__ecc_addr0_1); +set_reset_data( smcc__ecc_addr1_1, val_smcc__ecc_addr1_1); +set_reset_data( smcc__ecc_value0_1, val_smcc__ecc_value0_1); +set_reset_data( smcc__ecc_value1_1, val_smcc__ecc_value1_1); +set_reset_data( smcc__ecc_value2_1, val_smcc__ecc_value2_1); +set_reset_data( smcc__ecc_value3_1, val_smcc__ecc_value3_1); +set_reset_data( smcc__integration_test, val_smcc__integration_test); +set_reset_data( smcc__periph_id_0, val_smcc__periph_id_0); +set_reset_data( smcc__periph_id_1, val_smcc__periph_id_1); +set_reset_data( smcc__periph_id_2, val_smcc__periph_id_2); +set_reset_data( smcc__periph_id_3, val_smcc__periph_id_3); +set_reset_data( smcc__pcell_id_0, val_smcc__pcell_id_0); +set_reset_data( smcc__pcell_id_1, val_smcc__pcell_id_1); +set_reset_data( smcc__pcell_id_2, val_smcc__pcell_id_2); +set_reset_data( smcc__pcell_id_3, val_smcc__pcell_id_3); + +// ************************************************************ +// Module spi0 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( spi0__Config_reg0, val_spi0__Config_reg0); +set_reset_data( spi0__Intr_status_reg0, val_spi0__Intr_status_reg0); +set_reset_data( spi0__Intrpt_en_reg0, val_spi0__Intrpt_en_reg0); +set_reset_data( spi0__Intrpt_dis_reg0, val_spi0__Intrpt_dis_reg0); +set_reset_data( spi0__Intrpt_mask_reg0, val_spi0__Intrpt_mask_reg0); +set_reset_data( spi0__En_reg0, val_spi0__En_reg0); +set_reset_data( spi0__Delay_reg0, val_spi0__Delay_reg0); +set_reset_data( spi0__Tx_data_reg0, val_spi0__Tx_data_reg0); +set_reset_data( spi0__Rx_data_reg0, val_spi0__Rx_data_reg0); +set_reset_data( spi0__Slave_Idle_count_reg0, val_spi0__Slave_Idle_count_reg0); +set_reset_data( spi0__TX_thres_reg0, val_spi0__TX_thres_reg0); +set_reset_data( spi0__RX_thres_reg0, val_spi0__RX_thres_reg0); +set_reset_data( spi0__Mod_id_reg0, val_spi0__Mod_id_reg0); + +// ************************************************************ +// Module spi1 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( spi1__Config_reg0, val_spi1__Config_reg0); +set_reset_data( spi1__Intr_status_reg0, val_spi1__Intr_status_reg0); +set_reset_data( spi1__Intrpt_en_reg0, val_spi1__Intrpt_en_reg0); +set_reset_data( spi1__Intrpt_dis_reg0, val_spi1__Intrpt_dis_reg0); +set_reset_data( spi1__Intrpt_mask_reg0, val_spi1__Intrpt_mask_reg0); +set_reset_data( spi1__En_reg0, val_spi1__En_reg0); +set_reset_data( spi1__Delay_reg0, val_spi1__Delay_reg0); +set_reset_data( spi1__Tx_data_reg0, val_spi1__Tx_data_reg0); +set_reset_data( spi1__Rx_data_reg0, val_spi1__Rx_data_reg0); +set_reset_data( spi1__Slave_Idle_count_reg0, val_spi1__Slave_Idle_count_reg0); +set_reset_data( spi1__TX_thres_reg0, val_spi1__TX_thres_reg0); +set_reset_data( spi1__RX_thres_reg0, val_spi1__RX_thres_reg0); +set_reset_data( spi1__Mod_id_reg0, val_spi1__Mod_id_reg0); + +// ************************************************************ +// Module swdt swdt +// doc version: 2.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( swdt__MODE, val_swdt__MODE); +set_reset_data( swdt__CONTROL, val_swdt__CONTROL); +set_reset_data( swdt__RESTART, val_swdt__RESTART); +set_reset_data( swdt__STATUS, val_swdt__STATUS); + +// ************************************************************ +// Module ttc0 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ttc0__Clock_Control_1, val_ttc0__Clock_Control_1); +set_reset_data( ttc0__Clock_Control_2, val_ttc0__Clock_Control_2); +set_reset_data( ttc0__Clock_Control_3, val_ttc0__Clock_Control_3); +set_reset_data( ttc0__Counter_Control_1, val_ttc0__Counter_Control_1); +set_reset_data( ttc0__Counter_Control_2, val_ttc0__Counter_Control_2); +set_reset_data( ttc0__Counter_Control_3, val_ttc0__Counter_Control_3); +set_reset_data( ttc0__Counter_Value_1, val_ttc0__Counter_Value_1); +set_reset_data( ttc0__Counter_Value_2, val_ttc0__Counter_Value_2); +set_reset_data( ttc0__Counter_Value_3, val_ttc0__Counter_Value_3); +set_reset_data( ttc0__Interval_Counter_1, val_ttc0__Interval_Counter_1); +set_reset_data( ttc0__Interval_Counter_2, val_ttc0__Interval_Counter_2); +set_reset_data( ttc0__Interval_Counter_3, val_ttc0__Interval_Counter_3); +set_reset_data( ttc0__Match_1_Counter_1, val_ttc0__Match_1_Counter_1); +set_reset_data( ttc0__Match_1_Counter_2, val_ttc0__Match_1_Counter_2); +set_reset_data( ttc0__Match_1_Counter_3, val_ttc0__Match_1_Counter_3); +set_reset_data( ttc0__Match_2_Counter_1, val_ttc0__Match_2_Counter_1); +set_reset_data( ttc0__Match_2_Counter_2, val_ttc0__Match_2_Counter_2); +set_reset_data( ttc0__Match_2_Counter_3, val_ttc0__Match_2_Counter_3); +set_reset_data( ttc0__Match_3_Counter_1, val_ttc0__Match_3_Counter_1); +set_reset_data( ttc0__Match_3_Counter_2, val_ttc0__Match_3_Counter_2); +set_reset_data( ttc0__Match_3_Counter_3, val_ttc0__Match_3_Counter_3); +set_reset_data( ttc0__Interrupt_Register_1, val_ttc0__Interrupt_Register_1); +set_reset_data( ttc0__Interrupt_Register_2, val_ttc0__Interrupt_Register_2); +set_reset_data( ttc0__Interrupt_Register_3, val_ttc0__Interrupt_Register_3); +set_reset_data( ttc0__Interrupt_Enable_1, val_ttc0__Interrupt_Enable_1); +set_reset_data( ttc0__Interrupt_Enable_2, val_ttc0__Interrupt_Enable_2); +set_reset_data( ttc0__Interrupt_Enable_3, val_ttc0__Interrupt_Enable_3); +set_reset_data( ttc0__Event_Control_Timer_1, val_ttc0__Event_Control_Timer_1); +set_reset_data( ttc0__Event_Control_Timer_2, val_ttc0__Event_Control_Timer_2); +set_reset_data( ttc0__Event_Control_Timer_3, val_ttc0__Event_Control_Timer_3); +set_reset_data( ttc0__Event_Register_1, val_ttc0__Event_Register_1); +set_reset_data( ttc0__Event_Register_2, val_ttc0__Event_Register_2); +set_reset_data( ttc0__Event_Register_3, val_ttc0__Event_Register_3); + +// ************************************************************ +// Module ttc1 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ttc1__Clock_Control_1, val_ttc1__Clock_Control_1); +set_reset_data( ttc1__Clock_Control_2, val_ttc1__Clock_Control_2); +set_reset_data( ttc1__Clock_Control_3, val_ttc1__Clock_Control_3); +set_reset_data( ttc1__Counter_Control_1, val_ttc1__Counter_Control_1); +set_reset_data( ttc1__Counter_Control_2, val_ttc1__Counter_Control_2); +set_reset_data( ttc1__Counter_Control_3, val_ttc1__Counter_Control_3); +set_reset_data( ttc1__Counter_Value_1, val_ttc1__Counter_Value_1); +set_reset_data( ttc1__Counter_Value_2, val_ttc1__Counter_Value_2); +set_reset_data( ttc1__Counter_Value_3, val_ttc1__Counter_Value_3); +set_reset_data( ttc1__Interval_Counter_1, val_ttc1__Interval_Counter_1); +set_reset_data( ttc1__Interval_Counter_2, val_ttc1__Interval_Counter_2); +set_reset_data( ttc1__Interval_Counter_3, val_ttc1__Interval_Counter_3); +set_reset_data( ttc1__Match_1_Counter_1, val_ttc1__Match_1_Counter_1); +set_reset_data( ttc1__Match_1_Counter_2, val_ttc1__Match_1_Counter_2); +set_reset_data( ttc1__Match_1_Counter_3, val_ttc1__Match_1_Counter_3); +set_reset_data( ttc1__Match_2_Counter_1, val_ttc1__Match_2_Counter_1); +set_reset_data( ttc1__Match_2_Counter_2, val_ttc1__Match_2_Counter_2); +set_reset_data( ttc1__Match_2_Counter_3, val_ttc1__Match_2_Counter_3); +set_reset_data( ttc1__Match_3_Counter_1, val_ttc1__Match_3_Counter_1); +set_reset_data( ttc1__Match_3_Counter_2, val_ttc1__Match_3_Counter_2); +set_reset_data( ttc1__Match_3_Counter_3, val_ttc1__Match_3_Counter_3); +set_reset_data( ttc1__Interrupt_Register_1, val_ttc1__Interrupt_Register_1); +set_reset_data( ttc1__Interrupt_Register_2, val_ttc1__Interrupt_Register_2); +set_reset_data( ttc1__Interrupt_Register_3, val_ttc1__Interrupt_Register_3); +set_reset_data( ttc1__Interrupt_Enable_1, val_ttc1__Interrupt_Enable_1); +set_reset_data( ttc1__Interrupt_Enable_2, val_ttc1__Interrupt_Enable_2); +set_reset_data( ttc1__Interrupt_Enable_3, val_ttc1__Interrupt_Enable_3); +set_reset_data( ttc1__Event_Control_Timer_1, val_ttc1__Event_Control_Timer_1); +set_reset_data( ttc1__Event_Control_Timer_2, val_ttc1__Event_Control_Timer_2); +set_reset_data( ttc1__Event_Control_Timer_3, val_ttc1__Event_Control_Timer_3); +set_reset_data( ttc1__Event_Register_1, val_ttc1__Event_Register_1); +set_reset_data( ttc1__Event_Register_2, val_ttc1__Event_Register_2); +set_reset_data( ttc1__Event_Register_3, val_ttc1__Event_Register_3); + +// ************************************************************ +// Module uart0 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( uart0__Control_reg0, val_uart0__Control_reg0); +set_reset_data( uart0__mode_reg0, val_uart0__mode_reg0); +set_reset_data( uart0__Intrpt_en_reg0, val_uart0__Intrpt_en_reg0); +set_reset_data( uart0__Intrpt_dis_reg0, val_uart0__Intrpt_dis_reg0); +set_reset_data( uart0__Intrpt_mask_reg0, val_uart0__Intrpt_mask_reg0); +set_reset_data( uart0__Chnl_int_sts_reg0, val_uart0__Chnl_int_sts_reg0); +set_reset_data( uart0__Baud_rate_gen_reg0, val_uart0__Baud_rate_gen_reg0); +set_reset_data( uart0__Rcvr_timeout_reg0, val_uart0__Rcvr_timeout_reg0); +set_reset_data( uart0__Rcvr_FIFO_trigger_level0, val_uart0__Rcvr_FIFO_trigger_level0); +set_reset_data( uart0__Modem_ctrl_reg0, val_uart0__Modem_ctrl_reg0); +set_reset_data( uart0__Modem_sts_reg0, val_uart0__Modem_sts_reg0); +set_reset_data( uart0__Channel_sts_reg0, val_uart0__Channel_sts_reg0); +set_reset_data( uart0__TX_RX_FIFO0, val_uart0__TX_RX_FIFO0); +set_reset_data( uart0__Baud_rate_divider_reg0, val_uart0__Baud_rate_divider_reg0); +set_reset_data( uart0__Flow_delay_reg0, val_uart0__Flow_delay_reg0); +set_reset_data( uart0__IR_min_rcv_pulse_wdth0, val_uart0__IR_min_rcv_pulse_wdth0); +set_reset_data( uart0__IR_transmitted_pulse_wdth0, val_uart0__IR_transmitted_pulse_wdth0); +set_reset_data( uart0__Tx_FIFO_trigger_level0, val_uart0__Tx_FIFO_trigger_level0); + +// ************************************************************ +// Module uart1 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( uart1__Control_reg0, val_uart1__Control_reg0); +set_reset_data( uart1__mode_reg0, val_uart1__mode_reg0); +set_reset_data( uart1__Intrpt_en_reg0, val_uart1__Intrpt_en_reg0); +set_reset_data( uart1__Intrpt_dis_reg0, val_uart1__Intrpt_dis_reg0); +set_reset_data( uart1__Intrpt_mask_reg0, val_uart1__Intrpt_mask_reg0); +set_reset_data( uart1__Chnl_int_sts_reg0, val_uart1__Chnl_int_sts_reg0); +set_reset_data( uart1__Baud_rate_gen_reg0, val_uart1__Baud_rate_gen_reg0); +set_reset_data( uart1__Rcvr_timeout_reg0, val_uart1__Rcvr_timeout_reg0); +set_reset_data( uart1__Rcvr_FIFO_trigger_level0, val_uart1__Rcvr_FIFO_trigger_level0); +set_reset_data( uart1__Modem_ctrl_reg0, val_uart1__Modem_ctrl_reg0); +set_reset_data( uart1__Modem_sts_reg0, val_uart1__Modem_sts_reg0); +set_reset_data( uart1__Channel_sts_reg0, val_uart1__Channel_sts_reg0); +set_reset_data( uart1__TX_RX_FIFO0, val_uart1__TX_RX_FIFO0); +set_reset_data( uart1__Baud_rate_divider_reg0, val_uart1__Baud_rate_divider_reg0); +set_reset_data( uart1__Flow_delay_reg0, val_uart1__Flow_delay_reg0); +set_reset_data( uart1__IR_min_rcv_pulse_wdth0, val_uart1__IR_min_rcv_pulse_wdth0); +set_reset_data( uart1__IR_transmitted_pulse_wdth0, val_uart1__IR_transmitted_pulse_wdth0); +set_reset_data( uart1__Tx_FIFO_trigger_level0, val_uart1__Tx_FIFO_trigger_level0); + +// ************************************************************ +// Module usb0 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( usb0__ID, val_usb0__ID); +set_reset_data( usb0__HWGENERAL, val_usb0__HWGENERAL); +set_reset_data( usb0__HWHOST, val_usb0__HWHOST); +set_reset_data( usb0__HWDEVICE, val_usb0__HWDEVICE); +set_reset_data( usb0__HWTXBUF, val_usb0__HWTXBUF); +set_reset_data( usb0__HWRXBUF, val_usb0__HWRXBUF); +set_reset_data( usb0__GPTIMER0LD, val_usb0__GPTIMER0LD); +set_reset_data( usb0__GPTIMER0CTRL, val_usb0__GPTIMER0CTRL); +set_reset_data( usb0__GPTIMER1LD, val_usb0__GPTIMER1LD); +set_reset_data( usb0__GPTIMER1CTRL, val_usb0__GPTIMER1CTRL); +set_reset_data( usb0__SBUSCFG, val_usb0__SBUSCFG); +set_reset_data( usb0__CAPLENGTH_HCIVERSION, val_usb0__CAPLENGTH_HCIVERSION); +set_reset_data( usb0__HCSPARAMS, val_usb0__HCSPARAMS); +set_reset_data( usb0__HCCPARAMS, val_usb0__HCCPARAMS); +set_reset_data( usb0__DCIVERSION, val_usb0__DCIVERSION); +set_reset_data( usb0__DCCPARAMS, val_usb0__DCCPARAMS); +set_reset_data( usb0__USBCMD, val_usb0__USBCMD); +set_reset_data( usb0__USBSTS, val_usb0__USBSTS); +set_reset_data( usb0__USBINTR, val_usb0__USBINTR); +set_reset_data( usb0__FRINDEX, val_usb0__FRINDEX); +set_reset_data( usb0__PERIODICLISTBASE_DEVICEADDR, val_usb0__PERIODICLISTBASE_DEVICEADDR); +set_reset_data( usb0__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR); +set_reset_data( usb0__TTCTRL, val_usb0__TTCTRL); +set_reset_data( usb0__BURSTSIZE, val_usb0__BURSTSIZE); +set_reset_data( usb0__TXFILLTUNING, val_usb0__TXFILLTUNING); +set_reset_data( usb0__TXTTFILLTUNING, val_usb0__TXTTFILLTUNING); +set_reset_data( usb0__IC_USB, val_usb0__IC_USB); +set_reset_data( usb0__ULPI_VIEWPORT, val_usb0__ULPI_VIEWPORT); +set_reset_data( usb0__ENDPTNAK, val_usb0__ENDPTNAK); +set_reset_data( usb0__ENDPTNAKEN, val_usb0__ENDPTNAKEN); +set_reset_data( usb0__CONFIGFLAG, val_usb0__CONFIGFLAG); +set_reset_data( usb0__PORTSC1, val_usb0__PORTSC1); +set_reset_data( usb0__OTGSC, val_usb0__OTGSC); +set_reset_data( usb0__USBMODE, val_usb0__USBMODE); +set_reset_data( usb0__ENDPTSETUPSTAT, val_usb0__ENDPTSETUPSTAT); +set_reset_data( usb0__ENDPTPRIME, val_usb0__ENDPTPRIME); +set_reset_data( usb0__ENDPTFLUSH, val_usb0__ENDPTFLUSH); +set_reset_data( usb0__ENDPTSTAT, val_usb0__ENDPTSTAT); +set_reset_data( usb0__ENDPTCOMPLETE, val_usb0__ENDPTCOMPLETE); +set_reset_data( usb0__ENDPTCTRL0, val_usb0__ENDPTCTRL0); +set_reset_data( usb0__ENDPTCTRL1, val_usb0__ENDPTCTRL1); +set_reset_data( usb0__ENDPTCTRL2, val_usb0__ENDPTCTRL2); +set_reset_data( usb0__ENDPTCTRL3, val_usb0__ENDPTCTRL3); +set_reset_data( usb0__ENDPTCTRL4, val_usb0__ENDPTCTRL4); +set_reset_data( usb0__ENDPTCTRL5, val_usb0__ENDPTCTRL5); +set_reset_data( usb0__ENDPTCTRL6, val_usb0__ENDPTCTRL6); +set_reset_data( usb0__ENDPTCTRL7, val_usb0__ENDPTCTRL7); +set_reset_data( usb0__ENDPTCTRL8, val_usb0__ENDPTCTRL8); +set_reset_data( usb0__ENDPTCTRL9, val_usb0__ENDPTCTRL9); +set_reset_data( usb0__ENDPTCTRL10, val_usb0__ENDPTCTRL10); +set_reset_data( usb0__ENDPTCTRL11, val_usb0__ENDPTCTRL11); +set_reset_data( usb0__ENDPTCTRL12, val_usb0__ENDPTCTRL12); + +// ************************************************************ +// Module usb1 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( usb1__ID, val_usb1__ID); +set_reset_data( usb1__HWGENERAL, val_usb1__HWGENERAL); +set_reset_data( usb1__HWHOST, val_usb1__HWHOST); +set_reset_data( usb1__HWDEVICE, val_usb1__HWDEVICE); +set_reset_data( usb1__HWTXBUF, val_usb1__HWTXBUF); +set_reset_data( usb1__HWRXBUF, val_usb1__HWRXBUF); +set_reset_data( usb1__GPTIMER0LD, val_usb1__GPTIMER0LD); +set_reset_data( usb1__GPTIMER0CTRL, val_usb1__GPTIMER0CTRL); +set_reset_data( usb1__GPTIMER1LD, val_usb1__GPTIMER1LD); +set_reset_data( usb1__GPTIMER1CTRL, val_usb1__GPTIMER1CTRL); +set_reset_data( usb1__SBUSCFG, val_usb1__SBUSCFG); +set_reset_data( usb1__CAPLENGTH_HCIVERSION, val_usb1__CAPLENGTH_HCIVERSION); +set_reset_data( usb1__HCSPARAMS, val_usb1__HCSPARAMS); +set_reset_data( usb1__HCCPARAMS, val_usb1__HCCPARAMS); +set_reset_data( usb1__DCIVERSION, val_usb1__DCIVERSION); +set_reset_data( usb1__DCCPARAMS, val_usb1__DCCPARAMS); +set_reset_data( usb1__USBCMD, val_usb1__USBCMD); +set_reset_data( usb1__USBSTS, val_usb1__USBSTS); +set_reset_data( usb1__USBINTR, val_usb1__USBINTR); +set_reset_data( usb1__FRINDEX, val_usb1__FRINDEX); +set_reset_data( usb1__PERIODICLISTBASE_DEVICEADDR, val_usb1__PERIODICLISTBASE_DEVICEADDR); +set_reset_data( usb1__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR); +set_reset_data( usb1__TTCTRL, val_usb1__TTCTRL); +set_reset_data( usb1__BURSTSIZE, val_usb1__BURSTSIZE); +set_reset_data( usb1__TXFILLTUNING, val_usb1__TXFILLTUNING); +set_reset_data( usb1__TXTTFILLTUNING, val_usb1__TXTTFILLTUNING); +set_reset_data( usb1__IC_USB, val_usb1__IC_USB); +set_reset_data( usb1__ULPI_VIEWPORT, val_usb1__ULPI_VIEWPORT); +set_reset_data( usb1__ENDPTNAK, val_usb1__ENDPTNAK); +set_reset_data( usb1__ENDPTNAKEN, val_usb1__ENDPTNAKEN); +set_reset_data( usb1__CONFIGFLAG, val_usb1__CONFIGFLAG); +set_reset_data( usb1__PORTSC1, val_usb1__PORTSC1); +set_reset_data( usb1__OTGSC, val_usb1__OTGSC); +set_reset_data( usb1__USBMODE, val_usb1__USBMODE); +set_reset_data( usb1__ENDPTSETUPSTAT, val_usb1__ENDPTSETUPSTAT); +set_reset_data( usb1__ENDPTPRIME, val_usb1__ENDPTPRIME); +set_reset_data( usb1__ENDPTFLUSH, val_usb1__ENDPTFLUSH); +set_reset_data( usb1__ENDPTSTAT, val_usb1__ENDPTSTAT); +set_reset_data( usb1__ENDPTCOMPLETE, val_usb1__ENDPTCOMPLETE); +set_reset_data( usb1__ENDPTCTRL0, val_usb1__ENDPTCTRL0); +set_reset_data( usb1__ENDPTCTRL1, val_usb1__ENDPTCTRL1); +set_reset_data( usb1__ENDPTCTRL2, val_usb1__ENDPTCTRL2); +set_reset_data( usb1__ENDPTCTRL3, val_usb1__ENDPTCTRL3); +set_reset_data( usb1__ENDPTCTRL4, val_usb1__ENDPTCTRL4); +set_reset_data( usb1__ENDPTCTRL5, val_usb1__ENDPTCTRL5); +set_reset_data( usb1__ENDPTCTRL6, val_usb1__ENDPTCTRL6); +set_reset_data( usb1__ENDPTCTRL7, val_usb1__ENDPTCTRL7); +set_reset_data( usb1__ENDPTCTRL8, val_usb1__ENDPTCTRL8); +set_reset_data( usb1__ENDPTCTRL9, val_usb1__ENDPTCTRL9); +set_reset_data( usb1__ENDPTCTRL10, val_usb1__ENDPTCTRL10); +set_reset_data( usb1__ENDPTCTRL11, val_usb1__ENDPTCTRL11); +set_reset_data( usb1__ENDPTCTRL12, val_usb1__ENDPTCTRL12); diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_reg_params.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_reg_params.v new file mode 100644 index 0000000..808a138 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_reg_params.v @@ -0,0 +1,10519 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_reg_params.v + * + * Date : 2012-11 + * + * Description : Parameters for Register Address and Default values. + * + *****************************************************************************/ + +// Register default value info for chip pele_ps +// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 +// 54 modules, 2532 registers. + + +// ************************************************************ +// Module afi0 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi0__AFI_RDCHAN_CTRL = 32'hF8008000; +parameter val_afi0__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi0__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi0__AFI_RDCHAN_ISSUINGCAP = 32'hF8008004; +parameter val_afi0__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi0__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi0__AFI_RDQOS = 32'hF8008008; +parameter val_afi0__AFI_RDQOS = 32'h00000000; +parameter mask_afi0__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi0__AFI_RDDATAFIFO_LEVEL = 32'hF800800C; +parameter val_afi0__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi0__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi0__AFI_RDDEBUG = 32'hF8008010; +parameter val_afi0__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi0__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi0__AFI_WRCHAN_CTRL = 32'hF8008014; +parameter val_afi0__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi0__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi0__AFI_WRCHAN_ISSUINGCAP = 32'hF8008018; +parameter val_afi0__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi0__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi0__AFI_WRQOS = 32'hF800801C; +parameter val_afi0__AFI_WRQOS = 32'h00000000; +parameter mask_afi0__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi0__AFI_WRDATAFIFO_LEVEL = 32'hF8008020; +parameter val_afi0__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi0__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi0__AFI_WRDEBUG = 32'hF8008024; +parameter val_afi0__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi0__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi1 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi1__AFI_RDCHAN_CTRL = 32'hF8009000; +parameter val_afi1__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi1__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi1__AFI_RDCHAN_ISSUINGCAP = 32'hF8009004; +parameter val_afi1__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi1__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi1__AFI_RDQOS = 32'hF8009008; +parameter val_afi1__AFI_RDQOS = 32'h00000000; +parameter mask_afi1__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi1__AFI_RDDATAFIFO_LEVEL = 32'hF800900C; +parameter val_afi1__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi1__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi1__AFI_RDDEBUG = 32'hF8009010; +parameter val_afi1__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi1__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi1__AFI_WRCHAN_CTRL = 32'hF8009014; +parameter val_afi1__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi1__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi1__AFI_WRCHAN_ISSUINGCAP = 32'hF8009018; +parameter val_afi1__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi1__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi1__AFI_WRQOS = 32'hF800901C; +parameter val_afi1__AFI_WRQOS = 32'h00000000; +parameter mask_afi1__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi1__AFI_WRDATAFIFO_LEVEL = 32'hF8009020; +parameter val_afi1__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi1__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi1__AFI_WRDEBUG = 32'hF8009024; +parameter val_afi1__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi1__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi2 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi2__AFI_RDCHAN_CTRL = 32'hF800A000; +parameter val_afi2__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi2__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi2__AFI_RDCHAN_ISSUINGCAP = 32'hF800A004; +parameter val_afi2__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi2__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi2__AFI_RDQOS = 32'hF800A008; +parameter val_afi2__AFI_RDQOS = 32'h00000000; +parameter mask_afi2__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi2__AFI_RDDATAFIFO_LEVEL = 32'hF800A00C; +parameter val_afi2__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi2__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi2__AFI_RDDEBUG = 32'hF800A010; +parameter val_afi2__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi2__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi2__AFI_WRCHAN_CTRL = 32'hF800A014; +parameter val_afi2__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi2__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi2__AFI_WRCHAN_ISSUINGCAP = 32'hF800A018; +parameter val_afi2__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi2__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi2__AFI_WRQOS = 32'hF800A01C; +parameter val_afi2__AFI_WRQOS = 32'h00000000; +parameter mask_afi2__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi2__AFI_WRDATAFIFO_LEVEL = 32'hF800A020; +parameter val_afi2__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi2__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi2__AFI_WRDEBUG = 32'hF800A024; +parameter val_afi2__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi2__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi3 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi3__AFI_RDCHAN_CTRL = 32'hF800B000; +parameter val_afi3__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi3__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi3__AFI_RDCHAN_ISSUINGCAP = 32'hF800B004; +parameter val_afi3__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi3__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi3__AFI_RDQOS = 32'hF800B008; +parameter val_afi3__AFI_RDQOS = 32'h00000000; +parameter mask_afi3__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi3__AFI_RDDATAFIFO_LEVEL = 32'hF800B00C; +parameter val_afi3__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi3__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi3__AFI_RDDEBUG = 32'hF800B010; +parameter val_afi3__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi3__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi3__AFI_WRCHAN_CTRL = 32'hF800B014; +parameter val_afi3__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi3__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi3__AFI_WRCHAN_ISSUINGCAP = 32'hF800B018; +parameter val_afi3__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi3__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi3__AFI_WRQOS = 32'hF800B01C; +parameter val_afi3__AFI_WRQOS = 32'h00000000; +parameter mask_afi3__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi3__AFI_WRDATAFIFO_LEVEL = 32'hF800B020; +parameter val_afi3__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi3__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi3__AFI_WRDEBUG = 32'hF800B024; +parameter val_afi3__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi3__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module can0 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter can0__SRR = 32'hE0008000; +parameter val_can0__SRR = 32'h00000000; +parameter mask_can0__SRR = 32'hFFFFFFFF; + +parameter can0__MSR = 32'hE0008004; +parameter val_can0__MSR = 32'h00000000; +parameter mask_can0__MSR = 32'hFFFFFFFF; + +parameter can0__BRPR = 32'hE0008008; +parameter val_can0__BRPR = 32'h00000000; +parameter mask_can0__BRPR = 32'hFFFFFFFF; + +parameter can0__BTR = 32'hE000800C; +parameter val_can0__BTR = 32'h00000000; +parameter mask_can0__BTR = 32'hFFFFFFFF; + +parameter can0__ECR = 32'hE0008010; +parameter val_can0__ECR = 32'h00000000; +parameter mask_can0__ECR = 32'hFFFFFFFF; + +parameter can0__ESR = 32'hE0008014; +parameter val_can0__ESR = 32'h00000000; +parameter mask_can0__ESR = 32'hFFFFFFFF; + +parameter can0__SR = 32'hE0008018; +parameter val_can0__SR = 32'h00000001; +parameter mask_can0__SR = 32'hFFFFFFFF; + +parameter can0__ISR = 32'hE000801C; +parameter val_can0__ISR = 32'h00006000; +parameter mask_can0__ISR = 32'hFFFFFFFF; + +parameter can0__IER = 32'hE0008020; +parameter val_can0__IER = 32'h00000000; +parameter mask_can0__IER = 32'hFFFFFFFF; + +parameter can0__ICR = 32'hE0008024; +parameter val_can0__ICR = 32'h00000000; +parameter mask_can0__ICR = 32'hFFFFFFFF; + +parameter can0__TCR = 32'hE0008028; +parameter val_can0__TCR = 32'h00000000; +parameter mask_can0__TCR = 32'hFFFFFFFF; + +parameter can0__WIR = 32'hE000802C; +parameter val_can0__WIR = 32'h00003F3F; +parameter mask_can0__WIR = 32'hFFFFFFFF; + +parameter can0__TXFIFO_ID = 32'hE0008030; +parameter val_can0__TXFIFO_ID = 32'h00000000; +parameter mask_can0__TXFIFO_ID = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DLC = 32'hE0008034; +parameter val_can0__TXFIFO_DLC = 32'h00000000; +parameter mask_can0__TXFIFO_DLC = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DATA1 = 32'hE0008038; +parameter val_can0__TXFIFO_DATA1 = 32'h00000000; +parameter mask_can0__TXFIFO_DATA1 = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DATA2 = 32'hE000803C; +parameter val_can0__TXFIFO_DATA2 = 32'h00000000; +parameter mask_can0__TXFIFO_DATA2 = 32'hFFFFFFFF; + +parameter can0__TXHPB_ID = 32'hE0008040; +parameter val_can0__TXHPB_ID = 32'h00000000; +parameter mask_can0__TXHPB_ID = 32'hFFFFFFFF; + +parameter can0__TXHPB_DLC = 32'hE0008044; +parameter val_can0__TXHPB_DLC = 32'h00000000; +parameter mask_can0__TXHPB_DLC = 32'hFFFFFFFF; + +parameter can0__TXHPB_DATA1 = 32'hE0008048; +parameter val_can0__TXHPB_DATA1 = 32'h00000000; +parameter mask_can0__TXHPB_DATA1 = 32'hFFFFFFFF; + +parameter can0__TXHPB_DATA2 = 32'hE000804C; +parameter val_can0__TXHPB_DATA2 = 32'h00000000; +parameter mask_can0__TXHPB_DATA2 = 32'hFFFFFFFF; + +parameter can0__RXFIFO_ID = 32'hE0008050; +parameter val_can0__RXFIFO_ID = 32'h00000000; +parameter mask_can0__RXFIFO_ID = 32'h00000000; + +parameter can0__RXFIFO_DLC = 32'hE0008054; +parameter val_can0__RXFIFO_DLC = 32'h00000000; +parameter mask_can0__RXFIFO_DLC = 32'h00000000; + +parameter can0__RXFIFO_DATA1 = 32'hE0008058; +parameter val_can0__RXFIFO_DATA1 = 32'h00000000; +parameter mask_can0__RXFIFO_DATA1 = 32'h00000000; + +parameter can0__RXFIFO_DATA2 = 32'hE000805C; +parameter val_can0__RXFIFO_DATA2 = 32'h00000000; +parameter mask_can0__RXFIFO_DATA2 = 32'h00000000; + +parameter can0__AFR = 32'hE0008060; +parameter val_can0__AFR = 32'h00000000; +parameter mask_can0__AFR = 32'hFFFFFFFF; + +parameter can0__AFMR1 = 32'hE0008064; +parameter val_can0__AFMR1 = 32'h00000000; +parameter mask_can0__AFMR1 = 32'h00000000; + +parameter can0__AFIR1 = 32'hE0008068; +parameter val_can0__AFIR1 = 32'h00000000; +parameter mask_can0__AFIR1 = 32'h00000000; + +parameter can0__AFMR2 = 32'hE000806C; +parameter val_can0__AFMR2 = 32'h00000000; +parameter mask_can0__AFMR2 = 32'h00000000; + +parameter can0__AFIR2 = 32'hE0008070; +parameter val_can0__AFIR2 = 32'h00000000; +parameter mask_can0__AFIR2 = 32'h00000000; + +parameter can0__AFMR3 = 32'hE0008074; +parameter val_can0__AFMR3 = 32'h00000000; +parameter mask_can0__AFMR3 = 32'h00000000; + +parameter can0__AFIR3 = 32'hE0008078; +parameter val_can0__AFIR3 = 32'h00000000; +parameter mask_can0__AFIR3 = 32'h00000000; + +parameter can0__AFMR4 = 32'hE000807C; +parameter val_can0__AFMR4 = 32'h00000000; +parameter mask_can0__AFMR4 = 32'h00000000; + +parameter can0__AFIR4 = 32'hE0008080; +parameter val_can0__AFIR4 = 32'h00000000; +parameter mask_can0__AFIR4 = 32'h00000000; + + +// ************************************************************ +// Module can1 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter can1__SRR = 32'hE0009000; +parameter val_can1__SRR = 32'h00000000; +parameter mask_can1__SRR = 32'hFFFFFFFF; + +parameter can1__MSR = 32'hE0009004; +parameter val_can1__MSR = 32'h00000000; +parameter mask_can1__MSR = 32'hFFFFFFFF; + +parameter can1__BRPR = 32'hE0009008; +parameter val_can1__BRPR = 32'h00000000; +parameter mask_can1__BRPR = 32'hFFFFFFFF; + +parameter can1__BTR = 32'hE000900C; +parameter val_can1__BTR = 32'h00000000; +parameter mask_can1__BTR = 32'hFFFFFFFF; + +parameter can1__ECR = 32'hE0009010; +parameter val_can1__ECR = 32'h00000000; +parameter mask_can1__ECR = 32'hFFFFFFFF; + +parameter can1__ESR = 32'hE0009014; +parameter val_can1__ESR = 32'h00000000; +parameter mask_can1__ESR = 32'hFFFFFFFF; + +parameter can1__SR = 32'hE0009018; +parameter val_can1__SR = 32'h00000001; +parameter mask_can1__SR = 32'hFFFFFFFF; + +parameter can1__ISR = 32'hE000901C; +parameter val_can1__ISR = 32'h00006000; +parameter mask_can1__ISR = 32'hFFFFFFFF; + +parameter can1__IER = 32'hE0009020; +parameter val_can1__IER = 32'h00000000; +parameter mask_can1__IER = 32'hFFFFFFFF; + +parameter can1__ICR = 32'hE0009024; +parameter val_can1__ICR = 32'h00000000; +parameter mask_can1__ICR = 32'hFFFFFFFF; + +parameter can1__TCR = 32'hE0009028; +parameter val_can1__TCR = 32'h00000000; +parameter mask_can1__TCR = 32'hFFFFFFFF; + +parameter can1__WIR = 32'hE000902C; +parameter val_can1__WIR = 32'h00003F3F; +parameter mask_can1__WIR = 32'hFFFFFFFF; + +parameter can1__TXFIFO_ID = 32'hE0009030; +parameter val_can1__TXFIFO_ID = 32'h00000000; +parameter mask_can1__TXFIFO_ID = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DLC = 32'hE0009034; +parameter val_can1__TXFIFO_DLC = 32'h00000000; +parameter mask_can1__TXFIFO_DLC = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DATA1 = 32'hE0009038; +parameter val_can1__TXFIFO_DATA1 = 32'h00000000; +parameter mask_can1__TXFIFO_DATA1 = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DATA2 = 32'hE000903C; +parameter val_can1__TXFIFO_DATA2 = 32'h00000000; +parameter mask_can1__TXFIFO_DATA2 = 32'hFFFFFFFF; + +parameter can1__TXHPB_ID = 32'hE0009040; +parameter val_can1__TXHPB_ID = 32'h00000000; +parameter mask_can1__TXHPB_ID = 32'hFFFFFFFF; + +parameter can1__TXHPB_DLC = 32'hE0009044; +parameter val_can1__TXHPB_DLC = 32'h00000000; +parameter mask_can1__TXHPB_DLC = 32'hFFFFFFFF; + +parameter can1__TXHPB_DATA1 = 32'hE0009048; +parameter val_can1__TXHPB_DATA1 = 32'h00000000; +parameter mask_can1__TXHPB_DATA1 = 32'hFFFFFFFF; + +parameter can1__TXHPB_DATA2 = 32'hE000904C; +parameter val_can1__TXHPB_DATA2 = 32'h00000000; +parameter mask_can1__TXHPB_DATA2 = 32'hFFFFFFFF; + +parameter can1__RXFIFO_ID = 32'hE0009050; +parameter val_can1__RXFIFO_ID = 32'h00000000; +parameter mask_can1__RXFIFO_ID = 32'h00000000; + +parameter can1__RXFIFO_DLC = 32'hE0009054; +parameter val_can1__RXFIFO_DLC = 32'h00000000; +parameter mask_can1__RXFIFO_DLC = 32'h00000000; + +parameter can1__RXFIFO_DATA1 = 32'hE0009058; +parameter val_can1__RXFIFO_DATA1 = 32'h00000000; +parameter mask_can1__RXFIFO_DATA1 = 32'h00000000; + +parameter can1__RXFIFO_DATA2 = 32'hE000905C; +parameter val_can1__RXFIFO_DATA2 = 32'h00000000; +parameter mask_can1__RXFIFO_DATA2 = 32'h00000000; + +parameter can1__AFR = 32'hE0009060; +parameter val_can1__AFR = 32'h00000000; +parameter mask_can1__AFR = 32'hFFFFFFFF; + +parameter can1__AFMR1 = 32'hE0009064; +parameter val_can1__AFMR1 = 32'h00000000; +parameter mask_can1__AFMR1 = 32'h00000000; + +parameter can1__AFIR1 = 32'hE0009068; +parameter val_can1__AFIR1 = 32'h00000000; +parameter mask_can1__AFIR1 = 32'h00000000; + +parameter can1__AFMR2 = 32'hE000906C; +parameter val_can1__AFMR2 = 32'h00000000; +parameter mask_can1__AFMR2 = 32'h00000000; + +parameter can1__AFIR2 = 32'hE0009070; +parameter val_can1__AFIR2 = 32'h00000000; +parameter mask_can1__AFIR2 = 32'h00000000; + +parameter can1__AFMR3 = 32'hE0009074; +parameter val_can1__AFMR3 = 32'h00000000; +parameter mask_can1__AFMR3 = 32'h00000000; + +parameter can1__AFIR3 = 32'hE0009078; +parameter val_can1__AFIR3 = 32'h00000000; +parameter mask_can1__AFIR3 = 32'h00000000; + +parameter can1__AFMR4 = 32'hE000907C; +parameter val_can1__AFMR4 = 32'h00000000; +parameter mask_can1__AFMR4 = 32'h00000000; + +parameter can1__AFIR4 = 32'hE0009080; +parameter val_can1__AFIR4 = 32'h00000000; +parameter mask_can1__AFIR4 = 32'h00000000; + + +// ************************************************************ +// Module ddrc ddrc +// doc version: 1.25 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ddrc__ddrc_ctrl = 32'hF8006000; +parameter val_ddrc__ddrc_ctrl = 32'h00000200; +parameter mask_ddrc__ddrc_ctrl = 32'hFFFFFFFF; + +parameter ddrc__Two_rank_cfg = 32'hF8006004; +parameter val_ddrc__Two_rank_cfg = 32'h000C1076; +parameter mask_ddrc__Two_rank_cfg = 32'h1FFFFFFF; + +parameter ddrc__HPR_reg = 32'hF8006008; +parameter val_ddrc__HPR_reg = 32'h03C0780F; +parameter mask_ddrc__HPR_reg = 32'h03FFFFFF; + +parameter ddrc__LPR_reg = 32'hF800600C; +parameter val_ddrc__LPR_reg = 32'h03C0780F; +parameter mask_ddrc__LPR_reg = 32'h03FFFFFF; + +parameter ddrc__WR_reg = 32'hF8006010; +parameter val_ddrc__WR_reg = 32'h0007F80F; +parameter mask_ddrc__WR_reg = 32'h03FFFFFF; + +parameter ddrc__DRAM_param_reg0 = 32'hF8006014; +parameter val_ddrc__DRAM_param_reg0 = 32'h00041016; +parameter mask_ddrc__DRAM_param_reg0 = 32'h001FFFFF; + +parameter ddrc__DRAM_param_reg1 = 32'hF8006018; +parameter val_ddrc__DRAM_param_reg1 = 32'h351B48D9; +parameter mask_ddrc__DRAM_param_reg1 = 32'hF7FFFFFF; + +parameter ddrc__DRAM_param_reg2 = 32'hF800601C; +parameter val_ddrc__DRAM_param_reg2 = 32'h83015904; +parameter mask_ddrc__DRAM_param_reg2 = 32'hFFFFFFFF; + +parameter ddrc__DRAM_param_reg3 = 32'hF8006020; +parameter val_ddrc__DRAM_param_reg3 = 32'h250882D0; +parameter mask_ddrc__DRAM_param_reg3 = 32'hFFFFFFFF; + +parameter ddrc__DRAM_param_reg4 = 32'hF8006024; +parameter val_ddrc__DRAM_param_reg4 = 32'h0000003C; +parameter mask_ddrc__DRAM_param_reg4 = 32'h0FFFFFFF; + +parameter ddrc__DRAM_init_param = 32'hF8006028; +parameter val_ddrc__DRAM_init_param = 32'h00002007; +parameter mask_ddrc__DRAM_init_param = 32'h00003FFF; + +parameter ddrc__DRAM_EMR_reg = 32'hF800602C; +parameter val_ddrc__DRAM_EMR_reg = 32'h00000008; +parameter mask_ddrc__DRAM_EMR_reg = 32'hFFFFFFFF; + +parameter ddrc__DRAM_EMR_MR_reg = 32'hF8006030; +parameter val_ddrc__DRAM_EMR_MR_reg = 32'h00000940; +parameter mask_ddrc__DRAM_EMR_MR_reg = 32'hFFFFFFFF; + +parameter ddrc__DRAM_burst8_rdwr = 32'hF8006034; +parameter val_ddrc__DRAM_burst8_rdwr = 32'h00020034; +parameter mask_ddrc__DRAM_burst8_rdwr = 32'h1FFFFFFF; + +parameter ddrc__DRAM_disable_DQ = 32'hF8006038; +parameter val_ddrc__DRAM_disable_DQ = 32'h00000000; +parameter mask_ddrc__DRAM_disable_DQ = 32'h00001FFF; + +parameter ddrc__DRAM_addr_map_bank = 32'hF800603C; +parameter val_ddrc__DRAM_addr_map_bank = 32'h00000F77; +parameter mask_ddrc__DRAM_addr_map_bank = 32'h000FFFFF; + +parameter ddrc__DRAM_addr_map_col = 32'hF8006040; +parameter val_ddrc__DRAM_addr_map_col = 32'hFFF00000; +parameter mask_ddrc__DRAM_addr_map_col = 32'hFFFFFFFF; + +parameter ddrc__DRAM_addr_map_row = 32'hF8006044; +parameter val_ddrc__DRAM_addr_map_row = 32'h0FF55555; +parameter mask_ddrc__DRAM_addr_map_row = 32'h0FFFFFFF; + +parameter ddrc__DRAM_ODT_reg = 32'hF8006048; +parameter val_ddrc__DRAM_ODT_reg = 32'h00000249; +parameter mask_ddrc__DRAM_ODT_reg = 32'h3FFFFFFF; + +parameter ddrc__phy_dbg_reg = 32'hF800604C; +parameter val_ddrc__phy_dbg_reg = 32'h00000000; +parameter mask_ddrc__phy_dbg_reg = 32'h000FFFFF; + +parameter ddrc__phy_cmd_timeout_rddata_cpt = 32'hF8006050; +parameter val_ddrc__phy_cmd_timeout_rddata_cpt = 32'h00010200; +parameter mask_ddrc__phy_cmd_timeout_rddata_cpt = 32'hFFFFFFFF; + +parameter ddrc__mode_sts_reg = 32'hF8006054; +parameter val_ddrc__mode_sts_reg = 32'h00000000; +parameter mask_ddrc__mode_sts_reg = 32'h001FFFFF; + +parameter ddrc__DLL_calib = 32'hF8006058; +parameter val_ddrc__DLL_calib = 32'h00000101; +parameter mask_ddrc__DLL_calib = 32'h0001FFFF; + +parameter ddrc__ODT_delay_hold = 32'hF800605C; +parameter val_ddrc__ODT_delay_hold = 32'h00000023; +parameter mask_ddrc__ODT_delay_hold = 32'h0000FFFF; + +parameter ddrc__ctrl_reg1 = 32'hF8006060; +parameter val_ddrc__ctrl_reg1 = 32'h0000003E; +parameter mask_ddrc__ctrl_reg1 = 32'h00001FFF; + +parameter ddrc__ctrl_reg2 = 32'hF8006064; +parameter val_ddrc__ctrl_reg2 = 32'h00020000; +parameter mask_ddrc__ctrl_reg2 = 32'h0003FFFF; + +parameter ddrc__ctrl_reg3 = 32'hF8006068; +parameter val_ddrc__ctrl_reg3 = 32'h00284027; +parameter mask_ddrc__ctrl_reg3 = 32'h03FFFFFF; + +parameter ddrc__ctrl_reg4 = 32'hF800606C; +parameter val_ddrc__ctrl_reg4 = 32'h00001610; +parameter mask_ddrc__ctrl_reg4 = 32'h0000FFFF; + +parameter ddrc__ctrl_reg5 = 32'hF8006078; +parameter val_ddrc__ctrl_reg5 = 32'h00455111; +parameter mask_ddrc__ctrl_reg5 = 32'hFFFFFFFF; + +parameter ddrc__ctrl_reg6 = 32'hF800607C; +parameter val_ddrc__ctrl_reg6 = 32'h00032222; +parameter mask_ddrc__ctrl_reg6 = 32'hFFFFFFFF; + +parameter ddrc__CHE_REFRESH_TIMER01 = 32'hF80060A0; +parameter val_ddrc__CHE_REFRESH_TIMER01 = 32'h00008000; +parameter mask_ddrc__CHE_REFRESH_TIMER01 = 32'h00FFFFFF; + +parameter ddrc__CHE_T_ZQ = 32'hF80060A4; +parameter val_ddrc__CHE_T_ZQ = 32'h10300802; +parameter mask_ddrc__CHE_T_ZQ = 32'hFFFFFFFF; + +parameter ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'hF80060A8; +parameter val_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0020003A; +parameter mask_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0FFFFFFF; + +parameter ddrc__deep_pwrdwn_reg = 32'hF80060AC; +parameter val_ddrc__deep_pwrdwn_reg = 32'h00000000; +parameter mask_ddrc__deep_pwrdwn_reg = 32'h000001FF; + +parameter ddrc__reg_2c = 32'hF80060B0; +parameter val_ddrc__reg_2c = 32'h00000000; +parameter mask_ddrc__reg_2c = 32'h1FFFFFFF; + +parameter ddrc__reg_2d = 32'hF80060B4; +parameter val_ddrc__reg_2d = 32'h00000200; +parameter mask_ddrc__reg_2d = 32'h000007FF; + +parameter ddrc__dfi_timing = 32'hF80060B8; +parameter val_ddrc__dfi_timing = 32'h00200067; +parameter mask_ddrc__dfi_timing = 32'h01FFFFFF; + +parameter ddrc__refresh_timer_2 = 32'hF80060BC; +parameter val_ddrc__refresh_timer_2 = 32'h00000000; +parameter mask_ddrc__refresh_timer_2 = 32'h00FFFFFF; + +parameter ddrc__nc_timing = 32'hF80060C0; +parameter val_ddrc__nc_timing = 32'h00000000; +parameter mask_ddrc__nc_timing = 32'h003FFFFF; + +parameter ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'hF80060C4; +parameter val_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000003; + +parameter ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'hF80060C8; +parameter val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'hF80060CC; +parameter val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060D0; +parameter val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060D4; +parameter val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060D8; +parameter val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'hF80060DC; +parameter val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000001; + +parameter ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'hF80060E0; +parameter val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060E4; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060E8; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060EC; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_ECC_STATS_REG_OFFSET = 32'hF80060F0; +parameter val_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h0000FFFF; + +parameter ddrc__ECC_scrub = 32'hF80060F4; +parameter val_ddrc__ECC_scrub = 32'h00000008; +parameter mask_ddrc__ECC_scrub = 32'h0000000F; + +parameter ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hF80060F8; +parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hF80060FC; +parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__phy_rcvr_enable = 32'hF8006114; +parameter val_ddrc__phy_rcvr_enable = 32'h00000000; +parameter mask_ddrc__phy_rcvr_enable = 32'h000000FF; + +parameter ddrc__PHY_Config0 = 32'hF8006118; +parameter val_ddrc__PHY_Config0 = 32'h40000001; +parameter mask_ddrc__PHY_Config0 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config1 = 32'hF800611C; +parameter val_ddrc__PHY_Config1 = 32'h40000001; +parameter mask_ddrc__PHY_Config1 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config2 = 32'hF8006120; +parameter val_ddrc__PHY_Config2 = 32'h40000001; +parameter mask_ddrc__PHY_Config2 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config3 = 32'hF8006124; +parameter val_ddrc__PHY_Config3 = 32'h40000001; +parameter mask_ddrc__PHY_Config3 = 32'h7FFFFFFF; + +parameter ddrc__phy_init_ratio0 = 32'hF800612C; +parameter val_ddrc__phy_init_ratio0 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio0 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio1 = 32'hF8006130; +parameter val_ddrc__phy_init_ratio1 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio1 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio2 = 32'hF8006134; +parameter val_ddrc__phy_init_ratio2 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio2 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio3 = 32'hF8006138; +parameter val_ddrc__phy_init_ratio3 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio3 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg0 = 32'hF8006140; +parameter val_ddrc__phy_rd_dqs_cfg0 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg0 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg1 = 32'hF8006144; +parameter val_ddrc__phy_rd_dqs_cfg1 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg1 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg2 = 32'hF8006148; +parameter val_ddrc__phy_rd_dqs_cfg2 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg2 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg3 = 32'hF800614C; +parameter val_ddrc__phy_rd_dqs_cfg3 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg3 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg0 = 32'hF8006154; +parameter val_ddrc__phy_wr_dqs_cfg0 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg0 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg1 = 32'hF8006158; +parameter val_ddrc__phy_wr_dqs_cfg1 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg1 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg2 = 32'hF800615C; +parameter val_ddrc__phy_wr_dqs_cfg2 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg2 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg3 = 32'hF8006160; +parameter val_ddrc__phy_wr_dqs_cfg3 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg3 = 32'h000FFFFF; + +parameter ddrc__phy_we_cfg0 = 32'hF8006168; +parameter val_ddrc__phy_we_cfg0 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg0 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg1 = 32'hF800616C; +parameter val_ddrc__phy_we_cfg1 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg1 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg2 = 32'hF8006170; +parameter val_ddrc__phy_we_cfg2 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg2 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg3 = 32'hF8006174; +parameter val_ddrc__phy_we_cfg3 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg3 = 32'h001FFFFF; + +parameter ddrc__wr_data_slv0 = 32'hF800617C; +parameter val_ddrc__wr_data_slv0 = 32'h00000080; +parameter mask_ddrc__wr_data_slv0 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv1 = 32'hF8006180; +parameter val_ddrc__wr_data_slv1 = 32'h00000080; +parameter mask_ddrc__wr_data_slv1 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv2 = 32'hF8006184; +parameter val_ddrc__wr_data_slv2 = 32'h00000080; +parameter mask_ddrc__wr_data_slv2 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv3 = 32'hF8006188; +parameter val_ddrc__wr_data_slv3 = 32'h00000080; +parameter mask_ddrc__wr_data_slv3 = 32'h000FFFFF; + +parameter ddrc__reg_64 = 32'hF8006190; +parameter val_ddrc__reg_64 = 32'h10020000; +parameter mask_ddrc__reg_64 = 32'hFFFFFFFF; + +parameter ddrc__reg_65 = 32'hF8006194; +parameter val_ddrc__reg_65 = 32'h00000000; +parameter mask_ddrc__reg_65 = 32'h000FFFFF; + +parameter ddrc__reg69_6a0 = 32'hF80061A4; +parameter val_ddrc__reg69_6a0 = 32'h000F0000; +parameter mask_ddrc__reg69_6a0 = 32'h1FFFFFFF; + +parameter ddrc__reg69_6a1 = 32'hF80061A8; +parameter val_ddrc__reg69_6a1 = 32'h000F0000; +parameter mask_ddrc__reg69_6a1 = 32'h1FFFFFFF; + +parameter ddrc__reg6c_6d2 = 32'hF80061B0; +parameter val_ddrc__reg6c_6d2 = 32'h000F0000; +parameter mask_ddrc__reg6c_6d2 = 32'h1FFFFFFF; + +parameter ddrc__reg6c_6d3 = 32'hF80061B4; +parameter val_ddrc__reg6c_6d3 = 32'h000F0000; +parameter mask_ddrc__reg6c_6d3 = 32'h1FFFFFFF; + +parameter ddrc__reg6e_710 = 32'hF80061B8; +parameter val_ddrc__reg6e_710 = 32'h00000000; +parameter mask_ddrc__reg6e_710 = 32'h00000000; + +parameter ddrc__reg6e_711 = 32'hF80061BC; +parameter val_ddrc__reg6e_711 = 32'h00000000; +parameter mask_ddrc__reg6e_711 = 32'h00000000; + +parameter ddrc__reg6e_712 = 32'hF80061C0; +parameter val_ddrc__reg6e_712 = 32'h00000000; +parameter mask_ddrc__reg6e_712 = 32'h00000000; + +parameter ddrc__reg6e_713 = 32'hF80061C4; +parameter val_ddrc__reg6e_713 = 32'h00000000; +parameter mask_ddrc__reg6e_713 = 32'h00000000; + +parameter ddrc__phy_dll_sts0 = 32'hF80061CC; +parameter val_ddrc__phy_dll_sts0 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts0 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts1 = 32'hF80061D0; +parameter val_ddrc__phy_dll_sts1 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts1 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts2 = 32'hF80061D4; +parameter val_ddrc__phy_dll_sts2 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts2 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts3 = 32'hF80061D8; +parameter val_ddrc__phy_dll_sts3 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts3 = 32'h07FFFFFF; + +parameter ddrc__dll_lock_sts = 32'hF80061E0; +parameter val_ddrc__dll_lock_sts = 32'h00000000; +parameter mask_ddrc__dll_lock_sts = 32'h00FFFFFF; + +parameter ddrc__phy_ctrl_sts = 32'hF80061E4; +parameter val_ddrc__phy_ctrl_sts = 32'h00000000; +parameter mask_ddrc__phy_ctrl_sts = 32'h3FF80000; + +parameter ddrc__phy_ctrl_sts_reg2 = 32'hF80061E8; +parameter val_ddrc__phy_ctrl_sts_reg2 = 32'h00000000; +parameter mask_ddrc__phy_ctrl_sts_reg2 = 32'h07FFFFFF; + +parameter ddrc__axi_id = 32'hF8006200; +parameter val_ddrc__axi_id = 32'h00153042; +parameter mask_ddrc__axi_id = 32'h03FFFFFF; + +parameter ddrc__page_mask = 32'hF8006204; +parameter val_ddrc__page_mask = 32'h00000000; +parameter mask_ddrc__page_mask = 32'hFFFFFFFF; + +parameter ddrc__axi_priority_wr_port0 = 32'hF8006208; +parameter val_ddrc__axi_priority_wr_port0 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port0 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port1 = 32'hF800620C; +parameter val_ddrc__axi_priority_wr_port1 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port1 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port2 = 32'hF8006210; +parameter val_ddrc__axi_priority_wr_port2 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port2 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port3 = 32'hF8006214; +parameter val_ddrc__axi_priority_wr_port3 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port3 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port0 = 32'hF8006218; +parameter val_ddrc__axi_priority_rd_port0 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port0 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port1 = 32'hF800621C; +parameter val_ddrc__axi_priority_rd_port1 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port1 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port2 = 32'hF8006220; +parameter val_ddrc__axi_priority_rd_port2 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port2 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port3 = 32'hF8006224; +parameter val_ddrc__axi_priority_rd_port3 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port3 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg0 = 32'hF8006248; +parameter val_ddrc__AHB_priority_cfg0 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg0 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg1 = 32'hF800624C; +parameter val_ddrc__AHB_priority_cfg1 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg1 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg2 = 32'hF8006250; +parameter val_ddrc__AHB_priority_cfg2 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg2 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg3 = 32'hF8006254; +parameter val_ddrc__AHB_priority_cfg3 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg3 = 32'h000FFFFF; + +parameter ddrc__perf_mon0 = 32'hF8006260; +parameter val_ddrc__perf_mon0 = 32'h00000000; +parameter mask_ddrc__perf_mon0 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon1 = 32'hF8006264; +parameter val_ddrc__perf_mon1 = 32'h00000000; +parameter mask_ddrc__perf_mon1 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon2 = 32'hF8006268; +parameter val_ddrc__perf_mon2 = 32'h00000000; +parameter mask_ddrc__perf_mon2 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon3 = 32'hF800626C; +parameter val_ddrc__perf_mon3 = 32'h00000000; +parameter mask_ddrc__perf_mon3 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon20 = 32'hF8006270; +parameter val_ddrc__perf_mon20 = 32'h00000000; +parameter mask_ddrc__perf_mon20 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon21 = 32'hF8006274; +parameter val_ddrc__perf_mon21 = 32'h00000000; +parameter mask_ddrc__perf_mon21 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon22 = 32'hF8006278; +parameter val_ddrc__perf_mon22 = 32'h00000000; +parameter mask_ddrc__perf_mon22 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon23 = 32'hF800627C; +parameter val_ddrc__perf_mon23 = 32'h00000000; +parameter mask_ddrc__perf_mon23 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon30 = 32'hF8006280; +parameter val_ddrc__perf_mon30 = 32'h00000000; +parameter mask_ddrc__perf_mon30 = 32'h0000FFFF; + +parameter ddrc__perf_mon31 = 32'hF8006284; +parameter val_ddrc__perf_mon31 = 32'h00000000; +parameter mask_ddrc__perf_mon31 = 32'h0000FFFF; + +parameter ddrc__perf_mon32 = 32'hF8006288; +parameter val_ddrc__perf_mon32 = 32'h00000000; +parameter mask_ddrc__perf_mon32 = 32'h0000FFFF; + +parameter ddrc__perf_mon33 = 32'hF800628C; +parameter val_ddrc__perf_mon33 = 32'h00000000; +parameter mask_ddrc__perf_mon33 = 32'h0000FFFF; + +parameter ddrc__trusted_mem_cfg = 32'hF8006290; +parameter val_ddrc__trusted_mem_cfg = 32'h00000000; +parameter mask_ddrc__trusted_mem_cfg = 32'h0000FFFF; + +parameter ddrc__excl_access_cfg0 = 32'hF8006294; +parameter val_ddrc__excl_access_cfg0 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg0 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg1 = 32'hF8006298; +parameter val_ddrc__excl_access_cfg1 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg1 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg2 = 32'hF800629C; +parameter val_ddrc__excl_access_cfg2 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg2 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg3 = 32'hF80062A0; +parameter val_ddrc__excl_access_cfg3 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg3 = 32'h0003FFFF; + +parameter ddrc__mode_reg_read = 32'hF80062A4; +parameter val_ddrc__mode_reg_read = 32'h00000000; +parameter mask_ddrc__mode_reg_read = 32'hFFFFFFFF; + +parameter ddrc__lpddr_ctrl0 = 32'hF80062A8; +parameter val_ddrc__lpddr_ctrl0 = 32'h00000000; +parameter mask_ddrc__lpddr_ctrl0 = 32'h00000FFF; + +parameter ddrc__lpddr_ctrl1 = 32'hF80062AC; +parameter val_ddrc__lpddr_ctrl1 = 32'h00000000; +parameter mask_ddrc__lpddr_ctrl1 = 32'hFFFFFFFF; + +parameter ddrc__lpddr_ctrl2 = 32'hF80062B0; +parameter val_ddrc__lpddr_ctrl2 = 32'h003C0015; +parameter mask_ddrc__lpddr_ctrl2 = 32'h003FFFFF; + +parameter ddrc__lpddr_ctrl3 = 32'hF80062B4; +parameter val_ddrc__lpddr_ctrl3 = 32'h00000601; +parameter mask_ddrc__lpddr_ctrl3 = 32'h0003FFFF; + +parameter ddrc__phy_wr_lvl_fsm = 32'hF80062B8; +parameter val_ddrc__phy_wr_lvl_fsm = 32'h00004444; +parameter mask_ddrc__phy_wr_lvl_fsm = 32'h00007FFF; + +parameter ddrc__phy_rd_lvl_fsm = 32'hF80062BC; +parameter val_ddrc__phy_rd_lvl_fsm = 32'h00008888; +parameter mask_ddrc__phy_rd_lvl_fsm = 32'h0000FFFF; + +parameter ddrc__phy_gate_lvl_fsm = 32'hF80062C0; +parameter val_ddrc__phy_gate_lvl_fsm = 32'h00004444; +parameter mask_ddrc__phy_gate_lvl_fsm = 32'h00007FFF; + + +// ************************************************************ +// Module debug_axim axim +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_axim__GLOBAL_CTRL = 32'hF880C000; +parameter val_debug_axim__GLOBAL_CTRL = 32'h00000002; +parameter mask_debug_axim__GLOBAL_CTRL = 32'h00000003; + +parameter debug_axim__GLOBAL_STATUS = 32'hF880C004; +parameter val_debug_axim__GLOBAL_STATUS = 32'h00001000; +parameter mask_debug_axim__GLOBAL_STATUS = 32'h00001FC3; + +parameter debug_axim__FILTER_CTRL = 32'hF880C010; +parameter val_debug_axim__FILTER_CTRL = 32'h00000000; +parameter mask_debug_axim__FILTER_CTRL = 32'h0000007F; + +parameter debug_axim__TRIGGER_CTRL = 32'hF880C020; +parameter val_debug_axim__TRIGGER_CTRL = 32'h00000000; +parameter mask_debug_axim__TRIGGER_CTRL = 32'h0000FFFF; + +parameter debug_axim__TRIGGER_STATUS = 32'hF880C024; +parameter val_debug_axim__TRIGGER_STATUS = 32'h00000000; +parameter mask_debug_axim__TRIGGER_STATUS = 32'h00000003; + +parameter debug_axim__PACKET_CTRL = 32'hF880C030; +parameter val_debug_axim__PACKET_CTRL = 32'h00070000; +parameter mask_debug_axim__PACKET_CTRL = 32'h0007FFFF; + +parameter debug_axim__TOUT_CTRL = 32'hF880C040; +parameter val_debug_axim__TOUT_CTRL = 32'h00000000; +parameter mask_debug_axim__TOUT_CTRL = 32'h0000007F; + +parameter debug_axim__TOUT_THRESH = 32'hF880C044; +parameter val_debug_axim__TOUT_THRESH = 32'h00008000; +parameter mask_debug_axim__TOUT_THRESH = 32'hFFFFFFFF; + +parameter debug_axim__FIFO_CURRENT = 32'hF880C050; +parameter val_debug_axim__FIFO_CURRENT = 32'h80000000; +parameter mask_debug_axim__FIFO_CURRENT = 32'hFFFFFFFF; + +parameter debug_axim__FIFO_HYSTER = 32'hF880C054; +parameter val_debug_axim__FIFO_HYSTER = 32'h00000100; +parameter mask_debug_axim__FIFO_HYSTER = 32'h000003FF; + +parameter debug_axim__SYNC_CURRENT = 32'hF880C060; +parameter val_debug_axim__SYNC_CURRENT = 32'h00000000; +parameter mask_debug_axim__SYNC_CURRENT = 32'h00000FFF; + +parameter debug_axim__SYNC_RELOAD = 32'hF880C064; +parameter val_debug_axim__SYNC_RELOAD = 32'h00000800; +parameter mask_debug_axim__SYNC_RELOAD = 32'h00000FFF; + +parameter debug_axim__TSTMP_CURRENT = 32'hF880C070; +parameter val_debug_axim__TSTMP_CURRENT = 32'h00000000; +parameter mask_debug_axim__TSTMP_CURRENT = 32'h00000000; + +parameter debug_axim__ADDR0_MASK = 32'hF880C200; +parameter val_debug_axim__ADDR0_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR0_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_LOWER = 32'hF880C204; +parameter val_debug_axim__ADDR0_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR0_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_UPPER = 32'hF880C208; +parameter val_debug_axim__ADDR0_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR0_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_MISC = 32'hF880C20C; +parameter val_debug_axim__ADDR0_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR0_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR1_MASK = 32'hF880C210; +parameter val_debug_axim__ADDR1_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR1_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_LOWER = 32'hF880C214; +parameter val_debug_axim__ADDR1_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR1_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_UPPER = 32'hF880C218; +parameter val_debug_axim__ADDR1_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR1_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_MISC = 32'hF880C21C; +parameter val_debug_axim__ADDR1_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR1_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR2_MASK = 32'hF880C220; +parameter val_debug_axim__ADDR2_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR2_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_LOWER = 32'hF880C224; +parameter val_debug_axim__ADDR2_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR2_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_UPPER = 32'hF880C228; +parameter val_debug_axim__ADDR2_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR2_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_MISC = 32'hF880C22C; +parameter val_debug_axim__ADDR2_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR2_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR3_MASK = 32'hF880C230; +parameter val_debug_axim__ADDR3_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR3_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_LOWER = 32'hF880C234; +parameter val_debug_axim__ADDR3_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR3_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_UPPER = 32'hF880C238; +parameter val_debug_axim__ADDR3_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR3_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_MISC = 32'hF880C23C; +parameter val_debug_axim__ADDR3_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR3_MISC = 32'h00007FFF; + +parameter debug_axim__ID0_MASK = 32'hF880C300; +parameter val_debug_axim__ID0_MASK = 32'h000003FF; +parameter mask_debug_axim__ID0_MASK = 32'h000003FF; + +parameter debug_axim__ID0_LOWER = 32'hF880C304; +parameter val_debug_axim__ID0_LOWER = 32'h00000000; +parameter mask_debug_axim__ID0_LOWER = 32'h000003FF; + +parameter debug_axim__ID0_UPPER = 32'hF880C308; +parameter val_debug_axim__ID0_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID0_UPPER = 32'h000003FF; + +parameter debug_axim__ID0_MISC = 32'hF880C30C; +parameter val_debug_axim__ID0_MISC = 32'h00000000; +parameter mask_debug_axim__ID0_MISC = 32'h00003FFF; + +parameter debug_axim__ID1_MASK = 32'hF880C310; +parameter val_debug_axim__ID1_MASK = 32'h000003FF; +parameter mask_debug_axim__ID1_MASK = 32'h000003FF; + +parameter debug_axim__ID1_LOWER = 32'hF880C314; +parameter val_debug_axim__ID1_LOWER = 32'h00000000; +parameter mask_debug_axim__ID1_LOWER = 32'h000003FF; + +parameter debug_axim__ID1_UPPER = 32'hF880C318; +parameter val_debug_axim__ID1_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID1_UPPER = 32'h000003FF; + +parameter debug_axim__ID1_MISC = 32'hF880C31C; +parameter val_debug_axim__ID1_MISC = 32'h00000000; +parameter mask_debug_axim__ID1_MISC = 32'h00003FFF; + +parameter debug_axim__ID2_MASK = 32'hF880C320; +parameter val_debug_axim__ID2_MASK = 32'h000003FF; +parameter mask_debug_axim__ID2_MASK = 32'h000003FF; + +parameter debug_axim__ID2_LOWER = 32'hF880C324; +parameter val_debug_axim__ID2_LOWER = 32'h00000000; +parameter mask_debug_axim__ID2_LOWER = 32'h000003FF; + +parameter debug_axim__ID2_UPPER = 32'hF880C328; +parameter val_debug_axim__ID2_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID2_UPPER = 32'h000003FF; + +parameter debug_axim__ID2_MISC = 32'hF880C32C; +parameter val_debug_axim__ID2_MISC = 32'h00000000; +parameter mask_debug_axim__ID2_MISC = 32'h00003FFF; + +parameter debug_axim__ID3_MASK = 32'hF880C330; +parameter val_debug_axim__ID3_MASK = 32'h000003FF; +parameter mask_debug_axim__ID3_MASK = 32'h000003FF; + +parameter debug_axim__ID3_LOWER = 32'hF880C334; +parameter val_debug_axim__ID3_LOWER = 32'h00000000; +parameter mask_debug_axim__ID3_LOWER = 32'h000003FF; + +parameter debug_axim__ID3_UPPER = 32'hF880C338; +parameter val_debug_axim__ID3_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID3_UPPER = 32'h000003FF; + +parameter debug_axim__ID3_MISC = 32'hF880C33C; +parameter val_debug_axim__ID3_MISC = 32'h00000000; +parameter mask_debug_axim__ID3_MISC = 32'h00003FFF; + +parameter debug_axim__AXI_SEL = 32'hF880C800; +parameter val_debug_axim__AXI_SEL = 32'h00000000; +parameter mask_debug_axim__AXI_SEL = 32'h00000007; + +parameter debug_axim__IT_TRIGOUT = 32'hF880CED0; +parameter val_debug_axim__IT_TRIGOUT = 32'h00000000; +parameter mask_debug_axim__IT_TRIGOUT = 32'h00000001; + +parameter debug_axim__IT_TRIGOUTACK = 32'hF880CED4; +parameter val_debug_axim__IT_TRIGOUTACK = 32'h00000000; +parameter mask_debug_axim__IT_TRIGOUTACK = 32'h00000000; + +parameter debug_axim__IT_TRIGIN = 32'hF880CED8; +parameter val_debug_axim__IT_TRIGIN = 32'h00000000; +parameter mask_debug_axim__IT_TRIGIN = 32'h00000000; + +parameter debug_axim__IT_TRIGINACK = 32'hF880CEDC; +parameter val_debug_axim__IT_TRIGINACK = 32'h00000000; +parameter mask_debug_axim__IT_TRIGINACK = 32'h00000001; + +parameter debug_axim__IT_ATBDATA = 32'hF880CEEC; +parameter val_debug_axim__IT_ATBDATA = 32'h00000000; +parameter mask_debug_axim__IT_ATBDATA = 32'h0000001F; + +parameter debug_axim__IT_ATBSTATUS = 32'hF880CEF0; +parameter val_debug_axim__IT_ATBSTATUS = 32'h00000000; +parameter mask_debug_axim__IT_ATBSTATUS = 32'h00000000; + +parameter debug_axim__IT_ATBCTRL1 = 32'hF880CEF4; +parameter val_debug_axim__IT_ATBCTRL1 = 32'h00000000; +parameter mask_debug_axim__IT_ATBCTRL1 = 32'h0000007F; + +parameter debug_axim__IT_ATBCTRL0 = 32'hF880CEF8; +parameter val_debug_axim__IT_ATBCTRL0 = 32'h00000000; +parameter mask_debug_axim__IT_ATBCTRL0 = 32'h000003FF; + +parameter debug_axim__IT_CTRL = 32'hF880CF00; +parameter val_debug_axim__IT_CTRL = 32'h00000000; +parameter mask_debug_axim__IT_CTRL = 32'h00000001; + +parameter debug_axim__CLAIM_SET = 32'hF880CFA0; +parameter val_debug_axim__CLAIM_SET = 32'h00000001; +parameter mask_debug_axim__CLAIM_SET = 32'h0000000F; + +parameter debug_axim__CLAIM_CLEAR = 32'hF880CFA4; +parameter val_debug_axim__CLAIM_CLEAR = 32'h00000000; +parameter mask_debug_axim__CLAIM_CLEAR = 32'h0000000F; + +parameter debug_axim__LOCK_ACCESS = 32'hF880CFB0; +parameter val_debug_axim__LOCK_ACCESS = 32'h00000000; +parameter mask_debug_axim__LOCK_ACCESS = 32'hFFFFFFFF; + +parameter debug_axim__LOCK_STATUS = 32'hF880CFB4; +parameter val_debug_axim__LOCK_STATUS = 32'h00000003; +parameter mask_debug_axim__LOCK_STATUS = 32'h00000007; + +parameter debug_axim__AUTH_STATUS = 32'hF880CFB8; +parameter val_debug_axim__AUTH_STATUS = 32'h00000000; +parameter mask_debug_axim__AUTH_STATUS = 32'h00000033; + +parameter debug_axim__DEV_ID = 32'hF880CFC8; +parameter val_debug_axim__DEV_ID = 32'h00000000; +parameter mask_debug_axim__DEV_ID = 32'hFFFFFFFF; + +parameter debug_axim__DEV_TYPE = 32'hF880CFCC; +parameter val_debug_axim__DEV_TYPE = 32'h00000043; +parameter mask_debug_axim__DEV_TYPE = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID4 = 32'hF880CFD0; +parameter val_debug_axim__PERIPHID4 = 32'h00000003; +parameter mask_debug_axim__PERIPHID4 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID5 = 32'hF880CFD4; +parameter val_debug_axim__PERIPHID5 = 32'h00000000; +parameter mask_debug_axim__PERIPHID5 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID6 = 32'hF880CFD8; +parameter val_debug_axim__PERIPHID6 = 32'h00000000; +parameter mask_debug_axim__PERIPHID6 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID7 = 32'hF880CFDC; +parameter val_debug_axim__PERIPHID7 = 32'h00000000; +parameter mask_debug_axim__PERIPHID7 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID0 = 32'hF880CFE0; +parameter val_debug_axim__PERIPHID0 = 32'h000000B2; +parameter mask_debug_axim__PERIPHID0 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID1 = 32'hF880CFE4; +parameter val_debug_axim__PERIPHID1 = 32'h00000093; +parameter mask_debug_axim__PERIPHID1 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID2 = 32'hF880CFE8; +parameter val_debug_axim__PERIPHID2 = 32'h00000008; +parameter mask_debug_axim__PERIPHID2 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID3 = 32'hF880CFEC; +parameter val_debug_axim__PERIPHID3 = 32'h00000002; +parameter mask_debug_axim__PERIPHID3 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID0 = 32'hF880CFF0; +parameter val_debug_axim__COMPID0 = 32'h0000000D; +parameter mask_debug_axim__COMPID0 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID1 = 32'hF880CFF4; +parameter val_debug_axim__COMPID1 = 32'h00000090; +parameter mask_debug_axim__COMPID1 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID2 = 32'hF880CFF8; +parameter val_debug_axim__COMPID2 = 32'h00000005; +parameter mask_debug_axim__COMPID2 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID3 = 32'hF880CFFC; +parameter val_debug_axim__COMPID3 = 32'h000000B1; +parameter mask_debug_axim__COMPID3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_cti0 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_cti0__CTICONTROL = 32'hF8898000; +parameter val_debug_cpu_cti0__CTICONTROL = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICONTROL = 32'h00000001; + +parameter debug_cpu_cti0__CTIINTACK = 32'hF8898010; +parameter val_debug_cpu_cti0__CTIINTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINTACK = 32'h000000FF; + +parameter debug_cpu_cti0__CTIAPPSET = 32'hF8898014; +parameter val_debug_cpu_cti0__CTIAPPSET = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPSET = 32'h0000000F; + +parameter debug_cpu_cti0__CTIAPPCLEAR = 32'hF8898018; +parameter val_debug_cpu_cti0__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cpu_cti0__CTIAPPPULSE = 32'hF889801C; +parameter val_debug_cpu_cti0__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN0 = 32'hF8898020; +parameter val_debug_cpu_cti0__CTIINEN0 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN0 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN1 = 32'hF8898024; +parameter val_debug_cpu_cti0__CTIINEN1 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN1 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN2 = 32'hF8898028; +parameter val_debug_cpu_cti0__CTIINEN2 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN2 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN3 = 32'hF889802C; +parameter val_debug_cpu_cti0__CTIINEN3 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN3 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN4 = 32'hF8898030; +parameter val_debug_cpu_cti0__CTIINEN4 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN4 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN5 = 32'hF8898034; +parameter val_debug_cpu_cti0__CTIINEN5 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN5 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN6 = 32'hF8898038; +parameter val_debug_cpu_cti0__CTIINEN6 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN6 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN7 = 32'hF889803C; +parameter val_debug_cpu_cti0__CTIINEN7 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN7 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN0 = 32'hF88980A0; +parameter val_debug_cpu_cti0__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN1 = 32'hF88980A4; +parameter val_debug_cpu_cti0__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN2 = 32'hF88980A8; +parameter val_debug_cpu_cti0__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN3 = 32'hF88980AC; +parameter val_debug_cpu_cti0__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN4 = 32'hF88980B0; +parameter val_debug_cpu_cti0__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN5 = 32'hF88980B4; +parameter val_debug_cpu_cti0__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN6 = 32'hF88980B8; +parameter val_debug_cpu_cti0__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN7 = 32'hF88980BC; +parameter val_debug_cpu_cti0__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cpu_cti0__CTITRIGINSTATUS = 32'hF8898130; +parameter val_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cpu_cti0__CTITRIGOUTSTATUS = 32'hF8898134; +parameter val_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cpu_cti0__CTICHINSTATUS = 32'hF8898138; +parameter val_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; + +parameter debug_cpu_cti0__CTICHOUTSTATUS = 32'hF889813C; +parameter val_debug_cpu_cti0__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cpu_cti0__CTIGATE = 32'hF8898140; +parameter val_debug_cpu_cti0__CTIGATE = 32'h0000000F; +parameter mask_debug_cpu_cti0__CTIGATE = 32'h0000000F; + +parameter debug_cpu_cti0__ASICCTL = 32'hF8898144; +parameter val_debug_cpu_cti0__ASICCTL = 32'h00000000; +parameter mask_debug_cpu_cti0__ASICCTL = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHINACK = 32'hF8898EDC; +parameter val_debug_cpu_cti0__ITCHINACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHINACK = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGINACK = 32'hF8898EE0; +parameter val_debug_cpu_cti0__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGINACK = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHOUT = 32'hF8898EE4; +parameter val_debug_cpu_cti0__ITCHOUT = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHOUT = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGOUT = 32'hF8898EE8; +parameter val_debug_cpu_cti0__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGOUT = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHOUTACK = 32'hF8898EEC; +parameter val_debug_cpu_cti0__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHOUTACK = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGOUTACK = 32'hF8898EF0; +parameter val_debug_cpu_cti0__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHIN = 32'hF8898EF4; +parameter val_debug_cpu_cti0__ITCHIN = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHIN = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGIN = 32'hF8898EF8; +parameter val_debug_cpu_cti0__ITTRIGIN = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGIN = 32'h000000FF; + +parameter debug_cpu_cti0__ITCTRL = 32'hF8898F00; +parameter val_debug_cpu_cti0__ITCTRL = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCTRL = 32'h00000001; + +parameter debug_cpu_cti0__CTSR = 32'hF8898FA0; +parameter val_debug_cpu_cti0__CTSR = 32'h0000000F; +parameter mask_debug_cpu_cti0__CTSR = 32'h0000000F; + +parameter debug_cpu_cti0__CTCR = 32'hF8898FA4; +parameter val_debug_cpu_cti0__CTCR = 32'h00000000; +parameter mask_debug_cpu_cti0__CTCR = 32'h0000000F; + +parameter debug_cpu_cti0__LAR = 32'hF8898FB0; +parameter val_debug_cpu_cti0__LAR = 32'h00000000; +parameter mask_debug_cpu_cti0__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_cti0__LSR = 32'hF8898FB4; +parameter val_debug_cpu_cti0__LSR = 32'h00000003; +parameter mask_debug_cpu_cti0__LSR = 32'h00000007; + +parameter debug_cpu_cti0__ASR = 32'hF8898FB8; +parameter val_debug_cpu_cti0__ASR = 32'h00000005; +parameter mask_debug_cpu_cti0__ASR = 32'h00000005; + +parameter debug_cpu_cti0__DEVID = 32'hF8898FC8; +parameter val_debug_cpu_cti0__DEVID = 32'h00040800; +parameter mask_debug_cpu_cti0__DEVID = 32'h000FFFFF; + +parameter debug_cpu_cti0__DTIR = 32'hF8898FCC; +parameter val_debug_cpu_cti0__DTIR = 32'h00000014; +parameter mask_debug_cpu_cti0__DTIR = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID4 = 32'hF8898FD0; +parameter val_debug_cpu_cti0__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_cti0__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID5 = 32'hF8898FD4; +parameter val_debug_cpu_cti0__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID6 = 32'hF8898FD8; +parameter val_debug_cpu_cti0__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID7 = 32'hF8898FDC; +parameter val_debug_cpu_cti0__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID0 = 32'hF8898FE0; +parameter val_debug_cpu_cti0__PERIPHID0 = 32'h00000006; +parameter mask_debug_cpu_cti0__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID1 = 32'hF8898FE4; +parameter val_debug_cpu_cti0__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_cti0__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID2 = 32'hF8898FE8; +parameter val_debug_cpu_cti0__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cpu_cti0__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID3 = 32'hF8898FEC; +parameter val_debug_cpu_cti0__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID0 = 32'hF8898FF0; +parameter val_debug_cpu_cti0__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_cti0__COMPID0 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID1 = 32'hF8898FF4; +parameter val_debug_cpu_cti0__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_cti0__COMPID1 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID2 = 32'hF8898FF8; +parameter val_debug_cpu_cti0__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_cti0__COMPID2 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID3 = 32'hF8898FFC; +parameter val_debug_cpu_cti0__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_cti0__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_cti1 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_cti1__CTICONTROL = 32'hF8899000; +parameter val_debug_cpu_cti1__CTICONTROL = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICONTROL = 32'h00000001; + +parameter debug_cpu_cti1__CTIINTACK = 32'hF8899010; +parameter val_debug_cpu_cti1__CTIINTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINTACK = 32'h000000FF; + +parameter debug_cpu_cti1__CTIAPPSET = 32'hF8899014; +parameter val_debug_cpu_cti1__CTIAPPSET = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPSET = 32'h0000000F; + +parameter debug_cpu_cti1__CTIAPPCLEAR = 32'hF8899018; +parameter val_debug_cpu_cti1__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cpu_cti1__CTIAPPPULSE = 32'hF889901C; +parameter val_debug_cpu_cti1__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN0 = 32'hF8899020; +parameter val_debug_cpu_cti1__CTIINEN0 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN0 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN1 = 32'hF8899024; +parameter val_debug_cpu_cti1__CTIINEN1 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN1 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN2 = 32'hF8899028; +parameter val_debug_cpu_cti1__CTIINEN2 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN2 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN3 = 32'hF889902C; +parameter val_debug_cpu_cti1__CTIINEN3 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN3 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN4 = 32'hF8899030; +parameter val_debug_cpu_cti1__CTIINEN4 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN4 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN5 = 32'hF8899034; +parameter val_debug_cpu_cti1__CTIINEN5 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN5 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN6 = 32'hF8899038; +parameter val_debug_cpu_cti1__CTIINEN6 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN6 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN7 = 32'hF889903C; +parameter val_debug_cpu_cti1__CTIINEN7 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN7 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN0 = 32'hF88990A0; +parameter val_debug_cpu_cti1__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN1 = 32'hF88990A4; +parameter val_debug_cpu_cti1__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN2 = 32'hF88990A8; +parameter val_debug_cpu_cti1__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN3 = 32'hF88990AC; +parameter val_debug_cpu_cti1__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN4 = 32'hF88990B0; +parameter val_debug_cpu_cti1__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN5 = 32'hF88990B4; +parameter val_debug_cpu_cti1__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN6 = 32'hF88990B8; +parameter val_debug_cpu_cti1__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN7 = 32'hF88990BC; +parameter val_debug_cpu_cti1__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cpu_cti1__CTITRIGINSTATUS = 32'hF8899130; +parameter val_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cpu_cti1__CTITRIGOUTSTATUS = 32'hF8899134; +parameter val_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cpu_cti1__CTICHINSTATUS = 32'hF8899138; +parameter val_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; + +parameter debug_cpu_cti1__CTICHOUTSTATUS = 32'hF889913C; +parameter val_debug_cpu_cti1__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cpu_cti1__CTIGATE = 32'hF8899140; +parameter val_debug_cpu_cti1__CTIGATE = 32'h0000000F; +parameter mask_debug_cpu_cti1__CTIGATE = 32'h0000000F; + +parameter debug_cpu_cti1__ASICCTL = 32'hF8899144; +parameter val_debug_cpu_cti1__ASICCTL = 32'h00000000; +parameter mask_debug_cpu_cti1__ASICCTL = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHINACK = 32'hF8899EDC; +parameter val_debug_cpu_cti1__ITCHINACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHINACK = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGINACK = 32'hF8899EE0; +parameter val_debug_cpu_cti1__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGINACK = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHOUT = 32'hF8899EE4; +parameter val_debug_cpu_cti1__ITCHOUT = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHOUT = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGOUT = 32'hF8899EE8; +parameter val_debug_cpu_cti1__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGOUT = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHOUTACK = 32'hF8899EEC; +parameter val_debug_cpu_cti1__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHOUTACK = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGOUTACK = 32'hF8899EF0; +parameter val_debug_cpu_cti1__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHIN = 32'hF8899EF4; +parameter val_debug_cpu_cti1__ITCHIN = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHIN = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGIN = 32'hF8899EF8; +parameter val_debug_cpu_cti1__ITTRIGIN = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGIN = 32'h000000FF; + +parameter debug_cpu_cti1__ITCTRL = 32'hF8899F00; +parameter val_debug_cpu_cti1__ITCTRL = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCTRL = 32'h00000001; + +parameter debug_cpu_cti1__CTSR = 32'hF8899FA0; +parameter val_debug_cpu_cti1__CTSR = 32'h0000000F; +parameter mask_debug_cpu_cti1__CTSR = 32'h0000000F; + +parameter debug_cpu_cti1__CTCR = 32'hF8899FA4; +parameter val_debug_cpu_cti1__CTCR = 32'h00000000; +parameter mask_debug_cpu_cti1__CTCR = 32'h0000000F; + +parameter debug_cpu_cti1__LAR = 32'hF8899FB0; +parameter val_debug_cpu_cti1__LAR = 32'h00000000; +parameter mask_debug_cpu_cti1__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_cti1__LSR = 32'hF8899FB4; +parameter val_debug_cpu_cti1__LSR = 32'h00000003; +parameter mask_debug_cpu_cti1__LSR = 32'h00000007; + +parameter debug_cpu_cti1__ASR = 32'hF8899FB8; +parameter val_debug_cpu_cti1__ASR = 32'h00000005; +parameter mask_debug_cpu_cti1__ASR = 32'h00000005; + +parameter debug_cpu_cti1__DEVID = 32'hF8899FC8; +parameter val_debug_cpu_cti1__DEVID = 32'h00040800; +parameter mask_debug_cpu_cti1__DEVID = 32'h000FFFFF; + +parameter debug_cpu_cti1__DTIR = 32'hF8899FCC; +parameter val_debug_cpu_cti1__DTIR = 32'h00000014; +parameter mask_debug_cpu_cti1__DTIR = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID4 = 32'hF8899FD0; +parameter val_debug_cpu_cti1__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_cti1__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID5 = 32'hF8899FD4; +parameter val_debug_cpu_cti1__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID6 = 32'hF8899FD8; +parameter val_debug_cpu_cti1__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID7 = 32'hF8899FDC; +parameter val_debug_cpu_cti1__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID0 = 32'hF8899FE0; +parameter val_debug_cpu_cti1__PERIPHID0 = 32'h00000006; +parameter mask_debug_cpu_cti1__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID1 = 32'hF8899FE4; +parameter val_debug_cpu_cti1__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_cti1__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID2 = 32'hF8899FE8; +parameter val_debug_cpu_cti1__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cpu_cti1__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID3 = 32'hF8899FEC; +parameter val_debug_cpu_cti1__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID0 = 32'hF8899FF0; +parameter val_debug_cpu_cti1__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_cti1__COMPID0 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID1 = 32'hF8899FF4; +parameter val_debug_cpu_cti1__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_cti1__COMPID1 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID2 = 32'hF8899FF8; +parameter val_debug_cpu_cti1__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_cti1__COMPID2 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID3 = 32'hF8899FFC; +parameter val_debug_cpu_cti1__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_cti1__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_pmu0 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_pmu0__PMXEVCNTR0 = 32'hF8891000; +parameter val_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR1 = 32'hF8891004; +parameter val_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR2 = 32'hF8891008; +parameter val_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR3 = 32'hF889100C; +parameter val_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR4 = 32'hF8891010; +parameter val_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR5 = 32'hF8891014; +parameter val_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; + +parameter debug_cpu_pmu0__PMCCNTR = 32'hF889107C; +parameter val_debug_cpu_pmu0__PMCCNTR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCCNTR = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER0 = 32'hF8891400; +parameter val_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER1 = 32'hF8891404; +parameter val_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER2 = 32'hF8891408; +parameter val_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER3 = 32'hF889140C; +parameter val_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER4 = 32'hF8891410; +parameter val_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER5 = 32'hF8891414; +parameter val_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; + +parameter debug_cpu_pmu0__PMCNTENSET = 32'hF8891C00; +parameter val_debug_cpu_pmu0__PMCNTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCNTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMCNTENCLR = 32'hF8891C20; +parameter val_debug_cpu_pmu0__PMCNTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCNTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMINTENSET = 32'hF8891C40; +parameter val_debug_cpu_pmu0__PMINTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMINTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMINTENCLR = 32'hF8891C60; +parameter val_debug_cpu_pmu0__PMINTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMINTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMOVSR = 32'hF8891C80; +parameter val_debug_cpu_pmu0__PMOVSR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMOVSR = 32'h00000000; + +parameter debug_cpu_pmu0__PMSWINC = 32'hF8891CA0; +parameter val_debug_cpu_pmu0__PMSWINC = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMSWINC = 32'h00000000; + +parameter debug_cpu_pmu0__PMCR = 32'hF8891E04; +parameter val_debug_cpu_pmu0__PMCR = 32'h41093000; +parameter mask_debug_cpu_pmu0__PMCR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMUSERENR = 32'hF8891E08; +parameter val_debug_cpu_pmu0__PMUSERENR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMUSERENR = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_pmu1 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_pmu1__PMXEVCNTR0 = 32'hF8893000; +parameter val_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR1 = 32'hF8893004; +parameter val_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR2 = 32'hF8893008; +parameter val_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR3 = 32'hF889300C; +parameter val_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR4 = 32'hF8893010; +parameter val_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR5 = 32'hF8893014; +parameter val_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; + +parameter debug_cpu_pmu1__PMCCNTR = 32'hF889307C; +parameter val_debug_cpu_pmu1__PMCCNTR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCCNTR = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER0 = 32'hF8893400; +parameter val_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER1 = 32'hF8893404; +parameter val_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER2 = 32'hF8893408; +parameter val_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER3 = 32'hF889340C; +parameter val_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER4 = 32'hF8893410; +parameter val_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER5 = 32'hF8893414; +parameter val_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; + +parameter debug_cpu_pmu1__PMCNTENSET = 32'hF8893C00; +parameter val_debug_cpu_pmu1__PMCNTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCNTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMCNTENCLR = 32'hF8893C20; +parameter val_debug_cpu_pmu1__PMCNTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCNTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMINTENSET = 32'hF8893C40; +parameter val_debug_cpu_pmu1__PMINTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMINTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMINTENCLR = 32'hF8893C60; +parameter val_debug_cpu_pmu1__PMINTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMINTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMOVSR = 32'hF8893C80; +parameter val_debug_cpu_pmu1__PMOVSR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMOVSR = 32'h00000000; + +parameter debug_cpu_pmu1__PMSWINC = 32'hF8893CA0; +parameter val_debug_cpu_pmu1__PMSWINC = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMSWINC = 32'h00000000; + +parameter debug_cpu_pmu1__PMCR = 32'hF8893E04; +parameter val_debug_cpu_pmu1__PMCR = 32'h41093000; +parameter mask_debug_cpu_pmu1__PMCR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMUSERENR = 32'hF8893E08; +parameter val_debug_cpu_pmu1__PMUSERENR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMUSERENR = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_ptm0 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_ptm0__ETMCR = 32'hF889C000; +parameter val_debug_cpu_ptm0__ETMCR = 32'h00000400; +parameter mask_debug_cpu_ptm0__ETMCR = 32'h3FFFFFFF; + +parameter debug_cpu_ptm0__ETMCCR = 32'hF889C004; +parameter val_debug_cpu_ptm0__ETMCCR = 32'h8D294004; +parameter mask_debug_cpu_ptm0__ETMCCR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMTRIGGER = 32'hF889C008; +parameter val_debug_cpu_ptm0__ETMTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTRIGGER = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSR = 32'hF889C010; +parameter val_debug_cpu_ptm0__ETMSR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSR = 32'h0000000F; + +parameter debug_cpu_ptm0__ETMSCR = 32'hF889C014; +parameter val_debug_cpu_ptm0__ETMSCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSCR = 32'h00007FFF; + +parameter debug_cpu_ptm0__ETMTSSCR = 32'hF889C018; +parameter val_debug_cpu_ptm0__ETMTSSCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTSSCR = 32'h00FFFFFF; + +parameter debug_cpu_ptm0__ETMTECR1 = 32'hF889C024; +parameter val_debug_cpu_ptm0__ETMTECR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTECR1 = 32'h03FFFFFF; + +parameter debug_cpu_ptm0__ETMACVR1 = 32'hF889C040; +parameter val_debug_cpu_ptm0__ETMACVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR2 = 32'hF889C044; +parameter val_debug_cpu_ptm0__ETMACVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR2 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR3 = 32'hF889C048; +parameter val_debug_cpu_ptm0__ETMACVR3 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR3 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR4 = 32'hF889C04C; +parameter val_debug_cpu_ptm0__ETMACVR4 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR4 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR5 = 32'hF889C050; +parameter val_debug_cpu_ptm0__ETMACVR5 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR5 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR6 = 32'hF889C054; +parameter val_debug_cpu_ptm0__ETMACVR6 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR6 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR7 = 32'hF889C058; +parameter val_debug_cpu_ptm0__ETMACVR7 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR7 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR8 = 32'hF889C05C; +parameter val_debug_cpu_ptm0__ETMACVR8 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR8 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACTR1 = 32'hF889C080; +parameter val_debug_cpu_ptm0__ETMACTR1 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR1 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR2 = 32'hF889C084; +parameter val_debug_cpu_ptm0__ETMACTR2 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR2 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR3 = 32'hF889C088; +parameter val_debug_cpu_ptm0__ETMACTR3 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR3 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR4 = 32'hF889C08C; +parameter val_debug_cpu_ptm0__ETMACTR4 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR4 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR5 = 32'hF889C090; +parameter val_debug_cpu_ptm0__ETMACTR5 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR5 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR6 = 32'hF889C094; +parameter val_debug_cpu_ptm0__ETMACTR6 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR6 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR7 = 32'hF889C098; +parameter val_debug_cpu_ptm0__ETMACTR7 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR7 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR8 = 32'hF889C09C; +parameter val_debug_cpu_ptm0__ETMACTR8 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR8 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMCNTRLDVR1 = 32'hF889C140; +parameter val_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDVR2 = 32'hF889C144; +parameter val_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTENR1 = 32'hF889C150; +parameter val_debug_cpu_ptm0__ETMCNTENR1 = 32'h00020000; +parameter mask_debug_cpu_ptm0__ETMCNTENR1 = 32'h0003FFFF; + +parameter debug_cpu_ptm0__ETMCNTENR2 = 32'hF889C154; +parameter val_debug_cpu_ptm0__ETMCNTENR2 = 32'h00020000; +parameter mask_debug_cpu_ptm0__ETMCNTENR2 = 32'h0003FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'hF889C160; +parameter val_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'hF889C164; +parameter val_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCNTVR1 = 32'hF889C170; +parameter val_debug_cpu_ptm0__ETMCNTVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTVR2 = 32'hF889C174; +parameter val_debug_cpu_ptm0__ETMCNTVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMSQ12EVR = 32'hF889C180; +parameter val_debug_cpu_ptm0__ETMSQ12EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ12EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ21EVR = 32'hF889C184; +parameter val_debug_cpu_ptm0__ETMSQ21EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ21EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ23EVR = 32'hF889C188; +parameter val_debug_cpu_ptm0__ETMSQ23EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ23EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ31EVR = 32'hF889C18C; +parameter val_debug_cpu_ptm0__ETMSQ31EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ31EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ32EVR = 32'hF889C190; +parameter val_debug_cpu_ptm0__ETMSQ32EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ32EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ13EVR = 32'hF889C194; +parameter val_debug_cpu_ptm0__ETMSQ13EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ13EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQR = 32'hF889C19C; +parameter val_debug_cpu_ptm0__ETMSQR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQR = 32'h00000003; + +parameter debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'hF889C1A0; +parameter val_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'hF889C1A4; +parameter val_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCIDCVR1 = 32'hF889C1B0; +parameter val_debug_cpu_ptm0__ETMCIDCVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCIDCVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMCIDCMR = 32'hF889C1BC; +parameter val_debug_cpu_ptm0__ETMCIDCMR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCIDCMR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMSYNCFR = 32'hF889C1E0; +parameter val_debug_cpu_ptm0__ETMSYNCFR = 32'h00000400; +parameter mask_debug_cpu_ptm0__ETMSYNCFR = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMIDR = 32'hF889C1E4; +parameter val_debug_cpu_ptm0__ETMIDR = 32'h411CF300; +parameter mask_debug_cpu_ptm0__ETMIDR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMCCER = 32'hF889C1E8; +parameter val_debug_cpu_ptm0__ETMCCER = 32'h00C019A2; +parameter mask_debug_cpu_ptm0__ETMCCER = 32'h03FFFFFF; + +parameter debug_cpu_ptm0__ETMEXTINSELR = 32'hF889C1EC; +parameter val_debug_cpu_ptm0__ETMEXTINSELR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTINSELR = 32'h00003FFF; + +parameter debug_cpu_ptm0__ETMAUXCR = 32'hF889C1FC; +parameter val_debug_cpu_ptm0__ETMAUXCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMAUXCR = 32'h0000000F; + +parameter debug_cpu_ptm0__ETMTRACEIDR = 32'hF889C200; +parameter val_debug_cpu_ptm0__ETMTRACEIDR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTRACEIDR = 32'h0000007F; + +parameter debug_cpu_ptm0__OSLSR = 32'hF889C304; +parameter val_debug_cpu_ptm0__OSLSR = 32'h00000000; +parameter mask_debug_cpu_ptm0__OSLSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMPDSR = 32'hF889C314; +parameter val_debug_cpu_ptm0__ETMPDSR = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMPDSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ITMISCOUT = 32'hF889CEDC; +parameter val_debug_cpu_ptm0__ITMISCOUT = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITMISCOUT = 32'h000003FF; + +parameter debug_cpu_ptm0__ITMISCIN = 32'hF889CEE0; +parameter val_debug_cpu_ptm0__ITMISCIN = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITMISCIN = 32'h00000020; + +parameter debug_cpu_ptm0__ITTRIGGER = 32'hF889CEE8; +parameter val_debug_cpu_ptm0__ITTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITTRIGGER = 32'h00000001; + +parameter debug_cpu_ptm0__ITATBDATA0 = 32'hF889CEEC; +parameter val_debug_cpu_ptm0__ITATBDATA0 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBDATA0 = 32'h0000001F; + +parameter debug_cpu_ptm0__ITATBCTR2 = 32'hF889CEF0; +parameter val_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; + +parameter debug_cpu_ptm0__ITATBID = 32'hF889CEF4; +parameter val_debug_cpu_ptm0__ITATBID = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBID = 32'h0000007F; + +parameter debug_cpu_ptm0__ITATBCTR0 = 32'hF889CEF8; +parameter val_debug_cpu_ptm0__ITATBCTR0 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBCTR0 = 32'h000003FF; + +parameter debug_cpu_ptm0__ETMITCTRL = 32'hF889CF00; +parameter val_debug_cpu_ptm0__ETMITCTRL = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMITCTRL = 32'h00000001; + +parameter debug_cpu_ptm0__CTSR = 32'hF889CFA0; +parameter val_debug_cpu_ptm0__CTSR = 32'h000000FF; +parameter mask_debug_cpu_ptm0__CTSR = 32'h000000FF; + +parameter debug_cpu_ptm0__CTCR = 32'hF889CFA4; +parameter val_debug_cpu_ptm0__CTCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__CTCR = 32'h000000FF; + +parameter debug_cpu_ptm0__LAR = 32'hF889CFB0; +parameter val_debug_cpu_ptm0__LAR = 32'h00000000; +parameter mask_debug_cpu_ptm0__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__LSR = 32'hF889CFB4; +parameter val_debug_cpu_ptm0__LSR = 32'h00000003; +parameter mask_debug_cpu_ptm0__LSR = 32'h00000007; + +parameter debug_cpu_ptm0__ASR = 32'hF889CFB8; +parameter val_debug_cpu_ptm0__ASR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ASR = 32'h000000F3; + +parameter debug_cpu_ptm0__DEVID = 32'hF889CFC8; +parameter val_debug_cpu_ptm0__DEVID = 32'h00000000; +parameter mask_debug_cpu_ptm0__DEVID = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__DTIR = 32'hF889CFCC; +parameter val_debug_cpu_ptm0__DTIR = 32'h00000013; +parameter mask_debug_cpu_ptm0__DTIR = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID4 = 32'hF889CFD0; +parameter val_debug_cpu_ptm0__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_ptm0__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID5 = 32'hF889CFD4; +parameter val_debug_cpu_ptm0__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID6 = 32'hF889CFD8; +parameter val_debug_cpu_ptm0__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID7 = 32'hF889CFDC; +parameter val_debug_cpu_ptm0__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID0 = 32'hF889CFE0; +parameter val_debug_cpu_ptm0__PERIPHID0 = 32'h00000050; +parameter mask_debug_cpu_ptm0__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID1 = 32'hF889CFE4; +parameter val_debug_cpu_ptm0__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_ptm0__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID2 = 32'hF889CFE8; +parameter val_debug_cpu_ptm0__PERIPHID2 = 32'h0000001B; +parameter mask_debug_cpu_ptm0__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID3 = 32'hF889CFEC; +parameter val_debug_cpu_ptm0__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID0 = 32'hF889CFF0; +parameter val_debug_cpu_ptm0__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_ptm0__COMPID0 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID1 = 32'hF889CFF4; +parameter val_debug_cpu_ptm0__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_ptm0__COMPID1 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID2 = 32'hF889CFF8; +parameter val_debug_cpu_ptm0__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_ptm0__COMPID2 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID3 = 32'hF889CFFC; +parameter val_debug_cpu_ptm0__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_ptm0__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_ptm1 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_ptm1__ETMCR = 32'hF889D000; +parameter val_debug_cpu_ptm1__ETMCR = 32'h00000400; +parameter mask_debug_cpu_ptm1__ETMCR = 32'h3FFFFFFF; + +parameter debug_cpu_ptm1__ETMCCR = 32'hF889D004; +parameter val_debug_cpu_ptm1__ETMCCR = 32'h8D294004; +parameter mask_debug_cpu_ptm1__ETMCCR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMTRIGGER = 32'hF889D008; +parameter val_debug_cpu_ptm1__ETMTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTRIGGER = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSR = 32'hF889D010; +parameter val_debug_cpu_ptm1__ETMSR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSR = 32'h0000000F; + +parameter debug_cpu_ptm1__ETMSCR = 32'hF889D014; +parameter val_debug_cpu_ptm1__ETMSCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSCR = 32'h00007FFF; + +parameter debug_cpu_ptm1__ETMTSSCR = 32'hF889D018; +parameter val_debug_cpu_ptm1__ETMTSSCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTSSCR = 32'h00FFFFFF; + +parameter debug_cpu_ptm1__ETMTECR1 = 32'hF889D024; +parameter val_debug_cpu_ptm1__ETMTECR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTECR1 = 32'h03FFFFFF; + +parameter debug_cpu_ptm1__ETMACVR1 = 32'hF889D040; +parameter val_debug_cpu_ptm1__ETMACVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR2 = 32'hF889D044; +parameter val_debug_cpu_ptm1__ETMACVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR2 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR3 = 32'hF889D048; +parameter val_debug_cpu_ptm1__ETMACVR3 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR3 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR4 = 32'hF889D04C; +parameter val_debug_cpu_ptm1__ETMACVR4 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR4 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR5 = 32'hF889D050; +parameter val_debug_cpu_ptm1__ETMACVR5 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR5 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR6 = 32'hF889D054; +parameter val_debug_cpu_ptm1__ETMACVR6 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR6 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR7 = 32'hF889D058; +parameter val_debug_cpu_ptm1__ETMACVR7 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR7 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR8 = 32'hF889D05C; +parameter val_debug_cpu_ptm1__ETMACVR8 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR8 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACTR1 = 32'hF889D080; +parameter val_debug_cpu_ptm1__ETMACTR1 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR1 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR2 = 32'hF889D084; +parameter val_debug_cpu_ptm1__ETMACTR2 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR2 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR3 = 32'hF889D088; +parameter val_debug_cpu_ptm1__ETMACTR3 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR3 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR4 = 32'hF889D08C; +parameter val_debug_cpu_ptm1__ETMACTR4 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR4 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR5 = 32'hF889D090; +parameter val_debug_cpu_ptm1__ETMACTR5 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR5 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR6 = 32'hF889D094; +parameter val_debug_cpu_ptm1__ETMACTR6 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR6 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR7 = 32'hF889D098; +parameter val_debug_cpu_ptm1__ETMACTR7 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR7 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR8 = 32'hF889D09C; +parameter val_debug_cpu_ptm1__ETMACTR8 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR8 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMCNTRLDVR1 = 32'hF889D140; +parameter val_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDVR2 = 32'hF889D144; +parameter val_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTENR1 = 32'hF889D150; +parameter val_debug_cpu_ptm1__ETMCNTENR1 = 32'h00020000; +parameter mask_debug_cpu_ptm1__ETMCNTENR1 = 32'h0003FFFF; + +parameter debug_cpu_ptm1__ETMCNTENR2 = 32'hF889D154; +parameter val_debug_cpu_ptm1__ETMCNTENR2 = 32'h00020000; +parameter mask_debug_cpu_ptm1__ETMCNTENR2 = 32'h0003FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'hF889D160; +parameter val_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'hF889D164; +parameter val_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCNTVR1 = 32'hF889D170; +parameter val_debug_cpu_ptm1__ETMCNTVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTVR2 = 32'hF889D174; +parameter val_debug_cpu_ptm1__ETMCNTVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMSQ12EVR = 32'hF889D180; +parameter val_debug_cpu_ptm1__ETMSQ12EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ12EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ21EVR = 32'hF889D184; +parameter val_debug_cpu_ptm1__ETMSQ21EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ21EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ23EVR = 32'hF889D188; +parameter val_debug_cpu_ptm1__ETMSQ23EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ23EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ31EVR = 32'hF889D18C; +parameter val_debug_cpu_ptm1__ETMSQ31EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ31EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ32EVR = 32'hF889D190; +parameter val_debug_cpu_ptm1__ETMSQ32EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ32EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ13EVR = 32'hF889D194; +parameter val_debug_cpu_ptm1__ETMSQ13EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ13EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQR = 32'hF889D19C; +parameter val_debug_cpu_ptm1__ETMSQR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQR = 32'h00000003; + +parameter debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'hF889D1A0; +parameter val_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'hF889D1A4; +parameter val_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCIDCVR1 = 32'hF889D1B0; +parameter val_debug_cpu_ptm1__ETMCIDCVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCIDCVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMCIDCMR = 32'hF889D1BC; +parameter val_debug_cpu_ptm1__ETMCIDCMR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCIDCMR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMSYNCFR = 32'hF889D1E0; +parameter val_debug_cpu_ptm1__ETMSYNCFR = 32'h00000400; +parameter mask_debug_cpu_ptm1__ETMSYNCFR = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMIDR = 32'hF889D1E4; +parameter val_debug_cpu_ptm1__ETMIDR = 32'h411CF300; +parameter mask_debug_cpu_ptm1__ETMIDR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMCCER = 32'hF889D1E8; +parameter val_debug_cpu_ptm1__ETMCCER = 32'h00C019A2; +parameter mask_debug_cpu_ptm1__ETMCCER = 32'h03FFFFFF; + +parameter debug_cpu_ptm1__ETMEXTINSELR = 32'hF889D1EC; +parameter val_debug_cpu_ptm1__ETMEXTINSELR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTINSELR = 32'h00003FFF; + +parameter debug_cpu_ptm1__ETMAUXCR = 32'hF889D1FC; +parameter val_debug_cpu_ptm1__ETMAUXCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMAUXCR = 32'h0000000F; + +parameter debug_cpu_ptm1__ETMTRACEIDR = 32'hF889D200; +parameter val_debug_cpu_ptm1__ETMTRACEIDR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTRACEIDR = 32'h0000007F; + +parameter debug_cpu_ptm1__OSLSR = 32'hF889D304; +parameter val_debug_cpu_ptm1__OSLSR = 32'h00000000; +parameter mask_debug_cpu_ptm1__OSLSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMPDSR = 32'hF889D314; +parameter val_debug_cpu_ptm1__ETMPDSR = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMPDSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ITMISCOUT = 32'hF889DEDC; +parameter val_debug_cpu_ptm1__ITMISCOUT = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITMISCOUT = 32'h000003FF; + +parameter debug_cpu_ptm1__ITMISCIN = 32'hF889DEE0; +parameter val_debug_cpu_ptm1__ITMISCIN = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITMISCIN = 32'h00000020; + +parameter debug_cpu_ptm1__ITTRIGGER = 32'hF889DEE8; +parameter val_debug_cpu_ptm1__ITTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITTRIGGER = 32'h00000001; + +parameter debug_cpu_ptm1__ITATBDATA0 = 32'hF889DEEC; +parameter val_debug_cpu_ptm1__ITATBDATA0 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBDATA0 = 32'h0000001F; + +parameter debug_cpu_ptm1__ITATBCTR2 = 32'hF889DEF0; +parameter val_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; + +parameter debug_cpu_ptm1__ITATBID = 32'hF889DEF4; +parameter val_debug_cpu_ptm1__ITATBID = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBID = 32'h0000007F; + +parameter debug_cpu_ptm1__ITATBCTR0 = 32'hF889DEF8; +parameter val_debug_cpu_ptm1__ITATBCTR0 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBCTR0 = 32'h000003FF; + +parameter debug_cpu_ptm1__ETMITCTRL = 32'hF889DF00; +parameter val_debug_cpu_ptm1__ETMITCTRL = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMITCTRL = 32'h00000001; + +parameter debug_cpu_ptm1__CTSR = 32'hF889DFA0; +parameter val_debug_cpu_ptm1__CTSR = 32'h000000FF; +parameter mask_debug_cpu_ptm1__CTSR = 32'h000000FF; + +parameter debug_cpu_ptm1__CTCR = 32'hF889DFA4; +parameter val_debug_cpu_ptm1__CTCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__CTCR = 32'h000000FF; + +parameter debug_cpu_ptm1__LAR = 32'hF889DFB0; +parameter val_debug_cpu_ptm1__LAR = 32'h00000000; +parameter mask_debug_cpu_ptm1__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__LSR = 32'hF889DFB4; +parameter val_debug_cpu_ptm1__LSR = 32'h00000003; +parameter mask_debug_cpu_ptm1__LSR = 32'h00000007; + +parameter debug_cpu_ptm1__ASR = 32'hF889DFB8; +parameter val_debug_cpu_ptm1__ASR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ASR = 32'h000000F3; + +parameter debug_cpu_ptm1__DEVID = 32'hF889DFC8; +parameter val_debug_cpu_ptm1__DEVID = 32'h00000000; +parameter mask_debug_cpu_ptm1__DEVID = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__DTIR = 32'hF889DFCC; +parameter val_debug_cpu_ptm1__DTIR = 32'h00000013; +parameter mask_debug_cpu_ptm1__DTIR = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID4 = 32'hF889DFD0; +parameter val_debug_cpu_ptm1__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_ptm1__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID5 = 32'hF889DFD4; +parameter val_debug_cpu_ptm1__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID6 = 32'hF889DFD8; +parameter val_debug_cpu_ptm1__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID7 = 32'hF889DFDC; +parameter val_debug_cpu_ptm1__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID0 = 32'hF889DFE0; +parameter val_debug_cpu_ptm1__PERIPHID0 = 32'h00000050; +parameter mask_debug_cpu_ptm1__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID1 = 32'hF889DFE4; +parameter val_debug_cpu_ptm1__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_ptm1__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID2 = 32'hF889DFE8; +parameter val_debug_cpu_ptm1__PERIPHID2 = 32'h0000001B; +parameter mask_debug_cpu_ptm1__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID3 = 32'hF889DFEC; +parameter val_debug_cpu_ptm1__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID0 = 32'hF889DFF0; +parameter val_debug_cpu_ptm1__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_ptm1__COMPID0 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID1 = 32'hF889DFF4; +parameter val_debug_cpu_ptm1__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_ptm1__COMPID1 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID2 = 32'hF889DFF8; +parameter val_debug_cpu_ptm1__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_ptm1__COMPID2 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID3 = 32'hF889DFFC; +parameter val_debug_cpu_ptm1__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_ptm1__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_axim cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_axim__CTICONTROL = 32'hF880A000; +parameter val_debug_cti_axim__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_axim__CTICONTROL = 32'h00000001; + +parameter debug_cti_axim__CTIINTACK = 32'hF880A010; +parameter val_debug_cti_axim__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_axim__CTIINTACK = 32'h000000FF; + +parameter debug_cti_axim__CTIAPPSET = 32'hF880A014; +parameter val_debug_cti_axim__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_axim__CTIAPPCLEAR = 32'hF880A018; +parameter val_debug_cti_axim__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_axim__CTIAPPPULSE = 32'hF880A01C; +parameter val_debug_cti_axim__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN0 = 32'hF880A020; +parameter val_debug_cti_axim__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN1 = 32'hF880A024; +parameter val_debug_cti_axim__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN2 = 32'hF880A028; +parameter val_debug_cti_axim__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN3 = 32'hF880A02C; +parameter val_debug_cti_axim__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN4 = 32'hF880A030; +parameter val_debug_cti_axim__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN5 = 32'hF880A034; +parameter val_debug_cti_axim__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN6 = 32'hF880A038; +parameter val_debug_cti_axim__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN7 = 32'hF880A03C; +parameter val_debug_cti_axim__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN0 = 32'hF880A0A0; +parameter val_debug_cti_axim__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN1 = 32'hF880A0A4; +parameter val_debug_cti_axim__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN2 = 32'hF880A0A8; +parameter val_debug_cti_axim__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN3 = 32'hF880A0AC; +parameter val_debug_cti_axim__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN4 = 32'hF880A0B0; +parameter val_debug_cti_axim__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN5 = 32'hF880A0B4; +parameter val_debug_cti_axim__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN6 = 32'hF880A0B8; +parameter val_debug_cti_axim__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN7 = 32'hF880A0BC; +parameter val_debug_cti_axim__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_axim__CTITRIGINSTATUS = 32'hF880A130; +parameter val_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_axim__CTITRIGOUTSTATUS = 32'hF880A134; +parameter val_debug_cti_axim__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_axim__CTICHINSTATUS = 32'hF880A138; +parameter val_debug_cti_axim__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_axim__CTICHOUTSTATUS = 32'hF880A13C; +parameter val_debug_cti_axim__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_axim__CTIGATE = 32'hF880A140; +parameter val_debug_cti_axim__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_axim__CTIGATE = 32'h0000000F; + +parameter debug_cti_axim__ASICCTL = 32'hF880A144; +parameter val_debug_cti_axim__ASICCTL = 32'h00000000; +parameter mask_debug_cti_axim__ASICCTL = 32'h000000FF; + +parameter debug_cti_axim__ITCHINACK = 32'hF880AEDC; +parameter val_debug_cti_axim__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_axim__ITCHINACK = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGINACK = 32'hF880AEE0; +parameter val_debug_cti_axim__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_axim__ITCHOUT = 32'hF880AEE4; +parameter val_debug_cti_axim__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_axim__ITCHOUT = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGOUT = 32'hF880AEE8; +parameter val_debug_cti_axim__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_axim__ITCHOUTACK = 32'hF880AEEC; +parameter val_debug_cti_axim__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_axim__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGOUTACK = 32'hF880AEF0; +parameter val_debug_cti_axim__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_axim__ITCHIN = 32'hF880AEF4; +parameter val_debug_cti_axim__ITCHIN = 32'h00000000; +parameter mask_debug_cti_axim__ITCHIN = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGIN = 32'hF880AEF8; +parameter val_debug_cti_axim__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_axim__ITCTRL = 32'hF880AF00; +parameter val_debug_cti_axim__ITCTRL = 32'h00000000; +parameter mask_debug_cti_axim__ITCTRL = 32'h00000001; + +parameter debug_cti_axim__CTSR = 32'hF880AFA0; +parameter val_debug_cti_axim__CTSR = 32'h0000000F; +parameter mask_debug_cti_axim__CTSR = 32'h0000000F; + +parameter debug_cti_axim__CTCR = 32'hF880AFA4; +parameter val_debug_cti_axim__CTCR = 32'h00000000; +parameter mask_debug_cti_axim__CTCR = 32'h0000000F; + +parameter debug_cti_axim__LAR = 32'hF880AFB0; +parameter val_debug_cti_axim__LAR = 32'h00000000; +parameter mask_debug_cti_axim__LAR = 32'hFFFFFFFF; + +parameter debug_cti_axim__LSR = 32'hF880AFB4; +parameter val_debug_cti_axim__LSR = 32'h00000003; +parameter mask_debug_cti_axim__LSR = 32'h00000007; + +parameter debug_cti_axim__ASR = 32'hF880AFB8; +parameter val_debug_cti_axim__ASR = 32'h00000005; +parameter mask_debug_cti_axim__ASR = 32'h00000005; + +parameter debug_cti_axim__DEVID = 32'hF880AFC8; +parameter val_debug_cti_axim__DEVID = 32'h00040800; +parameter mask_debug_cti_axim__DEVID = 32'h000FFFFF; + +parameter debug_cti_axim__DTIR = 32'hF880AFCC; +parameter val_debug_cti_axim__DTIR = 32'h00000014; +parameter mask_debug_cti_axim__DTIR = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID4 = 32'hF880AFD0; +parameter val_debug_cti_axim__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_axim__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID5 = 32'hF880AFD4; +parameter val_debug_cti_axim__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID6 = 32'hF880AFD8; +parameter val_debug_cti_axim__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID7 = 32'hF880AFDC; +parameter val_debug_cti_axim__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID0 = 32'hF880AFE0; +parameter val_debug_cti_axim__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_axim__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID1 = 32'hF880AFE4; +parameter val_debug_cti_axim__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_axim__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID2 = 32'hF880AFE8; +parameter val_debug_cti_axim__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_axim__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID3 = 32'hF880AFEC; +parameter val_debug_cti_axim__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_axim__COMPID0 = 32'hF880AFF0; +parameter val_debug_cti_axim__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_axim__COMPID0 = 32'h000000FF; + +parameter debug_cti_axim__COMPID1 = 32'hF880AFF4; +parameter val_debug_cti_axim__COMPID1 = 32'h00000090; +parameter mask_debug_cti_axim__COMPID1 = 32'h000000FF; + +parameter debug_cti_axim__COMPID2 = 32'hF880AFF8; +parameter val_debug_cti_axim__COMPID2 = 32'h00000005; +parameter mask_debug_cti_axim__COMPID2 = 32'h000000FF; + +parameter debug_cti_axim__COMPID3 = 32'hF880AFFC; +parameter val_debug_cti_axim__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_axim__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_etb_tpiu cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_etb_tpiu__CTICONTROL = 32'hF8802000; +parameter val_debug_cti_etb_tpiu__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICONTROL = 32'h00000001; + +parameter debug_cti_etb_tpiu__CTIINTACK = 32'hF8802010; +parameter val_debug_cti_etb_tpiu__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINTACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__CTIAPPSET = 32'hF8802014; +parameter val_debug_cti_etb_tpiu__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIAPPCLEAR = 32'hF8802018; +parameter val_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIAPPPULSE = 32'hF880201C; +parameter val_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN0 = 32'hF8802020; +parameter val_debug_cti_etb_tpiu__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN1 = 32'hF8802024; +parameter val_debug_cti_etb_tpiu__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN2 = 32'hF8802028; +parameter val_debug_cti_etb_tpiu__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN3 = 32'hF880202C; +parameter val_debug_cti_etb_tpiu__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN4 = 32'hF8802030; +parameter val_debug_cti_etb_tpiu__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN5 = 32'hF8802034; +parameter val_debug_cti_etb_tpiu__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN6 = 32'hF8802038; +parameter val_debug_cti_etb_tpiu__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN7 = 32'hF880203C; +parameter val_debug_cti_etb_tpiu__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN0 = 32'hF88020A0; +parameter val_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN1 = 32'hF88020A4; +parameter val_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN2 = 32'hF88020A8; +parameter val_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN3 = 32'hF88020AC; +parameter val_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN4 = 32'hF88020B0; +parameter val_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN5 = 32'hF88020B4; +parameter val_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN6 = 32'hF88020B8; +parameter val_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN7 = 32'hF88020BC; +parameter val_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'hF8802130; +parameter val_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'hF8802134; +parameter val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_etb_tpiu__CTICHINSTATUS = 32'hF8802138; +parameter val_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'hF880213C; +parameter val_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIGATE = 32'hF8802140; +parameter val_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ASICCTL = 32'hF8802144; +parameter val_debug_cti_etb_tpiu__ASICCTL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ASICCTL = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHINACK = 32'hF8802EDC; +parameter val_debug_cti_etb_tpiu__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHINACK = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGINACK = 32'hF8802EE0; +parameter val_debug_cti_etb_tpiu__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHOUT = 32'hF8802EE4; +parameter val_debug_cti_etb_tpiu__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHOUT = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGOUT = 32'hF8802EE8; +parameter val_debug_cti_etb_tpiu__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHOUTACK = 32'hF8802EEC; +parameter val_debug_cti_etb_tpiu__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGOUTACK = 32'hF8802EF0; +parameter val_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHIN = 32'hF8802EF4; +parameter val_debug_cti_etb_tpiu__ITCHIN = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHIN = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGIN = 32'hF8802EF8; +parameter val_debug_cti_etb_tpiu__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCTRL = 32'hF8802F00; +parameter val_debug_cti_etb_tpiu__ITCTRL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCTRL = 32'h00000001; + +parameter debug_cti_etb_tpiu__CTSR = 32'hF8802FA0; +parameter val_debug_cti_etb_tpiu__CTSR = 32'h0000000F; +parameter mask_debug_cti_etb_tpiu__CTSR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTCR = 32'hF8802FA4; +parameter val_debug_cti_etb_tpiu__CTCR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTCR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__LAR = 32'hF8802FB0; +parameter val_debug_cti_etb_tpiu__LAR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__LAR = 32'hFFFFFFFF; + +parameter debug_cti_etb_tpiu__LSR = 32'hF8802FB4; +parameter val_debug_cti_etb_tpiu__LSR = 32'h00000003; +parameter mask_debug_cti_etb_tpiu__LSR = 32'h00000007; + +parameter debug_cti_etb_tpiu__ASR = 32'hF8802FB8; +parameter val_debug_cti_etb_tpiu__ASR = 32'h00000005; +parameter mask_debug_cti_etb_tpiu__ASR = 32'h00000005; + +parameter debug_cti_etb_tpiu__DEVID = 32'hF8802FC8; +parameter val_debug_cti_etb_tpiu__DEVID = 32'h00040800; +parameter mask_debug_cti_etb_tpiu__DEVID = 32'h000FFFFF; + +parameter debug_cti_etb_tpiu__DTIR = 32'hF8802FCC; +parameter val_debug_cti_etb_tpiu__DTIR = 32'h00000014; +parameter mask_debug_cti_etb_tpiu__DTIR = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID4 = 32'hF8802FD0; +parameter val_debug_cti_etb_tpiu__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_etb_tpiu__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID5 = 32'hF8802FD4; +parameter val_debug_cti_etb_tpiu__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID6 = 32'hF8802FD8; +parameter val_debug_cti_etb_tpiu__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID7 = 32'hF8802FDC; +parameter val_debug_cti_etb_tpiu__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID0 = 32'hF8802FE0; +parameter val_debug_cti_etb_tpiu__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_etb_tpiu__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID1 = 32'hF8802FE4; +parameter val_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID2 = 32'hF8802FE8; +parameter val_debug_cti_etb_tpiu__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_etb_tpiu__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID3 = 32'hF8802FEC; +parameter val_debug_cti_etb_tpiu__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID0 = 32'hF8802FF0; +parameter val_debug_cti_etb_tpiu__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_etb_tpiu__COMPID0 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID1 = 32'hF8802FF4; +parameter val_debug_cti_etb_tpiu__COMPID1 = 32'h00000090; +parameter mask_debug_cti_etb_tpiu__COMPID1 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID2 = 32'hF8802FF8; +parameter val_debug_cti_etb_tpiu__COMPID2 = 32'h00000005; +parameter mask_debug_cti_etb_tpiu__COMPID2 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID3 = 32'hF8802FFC; +parameter val_debug_cti_etb_tpiu__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_etb_tpiu__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_ftm cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_ftm__CTICONTROL = 32'hF8809000; +parameter val_debug_cti_ftm__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_ftm__CTICONTROL = 32'h00000001; + +parameter debug_cti_ftm__CTIINTACK = 32'hF8809010; +parameter val_debug_cti_ftm__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINTACK = 32'h000000FF; + +parameter debug_cti_ftm__CTIAPPSET = 32'hF8809014; +parameter val_debug_cti_ftm__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_ftm__CTIAPPCLEAR = 32'hF8809018; +parameter val_debug_cti_ftm__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_ftm__CTIAPPPULSE = 32'hF880901C; +parameter val_debug_cti_ftm__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN0 = 32'hF8809020; +parameter val_debug_cti_ftm__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN1 = 32'hF8809024; +parameter val_debug_cti_ftm__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN2 = 32'hF8809028; +parameter val_debug_cti_ftm__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN3 = 32'hF880902C; +parameter val_debug_cti_ftm__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN4 = 32'hF8809030; +parameter val_debug_cti_ftm__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN5 = 32'hF8809034; +parameter val_debug_cti_ftm__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN6 = 32'hF8809038; +parameter val_debug_cti_ftm__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN7 = 32'hF880903C; +parameter val_debug_cti_ftm__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN0 = 32'hF88090A0; +parameter val_debug_cti_ftm__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN1 = 32'hF88090A4; +parameter val_debug_cti_ftm__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN2 = 32'hF88090A8; +parameter val_debug_cti_ftm__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN3 = 32'hF88090AC; +parameter val_debug_cti_ftm__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN4 = 32'hF88090B0; +parameter val_debug_cti_ftm__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN5 = 32'hF88090B4; +parameter val_debug_cti_ftm__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN6 = 32'hF88090B8; +parameter val_debug_cti_ftm__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN7 = 32'hF88090BC; +parameter val_debug_cti_ftm__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_ftm__CTITRIGINSTATUS = 32'hF8809130; +parameter val_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_ftm__CTITRIGOUTSTATUS = 32'hF8809134; +parameter val_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_ftm__CTICHINSTATUS = 32'hF8809138; +parameter val_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_ftm__CTICHOUTSTATUS = 32'hF880913C; +parameter val_debug_cti_ftm__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_ftm__CTIGATE = 32'hF8809140; +parameter val_debug_cti_ftm__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_ftm__CTIGATE = 32'h0000000F; + +parameter debug_cti_ftm__ASICCTL = 32'hF8809144; +parameter val_debug_cti_ftm__ASICCTL = 32'h00000000; +parameter mask_debug_cti_ftm__ASICCTL = 32'h000000FF; + +parameter debug_cti_ftm__ITCHINACK = 32'hF8809EDC; +parameter val_debug_cti_ftm__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHINACK = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGINACK = 32'hF8809EE0; +parameter val_debug_cti_ftm__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_ftm__ITCHOUT = 32'hF8809EE4; +parameter val_debug_cti_ftm__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHOUT = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGOUT = 32'hF8809EE8; +parameter val_debug_cti_ftm__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_ftm__ITCHOUTACK = 32'hF8809EEC; +parameter val_debug_cti_ftm__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGOUTACK = 32'hF8809EF0; +parameter val_debug_cti_ftm__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_ftm__ITCHIN = 32'hF8809EF4; +parameter val_debug_cti_ftm__ITCHIN = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHIN = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGIN = 32'hF8809EF8; +parameter val_debug_cti_ftm__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_ftm__ITCTRL = 32'hF8809F00; +parameter val_debug_cti_ftm__ITCTRL = 32'h00000000; +parameter mask_debug_cti_ftm__ITCTRL = 32'h00000001; + +parameter debug_cti_ftm__CTSR = 32'hF8809FA0; +parameter val_debug_cti_ftm__CTSR = 32'h0000000F; +parameter mask_debug_cti_ftm__CTSR = 32'h0000000F; + +parameter debug_cti_ftm__CTCR = 32'hF8809FA4; +parameter val_debug_cti_ftm__CTCR = 32'h00000000; +parameter mask_debug_cti_ftm__CTCR = 32'h0000000F; + +parameter debug_cti_ftm__LAR = 32'hF8809FB0; +parameter val_debug_cti_ftm__LAR = 32'h00000000; +parameter mask_debug_cti_ftm__LAR = 32'hFFFFFFFF; + +parameter debug_cti_ftm__LSR = 32'hF8809FB4; +parameter val_debug_cti_ftm__LSR = 32'h00000003; +parameter mask_debug_cti_ftm__LSR = 32'h00000007; + +parameter debug_cti_ftm__ASR = 32'hF8809FB8; +parameter val_debug_cti_ftm__ASR = 32'h00000005; +parameter mask_debug_cti_ftm__ASR = 32'h00000005; + +parameter debug_cti_ftm__DEVID = 32'hF8809FC8; +parameter val_debug_cti_ftm__DEVID = 32'h00040800; +parameter mask_debug_cti_ftm__DEVID = 32'h000FFFFF; + +parameter debug_cti_ftm__DTIR = 32'hF8809FCC; +parameter val_debug_cti_ftm__DTIR = 32'h00000014; +parameter mask_debug_cti_ftm__DTIR = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID4 = 32'hF8809FD0; +parameter val_debug_cti_ftm__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_ftm__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID5 = 32'hF8809FD4; +parameter val_debug_cti_ftm__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID6 = 32'hF8809FD8; +parameter val_debug_cti_ftm__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID7 = 32'hF8809FDC; +parameter val_debug_cti_ftm__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID0 = 32'hF8809FE0; +parameter val_debug_cti_ftm__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_ftm__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID1 = 32'hF8809FE4; +parameter val_debug_cti_ftm__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_ftm__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID2 = 32'hF8809FE8; +parameter val_debug_cti_ftm__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_ftm__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID3 = 32'hF8809FEC; +parameter val_debug_cti_ftm__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID0 = 32'hF8809FF0; +parameter val_debug_cti_ftm__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_ftm__COMPID0 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID1 = 32'hF8809FF4; +parameter val_debug_cti_ftm__COMPID1 = 32'h00000090; +parameter mask_debug_cti_ftm__COMPID1 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID2 = 32'hF8809FF8; +parameter val_debug_cti_ftm__COMPID2 = 32'h00000005; +parameter mask_debug_cti_ftm__COMPID2 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID3 = 32'hF8809FFC; +parameter val_debug_cti_ftm__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_ftm__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_dap_rom dap +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_dap_rom__ROMENTRY00 = 32'hF8800000; +parameter val_debug_dap_rom__ROMENTRY00 = 32'h00001003; +parameter mask_debug_dap_rom__ROMENTRY00 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY01 = 32'hF8800004; +parameter val_debug_dap_rom__ROMENTRY01 = 32'h00002003; +parameter mask_debug_dap_rom__ROMENTRY01 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY02 = 32'hF8800008; +parameter val_debug_dap_rom__ROMENTRY02 = 32'h00003003; +parameter mask_debug_dap_rom__ROMENTRY02 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY03 = 32'hF880000C; +parameter val_debug_dap_rom__ROMENTRY03 = 32'h00004003; +parameter mask_debug_dap_rom__ROMENTRY03 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY04 = 32'hF8800010; +parameter val_debug_dap_rom__ROMENTRY04 = 32'h00005003; +parameter mask_debug_dap_rom__ROMENTRY04 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY05 = 32'hF8800014; +parameter val_debug_dap_rom__ROMENTRY05 = 32'h00009003; +parameter mask_debug_dap_rom__ROMENTRY05 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY06 = 32'hF8800018; +parameter val_debug_dap_rom__ROMENTRY06 = 32'h0000A003; +parameter mask_debug_dap_rom__ROMENTRY06 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY07 = 32'hF880001C; +parameter val_debug_dap_rom__ROMENTRY07 = 32'h0000B003; +parameter mask_debug_dap_rom__ROMENTRY07 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY08 = 32'hF8800020; +parameter val_debug_dap_rom__ROMENTRY08 = 32'h0000C003; +parameter mask_debug_dap_rom__ROMENTRY08 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY09 = 32'hF8800024; +parameter val_debug_dap_rom__ROMENTRY09 = 32'h00080003; +parameter mask_debug_dap_rom__ROMENTRY09 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY10 = 32'hF8800028; +parameter val_debug_dap_rom__ROMENTRY10 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY10 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY11 = 32'hF880002C; +parameter val_debug_dap_rom__ROMENTRY11 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY11 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY12 = 32'hF8800030; +parameter val_debug_dap_rom__ROMENTRY12 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY12 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY13 = 32'hF8800034; +parameter val_debug_dap_rom__ROMENTRY13 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY13 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY14 = 32'hF8800038; +parameter val_debug_dap_rom__ROMENTRY14 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY14 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY15 = 32'hF880003C; +parameter val_debug_dap_rom__ROMENTRY15 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY15 = 32'hFFFFFFFF; + +parameter debug_dap_rom__PERIPHID4 = 32'hF8800FD0; +parameter val_debug_dap_rom__PERIPHID4 = 32'h00000003; +parameter mask_debug_dap_rom__PERIPHID4 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID5 = 32'hF8800FD4; +parameter val_debug_dap_rom__PERIPHID5 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID5 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID6 = 32'hF8800FD8; +parameter val_debug_dap_rom__PERIPHID6 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID6 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID7 = 32'hF8800FDC; +parameter val_debug_dap_rom__PERIPHID7 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID7 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID0 = 32'hF8800FE0; +parameter val_debug_dap_rom__PERIPHID0 = 32'h000000B2; +parameter mask_debug_dap_rom__PERIPHID0 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID1 = 32'hF8800FE4; +parameter val_debug_dap_rom__PERIPHID1 = 32'h00000093; +parameter mask_debug_dap_rom__PERIPHID1 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID2 = 32'hF8800FE8; +parameter val_debug_dap_rom__PERIPHID2 = 32'h00000008; +parameter mask_debug_dap_rom__PERIPHID2 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID3 = 32'hF8800FEC; +parameter val_debug_dap_rom__PERIPHID3 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID3 = 32'h000000FF; + +parameter debug_dap_rom__COMPID0 = 32'hF8800FF0; +parameter val_debug_dap_rom__COMPID0 = 32'h0000000D; +parameter mask_debug_dap_rom__COMPID0 = 32'h000000FF; + +parameter debug_dap_rom__COMPID1 = 32'hF8800FF4; +parameter val_debug_dap_rom__COMPID1 = 32'h00000010; +parameter mask_debug_dap_rom__COMPID1 = 32'h000000FF; + +parameter debug_dap_rom__COMPID2 = 32'hF8800FF8; +parameter val_debug_dap_rom__COMPID2 = 32'h00000005; +parameter mask_debug_dap_rom__COMPID2 = 32'h000000FF; + +parameter debug_dap_rom__COMPID3 = 32'hF8800FFC; +parameter val_debug_dap_rom__COMPID3 = 32'h000000B1; +parameter mask_debug_dap_rom__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_etb etb +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_etb__RDP = 32'hF8801004; +parameter val_debug_etb__RDP = 32'h00000400; +parameter mask_debug_etb__RDP = 32'hFFFFFFFF; + +parameter debug_etb__STS = 32'hF880100C; +parameter val_debug_etb__STS = 32'h00000000; +parameter mask_debug_etb__STS = 32'h0000000F; + +parameter debug_etb__RRD = 32'hF8801010; +parameter val_debug_etb__RRD = 32'h00000000; +parameter mask_debug_etb__RRD = 32'hFFFFFFFF; + +parameter debug_etb__RRP = 32'hF8801014; +parameter val_debug_etb__RRP = 32'h00000000; +parameter mask_debug_etb__RRP = 32'h000003FF; + +parameter debug_etb__RWP = 32'hF8801018; +parameter val_debug_etb__RWP = 32'h00000000; +parameter mask_debug_etb__RWP = 32'h000003FF; + +parameter debug_etb__TRG = 32'hF880101C; +parameter val_debug_etb__TRG = 32'h00000000; +parameter mask_debug_etb__TRG = 32'h000003FF; + +parameter debug_etb__CTL = 32'hF8801020; +parameter val_debug_etb__CTL = 32'h00000000; +parameter mask_debug_etb__CTL = 32'h00000001; + +parameter debug_etb__RWD = 32'hF8801024; +parameter val_debug_etb__RWD = 32'h00000000; +parameter mask_debug_etb__RWD = 32'hFFFFFFFF; + +parameter debug_etb__FFSR = 32'hF8801300; +parameter val_debug_etb__FFSR = 32'h00000000; +parameter mask_debug_etb__FFSR = 32'h00000003; + +parameter debug_etb__FFCR = 32'hF8801304; +parameter val_debug_etb__FFCR = 32'h00000200; +parameter mask_debug_etb__FFCR = 32'h00003FFF; + +parameter debug_etb__ITMISCOP0 = 32'hF8801EE0; +parameter val_debug_etb__ITMISCOP0 = 32'h00000000; +parameter mask_debug_etb__ITMISCOP0 = 32'h00000003; + +parameter debug_etb__ITTRFLINACK = 32'hF8801EE4; +parameter val_debug_etb__ITTRFLINACK = 32'h00000000; +parameter mask_debug_etb__ITTRFLINACK = 32'h00000003; + +parameter debug_etb__ITTRFLIN = 32'hF8801EE8; +parameter val_debug_etb__ITTRFLIN = 32'h00000000; +parameter mask_debug_etb__ITTRFLIN = 32'h00000003; + +parameter debug_etb__ITATBDATA0 = 32'hF8801EEC; +parameter val_debug_etb__ITATBDATA0 = 32'h00000000; +parameter mask_debug_etb__ITATBDATA0 = 32'h0000001F; + +parameter debug_etb__ITATBCTR2 = 32'hF8801EF0; +parameter val_debug_etb__ITATBCTR2 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR2 = 32'h00000003; + +parameter debug_etb__ITATBCTR1 = 32'hF8801EF4; +parameter val_debug_etb__ITATBCTR1 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR1 = 32'h0000007F; + +parameter debug_etb__ITATBCTR0 = 32'hF8801EF8; +parameter val_debug_etb__ITATBCTR0 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR0 = 32'h000003FF; + +parameter debug_etb__IMCR = 32'hF8801F00; +parameter val_debug_etb__IMCR = 32'h00000000; +parameter mask_debug_etb__IMCR = 32'h00000001; + +parameter debug_etb__CTSR = 32'hF8801FA0; +parameter val_debug_etb__CTSR = 32'h0000000F; +parameter mask_debug_etb__CTSR = 32'h0000000F; + +parameter debug_etb__CTCR = 32'hF8801FA4; +parameter val_debug_etb__CTCR = 32'h00000000; +parameter mask_debug_etb__CTCR = 32'h0000000F; + +parameter debug_etb__LAR = 32'hF8801FB0; +parameter val_debug_etb__LAR = 32'h00000000; +parameter mask_debug_etb__LAR = 32'hFFFFFFFF; + +parameter debug_etb__LSR = 32'hF8801FB4; +parameter val_debug_etb__LSR = 32'h00000003; +parameter mask_debug_etb__LSR = 32'h00000007; + +parameter debug_etb__ASR = 32'hF8801FB8; +parameter val_debug_etb__ASR = 32'h00000000; +parameter mask_debug_etb__ASR = 32'h000000FF; + +parameter debug_etb__DEVID = 32'hF8801FC8; +parameter val_debug_etb__DEVID = 32'h00000000; +parameter mask_debug_etb__DEVID = 32'h0000003F; + +parameter debug_etb__DTIR = 32'hF8801FCC; +parameter val_debug_etb__DTIR = 32'h00000021; +parameter mask_debug_etb__DTIR = 32'h000000FF; + +parameter debug_etb__PERIPHID4 = 32'hF8801FD0; +parameter val_debug_etb__PERIPHID4 = 32'h00000004; +parameter mask_debug_etb__PERIPHID4 = 32'h000000FF; + +parameter debug_etb__PERIPHID5 = 32'hF8801FD4; +parameter val_debug_etb__PERIPHID5 = 32'h00000000; +parameter mask_debug_etb__PERIPHID5 = 32'h000000FF; + +parameter debug_etb__PERIPHID6 = 32'hF8801FD8; +parameter val_debug_etb__PERIPHID6 = 32'h00000000; +parameter mask_debug_etb__PERIPHID6 = 32'h000000FF; + +parameter debug_etb__PERIPHID7 = 32'hF8801FDC; +parameter val_debug_etb__PERIPHID7 = 32'h00000000; +parameter mask_debug_etb__PERIPHID7 = 32'h000000FF; + +parameter debug_etb__PERIPHID0 = 32'hF8801FE0; +parameter val_debug_etb__PERIPHID0 = 32'h00000007; +parameter mask_debug_etb__PERIPHID0 = 32'h000000FF; + +parameter debug_etb__PERIPHID1 = 32'hF8801FE4; +parameter val_debug_etb__PERIPHID1 = 32'h000000B9; +parameter mask_debug_etb__PERIPHID1 = 32'h000000FF; + +parameter debug_etb__PERIPHID2 = 32'hF8801FE8; +parameter val_debug_etb__PERIPHID2 = 32'h0000002B; +parameter mask_debug_etb__PERIPHID2 = 32'h000000FF; + +parameter debug_etb__PERIPHID3 = 32'hF8801FEC; +parameter val_debug_etb__PERIPHID3 = 32'h00000000; +parameter mask_debug_etb__PERIPHID3 = 32'h000000FF; + +parameter debug_etb__COMPID0 = 32'hF8801FF0; +parameter val_debug_etb__COMPID0 = 32'h0000000D; +parameter mask_debug_etb__COMPID0 = 32'h000000FF; + +parameter debug_etb__COMPID1 = 32'hF8801FF4; +parameter val_debug_etb__COMPID1 = 32'h00000090; +parameter mask_debug_etb__COMPID1 = 32'h000000FF; + +parameter debug_etb__COMPID2 = 32'hF8801FF8; +parameter val_debug_etb__COMPID2 = 32'h00000005; +parameter mask_debug_etb__COMPID2 = 32'h000000FF; + +parameter debug_etb__COMPID3 = 32'hF8801FFC; +parameter val_debug_etb__COMPID3 = 32'h000000B1; +parameter mask_debug_etb__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_ftm ftm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_ftm__FTMGLBCTRL = 32'hF880B000; +parameter val_debug_ftm__FTMGLBCTRL = 32'h00000000; +parameter mask_debug_ftm__FTMGLBCTRL = 32'h00000001; + +parameter debug_ftm__FTMSTATUS = 32'hF880B004; +parameter val_debug_ftm__FTMSTATUS = 32'h00000082; +parameter mask_debug_ftm__FTMSTATUS = 32'h000000FF; + +parameter debug_ftm__FTMCONTROL = 32'hF880B008; +parameter val_debug_ftm__FTMCONTROL = 32'h00000000; +parameter mask_debug_ftm__FTMCONTROL = 32'h00000007; + +parameter debug_ftm__FTMP2FDBG0 = 32'hF880B00C; +parameter val_debug_ftm__FTMP2FDBG0 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG0 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG1 = 32'hF880B010; +parameter val_debug_ftm__FTMP2FDBG1 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG1 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG2 = 32'hF880B014; +parameter val_debug_ftm__FTMP2FDBG2 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG2 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG3 = 32'hF880B018; +parameter val_debug_ftm__FTMP2FDBG3 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG3 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG0 = 32'hF880B01C; +parameter val_debug_ftm__FTMF2PDBG0 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG0 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG1 = 32'hF880B020; +parameter val_debug_ftm__FTMF2PDBG1 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG1 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG2 = 32'hF880B024; +parameter val_debug_ftm__FTMF2PDBG2 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG2 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG3 = 32'hF880B028; +parameter val_debug_ftm__FTMF2PDBG3 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG3 = 32'h000000FF; + +parameter debug_ftm__CYCOUNTPRE = 32'hF880B02C; +parameter val_debug_ftm__CYCOUNTPRE = 32'h00000000; +parameter mask_debug_ftm__CYCOUNTPRE = 32'h0000000F; + +parameter debug_ftm__FTMSYNCRELOAD = 32'hF880B030; +parameter val_debug_ftm__FTMSYNCRELOAD = 32'h00000000; +parameter mask_debug_ftm__FTMSYNCRELOAD = 32'h00000FFF; + +parameter debug_ftm__FTMSYNCCOUT = 32'hF880B034; +parameter val_debug_ftm__FTMSYNCCOUT = 32'h00000000; +parameter mask_debug_ftm__FTMSYNCCOUT = 32'h00000FFF; + +parameter debug_ftm__FTMATID = 32'hF880B400; +parameter val_debug_ftm__FTMATID = 32'h00000000; +parameter mask_debug_ftm__FTMATID = 32'h0000007F; + +parameter debug_ftm__FTMITTRIGOUTACK = 32'hF880BED0; +parameter val_debug_ftm__FTMITTRIGOUTACK = 32'h00000000; +parameter mask_debug_ftm__FTMITTRIGOUTACK = 32'h0000000F; + +parameter debug_ftm__FTMITTRIGGER = 32'hF880BED4; +parameter val_debug_ftm__FTMITTRIGGER = 32'h00000000; +parameter mask_debug_ftm__FTMITTRIGGER = 32'h0000000F; + +parameter debug_ftm__FTMITTRACEDIS = 32'hF880BED8; +parameter val_debug_ftm__FTMITTRACEDIS = 32'h00000000; +parameter mask_debug_ftm__FTMITTRACEDIS = 32'h00000001; + +parameter debug_ftm__FTMITCYCCOUNT = 32'hF880BEDC; +parameter val_debug_ftm__FTMITCYCCOUNT = 32'h00000001; +parameter mask_debug_ftm__FTMITCYCCOUNT = 32'hFFFFFFFF; + +parameter debug_ftm__FTMITATBDATA0 = 32'hF880BEEC; +parameter val_debug_ftm__FTMITATBDATA0 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBDATA0 = 32'h0000001F; + +parameter debug_ftm__FTMITATBCTR2 = 32'hF880BEF0; +parameter val_debug_ftm__FTMITATBCTR2 = 32'h00000001; +parameter mask_debug_ftm__FTMITATBCTR2 = 32'h00000003; + +parameter debug_ftm__FTMITATBCTR1 = 32'hF880BEF4; +parameter val_debug_ftm__FTMITATBCTR1 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBCTR1 = 32'h0000007F; + +parameter debug_ftm__FTMITATBCTR0 = 32'hF880BEF8; +parameter val_debug_ftm__FTMITATBCTR0 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBCTR0 = 32'h000003FF; + +parameter debug_ftm__FTMITCR = 32'hF880BF00; +parameter val_debug_ftm__FTMITCR = 32'h00000000; +parameter mask_debug_ftm__FTMITCR = 32'h00000001; + +parameter debug_ftm__CLAIMTAGSET = 32'hF880BFA0; +parameter val_debug_ftm__CLAIMTAGSET = 32'h000000FF; +parameter mask_debug_ftm__CLAIMTAGSET = 32'h000000FF; + +parameter debug_ftm__CLAIMTAGCLR = 32'hF880BFA4; +parameter val_debug_ftm__CLAIMTAGCLR = 32'h000000FF; +parameter mask_debug_ftm__CLAIMTAGCLR = 32'h000000FF; + +parameter debug_ftm__LOCK_ACCESS = 32'hF880BFB0; +parameter val_debug_ftm__LOCK_ACCESS = 32'h00000000; +parameter mask_debug_ftm__LOCK_ACCESS = 32'hFFFFFFFF; + +parameter debug_ftm__LOCK_STATUS = 32'hF880BFB4; +parameter val_debug_ftm__LOCK_STATUS = 32'h00000003; +parameter mask_debug_ftm__LOCK_STATUS = 32'h00000007; + +parameter debug_ftm__FTMAUTHSTATUS = 32'hF880BFB8; +parameter val_debug_ftm__FTMAUTHSTATUS = 32'h00000088; +parameter mask_debug_ftm__FTMAUTHSTATUS = 32'h000000FF; + +parameter debug_ftm__FTMDEVID = 32'hF880BFC8; +parameter val_debug_ftm__FTMDEVID = 32'h00000000; +parameter mask_debug_ftm__FTMDEVID = 32'h00000001; + +parameter debug_ftm__FTMDEV_TYPE = 32'hF880BFCC; +parameter val_debug_ftm__FTMDEV_TYPE = 32'h00000033; +parameter mask_debug_ftm__FTMDEV_TYPE = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID4 = 32'hF880BFD0; +parameter val_debug_ftm__FTMPERIPHID4 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID4 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID5 = 32'hF880BFD4; +parameter val_debug_ftm__FTMPERIPHID5 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID5 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID6 = 32'hF880BFD8; +parameter val_debug_ftm__FTMPERIPHID6 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID6 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID7 = 32'hF880BFDC; +parameter val_debug_ftm__FTMPERIPHID7 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID7 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID0 = 32'hF880BFE0; +parameter val_debug_ftm__FTMPERIPHID0 = 32'h00000001; +parameter mask_debug_ftm__FTMPERIPHID0 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID1 = 32'hF880BFE4; +parameter val_debug_ftm__FTMPERIPHID1 = 32'h00000090; +parameter mask_debug_ftm__FTMPERIPHID1 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID2 = 32'hF880BFE8; +parameter val_debug_ftm__FTMPERIPHID2 = 32'h0000000C; +parameter mask_debug_ftm__FTMPERIPHID2 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID3 = 32'hF880BFEC; +parameter val_debug_ftm__FTMPERIPHID3 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID3 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID0 = 32'hF880BFF0; +parameter val_debug_ftm__FTMCOMPONID0 = 32'h0000000D; +parameter mask_debug_ftm__FTMCOMPONID0 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID1 = 32'hF880BFF4; +parameter val_debug_ftm__FTMCOMPONID1 = 32'h00000090; +parameter mask_debug_ftm__FTMCOMPONID1 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID2 = 32'hF880BFF8; +parameter val_debug_ftm__FTMCOMPONID2 = 32'h00000005; +parameter mask_debug_ftm__FTMCOMPONID2 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID3 = 32'hF880BFFC; +parameter val_debug_ftm__FTMCOMPONID3 = 32'h000000B1; +parameter mask_debug_ftm__FTMCOMPONID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_funnel funnel +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_funnel__Control = 32'hF8804000; +parameter val_debug_funnel__Control = 32'h00000300; +parameter mask_debug_funnel__Control = 32'h00000FFF; + +parameter debug_funnel__PriControl = 32'hF8804004; +parameter val_debug_funnel__PriControl = 32'h00FAC688; +parameter mask_debug_funnel__PriControl = 32'h00FFFFFF; + +parameter debug_funnel__ITATBDATA0 = 32'hF8804EEC; +parameter val_debug_funnel__ITATBDATA0 = 32'h00000000; +parameter mask_debug_funnel__ITATBDATA0 = 32'h0000001F; + +parameter debug_funnel__ITATBCTR2 = 32'hF8804EF0; +parameter val_debug_funnel__ITATBCTR2 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR2 = 32'h00000003; + +parameter debug_funnel__ITATBCTR1 = 32'hF8804EF4; +parameter val_debug_funnel__ITATBCTR1 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR1 = 32'h0000007F; + +parameter debug_funnel__ITATBCTR0 = 32'hF8804EF8; +parameter val_debug_funnel__ITATBCTR0 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR0 = 32'h000003FF; + +parameter debug_funnel__IMCR = 32'hF8804F00; +parameter val_debug_funnel__IMCR = 32'h00000000; +parameter mask_debug_funnel__IMCR = 32'h00000001; + +parameter debug_funnel__CTSR = 32'hF8804FA0; +parameter val_debug_funnel__CTSR = 32'h0000000F; +parameter mask_debug_funnel__CTSR = 32'h0000000F; + +parameter debug_funnel__CTCR = 32'hF8804FA4; +parameter val_debug_funnel__CTCR = 32'h00000000; +parameter mask_debug_funnel__CTCR = 32'h0000000F; + +parameter debug_funnel__LAR = 32'hF8804FB0; +parameter val_debug_funnel__LAR = 32'h00000000; +parameter mask_debug_funnel__LAR = 32'hFFFFFFFF; + +parameter debug_funnel__LSR = 32'hF8804FB4; +parameter val_debug_funnel__LSR = 32'h00000003; +parameter mask_debug_funnel__LSR = 32'h00000007; + +parameter debug_funnel__ASR = 32'hF8804FB8; +parameter val_debug_funnel__ASR = 32'h00000000; +parameter mask_debug_funnel__ASR = 32'h000000FF; + +parameter debug_funnel__DEVID = 32'hF8804FC8; +parameter val_debug_funnel__DEVID = 32'h00000028; +parameter mask_debug_funnel__DEVID = 32'h000000FF; + +parameter debug_funnel__DTIR = 32'hF8804FCC; +parameter val_debug_funnel__DTIR = 32'h00000012; +parameter mask_debug_funnel__DTIR = 32'h000000FF; + +parameter debug_funnel__PERIPHID4 = 32'hF8804FD0; +parameter val_debug_funnel__PERIPHID4 = 32'h00000004; +parameter mask_debug_funnel__PERIPHID4 = 32'h000000FF; + +parameter debug_funnel__PERIPHID5 = 32'hF8804FD4; +parameter val_debug_funnel__PERIPHID5 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID5 = 32'h000000FF; + +parameter debug_funnel__PERIPHID6 = 32'hF8804FD8; +parameter val_debug_funnel__PERIPHID6 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID6 = 32'h000000FF; + +parameter debug_funnel__PERIPHID7 = 32'hF8804FDC; +parameter val_debug_funnel__PERIPHID7 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID7 = 32'h000000FF; + +parameter debug_funnel__PERIPHID0 = 32'hF8804FE0; +parameter val_debug_funnel__PERIPHID0 = 32'h00000008; +parameter mask_debug_funnel__PERIPHID0 = 32'h000000FF; + +parameter debug_funnel__PERIPHID1 = 32'hF8804FE4; +parameter val_debug_funnel__PERIPHID1 = 32'h000000B9; +parameter mask_debug_funnel__PERIPHID1 = 32'h000000FF; + +parameter debug_funnel__PERIPHID2 = 32'hF8804FE8; +parameter val_debug_funnel__PERIPHID2 = 32'h0000001B; +parameter mask_debug_funnel__PERIPHID2 = 32'h000000FF; + +parameter debug_funnel__PERIPHID3 = 32'hF8804FEC; +parameter val_debug_funnel__PERIPHID3 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID3 = 32'h000000FF; + +parameter debug_funnel__COMPID0 = 32'hF8804FF0; +parameter val_debug_funnel__COMPID0 = 32'h0000000D; +parameter mask_debug_funnel__COMPID0 = 32'h000000FF; + +parameter debug_funnel__COMPID1 = 32'hF8804FF4; +parameter val_debug_funnel__COMPID1 = 32'h00000090; +parameter mask_debug_funnel__COMPID1 = 32'h000000FF; + +parameter debug_funnel__COMPID2 = 32'hF8804FF8; +parameter val_debug_funnel__COMPID2 = 32'h00000005; +parameter mask_debug_funnel__COMPID2 = 32'h000000FF; + +parameter debug_funnel__COMPID3 = 32'hF8804FFC; +parameter val_debug_funnel__COMPID3 = 32'h000000B1; +parameter mask_debug_funnel__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_itm itm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_itm__StimPort00 = 32'hF8805000; +parameter val_debug_itm__StimPort00 = 32'h00000000; +parameter mask_debug_itm__StimPort00 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort01 = 32'hF8805004; +parameter val_debug_itm__StimPort01 = 32'h00000000; +parameter mask_debug_itm__StimPort01 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort02 = 32'hF8805008; +parameter val_debug_itm__StimPort02 = 32'h00000000; +parameter mask_debug_itm__StimPort02 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort03 = 32'hF880500C; +parameter val_debug_itm__StimPort03 = 32'h00000000; +parameter mask_debug_itm__StimPort03 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort04 = 32'hF8805010; +parameter val_debug_itm__StimPort04 = 32'h00000000; +parameter mask_debug_itm__StimPort04 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort05 = 32'hF8805014; +parameter val_debug_itm__StimPort05 = 32'h00000000; +parameter mask_debug_itm__StimPort05 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort06 = 32'hF8805018; +parameter val_debug_itm__StimPort06 = 32'h00000000; +parameter mask_debug_itm__StimPort06 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort07 = 32'hF880501C; +parameter val_debug_itm__StimPort07 = 32'h00000000; +parameter mask_debug_itm__StimPort07 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort08 = 32'hF8805020; +parameter val_debug_itm__StimPort08 = 32'h00000000; +parameter mask_debug_itm__StimPort08 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort09 = 32'hF8805024; +parameter val_debug_itm__StimPort09 = 32'h00000000; +parameter mask_debug_itm__StimPort09 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort10 = 32'hF8805028; +parameter val_debug_itm__StimPort10 = 32'h00000000; +parameter mask_debug_itm__StimPort10 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort11 = 32'hF880502C; +parameter val_debug_itm__StimPort11 = 32'h00000000; +parameter mask_debug_itm__StimPort11 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort12 = 32'hF8805030; +parameter val_debug_itm__StimPort12 = 32'h00000000; +parameter mask_debug_itm__StimPort12 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort13 = 32'hF8805034; +parameter val_debug_itm__StimPort13 = 32'h00000000; +parameter mask_debug_itm__StimPort13 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort14 = 32'hF8805038; +parameter val_debug_itm__StimPort14 = 32'h00000000; +parameter mask_debug_itm__StimPort14 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort15 = 32'hF880503C; +parameter val_debug_itm__StimPort15 = 32'h00000000; +parameter mask_debug_itm__StimPort15 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort16 = 32'hF8805040; +parameter val_debug_itm__StimPort16 = 32'h00000000; +parameter mask_debug_itm__StimPort16 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort17 = 32'hF8805044; +parameter val_debug_itm__StimPort17 = 32'h00000000; +parameter mask_debug_itm__StimPort17 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort18 = 32'hF8805048; +parameter val_debug_itm__StimPort18 = 32'h00000000; +parameter mask_debug_itm__StimPort18 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort19 = 32'hF880504C; +parameter val_debug_itm__StimPort19 = 32'h00000000; +parameter mask_debug_itm__StimPort19 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort20 = 32'hF8805050; +parameter val_debug_itm__StimPort20 = 32'h00000000; +parameter mask_debug_itm__StimPort20 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort21 = 32'hF8805054; +parameter val_debug_itm__StimPort21 = 32'h00000000; +parameter mask_debug_itm__StimPort21 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort22 = 32'hF8805058; +parameter val_debug_itm__StimPort22 = 32'h00000000; +parameter mask_debug_itm__StimPort22 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort23 = 32'hF880505C; +parameter val_debug_itm__StimPort23 = 32'h00000000; +parameter mask_debug_itm__StimPort23 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort24 = 32'hF8805060; +parameter val_debug_itm__StimPort24 = 32'h00000000; +parameter mask_debug_itm__StimPort24 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort25 = 32'hF8805064; +parameter val_debug_itm__StimPort25 = 32'h00000000; +parameter mask_debug_itm__StimPort25 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort26 = 32'hF8805068; +parameter val_debug_itm__StimPort26 = 32'h00000000; +parameter mask_debug_itm__StimPort26 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort27 = 32'hF880506C; +parameter val_debug_itm__StimPort27 = 32'h00000000; +parameter mask_debug_itm__StimPort27 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort28 = 32'hF8805070; +parameter val_debug_itm__StimPort28 = 32'h00000000; +parameter mask_debug_itm__StimPort28 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort29 = 32'hF8805074; +parameter val_debug_itm__StimPort29 = 32'h00000000; +parameter mask_debug_itm__StimPort29 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort30 = 32'hF8805078; +parameter val_debug_itm__StimPort30 = 32'h00000000; +parameter mask_debug_itm__StimPort30 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort31 = 32'hF880507C; +parameter val_debug_itm__StimPort31 = 32'h00000000; +parameter mask_debug_itm__StimPort31 = 32'hFFFFFFFF; + +parameter debug_itm__TER = 32'hF8805E00; +parameter val_debug_itm__TER = 32'h00000000; +parameter mask_debug_itm__TER = 32'hFFFFFFFF; + +parameter debug_itm__TTR = 32'hF8805E20; +parameter val_debug_itm__TTR = 32'h00000000; +parameter mask_debug_itm__TTR = 32'hFFFFFFFF; + +parameter debug_itm__CR = 32'hF8805E80; +parameter val_debug_itm__CR = 32'h00000004; +parameter mask_debug_itm__CR = 32'h00FFFFFF; + +parameter debug_itm__SCR = 32'hF8805E90; +parameter val_debug_itm__SCR = 32'h00000400; +parameter mask_debug_itm__SCR = 32'h00000FFF; + +parameter debug_itm__ITTRIGOUTACK = 32'hF8805EE4; +parameter val_debug_itm__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_itm__ITTRIGOUTACK = 32'h00000001; + +parameter debug_itm__ITTRIGOUT = 32'hF8805EE8; +parameter val_debug_itm__ITTRIGOUT = 32'h00000000; +parameter mask_debug_itm__ITTRIGOUT = 32'h00000001; + +parameter debug_itm__ITATBDATA0 = 32'hF8805EEC; +parameter val_debug_itm__ITATBDATA0 = 32'h00000000; +parameter mask_debug_itm__ITATBDATA0 = 32'h00000003; + +parameter debug_itm__ITATBCTR2 = 32'hF8805EF0; +parameter val_debug_itm__ITATBCTR2 = 32'h00000001; +parameter mask_debug_itm__ITATBCTR2 = 32'h00000001; + +parameter debug_itm__ITATABCTR1 = 32'hF8805EF4; +parameter val_debug_itm__ITATABCTR1 = 32'h00000000; +parameter mask_debug_itm__ITATABCTR1 = 32'h0000007F; + +parameter debug_itm__ITATBCTR0 = 32'hF8805EF8; +parameter val_debug_itm__ITATBCTR0 = 32'h00000000; +parameter mask_debug_itm__ITATBCTR0 = 32'h00000003; + +parameter debug_itm__IMCR = 32'hF8805F00; +parameter val_debug_itm__IMCR = 32'h00000000; +parameter mask_debug_itm__IMCR = 32'h00000001; + +parameter debug_itm__CTSR = 32'hF8805FA0; +parameter val_debug_itm__CTSR = 32'h000000FF; +parameter mask_debug_itm__CTSR = 32'h000000FF; + +parameter debug_itm__CTCR = 32'hF8805FA4; +parameter val_debug_itm__CTCR = 32'h00000000; +parameter mask_debug_itm__CTCR = 32'h000000FF; + +parameter debug_itm__LAR = 32'hF8805FB0; +parameter val_debug_itm__LAR = 32'h00000000; +parameter mask_debug_itm__LAR = 32'hFFFFFFFF; + +parameter debug_itm__LSR = 32'hF8805FB4; +parameter val_debug_itm__LSR = 32'h00000003; +parameter mask_debug_itm__LSR = 32'h00000007; + +parameter debug_itm__ASR = 32'hF8805FB8; +parameter val_debug_itm__ASR = 32'h00000088; +parameter mask_debug_itm__ASR = 32'h000000FF; + +parameter debug_itm__DEVID = 32'hF8805FC8; +parameter val_debug_itm__DEVID = 32'h00000020; +parameter mask_debug_itm__DEVID = 32'h00001FFF; + +parameter debug_itm__DTIR = 32'hF8805FCC; +parameter val_debug_itm__DTIR = 32'h00000043; +parameter mask_debug_itm__DTIR = 32'h000000FF; + +parameter debug_itm__PERIPHID4 = 32'hF8805FD0; +parameter val_debug_itm__PERIPHID4 = 32'h00000004; +parameter mask_debug_itm__PERIPHID4 = 32'h000000FF; + +parameter debug_itm__PERIPHID5 = 32'hF8805FD4; +parameter val_debug_itm__PERIPHID5 = 32'h00000000; +parameter mask_debug_itm__PERIPHID5 = 32'h000000FF; + +parameter debug_itm__PERIPHID6 = 32'hF8805FD8; +parameter val_debug_itm__PERIPHID6 = 32'h00000000; +parameter mask_debug_itm__PERIPHID6 = 32'h000000FF; + +parameter debug_itm__PERIPHID7 = 32'hF8805FDC; +parameter val_debug_itm__PERIPHID7 = 32'h00000000; +parameter mask_debug_itm__PERIPHID7 = 32'h000000FF; + +parameter debug_itm__PERIPHID0 = 32'hF8805FE0; +parameter val_debug_itm__PERIPHID0 = 32'h00000013; +parameter mask_debug_itm__PERIPHID0 = 32'h000000FF; + +parameter debug_itm__PERIPHID1 = 32'hF8805FE4; +parameter val_debug_itm__PERIPHID1 = 32'h000000B9; +parameter mask_debug_itm__PERIPHID1 = 32'h000000FF; + +parameter debug_itm__PERIPHID2 = 32'hF8805FE8; +parameter val_debug_itm__PERIPHID2 = 32'h0000002B; +parameter mask_debug_itm__PERIPHID2 = 32'h000000FF; + +parameter debug_itm__PERIPHID3 = 32'hF8805FEC; +parameter val_debug_itm__PERIPHID3 = 32'h00000000; +parameter mask_debug_itm__PERIPHID3 = 32'h000000FF; + +parameter debug_itm__COMPID0 = 32'hF8805FF0; +parameter val_debug_itm__COMPID0 = 32'h0000000D; +parameter mask_debug_itm__COMPID0 = 32'h000000FF; + +parameter debug_itm__COMPID1 = 32'hF8805FF4; +parameter val_debug_itm__COMPID1 = 32'h00000090; +parameter mask_debug_itm__COMPID1 = 32'h000000FF; + +parameter debug_itm__COMPID2 = 32'hF8805FF8; +parameter val_debug_itm__COMPID2 = 32'h00000005; +parameter mask_debug_itm__COMPID2 = 32'h000000FF; + +parameter debug_itm__COMPID3 = 32'hF8805FFC; +parameter val_debug_itm__COMPID3 = 32'h000000B1; +parameter mask_debug_itm__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_tpiu tpiu +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_tpiu__SuppSize = 32'hF8803000; +parameter val_debug_tpiu__SuppSize = 32'hFFFFFFFF; +parameter mask_debug_tpiu__SuppSize = 32'hFFFFFFFF; + +parameter debug_tpiu__CurrentSize = 32'hF8803004; +parameter val_debug_tpiu__CurrentSize = 32'h00000001; +parameter mask_debug_tpiu__CurrentSize = 32'hFFFFFFFF; + +parameter debug_tpiu__SuppTrigMode = 32'hF8803100; +parameter val_debug_tpiu__SuppTrigMode = 32'h0000011F; +parameter mask_debug_tpiu__SuppTrigMode = 32'h0003FFFF; + +parameter debug_tpiu__TrigCount = 32'hF8803104; +parameter val_debug_tpiu__TrigCount = 32'h00000000; +parameter mask_debug_tpiu__TrigCount = 32'h000000FF; + +parameter debug_tpiu__TrigMult = 32'hF8803108; +parameter val_debug_tpiu__TrigMult = 32'h00000000; +parameter mask_debug_tpiu__TrigMult = 32'h0000001F; + +parameter debug_tpiu__SuppTest = 32'hF8803200; +parameter val_debug_tpiu__SuppTest = 32'h0003000F; +parameter mask_debug_tpiu__SuppTest = 32'h0003FFFF; + +parameter debug_tpiu__CurrentTest = 32'hF8803204; +parameter val_debug_tpiu__CurrentTest = 32'h00000000; +parameter mask_debug_tpiu__CurrentTest = 32'h0003FFFF; + +parameter debug_tpiu__TestRepeatCount = 32'hF8803208; +parameter val_debug_tpiu__TestRepeatCount = 32'h00000000; +parameter mask_debug_tpiu__TestRepeatCount = 32'h000000FF; + +parameter debug_tpiu__FFSR = 32'hF8803300; +parameter val_debug_tpiu__FFSR = 32'h00000006; +parameter mask_debug_tpiu__FFSR = 32'h00000007; + +parameter debug_tpiu__FFCR = 32'hF8803304; +parameter val_debug_tpiu__FFCR = 32'h00000000; +parameter mask_debug_tpiu__FFCR = 32'h00003FFF; + +parameter debug_tpiu__FormatSyncCount = 32'hF8803308; +parameter val_debug_tpiu__FormatSyncCount = 32'h00000040; +parameter mask_debug_tpiu__FormatSyncCount = 32'h00000FFF; + +parameter debug_tpiu__EXTCTLIn = 32'hF8803400; +parameter val_debug_tpiu__EXTCTLIn = 32'h00000000; +parameter mask_debug_tpiu__EXTCTLIn = 32'h000000FF; + +parameter debug_tpiu__EXTCTLOut = 32'hF8803404; +parameter val_debug_tpiu__EXTCTLOut = 32'h00000000; +parameter mask_debug_tpiu__EXTCTLOut = 32'h000000FF; + +parameter debug_tpiu__ITTRFLINACK = 32'hF8803EE4; +parameter val_debug_tpiu__ITTRFLINACK = 32'h00000000; +parameter mask_debug_tpiu__ITTRFLINACK = 32'h00000003; + +parameter debug_tpiu__ITTRFLIN = 32'hF8803EE8; +parameter val_debug_tpiu__ITTRFLIN = 32'h00000000; +parameter mask_debug_tpiu__ITTRFLIN = 32'h00000000; + +parameter debug_tpiu__ITATBDATA0 = 32'hF8803EEC; +parameter val_debug_tpiu__ITATBDATA0 = 32'h00000000; +parameter mask_debug_tpiu__ITATBDATA0 = 32'h00000000; + +parameter debug_tpiu__ITATBCTR2 = 32'hF8803EF0; +parameter val_debug_tpiu__ITATBCTR2 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR2 = 32'h00000003; + +parameter debug_tpiu__ITATBCTR1 = 32'hF8803EF4; +parameter val_debug_tpiu__ITATBCTR1 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR1 = 32'h00000000; + +parameter debug_tpiu__ITATBCTR0 = 32'hF8803EF8; +parameter val_debug_tpiu__ITATBCTR0 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR0 = 32'h00000000; + +parameter debug_tpiu__IMCR = 32'hF8803F00; +parameter val_debug_tpiu__IMCR = 32'h00000000; +parameter mask_debug_tpiu__IMCR = 32'h00000001; + +parameter debug_tpiu__CTSR = 32'hF8803FA0; +parameter val_debug_tpiu__CTSR = 32'h0000000F; +parameter mask_debug_tpiu__CTSR = 32'h0000000F; + +parameter debug_tpiu__CTCR = 32'hF8803FA4; +parameter val_debug_tpiu__CTCR = 32'h00000000; +parameter mask_debug_tpiu__CTCR = 32'h0000000F; + +parameter debug_tpiu__LAR = 32'hF8803FB0; +parameter val_debug_tpiu__LAR = 32'h00000000; +parameter mask_debug_tpiu__LAR = 32'hFFFFFFFF; + +parameter debug_tpiu__LSR = 32'hF8803FB4; +parameter val_debug_tpiu__LSR = 32'h00000003; +parameter mask_debug_tpiu__LSR = 32'h00000007; + +parameter debug_tpiu__ASR = 32'hF8803FB8; +parameter val_debug_tpiu__ASR = 32'h00000000; +parameter mask_debug_tpiu__ASR = 32'h000000FF; + +parameter debug_tpiu__DEVID = 32'hF8803FC8; +parameter val_debug_tpiu__DEVID = 32'h000000A0; +parameter mask_debug_tpiu__DEVID = 32'h00000FFF; + +parameter debug_tpiu__DTIR = 32'hF8803FCC; +parameter val_debug_tpiu__DTIR = 32'h00000011; +parameter mask_debug_tpiu__DTIR = 32'h000000FF; + +parameter debug_tpiu__PERIPHID4 = 32'hF8803FD0; +parameter val_debug_tpiu__PERIPHID4 = 32'h00000004; +parameter mask_debug_tpiu__PERIPHID4 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID5 = 32'hF8803FD4; +parameter val_debug_tpiu__PERIPHID5 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID5 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID6 = 32'hF8803FD8; +parameter val_debug_tpiu__PERIPHID6 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID6 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID7 = 32'hF8803FDC; +parameter val_debug_tpiu__PERIPHID7 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID7 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID0 = 32'hF8803FE0; +parameter val_debug_tpiu__PERIPHID0 = 32'h00000012; +parameter mask_debug_tpiu__PERIPHID0 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID1 = 32'hF8803FE4; +parameter val_debug_tpiu__PERIPHID1 = 32'h000000B9; +parameter mask_debug_tpiu__PERIPHID1 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID2 = 32'hF8803FE8; +parameter val_debug_tpiu__PERIPHID2 = 32'h0000004B; +parameter mask_debug_tpiu__PERIPHID2 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID3 = 32'hF8803FEC; +parameter val_debug_tpiu__PERIPHID3 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID3 = 32'h000000FF; + +parameter debug_tpiu__COMPID0 = 32'hF8803FF0; +parameter val_debug_tpiu__COMPID0 = 32'h0000000D; +parameter mask_debug_tpiu__COMPID0 = 32'h000000FF; + +parameter debug_tpiu__COMPID1 = 32'hF8803FF4; +parameter val_debug_tpiu__COMPID1 = 32'h00000090; +parameter mask_debug_tpiu__COMPID1 = 32'h000000FF; + +parameter debug_tpiu__COMPID2 = 32'hF8803FF8; +parameter val_debug_tpiu__COMPID2 = 32'h00000005; +parameter mask_debug_tpiu__COMPID2 = 32'h000000FF; + +parameter debug_tpiu__COMPID3 = 32'hF8803FFC; +parameter val_debug_tpiu__COMPID3 = 32'h000000B1; +parameter mask_debug_tpiu__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module devcfg devcfg +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter devcfg__CTRL = 32'hF8007000; +parameter val_devcfg__CTRL = 32'h0C000000; +parameter mask_devcfg__CTRL = 32'hFFFFFFFF; + +parameter devcfg__LOCK = 32'hF8007004; +parameter val_devcfg__LOCK = 32'h00000000; +parameter mask_devcfg__LOCK = 32'hFFFFFFFF; + +parameter devcfg__CFG = 32'hF8007008; +parameter val_devcfg__CFG = 32'h0000050B; +parameter mask_devcfg__CFG = 32'hFFFFFFFF; + +parameter devcfg__INT_STS = 32'hF800700C; +parameter val_devcfg__INT_STS = 32'h00000000; +parameter mask_devcfg__INT_STS = 32'hFFFFFFFF; + +parameter devcfg__INT_MASK = 32'hF8007010; +parameter val_devcfg__INT_MASK = 32'hFFFFFFFF; +parameter mask_devcfg__INT_MASK = 32'hFFFFFFFF; + +parameter devcfg__STATUS = 32'hF8007014; +parameter val_devcfg__STATUS = 32'h40000820; +parameter mask_devcfg__STATUS = 32'hFFFFFFFF; + +parameter devcfg__DMA_SRC_ADDR = 32'hF8007018; +parameter val_devcfg__DMA_SRC_ADDR = 32'h00000000; +parameter mask_devcfg__DMA_SRC_ADDR = 32'hFFFFFFFF; + +parameter devcfg__DMA_DST_ADDR = 32'hF800701C; +parameter val_devcfg__DMA_DST_ADDR = 32'h00000000; +parameter mask_devcfg__DMA_DST_ADDR = 32'hFFFFFFFF; + +parameter devcfg__DMA_SRC_LEN = 32'hF8007020; +parameter val_devcfg__DMA_SRC_LEN = 32'h00000000; +parameter mask_devcfg__DMA_SRC_LEN = 32'hFFFFFFFF; + +parameter devcfg__DMA_DEST_LEN = 32'hF8007024; +parameter val_devcfg__DMA_DEST_LEN = 32'h00000000; +parameter mask_devcfg__DMA_DEST_LEN = 32'hFFFFFFFF; + +parameter devcfg__ROM_SHADOW = 32'hF8007028; +parameter val_devcfg__ROM_SHADOW = 32'h00000000; +parameter mask_devcfg__ROM_SHADOW = 32'hFFFFFFFF; + +parameter devcfg__MULTIBOOT_ADDR = 32'hF800702C; +parameter val_devcfg__MULTIBOOT_ADDR = 32'h00000000; +parameter mask_devcfg__MULTIBOOT_ADDR = 32'hFFFFFFFF; + +parameter devcfg__SW_ID = 32'hF8007030; +parameter val_devcfg__SW_ID = 32'h00000000; +parameter mask_devcfg__SW_ID = 32'hFFFFFFFF; + +parameter devcfg__UNLOCK = 32'hF8007034; +parameter val_devcfg__UNLOCK = 32'h00000000; +parameter mask_devcfg__UNLOCK = 32'hFFFFFFFF; + +parameter devcfg__MCTRL = 32'hF8007080; +parameter val_devcfg__MCTRL = 32'h00800000; +parameter mask_devcfg__MCTRL = 32'h0FFFFFFF; + +parameter devcfg__XADCIF_CFG = 32'hF8007100; +parameter val_devcfg__XADCIF_CFG = 32'h00001114; +parameter mask_devcfg__XADCIF_CFG = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_INT_STS = 32'hF8007104; +parameter val_devcfg__XADCIF_INT_STS = 32'h00000200; +parameter mask_devcfg__XADCIF_INT_STS = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_INT_MASK = 32'hF8007108; +parameter val_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; +parameter mask_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_MSTS = 32'hF800710C; +parameter val_devcfg__XADCIF_MSTS = 32'h00000500; +parameter mask_devcfg__XADCIF_MSTS = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_CMDFIFO = 32'hF8007110; +parameter val_devcfg__XADCIF_CMDFIFO = 32'h00000000; +parameter mask_devcfg__XADCIF_CMDFIFO = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_RDFIFO = 32'hF8007114; +parameter val_devcfg__XADCIF_RDFIFO = 32'h00000000; +parameter mask_devcfg__XADCIF_RDFIFO = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_MCTL = 32'hF8007118; +parameter val_devcfg__XADCIF_MCTL = 32'h00000010; +parameter mask_devcfg__XADCIF_MCTL = 32'hFFFFFFFF; + + +// ************************************************************ +// Module dmac0_ns dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter dmac0_ns__DSR = 32'hF8004000; +parameter val_dmac0_ns__DSR = 32'h00000000; +parameter mask_dmac0_ns__DSR = 32'hFFFFFFFF; + +parameter dmac0_ns__DPC = 32'hF8004004; +parameter val_dmac0_ns__DPC = 32'h00000000; +parameter mask_dmac0_ns__DPC = 32'hFFFFFFFF; + +parameter dmac0_ns__INTEN = 32'hF8004020; +parameter val_dmac0_ns__INTEN = 32'h00000000; +parameter mask_dmac0_ns__INTEN = 32'hFFFFFFFF; + +parameter dmac0_ns__INT_EVENT_RIS = 32'hF8004024; +parameter val_dmac0_ns__INT_EVENT_RIS = 32'h00000000; +parameter mask_dmac0_ns__INT_EVENT_RIS = 32'hFFFFFFFF; + +parameter dmac0_ns__INTMIS = 32'hF8004028; +parameter val_dmac0_ns__INTMIS = 32'h00000000; +parameter mask_dmac0_ns__INTMIS = 32'hFFFFFFFF; + +parameter dmac0_ns__INTCLR = 32'hF800402C; +parameter val_dmac0_ns__INTCLR = 32'h00000000; +parameter mask_dmac0_ns__INTCLR = 32'hFFFFFFFF; + +parameter dmac0_ns__FSRD = 32'hF8004030; +parameter val_dmac0_ns__FSRD = 32'h00000000; +parameter mask_dmac0_ns__FSRD = 32'hFFFFFFFF; + +parameter dmac0_ns__FSRC = 32'hF8004034; +parameter val_dmac0_ns__FSRC = 32'h00000000; +parameter mask_dmac0_ns__FSRC = 32'hFFFFFFFF; + +parameter dmac0_ns__FTRD = 32'hF8004038; +parameter val_dmac0_ns__FTRD = 32'h00000000; +parameter mask_dmac0_ns__FTRD = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR0 = 32'hF8004040; +parameter val_dmac0_ns__FTR0 = 32'h00000000; +parameter mask_dmac0_ns__FTR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR1 = 32'hF8004044; +parameter val_dmac0_ns__FTR1 = 32'h00000000; +parameter mask_dmac0_ns__FTR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR2 = 32'hF8004048; +parameter val_dmac0_ns__FTR2 = 32'h00000000; +parameter mask_dmac0_ns__FTR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR3 = 32'hF800404C; +parameter val_dmac0_ns__FTR3 = 32'h00000000; +parameter mask_dmac0_ns__FTR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR4 = 32'hF8004050; +parameter val_dmac0_ns__FTR4 = 32'h00000000; +parameter mask_dmac0_ns__FTR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR5 = 32'hF8004054; +parameter val_dmac0_ns__FTR5 = 32'h00000000; +parameter mask_dmac0_ns__FTR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR6 = 32'hF8004058; +parameter val_dmac0_ns__FTR6 = 32'h00000000; +parameter mask_dmac0_ns__FTR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR7 = 32'hF800405C; +parameter val_dmac0_ns__FTR7 = 32'h00000000; +parameter mask_dmac0_ns__FTR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR0 = 32'hF8004100; +parameter val_dmac0_ns__CSR0 = 32'h00000000; +parameter mask_dmac0_ns__CSR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC0 = 32'hF8004104; +parameter val_dmac0_ns__CPC0 = 32'h00000000; +parameter mask_dmac0_ns__CPC0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR1 = 32'hF8004108; +parameter val_dmac0_ns__CSR1 = 32'h00000000; +parameter mask_dmac0_ns__CSR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC1 = 32'hF800410C; +parameter val_dmac0_ns__CPC1 = 32'h00000000; +parameter mask_dmac0_ns__CPC1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR2 = 32'hF8004110; +parameter val_dmac0_ns__CSR2 = 32'h00000000; +parameter mask_dmac0_ns__CSR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC2 = 32'hF8004114; +parameter val_dmac0_ns__CPC2 = 32'h00000000; +parameter mask_dmac0_ns__CPC2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR3 = 32'hF8004118; +parameter val_dmac0_ns__CSR3 = 32'h00000000; +parameter mask_dmac0_ns__CSR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC3 = 32'hF800411C; +parameter val_dmac0_ns__CPC3 = 32'h00000000; +parameter mask_dmac0_ns__CPC3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR4 = 32'hF8004120; +parameter val_dmac0_ns__CSR4 = 32'h00000000; +parameter mask_dmac0_ns__CSR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC4 = 32'hF8004124; +parameter val_dmac0_ns__CPC4 = 32'h00000000; +parameter mask_dmac0_ns__CPC4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR5 = 32'hF8004128; +parameter val_dmac0_ns__CSR5 = 32'h00000000; +parameter mask_dmac0_ns__CSR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC5 = 32'hF800412C; +parameter val_dmac0_ns__CPC5 = 32'h00000000; +parameter mask_dmac0_ns__CPC5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR6 = 32'hF8004130; +parameter val_dmac0_ns__CSR6 = 32'h00000000; +parameter mask_dmac0_ns__CSR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC6 = 32'hF8004134; +parameter val_dmac0_ns__CPC6 = 32'h00000000; +parameter mask_dmac0_ns__CPC6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR7 = 32'hF8004138; +parameter val_dmac0_ns__CSR7 = 32'h00000000; +parameter mask_dmac0_ns__CSR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC7 = 32'hF800413C; +parameter val_dmac0_ns__CPC7 = 32'h00000000; +parameter mask_dmac0_ns__CPC7 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR0 = 32'hF8004400; +parameter val_dmac0_ns__SAR0 = 32'h00000000; +parameter mask_dmac0_ns__SAR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR0 = 32'hF8004404; +parameter val_dmac0_ns__DAR0 = 32'h00000000; +parameter mask_dmac0_ns__DAR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR0 = 32'hF8004408; +parameter val_dmac0_ns__CCR0 = 32'h00000000; +parameter mask_dmac0_ns__CCR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_0 = 32'hF800440C; +parameter val_dmac0_ns__LC0_0 = 32'h00000000; +parameter mask_dmac0_ns__LC0_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_0 = 32'hF8004410; +parameter val_dmac0_ns__LC1_0 = 32'h00000000; +parameter mask_dmac0_ns__LC1_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR1 = 32'hF8004420; +parameter val_dmac0_ns__SAR1 = 32'h00000000; +parameter mask_dmac0_ns__SAR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR1 = 32'hF8004424; +parameter val_dmac0_ns__DAR1 = 32'h00000000; +parameter mask_dmac0_ns__DAR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR1 = 32'hF8004428; +parameter val_dmac0_ns__CCR1 = 32'h00000000; +parameter mask_dmac0_ns__CCR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_1 = 32'hF800442C; +parameter val_dmac0_ns__LC0_1 = 32'h00000000; +parameter mask_dmac0_ns__LC0_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_1 = 32'hF8004430; +parameter val_dmac0_ns__LC1_1 = 32'h00000000; +parameter mask_dmac0_ns__LC1_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR2 = 32'hF8004440; +parameter val_dmac0_ns__SAR2 = 32'h00000000; +parameter mask_dmac0_ns__SAR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR2 = 32'hF8004444; +parameter val_dmac0_ns__DAR2 = 32'h00000000; +parameter mask_dmac0_ns__DAR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR2 = 32'hF8004448; +parameter val_dmac0_ns__CCR2 = 32'h00000000; +parameter mask_dmac0_ns__CCR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_2 = 32'hF800444C; +parameter val_dmac0_ns__LC0_2 = 32'h00000000; +parameter mask_dmac0_ns__LC0_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_2 = 32'hF8004450; +parameter val_dmac0_ns__LC1_2 = 32'h00000000; +parameter mask_dmac0_ns__LC1_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR3 = 32'hF8004460; +parameter val_dmac0_ns__SAR3 = 32'h00000000; +parameter mask_dmac0_ns__SAR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR3 = 32'hF8004464; +parameter val_dmac0_ns__DAR3 = 32'h00000000; +parameter mask_dmac0_ns__DAR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR3 = 32'hF8004468; +parameter val_dmac0_ns__CCR3 = 32'h00000000; +parameter mask_dmac0_ns__CCR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_3 = 32'hF800446C; +parameter val_dmac0_ns__LC0_3 = 32'h00000000; +parameter mask_dmac0_ns__LC0_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_3 = 32'hF8004470; +parameter val_dmac0_ns__LC1_3 = 32'h00000000; +parameter mask_dmac0_ns__LC1_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR4 = 32'hF8004480; +parameter val_dmac0_ns__SAR4 = 32'h00000000; +parameter mask_dmac0_ns__SAR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR4 = 32'hF8004484; +parameter val_dmac0_ns__DAR4 = 32'h00000000; +parameter mask_dmac0_ns__DAR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR4 = 32'hF8004488; +parameter val_dmac0_ns__CCR4 = 32'h00000000; +parameter mask_dmac0_ns__CCR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_4 = 32'hF800448C; +parameter val_dmac0_ns__LC0_4 = 32'h00000000; +parameter mask_dmac0_ns__LC0_4 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_4 = 32'hF8004490; +parameter val_dmac0_ns__LC1_4 = 32'h00000000; +parameter mask_dmac0_ns__LC1_4 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR5 = 32'hF80044A0; +parameter val_dmac0_ns__SAR5 = 32'h00000000; +parameter mask_dmac0_ns__SAR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR5 = 32'hF80044A4; +parameter val_dmac0_ns__DAR5 = 32'h00000000; +parameter mask_dmac0_ns__DAR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR5 = 32'hF80044A8; +parameter val_dmac0_ns__CCR5 = 32'h00000000; +parameter mask_dmac0_ns__CCR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_5 = 32'hF80044AC; +parameter val_dmac0_ns__LC0_5 = 32'h00000000; +parameter mask_dmac0_ns__LC0_5 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_5 = 32'hF80044B0; +parameter val_dmac0_ns__LC1_5 = 32'h00000000; +parameter mask_dmac0_ns__LC1_5 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR6 = 32'hF80044C0; +parameter val_dmac0_ns__SAR6 = 32'h00000000; +parameter mask_dmac0_ns__SAR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR6 = 32'hF80044C4; +parameter val_dmac0_ns__DAR6 = 32'h00000000; +parameter mask_dmac0_ns__DAR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR6 = 32'hF80044C8; +parameter val_dmac0_ns__CCR6 = 32'h00000000; +parameter mask_dmac0_ns__CCR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_6 = 32'hF80044CC; +parameter val_dmac0_ns__LC0_6 = 32'h00000000; +parameter mask_dmac0_ns__LC0_6 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_6 = 32'hF80044D0; +parameter val_dmac0_ns__LC1_6 = 32'h00000000; +parameter mask_dmac0_ns__LC1_6 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR7 = 32'hF80044E0; +parameter val_dmac0_ns__SAR7 = 32'h00000000; +parameter mask_dmac0_ns__SAR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR7 = 32'hF80044E4; +parameter val_dmac0_ns__DAR7 = 32'h00000000; +parameter mask_dmac0_ns__DAR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR7 = 32'hF80044E8; +parameter val_dmac0_ns__CCR7 = 32'h00000000; +parameter mask_dmac0_ns__CCR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_7 = 32'hF80044EC; +parameter val_dmac0_ns__LC0_7 = 32'h00000000; +parameter mask_dmac0_ns__LC0_7 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_7 = 32'hF80044F0; +parameter val_dmac0_ns__LC1_7 = 32'h00000000; +parameter mask_dmac0_ns__LC1_7 = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGSTATUS = 32'hF8004D00; +parameter val_dmac0_ns__DBGSTATUS = 32'h00000000; +parameter mask_dmac0_ns__DBGSTATUS = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGCMD = 32'hF8004D04; +parameter val_dmac0_ns__DBGCMD = 32'h00000000; +parameter mask_dmac0_ns__DBGCMD = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGINST0 = 32'hF8004D08; +parameter val_dmac0_ns__DBGINST0 = 32'h00000000; +parameter mask_dmac0_ns__DBGINST0 = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGINST1 = 32'hF8004D0C; +parameter val_dmac0_ns__DBGINST1 = 32'h00000000; +parameter mask_dmac0_ns__DBGINST1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR0 = 32'hF8004E00; +parameter val_dmac0_ns__CR0 = 32'h00000000; +parameter mask_dmac0_ns__CR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR1 = 32'hF8004E04; +parameter val_dmac0_ns__CR1 = 32'h00000000; +parameter mask_dmac0_ns__CR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR2 = 32'hF8004E08; +parameter val_dmac0_ns__CR2 = 32'h00000000; +parameter mask_dmac0_ns__CR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR3 = 32'hF8004E0C; +parameter val_dmac0_ns__CR3 = 32'h00000000; +parameter mask_dmac0_ns__CR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR4 = 32'hF8004E10; +parameter val_dmac0_ns__CR4 = 32'h00000000; +parameter mask_dmac0_ns__CR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CRD = 32'hF8004E14; +parameter val_dmac0_ns__CRD = 32'h00000000; +parameter mask_dmac0_ns__CRD = 32'hFFFFFFFF; + +parameter dmac0_ns__WD = 32'hF8004E80; +parameter val_dmac0_ns__WD = 32'h00000000; +parameter mask_dmac0_ns__WD = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_0 = 32'hF8004FE0; +parameter val_dmac0_ns__periph_id_0 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_1 = 32'hF8004FE4; +parameter val_dmac0_ns__periph_id_1 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_2 = 32'hF8004FE8; +parameter val_dmac0_ns__periph_id_2 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_3 = 32'hF8004FEC; +parameter val_dmac0_ns__periph_id_3 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_0 = 32'hF8004FF0; +parameter val_dmac0_ns__pcell_id_0 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_1 = 32'hF8004FF4; +parameter val_dmac0_ns__pcell_id_1 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_2 = 32'hF8004FF8; +parameter val_dmac0_ns__pcell_id_2 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_3 = 32'hF8004FFC; +parameter val_dmac0_ns__pcell_id_3 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module dmac0_s dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter dmac0_s__DSR = 32'hF8003000; +parameter val_dmac0_s__DSR = 32'h00000000; +parameter mask_dmac0_s__DSR = 32'hFFFFFFFF; + +parameter dmac0_s__DPC = 32'hF8003004; +parameter val_dmac0_s__DPC = 32'h00000000; +parameter mask_dmac0_s__DPC = 32'hFFFFFFFF; + +parameter dmac0_s__INTEN = 32'hF8003020; +parameter val_dmac0_s__INTEN = 32'h00000000; +parameter mask_dmac0_s__INTEN = 32'hFFFFFFFF; + +parameter dmac0_s__INT_EVENT_RIS = 32'hF8003024; +parameter val_dmac0_s__INT_EVENT_RIS = 32'h00000000; +parameter mask_dmac0_s__INT_EVENT_RIS = 32'hFFFFFFFF; + +parameter dmac0_s__INTMIS = 32'hF8003028; +parameter val_dmac0_s__INTMIS = 32'h00000000; +parameter mask_dmac0_s__INTMIS = 32'hFFFFFFFF; + +parameter dmac0_s__INTCLR = 32'hF800302C; +parameter val_dmac0_s__INTCLR = 32'h00000000; +parameter mask_dmac0_s__INTCLR = 32'hFFFFFFFF; + +parameter dmac0_s__FSRD = 32'hF8003030; +parameter val_dmac0_s__FSRD = 32'h00000000; +parameter mask_dmac0_s__FSRD = 32'hFFFFFFFF; + +parameter dmac0_s__FSRC = 32'hF8003034; +parameter val_dmac0_s__FSRC = 32'h00000000; +parameter mask_dmac0_s__FSRC = 32'hFFFFFFFF; + +parameter dmac0_s__FTRD = 32'hF8003038; +parameter val_dmac0_s__FTRD = 32'h00000000; +parameter mask_dmac0_s__FTRD = 32'hFFFFFFFF; + +parameter dmac0_s__FTR0 = 32'hF8003040; +parameter val_dmac0_s__FTR0 = 32'h00000000; +parameter mask_dmac0_s__FTR0 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR1 = 32'hF8003044; +parameter val_dmac0_s__FTR1 = 32'h00000000; +parameter mask_dmac0_s__FTR1 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR2 = 32'hF8003048; +parameter val_dmac0_s__FTR2 = 32'h00000000; +parameter mask_dmac0_s__FTR2 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR3 = 32'hF800304C; +parameter val_dmac0_s__FTR3 = 32'h00000000; +parameter mask_dmac0_s__FTR3 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR4 = 32'hF8003050; +parameter val_dmac0_s__FTR4 = 32'h00000000; +parameter mask_dmac0_s__FTR4 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR5 = 32'hF8003054; +parameter val_dmac0_s__FTR5 = 32'h00000000; +parameter mask_dmac0_s__FTR5 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR6 = 32'hF8003058; +parameter val_dmac0_s__FTR6 = 32'h00000000; +parameter mask_dmac0_s__FTR6 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR7 = 32'hF800305C; +parameter val_dmac0_s__FTR7 = 32'h00000000; +parameter mask_dmac0_s__FTR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR0 = 32'hF8003100; +parameter val_dmac0_s__CSR0 = 32'h00000000; +parameter mask_dmac0_s__CSR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC0 = 32'hF8003104; +parameter val_dmac0_s__CPC0 = 32'h00000000; +parameter mask_dmac0_s__CPC0 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR1 = 32'hF8003108; +parameter val_dmac0_s__CSR1 = 32'h00000000; +parameter mask_dmac0_s__CSR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC1 = 32'hF800310C; +parameter val_dmac0_s__CPC1 = 32'h00000000; +parameter mask_dmac0_s__CPC1 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR2 = 32'hF8003110; +parameter val_dmac0_s__CSR2 = 32'h00000000; +parameter mask_dmac0_s__CSR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC2 = 32'hF8003114; +parameter val_dmac0_s__CPC2 = 32'h00000000; +parameter mask_dmac0_s__CPC2 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR3 = 32'hF8003118; +parameter val_dmac0_s__CSR3 = 32'h00000000; +parameter mask_dmac0_s__CSR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC3 = 32'hF800311C; +parameter val_dmac0_s__CPC3 = 32'h00000000; +parameter mask_dmac0_s__CPC3 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR4 = 32'hF8003120; +parameter val_dmac0_s__CSR4 = 32'h00000000; +parameter mask_dmac0_s__CSR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC4 = 32'hF8003124; +parameter val_dmac0_s__CPC4 = 32'h00000000; +parameter mask_dmac0_s__CPC4 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR5 = 32'hF8003128; +parameter val_dmac0_s__CSR5 = 32'h00000000; +parameter mask_dmac0_s__CSR5 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC5 = 32'hF800312C; +parameter val_dmac0_s__CPC5 = 32'h00000000; +parameter mask_dmac0_s__CPC5 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR6 = 32'hF8003130; +parameter val_dmac0_s__CSR6 = 32'h00000000; +parameter mask_dmac0_s__CSR6 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC6 = 32'hF8003134; +parameter val_dmac0_s__CPC6 = 32'h00000000; +parameter mask_dmac0_s__CPC6 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR7 = 32'hF8003138; +parameter val_dmac0_s__CSR7 = 32'h00000000; +parameter mask_dmac0_s__CSR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC7 = 32'hF800313C; +parameter val_dmac0_s__CPC7 = 32'h00000000; +parameter mask_dmac0_s__CPC7 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR0 = 32'hF8003400; +parameter val_dmac0_s__SAR0 = 32'h00000000; +parameter mask_dmac0_s__SAR0 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR0 = 32'hF8003404; +parameter val_dmac0_s__DAR0 = 32'h00000000; +parameter mask_dmac0_s__DAR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR0 = 32'hF8003408; +parameter val_dmac0_s__CCR0 = 32'h00800200; +parameter mask_dmac0_s__CCR0 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_0 = 32'hF800340C; +parameter val_dmac0_s__LC0_0 = 32'h00000000; +parameter mask_dmac0_s__LC0_0 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_0 = 32'hF8003410; +parameter val_dmac0_s__LC1_0 = 32'h00000000; +parameter mask_dmac0_s__LC1_0 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR1 = 32'hF8003420; +parameter val_dmac0_s__SAR1 = 32'h00000000; +parameter mask_dmac0_s__SAR1 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR1 = 32'hF8003424; +parameter val_dmac0_s__DAR1 = 32'h00000000; +parameter mask_dmac0_s__DAR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR1 = 32'hF8003428; +parameter val_dmac0_s__CCR1 = 32'h00800200; +parameter mask_dmac0_s__CCR1 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_1 = 32'hF800342C; +parameter val_dmac0_s__LC0_1 = 32'h00000000; +parameter mask_dmac0_s__LC0_1 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_1 = 32'hF8003430; +parameter val_dmac0_s__LC1_1 = 32'h00000000; +parameter mask_dmac0_s__LC1_1 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR2 = 32'hF8003440; +parameter val_dmac0_s__SAR2 = 32'h00000000; +parameter mask_dmac0_s__SAR2 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR2 = 32'hF8003444; +parameter val_dmac0_s__DAR2 = 32'h00000000; +parameter mask_dmac0_s__DAR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR2 = 32'hF8003448; +parameter val_dmac0_s__CCR2 = 32'h00800200; +parameter mask_dmac0_s__CCR2 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_2 = 32'hF800344C; +parameter val_dmac0_s__LC0_2 = 32'h00000000; +parameter mask_dmac0_s__LC0_2 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_2 = 32'hF8003450; +parameter val_dmac0_s__LC1_2 = 32'h00000000; +parameter mask_dmac0_s__LC1_2 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR3 = 32'hF8003460; +parameter val_dmac0_s__SAR3 = 32'h00000000; +parameter mask_dmac0_s__SAR3 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR3 = 32'hF8003464; +parameter val_dmac0_s__DAR3 = 32'h00000000; +parameter mask_dmac0_s__DAR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR3 = 32'hF8003468; +parameter val_dmac0_s__CCR3 = 32'h00800200; +parameter mask_dmac0_s__CCR3 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_3 = 32'hF800346C; +parameter val_dmac0_s__LC0_3 = 32'h00000000; +parameter mask_dmac0_s__LC0_3 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_3 = 32'hF8003470; +parameter val_dmac0_s__LC1_3 = 32'h00000000; +parameter mask_dmac0_s__LC1_3 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR4 = 32'hF8003480; +parameter val_dmac0_s__SAR4 = 32'h00000000; +parameter mask_dmac0_s__SAR4 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR4 = 32'hF8003484; +parameter val_dmac0_s__DAR4 = 32'h00000000; +parameter mask_dmac0_s__DAR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR4 = 32'hF8003488; +parameter val_dmac0_s__CCR4 = 32'h00800200; +parameter mask_dmac0_s__CCR4 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_4 = 32'hF800348C; +parameter val_dmac0_s__LC0_4 = 32'h00000000; +parameter mask_dmac0_s__LC0_4 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_4 = 32'hF8003490; +parameter val_dmac0_s__LC1_4 = 32'h00000000; +parameter mask_dmac0_s__LC1_4 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR5 = 32'hF80034A0; +parameter val_dmac0_s__SAR5 = 32'h00000000; +parameter mask_dmac0_s__SAR5 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR5 = 32'hF80034A4; +parameter val_dmac0_s__DAR5 = 32'h00000000; +parameter mask_dmac0_s__DAR5 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR5 = 32'hF80034A8; +parameter val_dmac0_s__CCR5 = 32'h00800200; +parameter mask_dmac0_s__CCR5 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_5 = 32'hF80034AC; +parameter val_dmac0_s__LC0_5 = 32'h00000000; +parameter mask_dmac0_s__LC0_5 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_5 = 32'hF80034B0; +parameter val_dmac0_s__LC1_5 = 32'h00000000; +parameter mask_dmac0_s__LC1_5 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR6 = 32'hF80034C0; +parameter val_dmac0_s__SAR6 = 32'h00000000; +parameter mask_dmac0_s__SAR6 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR6 = 32'hF80034C4; +parameter val_dmac0_s__DAR6 = 32'h00000000; +parameter mask_dmac0_s__DAR6 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR6 = 32'hF80034C8; +parameter val_dmac0_s__CCR6 = 32'h00800200; +parameter mask_dmac0_s__CCR6 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_6 = 32'hF80034CC; +parameter val_dmac0_s__LC0_6 = 32'h00000000; +parameter mask_dmac0_s__LC0_6 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_6 = 32'hF80034D0; +parameter val_dmac0_s__LC1_6 = 32'h00000000; +parameter mask_dmac0_s__LC1_6 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR7 = 32'hF80034E0; +parameter val_dmac0_s__SAR7 = 32'h00000000; +parameter mask_dmac0_s__SAR7 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR7 = 32'hF80034E4; +parameter val_dmac0_s__DAR7 = 32'h00000000; +parameter mask_dmac0_s__DAR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR7 = 32'hF80034E8; +parameter val_dmac0_s__CCR7 = 32'h00800200; +parameter mask_dmac0_s__CCR7 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_7 = 32'hF80034EC; +parameter val_dmac0_s__LC0_7 = 32'h00000000; +parameter mask_dmac0_s__LC0_7 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_7 = 32'hF80034F0; +parameter val_dmac0_s__LC1_7 = 32'h00000000; +parameter mask_dmac0_s__LC1_7 = 32'hFFFFFFFF; + +parameter dmac0_s__DBGSTATUS = 32'hF8003D00; +parameter val_dmac0_s__DBGSTATUS = 32'h00000000; +parameter mask_dmac0_s__DBGSTATUS = 32'hFFFFFFFF; + +parameter dmac0_s__DBGCMD = 32'hF8003D04; +parameter val_dmac0_s__DBGCMD = 32'h00000000; +parameter mask_dmac0_s__DBGCMD = 32'hFFFFFFFF; + +parameter dmac0_s__DBGINST0 = 32'hF8003D08; +parameter val_dmac0_s__DBGINST0 = 32'h00000000; +parameter mask_dmac0_s__DBGINST0 = 32'hFFFFFFFF; + +parameter dmac0_s__DBGINST1 = 32'hF8003D0C; +parameter val_dmac0_s__DBGINST1 = 32'h00000000; +parameter mask_dmac0_s__DBGINST1 = 32'hFFFFFFFF; + +parameter dmac0_s__CR0 = 32'hF8003E00; +parameter val_dmac0_s__CR0 = 32'h001E3071; +parameter mask_dmac0_s__CR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CR1 = 32'hF8003E04; +parameter val_dmac0_s__CR1 = 32'h00000074; +parameter mask_dmac0_s__CR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CR2 = 32'hF8003E08; +parameter val_dmac0_s__CR2 = 32'h00000000; +parameter mask_dmac0_s__CR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CR3 = 32'hF8003E0C; +parameter val_dmac0_s__CR3 = 32'h00000000; +parameter mask_dmac0_s__CR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CR4 = 32'hF8003E10; +parameter val_dmac0_s__CR4 = 32'h00000000; +parameter mask_dmac0_s__CR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CRD = 32'hF8003E14; +parameter val_dmac0_s__CRD = 32'h07FF7F73; +parameter mask_dmac0_s__CRD = 32'hFFFFFFFF; + +parameter dmac0_s__WD = 32'hF8003E80; +parameter val_dmac0_s__WD = 32'h00000000; +parameter mask_dmac0_s__WD = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_0 = 32'hF8003FE0; +parameter val_dmac0_s__periph_id_0 = 32'h00000030; +parameter mask_dmac0_s__periph_id_0 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_1 = 32'hF8003FE4; +parameter val_dmac0_s__periph_id_1 = 32'h00000013; +parameter mask_dmac0_s__periph_id_1 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_2 = 32'hF8003FE8; +parameter val_dmac0_s__periph_id_2 = 32'h00000024; +parameter mask_dmac0_s__periph_id_2 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_3 = 32'hF8003FEC; +parameter val_dmac0_s__periph_id_3 = 32'h00000000; +parameter mask_dmac0_s__periph_id_3 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_0 = 32'hF8003FF0; +parameter val_dmac0_s__pcell_id_0 = 32'h0000000D; +parameter mask_dmac0_s__pcell_id_0 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_1 = 32'hF8003FF4; +parameter val_dmac0_s__pcell_id_1 = 32'h000000F0; +parameter mask_dmac0_s__pcell_id_1 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_2 = 32'hF8003FF8; +parameter val_dmac0_s__pcell_id_2 = 32'h00000005; +parameter mask_dmac0_s__pcell_id_2 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_3 = 32'hF8003FFC; +parameter val_dmac0_s__pcell_id_3 = 32'h000000B1; +parameter mask_dmac0_s__pcell_id_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module efuse_ctrl efuse_ctrl +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter efuse_ctrl__WR_LOCK = 32'hF800D000; +parameter val_efuse_ctrl__WR_LOCK = 32'h00000000; +parameter mask_efuse_ctrl__WR_LOCK = 32'hFFFFFFFF; + +parameter efuse_ctrl__WR_UNLOCK = 32'hF800D004; +parameter val_efuse_ctrl__WR_UNLOCK = 32'h00000000; +parameter mask_efuse_ctrl__WR_UNLOCK = 32'hFFFFFFFF; + +parameter efuse_ctrl__WR_LOCKSTA = 32'hF800D008; +parameter val_efuse_ctrl__WR_LOCKSTA = 32'h00000001; +parameter mask_efuse_ctrl__WR_LOCKSTA = 32'hFFFFFFFF; + +parameter efuse_ctrl__CFG = 32'hF800D00C; +parameter val_efuse_ctrl__CFG = 32'h00010F00; +parameter mask_efuse_ctrl__CFG = 32'hFFFFFFFF; + +parameter efuse_ctrl__STATUS = 32'hF800D010; +parameter val_efuse_ctrl__STATUS = 32'h00100000; +parameter mask_efuse_ctrl__STATUS = 32'hFFFFFFFF; + +parameter efuse_ctrl__CONTROL = 32'hF800D014; +parameter val_efuse_ctrl__CONTROL = 32'h00000003; +parameter mask_efuse_ctrl__CONTROL = 32'hFFFFFFFF; + +parameter efuse_ctrl__PGM_STBW = 32'hF800D018; +parameter val_efuse_ctrl__PGM_STBW = 32'h000002D0; +parameter mask_efuse_ctrl__PGM_STBW = 32'hFFFFFFFF; + +parameter efuse_ctrl__RD_STBW = 32'hF800D01C; +parameter val_efuse_ctrl__RD_STBW = 32'h0000000B; +parameter mask_efuse_ctrl__RD_STBW = 32'hFFFFFFFF; + + +// ************************************************************ +// Module gem0 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gem0__net_ctrl = 32'hE000B000; +parameter val_gem0__net_ctrl = 32'h00000000; +parameter mask_gem0__net_ctrl = 32'hFFFFFFFF; + +parameter gem0__net_cfg = 32'hE000B004; +parameter val_gem0__net_cfg = 32'h00080000; +parameter mask_gem0__net_cfg = 32'hFFFFFFFF; + +parameter gem0__net_status = 32'hE000B008; +parameter val_gem0__net_status = 32'h00000004; +parameter mask_gem0__net_status = 32'hFFFFFFFD; + +parameter gem0__user_io = 32'hE000B00C; +parameter val_gem0__user_io = 32'h00000000; +parameter mask_gem0__user_io = 32'h0000FFFF; + +parameter gem0__dma_cfg = 32'hE000B010; +parameter val_gem0__dma_cfg = 32'h00020784; +parameter mask_gem0__dma_cfg = 32'hFFFFFFFF; + +parameter gem0__tx_status = 32'hE000B014; +parameter val_gem0__tx_status = 32'h00000000; +parameter mask_gem0__tx_status = 32'hFFFFFFFF; + +parameter gem0__rx_qbar = 32'hE000B018; +parameter val_gem0__rx_qbar = 32'h00000000; +parameter mask_gem0__rx_qbar = 32'hFFFFFFFF; + +parameter gem0__tx_qbar = 32'hE000B01C; +parameter val_gem0__tx_qbar = 32'h00000000; +parameter mask_gem0__tx_qbar = 32'hFFFFFFFF; + +parameter gem0__rx_status = 32'hE000B020; +parameter val_gem0__rx_status = 32'h00000000; +parameter mask_gem0__rx_status = 32'hFFFFFFFF; + +parameter gem0__intr_status = 32'hE000B024; +parameter val_gem0__intr_status = 32'h00000000; +parameter mask_gem0__intr_status = 32'hFFFFFFFF; + +parameter gem0__intr_en = 32'hE000B028; +parameter val_gem0__intr_en = 32'h00000000; +parameter mask_gem0__intr_en = 32'h00000000; + +parameter gem0__intr_dis = 32'hE000B02C; +parameter val_gem0__intr_dis = 32'h00000000; +parameter mask_gem0__intr_dis = 32'h00000000; + +parameter gem0__intr_mask = 32'hE000B030; +parameter val_gem0__intr_mask = 32'h0001FFFF; +parameter mask_gem0__intr_mask = 32'hFC01FFFF; + +parameter gem0__phy_maint = 32'hE000B034; +parameter val_gem0__phy_maint = 32'h00000000; +parameter mask_gem0__phy_maint = 32'hFFFFFFFF; + +parameter gem0__rx_pauseq = 32'hE000B038; +parameter val_gem0__rx_pauseq = 32'h00000000; +parameter mask_gem0__rx_pauseq = 32'hFFFFFFFF; + +parameter gem0__tx_pauseq = 32'hE000B03C; +parameter val_gem0__tx_pauseq = 32'h0000FFFF; +parameter mask_gem0__tx_pauseq = 32'hFFFFFFFF; + +parameter gem0__tx_partial_st_fwd = 32'hE000B040; +parameter val_gem0__tx_partial_st_fwd = 32'h000003FF; +parameter mask_gem0__tx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem0__rx_partial_st_fwd = 32'hE000B044; +parameter val_gem0__rx_partial_st_fwd = 32'h000003FF; +parameter mask_gem0__rx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem0__hash_bot = 32'hE000B080; +parameter val_gem0__hash_bot = 32'h00000000; +parameter mask_gem0__hash_bot = 32'hFFFFFFFF; + +parameter gem0__hash_top = 32'hE000B084; +parameter val_gem0__hash_top = 32'h00000000; +parameter mask_gem0__hash_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_bot = 32'hE000B088; +parameter val_gem0__spec_addr1_bot = 32'h00000000; +parameter mask_gem0__spec_addr1_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_top = 32'hE000B08C; +parameter val_gem0__spec_addr1_top = 32'h00000000; +parameter mask_gem0__spec_addr1_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr2_bot = 32'hE000B090; +parameter val_gem0__spec_addr2_bot = 32'h00000000; +parameter mask_gem0__spec_addr2_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr2_top = 32'hE000B094; +parameter val_gem0__spec_addr2_top = 32'h00000000; +parameter mask_gem0__spec_addr2_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr3_bot = 32'hE000B098; +parameter val_gem0__spec_addr3_bot = 32'h00000000; +parameter mask_gem0__spec_addr3_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr3_top = 32'hE000B09C; +parameter val_gem0__spec_addr3_top = 32'h00000000; +parameter mask_gem0__spec_addr3_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr4_bot = 32'hE000B0A0; +parameter val_gem0__spec_addr4_bot = 32'h00000000; +parameter mask_gem0__spec_addr4_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr4_top = 32'hE000B0A4; +parameter val_gem0__spec_addr4_top = 32'h00000000; +parameter mask_gem0__spec_addr4_top = 32'hFFFFFFFF; + +parameter gem0__type_id_match1 = 32'hE000B0A8; +parameter val_gem0__type_id_match1 = 32'h00000000; +parameter mask_gem0__type_id_match1 = 32'hFFFFFFFF; + +parameter gem0__type_id_match2 = 32'hE000B0AC; +parameter val_gem0__type_id_match2 = 32'h00000000; +parameter mask_gem0__type_id_match2 = 32'hFFFFFFFF; + +parameter gem0__type_id_match3 = 32'hE000B0B0; +parameter val_gem0__type_id_match3 = 32'h00000000; +parameter mask_gem0__type_id_match3 = 32'hFFFFFFFF; + +parameter gem0__type_id_match4 = 32'hE000B0B4; +parameter val_gem0__type_id_match4 = 32'h00000000; +parameter mask_gem0__type_id_match4 = 32'hFFFFFFFF; + +parameter gem0__wake_on_lan = 32'hE000B0B8; +parameter val_gem0__wake_on_lan = 32'h00000000; +parameter mask_gem0__wake_on_lan = 32'hFFFFFFFF; + +parameter gem0__ipg_stretch = 32'hE000B0BC; +parameter val_gem0__ipg_stretch = 32'h00000000; +parameter mask_gem0__ipg_stretch = 32'hFFFFFFFF; + +parameter gem0__stacked_vlan = 32'hE000B0C0; +parameter val_gem0__stacked_vlan = 32'h00000000; +parameter mask_gem0__stacked_vlan = 32'hFFFFFFFF; + +parameter gem0__tx_pfc_pause = 32'hE000B0C4; +parameter val_gem0__tx_pfc_pause = 32'h00000000; +parameter mask_gem0__tx_pfc_pause = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_mask_bot = 32'hE000B0C8; +parameter val_gem0__spec_addr1_mask_bot = 32'h00000000; +parameter mask_gem0__spec_addr1_mask_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_mask_top = 32'hE000B0CC; +parameter val_gem0__spec_addr1_mask_top = 32'h00000000; +parameter mask_gem0__spec_addr1_mask_top = 32'hFFFFFFFF; + +parameter gem0__module_id = 32'hE000B0FC; +parameter val_gem0__module_id = 32'h00020118; +parameter mask_gem0__module_id = 32'hFFFFFFFF; + +parameter gem0__octets_tx_bot = 32'hE000B100; +parameter val_gem0__octets_tx_bot = 32'h00000000; +parameter mask_gem0__octets_tx_bot = 32'hFFFFFFFF; + +parameter gem0__octets_tx_top = 32'hE000B104; +parameter val_gem0__octets_tx_top = 32'h00000000; +parameter mask_gem0__octets_tx_top = 32'hFFFFFFFF; + +parameter gem0__frames_tx = 32'hE000B108; +parameter val_gem0__frames_tx = 32'h00000000; +parameter mask_gem0__frames_tx = 32'hFFFFFFFF; + +parameter gem0__broadcast_frames_tx = 32'hE000B10C; +parameter val_gem0__broadcast_frames_tx = 32'h00000000; +parameter mask_gem0__broadcast_frames_tx = 32'hFFFFFFFF; + +parameter gem0__multi_frames_tx = 32'hE000B110; +parameter val_gem0__multi_frames_tx = 32'h00000000; +parameter mask_gem0__multi_frames_tx = 32'hFFFFFFFF; + +parameter gem0__pause_frames_tx = 32'hE000B114; +parameter val_gem0__pause_frames_tx = 32'h00000000; +parameter mask_gem0__pause_frames_tx = 32'hFFFFFFFF; + +parameter gem0__frames_64b_tx = 32'hE000B118; +parameter val_gem0__frames_64b_tx = 32'h00000000; +parameter mask_gem0__frames_64b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_65to127b_tx = 32'hE000B11C; +parameter val_gem0__frames_65to127b_tx = 32'h00000000; +parameter mask_gem0__frames_65to127b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_128to255b_tx = 32'hE000B120; +parameter val_gem0__frames_128to255b_tx = 32'h00000000; +parameter mask_gem0__frames_128to255b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_256to511b_tx = 32'hE000B124; +parameter val_gem0__frames_256to511b_tx = 32'h00000000; +parameter mask_gem0__frames_256to511b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_512to1023b_tx = 32'hE000B128; +parameter val_gem0__frames_512to1023b_tx = 32'h00000000; +parameter mask_gem0__frames_512to1023b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_1024to1518b_tx = 32'hE000B12C; +parameter val_gem0__frames_1024to1518b_tx = 32'h00000000; +parameter mask_gem0__frames_1024to1518b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_gt1518b_tx = 32'hE000B130; +parameter val_gem0__frames_gt1518b_tx = 32'h00000000; +parameter mask_gem0__frames_gt1518b_tx = 32'hFFFFFFFF; + +parameter gem0__tx_under_runs = 32'hE000B134; +parameter val_gem0__tx_under_runs = 32'h00000000; +parameter mask_gem0__tx_under_runs = 32'hFFFFFFFF; + +parameter gem0__single_collisn_frames = 32'hE000B138; +parameter val_gem0__single_collisn_frames = 32'h00000000; +parameter mask_gem0__single_collisn_frames = 32'hFFFFFFFF; + +parameter gem0__multi_collisn_frames = 32'hE000B13C; +parameter val_gem0__multi_collisn_frames = 32'h00000000; +parameter mask_gem0__multi_collisn_frames = 32'hFFFFFFFF; + +parameter gem0__excessive_collisns = 32'hE000B140; +parameter val_gem0__excessive_collisns = 32'h00000000; +parameter mask_gem0__excessive_collisns = 32'hFFFFFFFF; + +parameter gem0__late_collisns = 32'hE000B144; +parameter val_gem0__late_collisns = 32'h00000000; +parameter mask_gem0__late_collisns = 32'hFFFFFFFF; + +parameter gem0__deferred_tx_frames = 32'hE000B148; +parameter val_gem0__deferred_tx_frames = 32'h00000000; +parameter mask_gem0__deferred_tx_frames = 32'hFFFFFFFF; + +parameter gem0__carrier_sense_errs = 32'hE000B14C; +parameter val_gem0__carrier_sense_errs = 32'h00000000; +parameter mask_gem0__carrier_sense_errs = 32'hFFFFFFFF; + +parameter gem0__octets_rx_bot = 32'hE000B150; +parameter val_gem0__octets_rx_bot = 32'h00000000; +parameter mask_gem0__octets_rx_bot = 32'hFFFFFFFF; + +parameter gem0__octets_rx_top = 32'hE000B154; +parameter val_gem0__octets_rx_top = 32'h00000000; +parameter mask_gem0__octets_rx_top = 32'hFFFFFFFF; + +parameter gem0__frames_rx = 32'hE000B158; +parameter val_gem0__frames_rx = 32'h00000000; +parameter mask_gem0__frames_rx = 32'hFFFFFFFF; + +parameter gem0__bdcast_fames_rx = 32'hE000B15C; +parameter val_gem0__bdcast_fames_rx = 32'h00000000; +parameter mask_gem0__bdcast_fames_rx = 32'hFFFFFFFF; + +parameter gem0__multi_frames_rx = 32'hE000B160; +parameter val_gem0__multi_frames_rx = 32'h00000000; +parameter mask_gem0__multi_frames_rx = 32'hFFFFFFFF; + +parameter gem0__pause_rx = 32'hE000B164; +parameter val_gem0__pause_rx = 32'h00000000; +parameter mask_gem0__pause_rx = 32'hFFFFFFFF; + +parameter gem0__frames_64b_rx = 32'hE000B168; +parameter val_gem0__frames_64b_rx = 32'h00000000; +parameter mask_gem0__frames_64b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_65to127b_rx = 32'hE000B16C; +parameter val_gem0__frames_65to127b_rx = 32'h00000000; +parameter mask_gem0__frames_65to127b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_128to255b_rx = 32'hE000B170; +parameter val_gem0__frames_128to255b_rx = 32'h00000000; +parameter mask_gem0__frames_128to255b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_256to511b_rx = 32'hE000B174; +parameter val_gem0__frames_256to511b_rx = 32'h00000000; +parameter mask_gem0__frames_256to511b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_512to1023b_rx = 32'hE000B178; +parameter val_gem0__frames_512to1023b_rx = 32'h00000000; +parameter mask_gem0__frames_512to1023b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_1024to1518b_rx = 32'hE000B17C; +parameter val_gem0__frames_1024to1518b_rx = 32'h00000000; +parameter mask_gem0__frames_1024to1518b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_gt1518b_rx = 32'hE000B180; +parameter val_gem0__frames_gt1518b_rx = 32'h00000000; +parameter mask_gem0__frames_gt1518b_rx = 32'hFFFFFFFF; + +parameter gem0__undersz_rx = 32'hE000B184; +parameter val_gem0__undersz_rx = 32'h00000000; +parameter mask_gem0__undersz_rx = 32'hFFFFFFFF; + +parameter gem0__oversz_rx = 32'hE000B188; +parameter val_gem0__oversz_rx = 32'h00000000; +parameter mask_gem0__oversz_rx = 32'hFFFFFFFF; + +parameter gem0__jab_rx = 32'hE000B18C; +parameter val_gem0__jab_rx = 32'h00000000; +parameter mask_gem0__jab_rx = 32'hFFFFFFFF; + +parameter gem0__fcs_errors = 32'hE000B190; +parameter val_gem0__fcs_errors = 32'h00000000; +parameter mask_gem0__fcs_errors = 32'hFFFFFFFF; + +parameter gem0__length_field_errors = 32'hE000B194; +parameter val_gem0__length_field_errors = 32'h00000000; +parameter mask_gem0__length_field_errors = 32'hFFFFFFFF; + +parameter gem0__rx_symbol_errors = 32'hE000B198; +parameter val_gem0__rx_symbol_errors = 32'h00000000; +parameter mask_gem0__rx_symbol_errors = 32'hFFFFFFFF; + +parameter gem0__align_errors = 32'hE000B19C; +parameter val_gem0__align_errors = 32'h00000000; +parameter mask_gem0__align_errors = 32'hFFFFFFFF; + +parameter gem0__rx_resource_errors = 32'hE000B1A0; +parameter val_gem0__rx_resource_errors = 32'h00000000; +parameter mask_gem0__rx_resource_errors = 32'hFFFFFFFF; + +parameter gem0__rx_overrun_errors = 32'hE000B1A4; +parameter val_gem0__rx_overrun_errors = 32'h00000000; +parameter mask_gem0__rx_overrun_errors = 32'hFFFFFFFF; + +parameter gem0__ip_hdr_csum_errors = 32'hE000B1A8; +parameter val_gem0__ip_hdr_csum_errors = 32'h00000000; +parameter mask_gem0__ip_hdr_csum_errors = 32'hFFFFFFFF; + +parameter gem0__tcp_csum_errors = 32'hE000B1AC; +parameter val_gem0__tcp_csum_errors = 32'h00000000; +parameter mask_gem0__tcp_csum_errors = 32'hFFFFFFFF; + +parameter gem0__udp_csum_errors = 32'hE000B1B0; +parameter val_gem0__udp_csum_errors = 32'h00000000; +parameter mask_gem0__udp_csum_errors = 32'hFFFFFFFF; + +parameter gem0__timer_strobe_s = 32'hE000B1C8; +parameter val_gem0__timer_strobe_s = 32'h00000000; +parameter mask_gem0__timer_strobe_s = 32'hFFFFFFFF; + +parameter gem0__timer_strobe_ns = 32'hE000B1CC; +parameter val_gem0__timer_strobe_ns = 32'h00000000; +parameter mask_gem0__timer_strobe_ns = 32'hFFFFFFFF; + +parameter gem0__timer_s = 32'hE000B1D0; +parameter val_gem0__timer_s = 32'h00000000; +parameter mask_gem0__timer_s = 32'hFFFFFFFF; + +parameter gem0__timer_ns = 32'hE000B1D4; +parameter val_gem0__timer_ns = 32'h00000000; +parameter mask_gem0__timer_ns = 32'hFFFFFFFF; + +parameter gem0__timer_adjust = 32'hE000B1D8; +parameter val_gem0__timer_adjust = 32'h00000000; +parameter mask_gem0__timer_adjust = 32'hFFFFFFFF; + +parameter gem0__timer_incr = 32'hE000B1DC; +parameter val_gem0__timer_incr = 32'h00000000; +parameter mask_gem0__timer_incr = 32'hFFFFFFFF; + +parameter gem0__ptp_tx_s = 32'hE000B1E0; +parameter val_gem0__ptp_tx_s = 32'h00000000; +parameter mask_gem0__ptp_tx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_tx_ns = 32'hE000B1E4; +parameter val_gem0__ptp_tx_ns = 32'h00000000; +parameter mask_gem0__ptp_tx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_rx_s = 32'hE000B1E8; +parameter val_gem0__ptp_rx_s = 32'h00000000; +parameter mask_gem0__ptp_rx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_rx_ns = 32'hE000B1EC; +parameter val_gem0__ptp_rx_ns = 32'h00000000; +parameter mask_gem0__ptp_rx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_tx_s = 32'hE000B1F0; +parameter val_gem0__ptp_peer_tx_s = 32'h00000000; +parameter mask_gem0__ptp_peer_tx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_tx_ns = 32'hE000B1F4; +parameter val_gem0__ptp_peer_tx_ns = 32'h00000000; +parameter mask_gem0__ptp_peer_tx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_rx_s = 32'hE000B1F8; +parameter val_gem0__ptp_peer_rx_s = 32'h00000000; +parameter mask_gem0__ptp_peer_rx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_rx_ns = 32'hE000B1FC; +parameter val_gem0__ptp_peer_rx_ns = 32'h00000000; +parameter mask_gem0__ptp_peer_rx_ns = 32'hFFFFFFFF; + +parameter gem0__pcs_ctrl = 32'hE000B200; +parameter val_gem0__pcs_ctrl = 32'h00000000; +parameter mask_gem0__pcs_ctrl = 32'h00000000; + +parameter gem0__pcs_status = 32'hE000B204; +parameter val_gem0__pcs_status = 32'h00000000; +parameter mask_gem0__pcs_status = 32'h00000000; + +parameter gem0__pcs_upper_phy_id = 32'hE000B208; +parameter val_gem0__pcs_upper_phy_id = 32'h00000000; +parameter mask_gem0__pcs_upper_phy_id = 32'h00000000; + +parameter gem0__pcs_lower_phy_id = 32'hE000B20C; +parameter val_gem0__pcs_lower_phy_id = 32'h00000000; +parameter mask_gem0__pcs_lower_phy_id = 32'h00000000; + +parameter gem0__pcs_autoneg_ad = 32'hE000B210; +parameter val_gem0__pcs_autoneg_ad = 32'h00000000; +parameter mask_gem0__pcs_autoneg_ad = 32'h00000000; + +parameter gem0__pcs_autoneg_ability = 32'hE000B214; +parameter val_gem0__pcs_autoneg_ability = 32'h00000000; +parameter mask_gem0__pcs_autoneg_ability = 32'h00000000; + +parameter gem0__pcs_autonec_exp = 32'hE000B218; +parameter val_gem0__pcs_autonec_exp = 32'h00000000; +parameter mask_gem0__pcs_autonec_exp = 32'h00000000; + +parameter gem0__pcs_autoneg_next_pg = 32'hE000B21C; +parameter val_gem0__pcs_autoneg_next_pg = 32'h00000000; +parameter mask_gem0__pcs_autoneg_next_pg = 32'h00000000; + +parameter gem0__pcs_autoneg_pnext_pg = 32'hE000B220; +parameter val_gem0__pcs_autoneg_pnext_pg = 32'h00000000; +parameter mask_gem0__pcs_autoneg_pnext_pg = 32'h00000000; + +parameter gem0__pcs_extended_status = 32'hE000B23C; +parameter val_gem0__pcs_extended_status = 32'h00000000; +parameter mask_gem0__pcs_extended_status = 32'h00000000; + +parameter gem0__design_cfg1 = 32'hE000B280; +parameter val_gem0__design_cfg1 = 32'h02000000; +parameter mask_gem0__design_cfg1 = 32'h0E000000; + +parameter gem0__design_cfg2 = 32'hE000B284; +parameter val_gem0__design_cfg2 = 32'h2A813FFF; +parameter mask_gem0__design_cfg2 = 32'h3FCFFFFF; + +parameter gem0__design_cfg3 = 32'hE000B288; +parameter val_gem0__design_cfg3 = 32'h00000000; +parameter mask_gem0__design_cfg3 = 32'hFFFFFFFF; + +parameter gem0__design_cfg4 = 32'hE000B28C; +parameter val_gem0__design_cfg4 = 32'h00000000; +parameter mask_gem0__design_cfg4 = 32'hFFFFFFFF; + +parameter gem0__design_cfg5 = 32'hE000B290; +parameter val_gem0__design_cfg5 = 32'h002F2045; +parameter mask_gem0__design_cfg5 = 32'h0FFFFCFF; + +parameter gem0__design_cfg6 = 32'hE000B294; +parameter val_gem0__design_cfg6 = 32'h00000000; +parameter mask_gem0__design_cfg6 = 32'h00000000; + +parameter gem0__design_cfg7 = 32'hE000B298; +parameter val_gem0__design_cfg7 = 32'h00000000; +parameter mask_gem0__design_cfg7 = 32'h00000000; + +parameter gem0__isr_pq1 = 32'hE000B400; +parameter val_gem0__isr_pq1 = 32'h00000000; +parameter mask_gem0__isr_pq1 = 32'h00000000; + +parameter gem0__isr_pq2 = 32'hE000B404; +parameter val_gem0__isr_pq2 = 32'h00000000; +parameter mask_gem0__isr_pq2 = 32'h00000000; + +parameter gem0__isr_pq3 = 32'hE000B408; +parameter val_gem0__isr_pq3 = 32'h00000000; +parameter mask_gem0__isr_pq3 = 32'h00000000; + +parameter gem0__isr_pq4 = 32'hE000B40C; +parameter val_gem0__isr_pq4 = 32'h00000000; +parameter mask_gem0__isr_pq4 = 32'h00000000; + +parameter gem0__isr_pq5 = 32'hE000B410; +parameter val_gem0__isr_pq5 = 32'h00000000; +parameter mask_gem0__isr_pq5 = 32'h00000000; + +parameter gem0__isr_pq6 = 32'hE000B414; +parameter val_gem0__isr_pq6 = 32'h00000000; +parameter mask_gem0__isr_pq6 = 32'h00000000; + +parameter gem0__isr_pq7 = 32'hE000B418; +parameter val_gem0__isr_pq7 = 32'h00000000; +parameter mask_gem0__isr_pq7 = 32'h00000000; + +parameter gem0__tx_qbar_q1 = 32'hE000B440; +parameter val_gem0__tx_qbar_q1 = 32'h00000000; +parameter mask_gem0__tx_qbar_q1 = 32'h00000000; + +parameter gem0__tx_qbar_q2 = 32'hE000B444; +parameter val_gem0__tx_qbar_q2 = 32'h00000000; +parameter mask_gem0__tx_qbar_q2 = 32'h00000000; + +parameter gem0__tx_qbar_q3 = 32'hE000B448; +parameter val_gem0__tx_qbar_q3 = 32'h00000000; +parameter mask_gem0__tx_qbar_q3 = 32'h00000000; + +parameter gem0__tx_qbar_q4 = 32'hE000B44C; +parameter val_gem0__tx_qbar_q4 = 32'h00000000; +parameter mask_gem0__tx_qbar_q4 = 32'h00000000; + +parameter gem0__tx_qbar_q5 = 32'hE000B450; +parameter val_gem0__tx_qbar_q5 = 32'h00000000; +parameter mask_gem0__tx_qbar_q5 = 32'h00000000; + +parameter gem0__tx_qbar_q6 = 32'hE000B454; +parameter val_gem0__tx_qbar_q6 = 32'h00000000; +parameter mask_gem0__tx_qbar_q6 = 32'h00000000; + +parameter gem0__tx_qbar_q7 = 32'hE000B458; +parameter val_gem0__tx_qbar_q7 = 32'h00000000; +parameter mask_gem0__tx_qbar_q7 = 32'h00000000; + +parameter gem0__rx_qbar_q1 = 32'hE000B480; +parameter val_gem0__rx_qbar_q1 = 32'h00000000; +parameter mask_gem0__rx_qbar_q1 = 32'h00000000; + +parameter gem0__rx_qbar_q2 = 32'hE000B484; +parameter val_gem0__rx_qbar_q2 = 32'h00000000; +parameter mask_gem0__rx_qbar_q2 = 32'h00000000; + +parameter gem0__rx_qbar_q3 = 32'hE000B488; +parameter val_gem0__rx_qbar_q3 = 32'h00000000; +parameter mask_gem0__rx_qbar_q3 = 32'h00000000; + +parameter gem0__rx_qbar_q4 = 32'hE000B48C; +parameter val_gem0__rx_qbar_q4 = 32'h00000000; +parameter mask_gem0__rx_qbar_q4 = 32'h00000000; + +parameter gem0__rx_qbar_q5 = 32'hE000B490; +parameter val_gem0__rx_qbar_q5 = 32'h00000000; +parameter mask_gem0__rx_qbar_q5 = 32'h00000000; + +parameter gem0__rx_qbar_q6 = 32'hE000B494; +parameter val_gem0__rx_qbar_q6 = 32'h00000000; +parameter mask_gem0__rx_qbar_q6 = 32'h00000000; + +parameter gem0__rx_qbar_q7 = 32'hE000B498; +parameter val_gem0__rx_qbar_q7 = 32'h00000000; +parameter mask_gem0__rx_qbar_q7 = 32'h00000000; + +parameter gem0__rx_bufsz_q1 = 32'hE000B4A0; +parameter val_gem0__rx_bufsz_q1 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q1 = 32'h00000000; + +parameter gem0__rx_bufsz_q2 = 32'hE000B4A4; +parameter val_gem0__rx_bufsz_q2 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q2 = 32'h00000000; + +parameter gem0__rx_bufsz_q3 = 32'hE000B4A8; +parameter val_gem0__rx_bufsz_q3 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q3 = 32'h00000000; + +parameter gem0__rx_bufsz_q4 = 32'hE000B4AC; +parameter val_gem0__rx_bufsz_q4 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q4 = 32'h00000000; + +parameter gem0__rx_bufsz_q5 = 32'hE000B4B0; +parameter val_gem0__rx_bufsz_q5 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q5 = 32'h00000000; + +parameter gem0__rx_bufsz_q6 = 32'hE000B4B4; +parameter val_gem0__rx_bufsz_q6 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q6 = 32'h00000000; + +parameter gem0__rx_bufsz_q7 = 32'hE000B4B8; +parameter val_gem0__rx_bufsz_q7 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q7 = 32'h00000000; + +parameter gem0__screen_t1_r0 = 32'hE000B500; +parameter val_gem0__screen_t1_r0 = 32'h00000000; +parameter mask_gem0__screen_t1_r0 = 32'h00000000; + +parameter gem0__screen_t1_r1 = 32'hE000B504; +parameter val_gem0__screen_t1_r1 = 32'h00000000; +parameter mask_gem0__screen_t1_r1 = 32'h00000000; + +parameter gem0__screen_t1_r2 = 32'hE000B508; +parameter val_gem0__screen_t1_r2 = 32'h00000000; +parameter mask_gem0__screen_t1_r2 = 32'h00000000; + +parameter gem0__screen_t1_r3 = 32'hE000B50C; +parameter val_gem0__screen_t1_r3 = 32'h00000000; +parameter mask_gem0__screen_t1_r3 = 32'h00000000; + +parameter gem0__screen_t1_r4 = 32'hE000B510; +parameter val_gem0__screen_t1_r4 = 32'h00000000; +parameter mask_gem0__screen_t1_r4 = 32'h00000000; + +parameter gem0__screen_t1_r5 = 32'hE000B514; +parameter val_gem0__screen_t1_r5 = 32'h00000000; +parameter mask_gem0__screen_t1_r5 = 32'h00000000; + +parameter gem0__screen_t1_r6 = 32'hE000B518; +parameter val_gem0__screen_t1_r6 = 32'h00000000; +parameter mask_gem0__screen_t1_r6 = 32'h00000000; + +parameter gem0__screen_t1_r7 = 32'hE000B51C; +parameter val_gem0__screen_t1_r7 = 32'h00000000; +parameter mask_gem0__screen_t1_r7 = 32'h00000000; + +parameter gem0__screen_t1_r8 = 32'hE000B520; +parameter val_gem0__screen_t1_r8 = 32'h00000000; +parameter mask_gem0__screen_t1_r8 = 32'h00000000; + +parameter gem0__screen_t1_r9 = 32'hE000B524; +parameter val_gem0__screen_t1_r9 = 32'h00000000; +parameter mask_gem0__screen_t1_r9 = 32'h00000000; + +parameter gem0__screen_t1_r10 = 32'hE000B528; +parameter val_gem0__screen_t1_r10 = 32'h00000000; +parameter mask_gem0__screen_t1_r10 = 32'h00000000; + +parameter gem0__screen_t1_r11 = 32'hE000B52C; +parameter val_gem0__screen_t1_r11 = 32'h00000000; +parameter mask_gem0__screen_t1_r11 = 32'h00000000; + +parameter gem0__screen_t1_r12 = 32'hE000B530; +parameter val_gem0__screen_t1_r12 = 32'h00000000; +parameter mask_gem0__screen_t1_r12 = 32'h00000000; + +parameter gem0__screen_t1_r13 = 32'hE000B534; +parameter val_gem0__screen_t1_r13 = 32'h00000000; +parameter mask_gem0__screen_t1_r13 = 32'h00000000; + +parameter gem0__screen_t1_r14 = 32'hE000B538; +parameter val_gem0__screen_t1_r14 = 32'h00000000; +parameter mask_gem0__screen_t1_r14 = 32'h00000000; + +parameter gem0__screen_t1_r15 = 32'hE000B53C; +parameter val_gem0__screen_t1_r15 = 32'h00000000; +parameter mask_gem0__screen_t1_r15 = 32'h00000000; + +parameter gem0__screen_t2_r0 = 32'hE000B540; +parameter val_gem0__screen_t2_r0 = 32'h00000000; +parameter mask_gem0__screen_t2_r0 = 32'h00000000; + +parameter gem0__screen_t2_r1 = 32'hE000B544; +parameter val_gem0__screen_t2_r1 = 32'h00000000; +parameter mask_gem0__screen_t2_r1 = 32'h00000000; + +parameter gem0__screen_t2_r2 = 32'hE000B548; +parameter val_gem0__screen_t2_r2 = 32'h00000000; +parameter mask_gem0__screen_t2_r2 = 32'h00000000; + +parameter gem0__screen_t2_r3 = 32'hE000B54C; +parameter val_gem0__screen_t2_r3 = 32'h00000000; +parameter mask_gem0__screen_t2_r3 = 32'h00000000; + +parameter gem0__screen_t2_r4 = 32'hE000B550; +parameter val_gem0__screen_t2_r4 = 32'h00000000; +parameter mask_gem0__screen_t2_r4 = 32'h00000000; + +parameter gem0__screen_t2_r5 = 32'hE000B554; +parameter val_gem0__screen_t2_r5 = 32'h00000000; +parameter mask_gem0__screen_t2_r5 = 32'h00000000; + +parameter gem0__screen_t2_r6 = 32'hE000B558; +parameter val_gem0__screen_t2_r6 = 32'h00000000; +parameter mask_gem0__screen_t2_r6 = 32'h00000000; + +parameter gem0__screen_t2_r7 = 32'hE000B55C; +parameter val_gem0__screen_t2_r7 = 32'h00000000; +parameter mask_gem0__screen_t2_r7 = 32'h00000000; + +parameter gem0__screen_t2_r8 = 32'hE000B560; +parameter val_gem0__screen_t2_r8 = 32'h00000000; +parameter mask_gem0__screen_t2_r8 = 32'h00000000; + +parameter gem0__screen_t2_r9 = 32'hE000B564; +parameter val_gem0__screen_t2_r9 = 32'h00000000; +parameter mask_gem0__screen_t2_r9 = 32'h00000000; + +parameter gem0__screen_t2_r10 = 32'hE000B568; +parameter val_gem0__screen_t2_r10 = 32'h00000000; +parameter mask_gem0__screen_t2_r10 = 32'h00000000; + +parameter gem0__screen_t2_r11 = 32'hE000B56C; +parameter val_gem0__screen_t2_r11 = 32'h00000000; +parameter mask_gem0__screen_t2_r11 = 32'h00000000; + +parameter gem0__screen_t2_r12 = 32'hE000B570; +parameter val_gem0__screen_t2_r12 = 32'h00000000; +parameter mask_gem0__screen_t2_r12 = 32'h00000000; + +parameter gem0__screen_t2_r13 = 32'hE000B574; +parameter val_gem0__screen_t2_r13 = 32'h00000000; +parameter mask_gem0__screen_t2_r13 = 32'h00000000; + +parameter gem0__screen_t2_r14 = 32'hE000B578; +parameter val_gem0__screen_t2_r14 = 32'h00000000; +parameter mask_gem0__screen_t2_r14 = 32'h00000000; + +parameter gem0__screen_t2_r15 = 32'hE000B57C; +parameter val_gem0__screen_t2_r15 = 32'h00000000; +parameter mask_gem0__screen_t2_r15 = 32'h00000000; + +parameter gem0__intr_en_pq1 = 32'hE000B600; +parameter val_gem0__intr_en_pq1 = 32'h00000000; +parameter mask_gem0__intr_en_pq1 = 32'h00000000; + +parameter gem0__intr_en_pq2 = 32'hE000B604; +parameter val_gem0__intr_en_pq2 = 32'h00000000; +parameter mask_gem0__intr_en_pq2 = 32'h00000000; + +parameter gem0__intr_en_pq3 = 32'hE000B608; +parameter val_gem0__intr_en_pq3 = 32'h00000000; +parameter mask_gem0__intr_en_pq3 = 32'h00000000; + +parameter gem0__intr_en_pq4 = 32'hE000B60C; +parameter val_gem0__intr_en_pq4 = 32'h00000000; +parameter mask_gem0__intr_en_pq4 = 32'h00000000; + +parameter gem0__intr_en_pq5 = 32'hE000B610; +parameter val_gem0__intr_en_pq5 = 32'h00000000; +parameter mask_gem0__intr_en_pq5 = 32'h00000000; + +parameter gem0__intr_en_pq6 = 32'hE000B614; +parameter val_gem0__intr_en_pq6 = 32'h00000000; +parameter mask_gem0__intr_en_pq6 = 32'h00000000; + +parameter gem0__intr_en_pq7 = 32'hE000B618; +parameter val_gem0__intr_en_pq7 = 32'h00000000; +parameter mask_gem0__intr_en_pq7 = 32'h00000000; + +parameter gem0__intr_dis_pq1 = 32'hE000B620; +parameter val_gem0__intr_dis_pq1 = 32'h00000000; +parameter mask_gem0__intr_dis_pq1 = 32'h00000000; + +parameter gem0__intr_dis_pq2 = 32'hE000B624; +parameter val_gem0__intr_dis_pq2 = 32'h00000000; +parameter mask_gem0__intr_dis_pq2 = 32'h00000000; + +parameter gem0__intr_dis_pq3 = 32'hE000B628; +parameter val_gem0__intr_dis_pq3 = 32'h00000000; +parameter mask_gem0__intr_dis_pq3 = 32'h00000000; + +parameter gem0__intr_dis_pq4 = 32'hE000B62C; +parameter val_gem0__intr_dis_pq4 = 32'h00000000; +parameter mask_gem0__intr_dis_pq4 = 32'h00000000; + +parameter gem0__intr_dis_pq5 = 32'hE000B630; +parameter val_gem0__intr_dis_pq5 = 32'h00000000; +parameter mask_gem0__intr_dis_pq5 = 32'h00000000; + +parameter gem0__intr_dis_pq6 = 32'hE000B634; +parameter val_gem0__intr_dis_pq6 = 32'h00000000; +parameter mask_gem0__intr_dis_pq6 = 32'h00000000; + +parameter gem0__intr_dis_pq7 = 32'hE000B638; +parameter val_gem0__intr_dis_pq7 = 32'h00000000; +parameter mask_gem0__intr_dis_pq7 = 32'h00000000; + +parameter gem0__intr_mask_pq1 = 32'hE000B640; +parameter val_gem0__intr_mask_pq1 = 32'h00000000; +parameter mask_gem0__intr_mask_pq1 = 32'h00000000; + +parameter gem0__intr_mask_pq2 = 32'hE000B644; +parameter val_gem0__intr_mask_pq2 = 32'h00000000; +parameter mask_gem0__intr_mask_pq2 = 32'h00000000; + +parameter gem0__intr_mask_pq3 = 32'hE000B648; +parameter val_gem0__intr_mask_pq3 = 32'h00000000; +parameter mask_gem0__intr_mask_pq3 = 32'h00000000; + +parameter gem0__intr_mask_pq4 = 32'hE000B64C; +parameter val_gem0__intr_mask_pq4 = 32'h00000000; +parameter mask_gem0__intr_mask_pq4 = 32'h00000000; + +parameter gem0__intr_mask_pq5 = 32'hE000B650; +parameter val_gem0__intr_mask_pq5 = 32'h00000000; +parameter mask_gem0__intr_mask_pq5 = 32'h00000000; + +parameter gem0__intr_mask_pq6 = 32'hE000B654; +parameter val_gem0__intr_mask_pq6 = 32'h00000000; +parameter mask_gem0__intr_mask_pq6 = 32'h00000000; + +parameter gem0__intr_mask_pq7 = 32'hE000B658; +parameter val_gem0__intr_mask_pq7 = 32'h00000000; +parameter mask_gem0__intr_mask_pq7 = 32'h00000000; + + +// ************************************************************ +// Module gem1 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gem1__net_ctrl = 32'hE000C000; +parameter val_gem1__net_ctrl = 32'h00000000; +parameter mask_gem1__net_ctrl = 32'hFFFFFFFF; + +parameter gem1__net_cfg = 32'hE000C004; +parameter val_gem1__net_cfg = 32'h00080000; +parameter mask_gem1__net_cfg = 32'hFFFFFFFF; + +parameter gem1__net_status = 32'hE000C008; +parameter val_gem1__net_status = 32'h00000004; +parameter mask_gem1__net_status = 32'hFFFFFFFD; + +parameter gem1__user_io = 32'hE000C00C; +parameter val_gem1__user_io = 32'h00000000; +parameter mask_gem1__user_io = 32'h0000FFFF; + +parameter gem1__dma_cfg = 32'hE000C010; +parameter val_gem1__dma_cfg = 32'h00020784; +parameter mask_gem1__dma_cfg = 32'hFFFFFFFF; + +parameter gem1__tx_status = 32'hE000C014; +parameter val_gem1__tx_status = 32'h00000000; +parameter mask_gem1__tx_status = 32'hFFFFFFFF; + +parameter gem1__rx_qbar = 32'hE000C018; +parameter val_gem1__rx_qbar = 32'h00000000; +parameter mask_gem1__rx_qbar = 32'hFFFFFFFF; + +parameter gem1__tx_qbar = 32'hE000C01C; +parameter val_gem1__tx_qbar = 32'h00000000; +parameter mask_gem1__tx_qbar = 32'hFFFFFFFF; + +parameter gem1__rx_status = 32'hE000C020; +parameter val_gem1__rx_status = 32'h00000000; +parameter mask_gem1__rx_status = 32'hFFFFFFFF; + +parameter gem1__intr_status = 32'hE000C024; +parameter val_gem1__intr_status = 32'h00000000; +parameter mask_gem1__intr_status = 32'hFFFFFFFF; + +parameter gem1__intr_en = 32'hE000C028; +parameter val_gem1__intr_en = 32'h00000000; +parameter mask_gem1__intr_en = 32'h00000000; + +parameter gem1__intr_dis = 32'hE000C02C; +parameter val_gem1__intr_dis = 32'h00000000; +parameter mask_gem1__intr_dis = 32'h00000000; + +parameter gem1__intr_mask = 32'hE000C030; +parameter val_gem1__intr_mask = 32'h0001FFFF; +parameter mask_gem1__intr_mask = 32'hFC01FFFF; + +parameter gem1__phy_maint = 32'hE000C034; +parameter val_gem1__phy_maint = 32'h00000000; +parameter mask_gem1__phy_maint = 32'hFFFFFFFF; + +parameter gem1__rx_pauseq = 32'hE000C038; +parameter val_gem1__rx_pauseq = 32'h00000000; +parameter mask_gem1__rx_pauseq = 32'hFFFFFFFF; + +parameter gem1__tx_pauseq = 32'hE000C03C; +parameter val_gem1__tx_pauseq = 32'h0000FFFF; +parameter mask_gem1__tx_pauseq = 32'hFFFFFFFF; + +parameter gem1__tx_partial_st_fwd = 32'hE000C040; +parameter val_gem1__tx_partial_st_fwd = 32'h000003FF; +parameter mask_gem1__tx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem1__rx_partial_st_fwd = 32'hE000C044; +parameter val_gem1__rx_partial_st_fwd = 32'h000003FF; +parameter mask_gem1__rx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem1__hash_bot = 32'hE000C080; +parameter val_gem1__hash_bot = 32'h00000000; +parameter mask_gem1__hash_bot = 32'hFFFFFFFF; + +parameter gem1__hash_top = 32'hE000C084; +parameter val_gem1__hash_top = 32'h00000000; +parameter mask_gem1__hash_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_bot = 32'hE000C088; +parameter val_gem1__spec_addr1_bot = 32'h00000000; +parameter mask_gem1__spec_addr1_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_top = 32'hE000C08C; +parameter val_gem1__spec_addr1_top = 32'h00000000; +parameter mask_gem1__spec_addr1_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr2_bot = 32'hE000C090; +parameter val_gem1__spec_addr2_bot = 32'h00000000; +parameter mask_gem1__spec_addr2_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr2_top = 32'hE000C094; +parameter val_gem1__spec_addr2_top = 32'h00000000; +parameter mask_gem1__spec_addr2_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr3_bot = 32'hE000C098; +parameter val_gem1__spec_addr3_bot = 32'h00000000; +parameter mask_gem1__spec_addr3_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr3_top = 32'hE000C09C; +parameter val_gem1__spec_addr3_top = 32'h00000000; +parameter mask_gem1__spec_addr3_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr4_bot = 32'hE000C0A0; +parameter val_gem1__spec_addr4_bot = 32'h00000000; +parameter mask_gem1__spec_addr4_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr4_top = 32'hE000C0A4; +parameter val_gem1__spec_addr4_top = 32'h00000000; +parameter mask_gem1__spec_addr4_top = 32'hFFFFFFFF; + +parameter gem1__type_id_match1 = 32'hE000C0A8; +parameter val_gem1__type_id_match1 = 32'h00000000; +parameter mask_gem1__type_id_match1 = 32'hFFFFFFFF; + +parameter gem1__type_id_match2 = 32'hE000C0AC; +parameter val_gem1__type_id_match2 = 32'h00000000; +parameter mask_gem1__type_id_match2 = 32'hFFFFFFFF; + +parameter gem1__type_id_match3 = 32'hE000C0B0; +parameter val_gem1__type_id_match3 = 32'h00000000; +parameter mask_gem1__type_id_match3 = 32'hFFFFFFFF; + +parameter gem1__type_id_match4 = 32'hE000C0B4; +parameter val_gem1__type_id_match4 = 32'h00000000; +parameter mask_gem1__type_id_match4 = 32'hFFFFFFFF; + +parameter gem1__wake_on_lan = 32'hE000C0B8; +parameter val_gem1__wake_on_lan = 32'h00000000; +parameter mask_gem1__wake_on_lan = 32'hFFFFFFFF; + +parameter gem1__ipg_stretch = 32'hE000C0BC; +parameter val_gem1__ipg_stretch = 32'h00000000; +parameter mask_gem1__ipg_stretch = 32'hFFFFFFFF; + +parameter gem1__stacked_vlan = 32'hE000C0C0; +parameter val_gem1__stacked_vlan = 32'h00000000; +parameter mask_gem1__stacked_vlan = 32'hFFFFFFFF; + +parameter gem1__tx_pfc_pause = 32'hE000C0C4; +parameter val_gem1__tx_pfc_pause = 32'h00000000; +parameter mask_gem1__tx_pfc_pause = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_mask_bot = 32'hE000C0C8; +parameter val_gem1__spec_addr1_mask_bot = 32'h00000000; +parameter mask_gem1__spec_addr1_mask_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_mask_top = 32'hE000C0CC; +parameter val_gem1__spec_addr1_mask_top = 32'h00000000; +parameter mask_gem1__spec_addr1_mask_top = 32'hFFFFFFFF; + +parameter gem1__module_id = 32'hE000C0FC; +parameter val_gem1__module_id = 32'h00020118; +parameter mask_gem1__module_id = 32'hFFFFFFFF; + +parameter gem1__octets_tx_bot = 32'hE000C100; +parameter val_gem1__octets_tx_bot = 32'h00000000; +parameter mask_gem1__octets_tx_bot = 32'hFFFFFFFF; + +parameter gem1__octets_tx_top = 32'hE000C104; +parameter val_gem1__octets_tx_top = 32'h00000000; +parameter mask_gem1__octets_tx_top = 32'hFFFFFFFF; + +parameter gem1__frames_tx = 32'hE000C108; +parameter val_gem1__frames_tx = 32'h00000000; +parameter mask_gem1__frames_tx = 32'hFFFFFFFF; + +parameter gem1__broadcast_frames_tx = 32'hE000C10C; +parameter val_gem1__broadcast_frames_tx = 32'h00000000; +parameter mask_gem1__broadcast_frames_tx = 32'hFFFFFFFF; + +parameter gem1__multi_frames_tx = 32'hE000C110; +parameter val_gem1__multi_frames_tx = 32'h00000000; +parameter mask_gem1__multi_frames_tx = 32'hFFFFFFFF; + +parameter gem1__pause_frames_tx = 32'hE000C114; +parameter val_gem1__pause_frames_tx = 32'h00000000; +parameter mask_gem1__pause_frames_tx = 32'hFFFFFFFF; + +parameter gem1__frames_64b_tx = 32'hE000C118; +parameter val_gem1__frames_64b_tx = 32'h00000000; +parameter mask_gem1__frames_64b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_65to127b_tx = 32'hE000C11C; +parameter val_gem1__frames_65to127b_tx = 32'h00000000; +parameter mask_gem1__frames_65to127b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_128to255b_tx = 32'hE000C120; +parameter val_gem1__frames_128to255b_tx = 32'h00000000; +parameter mask_gem1__frames_128to255b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_256to511b_tx = 32'hE000C124; +parameter val_gem1__frames_256to511b_tx = 32'h00000000; +parameter mask_gem1__frames_256to511b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_512to1023b_tx = 32'hE000C128; +parameter val_gem1__frames_512to1023b_tx = 32'h00000000; +parameter mask_gem1__frames_512to1023b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_1024to1518b_tx = 32'hE000C12C; +parameter val_gem1__frames_1024to1518b_tx = 32'h00000000; +parameter mask_gem1__frames_1024to1518b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_gt1518b_tx = 32'hE000C130; +parameter val_gem1__frames_gt1518b_tx = 32'h00000000; +parameter mask_gem1__frames_gt1518b_tx = 32'hFFFFFFFF; + +parameter gem1__tx_under_runs = 32'hE000C134; +parameter val_gem1__tx_under_runs = 32'h00000000; +parameter mask_gem1__tx_under_runs = 32'hFFFFFFFF; + +parameter gem1__single_collisn_frames = 32'hE000C138; +parameter val_gem1__single_collisn_frames = 32'h00000000; +parameter mask_gem1__single_collisn_frames = 32'hFFFFFFFF; + +parameter gem1__multi_collisn_frames = 32'hE000C13C; +parameter val_gem1__multi_collisn_frames = 32'h00000000; +parameter mask_gem1__multi_collisn_frames = 32'hFFFFFFFF; + +parameter gem1__excessive_collisns = 32'hE000C140; +parameter val_gem1__excessive_collisns = 32'h00000000; +parameter mask_gem1__excessive_collisns = 32'hFFFFFFFF; + +parameter gem1__late_collisns = 32'hE000C144; +parameter val_gem1__late_collisns = 32'h00000000; +parameter mask_gem1__late_collisns = 32'hFFFFFFFF; + +parameter gem1__deferred_tx_frames = 32'hE000C148; +parameter val_gem1__deferred_tx_frames = 32'h00000000; +parameter mask_gem1__deferred_tx_frames = 32'hFFFFFFFF; + +parameter gem1__carrier_sense_errs = 32'hE000C14C; +parameter val_gem1__carrier_sense_errs = 32'h00000000; +parameter mask_gem1__carrier_sense_errs = 32'hFFFFFFFF; + +parameter gem1__octets_rx_bot = 32'hE000C150; +parameter val_gem1__octets_rx_bot = 32'h00000000; +parameter mask_gem1__octets_rx_bot = 32'hFFFFFFFF; + +parameter gem1__octets_rx_top = 32'hE000C154; +parameter val_gem1__octets_rx_top = 32'h00000000; +parameter mask_gem1__octets_rx_top = 32'hFFFFFFFF; + +parameter gem1__frames_rx = 32'hE000C158; +parameter val_gem1__frames_rx = 32'h00000000; +parameter mask_gem1__frames_rx = 32'hFFFFFFFF; + +parameter gem1__bdcast_fames_rx = 32'hE000C15C; +parameter val_gem1__bdcast_fames_rx = 32'h00000000; +parameter mask_gem1__bdcast_fames_rx = 32'hFFFFFFFF; + +parameter gem1__multi_frames_rx = 32'hE000C160; +parameter val_gem1__multi_frames_rx = 32'h00000000; +parameter mask_gem1__multi_frames_rx = 32'hFFFFFFFF; + +parameter gem1__pause_rx = 32'hE000C164; +parameter val_gem1__pause_rx = 32'h00000000; +parameter mask_gem1__pause_rx = 32'hFFFFFFFF; + +parameter gem1__frames_64b_rx = 32'hE000C168; +parameter val_gem1__frames_64b_rx = 32'h00000000; +parameter mask_gem1__frames_64b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_65to127b_rx = 32'hE000C16C; +parameter val_gem1__frames_65to127b_rx = 32'h00000000; +parameter mask_gem1__frames_65to127b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_128to255b_rx = 32'hE000C170; +parameter val_gem1__frames_128to255b_rx = 32'h00000000; +parameter mask_gem1__frames_128to255b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_256to511b_rx = 32'hE000C174; +parameter val_gem1__frames_256to511b_rx = 32'h00000000; +parameter mask_gem1__frames_256to511b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_512to1023b_rx = 32'hE000C178; +parameter val_gem1__frames_512to1023b_rx = 32'h00000000; +parameter mask_gem1__frames_512to1023b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_1024to1518b_rx = 32'hE000C17C; +parameter val_gem1__frames_1024to1518b_rx = 32'h00000000; +parameter mask_gem1__frames_1024to1518b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_gt1518b_rx = 32'hE000C180; +parameter val_gem1__frames_gt1518b_rx = 32'h00000000; +parameter mask_gem1__frames_gt1518b_rx = 32'hFFFFFFFF; + +parameter gem1__undersz_rx = 32'hE000C184; +parameter val_gem1__undersz_rx = 32'h00000000; +parameter mask_gem1__undersz_rx = 32'hFFFFFFFF; + +parameter gem1__oversz_rx = 32'hE000C188; +parameter val_gem1__oversz_rx = 32'h00000000; +parameter mask_gem1__oversz_rx = 32'hFFFFFFFF; + +parameter gem1__jab_rx = 32'hE000C18C; +parameter val_gem1__jab_rx = 32'h00000000; +parameter mask_gem1__jab_rx = 32'hFFFFFFFF; + +parameter gem1__fcs_errors = 32'hE000C190; +parameter val_gem1__fcs_errors = 32'h00000000; +parameter mask_gem1__fcs_errors = 32'hFFFFFFFF; + +parameter gem1__length_field_errors = 32'hE000C194; +parameter val_gem1__length_field_errors = 32'h00000000; +parameter mask_gem1__length_field_errors = 32'hFFFFFFFF; + +parameter gem1__rx_symbol_errors = 32'hE000C198; +parameter val_gem1__rx_symbol_errors = 32'h00000000; +parameter mask_gem1__rx_symbol_errors = 32'hFFFFFFFF; + +parameter gem1__align_errors = 32'hE000C19C; +parameter val_gem1__align_errors = 32'h00000000; +parameter mask_gem1__align_errors = 32'hFFFFFFFF; + +parameter gem1__rx_resource_errors = 32'hE000C1A0; +parameter val_gem1__rx_resource_errors = 32'h00000000; +parameter mask_gem1__rx_resource_errors = 32'hFFFFFFFF; + +parameter gem1__rx_overrun_errors = 32'hE000C1A4; +parameter val_gem1__rx_overrun_errors = 32'h00000000; +parameter mask_gem1__rx_overrun_errors = 32'hFFFFFFFF; + +parameter gem1__ip_hdr_csum_errors = 32'hE000C1A8; +parameter val_gem1__ip_hdr_csum_errors = 32'h00000000; +parameter mask_gem1__ip_hdr_csum_errors = 32'hFFFFFFFF; + +parameter gem1__tcp_csum_errors = 32'hE000C1AC; +parameter val_gem1__tcp_csum_errors = 32'h00000000; +parameter mask_gem1__tcp_csum_errors = 32'hFFFFFFFF; + +parameter gem1__udp_csum_errors = 32'hE000C1B0; +parameter val_gem1__udp_csum_errors = 32'h00000000; +parameter mask_gem1__udp_csum_errors = 32'hFFFFFFFF; + +parameter gem1__timer_strobe_s = 32'hE000C1C8; +parameter val_gem1__timer_strobe_s = 32'h00000000; +parameter mask_gem1__timer_strobe_s = 32'hFFFFFFFF; + +parameter gem1__timer_strobe_ns = 32'hE000C1CC; +parameter val_gem1__timer_strobe_ns = 32'h00000000; +parameter mask_gem1__timer_strobe_ns = 32'hFFFFFFFF; + +parameter gem1__timer_s = 32'hE000C1D0; +parameter val_gem1__timer_s = 32'h00000000; +parameter mask_gem1__timer_s = 32'hFFFFFFFF; + +parameter gem1__timer_ns = 32'hE000C1D4; +parameter val_gem1__timer_ns = 32'h00000000; +parameter mask_gem1__timer_ns = 32'hFFFFFFFF; + +parameter gem1__timer_adjust = 32'hE000C1D8; +parameter val_gem1__timer_adjust = 32'h00000000; +parameter mask_gem1__timer_adjust = 32'hFFFFFFFF; + +parameter gem1__timer_incr = 32'hE000C1DC; +parameter val_gem1__timer_incr = 32'h00000000; +parameter mask_gem1__timer_incr = 32'hFFFFFFFF; + +parameter gem1__ptp_tx_s = 32'hE000C1E0; +parameter val_gem1__ptp_tx_s = 32'h00000000; +parameter mask_gem1__ptp_tx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_tx_ns = 32'hE000C1E4; +parameter val_gem1__ptp_tx_ns = 32'h00000000; +parameter mask_gem1__ptp_tx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_rx_s = 32'hE000C1E8; +parameter val_gem1__ptp_rx_s = 32'h00000000; +parameter mask_gem1__ptp_rx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_rx_ns = 32'hE000C1EC; +parameter val_gem1__ptp_rx_ns = 32'h00000000; +parameter mask_gem1__ptp_rx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_tx_s = 32'hE000C1F0; +parameter val_gem1__ptp_peer_tx_s = 32'h00000000; +parameter mask_gem1__ptp_peer_tx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_tx_ns = 32'hE000C1F4; +parameter val_gem1__ptp_peer_tx_ns = 32'h00000000; +parameter mask_gem1__ptp_peer_tx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_rx_s = 32'hE000C1F8; +parameter val_gem1__ptp_peer_rx_s = 32'h00000000; +parameter mask_gem1__ptp_peer_rx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_rx_ns = 32'hE000C1FC; +parameter val_gem1__ptp_peer_rx_ns = 32'h00000000; +parameter mask_gem1__ptp_peer_rx_ns = 32'hFFFFFFFF; + +parameter gem1__pcs_ctrl = 32'hE000C200; +parameter val_gem1__pcs_ctrl = 32'h00000000; +parameter mask_gem1__pcs_ctrl = 32'h00000000; + +parameter gem1__pcs_status = 32'hE000C204; +parameter val_gem1__pcs_status = 32'h00000000; +parameter mask_gem1__pcs_status = 32'h00000000; + +parameter gem1__pcs_upper_phy_id = 32'hE000C208; +parameter val_gem1__pcs_upper_phy_id = 32'h00000000; +parameter mask_gem1__pcs_upper_phy_id = 32'h00000000; + +parameter gem1__pcs_lower_phy_id = 32'hE000C20C; +parameter val_gem1__pcs_lower_phy_id = 32'h00000000; +parameter mask_gem1__pcs_lower_phy_id = 32'h00000000; + +parameter gem1__pcs_autoneg_ad = 32'hE000C210; +parameter val_gem1__pcs_autoneg_ad = 32'h00000000; +parameter mask_gem1__pcs_autoneg_ad = 32'h00000000; + +parameter gem1__pcs_autoneg_ability = 32'hE000C214; +parameter val_gem1__pcs_autoneg_ability = 32'h00000000; +parameter mask_gem1__pcs_autoneg_ability = 32'h00000000; + +parameter gem1__pcs_autonec_exp = 32'hE000C218; +parameter val_gem1__pcs_autonec_exp = 32'h00000000; +parameter mask_gem1__pcs_autonec_exp = 32'h00000000; + +parameter gem1__pcs_autoneg_next_pg = 32'hE000C21C; +parameter val_gem1__pcs_autoneg_next_pg = 32'h00000000; +parameter mask_gem1__pcs_autoneg_next_pg = 32'h00000000; + +parameter gem1__pcs_autoneg_pnext_pg = 32'hE000C220; +parameter val_gem1__pcs_autoneg_pnext_pg = 32'h00000000; +parameter mask_gem1__pcs_autoneg_pnext_pg = 32'h00000000; + +parameter gem1__pcs_extended_status = 32'hE000C23C; +parameter val_gem1__pcs_extended_status = 32'h00000000; +parameter mask_gem1__pcs_extended_status = 32'h00000000; + +parameter gem1__design_cfg1 = 32'hE000C280; +parameter val_gem1__design_cfg1 = 32'h02000000; +parameter mask_gem1__design_cfg1 = 32'h0E000000; + +parameter gem1__design_cfg2 = 32'hE000C284; +parameter val_gem1__design_cfg2 = 32'h2A813FFF; +parameter mask_gem1__design_cfg2 = 32'h3FCFFFFF; + +parameter gem1__design_cfg3 = 32'hE000C288; +parameter val_gem1__design_cfg3 = 32'h00000000; +parameter mask_gem1__design_cfg3 = 32'hFFFFFFFF; + +parameter gem1__design_cfg4 = 32'hE000C28C; +parameter val_gem1__design_cfg4 = 32'h00000000; +parameter mask_gem1__design_cfg4 = 32'hFFFFFFFF; + +parameter gem1__design_cfg5 = 32'hE000C290; +parameter val_gem1__design_cfg5 = 32'h002F2045; +parameter mask_gem1__design_cfg5 = 32'h0FFFFCFF; + +parameter gem1__design_cfg6 = 32'hE000C294; +parameter val_gem1__design_cfg6 = 32'h00000000; +parameter mask_gem1__design_cfg6 = 32'h00000000; + +parameter gem1__design_cfg7 = 32'hE000C298; +parameter val_gem1__design_cfg7 = 32'h00000000; +parameter mask_gem1__design_cfg7 = 32'h00000000; + +parameter gem1__isr_pq1 = 32'hE000C400; +parameter val_gem1__isr_pq1 = 32'h00000000; +parameter mask_gem1__isr_pq1 = 32'h00000000; + +parameter gem1__isr_pq2 = 32'hE000C404; +parameter val_gem1__isr_pq2 = 32'h00000000; +parameter mask_gem1__isr_pq2 = 32'h00000000; + +parameter gem1__isr_pq3 = 32'hE000C408; +parameter val_gem1__isr_pq3 = 32'h00000000; +parameter mask_gem1__isr_pq3 = 32'h00000000; + +parameter gem1__isr_pq4 = 32'hE000C40C; +parameter val_gem1__isr_pq4 = 32'h00000000; +parameter mask_gem1__isr_pq4 = 32'h00000000; + +parameter gem1__isr_pq5 = 32'hE000C410; +parameter val_gem1__isr_pq5 = 32'h00000000; +parameter mask_gem1__isr_pq5 = 32'h00000000; + +parameter gem1__isr_pq6 = 32'hE000C414; +parameter val_gem1__isr_pq6 = 32'h00000000; +parameter mask_gem1__isr_pq6 = 32'h00000000; + +parameter gem1__isr_pq7 = 32'hE000C418; +parameter val_gem1__isr_pq7 = 32'h00000000; +parameter mask_gem1__isr_pq7 = 32'h00000000; + +parameter gem1__tx_qbar_q1 = 32'hE000C440; +parameter val_gem1__tx_qbar_q1 = 32'h00000000; +parameter mask_gem1__tx_qbar_q1 = 32'h00000000; + +parameter gem1__tx_qbar_q2 = 32'hE000C444; +parameter val_gem1__tx_qbar_q2 = 32'h00000000; +parameter mask_gem1__tx_qbar_q2 = 32'h00000000; + +parameter gem1__tx_qbar_q3 = 32'hE000C448; +parameter val_gem1__tx_qbar_q3 = 32'h00000000; +parameter mask_gem1__tx_qbar_q3 = 32'h00000000; + +parameter gem1__tx_qbar_q4 = 32'hE000C44C; +parameter val_gem1__tx_qbar_q4 = 32'h00000000; +parameter mask_gem1__tx_qbar_q4 = 32'h00000000; + +parameter gem1__tx_qbar_q5 = 32'hE000C450; +parameter val_gem1__tx_qbar_q5 = 32'h00000000; +parameter mask_gem1__tx_qbar_q5 = 32'h00000000; + +parameter gem1__tx_qbar_q6 = 32'hE000C454; +parameter val_gem1__tx_qbar_q6 = 32'h00000000; +parameter mask_gem1__tx_qbar_q6 = 32'h00000000; + +parameter gem1__tx_qbar_q7 = 32'hE000C458; +parameter val_gem1__tx_qbar_q7 = 32'h00000000; +parameter mask_gem1__tx_qbar_q7 = 32'h00000000; + +parameter gem1__rx_qbar_q1 = 32'hE000C480; +parameter val_gem1__rx_qbar_q1 = 32'h00000000; +parameter mask_gem1__rx_qbar_q1 = 32'h00000000; + +parameter gem1__rx_qbar_q2 = 32'hE000C484; +parameter val_gem1__rx_qbar_q2 = 32'h00000000; +parameter mask_gem1__rx_qbar_q2 = 32'h00000000; + +parameter gem1__rx_qbar_q3 = 32'hE000C488; +parameter val_gem1__rx_qbar_q3 = 32'h00000000; +parameter mask_gem1__rx_qbar_q3 = 32'h00000000; + +parameter gem1__rx_qbar_q4 = 32'hE000C48C; +parameter val_gem1__rx_qbar_q4 = 32'h00000000; +parameter mask_gem1__rx_qbar_q4 = 32'h00000000; + +parameter gem1__rx_qbar_q5 = 32'hE000C490; +parameter val_gem1__rx_qbar_q5 = 32'h00000000; +parameter mask_gem1__rx_qbar_q5 = 32'h00000000; + +parameter gem1__rx_qbar_q6 = 32'hE000C494; +parameter val_gem1__rx_qbar_q6 = 32'h00000000; +parameter mask_gem1__rx_qbar_q6 = 32'h00000000; + +parameter gem1__rx_qbar_q7 = 32'hE000C498; +parameter val_gem1__rx_qbar_q7 = 32'h00000000; +parameter mask_gem1__rx_qbar_q7 = 32'h00000000; + +parameter gem1__rx_bufsz_q1 = 32'hE000C4A0; +parameter val_gem1__rx_bufsz_q1 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q1 = 32'h00000000; + +parameter gem1__rx_bufsz_q2 = 32'hE000C4A4; +parameter val_gem1__rx_bufsz_q2 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q2 = 32'h00000000; + +parameter gem1__rx_bufsz_q3 = 32'hE000C4A8; +parameter val_gem1__rx_bufsz_q3 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q3 = 32'h00000000; + +parameter gem1__rx_bufsz_q4 = 32'hE000C4AC; +parameter val_gem1__rx_bufsz_q4 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q4 = 32'h00000000; + +parameter gem1__rx_bufsz_q5 = 32'hE000C4B0; +parameter val_gem1__rx_bufsz_q5 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q5 = 32'h00000000; + +parameter gem1__rx_bufsz_q6 = 32'hE000C4B4; +parameter val_gem1__rx_bufsz_q6 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q6 = 32'h00000000; + +parameter gem1__rx_bufsz_q7 = 32'hE000C4B8; +parameter val_gem1__rx_bufsz_q7 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q7 = 32'h00000000; + +parameter gem1__screen_t1_r0 = 32'hE000C500; +parameter val_gem1__screen_t1_r0 = 32'h00000000; +parameter mask_gem1__screen_t1_r0 = 32'h00000000; + +parameter gem1__screen_t1_r1 = 32'hE000C504; +parameter val_gem1__screen_t1_r1 = 32'h00000000; +parameter mask_gem1__screen_t1_r1 = 32'h00000000; + +parameter gem1__screen_t1_r2 = 32'hE000C508; +parameter val_gem1__screen_t1_r2 = 32'h00000000; +parameter mask_gem1__screen_t1_r2 = 32'h00000000; + +parameter gem1__screen_t1_r3 = 32'hE000C50C; +parameter val_gem1__screen_t1_r3 = 32'h00000000; +parameter mask_gem1__screen_t1_r3 = 32'h00000000; + +parameter gem1__screen_t1_r4 = 32'hE000C510; +parameter val_gem1__screen_t1_r4 = 32'h00000000; +parameter mask_gem1__screen_t1_r4 = 32'h00000000; + +parameter gem1__screen_t1_r5 = 32'hE000C514; +parameter val_gem1__screen_t1_r5 = 32'h00000000; +parameter mask_gem1__screen_t1_r5 = 32'h00000000; + +parameter gem1__screen_t1_r6 = 32'hE000C518; +parameter val_gem1__screen_t1_r6 = 32'h00000000; +parameter mask_gem1__screen_t1_r6 = 32'h00000000; + +parameter gem1__screen_t1_r7 = 32'hE000C51C; +parameter val_gem1__screen_t1_r7 = 32'h00000000; +parameter mask_gem1__screen_t1_r7 = 32'h00000000; + +parameter gem1__screen_t1_r8 = 32'hE000C520; +parameter val_gem1__screen_t1_r8 = 32'h00000000; +parameter mask_gem1__screen_t1_r8 = 32'h00000000; + +parameter gem1__screen_t1_r9 = 32'hE000C524; +parameter val_gem1__screen_t1_r9 = 32'h00000000; +parameter mask_gem1__screen_t1_r9 = 32'h00000000; + +parameter gem1__screen_t1_r10 = 32'hE000C528; +parameter val_gem1__screen_t1_r10 = 32'h00000000; +parameter mask_gem1__screen_t1_r10 = 32'h00000000; + +parameter gem1__screen_t1_r11 = 32'hE000C52C; +parameter val_gem1__screen_t1_r11 = 32'h00000000; +parameter mask_gem1__screen_t1_r11 = 32'h00000000; + +parameter gem1__screen_t1_r12 = 32'hE000C530; +parameter val_gem1__screen_t1_r12 = 32'h00000000; +parameter mask_gem1__screen_t1_r12 = 32'h00000000; + +parameter gem1__screen_t1_r13 = 32'hE000C534; +parameter val_gem1__screen_t1_r13 = 32'h00000000; +parameter mask_gem1__screen_t1_r13 = 32'h00000000; + +parameter gem1__screen_t1_r14 = 32'hE000C538; +parameter val_gem1__screen_t1_r14 = 32'h00000000; +parameter mask_gem1__screen_t1_r14 = 32'h00000000; + +parameter gem1__screen_t1_r15 = 32'hE000C53C; +parameter val_gem1__screen_t1_r15 = 32'h00000000; +parameter mask_gem1__screen_t1_r15 = 32'h00000000; + +parameter gem1__screen_t2_r0 = 32'hE000C540; +parameter val_gem1__screen_t2_r0 = 32'h00000000; +parameter mask_gem1__screen_t2_r0 = 32'h00000000; + +parameter gem1__screen_t2_r1 = 32'hE000C544; +parameter val_gem1__screen_t2_r1 = 32'h00000000; +parameter mask_gem1__screen_t2_r1 = 32'h00000000; + +parameter gem1__screen_t2_r2 = 32'hE000C548; +parameter val_gem1__screen_t2_r2 = 32'h00000000; +parameter mask_gem1__screen_t2_r2 = 32'h00000000; + +parameter gem1__screen_t2_r3 = 32'hE000C54C; +parameter val_gem1__screen_t2_r3 = 32'h00000000; +parameter mask_gem1__screen_t2_r3 = 32'h00000000; + +parameter gem1__screen_t2_r4 = 32'hE000C550; +parameter val_gem1__screen_t2_r4 = 32'h00000000; +parameter mask_gem1__screen_t2_r4 = 32'h00000000; + +parameter gem1__screen_t2_r5 = 32'hE000C554; +parameter val_gem1__screen_t2_r5 = 32'h00000000; +parameter mask_gem1__screen_t2_r5 = 32'h00000000; + +parameter gem1__screen_t2_r6 = 32'hE000C558; +parameter val_gem1__screen_t2_r6 = 32'h00000000; +parameter mask_gem1__screen_t2_r6 = 32'h00000000; + +parameter gem1__screen_t2_r7 = 32'hE000C55C; +parameter val_gem1__screen_t2_r7 = 32'h00000000; +parameter mask_gem1__screen_t2_r7 = 32'h00000000; + +parameter gem1__screen_t2_r8 = 32'hE000C560; +parameter val_gem1__screen_t2_r8 = 32'h00000000; +parameter mask_gem1__screen_t2_r8 = 32'h00000000; + +parameter gem1__screen_t2_r9 = 32'hE000C564; +parameter val_gem1__screen_t2_r9 = 32'h00000000; +parameter mask_gem1__screen_t2_r9 = 32'h00000000; + +parameter gem1__screen_t2_r10 = 32'hE000C568; +parameter val_gem1__screen_t2_r10 = 32'h00000000; +parameter mask_gem1__screen_t2_r10 = 32'h00000000; + +parameter gem1__screen_t2_r11 = 32'hE000C56C; +parameter val_gem1__screen_t2_r11 = 32'h00000000; +parameter mask_gem1__screen_t2_r11 = 32'h00000000; + +parameter gem1__screen_t2_r12 = 32'hE000C570; +parameter val_gem1__screen_t2_r12 = 32'h00000000; +parameter mask_gem1__screen_t2_r12 = 32'h00000000; + +parameter gem1__screen_t2_r13 = 32'hE000C574; +parameter val_gem1__screen_t2_r13 = 32'h00000000; +parameter mask_gem1__screen_t2_r13 = 32'h00000000; + +parameter gem1__screen_t2_r14 = 32'hE000C578; +parameter val_gem1__screen_t2_r14 = 32'h00000000; +parameter mask_gem1__screen_t2_r14 = 32'h00000000; + +parameter gem1__screen_t2_r15 = 32'hE000C57C; +parameter val_gem1__screen_t2_r15 = 32'h00000000; +parameter mask_gem1__screen_t2_r15 = 32'h00000000; + +parameter gem1__intr_en_pq1 = 32'hE000C600; +parameter val_gem1__intr_en_pq1 = 32'h00000000; +parameter mask_gem1__intr_en_pq1 = 32'h00000000; + +parameter gem1__intr_en_pq2 = 32'hE000C604; +parameter val_gem1__intr_en_pq2 = 32'h00000000; +parameter mask_gem1__intr_en_pq2 = 32'h00000000; + +parameter gem1__intr_en_pq3 = 32'hE000C608; +parameter val_gem1__intr_en_pq3 = 32'h00000000; +parameter mask_gem1__intr_en_pq3 = 32'h00000000; + +parameter gem1__intr_en_pq4 = 32'hE000C60C; +parameter val_gem1__intr_en_pq4 = 32'h00000000; +parameter mask_gem1__intr_en_pq4 = 32'h00000000; + +parameter gem1__intr_en_pq5 = 32'hE000C610; +parameter val_gem1__intr_en_pq5 = 32'h00000000; +parameter mask_gem1__intr_en_pq5 = 32'h00000000; + +parameter gem1__intr_en_pq6 = 32'hE000C614; +parameter val_gem1__intr_en_pq6 = 32'h00000000; +parameter mask_gem1__intr_en_pq6 = 32'h00000000; + +parameter gem1__intr_en_pq7 = 32'hE000C618; +parameter val_gem1__intr_en_pq7 = 32'h00000000; +parameter mask_gem1__intr_en_pq7 = 32'h00000000; + +parameter gem1__intr_dis_pq1 = 32'hE000C620; +parameter val_gem1__intr_dis_pq1 = 32'h00000000; +parameter mask_gem1__intr_dis_pq1 = 32'h00000000; + +parameter gem1__intr_dis_pq2 = 32'hE000C624; +parameter val_gem1__intr_dis_pq2 = 32'h00000000; +parameter mask_gem1__intr_dis_pq2 = 32'h00000000; + +parameter gem1__intr_dis_pq3 = 32'hE000C628; +parameter val_gem1__intr_dis_pq3 = 32'h00000000; +parameter mask_gem1__intr_dis_pq3 = 32'h00000000; + +parameter gem1__intr_dis_pq4 = 32'hE000C62C; +parameter val_gem1__intr_dis_pq4 = 32'h00000000; +parameter mask_gem1__intr_dis_pq4 = 32'h00000000; + +parameter gem1__intr_dis_pq5 = 32'hE000C630; +parameter val_gem1__intr_dis_pq5 = 32'h00000000; +parameter mask_gem1__intr_dis_pq5 = 32'h00000000; + +parameter gem1__intr_dis_pq6 = 32'hE000C634; +parameter val_gem1__intr_dis_pq6 = 32'h00000000; +parameter mask_gem1__intr_dis_pq6 = 32'h00000000; + +parameter gem1__intr_dis_pq7 = 32'hE000C638; +parameter val_gem1__intr_dis_pq7 = 32'h00000000; +parameter mask_gem1__intr_dis_pq7 = 32'h00000000; + +parameter gem1__intr_mask_pq1 = 32'hE000C640; +parameter val_gem1__intr_mask_pq1 = 32'h00000000; +parameter mask_gem1__intr_mask_pq1 = 32'h00000000; + +parameter gem1__intr_mask_pq2 = 32'hE000C644; +parameter val_gem1__intr_mask_pq2 = 32'h00000000; +parameter mask_gem1__intr_mask_pq2 = 32'h00000000; + +parameter gem1__intr_mask_pq3 = 32'hE000C648; +parameter val_gem1__intr_mask_pq3 = 32'h00000000; +parameter mask_gem1__intr_mask_pq3 = 32'h00000000; + +parameter gem1__intr_mask_pq4 = 32'hE000C64C; +parameter val_gem1__intr_mask_pq4 = 32'h00000000; +parameter mask_gem1__intr_mask_pq4 = 32'h00000000; + +parameter gem1__intr_mask_pq5 = 32'hE000C650; +parameter val_gem1__intr_mask_pq5 = 32'h00000000; +parameter mask_gem1__intr_mask_pq5 = 32'h00000000; + +parameter gem1__intr_mask_pq6 = 32'hE000C654; +parameter val_gem1__intr_mask_pq6 = 32'h00000000; +parameter mask_gem1__intr_mask_pq6 = 32'h00000000; + +parameter gem1__intr_mask_pq7 = 32'hE000C658; +parameter val_gem1__intr_mask_pq7 = 32'h00000000; +parameter mask_gem1__intr_mask_pq7 = 32'h00000000; + + +// ************************************************************ +// Module gpio gpio +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpio__MASK_DATA_0_LSW = 32'hE000A000; +parameter val_gpio__MASK_DATA_0_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_0_LSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_0_MSW = 32'hE000A004; +parameter val_gpio__MASK_DATA_0_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_0_MSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_1_LSW = 32'hE000A008; +parameter val_gpio__MASK_DATA_1_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_1_LSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_1_MSW = 32'hE000A00C; +parameter val_gpio__MASK_DATA_1_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_1_MSW = 32'h003FFFC0; + +parameter gpio__MASK_DATA_2_LSW = 32'hE000A010; +parameter val_gpio__MASK_DATA_2_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_2_LSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_2_MSW = 32'hE000A014; +parameter val_gpio__MASK_DATA_2_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_2_MSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_3_LSW = 32'hE000A018; +parameter val_gpio__MASK_DATA_3_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_3_LSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_3_MSW = 32'hE000A01C; +parameter val_gpio__MASK_DATA_3_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_3_MSW = 32'hFFFFFFFF; + +parameter gpio__DATA_0 = 32'hE000A040; +parameter val_gpio__DATA_0 = 32'h00000000; +parameter mask_gpio__DATA_0 = 32'h00000000; + +parameter gpio__DATA_1 = 32'hE000A044; +parameter val_gpio__DATA_1 = 32'h00000000; +parameter mask_gpio__DATA_1 = 32'h00000000; + +parameter gpio__DATA_2 = 32'hE000A048; +parameter val_gpio__DATA_2 = 32'h00000000; +parameter mask_gpio__DATA_2 = 32'hFFFFFFFF; + +parameter gpio__DATA_3 = 32'hE000A04C; +parameter val_gpio__DATA_3 = 32'h00000000; +parameter mask_gpio__DATA_3 = 32'hFFFFFFFF; + +parameter gpio__DATA_0_RO = 32'hE000A060; +parameter val_gpio__DATA_0_RO = 32'h00000000; +parameter mask_gpio__DATA_0_RO = 32'h00000000; + +parameter gpio__DATA_1_RO = 32'hE000A064; +parameter val_gpio__DATA_1_RO = 32'h00000000; +parameter mask_gpio__DATA_1_RO = 32'h00000000; + +parameter gpio__DATA_2_RO = 32'hE000A068; +parameter val_gpio__DATA_2_RO = 32'h00000000; +parameter mask_gpio__DATA_2_RO = 32'hFFFFFFFF; + +parameter gpio__DATA_3_RO = 32'hE000A06C; +parameter val_gpio__DATA_3_RO = 32'h00000000; +parameter mask_gpio__DATA_3_RO = 32'hFFFFFFFF; + +parameter gpio__BYPM_0 = 32'hE000A200; +parameter val_gpio__BYPM_0 = 32'h00000000; +parameter mask_gpio__BYPM_0 = 32'hFFFFFFFF; + +parameter gpio__DIRM_0 = 32'hE000A204; +parameter val_gpio__DIRM_0 = 32'h00000000; +parameter mask_gpio__DIRM_0 = 32'hFFFFFFFF; + +parameter gpio__OEN_0 = 32'hE000A208; +parameter val_gpio__OEN_0 = 32'h00000000; +parameter mask_gpio__OEN_0 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_0 = 32'hE000A20C; +parameter val_gpio__INT_MASK_0 = 32'h00000000; +parameter mask_gpio__INT_MASK_0 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_0 = 32'hE000A210; +parameter val_gpio__INT_EN_0 = 32'h00000000; +parameter mask_gpio__INT_EN_0 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_0 = 32'hE000A214; +parameter val_gpio__INT_DIS_0 = 32'h00000000; +parameter mask_gpio__INT_DIS_0 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_0 = 32'hE000A218; +parameter val_gpio__INT_STAT_0 = 32'h00000000; +parameter mask_gpio__INT_STAT_0 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_0 = 32'hE000A21C; +parameter val_gpio__INT_TYPE_0 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_0 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_0 = 32'hE000A220; +parameter val_gpio__INT_POLARITY_0 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_0 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_0 = 32'hE000A224; +parameter val_gpio__INT_ANY_0 = 32'h00000000; +parameter mask_gpio__INT_ANY_0 = 32'hFFFFFFFF; + +parameter gpio__BYPM_1 = 32'hE000A240; +parameter val_gpio__BYPM_1 = 32'h00000000; +parameter mask_gpio__BYPM_1 = 32'h003FFFFF; + +parameter gpio__DIRM_1 = 32'hE000A244; +parameter val_gpio__DIRM_1 = 32'h00000000; +parameter mask_gpio__DIRM_1 = 32'h003FFFFF; + +parameter gpio__OEN_1 = 32'hE000A248; +parameter val_gpio__OEN_1 = 32'h00000000; +parameter mask_gpio__OEN_1 = 32'h003FFFFF; + +parameter gpio__INT_MASK_1 = 32'hE000A24C; +parameter val_gpio__INT_MASK_1 = 32'h00000000; +parameter mask_gpio__INT_MASK_1 = 32'h003FFFFF; + +parameter gpio__INT_EN_1 = 32'hE000A250; +parameter val_gpio__INT_EN_1 = 32'h00000000; +parameter mask_gpio__INT_EN_1 = 32'h003FFFFF; + +parameter gpio__INT_DIS_1 = 32'hE000A254; +parameter val_gpio__INT_DIS_1 = 32'h00000000; +parameter mask_gpio__INT_DIS_1 = 32'h003FFFFF; + +parameter gpio__INT_STAT_1 = 32'hE000A258; +parameter val_gpio__INT_STAT_1 = 32'h00000000; +parameter mask_gpio__INT_STAT_1 = 32'h003FFFFF; + +parameter gpio__INT_TYPE_1 = 32'hE000A25C; +parameter val_gpio__INT_TYPE_1 = 32'h003FFFFF; +parameter mask_gpio__INT_TYPE_1 = 32'h003FFFFF; + +parameter gpio__INT_POLARITY_1 = 32'hE000A260; +parameter val_gpio__INT_POLARITY_1 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_1 = 32'h003FFFFF; + +parameter gpio__INT_ANY_1 = 32'hE000A264; +parameter val_gpio__INT_ANY_1 = 32'h00000000; +parameter mask_gpio__INT_ANY_1 = 32'h003FFFFF; + +parameter gpio__BYPM_2 = 32'hE000A280; +parameter val_gpio__BYPM_2 = 32'h00000000; +parameter mask_gpio__BYPM_2 = 32'hFFFFFFFF; + +parameter gpio__DIRM_2 = 32'hE000A284; +parameter val_gpio__DIRM_2 = 32'h00000000; +parameter mask_gpio__DIRM_2 = 32'hFFFFFFFF; + +parameter gpio__OEN_2 = 32'hE000A288; +parameter val_gpio__OEN_2 = 32'h00000000; +parameter mask_gpio__OEN_2 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_2 = 32'hE000A28C; +parameter val_gpio__INT_MASK_2 = 32'h00000000; +parameter mask_gpio__INT_MASK_2 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_2 = 32'hE000A290; +parameter val_gpio__INT_EN_2 = 32'h00000000; +parameter mask_gpio__INT_EN_2 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_2 = 32'hE000A294; +parameter val_gpio__INT_DIS_2 = 32'h00000000; +parameter mask_gpio__INT_DIS_2 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_2 = 32'hE000A298; +parameter val_gpio__INT_STAT_2 = 32'h00000000; +parameter mask_gpio__INT_STAT_2 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_2 = 32'hE000A29C; +parameter val_gpio__INT_TYPE_2 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_2 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_2 = 32'hE000A2A0; +parameter val_gpio__INT_POLARITY_2 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_2 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_2 = 32'hE000A2A4; +parameter val_gpio__INT_ANY_2 = 32'h00000000; +parameter mask_gpio__INT_ANY_2 = 32'hFFFFFFFF; + +parameter gpio__BYPM_3 = 32'hE000A2C0; +parameter val_gpio__BYPM_3 = 32'h00000000; +parameter mask_gpio__BYPM_3 = 32'hFFFFFFFF; + +parameter gpio__DIRM_3 = 32'hE000A2C4; +parameter val_gpio__DIRM_3 = 32'h00000000; +parameter mask_gpio__DIRM_3 = 32'hFFFFFFFF; + +parameter gpio__OEN_3 = 32'hE000A2C8; +parameter val_gpio__OEN_3 = 32'h00000000; +parameter mask_gpio__OEN_3 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_3 = 32'hE000A2CC; +parameter val_gpio__INT_MASK_3 = 32'h00000000; +parameter mask_gpio__INT_MASK_3 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_3 = 32'hE000A2D0; +parameter val_gpio__INT_EN_3 = 32'h00000000; +parameter mask_gpio__INT_EN_3 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_3 = 32'hE000A2D4; +parameter val_gpio__INT_DIS_3 = 32'h00000000; +parameter mask_gpio__INT_DIS_3 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_3 = 32'hE000A2D8; +parameter val_gpio__INT_STAT_3 = 32'h00000000; +parameter mask_gpio__INT_STAT_3 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_3 = 32'hE000A2DC; +parameter val_gpio__INT_TYPE_3 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_3 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_3 = 32'hE000A2E0; +parameter val_gpio__INT_POLARITY_3 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_3 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_3 = 32'hE000A2E4; +parameter val_gpio__INT_ANY_3 = 32'h00000000; +parameter mask_gpio__INT_ANY_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module gpv_iou_switch gpv_iou_switch +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_iou_switch__Remap = 32'hE0200000; +parameter val_gpv_iou_switch__Remap = 32'h00000000; +parameter mask_gpv_iou_switch__Remap = 32'h000000FF; + +parameter gpv_iou_switch__security2_sdio0 = 32'hE0200008; +parameter val_gpv_iou_switch__security2_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__security2_sdio0 = 32'h00000001; + +parameter gpv_iou_switch__security3_sdio1 = 32'hE020000C; +parameter val_gpv_iou_switch__security3_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__security3_sdio1 = 32'h00000001; + +parameter gpv_iou_switch__security4_qspi = 32'hE0200010; +parameter val_gpv_iou_switch__security4_qspi = 32'h00000000; +parameter mask_gpv_iou_switch__security4_qspi = 32'h00000001; + +parameter gpv_iou_switch__security5_miou = 32'hE0200014; +parameter val_gpv_iou_switch__security5_miou = 32'h00000000; +parameter mask_gpv_iou_switch__security5_miou = 32'h00000001; + +parameter gpv_iou_switch__security6_apb_slaves = 32'hE0200018; +parameter val_gpv_iou_switch__security6_apb_slaves = 32'h00000000; +parameter mask_gpv_iou_switch__security6_apb_slaves = 32'h00007FFF; + +parameter gpv_iou_switch__security7_smc = 32'hE020001C; +parameter val_gpv_iou_switch__security7_smc = 32'h00000000; +parameter mask_gpv_iou_switch__security7_smc = 32'h00000001; + +parameter gpv_iou_switch__peripheral_id4 = 32'hE0201FD0; +parameter val_gpv_iou_switch__peripheral_id4 = 32'h00000004; +parameter mask_gpv_iou_switch__peripheral_id4 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id5 = 32'hE0201FD4; +parameter val_gpv_iou_switch__peripheral_id5 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id5 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id6 = 32'hE0201FD8; +parameter val_gpv_iou_switch__peripheral_id6 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id6 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id7 = 32'hE0201FDC; +parameter val_gpv_iou_switch__peripheral_id7 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id7 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id0 = 32'hE0201FE0; +parameter val_gpv_iou_switch__peripheral_id0 = 32'h00000001; +parameter mask_gpv_iou_switch__peripheral_id0 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id1 = 32'hE0201FE4; +parameter val_gpv_iou_switch__peripheral_id1 = 32'h000000B3; +parameter mask_gpv_iou_switch__peripheral_id1 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id2 = 32'hE0201FE8; +parameter val_gpv_iou_switch__peripheral_id2 = 32'h0000005B; +parameter mask_gpv_iou_switch__peripheral_id2 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id3 = 32'hE0201FEC; +parameter val_gpv_iou_switch__peripheral_id3 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id3 = 32'h000000FF; + +parameter gpv_iou_switch__component_id0 = 32'hE0201FF0; +parameter val_gpv_iou_switch__component_id0 = 32'h0000000D; +parameter mask_gpv_iou_switch__component_id0 = 32'h000000FF; + +parameter gpv_iou_switch__component_id1 = 32'hE0201FF4; +parameter val_gpv_iou_switch__component_id1 = 32'h000000F0; +parameter mask_gpv_iou_switch__component_id1 = 32'h000000FF; + +parameter gpv_iou_switch__component_id2 = 32'hE0201FF8; +parameter val_gpv_iou_switch__component_id2 = 32'h00000005; +parameter mask_gpv_iou_switch__component_id2 = 32'h000000FF; + +parameter gpv_iou_switch__component_id3 = 32'hE0201FFC; +parameter val_gpv_iou_switch__component_id3 = 32'h000000B1; +parameter mask_gpv_iou_switch__component_id3 = 32'h000000FF; + +parameter gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'hE0202008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000003; + +parameter gpv_iou_switch__ahb_cntl_sdio0 = 32'hE0202044; +parameter val_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; + +parameter gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'hE0203008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000003; + +parameter gpv_iou_switch__ahb_cntl_sdio1 = 32'hE0203044; +parameter val_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; + +parameter gpv_iou_switch__fn_mod_bm_iss_qspi = 32'hE0204008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_bm_iss_miou = 32'hE0205008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_bm_iss_smc = 32'hE0207008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_gem0 = 32'hE0242028; +parameter val_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_gem0 = 32'hE0242100; +parameter val_gpv_iou_switch__read_qos_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_gem0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_gem0 = 32'hE0242104; +parameter val_gpv_iou_switch__write_qos_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_gem0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_gem0 = 32'hE0242108; +parameter val_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_gem1 = 32'hE0243028; +parameter val_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_gem1 = 32'hE0243100; +parameter val_gpv_iou_switch__read_qos_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_gem1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_gem1 = 32'hE0243104; +parameter val_gpv_iou_switch__write_qos_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_gem1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_gem1 = 32'hE0243108; +parameter val_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_usb0 = 32'hE0244028; +parameter val_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_usb0 = 32'hE0244100; +parameter val_gpv_iou_switch__read_qos_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_usb0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_usb0 = 32'hE0244104; +parameter val_gpv_iou_switch__write_qos_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_usb0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_usb0 = 32'hE0244108; +parameter val_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_usb1 = 32'hE0245028; +parameter val_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_usb1 = 32'hE0245100; +parameter val_gpv_iou_switch__read_qos_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_usb1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_usb1 = 32'hE0245104; +parameter val_gpv_iou_switch__write_qos_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_usb1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_usb1 = 32'hE0245108; +parameter val_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_sdio0 = 32'hE0246028; +parameter val_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_sdio0 = 32'hE0246100; +parameter val_gpv_iou_switch__read_qos_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_sdio0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_sdio0 = 32'hE0246104; +parameter val_gpv_iou_switch__write_qos_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_sdio0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_sdio0 = 32'hE0246108; +parameter val_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_sdio1 = 32'hE0247028; +parameter val_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_sdio1 = 32'hE0247100; +parameter val_gpv_iou_switch__read_qos_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_sdio1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_sdio1 = 32'hE0247104; +parameter val_gpv_iou_switch__write_qos_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_sdio1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_sdio1 = 32'hE0247108; +parameter val_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_iss_siou = 32'hE0249108; +parameter val_gpv_iou_switch__fn_mod_iss_siou = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_siou = 32'h00000003; + + +// ************************************************************ +// Module gpv_qos301_cpu qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_cpu__qos_cntl = 32'hF894610C; +parameter val_gpv_qos301_cpu__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_cpu__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_cpu__max_ot = 32'hF8946110; +parameter val_gpv_qos301_cpu__max_ot = 32'h00000000; +parameter mask_gpv_qos301_cpu__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_cpu__max_comb_ot = 32'hF8946114; +parameter val_gpv_qos301_cpu__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_cpu__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_cpu__aw_p = 32'hF8946118; +parameter val_gpv_qos301_cpu__aw_p = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_p = 32'hFF000000; + +parameter gpv_qos301_cpu__aw_b = 32'hF894611C; +parameter val_gpv_qos301_cpu__aw_b = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_cpu__aw_r = 32'hF8946120; +parameter val_gpv_qos301_cpu__aw_r = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_r = 32'hFFF00000; + +parameter gpv_qos301_cpu__ar_p = 32'hF8946124; +parameter val_gpv_qos301_cpu__ar_p = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_p = 32'hFF000000; + +parameter gpv_qos301_cpu__ar_b = 32'hF8946128; +parameter val_gpv_qos301_cpu__ar_b = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_cpu__ar_r = 32'hF894612C; +parameter val_gpv_qos301_cpu__ar_r = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_qos301_dmac qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_dmac__qos_cntl = 32'hF894710C; +parameter val_gpv_qos301_dmac__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_dmac__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_dmac__max_ot = 32'hF8947110; +parameter val_gpv_qos301_dmac__max_ot = 32'h00000000; +parameter mask_gpv_qos301_dmac__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_dmac__max_comb_ot = 32'hF8947114; +parameter val_gpv_qos301_dmac__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_dmac__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_dmac__aw_p = 32'hF8947118; +parameter val_gpv_qos301_dmac__aw_p = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_p = 32'hFF000000; + +parameter gpv_qos301_dmac__aw_b = 32'hF894711C; +parameter val_gpv_qos301_dmac__aw_b = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_dmac__aw_r = 32'hF8947120; +parameter val_gpv_qos301_dmac__aw_r = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_r = 32'hFFF00000; + +parameter gpv_qos301_dmac__ar_p = 32'hF8947124; +parameter val_gpv_qos301_dmac__ar_p = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_p = 32'hFF000000; + +parameter gpv_qos301_dmac__ar_b = 32'hF8947128; +parameter val_gpv_qos301_dmac__ar_b = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_dmac__ar_r = 32'hF894712C; +parameter val_gpv_qos301_dmac__ar_r = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_qos301_iou qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_iou__qos_cntl = 32'hF894810C; +parameter val_gpv_qos301_iou__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_iou__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_iou__max_ot = 32'hF8948110; +parameter val_gpv_qos301_iou__max_ot = 32'h00000000; +parameter mask_gpv_qos301_iou__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_iou__max_comb_ot = 32'hF8948114; +parameter val_gpv_qos301_iou__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_iou__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_iou__aw_p = 32'hF8948118; +parameter val_gpv_qos301_iou__aw_p = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_p = 32'hFF000000; + +parameter gpv_qos301_iou__aw_b = 32'hF894811C; +parameter val_gpv_qos301_iou__aw_b = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_iou__aw_r = 32'hF8948120; +parameter val_gpv_qos301_iou__aw_r = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_r = 32'hFFF00000; + +parameter gpv_qos301_iou__ar_p = 32'hF8948124; +parameter val_gpv_qos301_iou__ar_p = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_p = 32'hFF000000; + +parameter gpv_qos301_iou__ar_b = 32'hF8948128; +parameter val_gpv_qos301_iou__ar_b = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_iou__ar_r = 32'hF894812C; +parameter val_gpv_qos301_iou__ar_r = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_trustzone nic301_addr_region_ctrl_registers +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_trustzone__Remap = 32'hF8900000; +parameter val_gpv_trustzone__Remap = 32'h00000000; +parameter mask_gpv_trustzone__Remap = 32'h000000C0; + +parameter gpv_trustzone__security_fssw_s0 = 32'hF890001C; +parameter val_gpv_trustzone__security_fssw_s0 = 32'h00000000; +parameter mask_gpv_trustzone__security_fssw_s0 = 32'h00000001; + +parameter gpv_trustzone__security_fssw_s1 = 32'hF8900020; +parameter val_gpv_trustzone__security_fssw_s1 = 32'h00000000; +parameter mask_gpv_trustzone__security_fssw_s1 = 32'h00000001; + +parameter gpv_trustzone__security_apb = 32'hF8900028; +parameter val_gpv_trustzone__security_apb = 32'h00000000; +parameter mask_gpv_trustzone__security_apb = 32'h0000003F; + + +// ************************************************************ +// Module i2c0 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter i2c0__Control_reg0 = 32'hE0004000; +parameter val_i2c0__Control_reg0 = 32'h00000000; +parameter mask_i2c0__Control_reg0 = 32'h0000FFFF; + +parameter i2c0__Status_reg0 = 32'hE0004004; +parameter val_i2c0__Status_reg0 = 32'h00000000; +parameter mask_i2c0__Status_reg0 = 32'h0000FFFF; + +parameter i2c0__I2C_address_reg0 = 32'hE0004008; +parameter val_i2c0__I2C_address_reg0 = 32'h00000000; +parameter mask_i2c0__I2C_address_reg0 = 32'h0000FFFF; + +parameter i2c0__I2C_data_reg0 = 32'hE000400C; +parameter val_i2c0__I2C_data_reg0 = 32'h00000000; +parameter mask_i2c0__I2C_data_reg0 = 32'h0000FFFF; + +parameter i2c0__Interrupt_status_reg0 = 32'hE0004010; +parameter val_i2c0__Interrupt_status_reg0 = 32'h00000000; +parameter mask_i2c0__Interrupt_status_reg0 = 32'h0000FFFF; + +parameter i2c0__Transfer_size_reg0 = 32'hE0004014; +parameter val_i2c0__Transfer_size_reg0 = 32'h00000000; +parameter mask_i2c0__Transfer_size_reg0 = 32'h000000FF; + +parameter i2c0__Slave_mon_pause_reg0 = 32'hE0004018; +parameter val_i2c0__Slave_mon_pause_reg0 = 32'h00000000; +parameter mask_i2c0__Slave_mon_pause_reg0 = 32'h000000FF; + +parameter i2c0__Time_out_reg0 = 32'hE000401C; +parameter val_i2c0__Time_out_reg0 = 32'h0000001F; +parameter mask_i2c0__Time_out_reg0 = 32'h000000FF; + +parameter i2c0__Intrpt_mask_reg0 = 32'hE0004020; +parameter val_i2c0__Intrpt_mask_reg0 = 32'h000002FF; +parameter mask_i2c0__Intrpt_mask_reg0 = 32'h0000FFFF; + +parameter i2c0__Intrpt_enable_reg0 = 32'hE0004024; +parameter val_i2c0__Intrpt_enable_reg0 = 32'h00000000; +parameter mask_i2c0__Intrpt_enable_reg0 = 32'h0000FFFF; + +parameter i2c0__Intrpt_disable_reg0 = 32'hE0004028; +parameter val_i2c0__Intrpt_disable_reg0 = 32'h00000000; +parameter mask_i2c0__Intrpt_disable_reg0 = 32'h0000FFFF; + + +// ************************************************************ +// Module i2c1 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter i2c1__Control_reg0 = 32'hE0005000; +parameter val_i2c1__Control_reg0 = 32'h00000000; +parameter mask_i2c1__Control_reg0 = 32'h0000FFFF; + +parameter i2c1__Status_reg0 = 32'hE0005004; +parameter val_i2c1__Status_reg0 = 32'h00000000; +parameter mask_i2c1__Status_reg0 = 32'h0000FFFF; + +parameter i2c1__I2C_address_reg0 = 32'hE0005008; +parameter val_i2c1__I2C_address_reg0 = 32'h00000000; +parameter mask_i2c1__I2C_address_reg0 = 32'h0000FFFF; + +parameter i2c1__I2C_data_reg0 = 32'hE000500C; +parameter val_i2c1__I2C_data_reg0 = 32'h00000000; +parameter mask_i2c1__I2C_data_reg0 = 32'h0000FFFF; + +parameter i2c1__Interrupt_status_reg0 = 32'hE0005010; +parameter val_i2c1__Interrupt_status_reg0 = 32'h00000000; +parameter mask_i2c1__Interrupt_status_reg0 = 32'h0000FFFF; + +parameter i2c1__Transfer_size_reg0 = 32'hE0005014; +parameter val_i2c1__Transfer_size_reg0 = 32'h00000000; +parameter mask_i2c1__Transfer_size_reg0 = 32'h000000FF; + +parameter i2c1__Slave_mon_pause_reg0 = 32'hE0005018; +parameter val_i2c1__Slave_mon_pause_reg0 = 32'h00000000; +parameter mask_i2c1__Slave_mon_pause_reg0 = 32'h000000FF; + +parameter i2c1__Time_out_reg0 = 32'hE000501C; +parameter val_i2c1__Time_out_reg0 = 32'h0000001F; +parameter mask_i2c1__Time_out_reg0 = 32'h000000FF; + +parameter i2c1__Intrpt_mask_reg0 = 32'hE0005020; +parameter val_i2c1__Intrpt_mask_reg0 = 32'h000002FF; +parameter mask_i2c1__Intrpt_mask_reg0 = 32'h0000FFFF; + +parameter i2c1__Intrpt_enable_reg0 = 32'hE0005024; +parameter val_i2c1__Intrpt_enable_reg0 = 32'h00000000; +parameter mask_i2c1__Intrpt_enable_reg0 = 32'h0000FFFF; + +parameter i2c1__Intrpt_disable_reg0 = 32'hE0005028; +parameter val_i2c1__Intrpt_disable_reg0 = 32'h00000000; +parameter mask_i2c1__Intrpt_disable_reg0 = 32'h0000FFFF; + + +// ************************************************************ +// Module l2cache L2Cpl310 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter l2cache__reg0_cache_id = 32'hF8F02000; +parameter val_l2cache__reg0_cache_id = 32'h410000C8; +parameter mask_l2cache__reg0_cache_id = 32'hFFFFFFFF; + +parameter l2cache__reg0_cache_type = 32'hF8F02004; +parameter val_l2cache__reg0_cache_type = 32'h9E300300; +parameter mask_l2cache__reg0_cache_type = 32'hFFFFFFFF; + +parameter l2cache__reg1_control = 32'hF8F02100; +parameter val_l2cache__reg1_control = 32'h00000000; +parameter mask_l2cache__reg1_control = 32'h7FFFFFFF; + +parameter l2cache__reg1_aux_control = 32'hF8F02104; +parameter val_l2cache__reg1_aux_control = 32'h02050000; +parameter mask_l2cache__reg1_aux_control = 32'hFFFFFFFF; + +parameter l2cache__reg1_tag_ram_control = 32'hF8F02108; +parameter val_l2cache__reg1_tag_ram_control = 32'h00000777; +parameter mask_l2cache__reg1_tag_ram_control = 32'hFFFFFFFF; + +parameter l2cache__reg1_data_ram_control = 32'hF8F0210C; +parameter val_l2cache__reg1_data_ram_control = 32'h00000777; +parameter mask_l2cache__reg1_data_ram_control = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter_ctrl = 32'hF8F02200; +parameter val_l2cache__reg2_ev_counter_ctrl = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter1_cfg = 32'hF8F02204; +parameter val_l2cache__reg2_ev_counter1_cfg = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter1_cfg = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter0_cfg = 32'hF8F02208; +parameter val_l2cache__reg2_ev_counter0_cfg = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter0_cfg = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter1 = 32'hF8F0220C; +parameter val_l2cache__reg2_ev_counter1 = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter1 = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter0 = 32'hF8F02210; +parameter val_l2cache__reg2_ev_counter0 = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter0 = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_mask = 32'hF8F02214; +parameter val_l2cache__reg2_int_mask = 32'h00000000; +parameter mask_l2cache__reg2_int_mask = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_mask_status = 32'hF8F02218; +parameter val_l2cache__reg2_int_mask_status = 32'h00000000; +parameter mask_l2cache__reg2_int_mask_status = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_raw_status = 32'hF8F0221C; +parameter val_l2cache__reg2_int_raw_status = 32'h00000000; +parameter mask_l2cache__reg2_int_raw_status = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_clear = 32'hF8F02220; +parameter val_l2cache__reg2_int_clear = 32'h00000000; +parameter mask_l2cache__reg2_int_clear = 32'hFFFFFFFF; + +parameter l2cache__reg7_cache_sync = 32'hF8F02730; +parameter val_l2cache__reg7_cache_sync = 32'h00000000; +parameter mask_l2cache__reg7_cache_sync = 32'hFFFFFFFF; + +parameter l2cache__reg7_inv_pa = 32'hF8F02770; +parameter val_l2cache__reg7_inv_pa = 32'h00000000; +parameter mask_l2cache__reg7_inv_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_inv_way = 32'hF8F0277C; +parameter val_l2cache__reg7_inv_way = 32'h00000000; +parameter mask_l2cache__reg7_inv_way = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_pa = 32'hF8F027B0; +parameter val_l2cache__reg7_clean_pa = 32'h00000000; +parameter mask_l2cache__reg7_clean_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_index = 32'hF8F027B8; +parameter val_l2cache__reg7_clean_index = 32'h00000000; +parameter mask_l2cache__reg7_clean_index = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_way = 32'hF8F027BC; +parameter val_l2cache__reg7_clean_way = 32'h00000000; +parameter mask_l2cache__reg7_clean_way = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_pa = 32'hF8F027F0; +parameter val_l2cache__reg7_clean_inv_pa = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_index = 32'hF8F027F8; +parameter val_l2cache__reg7_clean_inv_index = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_index = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_way = 32'hF8F027FC; +parameter val_l2cache__reg7_clean_inv_way = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_way = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown0 = 32'hF8F02900; +parameter val_l2cache__reg9_d_lockdown0 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown0 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown0 = 32'hF8F02904; +parameter val_l2cache__reg9_i_lockdown0 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown0 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown1 = 32'hF8F02908; +parameter val_l2cache__reg9_d_lockdown1 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown1 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown1 = 32'hF8F0290C; +parameter val_l2cache__reg9_i_lockdown1 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown1 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown2 = 32'hF8F02910; +parameter val_l2cache__reg9_d_lockdown2 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown2 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown2 = 32'hF8F02914; +parameter val_l2cache__reg9_i_lockdown2 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown2 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown3 = 32'hF8F02918; +parameter val_l2cache__reg9_d_lockdown3 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown3 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown3 = 32'hF8F0291C; +parameter val_l2cache__reg9_i_lockdown3 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown3 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown4 = 32'hF8F02920; +parameter val_l2cache__reg9_d_lockdown4 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown4 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown4 = 32'hF8F02924; +parameter val_l2cache__reg9_i_lockdown4 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown4 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown5 = 32'hF8F02928; +parameter val_l2cache__reg9_d_lockdown5 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown5 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown5 = 32'hF8F0292C; +parameter val_l2cache__reg9_i_lockdown5 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown5 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown6 = 32'hF8F02930; +parameter val_l2cache__reg9_d_lockdown6 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown6 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown6 = 32'hF8F02934; +parameter val_l2cache__reg9_i_lockdown6 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown6 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown7 = 32'hF8F02938; +parameter val_l2cache__reg9_d_lockdown7 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown7 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown7 = 32'hF8F0293C; +parameter val_l2cache__reg9_i_lockdown7 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown7 = 32'hFFFFFFFF; + +parameter l2cache__reg9_lock_line_en = 32'hF8F02950; +parameter val_l2cache__reg9_lock_line_en = 32'h00000000; +parameter mask_l2cache__reg9_lock_line_en = 32'hFFFFFFFF; + +parameter l2cache__reg9_unlock_way = 32'hF8F02954; +parameter val_l2cache__reg9_unlock_way = 32'h00000000; +parameter mask_l2cache__reg9_unlock_way = 32'hFFFFFFFF; + +parameter l2cache__reg12_addr_filtering_start = 32'hF8F02C00; +parameter val_l2cache__reg12_addr_filtering_start = 32'h40000001; +parameter mask_l2cache__reg12_addr_filtering_start = 32'hFFFFFFFF; + +parameter l2cache__reg12_addr_filtering_end = 32'hF8F02C04; +parameter val_l2cache__reg12_addr_filtering_end = 32'hFFF00000; +parameter mask_l2cache__reg12_addr_filtering_end = 32'hFFFFFFFF; + +parameter l2cache__reg15_debug_ctrl = 32'hF8F02F40; +parameter val_l2cache__reg15_debug_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_debug_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg15_prefetch_ctrl = 32'hF8F02F60; +parameter val_l2cache__reg15_prefetch_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_prefetch_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg15_power_ctrl = 32'hF8F02F80; +parameter val_l2cache__reg15_power_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_power_ctrl = 32'hFFFFFFFF; + + +// ************************************************************ +// Module mpcore mpcore +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter mpcore__SCU_CONTROL_REGISTER = 32'hF8F00000; +parameter val_mpcore__SCU_CONTROL_REGISTER = 32'h00000002; +parameter mask_mpcore__SCU_CONTROL_REGISTER = 32'hFFFFFFFF; + +parameter mpcore__SCU_CONFIGURATION_REGISTER = 32'hF8F00004; +parameter val_mpcore__SCU_CONFIGURATION_REGISTER = 32'h00000501; +parameter mask_mpcore__SCU_CONFIGURATION_REGISTER = 32'hFFFFFFFF; + +parameter mpcore__SCU_CPU_Power_Status_Register = 32'hF8F00008; +parameter val_mpcore__SCU_CPU_Power_Status_Register = 32'h00000000; +parameter mask_mpcore__SCU_CPU_Power_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hF8F0000C; +parameter val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'h00000000; +parameter mask_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hFFFFFFFF; + +parameter mpcore__Filtering_Start_Address_Register = 32'hF8F00040; +parameter val_mpcore__Filtering_Start_Address_Register = 32'h00100000; +parameter mask_mpcore__Filtering_Start_Address_Register = 32'hFFFFFFFF; + +parameter mpcore__Filtering_End_Address_Register = 32'hF8F00044; +parameter val_mpcore__Filtering_End_Address_Register = 32'h00000000; +parameter mask_mpcore__Filtering_End_Address_Register = 32'hFFFFFFFF; + +parameter mpcore__SCU_Access_Control_Register_SAC = 32'hF8F00050; +parameter val_mpcore__SCU_Access_Control_Register_SAC = 32'h0000000F; +parameter mask_mpcore__SCU_Access_Control_Register_SAC = 32'hFFFFFFFF; + +parameter mpcore__SCU_Non_secure_Access_Control_Register = 32'hF8F00054; +parameter val_mpcore__SCU_Non_secure_Access_Control_Register = 32'h00000000; +parameter mask_mpcore__SCU_Non_secure_Access_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__ICCICR = 32'hF8F00100; +parameter val_mpcore__ICCICR = 32'h00000000; +parameter mask_mpcore__ICCICR = 32'hFFFFFFFF; + +parameter mpcore__ICCPMR = 32'hF8F00104; +parameter val_mpcore__ICCPMR = 32'h00000000; +parameter mask_mpcore__ICCPMR = 32'hFFFFFFFF; + +parameter mpcore__ICCBPR = 32'hF8F00108; +parameter val_mpcore__ICCBPR = 32'h00000002; +parameter mask_mpcore__ICCBPR = 32'hFFFFFFFF; + +parameter mpcore__ICCIAR = 32'hF8F0010C; +parameter val_mpcore__ICCIAR = 32'h000003FF; +parameter mask_mpcore__ICCIAR = 32'hFFFFFFFF; + +parameter mpcore__ICCEOIR = 32'hF8F00110; +parameter val_mpcore__ICCEOIR = 32'h00000000; +parameter mask_mpcore__ICCEOIR = 32'hFFFFFFFF; + +parameter mpcore__ICCRPR = 32'hF8F00114; +parameter val_mpcore__ICCRPR = 32'h000000FF; +parameter mask_mpcore__ICCRPR = 32'hFFFFFFFF; + +parameter mpcore__ICCHPIR = 32'hF8F00118; +parameter val_mpcore__ICCHPIR = 32'h000003FF; +parameter mask_mpcore__ICCHPIR = 32'hFFFFFFFF; + +parameter mpcore__ICCABPR = 32'hF8F0011C; +parameter val_mpcore__ICCABPR = 32'h00000003; +parameter mask_mpcore__ICCABPR = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR = 32'hF8F001FC; +parameter val_mpcore__ICCIDR = 32'h3901243B; +parameter mask_mpcore__ICCIDR = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Counter_Register0 = 32'hF8F00200; +parameter val_mpcore__Global_Timer_Counter_Register0 = 32'h00000000; +parameter mask_mpcore__Global_Timer_Counter_Register0 = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Counter_Register1 = 32'hF8F00204; +parameter val_mpcore__Global_Timer_Counter_Register1 = 32'h00000000; +parameter mask_mpcore__Global_Timer_Counter_Register1 = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Control_Register = 32'hF8F00208; +parameter val_mpcore__Global_Timer_Control_Register = 32'h00000000; +parameter mask_mpcore__Global_Timer_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Interrupt_Status_Register = 32'hF8F0020C; +parameter val_mpcore__Global_Timer_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Global_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Comparator_Value_Register0 = 32'hF8F00210; +parameter val_mpcore__Comparator_Value_Register0 = 32'h00000000; +parameter mask_mpcore__Comparator_Value_Register0 = 32'hFFFFFFFF; + +parameter mpcore__Comparator_Value_Register1 = 32'hF8F00214; +parameter val_mpcore__Comparator_Value_Register1 = 32'h00000000; +parameter mask_mpcore__Comparator_Value_Register1 = 32'hFFFFFFFF; + +parameter mpcore__Auto_increment_Register = 32'hF8F00218; +parameter val_mpcore__Auto_increment_Register = 32'h00000000; +parameter mask_mpcore__Auto_increment_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Load_Register = 32'hF8F00600; +parameter val_mpcore__Private_Timer_Load_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Load_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Counter_Register = 32'hF8F00604; +parameter val_mpcore__Private_Timer_Counter_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Counter_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Control_Register = 32'hF8F00608; +parameter val_mpcore__Private_Timer_Control_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Interrupt_Status_Register = 32'hF8F0060C; +parameter val_mpcore__Private_Timer_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Load_Register = 32'hF8F00620; +parameter val_mpcore__Watchdog_Load_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Load_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Counter_Register = 32'hF8F00624; +parameter val_mpcore__Watchdog_Counter_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Counter_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Control_Register = 32'hF8F00628; +parameter val_mpcore__Watchdog_Control_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Interrupt_Status_Register = 32'hF8F0062C; +parameter val_mpcore__Watchdog_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Reset_Status_Register = 32'hF8F00630; +parameter val_mpcore__Watchdog_Reset_Status_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Reset_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Disable_Register = 32'hF8F00634; +parameter val_mpcore__Watchdog_Disable_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Disable_Register = 32'hFFFFFFFF; + +parameter mpcore__ICDDCR = 32'hF8F01000; +parameter val_mpcore__ICDDCR = 32'h00000000; +parameter mask_mpcore__ICDDCR = 32'hFFFFFFFF; + +parameter mpcore__ICDICTR = 32'hF8F01004; +parameter val_mpcore__ICDICTR = 32'h00000C22; +parameter mask_mpcore__ICDICTR = 32'hE000FFFF; + +parameter mpcore__ICDIIDR = 32'hF8F01008; +parameter val_mpcore__ICDIIDR = 32'h0102043B; +parameter mask_mpcore__ICDIIDR = 32'hFFFFFFFF; + +parameter mpcore__ICDISR0 = 32'hF8F01080; +parameter val_mpcore__ICDISR0 = 32'h00000000; +parameter mask_mpcore__ICDISR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISR1 = 32'hF8F01084; +parameter val_mpcore__ICDISR1 = 32'h00000000; +parameter mask_mpcore__ICDISR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISR2 = 32'hF8F01088; +parameter val_mpcore__ICDISR2 = 32'h00000000; +parameter mask_mpcore__ICDISR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER0 = 32'hF8F01100; +parameter val_mpcore__ICDISER0 = 32'h0000FFFF; +parameter mask_mpcore__ICDISER0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER1 = 32'hF8F01104; +parameter val_mpcore__ICDISER1 = 32'h00000000; +parameter mask_mpcore__ICDISER1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER2 = 32'hF8F01108; +parameter val_mpcore__ICDISER2 = 32'h00000000; +parameter mask_mpcore__ICDISER2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER0 = 32'hF8F01180; +parameter val_mpcore__ICDICER0 = 32'h0000FFFF; +parameter mask_mpcore__ICDICER0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER1 = 32'hF8F01184; +parameter val_mpcore__ICDICER1 = 32'h00000000; +parameter mask_mpcore__ICDICER1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER2 = 32'hF8F01188; +parameter val_mpcore__ICDICER2 = 32'h00000000; +parameter mask_mpcore__ICDICER2 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR0 = 32'hF8F01200; +parameter val_mpcore__ICDISPR0 = 32'h00000000; +parameter mask_mpcore__ICDISPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR1 = 32'hF8F01204; +parameter val_mpcore__ICDISPR1 = 32'h00000000; +parameter mask_mpcore__ICDISPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR2 = 32'hF8F01208; +parameter val_mpcore__ICDISPR2 = 32'h00000000; +parameter mask_mpcore__ICDISPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR0 = 32'hF8F01280; +parameter val_mpcore__ICDICPR0 = 32'h00000000; +parameter mask_mpcore__ICDICPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR1 = 32'hF8F01284; +parameter val_mpcore__ICDICPR1 = 32'h00000000; +parameter mask_mpcore__ICDICPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR2 = 32'hF8F01288; +parameter val_mpcore__ICDICPR2 = 32'h00000000; +parameter mask_mpcore__ICDICPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR0 = 32'hF8F01300; +parameter val_mpcore__ICDABR0 = 32'h00000000; +parameter mask_mpcore__ICDABR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR1 = 32'hF8F01304; +parameter val_mpcore__ICDABR1 = 32'h00000000; +parameter mask_mpcore__ICDABR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR2 = 32'hF8F01308; +parameter val_mpcore__ICDABR2 = 32'h00000000; +parameter mask_mpcore__ICDABR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR0 = 32'hF8F01400; +parameter val_mpcore__ICDIPR0 = 32'h00000000; +parameter mask_mpcore__ICDIPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR1 = 32'hF8F01404; +parameter val_mpcore__ICDIPR1 = 32'h00000000; +parameter mask_mpcore__ICDIPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR2 = 32'hF8F01408; +parameter val_mpcore__ICDIPR2 = 32'h00000000; +parameter mask_mpcore__ICDIPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR3 = 32'hF8F0140C; +parameter val_mpcore__ICDIPR3 = 32'h00000000; +parameter mask_mpcore__ICDIPR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR4 = 32'hF8F01410; +parameter val_mpcore__ICDIPR4 = 32'h00000000; +parameter mask_mpcore__ICDIPR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR5 = 32'hF8F01414; +parameter val_mpcore__ICDIPR5 = 32'h00000000; +parameter mask_mpcore__ICDIPR5 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR6 = 32'hF8F01418; +parameter val_mpcore__ICDIPR6 = 32'h00000000; +parameter mask_mpcore__ICDIPR6 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR7 = 32'hF8F0141C; +parameter val_mpcore__ICDIPR7 = 32'h00000000; +parameter mask_mpcore__ICDIPR7 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR8 = 32'hF8F01420; +parameter val_mpcore__ICDIPR8 = 32'h00000000; +parameter mask_mpcore__ICDIPR8 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR9 = 32'hF8F01424; +parameter val_mpcore__ICDIPR9 = 32'h00000000; +parameter mask_mpcore__ICDIPR9 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR10 = 32'hF8F01428; +parameter val_mpcore__ICDIPR10 = 32'h00000000; +parameter mask_mpcore__ICDIPR10 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR11 = 32'hF8F0142C; +parameter val_mpcore__ICDIPR11 = 32'h00000000; +parameter mask_mpcore__ICDIPR11 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR12 = 32'hF8F01430; +parameter val_mpcore__ICDIPR12 = 32'h00000000; +parameter mask_mpcore__ICDIPR12 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR13 = 32'hF8F01434; +parameter val_mpcore__ICDIPR13 = 32'h00000000; +parameter mask_mpcore__ICDIPR13 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR14 = 32'hF8F01438; +parameter val_mpcore__ICDIPR14 = 32'h00000000; +parameter mask_mpcore__ICDIPR14 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR15 = 32'hF8F0143C; +parameter val_mpcore__ICDIPR15 = 32'h00000000; +parameter mask_mpcore__ICDIPR15 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR16 = 32'hF8F01440; +parameter val_mpcore__ICDIPR16 = 32'h00000000; +parameter mask_mpcore__ICDIPR16 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR17 = 32'hF8F01444; +parameter val_mpcore__ICDIPR17 = 32'h00000000; +parameter mask_mpcore__ICDIPR17 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR18 = 32'hF8F01448; +parameter val_mpcore__ICDIPR18 = 32'h00000000; +parameter mask_mpcore__ICDIPR18 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR19 = 32'hF8F0144C; +parameter val_mpcore__ICDIPR19 = 32'h00000000; +parameter mask_mpcore__ICDIPR19 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR20 = 32'hF8F01450; +parameter val_mpcore__ICDIPR20 = 32'h00000000; +parameter mask_mpcore__ICDIPR20 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR21 = 32'hF8F01454; +parameter val_mpcore__ICDIPR21 = 32'h00000000; +parameter mask_mpcore__ICDIPR21 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR22 = 32'hF8F01458; +parameter val_mpcore__ICDIPR22 = 32'h00000000; +parameter mask_mpcore__ICDIPR22 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR23 = 32'hF8F0145C; +parameter val_mpcore__ICDIPR23 = 32'h00000000; +parameter mask_mpcore__ICDIPR23 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR0 = 32'hF8F01800; +parameter val_mpcore__ICDIPTR0 = 32'h01010101; +parameter mask_mpcore__ICDIPTR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR1 = 32'hF8F01804; +parameter val_mpcore__ICDIPTR1 = 32'h01010101; +parameter mask_mpcore__ICDIPTR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR2 = 32'hF8F01808; +parameter val_mpcore__ICDIPTR2 = 32'h01010101; +parameter mask_mpcore__ICDIPTR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR3 = 32'hF8F0180C; +parameter val_mpcore__ICDIPTR3 = 32'h01010101; +parameter mask_mpcore__ICDIPTR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR4 = 32'hF8F01810; +parameter val_mpcore__ICDIPTR4 = 32'h01010101; +parameter mask_mpcore__ICDIPTR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR5 = 32'hF8F01814; +parameter val_mpcore__ICDIPTR5 = 32'h01010101; +parameter mask_mpcore__ICDIPTR5 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR6 = 32'hF8F01818; +parameter val_mpcore__ICDIPTR6 = 32'h01010101; +parameter mask_mpcore__ICDIPTR6 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR7 = 32'hF8F0181C; +parameter val_mpcore__ICDIPTR7 = 32'h01010101; +parameter mask_mpcore__ICDIPTR7 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR8 = 32'hF8F01820; +parameter val_mpcore__ICDIPTR8 = 32'h01010101; +parameter mask_mpcore__ICDIPTR8 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR9 = 32'hF8F01824; +parameter val_mpcore__ICDIPTR9 = 32'h01010101; +parameter mask_mpcore__ICDIPTR9 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR10 = 32'hF8F01828; +parameter val_mpcore__ICDIPTR10 = 32'h01010101; +parameter mask_mpcore__ICDIPTR10 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR11 = 32'hF8F0182C; +parameter val_mpcore__ICDIPTR11 = 32'h01010101; +parameter mask_mpcore__ICDIPTR11 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR12 = 32'hF8F01830; +parameter val_mpcore__ICDIPTR12 = 32'h01010101; +parameter mask_mpcore__ICDIPTR12 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR13 = 32'hF8F01834; +parameter val_mpcore__ICDIPTR13 = 32'h01010101; +parameter mask_mpcore__ICDIPTR13 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR14 = 32'hF8F01838; +parameter val_mpcore__ICDIPTR14 = 32'h01010101; +parameter mask_mpcore__ICDIPTR14 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR15 = 32'hF8F0183C; +parameter val_mpcore__ICDIPTR15 = 32'h01010101; +parameter mask_mpcore__ICDIPTR15 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR16 = 32'hF8F01840; +parameter val_mpcore__ICDIPTR16 = 32'h01010101; +parameter mask_mpcore__ICDIPTR16 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR17 = 32'hF8F01844; +parameter val_mpcore__ICDIPTR17 = 32'h01010101; +parameter mask_mpcore__ICDIPTR17 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR18 = 32'hF8F01848; +parameter val_mpcore__ICDIPTR18 = 32'h01010101; +parameter mask_mpcore__ICDIPTR18 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR19 = 32'hF8F0184C; +parameter val_mpcore__ICDIPTR19 = 32'h01010101; +parameter mask_mpcore__ICDIPTR19 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR20 = 32'hF8F01850; +parameter val_mpcore__ICDIPTR20 = 32'h01010101; +parameter mask_mpcore__ICDIPTR20 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR21 = 32'hF8F01854; +parameter val_mpcore__ICDIPTR21 = 32'h01010101; +parameter mask_mpcore__ICDIPTR21 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR22 = 32'hF8F01858; +parameter val_mpcore__ICDIPTR22 = 32'h01010101; +parameter mask_mpcore__ICDIPTR22 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR23 = 32'hF8F0185C; +parameter val_mpcore__ICDIPTR23 = 32'h01010101; +parameter mask_mpcore__ICDIPTR23 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR0 = 32'hF8F01C00; +parameter val_mpcore__ICDICFR0 = 32'hAAAAAAAA; +parameter mask_mpcore__ICDICFR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR1 = 32'hF8F01C04; +parameter val_mpcore__ICDICFR1 = 32'h7DC00000; +parameter mask_mpcore__ICDICFR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR2 = 32'hF8F01C08; +parameter val_mpcore__ICDICFR2 = 32'h55555555; +parameter mask_mpcore__ICDICFR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR3 = 32'hF8F01C0C; +parameter val_mpcore__ICDICFR3 = 32'h55555555; +parameter mask_mpcore__ICDICFR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR4 = 32'hF8F01C10; +parameter val_mpcore__ICDICFR4 = 32'h55555555; +parameter mask_mpcore__ICDICFR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR5 = 32'hF8F01C14; +parameter val_mpcore__ICDICFR5 = 32'h55555555; +parameter mask_mpcore__ICDICFR5 = 32'hFFFFFFFF; + +parameter mpcore__ppi_status = 32'hF8F01D00; +parameter val_mpcore__ppi_status = 32'h00000000; +parameter mask_mpcore__ppi_status = 32'hFFFFFFFF; + +parameter mpcore__spi_status_0 = 32'hF8F01D04; +parameter val_mpcore__spi_status_0 = 32'h00000000; +parameter mask_mpcore__spi_status_0 = 32'hFFFFFFFF; + +parameter mpcore__spi_status_1 = 32'hF8F01D08; +parameter val_mpcore__spi_status_1 = 32'h00000000; +parameter mask_mpcore__spi_status_1 = 32'hFFFFFFFF; + +parameter mpcore__ICDSGIR = 32'hF8F01F00; +parameter val_mpcore__ICDSGIR = 32'h00000000; +parameter mask_mpcore__ICDSGIR = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR4 = 32'hF8F01FD0; +parameter val_mpcore__ICPIDR4 = 32'h00000004; +parameter mask_mpcore__ICPIDR4 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR5 = 32'hF8F01FD4; +parameter val_mpcore__ICPIDR5 = 32'h00000000; +parameter mask_mpcore__ICPIDR5 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR6 = 32'hF8F01FD8; +parameter val_mpcore__ICPIDR6 = 32'h00000000; +parameter mask_mpcore__ICPIDR6 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR7 = 32'hF8F01FDC; +parameter val_mpcore__ICPIDR7 = 32'h00000000; +parameter mask_mpcore__ICPIDR7 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR0 = 32'hF8F01FE0; +parameter val_mpcore__ICPIDR0 = 32'h00000090; +parameter mask_mpcore__ICPIDR0 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR1 = 32'hF8F01FE4; +parameter val_mpcore__ICPIDR1 = 32'h000000B3; +parameter mask_mpcore__ICPIDR1 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR2 = 32'hF8F01FE8; +parameter val_mpcore__ICPIDR2 = 32'h0000001B; +parameter mask_mpcore__ICPIDR2 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR3 = 32'hF8F01FEC; +parameter val_mpcore__ICPIDR3 = 32'h00000000; +parameter mask_mpcore__ICPIDR3 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR0 = 32'hF8F01FF0; +parameter val_mpcore__ICCIDR0 = 32'h0000000D; +parameter mask_mpcore__ICCIDR0 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR1 = 32'hF8F01FF4; +parameter val_mpcore__ICCIDR1 = 32'h000000F0; +parameter mask_mpcore__ICCIDR1 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR2 = 32'hF8F01FF8; +parameter val_mpcore__ICCIDR2 = 32'h00000005; +parameter mask_mpcore__ICCIDR2 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR3 = 32'hF8F01FFC; +parameter val_mpcore__ICCIDR3 = 32'h000000B1; +parameter mask_mpcore__ICCIDR3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module ocm ocm +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ocm__OCM_PARITY_CTRL = 32'hF800C000; +parameter val_ocm__OCM_PARITY_CTRL = 32'h00000000; +parameter mask_ocm__OCM_PARITY_CTRL = 32'hFFFFFFFF; + +parameter ocm__OCM_PARITY_ERRADDRESS = 32'hF800C004; +parameter val_ocm__OCM_PARITY_ERRADDRESS = 32'h00000000; +parameter mask_ocm__OCM_PARITY_ERRADDRESS = 32'hFFFFFFFF; + +parameter ocm__OCM_IRQ_STS = 32'hF800C008; +parameter val_ocm__OCM_IRQ_STS = 32'h00000000; +parameter mask_ocm__OCM_IRQ_STS = 32'hFFFFFFFF; + +parameter ocm__OCM_CONTROL = 32'hF800C00C; +parameter val_ocm__OCM_CONTROL = 32'h00000000; +parameter mask_ocm__OCM_CONTROL = 32'hFFFFFFFF; + + +// ************************************************************ +// Module qspi qspi +// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller +// Design Specification document +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter qspi__Config_reg = 32'hE000D000; +parameter val_qspi__Config_reg = 32'h80000000; +parameter mask_qspi__Config_reg = 32'hFFFDFFFF; + +parameter qspi__Intr_status_REG = 32'hE000D004; +parameter val_qspi__Intr_status_REG = 32'h00000004; +parameter mask_qspi__Intr_status_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_en_REG = 32'hE000D008; +parameter val_qspi__Intrpt_en_REG = 32'h00000000; +parameter mask_qspi__Intrpt_en_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_dis_REG = 32'hE000D00C; +parameter val_qspi__Intrpt_dis_REG = 32'h00000000; +parameter mask_qspi__Intrpt_dis_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_mask_REG = 32'hE000D010; +parameter val_qspi__Intrpt_mask_REG = 32'h00000000; +parameter mask_qspi__Intrpt_mask_REG = 32'hFFFFFFFF; + +parameter qspi__En_REG = 32'hE000D014; +parameter val_qspi__En_REG = 32'h00000000; +parameter mask_qspi__En_REG = 32'hFFFFFFFF; + +parameter qspi__Delay_REG = 32'hE000D018; +parameter val_qspi__Delay_REG = 32'h00000000; +parameter mask_qspi__Delay_REG = 32'hFFFFFFFF; + +parameter qspi__TXD0 = 32'hE000D01C; +parameter val_qspi__TXD0 = 32'h00000000; +parameter mask_qspi__TXD0 = 32'hFFFFFFFF; + +parameter qspi__Rx_data_REG = 32'hE000D020; +parameter val_qspi__Rx_data_REG = 32'h00000000; +parameter mask_qspi__Rx_data_REG = 32'hFFFFFFFF; + +parameter qspi__Slave_Idle_count_REG = 32'hE000D024; +parameter val_qspi__Slave_Idle_count_REG = 32'h000000FF; +parameter mask_qspi__Slave_Idle_count_REG = 32'hFFFFFFFF; + +parameter qspi__TX_thres_REG = 32'hE000D028; +parameter val_qspi__TX_thres_REG = 32'h00000001; +parameter mask_qspi__TX_thres_REG = 32'hFFFFFFFF; + +parameter qspi__RX_thres_REG = 32'hE000D02C; +parameter val_qspi__RX_thres_REG = 32'h00000001; +parameter mask_qspi__RX_thres_REG = 32'hFFFFFFFF; + +parameter qspi__GPIO = 32'hE000D030; +parameter val_qspi__GPIO = 32'h00000001; +parameter mask_qspi__GPIO = 32'hFFFFFFFF; + +parameter qspi__LPBK_DLY_ADJ = 32'hE000D038; +parameter val_qspi__LPBK_DLY_ADJ = 32'h00000033; +parameter mask_qspi__LPBK_DLY_ADJ = 32'hFFFFFFFF; + +parameter qspi__TXD1 = 32'hE000D080; +parameter val_qspi__TXD1 = 32'h00000000; +parameter mask_qspi__TXD1 = 32'hFFFFFFFF; + +parameter qspi__TXD2 = 32'hE000D084; +parameter val_qspi__TXD2 = 32'h00000000; +parameter mask_qspi__TXD2 = 32'hFFFFFFFF; + +parameter qspi__TXD3 = 32'hE000D088; +parameter val_qspi__TXD3 = 32'h00000000; +parameter mask_qspi__TXD3 = 32'hFFFFFFFF; + +parameter qspi__LQSPI_CFG = 32'hE000D0A0; +parameter val_qspi__LQSPI_CFG = 32'h03A002EB; +parameter mask_qspi__LQSPI_CFG = 32'hFBFF07FF; + +parameter qspi__LQSPI_STS = 32'hE000D0A4; +parameter val_qspi__LQSPI_STS = 32'h00000000; +parameter mask_qspi__LQSPI_STS = 32'h000001FF; + +parameter qspi__MOD_ID = 32'hE000D0FC; +parameter val_qspi__MOD_ID = 32'h01090101; +parameter mask_qspi__MOD_ID = 32'hFFFFFFFF; + + +// ************************************************************ +// Module sd0 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter sd0__SDMA_system_address_register = 32'hE0100000; +parameter val_sd0__SDMA_system_address_register = 32'h00000000; +parameter mask_sd0__SDMA_system_address_register = 32'hFFFFFFFF; + +parameter sd0__Block_Size_Block_Count = 32'hE0100004; +parameter val_sd0__Block_Size_Block_Count = 32'h00000000; +parameter mask_sd0__Block_Size_Block_Count = 32'hFFFFFFFF; + +parameter sd0__Argument = 32'hE0100008; +parameter val_sd0__Argument = 32'h00000000; +parameter mask_sd0__Argument = 32'hFFFFFFFF; + +parameter sd0__Transfer_Mode_Command = 32'hE010000C; +parameter val_sd0__Transfer_Mode_Command = 32'h00000000; +parameter mask_sd0__Transfer_Mode_Command = 32'h1FFFFFFF; + +parameter sd0__Response0 = 32'hE0100010; +parameter val_sd0__Response0 = 32'h00000000; +parameter mask_sd0__Response0 = 32'hFFFFFFFF; + +parameter sd0__Response1 = 32'hE0100014; +parameter val_sd0__Response1 = 32'h00000000; +parameter mask_sd0__Response1 = 32'hFFFFFFFF; + +parameter sd0__Response2 = 32'hE0100018; +parameter val_sd0__Response2 = 32'h00000000; +parameter mask_sd0__Response2 = 32'hFFFFFFFF; + +parameter sd0__Response3 = 32'hE010001C; +parameter val_sd0__Response3 = 32'h00000000; +parameter mask_sd0__Response3 = 32'hFFFFFFFF; + +parameter sd0__Buffer_Data_Port = 32'hE0100020; +parameter val_sd0__Buffer_Data_Port = 32'h00000000; +parameter mask_sd0__Buffer_Data_Port = 32'hFFFFFFFF; + +parameter sd0__Present_State = 32'hE0100024; +parameter val_sd0__Present_State = 32'h01F20000; +parameter mask_sd0__Present_State = 32'h01FFFFFF; + +parameter sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0100028; +parameter val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; +parameter mask_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; + +parameter sd0__Clock_Control_Timeout_control_Software_reset = 32'hE010002C; +parameter val_sd0__Clock_Control_Timeout_control_Software_reset = 32'h00000000; +parameter mask_sd0__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; + +parameter sd0__Normal_interrupt_status_Error_interrupt_status = 32'hE0100030; +parameter val_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; +parameter mask_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; + +parameter sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0100034; +parameter val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; +parameter mask_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; + +parameter sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0100038; +parameter val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; +parameter mask_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; + +parameter sd0__Auto_CMD12_error_status = 32'hE010003C; +parameter val_sd0__Auto_CMD12_error_status = 32'h00000000; +parameter mask_sd0__Auto_CMD12_error_status = 32'h000000FF; + +parameter sd0__Capabilities = 32'hE0100040; +parameter val_sd0__Capabilities = 32'h69EC0080; +parameter mask_sd0__Capabilities = 32'h7FFFFFFF; + +parameter sd0__Maximum_current_capabilities = 32'hE0100048; +parameter val_sd0__Maximum_current_capabilities = 32'h00000001; +parameter mask_sd0__Maximum_current_capabilities = 32'h00FFFFFF; + +parameter sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0100050; +parameter val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; +parameter mask_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; + +parameter sd0__ADMA_error_status = 32'hE0100054; +parameter val_sd0__ADMA_error_status = 32'h00000000; +parameter mask_sd0__ADMA_error_status = 32'h00000007; + +parameter sd0__ADMA_system_address = 32'hE0100058; +parameter val_sd0__ADMA_system_address = 32'h00000000; +parameter mask_sd0__ADMA_system_address = 32'hFFFFFFFF; + +parameter sd0__Boot_Timeout_control = 32'hE0100060; +parameter val_sd0__Boot_Timeout_control = 32'h00000000; +parameter mask_sd0__Boot_Timeout_control = 32'hFFFFFFFF; + +parameter sd0__Debug_Selection = 32'hE0100064; +parameter val_sd0__Debug_Selection = 32'h00000000; +parameter mask_sd0__Debug_Selection = 32'h00000001; + +parameter sd0__SPI_interrupt_support = 32'hE01000F0; +parameter val_sd0__SPI_interrupt_support = 32'h00000000; +parameter mask_sd0__SPI_interrupt_support = 32'h000000FF; + +parameter sd0__Slot_interrupt_status_Host_controller_version = 32'hE01000FC; +parameter val_sd0__Slot_interrupt_status_Host_controller_version = 32'h89010000; +parameter mask_sd0__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; + + +// ************************************************************ +// Module sd1 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter sd1__SDMA_system_address_register = 32'hE0101000; +parameter val_sd1__SDMA_system_address_register = 32'h00000000; +parameter mask_sd1__SDMA_system_address_register = 32'hFFFFFFFF; + +parameter sd1__Block_Size_Block_Count = 32'hE0101004; +parameter val_sd1__Block_Size_Block_Count = 32'h00000000; +parameter mask_sd1__Block_Size_Block_Count = 32'hFFFFFFFF; + +parameter sd1__Argument = 32'hE0101008; +parameter val_sd1__Argument = 32'h00000000; +parameter mask_sd1__Argument = 32'hFFFFFFFF; + +parameter sd1__Transfer_Mode_Command = 32'hE010100C; +parameter val_sd1__Transfer_Mode_Command = 32'h00000000; +parameter mask_sd1__Transfer_Mode_Command = 32'h1FFFFFFF; + +parameter sd1__Response0 = 32'hE0101010; +parameter val_sd1__Response0 = 32'h00000000; +parameter mask_sd1__Response0 = 32'hFFFFFFFF; + +parameter sd1__Response1 = 32'hE0101014; +parameter val_sd1__Response1 = 32'h00000000; +parameter mask_sd1__Response1 = 32'hFFFFFFFF; + +parameter sd1__Response2 = 32'hE0101018; +parameter val_sd1__Response2 = 32'h00000000; +parameter mask_sd1__Response2 = 32'hFFFFFFFF; + +parameter sd1__Response3 = 32'hE010101C; +parameter val_sd1__Response3 = 32'h00000000; +parameter mask_sd1__Response3 = 32'hFFFFFFFF; + +parameter sd1__Buffer_Data_Port = 32'hE0101020; +parameter val_sd1__Buffer_Data_Port = 32'h00000000; +parameter mask_sd1__Buffer_Data_Port = 32'hFFFFFFFF; + +parameter sd1__Present_State = 32'hE0101024; +parameter val_sd1__Present_State = 32'h01F20000; +parameter mask_sd1__Present_State = 32'h01FFFFFF; + +parameter sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0101028; +parameter val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; +parameter mask_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; + +parameter sd1__Clock_Control_Timeout_control_Software_reset = 32'hE010102C; +parameter val_sd1__Clock_Control_Timeout_control_Software_reset = 32'h00000000; +parameter mask_sd1__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; + +parameter sd1__Normal_interrupt_status_Error_interrupt_status = 32'hE0101030; +parameter val_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; +parameter mask_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; + +parameter sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0101034; +parameter val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; +parameter mask_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; + +parameter sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0101038; +parameter val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; +parameter mask_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; + +parameter sd1__Auto_CMD12_error_status = 32'hE010103C; +parameter val_sd1__Auto_CMD12_error_status = 32'h00000000; +parameter mask_sd1__Auto_CMD12_error_status = 32'h000000FF; + +parameter sd1__Capabilities = 32'hE0101040; +parameter val_sd1__Capabilities = 32'h69EC0080; +parameter mask_sd1__Capabilities = 32'h7FFFFFFF; + +parameter sd1__Maximum_current_capabilities = 32'hE0101048; +parameter val_sd1__Maximum_current_capabilities = 32'h00000001; +parameter mask_sd1__Maximum_current_capabilities = 32'h00FFFFFF; + +parameter sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0101050; +parameter val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; +parameter mask_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; + +parameter sd1__ADMA_error_status = 32'hE0101054; +parameter val_sd1__ADMA_error_status = 32'h00000000; +parameter mask_sd1__ADMA_error_status = 32'h00000007; + +parameter sd1__ADMA_system_address = 32'hE0101058; +parameter val_sd1__ADMA_system_address = 32'h00000000; +parameter mask_sd1__ADMA_system_address = 32'hFFFFFFFF; + +parameter sd1__Boot_Timeout_control = 32'hE0101060; +parameter val_sd1__Boot_Timeout_control = 32'h00000000; +parameter mask_sd1__Boot_Timeout_control = 32'hFFFFFFFF; + +parameter sd1__Debug_Selection = 32'hE0101064; +parameter val_sd1__Debug_Selection = 32'h00000000; +parameter mask_sd1__Debug_Selection = 32'h00000001; + +parameter sd1__SPI_interrupt_support = 32'hE01010F0; +parameter val_sd1__SPI_interrupt_support = 32'h00000000; +parameter mask_sd1__SPI_interrupt_support = 32'h000000FF; + +parameter sd1__Slot_interrupt_status_Host_controller_version = 32'hE01010FC; +parameter val_sd1__Slot_interrupt_status_Host_controller_version = 32'h89010000; +parameter mask_sd1__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; + + +// ************************************************************ +// Module slcr slcr +// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter slcr__SCL = 32'hF8000000; +parameter val_slcr__SCL = 32'h00000000; +parameter mask_slcr__SCL = 32'hFFFFFFFF; + +parameter slcr__SLCR_LOCK = 32'hF8000004; +parameter val_slcr__SLCR_LOCK = 32'h00000000; +parameter mask_slcr__SLCR_LOCK = 32'hFFFFFFFF; + +parameter slcr__SLCR_UNLOCK = 32'hF8000008; +parameter val_slcr__SLCR_UNLOCK = 32'h00000000; +parameter mask_slcr__SLCR_UNLOCK = 32'hFFFFFFFF; + +parameter slcr__SLCR_LOCKSTA = 32'hF800000C; +parameter val_slcr__SLCR_LOCKSTA = 32'h00000001; +parameter mask_slcr__SLCR_LOCKSTA = 32'hFFFFFFFF; + +parameter slcr__ARM_PLL_CTRL = 32'hF8000100; +parameter val_slcr__ARM_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__ARM_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_PLL_CTRL = 32'hF8000104; +parameter val_slcr__DDR_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__DDR_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__IO_PLL_CTRL = 32'hF8000108; +parameter val_slcr__IO_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__IO_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__PLL_STATUS = 32'hF800010C; +parameter val_slcr__PLL_STATUS = 32'h0000003F; +parameter mask_slcr__PLL_STATUS = 32'hFFFFFFFF; + +parameter slcr__ARM_PLL_CFG = 32'hF8000110; +parameter val_slcr__ARM_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__ARM_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__DDR_PLL_CFG = 32'hF8000114; +parameter val_slcr__DDR_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__DDR_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__IO_PLL_CFG = 32'hF8000118; +parameter val_slcr__IO_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__IO_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__PLL_BG_CTRL = 32'hF800011C; +parameter val_slcr__PLL_BG_CTRL = 32'h00000000; +parameter mask_slcr__PLL_BG_CTRL = 32'hFFFFFFFF; + +parameter slcr__ARM_CLK_CTRL = 32'hF8000120; +parameter val_slcr__ARM_CLK_CTRL = 32'h1F000400; +parameter mask_slcr__ARM_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_CLK_CTRL = 32'hF8000124; +parameter val_slcr__DDR_CLK_CTRL = 32'h18400003; +parameter mask_slcr__DDR_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DCI_CLK_CTRL = 32'hF8000128; +parameter val_slcr__DCI_CLK_CTRL = 32'h01E03201; +parameter mask_slcr__DCI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__APER_CLK_CTRL = 32'hF800012C; +parameter val_slcr__APER_CLK_CTRL = 32'h01FFCCCD; +parameter mask_slcr__APER_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB0_CLK_CTRL = 32'hF8000130; +parameter val_slcr__USB0_CLK_CTRL = 32'h00101941; +parameter mask_slcr__USB0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB1_CLK_CTRL = 32'hF8000134; +parameter val_slcr__USB1_CLK_CTRL = 32'h00101941; +parameter mask_slcr__USB1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM0_RCLK_CTRL = 32'hF8000138; +parameter val_slcr__GEM0_RCLK_CTRL = 32'h00000001; +parameter mask_slcr__GEM0_RCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM1_RCLK_CTRL = 32'hF800013C; +parameter val_slcr__GEM1_RCLK_CTRL = 32'h00000001; +parameter mask_slcr__GEM1_RCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM0_CLK_CTRL = 32'hF8000140; +parameter val_slcr__GEM0_CLK_CTRL = 32'h00003C01; +parameter mask_slcr__GEM0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM1_CLK_CTRL = 32'hF8000144; +parameter val_slcr__GEM1_CLK_CTRL = 32'h00003C01; +parameter mask_slcr__GEM1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SMC_CLK_CTRL = 32'hF8000148; +parameter val_slcr__SMC_CLK_CTRL = 32'h00003C21; +parameter mask_slcr__SMC_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__LQSPI_CLK_CTRL = 32'hF800014C; +parameter val_slcr__LQSPI_CLK_CTRL = 32'h00002821; +parameter mask_slcr__LQSPI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SDIO_CLK_CTRL = 32'hF8000150; +parameter val_slcr__SDIO_CLK_CTRL = 32'h00001E03; +parameter mask_slcr__SDIO_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__UART_CLK_CTRL = 32'hF8000154; +parameter val_slcr__UART_CLK_CTRL = 32'h00003F03; +parameter mask_slcr__UART_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SPI_CLK_CTRL = 32'hF8000158; +parameter val_slcr__SPI_CLK_CTRL = 32'h00003F03; +parameter mask_slcr__SPI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_CLK_CTRL = 32'hF800015C; +parameter val_slcr__CAN_CLK_CTRL = 32'h00501903; +parameter mask_slcr__CAN_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_MIOCLK_CTRL = 32'hF8000160; +parameter val_slcr__CAN_MIOCLK_CTRL = 32'h00000000; +parameter mask_slcr__CAN_MIOCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DBG_CLK_CTRL = 32'hF8000164; +parameter val_slcr__DBG_CLK_CTRL = 32'h00000F03; +parameter mask_slcr__DBG_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__PCAP_CLK_CTRL = 32'hF8000168; +parameter val_slcr__PCAP_CLK_CTRL = 32'h00000F01; +parameter mask_slcr__PCAP_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__TOPSW_CLK_CTRL = 32'hF800016C; +parameter val_slcr__TOPSW_CLK_CTRL = 32'h00000000; +parameter mask_slcr__TOPSW_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_CLK_CTRL = 32'hF8000170; +parameter val_slcr__FPGA0_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_CTRL = 32'hF8000174; +parameter val_slcr__FPGA0_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA0_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_CNT = 32'hF8000178; +parameter val_slcr__FPGA0_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA0_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_STA = 32'hF800017C; +parameter val_slcr__FPGA0_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA0_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA1_CLK_CTRL = 32'hF8000180; +parameter val_slcr__FPGA1_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_CTRL = 32'hF8000184; +parameter val_slcr__FPGA1_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA1_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_CNT = 32'hF8000188; +parameter val_slcr__FPGA1_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA1_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_STA = 32'hF800018C; +parameter val_slcr__FPGA1_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA1_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA2_CLK_CTRL = 32'hF8000190; +parameter val_slcr__FPGA2_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA2_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_CTRL = 32'hF8000194; +parameter val_slcr__FPGA2_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA2_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_CNT = 32'hF8000198; +parameter val_slcr__FPGA2_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA2_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_STA = 32'hF800019C; +parameter val_slcr__FPGA2_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA2_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA3_CLK_CTRL = 32'hF80001A0; +parameter val_slcr__FPGA3_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA3_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_CTRL = 32'hF80001A4; +parameter val_slcr__FPGA3_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA3_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_CNT = 32'hF80001A8; +parameter val_slcr__FPGA3_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA3_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_STA = 32'hF80001AC; +parameter val_slcr__FPGA3_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA3_THR_STA = 32'hFFFFFFFF; + +parameter slcr__SRST_UART_CTRL = 32'hF80001B0; +parameter val_slcr__SRST_UART_CTRL = 32'h00000000; +parameter mask_slcr__SRST_UART_CTRL = 32'hFFFFFFFF; + +parameter slcr__BANDGAP_TRIM = 32'hF80001B8; +parameter val_slcr__BANDGAP_TRIM = 32'h0000001F; +parameter mask_slcr__BANDGAP_TRIM = 32'hFFFFFFFF; + +parameter slcr__CC_TEST = 32'hF80001BC; +parameter val_slcr__CC_TEST = 32'h00000000; +parameter mask_slcr__CC_TEST = 32'hFFFFFFFF; + +parameter slcr__PLL_PREDIVISOR = 32'hF80001C0; +parameter val_slcr__PLL_PREDIVISOR = 32'h00000001; +parameter mask_slcr__PLL_PREDIVISOR = 32'hFFFFFFFF; + +parameter slcr__CLK_621_TRUE = 32'hF80001C4; +parameter val_slcr__CLK_621_TRUE = 32'h00000001; +parameter mask_slcr__CLK_621_TRUE = 32'hFFFFFFC1; + +parameter slcr__PICTURE_DBG = 32'hF80001D0; +parameter val_slcr__PICTURE_DBG = 32'h00000000; +parameter mask_slcr__PICTURE_DBG = 32'hFFFFFFFF; + +parameter slcr__PICTURE_DBG_UCNT = 32'hF80001D4; +parameter val_slcr__PICTURE_DBG_UCNT = 32'h00000000; +parameter mask_slcr__PICTURE_DBG_UCNT = 32'hFFFFFFFF; + +parameter slcr__PICTURE_DBG_LCNT = 32'hF80001D8; +parameter val_slcr__PICTURE_DBG_LCNT = 32'h00000000; +parameter mask_slcr__PICTURE_DBG_LCNT = 32'hFFFFFFFF; + +parameter slcr__PSS_RST_CTRL = 32'hF8000200; +parameter val_slcr__PSS_RST_CTRL = 32'h00000000; +parameter mask_slcr__PSS_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_RST_CTRL = 32'hF8000204; +parameter val_slcr__DDR_RST_CTRL = 32'h00000000; +parameter mask_slcr__DDR_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__TOPSW_RST_CTRL = 32'hF8000208; +parameter val_slcr__TOPSW_RST_CTRL = 32'h00000000; +parameter mask_slcr__TOPSW_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DMAC_RST_CTRL = 32'hF800020C; +parameter val_slcr__DMAC_RST_CTRL = 32'h00000000; +parameter mask_slcr__DMAC_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB_RST_CTRL = 32'hF8000210; +parameter val_slcr__USB_RST_CTRL = 32'h00000000; +parameter mask_slcr__USB_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM_RST_CTRL = 32'hF8000214; +parameter val_slcr__GEM_RST_CTRL = 32'h00000000; +parameter mask_slcr__GEM_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SDIO_RST_CTRL = 32'hF8000218; +parameter val_slcr__SDIO_RST_CTRL = 32'h00000000; +parameter mask_slcr__SDIO_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SPI_RST_CTRL = 32'hF800021C; +parameter val_slcr__SPI_RST_CTRL = 32'h00000000; +parameter mask_slcr__SPI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_RST_CTRL = 32'hF8000220; +parameter val_slcr__CAN_RST_CTRL = 32'h00000000; +parameter mask_slcr__CAN_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__I2C_RST_CTRL = 32'hF8000224; +parameter val_slcr__I2C_RST_CTRL = 32'h00000000; +parameter mask_slcr__I2C_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__UART_RST_CTRL = 32'hF8000228; +parameter val_slcr__UART_RST_CTRL = 32'h00000000; +parameter mask_slcr__UART_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__GPIO_RST_CTRL = 32'hF800022C; +parameter val_slcr__GPIO_RST_CTRL = 32'h00000000; +parameter mask_slcr__GPIO_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__LQSPI_RST_CTRL = 32'hF8000230; +parameter val_slcr__LQSPI_RST_CTRL = 32'h00000000; +parameter mask_slcr__LQSPI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SMC_RST_CTRL = 32'hF8000234; +parameter val_slcr__SMC_RST_CTRL = 32'h00000000; +parameter mask_slcr__SMC_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__OCM_RST_CTRL = 32'hF8000238; +parameter val_slcr__OCM_RST_CTRL = 32'h00000000; +parameter mask_slcr__OCM_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DEVCI_RST_CTRL = 32'hF800023C; +parameter val_slcr__DEVCI_RST_CTRL = 32'h00000000; +parameter mask_slcr__DEVCI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA_RST_CTRL = 32'hF8000240; +parameter val_slcr__FPGA_RST_CTRL = 32'h01F33F0F; +parameter mask_slcr__FPGA_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__A9_CPU_RST_CTRL = 32'hF8000244; +parameter val_slcr__A9_CPU_RST_CTRL = 32'h00000000; +parameter mask_slcr__A9_CPU_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__RS_AWDT_CTRL = 32'hF800024C; +parameter val_slcr__RS_AWDT_CTRL = 32'h00000000; +parameter mask_slcr__RS_AWDT_CTRL = 32'hFFFFFFFF; + +parameter slcr__RST_REASON = 32'hF8000250; +parameter val_slcr__RST_REASON = 32'h00000040; +parameter mask_slcr__RST_REASON = 32'hFFFFFFFF; + +parameter slcr__RST_REASON_CLR = 32'hF8000254; +parameter val_slcr__RST_REASON_CLR = 32'h00000000; +parameter mask_slcr__RST_REASON_CLR = 32'hFFFFFFFF; + +parameter slcr__REBOOT_STATUS = 32'hF8000258; +parameter val_slcr__REBOOT_STATUS = 32'h00400000; +parameter mask_slcr__REBOOT_STATUS = 32'hFFFFFFFF; + +parameter slcr__BOOT_MODE = 32'hF800025C; +parameter val_slcr__BOOT_MODE = 32'h00000000; +parameter mask_slcr__BOOT_MODE = 32'hFFFFFFF0; + +parameter slcr__APU_CTRL = 32'hF8000300; +parameter val_slcr__APU_CTRL = 32'h00000000; +parameter mask_slcr__APU_CTRL = 32'hFFFFFFFF; + +parameter slcr__WDT_CLK_SEL = 32'hF8000304; +parameter val_slcr__WDT_CLK_SEL = 32'h00000000; +parameter mask_slcr__WDT_CLK_SEL = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_RAM0 = 32'hF8000400; +parameter val_slcr__TZ_OCM_RAM0 = 32'h00000000; +parameter mask_slcr__TZ_OCM_RAM0 = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_RAM1 = 32'hF8000404; +parameter val_slcr__TZ_OCM_RAM1 = 32'h00000000; +parameter mask_slcr__TZ_OCM_RAM1 = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_ROM = 32'hF8000408; +parameter val_slcr__TZ_OCM_ROM = 32'h00000000; +parameter mask_slcr__TZ_OCM_ROM = 32'hFFFFFFFF; + +parameter slcr__TZ_DDR_RAM = 32'hF8000430; +parameter val_slcr__TZ_DDR_RAM = 32'h00000000; +parameter mask_slcr__TZ_DDR_RAM = 32'h00000001; + +parameter slcr__TZ_DMA_NS = 32'hF8000440; +parameter val_slcr__TZ_DMA_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_DMA_IRQ_NS = 32'hF8000444; +parameter val_slcr__TZ_DMA_IRQ_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_IRQ_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_DMA_PERIPH_NS = 32'hF8000448; +parameter val_slcr__TZ_DMA_PERIPH_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_PERIPH_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_GEM = 32'hF8000450; +parameter val_slcr__TZ_GEM = 32'h00000000; +parameter mask_slcr__TZ_GEM = 32'hFFFFFFFF; + +parameter slcr__TZ_SDIO = 32'hF8000454; +parameter val_slcr__TZ_SDIO = 32'h00000000; +parameter mask_slcr__TZ_SDIO = 32'hFFFFFFFF; + +parameter slcr__TZ_USB = 32'hF8000458; +parameter val_slcr__TZ_USB = 32'h00000000; +parameter mask_slcr__TZ_USB = 32'hFFFFFFFF; + +parameter slcr__TZ_FPGA_M = 32'hF8000484; +parameter val_slcr__TZ_FPGA_M = 32'h00000000; +parameter mask_slcr__TZ_FPGA_M = 32'hFFFFFFFF; + +parameter slcr__TZ_FPGA_AFI = 32'hF8000488; +parameter val_slcr__TZ_FPGA_AFI = 32'h00000000; +parameter mask_slcr__TZ_FPGA_AFI = 32'hFFFFFFFF; + +parameter slcr__DBG_CTRL = 32'hF8000500; +parameter val_slcr__DBG_CTRL = 32'h00000000; +parameter mask_slcr__DBG_CTRL = 32'hFFFFFFFF; + +parameter slcr__PSS_IDCODE = 32'hF8000530; +parameter val_slcr__PSS_IDCODE = 32'h03720093; +parameter mask_slcr__PSS_IDCODE = 32'h0FFE0FFF; + +parameter slcr__DDR_URGENT = 32'hF8000600; +parameter val_slcr__DDR_URGENT = 32'h00000000; +parameter mask_slcr__DDR_URGENT = 32'hFFFFFFFF; + +parameter slcr__DDR_CAL_START = 32'hF800060C; +parameter val_slcr__DDR_CAL_START = 32'h00000000; +parameter mask_slcr__DDR_CAL_START = 32'hFFFFFFFF; + +parameter slcr__DDR_REF_START = 32'hF8000614; +parameter val_slcr__DDR_REF_START = 32'h00000000; +parameter mask_slcr__DDR_REF_START = 32'hFFFFFFFF; + +parameter slcr__DDR_CMD_STA = 32'hF8000618; +parameter val_slcr__DDR_CMD_STA = 32'h00000000; +parameter mask_slcr__DDR_CMD_STA = 32'hFFFFFFFF; + +parameter slcr__DDR_URGENT_SEL = 32'hF800061C; +parameter val_slcr__DDR_URGENT_SEL = 32'h00000000; +parameter mask_slcr__DDR_URGENT_SEL = 32'hFFFFFFFF; + +parameter slcr__DDR_DFI_STATUS = 32'hF8000620; +parameter val_slcr__DDR_DFI_STATUS = 32'h00000000; +parameter mask_slcr__DDR_DFI_STATUS = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_00 = 32'hF8000700; +parameter val_slcr__MIO_PIN_00 = 32'h00001601; +parameter mask_slcr__MIO_PIN_00 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_01 = 32'hF8000704; +parameter val_slcr__MIO_PIN_01 = 32'h00001601; +parameter mask_slcr__MIO_PIN_01 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_02 = 32'hF8000708; +parameter val_slcr__MIO_PIN_02 = 32'h00000601; +parameter mask_slcr__MIO_PIN_02 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_03 = 32'hF800070C; +parameter val_slcr__MIO_PIN_03 = 32'h00000601; +parameter mask_slcr__MIO_PIN_03 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_04 = 32'hF8000710; +parameter val_slcr__MIO_PIN_04 = 32'h00000601; +parameter mask_slcr__MIO_PIN_04 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_05 = 32'hF8000714; +parameter val_slcr__MIO_PIN_05 = 32'h00000601; +parameter mask_slcr__MIO_PIN_05 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_06 = 32'hF8000718; +parameter val_slcr__MIO_PIN_06 = 32'h00000601; +parameter mask_slcr__MIO_PIN_06 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_07 = 32'hF800071C; +parameter val_slcr__MIO_PIN_07 = 32'h00000601; +parameter mask_slcr__MIO_PIN_07 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_08 = 32'hF8000720; +parameter val_slcr__MIO_PIN_08 = 32'h00000601; +parameter mask_slcr__MIO_PIN_08 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_09 = 32'hF8000724; +parameter val_slcr__MIO_PIN_09 = 32'h00001601; +parameter mask_slcr__MIO_PIN_09 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_10 = 32'hF8000728; +parameter val_slcr__MIO_PIN_10 = 32'h00001601; +parameter mask_slcr__MIO_PIN_10 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_11 = 32'hF800072C; +parameter val_slcr__MIO_PIN_11 = 32'h00001601; +parameter mask_slcr__MIO_PIN_11 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_12 = 32'hF8000730; +parameter val_slcr__MIO_PIN_12 = 32'h00001601; +parameter mask_slcr__MIO_PIN_12 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_13 = 32'hF8000734; +parameter val_slcr__MIO_PIN_13 = 32'h00001601; +parameter mask_slcr__MIO_PIN_13 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_14 = 32'hF8000738; +parameter val_slcr__MIO_PIN_14 = 32'h00001601; +parameter mask_slcr__MIO_PIN_14 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_15 = 32'hF800073C; +parameter val_slcr__MIO_PIN_15 = 32'h00001601; +parameter mask_slcr__MIO_PIN_15 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_16 = 32'hF8000740; +parameter val_slcr__MIO_PIN_16 = 32'h00001601; +parameter mask_slcr__MIO_PIN_16 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_17 = 32'hF8000744; +parameter val_slcr__MIO_PIN_17 = 32'h00001601; +parameter mask_slcr__MIO_PIN_17 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_18 = 32'hF8000748; +parameter val_slcr__MIO_PIN_18 = 32'h00001601; +parameter mask_slcr__MIO_PIN_18 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_19 = 32'hF800074C; +parameter val_slcr__MIO_PIN_19 = 32'h00001601; +parameter mask_slcr__MIO_PIN_19 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_20 = 32'hF8000750; +parameter val_slcr__MIO_PIN_20 = 32'h00001601; +parameter mask_slcr__MIO_PIN_20 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_21 = 32'hF8000754; +parameter val_slcr__MIO_PIN_21 = 32'h00001601; +parameter mask_slcr__MIO_PIN_21 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_22 = 32'hF8000758; +parameter val_slcr__MIO_PIN_22 = 32'h00001601; +parameter mask_slcr__MIO_PIN_22 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_23 = 32'hF800075C; +parameter val_slcr__MIO_PIN_23 = 32'h00001601; +parameter mask_slcr__MIO_PIN_23 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_24 = 32'hF8000760; +parameter val_slcr__MIO_PIN_24 = 32'h00001601; +parameter mask_slcr__MIO_PIN_24 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_25 = 32'hF8000764; +parameter val_slcr__MIO_PIN_25 = 32'h00001601; +parameter mask_slcr__MIO_PIN_25 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_26 = 32'hF8000768; +parameter val_slcr__MIO_PIN_26 = 32'h00001601; +parameter mask_slcr__MIO_PIN_26 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_27 = 32'hF800076C; +parameter val_slcr__MIO_PIN_27 = 32'h00001601; +parameter mask_slcr__MIO_PIN_27 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_28 = 32'hF8000770; +parameter val_slcr__MIO_PIN_28 = 32'h00001601; +parameter mask_slcr__MIO_PIN_28 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_29 = 32'hF8000774; +parameter val_slcr__MIO_PIN_29 = 32'h00001601; +parameter mask_slcr__MIO_PIN_29 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_30 = 32'hF8000778; +parameter val_slcr__MIO_PIN_30 = 32'h00001601; +parameter mask_slcr__MIO_PIN_30 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_31 = 32'hF800077C; +parameter val_slcr__MIO_PIN_31 = 32'h00001601; +parameter mask_slcr__MIO_PIN_31 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_32 = 32'hF8000780; +parameter val_slcr__MIO_PIN_32 = 32'h00001601; +parameter mask_slcr__MIO_PIN_32 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_33 = 32'hF8000784; +parameter val_slcr__MIO_PIN_33 = 32'h00001601; +parameter mask_slcr__MIO_PIN_33 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_34 = 32'hF8000788; +parameter val_slcr__MIO_PIN_34 = 32'h00001601; +parameter mask_slcr__MIO_PIN_34 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_35 = 32'hF800078C; +parameter val_slcr__MIO_PIN_35 = 32'h00001601; +parameter mask_slcr__MIO_PIN_35 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_36 = 32'hF8000790; +parameter val_slcr__MIO_PIN_36 = 32'h00001601; +parameter mask_slcr__MIO_PIN_36 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_37 = 32'hF8000794; +parameter val_slcr__MIO_PIN_37 = 32'h00001601; +parameter mask_slcr__MIO_PIN_37 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_38 = 32'hF8000798; +parameter val_slcr__MIO_PIN_38 = 32'h00001601; +parameter mask_slcr__MIO_PIN_38 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_39 = 32'hF800079C; +parameter val_slcr__MIO_PIN_39 = 32'h00001601; +parameter mask_slcr__MIO_PIN_39 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_40 = 32'hF80007A0; +parameter val_slcr__MIO_PIN_40 = 32'h00001601; +parameter mask_slcr__MIO_PIN_40 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_41 = 32'hF80007A4; +parameter val_slcr__MIO_PIN_41 = 32'h00001601; +parameter mask_slcr__MIO_PIN_41 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_42 = 32'hF80007A8; +parameter val_slcr__MIO_PIN_42 = 32'h00001601; +parameter mask_slcr__MIO_PIN_42 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_43 = 32'hF80007AC; +parameter val_slcr__MIO_PIN_43 = 32'h00001601; +parameter mask_slcr__MIO_PIN_43 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_44 = 32'hF80007B0; +parameter val_slcr__MIO_PIN_44 = 32'h00001601; +parameter mask_slcr__MIO_PIN_44 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_45 = 32'hF80007B4; +parameter val_slcr__MIO_PIN_45 = 32'h00001601; +parameter mask_slcr__MIO_PIN_45 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_46 = 32'hF80007B8; +parameter val_slcr__MIO_PIN_46 = 32'h00001601; +parameter mask_slcr__MIO_PIN_46 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_47 = 32'hF80007BC; +parameter val_slcr__MIO_PIN_47 = 32'h00001601; +parameter mask_slcr__MIO_PIN_47 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_48 = 32'hF80007C0; +parameter val_slcr__MIO_PIN_48 = 32'h00001601; +parameter mask_slcr__MIO_PIN_48 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_49 = 32'hF80007C4; +parameter val_slcr__MIO_PIN_49 = 32'h00001601; +parameter mask_slcr__MIO_PIN_49 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_50 = 32'hF80007C8; +parameter val_slcr__MIO_PIN_50 = 32'h00001601; +parameter mask_slcr__MIO_PIN_50 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_51 = 32'hF80007CC; +parameter val_slcr__MIO_PIN_51 = 32'h00001601; +parameter mask_slcr__MIO_PIN_51 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_52 = 32'hF80007D0; +parameter val_slcr__MIO_PIN_52 = 32'h00001601; +parameter mask_slcr__MIO_PIN_52 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_53 = 32'hF80007D4; +parameter val_slcr__MIO_PIN_53 = 32'h00001601; +parameter mask_slcr__MIO_PIN_53 = 32'hFFFFFFFF; + +parameter slcr__MIO_FMIO_GEM_SEL = 32'hF8000800; +parameter val_slcr__MIO_FMIO_GEM_SEL = 32'h00000000; +parameter mask_slcr__MIO_FMIO_GEM_SEL = 32'hFFFFFFFF; + +parameter slcr__MIO_LOOPBACK = 32'hF8000804; +parameter val_slcr__MIO_LOOPBACK = 32'h00000000; +parameter mask_slcr__MIO_LOOPBACK = 32'hFFFFFFFF; + +parameter slcr__MIO_MST_TRI0 = 32'hF800080C; +parameter val_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; +parameter mask_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; + +parameter slcr__MIO_MST_TRI1 = 32'hF8000810; +parameter val_slcr__MIO_MST_TRI1 = 32'h003FFFFF; +parameter mask_slcr__MIO_MST_TRI1 = 32'hFFFFFFFF; + +parameter slcr__SD0_WP_CD_SEL = 32'hF8000830; +parameter val_slcr__SD0_WP_CD_SEL = 32'h00000000; +parameter mask_slcr__SD0_WP_CD_SEL = 32'hFFFFFFFF; + +parameter slcr__SD1_WP_CD_SEL = 32'hF8000834; +parameter val_slcr__SD1_WP_CD_SEL = 32'h00000000; +parameter mask_slcr__SD1_WP_CD_SEL = 32'hFFFFFFFF; + +parameter slcr__LVL_SHFTR_EN = 32'hF8000900; +parameter val_slcr__LVL_SHFTR_EN = 32'h00000000; +parameter mask_slcr__LVL_SHFTR_EN = 32'hFFFFFFFF; + +parameter slcr__OCM_CFG = 32'hF8000910; +parameter val_slcr__OCM_CFG = 32'h00000000; +parameter mask_slcr__OCM_CFG = 32'hFFFFFFFF; + +parameter slcr__CPU0_RAM0 = 32'hF8000A00; +parameter val_slcr__CPU0_RAM0 = 32'h00020202; +parameter mask_slcr__CPU0_RAM0 = 32'h00FFFFFF; + +parameter slcr__CPU0_RAM1 = 32'hF8000A04; +parameter val_slcr__CPU0_RAM1 = 32'h00020202; +parameter mask_slcr__CPU0_RAM1 = 32'h00FFFFFF; + +parameter slcr__CPU0_RAM2 = 32'hF8000A08; +parameter val_slcr__CPU0_RAM2 = 32'h02020202; +parameter mask_slcr__CPU0_RAM2 = 32'hFFFFFFFF; + +parameter slcr__CPU1_RAM0 = 32'hF8000A0C; +parameter val_slcr__CPU1_RAM0 = 32'h00020202; +parameter mask_slcr__CPU1_RAM0 = 32'h00FFFFFF; + +parameter slcr__CPU1_RAM1 = 32'hF8000A10; +parameter val_slcr__CPU1_RAM1 = 32'h00020202; +parameter mask_slcr__CPU1_RAM1 = 32'h00FFFFFF; + +parameter slcr__CPU1_RAM2 = 32'hF8000A14; +parameter val_slcr__CPU1_RAM2 = 32'h02020202; +parameter mask_slcr__CPU1_RAM2 = 32'hFFFFFFFF; + +parameter slcr__SCU_RAM = 32'hF8000A18; +parameter val_slcr__SCU_RAM = 32'h00000002; +parameter mask_slcr__SCU_RAM = 32'h000000FF; + +parameter slcr__L2C_RAM = 32'hF8000A1C; +parameter val_slcr__L2C_RAM = 32'h00020202; +parameter mask_slcr__L2C_RAM = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_GEM01 = 32'hF8000A30; +parameter val_slcr__IOU_RAM_GEM01 = 32'h09090909; +parameter mask_slcr__IOU_RAM_GEM01 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_USB01 = 32'hF8000A34; +parameter val_slcr__IOU_RAM_USB01 = 32'h09090909; +parameter mask_slcr__IOU_RAM_USB01 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_SDIO0 = 32'hF8000A38; +parameter val_slcr__IOU_RAM_SDIO0 = 32'h09090909; +parameter mask_slcr__IOU_RAM_SDIO0 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_SDIO1 = 32'hF8000A3C; +parameter val_slcr__IOU_RAM_SDIO1 = 32'h09090909; +parameter mask_slcr__IOU_RAM_SDIO1 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_CAN0 = 32'hF8000A40; +parameter val_slcr__IOU_RAM_CAN0 = 32'h00090909; +parameter mask_slcr__IOU_RAM_CAN0 = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_CAN1 = 32'hF8000A44; +parameter val_slcr__IOU_RAM_CAN1 = 32'h00090909; +parameter mask_slcr__IOU_RAM_CAN1 = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_LQSPI = 32'hF8000A48; +parameter val_slcr__IOU_RAM_LQSPI = 32'h00000909; +parameter mask_slcr__IOU_RAM_LQSPI = 32'h0000FFFF; + +parameter slcr__DMAC_RAM = 32'hF8000A50; +parameter val_slcr__DMAC_RAM = 32'h00000009; +parameter mask_slcr__DMAC_RAM = 32'h000000FF; + +parameter slcr__AFI0_RAM0 = 32'hF8000A60; +parameter val_slcr__AFI0_RAM0 = 32'h09090909; +parameter mask_slcr__AFI0_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI0_RAM1 = 32'hF8000A64; +parameter val_slcr__AFI0_RAM1 = 32'h09090909; +parameter mask_slcr__AFI0_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI0_RAM2 = 32'hF8000A68; +parameter val_slcr__AFI0_RAM2 = 32'h00000909; +parameter mask_slcr__AFI0_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI1_RAM0 = 32'hF8000A6C; +parameter val_slcr__AFI1_RAM0 = 32'h09090909; +parameter mask_slcr__AFI1_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI1_RAM1 = 32'hF8000A70; +parameter val_slcr__AFI1_RAM1 = 32'h09090909; +parameter mask_slcr__AFI1_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI1_RAM2 = 32'hF8000A74; +parameter val_slcr__AFI1_RAM2 = 32'h00000909; +parameter mask_slcr__AFI1_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI2_RAM0 = 32'hF8000A78; +parameter val_slcr__AFI2_RAM0 = 32'h09090909; +parameter mask_slcr__AFI2_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI2_RAM1 = 32'hF8000A7C; +parameter val_slcr__AFI2_RAM1 = 32'h09090909; +parameter mask_slcr__AFI2_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI2_RAM2 = 32'hF8000A80; +parameter val_slcr__AFI2_RAM2 = 32'h00000909; +parameter mask_slcr__AFI2_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI3_RAM0 = 32'hF8000A84; +parameter val_slcr__AFI3_RAM0 = 32'h09090909; +parameter mask_slcr__AFI3_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI3_RAM1 = 32'hF8000A88; +parameter val_slcr__AFI3_RAM1 = 32'h09090909; +parameter mask_slcr__AFI3_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI3_RAM2 = 32'hF8000A8C; +parameter val_slcr__AFI3_RAM2 = 32'h00000909; +parameter mask_slcr__AFI3_RAM2 = 32'h0000FFFF; + +parameter slcr__OCM_RAM = 32'hF8000A90; +parameter val_slcr__OCM_RAM = 32'h01010101; +parameter mask_slcr__OCM_RAM = 32'hFFFFFFFF; + +parameter slcr__OCM_ROM0 = 32'hF8000A94; +parameter val_slcr__OCM_ROM0 = 32'h09090909; +parameter mask_slcr__OCM_ROM0 = 32'hFFFFFFFF; + +parameter slcr__OCM_ROM1 = 32'hF8000A98; +parameter val_slcr__OCM_ROM1 = 32'h09090909; +parameter mask_slcr__OCM_ROM1 = 32'hFFFFFFFF; + +parameter slcr__DEVCI_RAM = 32'hF8000AA0; +parameter val_slcr__DEVCI_RAM = 32'h00000909; +parameter mask_slcr__DEVCI_RAM = 32'h0000FFFF; + +parameter slcr__CSG_RAM = 32'hF8000AB0; +parameter val_slcr__CSG_RAM = 32'h00000001; +parameter mask_slcr__CSG_RAM = 32'h000000FF; + +parameter slcr__GPIOB_CTRL = 32'hF8000B00; +parameter val_slcr__GPIOB_CTRL = 32'h00000000; +parameter mask_slcr__GPIOB_CTRL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS18 = 32'hF8000B04; +parameter val_slcr__GPIOB_CFG_CMOS18 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS18 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS25 = 32'hF8000B08; +parameter val_slcr__GPIOB_CFG_CMOS25 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS25 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS33 = 32'hF8000B0C; +parameter val_slcr__GPIOB_CFG_CMOS33 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS33 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_LVTTL = 32'hF8000B10; +parameter val_slcr__GPIOB_CFG_LVTTL = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_LVTTL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_HSTL = 32'hF8000B14; +parameter val_slcr__GPIOB_CFG_HSTL = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_HSTL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_DRVR_BIAS_CTRL = 32'hF8000B18; +parameter val_slcr__GPIOB_DRVR_BIAS_CTRL = 32'h00000000; +parameter mask_slcr__GPIOB_DRVR_BIAS_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_ADDR0 = 32'hF8000B40; +parameter val_slcr__DDRIOB_ADDR0 = 32'h00000800; +parameter mask_slcr__DDRIOB_ADDR0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_ADDR1 = 32'hF8000B44; +parameter val_slcr__DDRIOB_ADDR1 = 32'h00000800; +parameter mask_slcr__DDRIOB_ADDR1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DATA0 = 32'hF8000B48; +parameter val_slcr__DDRIOB_DATA0 = 32'h00000800; +parameter mask_slcr__DDRIOB_DATA0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DATA1 = 32'hF8000B4C; +parameter val_slcr__DDRIOB_DATA1 = 32'h00000800; +parameter mask_slcr__DDRIOB_DATA1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DIFF0 = 32'hF8000B50; +parameter val_slcr__DDRIOB_DIFF0 = 32'h00000800; +parameter mask_slcr__DDRIOB_DIFF0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DIFF1 = 32'hF8000B54; +parameter val_slcr__DDRIOB_DIFF1 = 32'h00000800; +parameter mask_slcr__DDRIOB_DIFF1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_CLOCK = 32'hF8000B58; +parameter val_slcr__DDRIOB_CLOCK = 32'h00000800; +parameter mask_slcr__DDRIOB_CLOCK = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hF8000B5C; +parameter val_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hF8000B60; +parameter val_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hF8000B64; +parameter val_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hF8000B68; +parameter val_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DDR_CTRL = 32'hF8000B6C; +parameter val_slcr__DDRIOB_DDR_CTRL = 32'h00000000; +parameter mask_slcr__DDRIOB_DDR_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DCI_CTRL = 32'hF8000B70; +parameter val_slcr__DDRIOB_DCI_CTRL = 32'h00000020; +parameter mask_slcr__DDRIOB_DCI_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DCI_STATUS = 32'hF8000B74; +parameter val_slcr__DDRIOB_DCI_STATUS = 32'h00000000; +parameter mask_slcr__DDRIOB_DCI_STATUS = 32'hFFFFFFFF; + + +// ************************************************************ +// Module smcc pl353 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter smcc__memc_status = 32'hE000E000; +parameter val_smcc__memc_status = 32'h00000000; +parameter mask_smcc__memc_status = 32'h00001FFF; + +parameter smcc__memif_cfg = 32'hE000E004; +parameter val_smcc__memif_cfg = 32'h00011205; +parameter mask_smcc__memif_cfg = 32'h0003FFFF; + +parameter smcc__memc_cfg_set = 32'hE000E008; +parameter val_smcc__memc_cfg_set = 32'h00000000; +parameter mask_smcc__memc_cfg_set = 32'h00000000; + +parameter smcc__memc_cfg_clr = 32'hE000E00C; +parameter val_smcc__memc_cfg_clr = 32'h00000000; +parameter mask_smcc__memc_cfg_clr = 32'h00000000; + +parameter smcc__direct_cmd = 32'hE000E010; +parameter val_smcc__direct_cmd = 32'h00000000; +parameter mask_smcc__direct_cmd = 32'h00000000; + +parameter smcc__set_cycles = 32'hE000E014; +parameter val_smcc__set_cycles = 32'h00000000; +parameter mask_smcc__set_cycles = 32'h00000000; + +parameter smcc__set_opmode = 32'hE000E018; +parameter val_smcc__set_opmode = 32'h00000000; +parameter mask_smcc__set_opmode = 32'h00000000; + +parameter smcc__refresh_period_0 = 32'hE000E020; +parameter val_smcc__refresh_period_0 = 32'h00000000; +parameter mask_smcc__refresh_period_0 = 32'h0000000F; + +parameter smcc__refresh_period_1 = 32'hE000E024; +parameter val_smcc__refresh_period_1 = 32'h00000000; +parameter mask_smcc__refresh_period_1 = 32'h0000000F; + +parameter smcc__sram_cycles0_0 = 32'hE000E100; +parameter val_smcc__sram_cycles0_0 = 32'h0002B3CC; +parameter mask_smcc__sram_cycles0_0 = 32'h001FFFFF; + +parameter smcc__opmode0_0 = 32'hE000E104; +parameter val_smcc__opmode0_0 = 32'hE2FE0800; +parameter mask_smcc__opmode0_0 = 32'hFFFFFFFF; + +parameter smcc__sram_cycles0_1 = 32'hE000E120; +parameter val_smcc__sram_cycles0_1 = 32'h0002B3CC; +parameter mask_smcc__sram_cycles0_1 = 32'h001FFFFF; + +parameter smcc__opmode0_1 = 32'hE000E124; +parameter val_smcc__opmode0_1 = 32'hE4FE0800; +parameter mask_smcc__opmode0_1 = 32'hFFFFFFFF; + +parameter smcc__nand_cycles1_0 = 32'hE000E180; +parameter val_smcc__nand_cycles1_0 = 32'h0024ABCC; +parameter mask_smcc__nand_cycles1_0 = 32'h00FFFFFF; + +parameter smcc__opmode1_0 = 32'hE000E184; +parameter val_smcc__opmode1_0 = 32'hE1FF0001; +parameter mask_smcc__opmode1_0 = 32'hFFFFFFFF; + +parameter smcc__user_status = 32'hE000E200; +parameter val_smcc__user_status = 32'h00000000; +parameter mask_smcc__user_status = 32'h000000FF; + +parameter smcc__user_config = 32'hE000E204; +parameter val_smcc__user_config = 32'h00000000; +parameter mask_smcc__user_config = 32'h00000000; + +parameter smcc__ecc_status_0 = 32'hE000E300; +parameter val_smcc__ecc_status_0 = 32'h00000000; +parameter mask_smcc__ecc_status_0 = 32'h3FFFFFFF; + +parameter smcc__ecc_memcfg_0 = 32'hE000E304; +parameter val_smcc__ecc_memcfg_0 = 32'h00000000; +parameter mask_smcc__ecc_memcfg_0 = 32'h00001FFF; + +parameter smcc__ecc_memcommand1_0 = 32'hE000E308; +parameter val_smcc__ecc_memcommand1_0 = 32'h00000000; +parameter mask_smcc__ecc_memcommand1_0 = 32'h01FFFFFF; + +parameter smcc__ecc_memcommand2_0 = 32'hE000E30C; +parameter val_smcc__ecc_memcommand2_0 = 32'h00000000; +parameter mask_smcc__ecc_memcommand2_0 = 32'h01FFFFFF; + +parameter smcc__ecc_addr0_0 = 32'hE000E310; +parameter val_smcc__ecc_addr0_0 = 32'h00000000; +parameter mask_smcc__ecc_addr0_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_addr1_0 = 32'hE000E314; +parameter val_smcc__ecc_addr1_0 = 32'h00000000; +parameter mask_smcc__ecc_addr1_0 = 32'h00FFFFFF; + +parameter smcc__ecc_value0_0 = 32'hE000E318; +parameter val_smcc__ecc_value0_0 = 32'h00000000; +parameter mask_smcc__ecc_value0_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value1_0 = 32'hE000E31C; +parameter val_smcc__ecc_value1_0 = 32'h00000000; +parameter mask_smcc__ecc_value1_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value2_0 = 32'hE000E320; +parameter val_smcc__ecc_value2_0 = 32'h00000000; +parameter mask_smcc__ecc_value2_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value3_0 = 32'hE000E324; +parameter val_smcc__ecc_value3_0 = 32'h00000000; +parameter mask_smcc__ecc_value3_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_status_1 = 32'hE000E400; +parameter val_smcc__ecc_status_1 = 32'h00000000; +parameter mask_smcc__ecc_status_1 = 32'h3FFFFFFF; + +parameter smcc__ecc_memcfg_1 = 32'hE000E404; +parameter val_smcc__ecc_memcfg_1 = 32'h00000043; +parameter mask_smcc__ecc_memcfg_1 = 32'h00001FFF; + +parameter smcc__ecc_memcommand1_1 = 32'hE000E408; +parameter val_smcc__ecc_memcommand1_1 = 32'h01300080; +parameter mask_smcc__ecc_memcommand1_1 = 32'h01FFFFFF; + +parameter smcc__ecc_memcommand2_1 = 32'hE000E40C; +parameter val_smcc__ecc_memcommand2_1 = 32'h01E00585; +parameter mask_smcc__ecc_memcommand2_1 = 32'h01FFFFFF; + +parameter smcc__ecc_addr0_1 = 32'hE000E410; +parameter val_smcc__ecc_addr0_1 = 32'h00000000; +parameter mask_smcc__ecc_addr0_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_addr1_1 = 32'hE000E414; +parameter val_smcc__ecc_addr1_1 = 32'h00000000; +parameter mask_smcc__ecc_addr1_1 = 32'h00FFFFFF; + +parameter smcc__ecc_value0_1 = 32'hE000E418; +parameter val_smcc__ecc_value0_1 = 32'h00000000; +parameter mask_smcc__ecc_value0_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value1_1 = 32'hE000E41C; +parameter val_smcc__ecc_value1_1 = 32'h00000000; +parameter mask_smcc__ecc_value1_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value2_1 = 32'hE000E420; +parameter val_smcc__ecc_value2_1 = 32'h00000000; +parameter mask_smcc__ecc_value2_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value3_1 = 32'hE000E424; +parameter val_smcc__ecc_value3_1 = 32'h00000000; +parameter mask_smcc__ecc_value3_1 = 32'hFFFFFFFF; + +parameter smcc__integration_test = 32'hE000EE00; +parameter val_smcc__integration_test = 32'h00000000; +parameter mask_smcc__integration_test = 32'hFFFFFFFF; + +parameter smcc__periph_id_0 = 32'hE000EFE0; +parameter val_smcc__periph_id_0 = 32'h00000053; +parameter mask_smcc__periph_id_0 = 32'h000000FF; + +parameter smcc__periph_id_1 = 32'hE000EFE4; +parameter val_smcc__periph_id_1 = 32'h00000013; +parameter mask_smcc__periph_id_1 = 32'h000000FF; + +parameter smcc__periph_id_2 = 32'hE000EFE8; +parameter val_smcc__periph_id_2 = 32'h00000054; +parameter mask_smcc__periph_id_2 = 32'h000000FF; + +parameter smcc__periph_id_3 = 32'hE000EFEC; +parameter val_smcc__periph_id_3 = 32'h00000000; +parameter mask_smcc__periph_id_3 = 32'h00000001; + +parameter smcc__pcell_id_0 = 32'hE000EFF0; +parameter val_smcc__pcell_id_0 = 32'h0000000D; +parameter mask_smcc__pcell_id_0 = 32'h000000FF; + +parameter smcc__pcell_id_1 = 32'hE000EFF4; +parameter val_smcc__pcell_id_1 = 32'h000000F0; +parameter mask_smcc__pcell_id_1 = 32'h000000FF; + +parameter smcc__pcell_id_2 = 32'hE000EFF8; +parameter val_smcc__pcell_id_2 = 32'h00000005; +parameter mask_smcc__pcell_id_2 = 32'h000000FF; + +parameter smcc__pcell_id_3 = 32'hE000EFFC; +parameter val_smcc__pcell_id_3 = 32'h000000B1; +parameter mask_smcc__pcell_id_3 = 32'h000000FF; + + +// ************************************************************ +// Module spi0 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter spi0__Config_reg0 = 32'hE0006000; +parameter val_spi0__Config_reg0 = 32'h00020000; +parameter mask_spi0__Config_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intr_status_reg0 = 32'hE0006004; +parameter val_spi0__Intr_status_reg0 = 32'h00000004; +parameter mask_spi0__Intr_status_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_en_reg0 = 32'hE0006008; +parameter val_spi0__Intrpt_en_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_dis_reg0 = 32'hE000600C; +parameter val_spi0__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_mask_reg0 = 32'hE0006010; +parameter val_spi0__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter spi0__En_reg0 = 32'hE0006014; +parameter val_spi0__En_reg0 = 32'h00000000; +parameter mask_spi0__En_reg0 = 32'hFFFFFFFF; + +parameter spi0__Delay_reg0 = 32'hE0006018; +parameter val_spi0__Delay_reg0 = 32'h00000000; +parameter mask_spi0__Delay_reg0 = 32'hFFFFFFFF; + +parameter spi0__Tx_data_reg0 = 32'hE000601C; +parameter val_spi0__Tx_data_reg0 = 32'h00000000; +parameter mask_spi0__Tx_data_reg0 = 32'hFFFFFFFF; + +parameter spi0__Rx_data_reg0 = 32'hE0006020; +parameter val_spi0__Rx_data_reg0 = 32'h00000000; +parameter mask_spi0__Rx_data_reg0 = 32'hFFFFFFFF; + +parameter spi0__Slave_Idle_count_reg0 = 32'hE0006024; +parameter val_spi0__Slave_Idle_count_reg0 = 32'h000000FF; +parameter mask_spi0__Slave_Idle_count_reg0 = 32'hFFFFFFFF; + +parameter spi0__TX_thres_reg0 = 32'hE0006028; +parameter val_spi0__TX_thres_reg0 = 32'h00000001; +parameter mask_spi0__TX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi0__RX_thres_reg0 = 32'hE000602C; +parameter val_spi0__RX_thres_reg0 = 32'h00000001; +parameter mask_spi0__RX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi0__Mod_id_reg0 = 32'hE00060FC; +parameter val_spi0__Mod_id_reg0 = 32'h00090106; +parameter mask_spi0__Mod_id_reg0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module spi1 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter spi1__Config_reg0 = 32'hE0007000; +parameter val_spi1__Config_reg0 = 32'h00020000; +parameter mask_spi1__Config_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intr_status_reg0 = 32'hE0007004; +parameter val_spi1__Intr_status_reg0 = 32'h00000004; +parameter mask_spi1__Intr_status_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_en_reg0 = 32'hE0007008; +parameter val_spi1__Intrpt_en_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_dis_reg0 = 32'hE000700C; +parameter val_spi1__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_mask_reg0 = 32'hE0007010; +parameter val_spi1__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter spi1__En_reg0 = 32'hE0007014; +parameter val_spi1__En_reg0 = 32'h00000000; +parameter mask_spi1__En_reg0 = 32'hFFFFFFFF; + +parameter spi1__Delay_reg0 = 32'hE0007018; +parameter val_spi1__Delay_reg0 = 32'h00000000; +parameter mask_spi1__Delay_reg0 = 32'hFFFFFFFF; + +parameter spi1__Tx_data_reg0 = 32'hE000701C; +parameter val_spi1__Tx_data_reg0 = 32'h00000000; +parameter mask_spi1__Tx_data_reg0 = 32'hFFFFFFFF; + +parameter spi1__Rx_data_reg0 = 32'hE0007020; +parameter val_spi1__Rx_data_reg0 = 32'h00000000; +parameter mask_spi1__Rx_data_reg0 = 32'hFFFFFFFF; + +parameter spi1__Slave_Idle_count_reg0 = 32'hE0007024; +parameter val_spi1__Slave_Idle_count_reg0 = 32'h000000FF; +parameter mask_spi1__Slave_Idle_count_reg0 = 32'hFFFFFFFF; + +parameter spi1__TX_thres_reg0 = 32'hE0007028; +parameter val_spi1__TX_thres_reg0 = 32'h00000001; +parameter mask_spi1__TX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi1__RX_thres_reg0 = 32'hE000702C; +parameter val_spi1__RX_thres_reg0 = 32'h00000001; +parameter mask_spi1__RX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi1__Mod_id_reg0 = 32'hE00070FC; +parameter val_spi1__Mod_id_reg0 = 32'h00090106; +parameter mask_spi1__Mod_id_reg0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module swdt swdt +// doc version: 2.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter swdt__MODE = 32'hF8005000; +parameter val_swdt__MODE = 32'h000001C2; +parameter mask_swdt__MODE = 32'h00FFFFFF; + +parameter swdt__CONTROL = 32'hF8005004; +parameter val_swdt__CONTROL = 32'h03FFC3FC; +parameter mask_swdt__CONTROL = 32'h03FFFFFF; + +parameter swdt__RESTART = 32'hF8005008; +parameter val_swdt__RESTART = 32'h00000000; +parameter mask_swdt__RESTART = 32'h0000FFFF; + +parameter swdt__STATUS = 32'hF800500C; +parameter val_swdt__STATUS = 32'h00000000; +parameter mask_swdt__STATUS = 32'h00000001; + + +// ************************************************************ +// Module ttc0 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ttc0__Clock_Control_1 = 32'hF8001000; +parameter val_ttc0__Clock_Control_1 = 32'h00000000; +parameter mask_ttc0__Clock_Control_1 = 32'h0000007F; + +parameter ttc0__Clock_Control_2 = 32'hF8001004; +parameter val_ttc0__Clock_Control_2 = 32'h00000000; +parameter mask_ttc0__Clock_Control_2 = 32'h0000007F; + +parameter ttc0__Clock_Control_3 = 32'hF8001008; +parameter val_ttc0__Clock_Control_3 = 32'h00000000; +parameter mask_ttc0__Clock_Control_3 = 32'h0000007F; + +parameter ttc0__Counter_Control_1 = 32'hF800100C; +parameter val_ttc0__Counter_Control_1 = 32'h00000021; +parameter mask_ttc0__Counter_Control_1 = 32'h0000007F; + +parameter ttc0__Counter_Control_2 = 32'hF8001010; +parameter val_ttc0__Counter_Control_2 = 32'h00000021; +parameter mask_ttc0__Counter_Control_2 = 32'h0000007F; + +parameter ttc0__Counter_Control_3 = 32'hF8001014; +parameter val_ttc0__Counter_Control_3 = 32'h00000021; +parameter mask_ttc0__Counter_Control_3 = 32'h0000007F; + +parameter ttc0__Counter_Value_1 = 32'hF8001018; +parameter val_ttc0__Counter_Value_1 = 32'h00000000; +parameter mask_ttc0__Counter_Value_1 = 32'h0000FFFF; + +parameter ttc0__Counter_Value_2 = 32'hF800101C; +parameter val_ttc0__Counter_Value_2 = 32'h00000000; +parameter mask_ttc0__Counter_Value_2 = 32'h0000FFFF; + +parameter ttc0__Counter_Value_3 = 32'hF8001020; +parameter val_ttc0__Counter_Value_3 = 32'h00000000; +parameter mask_ttc0__Counter_Value_3 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_1 = 32'hF8001024; +parameter val_ttc0__Interval_Counter_1 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_2 = 32'hF8001028; +parameter val_ttc0__Interval_Counter_2 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_3 = 32'hF800102C; +parameter val_ttc0__Interval_Counter_3 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_1 = 32'hF8001030; +parameter val_ttc0__Match_1_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_2 = 32'hF8001034; +parameter val_ttc0__Match_1_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_3 = 32'hF8001038; +parameter val_ttc0__Match_1_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_1 = 32'hF800103C; +parameter val_ttc0__Match_2_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_2 = 32'hF8001040; +parameter val_ttc0__Match_2_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_3 = 32'hF8001044; +parameter val_ttc0__Match_2_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_1 = 32'hF8001048; +parameter val_ttc0__Match_3_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_2 = 32'hF800104C; +parameter val_ttc0__Match_3_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_3 = 32'hF8001050; +parameter val_ttc0__Match_3_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Interrupt_Register_1 = 32'hF8001054; +parameter val_ttc0__Interrupt_Register_1 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_1 = 32'h0000003F; + +parameter ttc0__Interrupt_Register_2 = 32'hF8001058; +parameter val_ttc0__Interrupt_Register_2 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_2 = 32'h0000003F; + +parameter ttc0__Interrupt_Register_3 = 32'hF800105C; +parameter val_ttc0__Interrupt_Register_3 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_3 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_1 = 32'hF8001060; +parameter val_ttc0__Interrupt_Enable_1 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_1 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_2 = 32'hF8001064; +parameter val_ttc0__Interrupt_Enable_2 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_2 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_3 = 32'hF8001068; +parameter val_ttc0__Interrupt_Enable_3 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_3 = 32'h0000003F; + +parameter ttc0__Event_Control_Timer_1 = 32'hF800106C; +parameter val_ttc0__Event_Control_Timer_1 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_1 = 32'h00000007; + +parameter ttc0__Event_Control_Timer_2 = 32'hF8001070; +parameter val_ttc0__Event_Control_Timer_2 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_2 = 32'h00000007; + +parameter ttc0__Event_Control_Timer_3 = 32'hF8001074; +parameter val_ttc0__Event_Control_Timer_3 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_3 = 32'h00000007; + +parameter ttc0__Event_Register_1 = 32'hF8001078; +parameter val_ttc0__Event_Register_1 = 32'h00000000; +parameter mask_ttc0__Event_Register_1 = 32'h0000FFFF; + +parameter ttc0__Event_Register_2 = 32'hF800107C; +parameter val_ttc0__Event_Register_2 = 32'h00000000; +parameter mask_ttc0__Event_Register_2 = 32'h0000FFFF; + +parameter ttc0__Event_Register_3 = 32'hF8001080; +parameter val_ttc0__Event_Register_3 = 32'h00000000; +parameter mask_ttc0__Event_Register_3 = 32'h0000FFFF; + + +// ************************************************************ +// Module ttc1 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ttc1__Clock_Control_1 = 32'hF8002000; +parameter val_ttc1__Clock_Control_1 = 32'h00000000; +parameter mask_ttc1__Clock_Control_1 = 32'h0000007F; + +parameter ttc1__Clock_Control_2 = 32'hF8002004; +parameter val_ttc1__Clock_Control_2 = 32'h00000000; +parameter mask_ttc1__Clock_Control_2 = 32'h0000007F; + +parameter ttc1__Clock_Control_3 = 32'hF8002008; +parameter val_ttc1__Clock_Control_3 = 32'h00000000; +parameter mask_ttc1__Clock_Control_3 = 32'h0000007F; + +parameter ttc1__Counter_Control_1 = 32'hF800200C; +parameter val_ttc1__Counter_Control_1 = 32'h00000021; +parameter mask_ttc1__Counter_Control_1 = 32'h0000007F; + +parameter ttc1__Counter_Control_2 = 32'hF8002010; +parameter val_ttc1__Counter_Control_2 = 32'h00000021; +parameter mask_ttc1__Counter_Control_2 = 32'h0000007F; + +parameter ttc1__Counter_Control_3 = 32'hF8002014; +parameter val_ttc1__Counter_Control_3 = 32'h00000021; +parameter mask_ttc1__Counter_Control_3 = 32'h0000007F; + +parameter ttc1__Counter_Value_1 = 32'hF8002018; +parameter val_ttc1__Counter_Value_1 = 32'h00000000; +parameter mask_ttc1__Counter_Value_1 = 32'h0000FFFF; + +parameter ttc1__Counter_Value_2 = 32'hF800201C; +parameter val_ttc1__Counter_Value_2 = 32'h00000000; +parameter mask_ttc1__Counter_Value_2 = 32'h0000FFFF; + +parameter ttc1__Counter_Value_3 = 32'hF8002020; +parameter val_ttc1__Counter_Value_3 = 32'h00000000; +parameter mask_ttc1__Counter_Value_3 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_1 = 32'hF8002024; +parameter val_ttc1__Interval_Counter_1 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_2 = 32'hF8002028; +parameter val_ttc1__Interval_Counter_2 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_3 = 32'hF800202C; +parameter val_ttc1__Interval_Counter_3 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_1 = 32'hF8002030; +parameter val_ttc1__Match_1_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_2 = 32'hF8002034; +parameter val_ttc1__Match_1_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_3 = 32'hF8002038; +parameter val_ttc1__Match_1_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_1 = 32'hF800203C; +parameter val_ttc1__Match_2_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_2 = 32'hF8002040; +parameter val_ttc1__Match_2_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_3 = 32'hF8002044; +parameter val_ttc1__Match_2_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_1 = 32'hF8002048; +parameter val_ttc1__Match_3_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_2 = 32'hF800204C; +parameter val_ttc1__Match_3_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_3 = 32'hF8002050; +parameter val_ttc1__Match_3_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Interrupt_Register_1 = 32'hF8002054; +parameter val_ttc1__Interrupt_Register_1 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_1 = 32'h0000003F; + +parameter ttc1__Interrupt_Register_2 = 32'hF8002058; +parameter val_ttc1__Interrupt_Register_2 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_2 = 32'h0000003F; + +parameter ttc1__Interrupt_Register_3 = 32'hF800205C; +parameter val_ttc1__Interrupt_Register_3 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_3 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_1 = 32'hF8002060; +parameter val_ttc1__Interrupt_Enable_1 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_1 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_2 = 32'hF8002064; +parameter val_ttc1__Interrupt_Enable_2 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_2 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_3 = 32'hF8002068; +parameter val_ttc1__Interrupt_Enable_3 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_3 = 32'h0000003F; + +parameter ttc1__Event_Control_Timer_1 = 32'hF800206C; +parameter val_ttc1__Event_Control_Timer_1 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_1 = 32'h00000007; + +parameter ttc1__Event_Control_Timer_2 = 32'hF8002070; +parameter val_ttc1__Event_Control_Timer_2 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_2 = 32'h00000007; + +parameter ttc1__Event_Control_Timer_3 = 32'hF8002074; +parameter val_ttc1__Event_Control_Timer_3 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_3 = 32'h00000007; + +parameter ttc1__Event_Register_1 = 32'hF8002078; +parameter val_ttc1__Event_Register_1 = 32'h00000000; +parameter mask_ttc1__Event_Register_1 = 32'h0000FFFF; + +parameter ttc1__Event_Register_2 = 32'hF800207C; +parameter val_ttc1__Event_Register_2 = 32'h00000000; +parameter mask_ttc1__Event_Register_2 = 32'h0000FFFF; + +parameter ttc1__Event_Register_3 = 32'hF8002080; +parameter val_ttc1__Event_Register_3 = 32'h00000000; +parameter mask_ttc1__Event_Register_3 = 32'h0000FFFF; + + +// ************************************************************ +// Module uart0 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter uart0__Control_reg0 = 32'hE0000000; +parameter val_uart0__Control_reg0 = 32'h00000128; +parameter mask_uart0__Control_reg0 = 32'hFFFFFFFF; + +parameter uart0__mode_reg0 = 32'hE0000004; +parameter val_uart0__mode_reg0 = 32'h00000000; +parameter mask_uart0__mode_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_en_reg0 = 32'hE0000008; +parameter val_uart0__Intrpt_en_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_dis_reg0 = 32'hE000000C; +parameter val_uart0__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_mask_reg0 = 32'hE0000010; +parameter val_uart0__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter uart0__Chnl_int_sts_reg0 = 32'hE0000014; +parameter val_uart0__Chnl_int_sts_reg0 = 32'h00000200; +parameter mask_uart0__Chnl_int_sts_reg0 = 32'hFFFFFFFF; + +parameter uart0__Baud_rate_gen_reg0 = 32'hE0000018; +parameter val_uart0__Baud_rate_gen_reg0 = 32'h0000028B; +parameter mask_uart0__Baud_rate_gen_reg0 = 32'hFFFFFFFF; + +parameter uart0__Rcvr_timeout_reg0 = 32'hE000001C; +parameter val_uart0__Rcvr_timeout_reg0 = 32'h00000000; +parameter mask_uart0__Rcvr_timeout_reg0 = 32'hFFFFFFFF; + +parameter uart0__Rcvr_FIFO_trigger_level0 = 32'hE0000020; +parameter val_uart0__Rcvr_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart0__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; + +parameter uart0__Modem_ctrl_reg0 = 32'hE0000024; +parameter val_uart0__Modem_ctrl_reg0 = 32'h00000000; +parameter mask_uart0__Modem_ctrl_reg0 = 32'hFFFFFFFF; + +parameter uart0__Modem_sts_reg0 = 32'hE0000028; +parameter val_uart0__Modem_sts_reg0 = 32'h00000000; +parameter mask_uart0__Modem_sts_reg0 = 32'h00000000; + +parameter uart0__Channel_sts_reg0 = 32'hE000002C; +parameter val_uart0__Channel_sts_reg0 = 32'h00000000; +parameter mask_uart0__Channel_sts_reg0 = 32'hFFFFFFFF; + +parameter uart0__TX_RX_FIFO0 = 32'hE0000030; +parameter val_uart0__TX_RX_FIFO0 = 32'h00000000; +parameter mask_uart0__TX_RX_FIFO0 = 32'hFFFFFFFF; + +parameter uart0__Baud_rate_divider_reg0 = 32'hE0000034; +parameter val_uart0__Baud_rate_divider_reg0 = 32'h0000000F; +parameter mask_uart0__Baud_rate_divider_reg0 = 32'hFFFFFFFF; + +parameter uart0__Flow_delay_reg0 = 32'hE0000038; +parameter val_uart0__Flow_delay_reg0 = 32'h00000000; +parameter mask_uart0__Flow_delay_reg0 = 32'hFFFFFFFF; + +parameter uart0__IR_min_rcv_pulse_wdth0 = 32'hE000003C; +parameter val_uart0__IR_min_rcv_pulse_wdth0 = 32'h00000000; +parameter mask_uart0__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; + +parameter uart0__IR_transmitted_pulse_wdth0 = 32'hE0000040; +parameter val_uart0__IR_transmitted_pulse_wdth0 = 32'h00000000; +parameter mask_uart0__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; + +parameter uart0__Tx_FIFO_trigger_level0 = 32'hE0000044; +parameter val_uart0__Tx_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart0__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module uart1 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter uart1__Control_reg0 = 32'hE0001000; +parameter val_uart1__Control_reg0 = 32'h00000128; +parameter mask_uart1__Control_reg0 = 32'hFFFFFFFF; + +parameter uart1__mode_reg0 = 32'hE0001004; +parameter val_uart1__mode_reg0 = 32'h00000000; +parameter mask_uart1__mode_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_en_reg0 = 32'hE0001008; +parameter val_uart1__Intrpt_en_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_dis_reg0 = 32'hE000100C; +parameter val_uart1__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_mask_reg0 = 32'hE0001010; +parameter val_uart1__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter uart1__Chnl_int_sts_reg0 = 32'hE0001014; +parameter val_uart1__Chnl_int_sts_reg0 = 32'h00000200; +parameter mask_uart1__Chnl_int_sts_reg0 = 32'hFFFFFFFF; + +parameter uart1__Baud_rate_gen_reg0 = 32'hE0001018; +parameter val_uart1__Baud_rate_gen_reg0 = 32'h0000028B; +parameter mask_uart1__Baud_rate_gen_reg0 = 32'hFFFFFFFF; + +parameter uart1__Rcvr_timeout_reg0 = 32'hE000101C; +parameter val_uart1__Rcvr_timeout_reg0 = 32'h00000000; +parameter mask_uart1__Rcvr_timeout_reg0 = 32'hFFFFFFFF; + +parameter uart1__Rcvr_FIFO_trigger_level0 = 32'hE0001020; +parameter val_uart1__Rcvr_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart1__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; + +parameter uart1__Modem_ctrl_reg0 = 32'hE0001024; +parameter val_uart1__Modem_ctrl_reg0 = 32'h00000000; +parameter mask_uart1__Modem_ctrl_reg0 = 32'hFFFFFFFF; + +parameter uart1__Modem_sts_reg0 = 32'hE0001028; +parameter val_uart1__Modem_sts_reg0 = 32'h00000000; +parameter mask_uart1__Modem_sts_reg0 = 32'h00000000; + +parameter uart1__Channel_sts_reg0 = 32'hE000102C; +parameter val_uart1__Channel_sts_reg0 = 32'h00000000; +parameter mask_uart1__Channel_sts_reg0 = 32'hFFFFFFFF; + +parameter uart1__TX_RX_FIFO0 = 32'hE0001030; +parameter val_uart1__TX_RX_FIFO0 = 32'h00000000; +parameter mask_uart1__TX_RX_FIFO0 = 32'hFFFFFFFF; + +parameter uart1__Baud_rate_divider_reg0 = 32'hE0001034; +parameter val_uart1__Baud_rate_divider_reg0 = 32'h0000000F; +parameter mask_uart1__Baud_rate_divider_reg0 = 32'hFFFFFFFF; + +parameter uart1__Flow_delay_reg0 = 32'hE0001038; +parameter val_uart1__Flow_delay_reg0 = 32'h00000000; +parameter mask_uart1__Flow_delay_reg0 = 32'hFFFFFFFF; + +parameter uart1__IR_min_rcv_pulse_wdth0 = 32'hE000103C; +parameter val_uart1__IR_min_rcv_pulse_wdth0 = 32'h00000000; +parameter mask_uart1__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; + +parameter uart1__IR_transmitted_pulse_wdth0 = 32'hE0001040; +parameter val_uart1__IR_transmitted_pulse_wdth0 = 32'h00000000; +parameter mask_uart1__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; + +parameter uart1__Tx_FIFO_trigger_level0 = 32'hE0001044; +parameter val_uart1__Tx_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart1__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module usb0 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter usb0__ID = 32'hE0002000; +parameter val_usb0__ID = 32'hE441FA05; +parameter mask_usb0__ID = 32'hFFFFFFFF; + +parameter usb0__HWGENERAL = 32'hE0002004; +parameter val_usb0__HWGENERAL = 32'h00000083; +parameter mask_usb0__HWGENERAL = 32'h00000FFF; + +parameter usb0__HWHOST = 32'hE0002008; +parameter val_usb0__HWHOST = 32'h10020001; +parameter mask_usb0__HWHOST = 32'hFFFFFFFF; + +parameter usb0__HWDEVICE = 32'hE000200C; +parameter val_usb0__HWDEVICE = 32'h00000019; +parameter mask_usb0__HWDEVICE = 32'h0000003F; + +parameter usb0__HWTXBUF = 32'hE0002010; +parameter val_usb0__HWTXBUF = 32'h80060A10; +parameter mask_usb0__HWTXBUF = 32'hFFFFFFFF; + +parameter usb0__HWRXBUF = 32'hE0002014; +parameter val_usb0__HWRXBUF = 32'h00000A10; +parameter mask_usb0__HWRXBUF = 32'hFF00FFFF; + +parameter usb0__GPTIMER0LD = 32'hE0002080; +parameter val_usb0__GPTIMER0LD = 32'h00000000; +parameter mask_usb0__GPTIMER0LD = 32'h00FFFFFF; + +parameter usb0__GPTIMER0CTRL = 32'hE0002084; +parameter val_usb0__GPTIMER0CTRL = 32'h00000000; +parameter mask_usb0__GPTIMER0CTRL = 32'hFFFFFFFF; + +parameter usb0__GPTIMER1LD = 32'hE0002088; +parameter val_usb0__GPTIMER1LD = 32'h00000000; +parameter mask_usb0__GPTIMER1LD = 32'h00FFFFFF; + +parameter usb0__GPTIMER1CTRL = 32'hE000208C; +parameter val_usb0__GPTIMER1CTRL = 32'h00000000; +parameter mask_usb0__GPTIMER1CTRL = 32'hFFFFFFFF; + +parameter usb0__SBUSCFG = 32'hE0002090; +parameter val_usb0__SBUSCFG = 32'h00000003; +parameter mask_usb0__SBUSCFG = 32'h00000007; + +parameter usb0__CAPLENGTH_HCIVERSION = 32'hE0002100; +parameter val_usb0__CAPLENGTH_HCIVERSION = 32'h01000040; +parameter mask_usb0__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; + +parameter usb0__HCSPARAMS = 32'hE0002104; +parameter val_usb0__HCSPARAMS = 32'h00010011; +parameter mask_usb0__HCSPARAMS = 32'h0FFFFFFF; + +parameter usb0__HCCPARAMS = 32'hE0002108; +parameter val_usb0__HCCPARAMS = 32'h00000006; +parameter mask_usb0__HCCPARAMS = 32'h0000FFFF; + +parameter usb0__DCIVERSION = 32'hE0002120; +parameter val_usb0__DCIVERSION = 32'h00000001; +parameter mask_usb0__DCIVERSION = 32'h0000FFFF; + +parameter usb0__DCCPARAMS = 32'hE0002124; +parameter val_usb0__DCCPARAMS = 32'h0000018C; +parameter mask_usb0__DCCPARAMS = 32'h000001FF; + +parameter usb0__USBCMD = 32'hE0002140; +parameter val_usb0__USBCMD = 32'h00000B00; +parameter mask_usb0__USBCMD = 32'h00FFFFFF; + +parameter usb0__USBSTS = 32'hE0002144; +parameter val_usb0__USBSTS = 32'h00000000; +parameter mask_usb0__USBSTS = 32'h03FFFFFF; + +parameter usb0__USBINTR = 32'hE0002148; +parameter val_usb0__USBINTR = 32'h00000000; +parameter mask_usb0__USBINTR = 32'h03FF0FFF; + +parameter usb0__FRINDEX = 32'hE000214C; +parameter val_usb0__FRINDEX = 32'h00000000; +parameter mask_usb0__FRINDEX = 32'h00003FFF; + +parameter usb0__PERIODICLISTBASE_DEVICEADDR = 32'hE0002154; +parameter val_usb0__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; +parameter mask_usb0__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; + +parameter usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0002158; +parameter val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; +parameter mask_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; + +parameter usb0__TTCTRL = 32'hE000215C; +parameter val_usb0__TTCTRL = 32'h00000000; +parameter mask_usb0__TTCTRL = 32'hFFFFFFFF; + +parameter usb0__BURSTSIZE = 32'hE0002160; +parameter val_usb0__BURSTSIZE = 32'h00001010; +parameter mask_usb0__BURSTSIZE = 32'h0001FFFF; + +parameter usb0__TXFILLTUNING = 32'hE0002164; +parameter val_usb0__TXFILLTUNING = 32'h00020000; +parameter mask_usb0__TXFILLTUNING = 32'h003FFFFF; + +parameter usb0__TXTTFILLTUNING = 32'hE0002168; +parameter val_usb0__TXTTFILLTUNING = 32'h00000000; +parameter mask_usb0__TXTTFILLTUNING = 32'h00001FFF; + +parameter usb0__IC_USB = 32'hE000216C; +parameter val_usb0__IC_USB = 32'h00000000; +parameter mask_usb0__IC_USB = 32'hFFFFFFFF; + +parameter usb0__ULPI_VIEWPORT = 32'hE0002170; +parameter val_usb0__ULPI_VIEWPORT = 32'h00000000; +parameter mask_usb0__ULPI_VIEWPORT = 32'hFFFFFFFF; + +parameter usb0__ENDPTNAK = 32'hE0002178; +parameter val_usb0__ENDPTNAK = 32'h00000000; +parameter mask_usb0__ENDPTNAK = 32'hFFFFFFFF; + +parameter usb0__ENDPTNAKEN = 32'hE000217C; +parameter val_usb0__ENDPTNAKEN = 32'h00000000; +parameter mask_usb0__ENDPTNAKEN = 32'hFFFFFFFF; + +parameter usb0__CONFIGFLAG = 32'hE0002180; +parameter val_usb0__CONFIGFLAG = 32'h00000001; +parameter mask_usb0__CONFIGFLAG = 32'hFFFFFFFF; + +parameter usb0__PORTSC1 = 32'hE0002184; +parameter val_usb0__PORTSC1 = 32'h00000000; +parameter mask_usb0__PORTSC1 = 32'hFFFFFFFF; + +parameter usb0__OTGSC = 32'hE00021A4; +parameter val_usb0__OTGSC = 32'h00000020; +parameter mask_usb0__OTGSC = 32'hFFFFFFFF; + +parameter usb0__USBMODE = 32'hE00021A8; +parameter val_usb0__USBMODE = 32'h00000000; +parameter mask_usb0__USBMODE = 32'h0000FFFF; + +parameter usb0__ENDPTSETUPSTAT = 32'hE00021AC; +parameter val_usb0__ENDPTSETUPSTAT = 32'h00000000; +parameter mask_usb0__ENDPTSETUPSTAT = 32'h0000FFFF; + +parameter usb0__ENDPTPRIME = 32'hE00021B0; +parameter val_usb0__ENDPTPRIME = 32'h00000000; +parameter mask_usb0__ENDPTPRIME = 32'hFFFFFFFF; + +parameter usb0__ENDPTFLUSH = 32'hE00021B4; +parameter val_usb0__ENDPTFLUSH = 32'h00000000; +parameter mask_usb0__ENDPTFLUSH = 32'hFFFFFFFF; + +parameter usb0__ENDPTSTAT = 32'hE00021B8; +parameter val_usb0__ENDPTSTAT = 32'h00000000; +parameter mask_usb0__ENDPTSTAT = 32'hFFFFFFFF; + +parameter usb0__ENDPTCOMPLETE = 32'hE00021BC; +parameter val_usb0__ENDPTCOMPLETE = 32'h00000000; +parameter mask_usb0__ENDPTCOMPLETE = 32'hFFFFFFFF; + +parameter usb0__ENDPTCTRL0 = 32'hE00021C0; +parameter val_usb0__ENDPTCTRL0 = 32'h00800080; +parameter mask_usb0__ENDPTCTRL0 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL1 = 32'hE00021C4; +parameter val_usb0__ENDPTCTRL1 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL1 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL2 = 32'hE00021C8; +parameter val_usb0__ENDPTCTRL2 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL2 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL3 = 32'hE00021CC; +parameter val_usb0__ENDPTCTRL3 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL3 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL4 = 32'hE00021D0; +parameter val_usb0__ENDPTCTRL4 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL4 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL5 = 32'hE00021D4; +parameter val_usb0__ENDPTCTRL5 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL5 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL6 = 32'hE00021D8; +parameter val_usb0__ENDPTCTRL6 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL6 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL7 = 32'hE00021DC; +parameter val_usb0__ENDPTCTRL7 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL7 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL8 = 32'hE00021E0; +parameter val_usb0__ENDPTCTRL8 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL8 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL9 = 32'hE00021E4; +parameter val_usb0__ENDPTCTRL9 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL9 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL10 = 32'hE00021E8; +parameter val_usb0__ENDPTCTRL10 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL10 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL11 = 32'hE00021EC; +parameter val_usb0__ENDPTCTRL11 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL11 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL12 = 32'hE00021F0; +parameter val_usb0__ENDPTCTRL12 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL12 = 32'h00FFFFFF; + + +// ************************************************************ +// Module usb1 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter usb1__ID = 32'hE0003000; +parameter val_usb1__ID = 32'hE441FA05; +parameter mask_usb1__ID = 32'hFFFFFFFF; + +parameter usb1__HWGENERAL = 32'hE0003004; +parameter val_usb1__HWGENERAL = 32'h00000083; +parameter mask_usb1__HWGENERAL = 32'h00000FFF; + +parameter usb1__HWHOST = 32'hE0003008; +parameter val_usb1__HWHOST = 32'h10020001; +parameter mask_usb1__HWHOST = 32'hFFFFFFFF; + +parameter usb1__HWDEVICE = 32'hE000300C; +parameter val_usb1__HWDEVICE = 32'h00000019; +parameter mask_usb1__HWDEVICE = 32'h0000003F; + +parameter usb1__HWTXBUF = 32'hE0003010; +parameter val_usb1__HWTXBUF = 32'h80060A10; +parameter mask_usb1__HWTXBUF = 32'hFFFFFFFF; + +parameter usb1__HWRXBUF = 32'hE0003014; +parameter val_usb1__HWRXBUF = 32'h00000A10; +parameter mask_usb1__HWRXBUF = 32'hFF00FFFF; + +parameter usb1__GPTIMER0LD = 32'hE0003080; +parameter val_usb1__GPTIMER0LD = 32'h00000000; +parameter mask_usb1__GPTIMER0LD = 32'h00FFFFFF; + +parameter usb1__GPTIMER0CTRL = 32'hE0003084; +parameter val_usb1__GPTIMER0CTRL = 32'h00000000; +parameter mask_usb1__GPTIMER0CTRL = 32'hFFFFFFFF; + +parameter usb1__GPTIMER1LD = 32'hE0003088; +parameter val_usb1__GPTIMER1LD = 32'h00000000; +parameter mask_usb1__GPTIMER1LD = 32'h00FFFFFF; + +parameter usb1__GPTIMER1CTRL = 32'hE000308C; +parameter val_usb1__GPTIMER1CTRL = 32'h00000000; +parameter mask_usb1__GPTIMER1CTRL = 32'hFFFFFFFF; + +parameter usb1__SBUSCFG = 32'hE0003090; +parameter val_usb1__SBUSCFG = 32'h00000003; +parameter mask_usb1__SBUSCFG = 32'h00000007; + +parameter usb1__CAPLENGTH_HCIVERSION = 32'hE0003100; +parameter val_usb1__CAPLENGTH_HCIVERSION = 32'h01000040; +parameter mask_usb1__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; + +parameter usb1__HCSPARAMS = 32'hE0003104; +parameter val_usb1__HCSPARAMS = 32'h00010011; +parameter mask_usb1__HCSPARAMS = 32'h0FFFFFFF; + +parameter usb1__HCCPARAMS = 32'hE0003108; +parameter val_usb1__HCCPARAMS = 32'h00000006; +parameter mask_usb1__HCCPARAMS = 32'h0000FFFF; + +parameter usb1__DCIVERSION = 32'hE0003120; +parameter val_usb1__DCIVERSION = 32'h00000001; +parameter mask_usb1__DCIVERSION = 32'h0000FFFF; + +parameter usb1__DCCPARAMS = 32'hE0003124; +parameter val_usb1__DCCPARAMS = 32'h0000018C; +parameter mask_usb1__DCCPARAMS = 32'h000001FF; + +parameter usb1__USBCMD = 32'hE0003140; +parameter val_usb1__USBCMD = 32'h00000B00; +parameter mask_usb1__USBCMD = 32'h00FFFFFF; + +parameter usb1__USBSTS = 32'hE0003144; +parameter val_usb1__USBSTS = 32'h00000000; +parameter mask_usb1__USBSTS = 32'h03FFFFFF; + +parameter usb1__USBINTR = 32'hE0003148; +parameter val_usb1__USBINTR = 32'h00000000; +parameter mask_usb1__USBINTR = 32'h03FF0FFF; + +parameter usb1__FRINDEX = 32'hE000314C; +parameter val_usb1__FRINDEX = 32'h00000000; +parameter mask_usb1__FRINDEX = 32'h00003FFF; + +parameter usb1__PERIODICLISTBASE_DEVICEADDR = 32'hE0003154; +parameter val_usb1__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; +parameter mask_usb1__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; + +parameter usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0003158; +parameter val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; +parameter mask_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; + +parameter usb1__TTCTRL = 32'hE000315C; +parameter val_usb1__TTCTRL = 32'h00000000; +parameter mask_usb1__TTCTRL = 32'hFFFFFFFF; + +parameter usb1__BURSTSIZE = 32'hE0003160; +parameter val_usb1__BURSTSIZE = 32'h00001010; +parameter mask_usb1__BURSTSIZE = 32'h0001FFFF; + +parameter usb1__TXFILLTUNING = 32'hE0003164; +parameter val_usb1__TXFILLTUNING = 32'h00020000; +parameter mask_usb1__TXFILLTUNING = 32'h003FFFFF; + +parameter usb1__TXTTFILLTUNING = 32'hE0003168; +parameter val_usb1__TXTTFILLTUNING = 32'h00000000; +parameter mask_usb1__TXTTFILLTUNING = 32'h00001FFF; + +parameter usb1__IC_USB = 32'hE000316C; +parameter val_usb1__IC_USB = 32'h00000000; +parameter mask_usb1__IC_USB = 32'hFFFFFFFF; + +parameter usb1__ULPI_VIEWPORT = 32'hE0003170; +parameter val_usb1__ULPI_VIEWPORT = 32'h00000000; +parameter mask_usb1__ULPI_VIEWPORT = 32'hFFFFFFFF; + +parameter usb1__ENDPTNAK = 32'hE0003178; +parameter val_usb1__ENDPTNAK = 32'h00000000; +parameter mask_usb1__ENDPTNAK = 32'hFFFFFFFF; + +parameter usb1__ENDPTNAKEN = 32'hE000317C; +parameter val_usb1__ENDPTNAKEN = 32'h00000000; +parameter mask_usb1__ENDPTNAKEN = 32'hFFFFFFFF; + +parameter usb1__CONFIGFLAG = 32'hE0003180; +parameter val_usb1__CONFIGFLAG = 32'h00000001; +parameter mask_usb1__CONFIGFLAG = 32'hFFFFFFFF; + +parameter usb1__PORTSC1 = 32'hE0003184; +parameter val_usb1__PORTSC1 = 32'h00000000; +parameter mask_usb1__PORTSC1 = 32'hFFFFFFFF; + +parameter usb1__OTGSC = 32'hE00031A4; +parameter val_usb1__OTGSC = 32'h00000020; +parameter mask_usb1__OTGSC = 32'hFFFFFFFF; + +parameter usb1__USBMODE = 32'hE00031A8; +parameter val_usb1__USBMODE = 32'h00000000; +parameter mask_usb1__USBMODE = 32'h0000FFFF; + +parameter usb1__ENDPTSETUPSTAT = 32'hE00031AC; +parameter val_usb1__ENDPTSETUPSTAT = 32'h00000000; +parameter mask_usb1__ENDPTSETUPSTAT = 32'h0000FFFF; + +parameter usb1__ENDPTPRIME = 32'hE00031B0; +parameter val_usb1__ENDPTPRIME = 32'h00000000; +parameter mask_usb1__ENDPTPRIME = 32'hFFFFFFFF; + +parameter usb1__ENDPTFLUSH = 32'hE00031B4; +parameter val_usb1__ENDPTFLUSH = 32'h00000000; +parameter mask_usb1__ENDPTFLUSH = 32'hFFFFFFFF; + +parameter usb1__ENDPTSTAT = 32'hE00031B8; +parameter val_usb1__ENDPTSTAT = 32'h00000000; +parameter mask_usb1__ENDPTSTAT = 32'hFFFFFFFF; + +parameter usb1__ENDPTCOMPLETE = 32'hE00031BC; +parameter val_usb1__ENDPTCOMPLETE = 32'h00000000; +parameter mask_usb1__ENDPTCOMPLETE = 32'hFFFFFFFF; + +parameter usb1__ENDPTCTRL0 = 32'hE00031C0; +parameter val_usb1__ENDPTCTRL0 = 32'h00800080; +parameter mask_usb1__ENDPTCTRL0 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL1 = 32'hE00031C4; +parameter val_usb1__ENDPTCTRL1 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL1 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL2 = 32'hE00031C8; +parameter val_usb1__ENDPTCTRL2 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL2 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL3 = 32'hE00031CC; +parameter val_usb1__ENDPTCTRL3 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL3 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL4 = 32'hE00031D0; +parameter val_usb1__ENDPTCTRL4 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL4 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL5 = 32'hE00031D4; +parameter val_usb1__ENDPTCTRL5 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL5 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL6 = 32'hE00031D8; +parameter val_usb1__ENDPTCTRL6 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL6 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL7 = 32'hE00031DC; +parameter val_usb1__ENDPTCTRL7 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL7 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL8 = 32'hE00031E0; +parameter val_usb1__ENDPTCTRL8 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL8 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL9 = 32'hE00031E4; +parameter val_usb1__ENDPTCTRL9 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL9 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL10 = 32'hE00031E8; +parameter val_usb1__ENDPTCTRL10 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL10 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL11 = 32'hE00031EC; +parameter val_usb1__ENDPTCTRL11 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL11 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL12 = 32'hE00031F0; +parameter val_usb1__ENDPTCTRL12 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL12 = 32'h00FFFFFF; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_vl_rfs.sv b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_vl_rfs.sv new file mode 100644 index 0000000..800388a --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/aed8/hdl/processing_system7_vip_v1_0_vl_rfs.sv @@ -0,0 +1,13885 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_arb_wr.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 2 write requests from 2 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_arb_wr( + rstn, + sw_clk, + qos1, + qos2, + prt_dv1, + prt_dv2, + prt_data1, + prt_data2, + prt_addr1, + prt_addr2, + prt_bytes1, + prt_bytes2, + prt_strb1, + prt_strb2, + prt_ack1, + prt_ack2, + prt_qos, + prt_req, + prt_data, + prt_strb, + prt_addr, + prt_bytes, + prt_ack + +); +`include "processing_system7_vip_v1_0_16_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2; +input [max_burst_bits-1:0] prt_data1,prt_data2; +input [max_burst_bytes-1:0] prt_strb1,prt_strb2; +input [addr_width-1:0] prt_addr1,prt_addr2; +input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2; +input prt_dv1, prt_dv2, prt_ack; +output reg prt_ack1,prt_ack2,prt_req; +output reg [max_burst_bits-1:0] prt_data; +output reg [max_burst_bytes-1:0] prt_strb; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +output reg [axi_qos_width-1:0] prt_qos; + +parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11; +reg [1:0] state,temp_state; +bit DEBUG_INFO = 1; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_req = 1'b0; + if(prt_dv1 && !prt_dv2) begin + state = serv_req1; + prt_req = 1; + #0 prt_data = prt_data1; + #0 prt_strb = prt_strb1; + if(DEBUG_INFO) begin + $display("%m : prt_strb %0h prt_strb1 %0h",prt_data,prt_data1); + $display("%m : prt_strb %0h prt_strb1 %0h",prt_strb,prt_strb1); + end + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + prt_qos = qos1; + end else if(!prt_dv1 && prt_dv2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + #0 prt_data = prt_data2; + #0 prt_strb = prt_strb2; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data2 %0h",prt_strb,prt_data2); + $display("%m : prt_strb %0h prt_strb2 %0h",prt_strb,prt_strb2); + end + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv1 && prt_dv2) begin + if(qos1 > qos2) begin + prt_req = 1; + prt_qos = qos1; + #0 prt_data = prt_data1; + #0 prt_strb = prt_strb1; + if(DEBUG_INFO) begin + $display("%m : prt_strb %0h prt_strb1 %0h",prt_strb,prt_strb1); + end + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else if(qos1 < qos2) begin + prt_req = 1; + prt_qos = qos2; + #0 prt_data = prt_data2; + #0 prt_strb = prt_strb2; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data2 %0h",prt_strb,prt_data2); + $display("%m : prt_strb %0h prt_strb2 %0h",prt_strb,prt_strb2); + end + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + prt_req = 1; + prt_qos = qos1; + #0 prt_data = prt_data1; + #0 prt_strb = prt_strb1; + if(DEBUG_INFO) begin + $display("%m : prt_strb %0h prt_strb1 %0h",prt_strb,prt_strb1); + end + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req1:begin + state = serv_req1; + prt_ack2 = 1'b0; + if(prt_ack) begin + prt_ack1 = 1'b1; + prt_req = 0; + if(prt_dv2) begin + prt_req = 1; + prt_qos = qos2; + #0 prt_data = prt_data2; + #0 prt_strb = prt_strb2; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data2 %0h",prt_strb,prt_data2); + $display("%m : prt_strb %0h prt_strb2 %0h",prt_strb,prt_strb2); + end + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + // state = wait_req; + state = wait_ack_low; + end + end + end + serv_req2:begin + state = serv_req2; + prt_ack1 = 1'b0; + if(prt_ack) begin + prt_ack2 = 1'b1; + prt_req = 0; + if(prt_dv1) begin + prt_req = 1; + prt_qos = qos1; + #0 prt_data = prt_data1; + #0 prt_strb = prt_strb1; + if(DEBUG_INFO) begin + $display("%m : prt_strb %0h prt_strb1 %0h",prt_strb,prt_strb1); + end + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else begin + state = wait_ack_low; + // state = wait_req; + end + end + end + wait_ack_low:begin + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + state = wait_ack_low; + if(!prt_ack) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_arb_rd.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 2 read requests from 2 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_arb_rd( + rstn, + sw_clk, + + qos1, + qos2, + + prt_req1, + prt_req2, + prt_bytes1, + prt_bytes2, + prt_addr1, + prt_addr2, + prt_data1, + prt_data2, + prt_dv1, + prt_dv2, + + prt_req, + prt_qos, + prt_addr, + prt_bytes, + prt_data, + prt_dv + +); +`include "processing_system7_vip_v1_0_16_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2; +input prt_req1, prt_req2; +input [addr_width-1:0] prt_addr1, prt_addr2; +input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2; +output reg prt_dv1, prt_dv2; +output reg [max_burst_bits-1:0] prt_data1,prt_data2; + +output reg prt_req; +output reg [axi_qos_width-1:0] prt_qos; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +input [max_burst_bits-1:0] prt_data; +input prt_dv; + +parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11; +reg [1:0] state; +bit DEBUG_INFO = 1; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_req = 0; + if(prt_req1 && !prt_req2) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(!prt_req1 && prt_req2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req1 && prt_req2) begin + if(qos1 > qos2) begin + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else if(qos1 < qos2) begin + prt_req = 1; + prt_addr = prt_addr2; + prt_qos = qos2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req1:begin + state = serv_req1; + prt_dv2 = 1'b0; + if(prt_dv) begin + prt_dv1 = 1'b1; + prt_data1 = prt_data; + prt_req = 0; + if(prt_req2) begin + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + state = wait_dv_low; + //state = wait_req; + end + end + end + serv_req2:begin + state = serv_req2; + prt_dv1 = 1'b0; + if(prt_dv) begin + prt_dv2 = 1'b1; + prt_data2 = prt_data; + prt_req = 0; + if(prt_req1) begin + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else begin + state = wait_dv_low; + //state = wait_req; + end + end + end + + wait_dv_low:begin + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + state = wait_dv_low; + if(!prt_dv) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_arb_wr_4.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 4 write requests from 4 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_arb_wr_4( + rstn, + sw_clk, + + qos1, + qos2, + qos3, + qos4, + + prt_dv1, + prt_dv2, + prt_dv3, + prt_dv4, + + prt_data1, + prt_data2, + prt_data3, + prt_data4, + + prt_strb1, + prt_strb2, + prt_strb3, + prt_strb4, + + prt_addr1, + prt_addr2, + prt_addr3, + prt_addr4, + + prt_bytes1, + prt_bytes2, + prt_bytes3, + prt_bytes4, + +prt_ack1, + prt_ack2, + prt_ack3, + prt_ack4, + + prt_qos, + prt_req, + prt_data, + prt_strb, + prt_addr, + prt_bytes, + prt_ack + +); +`include "processing_system7_vip_v1_0_16_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2,qos3,qos4; +input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4; +input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4; +input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4; +input [max_burst_bytes-1:0] prt_strb1,prt_strb2,prt_strb3,prt_strb4; +input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack; +output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req; +output reg [max_burst_bits-1:0] prt_data; +output reg [max_burst_bytes-1:0] prt_strb; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +output reg [axi_qos_width-1:0] prt_qos; +parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101; +reg [2:0] state; +reg DEBUG_INFO = 1; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + prt_req = 0; + if(prt_dv1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + #0 prt_data = prt_data1; + #0 prt_strb = prt_strb1; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data1 %0h ",prt_data,prt_data1); + $display("%m : prt_strb %0h prt_strb1 %0h ",prt_strb,prt_strb1); + end + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_dv2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + #0 prt_data = prt_data2; + #0 prt_strb = prt_strb2; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data2 %0h ",prt_data,prt_data2); + $display("%m : prt_strb %0h prt_strb2 %0h ",prt_strb,prt_strb2); + end + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + #0 prt_data = prt_data3; + #0 prt_strb = prt_strb3; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data3 %0h ",prt_data,prt_data3); + $display("%m : prt_strb %0h prt_strb3 %0h ",prt_strb,prt_strb3); + end + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_dv4) begin + prt_req = 1; + prt_qos = qos4; + #0 prt_data = prt_data4; + #0 prt_strb = prt_strb4; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data4 %0h ",prt_data,prt_data4); + $display("%m : prt_strb %0h prt_strb4 %0h ",prt_strb,prt_strb4); + end + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + serv_req1:begin + state = serv_req1; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + if(prt_ack)begin + prt_ack1 = 1'b1; + //state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv2) begin + state = serv_req2; + prt_qos = qos2; + prt_req = 1; + #0 prt_data = prt_data2; + #0 prt_strb = prt_strb2; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data2 %0h ",prt_data,prt_data2); + $display("%m : prt_strb %0h prt_strb2 %0h ",prt_strb,prt_strb2); + end + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + #0 prt_data = prt_data3; + #0 prt_strb = prt_strb3; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data3 %0h ",prt_data,prt_data3); + $display("%m : prt_strb %0h prt_strb3 %0h ",prt_strb,prt_strb3); + end + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_dv4) begin + prt_req = 1; + prt_qos = qos4; + #0 prt_data = prt_data4; + #0 prt_strb = prt_strb4; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data4 %0h ",prt_data,prt_data4); + $display("%m : prt_strb %0h prt_strb4 %0h ",prt_strb,prt_strb4); + end + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + end + serv_req2:begin + state = serv_req2; + prt_ack1 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + if(prt_ack)begin + prt_ack2 = 1'b1; + //state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv3) begin + state = serv_req3; + prt_qos = qos3; + prt_req = 1; + #0 prt_data = prt_data3; + #0 prt_strb = prt_strb3; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data3 %0h ",prt_data,prt_data3); + $display("%m : prt_strb %0h prt_strb3 %0h ",prt_strb,prt_strb3); + end + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_dv4) begin + state = serv_req4; + prt_req = 1; + prt_qos = qos4; + #0 prt_data = prt_data4; + #0 prt_strb = prt_strb4; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data4 %0h ",prt_data,prt_data4); + $display("%m : prt_strb %0h prt_strb4 %0h ",prt_strb,prt_strb4); + end + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_dv1) begin + prt_req = 1; + prt_qos = qos1; + #0 prt_data = prt_data1; + #0 prt_strb = prt_strb1; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data1 %0h ",prt_data,prt_data1); + $display("%m : prt_strb %0h prt_strb1 %0h ",prt_strb,prt_strb1); + end + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req3:begin + state = serv_req3; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack4 = 1'b0; + if(prt_ack)begin + prt_ack3 = 1'b1; +// state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv4) begin + state = serv_req4; + prt_qos = qos4; + prt_req = 1; + #0 prt_data = prt_data4; + #0 prt_strb = prt_strb4; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data4 %0h ",prt_data,prt_data4); + $display("%m : prt_strb %0h prt_strb4 %0h ",prt_strb,prt_strb4); + end + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_dv1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + #0 prt_data = prt_data1; + #0 prt_strb = prt_strb1; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data1 %0h ",prt_data,prt_data1); + $display("%m : prt_strb %0h prt_strb1 %0h ",prt_strb,prt_strb1); + end + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_dv2) begin + prt_req = 1; + prt_qos = qos2; + #0 prt_data = prt_data2; + #0 prt_strb = prt_strb2; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data2 %0h ",prt_data,prt_data2); + $display("%m : prt_strb %0h prt_strb2 %0h ",prt_strb,prt_strb2); + end + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end + end + end + serv_req4:begin + state = serv_req4; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + if(prt_ack)begin + prt_ack4 = 1'b1; + //state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + #0 prt_data = prt_data1; + #0 prt_strb = prt_strb1; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data1 %0h ",prt_data,prt_data1); + $display("%m : prt_strb %0h prt_strb1 %0h ",prt_strb,prt_strb1); + end + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_dv2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + #0 prt_data = prt_data2; + #0 prt_strb = prt_strb2; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data2 %0h ",prt_data,prt_data2); + $display("%m : prt_strb %0h prt_strb2 %0h ",prt_strb,prt_strb2); + end + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv3) begin + prt_req = 1; + prt_qos = qos3; + #0 prt_data = prt_data3; + #0 prt_strb = prt_strb3; + if(DEBUG_INFO) begin + $display("%m : prt_data %0h prt_data3 %0h ",prt_data,prt_data3); + $display("%m : prt_strb %0h prt_strb3 %0h ",prt_strb,prt_strb3); + end + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + state = serv_req3; + end + end + end + wait_ack_low:begin + state = wait_ack_low; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + if(!prt_ack) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_arb_rd_4.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 4 read requests from 4 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_arb_rd_4( + rstn, + sw_clk, + + qos1, + qos2, + qos3, + qos4, + + prt_req1, + prt_req2, + prt_req3, + prt_req4, + + prt_data1, + prt_data2, + prt_data3, + prt_data4, + + prt_addr1, + prt_addr2, + prt_addr3, + prt_addr4, + + prt_bytes1, + prt_bytes2, + prt_bytes3, + prt_bytes4, + + prt_dv1, + prt_dv2, + prt_dv3, + prt_dv4, + + prt_qos, + prt_req, + prt_data, + prt_addr, + prt_bytes, + prt_dv + +); +`include "processing_system7_vip_v1_0_16_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2,qos3,qos4; +input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv; +output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4; +input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4; +input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4; +output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req; +input [max_burst_bits-1:0] prt_data; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +output reg [axi_qos_width-1:0] prt_qos; + +parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101; +reg [2:0] state; +bit DEBUG_INFO = 1; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + prt_req = 1'b0; + if(prt_req1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_req2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_req4) begin + prt_req = 1; + prt_addr = prt_addr4; + prt_qos = qos4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + serv_req1:begin + state = serv_req1; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + if(prt_dv)begin + prt_dv1 = 1'b1; + prt_data1 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req2) begin + state = serv_req2; + prt_qos = qos2; + prt_req = 1; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req3) begin + state = serv_req3; + prt_qos = qos3; + prt_req = 1; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_req4) begin + prt_req = 1; + prt_qos = qos4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + end + serv_req2:begin + state = serv_req2; + prt_dv1 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + if(prt_dv)begin + prt_dv2 = 1'b1; + prt_data2 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_req4) begin + state = serv_req4; + prt_req = 1; + prt_qos = qos4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_req1) begin + prt_req = 1; + prt_addr = prt_addr1; + prt_qos = qos1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req3:begin + state = serv_req3; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv4 = 1'b0; + if(prt_dv)begin + prt_dv3 = 1'b1; + prt_data3 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req4) begin + state = serv_req4; + prt_qos = qos4; + prt_req = 1; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_req1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_req2) begin + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end + end + end + serv_req4:begin + state = serv_req4; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + if(prt_dv)begin + prt_dv4 = 1'b1; + prt_data4 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req1) begin + state = serv_req1; + prt_qos = qos1; + prt_req = 1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_req2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req3) begin + prt_req = 1; + prt_addr = prt_addr3; + prt_qos = qos3; + prt_bytes = prt_bytes3; + state = serv_req3; + end + end + end + wait_dv_low:begin + state = wait_dv_low; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + if(!prt_dv) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_arb_hp2_3.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between RD/WR requests from 2 ports. + * Used for modelling the Top_Interconnect switch. + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_arb_hp2_3( + sw_clk, + rstn, + w_qos_hp2, + r_qos_hp2, + w_qos_hp3, + r_qos_hp3, + + wr_ack_ddr_hp2, + wr_data_hp2, + wr_strb_hp2, + wr_addr_hp2, + wr_bytes_hp2, + wr_dv_ddr_hp2, + rd_req_ddr_hp2, + rd_addr_hp2, + rd_bytes_hp2, + rd_data_ddr_hp2, + rd_dv_ddr_hp2, + + wr_ack_ddr_hp3, + wr_data_hp3, + wr_strb_hp3, + wr_addr_hp3, + wr_bytes_hp3, + wr_dv_ddr_hp3, + rd_req_ddr_hp3, + rd_addr_hp3, + rd_bytes_hp3, + rd_data_ddr_hp3, + rd_dv_ddr_hp3, + + ddr_wr_ack, + ddr_wr_dv, + ddr_rd_req, + ddr_rd_dv, + ddr_rd_qos, + ddr_wr_qos, + + ddr_wr_addr, + ddr_wr_data, + ddr_wr_strb, + ddr_wr_bytes, + ddr_rd_addr, + ddr_rd_data, + ddr_rd_bytes + +); +`include "processing_system7_vip_v1_0_16_local_params.v" +input sw_clk; +input rstn; +input [axi_qos_width-1:0] w_qos_hp2; +input [axi_qos_width-1:0] r_qos_hp2; +input [axi_qos_width-1:0] w_qos_hp3; +input [axi_qos_width-1:0] r_qos_hp3; +input [axi_qos_width-1:0] ddr_rd_qos; +input [axi_qos_width-1:0] ddr_wr_qos; + +output wr_ack_ddr_hp2; +input [max_burst_bits-1:0] wr_data_hp2; +input [max_burst_bytes-1:0] wr_strb_hp2; +input [addr_width-1:0] wr_addr_hp2; +input [max_burst_bytes_width:0] wr_bytes_hp2; +output wr_dv_ddr_hp2; + +input rd_req_ddr_hp2; +input [addr_width-1:0] rd_addr_hp2; +input [max_burst_bytes_width:0] rd_bytes_hp2; +output [max_burst_bits-1:0] rd_data_ddr_hp2; +output rd_dv_ddr_hp2; + +output wr_ack_ddr_hp3; +input [max_burst_bits-1:0] wr_data_hp3; +input [max_burst_bytes-1:0] wr_strb_hp3; +input [addr_width-1:0] wr_addr_hp3; +input [max_burst_bytes_width:0] wr_bytes_hp3; +output wr_dv_ddr_hp3; + +input rd_req_ddr_hp3; +input [addr_width-1:0] rd_addr_hp3; +input [max_burst_bytes_width:0] rd_bytes_hp3; +output [max_burst_bits-1:0] rd_data_ddr_hp3; +output rd_dv_ddr_hp3; + +input ddr_wr_ack; +output ddr_wr_dv; +output [addr_width-1:0]ddr_wr_addr; +output [max_burst_bits-1:0]ddr_wr_data; +output [max_burst_bytes-1:0]ddr_wr_strb; +output [max_burst_bytes_width:0]ddr_wr_bytes; + +input ddr_rd_dv; +input [max_burst_bits-1:0] ddr_rd_data; +output ddr_rd_req; +output [addr_width-1:0] ddr_rd_addr; +output [max_burst_bytes_width:0] ddr_rd_bytes; + + + + +processing_system7_vip_v1_0_16_arb_wr ddr_hp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_hp2), + .qos2(w_qos_hp3), + .prt_dv1(wr_dv_ddr_hp2), + .prt_dv2(wr_dv_ddr_hp3), + .prt_data1(wr_data_hp2), + .prt_data2(wr_data_hp3), + .prt_strb1(wr_strb_hp2), + .prt_strb2(wr_strb_hp3), + .prt_addr1(wr_addr_hp2), + .prt_addr2(wr_addr_hp3), + .prt_bytes1(wr_bytes_hp2), + .prt_bytes2(wr_bytes_hp3), + .prt_ack1(wr_ack_ddr_hp2), + .prt_ack2(wr_ack_ddr_hp3), + .prt_req(ddr_wr_dv), + .prt_qos(ddr_wr_qos), + .prt_data(ddr_wr_data), + .prt_strb(ddr_wr_strb), + .prt_addr(ddr_wr_addr), + .prt_bytes(ddr_wr_bytes), + .prt_ack(ddr_wr_ack) +); + +processing_system7_vip_v1_0_16_arb_rd ddr_hp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_hp2), + .qos2(r_qos_hp3), + .prt_req1(rd_req_ddr_hp2), + .prt_req2(rd_req_ddr_hp3), + .prt_data1(rd_data_ddr_hp2), + .prt_data2(rd_data_ddr_hp3), + .prt_addr1(rd_addr_hp2), + .prt_addr2(rd_addr_hp3), + .prt_bytes1(rd_bytes_hp2), + .prt_bytes2(rd_bytes_hp3), + .prt_dv1(rd_dv_ddr_hp2), + .prt_dv2(rd_dv_ddr_hp3), + .prt_req(ddr_rd_req), + .prt_qos(ddr_rd_qos), + .prt_data(ddr_rd_data), + .prt_addr(ddr_rd_addr), + .prt_bytes(ddr_rd_bytes), + .prt_dv(ddr_rd_dv) +); + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_arb_hp0_1.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between RD/WR requests from 2 ports. + * Used for modelling the Top_Interconnect switch. + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_arb_hp0_1( + sw_clk, + rstn, + w_qos_hp0, + r_qos_hp0, + w_qos_hp1, + r_qos_hp1, + + wr_ack_ddr_hp0, + wr_data_hp0, + wr_strb_hp0, + wr_addr_hp0, + wr_bytes_hp0, + wr_dv_ddr_hp0, + rd_req_ddr_hp0, + rd_addr_hp0, + rd_bytes_hp0, + rd_data_ddr_hp0, + rd_dv_ddr_hp0, + + wr_ack_ddr_hp1, + wr_data_hp1, + wr_strb_hp1, + wr_addr_hp1, + wr_bytes_hp1, + wr_dv_ddr_hp1, + rd_req_ddr_hp1, + rd_addr_hp1, + rd_bytes_hp1, + rd_data_ddr_hp1, + rd_dv_ddr_hp1, + + ddr_wr_ack, + ddr_wr_dv, + ddr_rd_req, + ddr_rd_dv, + ddr_rd_qos, + ddr_wr_qos, + + ddr_wr_addr, + ddr_wr_data, + ddr_wr_strb, + ddr_wr_bytes, + ddr_rd_addr, + ddr_rd_data, + ddr_rd_bytes + +); +`include "processing_system7_vip_v1_0_16_local_params.v" +input sw_clk; +input rstn; +input [axi_qos_width-1:0] w_qos_hp0; +input [axi_qos_width-1:0] r_qos_hp0; +input [axi_qos_width-1:0] w_qos_hp1; +input [axi_qos_width-1:0] r_qos_hp1; +input [axi_qos_width-1:0] ddr_rd_qos; +input [axi_qos_width-1:0] ddr_wr_qos; + +output wr_ack_ddr_hp0; +input [max_burst_bits-1:0] wr_data_hp0; +input [max_burst_bytes-1:0] wr_strb_hp0; +input [addr_width-1:0] wr_addr_hp0; +input [max_burst_bytes_width:0] wr_bytes_hp0; +output wr_dv_ddr_hp0; + +input rd_req_ddr_hp0; +input [addr_width-1:0] rd_addr_hp0; +input [max_burst_bytes_width:0] rd_bytes_hp0; +output [max_burst_bits-1:0] rd_data_ddr_hp0; +output rd_dv_ddr_hp0; + +output wr_ack_ddr_hp1; +input [max_burst_bits-1:0] wr_data_hp1; +input [max_burst_bytes-1:0] wr_strb_hp1; +input [addr_width-1:0] wr_addr_hp1; +input [max_burst_bytes_width:0] wr_bytes_hp1; +output wr_dv_ddr_hp1; + +input rd_req_ddr_hp1; +input [addr_width-1:0] rd_addr_hp1; +input [max_burst_bytes_width:0] rd_bytes_hp1; +output [max_burst_bits-1:0] rd_data_ddr_hp1; +output rd_dv_ddr_hp1; + +input ddr_wr_ack; +output ddr_wr_dv; +output [addr_width-1:0]ddr_wr_addr; +output [max_burst_bits-1:0]ddr_wr_data; +output [max_burst_bytes-1:0]ddr_wr_strb; +output [max_burst_bytes_width:0]ddr_wr_bytes; + +input ddr_rd_dv; +input [max_burst_bits-1:0] ddr_rd_data; +output ddr_rd_req; +output [addr_width-1:0] ddr_rd_addr; +output [max_burst_bytes_width:0] ddr_rd_bytes; + + + + +processing_system7_vip_v1_0_16_arb_wr ddr_hp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_hp0), + .qos2(w_qos_hp1), + .prt_dv1(wr_dv_ddr_hp0), + .prt_dv2(wr_dv_ddr_hp1), + .prt_data1(wr_data_hp0), + .prt_data2(wr_data_hp1), + .prt_strb1(wr_strb_hp0), + .prt_strb2(wr_strb_hp1), + .prt_addr1(wr_addr_hp0), + .prt_addr2(wr_addr_hp1), + .prt_bytes1(wr_bytes_hp0), + .prt_bytes2(wr_bytes_hp1), + .prt_ack1(wr_ack_ddr_hp0), + .prt_ack2(wr_ack_ddr_hp1), + .prt_req(ddr_wr_dv), + .prt_qos(ddr_wr_qos), + .prt_data(ddr_wr_data), + .prt_strb(ddr_wr_strb), + .prt_addr(ddr_wr_addr), + .prt_bytes(ddr_wr_bytes), + .prt_ack(ddr_wr_ack) +); + +processing_system7_vip_v1_0_16_arb_rd ddr_hp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_hp0), + .qos2(r_qos_hp1), + .prt_req1(rd_req_ddr_hp0), + .prt_req2(rd_req_ddr_hp1), + .prt_data1(rd_data_ddr_hp0), + .prt_data2(rd_data_ddr_hp1), + .prt_addr1(rd_addr_hp0), + .prt_addr2(rd_addr_hp1), + .prt_bytes1(rd_bytes_hp0), + .prt_bytes2(rd_bytes_hp1), + .prt_dv1(rd_dv_ddr_hp0), + .prt_dv2(rd_dv_ddr_hp1), + .prt_qos(ddr_rd_qos), + .prt_req(ddr_rd_req), + .prt_data(ddr_rd_data), + .prt_addr(ddr_rd_addr), + .prt_bytes(ddr_rd_bytes), + .prt_dv(ddr_rd_dv) +); + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_ssw_hp.v + * + * Date : 2012-11 + * + * Description : SSW switch Model + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_ssw_hp( + sw_clk, + rstn, + w_qos_hp0, + r_qos_hp0, + w_qos_hp1, + r_qos_hp1, + w_qos_hp2, + r_qos_hp2, + w_qos_hp3, + r_qos_hp3, + + wr_ack_ddr_hp0, + wr_data_hp0, + wr_strb_hp0, + wr_addr_hp0, + wr_bytes_hp0, + wr_dv_ddr_hp0, + rd_req_ddr_hp0, + rd_addr_hp0, + rd_bytes_hp0, + rd_data_ddr_hp0, + rd_dv_ddr_hp0, + + rd_data_ocm_hp0, + wr_ack_ocm_hp0, + wr_dv_ocm_hp0, + rd_req_ocm_hp0, + rd_dv_ocm_hp0, + + wr_ack_ddr_hp1, + wr_data_hp1, + wr_strb_hp1, + wr_addr_hp1, + wr_bytes_hp1, + wr_dv_ddr_hp1, + rd_req_ddr_hp1, + rd_addr_hp1, + rd_bytes_hp1, + rd_data_ddr_hp1, + rd_data_ocm_hp1, + rd_dv_ddr_hp1, + + wr_ack_ocm_hp1, + wr_dv_ocm_hp1, + rd_req_ocm_hp1, + rd_dv_ocm_hp1, + + wr_ack_ddr_hp2, + wr_data_hp2, + wr_strb_hp2, + wr_addr_hp2, + wr_bytes_hp2, + wr_dv_ddr_hp2, + rd_req_ddr_hp2, + rd_addr_hp2, + rd_bytes_hp2, + rd_data_ddr_hp2, + rd_data_ocm_hp2, + rd_dv_ddr_hp2, + + wr_ack_ocm_hp2, + wr_dv_ocm_hp2, + rd_req_ocm_hp2, + rd_dv_ocm_hp2, + + wr_ack_ddr_hp3, + wr_data_hp3, + wr_strb_hp3, + wr_addr_hp3, + wr_bytes_hp3, + wr_dv_ddr_hp3, + rd_req_ddr_hp3, + rd_addr_hp3, + rd_bytes_hp3, + rd_data_ocm_hp3, + rd_data_ddr_hp3, + rd_dv_ddr_hp3, + + wr_ack_ocm_hp3, + wr_dv_ocm_hp3, + rd_req_ocm_hp3, + rd_dv_ocm_hp3, + + ddr_wr_ack0, + ddr_wr_dv0, + ddr_rd_req0, + ddr_rd_dv0, + ddr_rd_qos0, + ddr_wr_qos0, + + ddr_wr_addr0, + ddr_wr_data0, + ddr_wr_strb0, + ddr_wr_bytes0, + ddr_rd_addr0, + ddr_rd_data0, + ddr_rd_bytes0, + + ddr_wr_ack1, + ddr_wr_dv1, + ddr_rd_req1, + ddr_rd_dv1, + ddr_rd_qos1, + ddr_wr_qos1, + ddr_wr_addr1, + ddr_wr_data1, + ddr_wr_strb1, + ddr_wr_bytes1, + ddr_rd_addr1, + ddr_rd_data1, + ddr_rd_bytes1, + + ocm_wr_ack, + ocm_wr_dv, + ocm_rd_req, + ocm_rd_dv, + + ocm_wr_qos, + ocm_rd_qos, + ocm_wr_addr, + ocm_wr_data, + ocm_wr_strb, + ocm_wr_bytes, + ocm_rd_addr, + ocm_rd_data, + ocm_rd_bytes + + + +); + +input sw_clk; +input rstn; +input [3:0] w_qos_hp0; +input [3:0] r_qos_hp0; +input [3:0] w_qos_hp1; +input [3:0] r_qos_hp1; +input [3:0] w_qos_hp2; +input [3:0] r_qos_hp2; +input [3:0] w_qos_hp3; +input [3:0] r_qos_hp3; + +output [3:0] ddr_rd_qos0; +output [3:0] ddr_wr_qos0; +output [3:0] ddr_rd_qos1; +output [3:0] ddr_wr_qos1; +output [3:0] ocm_wr_qos; +output [3:0] ocm_rd_qos; + +output wr_ack_ddr_hp0; +input [1023:0] wr_data_hp0; +input [127:0] wr_strb_hp0; +input [31:0] wr_addr_hp0; +input [7:0] wr_bytes_hp0; +output wr_dv_ddr_hp0; + +input rd_req_ddr_hp0; +input [31:0] rd_addr_hp0; +input [7:0] rd_bytes_hp0; +output [1023:0] rd_data_ddr_hp0; +output rd_dv_ddr_hp0; + +output wr_ack_ddr_hp1; +input [1023:0] wr_data_hp1; +input [127:0] wr_strb_hp1; +input [31:0] wr_addr_hp1; +input [7:0] wr_bytes_hp1; +output wr_dv_ddr_hp1; + +input rd_req_ddr_hp1; +input [31:0] rd_addr_hp1; +input [7:0] rd_bytes_hp1; +output [1023:0] rd_data_ddr_hp1; +output rd_dv_ddr_hp1; + +output wr_ack_ddr_hp2; +input [1023:0] wr_data_hp2; +input [127:0] wr_strb_hp2; +input [31:0] wr_addr_hp2; +input [7:0] wr_bytes_hp2; +output wr_dv_ddr_hp2; + +input rd_req_ddr_hp2; +input [31:0] rd_addr_hp2; +input [7:0] rd_bytes_hp2; +output [1023:0] rd_data_ddr_hp2; +output rd_dv_ddr_hp2; + +output wr_ack_ddr_hp3; +input [1023:0] wr_data_hp3; +input [127:0] wr_strb_hp3; +input [31:0] wr_addr_hp3; +input [7:0] wr_bytes_hp3; +output wr_dv_ddr_hp3; + +input rd_req_ddr_hp3; +input [31:0] rd_addr_hp3; +input [7:0] rd_bytes_hp3; +output [1023:0] rd_data_ddr_hp3; +output rd_dv_ddr_hp3; + +input ddr_wr_ack0; +output ddr_wr_dv0; +output [31:0]ddr_wr_addr0; +output [1023:0]ddr_wr_data0; +output [127:0]ddr_wr_strb0; +output [7:0]ddr_wr_bytes0; + +input ddr_rd_dv0; +input [1023:0] ddr_rd_data0; +output ddr_rd_req0; +output [31:0] ddr_rd_addr0; +output [7:0] ddr_rd_bytes0; + +input ddr_wr_ack1; +output ddr_wr_dv1; +output [31:0]ddr_wr_addr1; +output [1023:0]ddr_wr_data1; +output [127:0]ddr_wr_strb1; +output [7:0]ddr_wr_bytes1; + +input ddr_rd_dv1; +input [1023:0] ddr_rd_data1; +output ddr_rd_req1; +output [31:0] ddr_rd_addr1; +output [7:0] ddr_rd_bytes1; + +output wr_ack_ocm_hp0; +input wr_dv_ocm_hp0; +input rd_req_ocm_hp0; +output rd_dv_ocm_hp0; +output [1023:0] rd_data_ocm_hp0; + +output wr_ack_ocm_hp1; +input wr_dv_ocm_hp1; +input rd_req_ocm_hp1; +output rd_dv_ocm_hp1; +output [1023:0] rd_data_ocm_hp1; + +output wr_ack_ocm_hp2; +input wr_dv_ocm_hp2; +input rd_req_ocm_hp2; +output rd_dv_ocm_hp2; +output [1023:0] rd_data_ocm_hp2; + +output wr_ack_ocm_hp3; +input wr_dv_ocm_hp3; +input rd_req_ocm_hp3; +output rd_dv_ocm_hp3; +output [1023:0] rd_data_ocm_hp3; + +input ocm_wr_ack; +output ocm_wr_dv; +output [31:0]ocm_wr_addr; +output [1023:0]ocm_wr_data; +output [127:0]ocm_wr_strb; +output [7:0]ocm_wr_bytes; + +input ocm_rd_dv; +input [1023:0] ocm_rd_data; +output ocm_rd_req; +output [31:0] ocm_rd_addr; +output [7:0] ocm_rd_bytes; + +/* FOR DDR */ +processing_system7_vip_v1_0_16_arb_hp0_1 ddr_hp01 ( + .sw_clk(sw_clk), + .rstn(rstn), + .w_qos_hp0(w_qos_hp0), + .r_qos_hp0(r_qos_hp0), + .w_qos_hp1(w_qos_hp1), + .r_qos_hp1(r_qos_hp1), + + .wr_ack_ddr_hp0(wr_ack_ddr_hp0), + .wr_data_hp0(wr_data_hp0), + .wr_strb_hp0(wr_strb_hp0), + .wr_addr_hp0(wr_addr_hp0), + .wr_bytes_hp0(wr_bytes_hp0), + .wr_dv_ddr_hp0(wr_dv_ddr_hp0), + .rd_req_ddr_hp0(rd_req_ddr_hp0), + .rd_addr_hp0(rd_addr_hp0), + .rd_bytes_hp0(rd_bytes_hp0), + .rd_data_ddr_hp0(rd_data_ddr_hp0), + .rd_dv_ddr_hp0(rd_dv_ddr_hp0), + + .wr_ack_ddr_hp1(wr_ack_ddr_hp1), + .wr_data_hp1(wr_data_hp1), + .wr_strb_hp1(wr_strb_hp1), + .wr_addr_hp1(wr_addr_hp1), + .wr_bytes_hp1(wr_bytes_hp1), + .wr_dv_ddr_hp1(wr_dv_ddr_hp1), + .rd_req_ddr_hp1(rd_req_ddr_hp1), + .rd_addr_hp1(rd_addr_hp1), + .rd_bytes_hp1(rd_bytes_hp1), + .rd_data_ddr_hp1(rd_data_ddr_hp1), + .rd_dv_ddr_hp1(rd_dv_ddr_hp1), + + .ddr_wr_ack(ddr_wr_ack0), + .ddr_wr_dv(ddr_wr_dv0), + .ddr_rd_req(ddr_rd_req0), + .ddr_rd_dv(ddr_rd_dv0), + .ddr_rd_qos(ddr_rd_qos0), + .ddr_wr_qos(ddr_wr_qos0), + .ddr_wr_addr(ddr_wr_addr0), + .ddr_wr_data(ddr_wr_data0), + .ddr_wr_strb(ddr_wr_strb0), + .ddr_wr_bytes(ddr_wr_bytes0), + .ddr_rd_addr(ddr_rd_addr0), + .ddr_rd_data(ddr_rd_data0), + .ddr_rd_bytes(ddr_rd_bytes0) +); + +/* FOR DDR */ +processing_system7_vip_v1_0_16_arb_hp2_3 ddr_hp23 ( + .sw_clk(sw_clk), + .rstn(rstn), + .w_qos_hp2(w_qos_hp2), + .r_qos_hp2(r_qos_hp2), + .w_qos_hp3(w_qos_hp3), + .r_qos_hp3(r_qos_hp3), + + .wr_ack_ddr_hp2(wr_ack_ddr_hp2), + .wr_data_hp2(wr_data_hp2), + .wr_strb_hp2(wr_strb_hp2), + .wr_addr_hp2(wr_addr_hp2), + .wr_bytes_hp2(wr_bytes_hp2), + .wr_dv_ddr_hp2(wr_dv_ddr_hp2), + .rd_req_ddr_hp2(rd_req_ddr_hp2), + .rd_addr_hp2(rd_addr_hp2), + .rd_bytes_hp2(rd_bytes_hp2), + .rd_data_ddr_hp2(rd_data_ddr_hp2), + .rd_dv_ddr_hp2(rd_dv_ddr_hp2), + + .wr_ack_ddr_hp3(wr_ack_ddr_hp3), + .wr_data_hp3(wr_data_hp3), + .wr_strb_hp3(wr_strb_hp3), + .wr_addr_hp3(wr_addr_hp3), + .wr_bytes_hp3(wr_bytes_hp3), + .wr_dv_ddr_hp3(wr_dv_ddr_hp3), + .rd_req_ddr_hp3(rd_req_ddr_hp3), + .rd_addr_hp3(rd_addr_hp3), + .rd_bytes_hp3(rd_bytes_hp3), + .rd_data_ddr_hp3(rd_data_ddr_hp3), + .rd_dv_ddr_hp3(rd_dv_ddr_hp3), + + .ddr_wr_ack(ddr_wr_ack1), + .ddr_wr_dv(ddr_wr_dv1), + .ddr_rd_req(ddr_rd_req1), + .ddr_rd_dv(ddr_rd_dv1), + .ddr_rd_qos(ddr_rd_qos1), + .ddr_wr_qos(ddr_wr_qos1), + + .ddr_wr_addr(ddr_wr_addr1), + .ddr_wr_data(ddr_wr_data1), + .ddr_wr_strb(ddr_wr_strb1), + .ddr_wr_bytes(ddr_wr_bytes1), + .ddr_rd_addr(ddr_rd_addr1), + .ddr_rd_data(ddr_rd_data1), + .ddr_rd_bytes(ddr_rd_bytes1) +); + + +/* FOR OCM_WR */ +processing_system7_vip_v1_0_16_arb_wr_4 ocm_wr_hp( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(w_qos_hp0), + .qos2(w_qos_hp1), + .qos3(w_qos_hp2), + .qos4(w_qos_hp3), + + .prt_dv1(wr_dv_ocm_hp0), + .prt_dv2(wr_dv_ocm_hp1), + .prt_dv3(wr_dv_ocm_hp2), + .prt_dv4(wr_dv_ocm_hp3), + + .prt_data1(wr_data_hp0), + .prt_data2(wr_data_hp1), + .prt_data3(wr_data_hp2), + .prt_data4(wr_data_hp3), + + .prt_strb1(wr_strb_hp0), + .prt_strb2(wr_strb_hp1), + .prt_strb3(wr_strb_hp2), + .prt_strb4(wr_strb_hp3), + + .prt_addr1(wr_addr_hp0), + .prt_addr2(wr_addr_hp1), + .prt_addr3(wr_addr_hp2), + .prt_addr4(wr_addr_hp3), + + .prt_bytes1(wr_bytes_hp0), + .prt_bytes2(wr_bytes_hp1), + .prt_bytes3(wr_bytes_hp2), + .prt_bytes4(wr_bytes_hp3), + + .prt_ack1(wr_ack_ocm_hp0), + .prt_ack2(wr_ack_ocm_hp1), + .prt_ack3(wr_ack_ocm_hp2), + .prt_ack4(wr_ack_ocm_hp3), + + .prt_qos(ocm_wr_qos), + .prt_req(ocm_wr_dv), + .prt_data(ocm_wr_data), + .prt_strb(ocm_wr_strb), + .prt_addr(ocm_wr_addr), + .prt_bytes(ocm_wr_bytes), + .prt_ack(ocm_wr_ack) + +); + +/* FOR OCM_RD */ +processing_system7_vip_v1_0_16_arb_rd_4 ocm_rd_hp( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(r_qos_hp0), + .qos2(r_qos_hp1), + .qos3(r_qos_hp2), + .qos4(r_qos_hp3), + + .prt_req1(rd_req_ocm_hp0), + .prt_req2(rd_req_ocm_hp1), + .prt_req3(rd_req_ocm_hp2), + .prt_req4(rd_req_ocm_hp3), + + .prt_data1(rd_data_ocm_hp0), + .prt_data2(rd_data_ocm_hp1), + .prt_data3(rd_data_ocm_hp2), + .prt_data4(rd_data_ocm_hp3), + + .prt_addr1(rd_addr_hp0), + .prt_addr2(rd_addr_hp1), + .prt_addr3(rd_addr_hp2), + .prt_addr4(rd_addr_hp3), + + .prt_bytes1(rd_bytes_hp0), + .prt_bytes2(rd_bytes_hp1), + .prt_bytes3(rd_bytes_hp2), + .prt_bytes4(rd_bytes_hp3), + + .prt_dv1(rd_dv_ocm_hp0), + .prt_dv2(rd_dv_ocm_hp1), + .prt_dv3(rd_dv_ocm_hp2), + .prt_dv4(rd_dv_ocm_hp3), + + .prt_qos(ocm_rd_qos), + .prt_req(ocm_rd_req), + .prt_data(ocm_rd_data), + .prt_addr(ocm_rd_addr), + .prt_bytes(ocm_rd_bytes), + .prt_dv(ocm_rd_dv) + +); + + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_sparse_mem.v + * + * Date : 2012-11 + * + * Description : Sparse Memory Model + * + *****************************************************************************/ + +/*** WA for CR # 695818 ***/ +`ifdef XILINX_SIMULATOR + `define XSIM_ISIM +`endif +`ifdef XILINX_ISIM + `define XSIM_ISIM +`endif + + `timescale 1ns/1ps +module processing_system7_vip_v1_0_16_sparse_mem(); + +`include "processing_system7_vip_v1_0_16_local_params.v" + +parameter mem_size = 32'h4000_0000; /// 1GB mem size +parameter xsim_mem_size = 32'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM) +bit DEBUG_INFO = 1; + +// `ifdef XSIM_ISIM +// reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +// reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +// reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +// reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +// reg [data_width-1:0] ddr_mem4 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +// reg [data_width-1:0] ddr_mem5 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +// reg [data_width-1:0] ddr_mem6 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +// reg [data_width-1:0] ddr_mem7 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +// `else + reg /*sparse*/ [data_width-1:0] ddr_mem0 [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem + reg /*sparse*/ [data_width-1:0] ddr_mem1 [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem +// `endif + +event mem_updated; +reg check_we; +reg [addr_width-1:0] check_up_add; +reg [data_width-1:0] updated_data; + +/* preload memory from file */ +// task automatic pre_load_mem_from_file; +// input [(max_chars*8)-1:0] file_name; +// input [addr_width-1:0] start_addr; +// input [int_width-1:0] no_of_bytes; +// `ifdef XSIM_ISIM +// case(start_addr[31:28]) +// 4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits); +// 4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits); +// 4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits); +// 4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits); +// endcase +// `else +// $readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits); +// `endif +// endtask + +/* preload memory from file */ +task automatic pre_load_mem_from_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +logic [31:0] addr; +// reg /*sparse*/ [data_width-1:0] ddr_mem0_temp [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem +// reg /*sparse*/ [data_width-1:0] ddr_mem1_temp [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem + +// `ifdef XSIM_ISIM +// if (start_addr[35:32] == 4'h0) begin +// case(start_addr[31:28]) +// 4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits); +// 4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits); +// 4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits); +// 4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits); +// endcase +// end else if (start_addr[35:32] == 4'h8) begin +// case(start_addr[31:28]) +// 4'd0 : $readmemh(file_name,ddr_mem4,start_addr>>shft_addr_bits); +// 4'd1 : $readmemh(file_name,ddr_mem5,start_addr>>shft_addr_bits); +// 4'd2 : $readmemh(file_name,ddr_mem6,start_addr>>shft_addr_bits); +// 4'd3 : $readmemh(file_name,ddr_mem7,start_addr>>shft_addr_bits); +// endcase +// end +// `else +// if (start_addr[31:28] == 4'h0) begin +// $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits); +// end else if (start_addr[31:28] == 4'h8) begin +// $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits); +// end +// `endif +addr = start_addr>>shft_addr_bits; +// if(addr[28] == 1'h0) begin +// $display(" pre_load_mem_from_file11 entered"); +// // $readmemh(file_name,ddr_mem0,addr[27:0]); +// $readmemh(file_name,ddr_mem0_temp,start_addr>>shft_addr_bits); +// for (int i = 0; i < no_of_bytes; i = i + 1) begin +// ddr_mem0[(start_addr>>shft_addr_bits) + i] = ddr_mem0_temp[(start_addr>>shft_addr_bits) + i]; +// end +// end else begin +// $display(" pre_load_mem_from_file222 entered"); +// // $readmemh(file_name,ddr_mem1,addr[27:0]); +// $readmemh(file_name,ddr_mem1_temp,start_addr>>shft_addr_bits); +// for (int i = 0; i < no_of_bytes; i = i + 1) begin +// ddr_mem1[(start_addr>>shft_addr_bits) + i] = ddr_mem1_temp[(start_addr>>shft_addr_bits) + i]; +// end +// end + if(addr[28] == 1'h0) begin + if(DEBUG_INFO) $display(" pre_load_mem_from_file11 entered"); + $readmemh(file_name,ddr_mem0,addr[27:0],addr[27:0]+(no_of_bytes-1)); + end else begin + if(DEBUG_INFO) $display(" pre_load_mem_from_file222 entered"); + $readmemh(file_name,ddr_mem1,addr[27:0],addr[27:0]+(no_of_bytes-1)); + end +endtask + + +/* preload memory with some random data */ +// task automatic pre_load_mem; +// input [1:0] data_type; +// input [addr_width-1:0] start_addr; +// input [int_width-1:0] no_of_bytes; +// integer i; +// reg [addr_width-1:0] addr; +// begin +// addr = start_addr >> shft_addr_bits; +// for (i = 0; i < no_of_bytes; i = i + mem_width) begin +// case(data_type) +// ALL_RANDOM : set_data(addr , $random); +// ALL_ZEROS : set_data(addr , 32'h0000_0000); +// ALL_ONES : set_data(addr , 32'hFFFF_FFFF); +// default : set_data(addr , $random); +// endcase +// addr = addr+1; +// end +// end +// endtask + +/* preload memory with some random data */ +task automatic pre_load_mem; +input [1:0] data_type; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +integer i; +reg [addr_width-1:0] addr; +begin +addr = start_addr >> shft_addr_bits; +for (i = 0; i < no_of_bytes; i = i + mem_width) begin + case(data_type) + ALL_RANDOM : set_data(addr , $random, 4'hF); + ALL_ZEROS : set_data(addr , 32'h0000_0000, 4'hF); + ALL_ONES : set_data(addr , 32'hFFFF_FFFF, 4'hF); + default : set_data(addr , $random, 4'hF); + endcase + addr = addr+1; +end +end +endtask + + +/* wait for memory update at certain location */ +task automatic wait_mem_update; +input[addr_width-1:0] address; +output[data_width-1:0] dataout; +begin + check_up_add = address >> shft_addr_bits; + check_we = 1; + @(mem_updated); + dataout = updated_data; + check_we = 0; +end +endtask + +/* internal task to write data in memory */ +// task automatic set_data; +// input [addr_width-1:0] addr; +// input [data_width-1:0] data; +// begin +// if(check_we && (addr === check_up_add)) begin +// updated_data = data; +// -> mem_updated; +// end +// `ifdef XSIM_ISIM +// case(addr[31:26]) +// 6'd0 : ddr_mem0[addr[25:0]] = data; +// 6'd1 : ddr_mem1[addr[25:0]] = data; +// 6'd2 : ddr_mem2[addr[25:0]] = data; +// 6'd3 : ddr_mem3[addr[25:0]] = data; +// endcase +// `else +// ddr_mem[addr] = data; +// `endif +// end +// endtask + + +/* internal task to write data in memory */ +task automatic set_data; +input [addr_width-1:0] addr; +input [data_width-1:0] data; +input [(data_width/8)-1:0] strb; +begin +//$display("set_data ddr addr %0h data %0h strb %0h data_width %0d strb %0h",addr,data,strb,strb,data_width,strb); +if(check_we && (addr === check_up_add)) begin + updated_data = data; + -> mem_updated; +end +// `ifdef XSIM_ISIM +// // if (addr[35:30] == 6'h0) begin +// case(addr[31:26]) +// 6'd0 : begin +// if (strb[0] == 1'b1) ddr_mem0[addr[25:0]][7:0] = data[7:0]; +// if (strb[1] == 1'b1) ddr_mem0[addr[25:0]][15:8] = data[15:8]; +// if (strb[2] == 1'b1) ddr_mem0[addr[25:0]][23:16] = data[23:16]; +// if (strb[3] == 1'b1) ddr_mem0[addr[25:0]][31:24] = data[31:24]; +// end +// 6'd1 : begin +// if (strb[0] == 1'b1) ddr_mem1[addr[25:0]][7:0] = data[7:0]; +// if (strb[1] == 1'b1) ddr_mem1[addr[25:0]][15:8] = data[15:8]; +// if (strb[2] == 1'b1) ddr_mem1[addr[25:0]][23:16] = data[23:16]; +// if (strb[3] == 1'b1) ddr_mem1[addr[25:0]][31:24] = data[31:24]; +// end +// 6'd2 : begin +// if (strb[0] == 1'b1) ddr_mem2[addr[25:0]][7:0] = data[7:0]; +// if (strb[1] == 1'b1) ddr_mem2[addr[25:0]][15:8] = data[15:8]; +// if (strb[2] == 1'b1) ddr_mem2[addr[25:0]][23:16] = data[23:16]; +// if (strb[3] == 1'b1) ddr_mem2[addr[25:0]][31:24] = data[31:24]; +// end +// 6'd3 : begin +// if (strb[0] == 1'b1) ddr_mem3[addr[25:0]][7:0] = data[7:0]; +// if (strb[1] == 1'b1) ddr_mem3[addr[25:0]][15:8] = data[15:8]; +// if (strb[2] == 1'b1) ddr_mem3[addr[25:0]][23:16] = data[23:16]; +// if (strb[3] == 1'b1) ddr_mem3[addr[25:0]][31:24] = data[31:24]; +// end +// endcase +// end else if (addr[35:30] == 6'h8) begin +// case(addr[31:26]) +// 6'd0 : begin +// if (strb[0] == 1'b1) ddr_mem4[addr[25:0]][7:0] = data[7:0]; +// if (strb[1] == 1'b1) ddr_mem4[addr[25:0]][15:8] = data[15:8]; +// if (strb[2] == 1'b1) ddr_mem4[addr[25:0]][23:16] = data[23:16]; +// if (strb[3] == 1'b1) ddr_mem4[addr[25:0]][31:24] = data[31:24]; +// end +// 6'd1 : begin +// if (strb[0] == 1'b1) ddr_mem5[addr[25:0]][7:0] = data[7:0]; +// if (strb[1] == 1'b1) ddr_mem5[addr[25:0]][15:8] = data[15:8]; +// if (strb[2] == 1'b1) ddr_mem5[addr[25:0]][23:16] = data[23:16]; +// if (strb[3] == 1'b1) ddr_mem5[addr[25:0]][31:24] = data[31:24]; +// end +// 6'd2 : begin +// if (strb[0] == 1'b1) ddr_mem6[addr[25:0]][7:0] = data[7:0]; +// if (strb[1] == 1'b1) ddr_mem6[addr[25:0]][15:8] = data[15:8]; +// if (strb[2] == 1'b1) ddr_mem6[addr[25:0]][23:16] = data[23:16]; +// if (strb[3] == 1'b1) ddr_mem6[addr[25:0]][31:24] = data[31:24]; +// end +// 6'd3 : begin +// if (strb[0] == 1'b1) ddr_mem7[addr[25:0]][7:0] = data[7:0]; +// if (strb[1] == 1'b1) ddr_mem7[addr[25:0]][15:8] = data[15:8]; +// if (strb[2] == 1'b1) ddr_mem7[addr[25:0]][23:16] = data[23:16]; +// if (strb[3] == 1'b1) ddr_mem7[addr[25:0]][31:24] = data[31:24]; +// end +// endcase +// end +// `else +// //$display("set_data ddr addr %0h data %0h strb %0h data_width %0h addr[31:30] %0h",addr,data,strb,strb,data_width,addr[31:30]); +// if (addr[31:30] === 6'h0) begin +// // $display("set_data ddr addr %0h data %0h strb %0h data_width %0d strb %0h addr[31:30] is zero",addr,data,strb,strb,data_width,strb); +// if (strb[0] == 1'b1) ddr_mem0[addr[25:0]][7:0] = data[7:0]; +// //$display("ddr addr %0h data %0h ddr_mem0[%0h][7:0] %0h strb[0] %0b ",addr,data,addr,ddr_mem0[addr[25:0]][7:0],strb[0]); +// if (strb[1] == 1'b1) ddr_mem0[addr[25:0]][15:8] = data[15:8]; +// //$display("ddr addr %0h data %0h ddr_mem0[%0h][15:8] %0h strb[1] %0b ",addr,data,addr,ddr_mem0[addr[25:0]][15:8],strb[1]); +// if (strb[2] == 1'b1) ddr_mem0[addr[25:0]][23:16] = data[23:16]; +// //$display("ddr addr %0h data %0h ddr_mem0[%0h][23:16] %0h strb[2] %0b ",addr,data,addr,ddr_mem0[addr[25:0]][23:16],strb[2]); +// if (strb[3] == 1'b1) ddr_mem0[addr[25:0]][31:24] = data[31:24]; +// //$display("ddr addr %0h data %0h ddr_mem0[%0h][31:24] %0h strb[3] %0b ",addr,data,addr,ddr_mem0[addr[25:0]][31:24],strb[3]); +//// ddr_mem0[addr[25:0]] = data ; +// //$display("ddr addr %0h data %0h ddr_mem0[%0h] %0h",addr,data,addr,ddr_mem0[addr[25:0]]); +// //$display("ddr addr %0h data %0h ddr_mem0[%0h][7:0] %0h",addr,data,addr,ddr_mem0[addr[25:0]][7:0]); +// end else if (addr[31:30] == 6'h8) begin +// //$display("set_data ddr addr %0h data %0h strb %0h data_width %0d strb %0h addr[31:30] is 8",addr,data,strb,strb,data_width,strb); +// if (strb[0] == 1'b1) ddr_mem1[addr[25:0]][7:0] = data[7:0];// +// if (strb[1] == 1'b1) ddr_mem1[addr[25:0]][15:8] = data[15:8]; +// if (strb[2] == 1'b1) ddr_mem1[addr[25:0]][23:16] = data[23:16]; +// if (strb[3] == 1'b1) ddr_mem1[addr[25:0]][31:24] = data[31:24]; +// end +// `endif + if (addr[28] == 1'h0) begin + if (strb[0] == 1'b1) ddr_mem0[addr[27:0]][7:0] = data[7:0]; + if (strb[1] == 1'b1) ddr_mem0[addr[27:0]][15:8] = data[15:8]; + if (strb[2] == 1'b1) ddr_mem0[addr[27:0]][23:16] = data[23:16]; + if (strb[3] == 1'b1) ddr_mem0[addr[27:0]][31:24] = data[31:24]; + end else begin + if (strb[0] == 1'b1) ddr_mem1[addr[27:0]][7:0] = data[7:0]; + if (strb[1] == 1'b1) ddr_mem1[addr[27:0]][15:8] = data[15:8]; + if (strb[2] == 1'b1) ddr_mem1[addr[27:0]][23:16] = data[23:16]; + if (strb[3] == 1'b1) ddr_mem1[addr[27:0]][31:24] = data[31:24]; + end +end +endtask + + + +/* internal task to read data from memory */ +// task automatic get_data; +// input [addr_width-1:0] addr; +// output [data_width-1:0] data; +// begin +// `ifdef XSIM_ISIM +// case(addr[31:26]) +// 6'd0 : data = ddr_mem0[addr[25:0]]; +// 6'd1 : data = ddr_mem1[addr[25:0]]; +// 6'd2 : data = ddr_mem2[addr[25:0]]; +// 6'd3 : data = ddr_mem3[addr[25:0]]; +// endcase +// `else +// data = ddr_mem[addr]; +// `endif +// end +// endtask + +/* internal task to read data from memory */ +task automatic get_data; +input [addr_width-1:0] addr; +output [data_width-1:0] data; +begin +// `ifdef XSIM_ISIM +// if (addr[35:30] == 6'h0) begin +// case(addr[31:26]) +// 6'd0 : data = ddr_mem0[addr[25:0]]; +// 6'd1 : data = ddr_mem1[addr[25:0]]; +// 6'd2 : data = ddr_mem2[addr[25:0]]; +// 6'd3 : data = ddr_mem3[addr[25:0]]; +// endcase +// end else if (addr[35:30] == 6'h8) begin +// case(addr[31:26]) +// 6'd0 : data = ddr_mem4[addr[25:0]]; +// //$display("addr %0h data %0h ddr_mem0[%0h][7:0] %0h strb[0] %0b ",addr,data,addr,ddr_mem0[addr[25:0]][7:0],strb[0]); +// 6'd1 : data = ddr_mem5[addr[25:0]]; +// //$display("addr %0h data %0h ddr_mem0[%0h][15:8] %0h strb[1] %0b ",addr,data,addr,ddr_mem0[addr[25:0]][15:8],strb[1]); +// 6'd2 : data = ddr_mem6[addr[25:0]]; +// //$display("addr %0h data %0h ddr_mem0[%0h][23:16] %0h strb[2] %0b ",addr,data,addr,ddr_mem0[addr[25:0]][23:16],strb[2]); +// 6'd3 : data = ddr_mem7[addr[25:0]]; +// //$display("addr %0h data %0h ddr_mem0[%0h][31:24] %0h strb[3] %0b ",addr,data,addr,ddr_mem0[addr[25:0]][31:24],strb[3]); +// endcase +// end +// `else +// if (addr[31:30] == 6'h0) begin +// data = ddr_mem0[addr[25:0]]; +// //$display(" read addr %0h data %0h ddr_mem0[%0h] %0h ",addr[25:0],data,addr[25:0],ddr_mem0[addr[25:0]]); +// end else if (addr[31:30] == 6'h8) begin +// data = ddr_mem1[addr]; +// end +// `endif + if (addr[28] == 1'h0 ) begin + data = ddr_mem0[addr[27:0]]; + //$display(" ddr_mem0 read addr %0h data %0h ddr_mem0[%0h] %0h ",addr[28:0],data,addr[27:0],ddr_mem0[addr[27:0]]); + end else begin + data = ddr_mem1[addr[27:0]]; + //$display(" ddr_mem1 read addr %0h data %0h ddr_mem1[%0h] %0h ",addr[28:0],data,addr[27:0],ddr_mem1[addr[27:0]]); + end +end +endtask + +/* Write memory */ +// task write_mem; +// input [max_burst_bits-1 :0] data; +// input [addr_width-1:0] start_addr; +// input [max_burst_bytes_width:0] no_of_bytes; +// reg [addr_width-1:0] addr; +// reg [max_burst_bits-1 :0] wr_temp_data; +// reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; +// integer bytes_left; +// integer pre_pad_bytes; +// integer post_pad_bytes; +// begin +// addr = start_addr >> shft_addr_bits; +// wr_temp_data = data; +// +// `ifdef XLNX_INT_DBG +// $display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); +// `endif +// +// temp_data = wr_temp_data[data_width-1:0]; +// bytes_left = no_of_bytes; +// /* when the no. of bytes to be updated is less than mem_width */ +// if(bytes_left < mem_width) begin +// /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ +// if(start_addr[shft_addr_bits-1:0] > 0) begin +// //temp_data = ddr_mem[addr]; +// get_data(addr,temp_data); +// pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; +// repeat(pre_pad_bytes) temp_data = temp_data << 8; +// repeat(pre_pad_bytes) begin +// temp_data = temp_data >> 8; +// temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; +// wr_temp_data = wr_temp_data >> 8; +// end +// bytes_left = bytes_left + pre_pad_bytes; +// end +// /* This is needed for post padding the data ...*/ +// post_pad_bytes = mem_width - bytes_left; +// //post_pad_data = ddr_mem[addr]; +// get_data(addr,post_pad_data); +// repeat(post_pad_bytes) temp_data = temp_data << 8; +// repeat(bytes_left) post_pad_data = post_pad_data >> 8; +// repeat(post_pad_bytes) begin +// temp_data = temp_data >> 8; +// temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; +// post_pad_data = post_pad_data >> 8; +// end +// //ddr_mem[addr] = temp_data; +// set_data(addr,temp_data); +// end else begin +// /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ +// if(start_addr[shft_addr_bits-1:0] > 0) begin +// //temp_data = ddr_mem[addr]; +// get_data(addr,temp_data); +// pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; +// repeat(pre_pad_bytes) temp_data = temp_data << 8; +// repeat(pre_pad_bytes) begin +// temp_data = temp_data >> 8; +// temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; +// wr_temp_data = wr_temp_data >> 8; +// bytes_left = bytes_left -1; +// end +// end else begin +// wr_temp_data = wr_temp_data >> data_width; +// bytes_left = bytes_left - mem_width; +// end +// /* first data word end */ +// //ddr_mem[addr] = temp_data; +// set_data(addr,temp_data); +// addr = addr + 1; +// while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. +// //ddr_mem[addr] = wr_temp_data[data_width-1:0]; +// set_data(addr,wr_temp_data[data_width-1:0]); +// addr = addr+1; +// wr_temp_data = wr_temp_data >> data_width; +// bytes_left = bytes_left - mem_width; +// end +// +// //post_pad_data = ddr_mem[addr]; +// get_data(addr,post_pad_data); +// post_pad_bytes = mem_width - bytes_left; +// /* This is needed for last transfer in unaliged burst */ +// if(bytes_left > 0) begin +// temp_data = wr_temp_data[data_width-1:0]; +// repeat(post_pad_bytes) temp_data = temp_data << 8; +// repeat(bytes_left) post_pad_data = post_pad_data >> 8; +// repeat(post_pad_bytes) begin +// temp_data = temp_data >> 8; +// temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; +// post_pad_data = post_pad_data >> 8; +// end +// //ddr_mem[addr] = temp_data; +// set_data(addr,temp_data); +// end +// end +// `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); +// `endif +// end +// endtask + +/* Write memory */ +task write_mem; +input [max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +input [max_burst_bytes-1:0] strb; +reg [addr_width-1:0] addr; +reg [max_burst_bits-1 :0] wr_temp_data; +reg [max_burst_bytes-1:0] wr_temp_strb; +reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; +reg [(data_width/8)-1:0] pre_pad_strb,post_pad_strb,temp_strb; +integer bytes_left; +integer pre_pad_bytes; +integer post_pad_bytes; +begin +addr = start_addr >> shft_addr_bits; +wr_temp_data = data; +wr_temp_strb = strb; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); +`endif + +temp_data = wr_temp_data[data_width-1:0]; +temp_strb = wr_temp_strb[(data_width/8)-1:0]; +bytes_left = no_of_bytes; +/* when the no. of bytes to be updated is less than mem_width */ +if(bytes_left+start_addr[shft_addr_bits-1:0] < mem_width) begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + //temp_data = ddr_mem[addr]; + get_data(addr,temp_data); + temp_strb = 4'hF; + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) begin + temp_data = temp_data << 8; + temp_strb = temp_strb << 1; + end + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_strb = temp_strb >> 1; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + temp_strb[(data_width/8)-1] = wr_temp_strb[0]; + wr_temp_data = wr_temp_data >> 8; + wr_temp_strb = wr_temp_strb >> 1; + end + bytes_left = bytes_left + pre_pad_bytes; + end + /* This is needed for post padding the data ...*/ + post_pad_bytes = mem_width - bytes_left; + //post_pad_data = ddr_mem[addr]; + get_data(addr,post_pad_data); + post_pad_strb = 4'hF; + repeat(post_pad_bytes) begin + temp_data = temp_data << 8; + temp_strb = temp_strb << 1; + end + repeat(bytes_left) begin + post_pad_data = post_pad_data >> 8; + post_pad_strb = post_pad_strb >> 1; + end + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_strb = temp_strb >> 1; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + temp_strb[(data_width/8)-1] = post_pad_strb[0]; + post_pad_data = post_pad_data >> 8; + post_pad_strb = post_pad_strb >> 1; + end + //ddr_mem[addr] = temp_data; + set_data(addr,temp_data,temp_strb); +end else begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + //temp_data = ddr_mem[addr]; + get_data(addr,temp_data); + temp_strb = 4'hF; + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) begin + temp_data = temp_data << 8; + temp_strb = temp_strb << 1; + end + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_strb = temp_strb >> 1; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + temp_strb[(data_width/8)-1] = wr_temp_strb[0]; + wr_temp_data = wr_temp_data >> 8; + wr_temp_strb = wr_temp_strb >> 1; + bytes_left = bytes_left -1; + end + end else begin + wr_temp_data = wr_temp_data >> data_width; + wr_temp_strb = wr_temp_strb >> data_width/8; + bytes_left = bytes_left - mem_width; + end + /* first data word end */ + //ddr_mem[addr] = temp_data; + set_data(addr,temp_data,temp_strb); + addr = addr + 1; + while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. + //ddr_mem[addr] = wr_temp_data[data_width-1:0]; + set_data(addr,wr_temp_data[data_width-1:0],wr_temp_strb[(data_width/8)-1:0]); + addr = addr+1; + wr_temp_data = wr_temp_data >> data_width; + wr_temp_strb = wr_temp_strb >> data_width/8; + bytes_left = bytes_left - mem_width; + end + + //post_pad_data = ddr_mem[addr]; + get_data(addr,post_pad_data); + post_pad_strb = 4'hF; + post_pad_bytes = mem_width - bytes_left; + /* This is needed for last transfer in unaliged burst */ + if(bytes_left > 0) begin + temp_data = wr_temp_data[data_width-1:0]; + temp_strb = wr_temp_strb[(data_width/8)-1:0]; + repeat(post_pad_bytes) begin + temp_data = temp_data << 8; + temp_strb = temp_strb << 1; + end + repeat(bytes_left) begin + post_pad_data = post_pad_data >> 8; + post_pad_strb = post_pad_strb >> 1; + end + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_strb = temp_strb >> 1; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + temp_strb[(data_width/8)-1] = post_pad_strb[0]; + post_pad_data = post_pad_data >> 8; + post_pad_strb = post_pad_strb >> 1; + end + //ddr_mem[addr] = temp_data; + set_data(addr,temp_data,temp_strb); + end +end +`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); +`endif +end +endtask + + + + +/* read_memory */ +// task read_mem; +// output[max_burst_bits-1 :0] data; +// input [addr_width-1:0] start_addr; +// input [max_burst_bytes_width :0] no_of_bytes; +// integer i; +// reg [addr_width-1:0] addr; +// reg [data_width-1:0] temp_rd_data; +// reg [max_burst_bits-1:0] temp_data; +// integer pre_bytes; +// integer bytes_left; +// begin +// addr = start_addr >> shft_addr_bits; +// pre_bytes = start_addr[shft_addr_bits-1:0]; +// bytes_left = no_of_bytes; +// +// `ifdef XLNX_INT_DBG +// $display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +// `endif +// +// /* Get first data ... if unaligned address */ +// //temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; +// get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); +// +// if(no_of_bytes < mem_width ) begin +// temp_data = temp_data >> (pre_bytes * 8); +// repeat(max_burst_bytes - mem_width) +// temp_data = temp_data >> 8; +// +// end else begin +// bytes_left = bytes_left - (mem_width - pre_bytes); +// addr = addr+1; +// /* Got first data */ +// while (bytes_left > (mem_width-1) ) begin +// temp_data = temp_data >> data_width; +// //temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; +// get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); +// addr = addr+1; +// bytes_left = bytes_left - mem_width; +// end +// +// /* Get last valid data in the burst*/ +// //temp_rd_data = ddr_mem[addr]; +// get_data(addr,temp_rd_data); +// while(bytes_left > 0) begin +// temp_data = temp_data >> 8; +// temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; +// temp_rd_data = temp_rd_data >> 8; +// bytes_left = bytes_left - 1; +// end +// /* align to the brst_byte length */ +// repeat(max_burst_bytes - no_of_bytes) +// temp_data = temp_data >> 8; +// end +// data = temp_data; +// `ifdef XLNX_INT_DBG +// $display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +// `endif +// end +// endtask + + +/* read_memory */ +task read_mem; +output[max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width :0] no_of_bytes; +integer i; +reg [addr_width-1:0] addr; +reg [data_width-1:0] temp_rd_data; +reg [max_burst_bits-1:0] temp_data; +integer pre_bytes; +integer bytes_left; +begin +addr = start_addr >> shft_addr_bits; +pre_bytes = start_addr[shft_addr_bits-1:0]; +bytes_left = no_of_bytes; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +`endif + +/* Get first data ... if unaligned address */ +//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; +get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); + +if(no_of_bytes+start_addr[shft_addr_bits-1:0] < mem_width ) begin + temp_data = temp_data >> (pre_bytes * 8); + repeat(max_burst_bytes - mem_width) + temp_data = temp_data >> 8; + +end else begin + bytes_left = bytes_left - (mem_width - pre_bytes); + addr = addr+1; + /* Got first data */ + while (bytes_left > (mem_width-1) ) begin + temp_data = temp_data >> data_width; + //temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; + get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); + addr = addr+1; + bytes_left = bytes_left - mem_width; + end + + /* Get last valid data in the burst*/ + //temp_rd_data = ddr_mem[addr]; + get_data(addr,temp_rd_data); + while(bytes_left > 0) begin + temp_data = temp_data >> 8; + temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; + temp_rd_data = temp_rd_data >> 8; + bytes_left = bytes_left - 1; + end + /* align to the brst_byte length */ + repeat(max_burst_bytes - no_of_bytes) + temp_data = temp_data >> 8; +end +data = temp_data; +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +`endif +end +endtask + + + + +/* backdoor read to memory */ +task peek_mem_to_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; + +integer rd_fd; +integer bytes; +reg [addr_width-1:0] addr; +reg [data_width-1:0] rd_data; +begin +rd_fd = $fopen(file_name,"w"); +bytes = no_of_bytes; + +addr = start_addr >> shft_addr_bits; +while (bytes > 0) begin + get_data(addr,rd_data); + $fdisplayh(rd_fd,rd_data); + bytes = bytes - 4; + addr = addr + 1; +end +end +endtask + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_reg_map.v + * + * Date : 2012-11 + * + * Description : Controller for Register Map Memory + * + *****************************************************************************/ +/*** WA for CR # 695818 ***/ +`ifdef XILINX_SIMULATOR + `define XSIM_ISIM +`endif +`ifdef XILINX_ISIM + `define XSIM_ISIM +`endif + + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_reg_map(); + +`include "processing_system7_vip_v1_0_16_local_params.v" + +/* Register definitions */ +`include "processing_system7_vip_v1_0_16_reg_params.v" + +parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide +parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB + +`ifdef XSIM_ISIM + reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + parameter addr_offset_bits = 26; +`else + reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space + parameter addr_offset_bits = 27; +`endif + +/* preload reset_values from file */ +task automatic pre_load_rst_values; +input dummy; +begin + `include "processing_system7_vip_v1_0_16_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/ +end +endtask + +/* writes the reset data into the reg memory */ +task automatic set_reset_data; +input [addr_width-1:0] address; +input [data_width-1:0] data; +reg [addr_width-1:0] addr; +begin +addr = address >> 2; +`ifdef XSIM_ISIM + case(addr[addr_width-1:addr_offset_bits]) + 14 : reg_mem0[addr[addr_offset_bits-1:0]] = data; + 15 : reg_mem1[addr[addr_offset_bits-1:0]] = data; + endcase +`else + reg_mem[addr[addr_offset_bits-1:0]] = data; +`endif +end +endtask + +/* writes the data into the reg memory */ +task automatic set_data; +input [addr_width-1:0] addr; +input [data_width-1:0] data; +begin +`ifdef XSIM_ISIM + case(addr[addr_width-1:addr_offset_bits]) + 6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data; + 6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data; + endcase +`else + reg_mem[addr[addr_offset_bits-1:0]] = data; +`endif +end +endtask + +/* get the read data from reg mem */ +task automatic get_data; +input [addr_width-1:0] addr; +output [data_width-1:0] data; +begin +`ifdef XSIM_ISIM + case(addr[addr_width-1:addr_offset_bits]) + 6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]]; + 6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]]; + endcase +`else + data = reg_mem[addr[addr_offset_bits-1:0]]; +`endif +end +endtask + +/* read chunk of registers */ +task read_reg_mem; +output[max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +integer i; +reg [addr_width-1:0] addr; +reg [data_width-1:0] temp_rd_data; +reg [max_burst_bits-1:0] temp_data; +integer bytes_left; +begin +addr = start_addr >> shft_addr_bits; +bytes_left = no_of_bytes; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +`endif + +/* Get first data ... if unaligned address */ +get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]); + +if(no_of_bytes < mem_width ) begin + repeat(max_burst_bytes - mem_width) + temp_data = temp_data >> 8; + +end else begin + bytes_left = bytes_left - mem_width; + addr = addr+1; + /* Got first data */ + while (bytes_left > (mem_width-1) ) begin + temp_data = temp_data >> data_width; + get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); + addr = addr+1; + bytes_left = bytes_left - mem_width; + end + + /* Get last valid data in the burst*/ + get_data(addr,temp_rd_data); + while(bytes_left > 0) begin + temp_data = temp_data >> 8; + temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; + temp_rd_data = temp_rd_data >> 8; + bytes_left = bytes_left - 1; + end + /* align to the brst_byte length */ + repeat(max_burst_bytes - no_of_bytes) + temp_data = temp_data >> 8; +end +data = temp_data; +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +`endif +end +endtask + +initial +begin + pre_load_rst_values(1); +end + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_ocm_mem.v + * + * Date : 2012-11 + * + * Description : Mimics OCM model + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_ocm_mem(); +`include "processing_system7_vip_v1_0_16_local_params.v" + +parameter mem_size = 32'h4_0000; /// 256 KB +parameter mem_addr_width = clogb2(mem_size/mem_width); + +reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory + +/* preload memory from file */ +// task automatic pre_load_mem_from_file; +// input [(max_chars*8)-1:0] file_name; +// input [addr_width-1:0] start_addr; +// input [int_width-1:0] no_of_bytes; +// $readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits); +// endtask + +task automatic pre_load_mem_from_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +integer i; + reg [data_width-1:0] ocm_memory_temp [0:(mem_size/mem_width)-1]; /// 256 KB memory + + $readmemh(file_name,ocm_memory_temp,start_addr>>shft_addr_bits); + for (i = 0; i < no_of_bytes; i = i + 1) begin + ocm_memory[(start_addr>>shft_addr_bits) + i] = ocm_memory_temp[(start_addr>>shft_addr_bits) + i]; + end + +endtask + + +/* preload memory with some random data */ +task automatic pre_load_mem; +input [1:0] data_type; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +integer i; +reg [mem_addr_width-1:0] addr; +begin +addr = start_addr >> shft_addr_bits; + +for (i = 0; i < no_of_bytes; i = i + mem_width) begin + case(data_type) + ALL_RANDOM : ocm_memory[addr] = $random; + ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000; + ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF; + default : ocm_memory[addr] = $random; + endcase + addr = addr+1; +end +end +endtask + +/* Write memory */ +task write_mem; +input [max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +input [max_burst_bytes-1 :0] strb; +reg [mem_addr_width-1:0] addr; +reg [max_burst_bits-1 :0] wr_temp_data; +reg [max_burst_bytes-1 :0] wr_temp_strb; +reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; +reg [(data_width/8)-1:0] pre_pad_strb, post_pad_strb, temp_strb; + +integer bytes_left; +integer pre_pad_bytes; +integer post_pad_bytes; +begin +addr = start_addr >> shft_addr_bits; +wr_temp_data = data; +wr_temp_strb = strb; + + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); +`endif + +temp_data = wr_temp_data[data_width-1:0]; +temp_strb = wr_temp_strb[(data_width/8)-1:0]; +bytes_left = no_of_bytes; +/* when the no. of bytes to be updated is less than mem_width */ + if(bytes_left+start_addr[shft_addr_bits-1:0] < mem_width) begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + temp_data = ocm_memory[addr]; + temp_strb = 4'hF; + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) begin + temp_data = temp_data << 8; + temp_strb = temp_strb << 1; + end + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_strb = temp_strb >> 1; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + temp_strb[(data_width/8)-1] = wr_temp_strb[0]; + wr_temp_data = wr_temp_data >> 8; + wr_temp_strb = wr_temp_strb >> 1; + end + bytes_left = bytes_left + pre_pad_bytes; + end + /* This is needed for post padding the data ...*/ + post_pad_bytes = mem_width - bytes_left; + post_pad_data = ocm_memory[addr]; + post_pad_strb = 4'hF; + repeat(post_pad_bytes) begin + temp_data = temp_data << 8; + temp_strb = temp_strb << 1; + end + repeat(bytes_left) begin + post_pad_data = post_pad_data >> 8; + post_pad_strb = post_pad_strb >> 1; + end + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_strb = temp_strb >> 1; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + temp_strb[(data_width/8)-1] = post_pad_strb[0]; + post_pad_data = post_pad_data >> 8; + post_pad_strb = post_pad_strb >> 1; + end + if (temp_strb[0] == 1'b1) ocm_memory[addr][7:0] = temp_data[7:0]; + if (temp_strb[1] == 1'b1) ocm_memory[addr][15:8] = temp_data[15:8]; + if (temp_strb[2] == 1'b1) ocm_memory[addr][23:16] = temp_data[23:16]; + if (temp_strb[3] == 1'b1) ocm_memory[addr][31:24] = temp_data[31:24]; + //$display(" zero ocm_memory[addr] %0h temp_data %0h ",ocm_memory[addr],temp_data[31:0]); +end else begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + temp_data = ocm_memory[addr]; + temp_strb = 4'hF; + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) begin + temp_data = temp_data << 8; + temp_strb = temp_strb << 1; + end + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_strb = temp_strb >> 1; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + temp_strb[(data_width/8)-1] = wr_temp_strb[0]; + wr_temp_data = wr_temp_data >> 8; + wr_temp_strb = wr_temp_strb >> 1; + bytes_left = bytes_left -1; + end + end else begin + wr_temp_data = wr_temp_data >> data_width; + wr_temp_strb = wr_temp_strb >> data_width/8; + bytes_left = bytes_left - mem_width; + end + /* first data word end */ + if (temp_strb[0] == 1'b1) ocm_memory[addr][7:0] = temp_data[7:0]; + if (temp_strb[1] == 1'b1) ocm_memory[addr][15:8] = temp_data[15:8]; + if (temp_strb[2] == 1'b1) ocm_memory[addr][23:16] = temp_data[23:16]; + if (temp_strb[3] == 1'b1) ocm_memory[addr][31:24] = temp_data[31:24]; + addr = addr + 1; + //$display(" first write ocm_memory[addr] %0h temp_data %0h ",ocm_memory[addr],temp_data[31:0]); + while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. + if (wr_temp_strb[0] == 1'b1) ocm_memory[addr][7:0] = wr_temp_data[7:0]; + if (wr_temp_strb[1] == 1'b1) ocm_memory[addr][15:8] = wr_temp_data[15:8]; + if (wr_temp_strb[2] == 1'b1) ocm_memory[addr][23:16] = wr_temp_data[23:16]; + if (wr_temp_strb[3] == 1'b1) ocm_memory[addr][31:24] = wr_temp_data[31:24]; + //$display("second write ocm_memory[addr] %0h temp_data %0h ",ocm_memory[addr],temp_data[31:0]); +//ocm_memory[addr] = wr_temp_data[data_width-1:0]; + addr = addr+1; + wr_temp_data = wr_temp_data >> data_width; + wr_temp_strb = wr_temp_strb >> data_width/8; + bytes_left = bytes_left - mem_width; + end + + post_pad_data = ocm_memory[addr]; + post_pad_strb = 4'hF; + post_pad_bytes = mem_width - bytes_left; + /* This is needed for last transfer in unaliged burst */ + if(bytes_left > 0) begin + temp_data = wr_temp_data[data_width-1:0]; + temp_strb = wr_temp_strb[(data_width/8)-1:0]; + repeat(post_pad_bytes) begin + temp_data = temp_data << 8; + temp_strb = temp_strb << 1; + end + repeat(bytes_left) begin + post_pad_data = post_pad_data >> 8; + post_pad_strb = post_pad_strb >> 1; + end + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_strb = temp_strb >> 1; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + temp_strb[(data_width/8)-1] = post_pad_strb[0]; + post_pad_data = post_pad_data >> 8; + post_pad_strb = post_pad_strb >> 1; + end + if (temp_strb[0] == 1'b1) ocm_memory[addr][7:0] = temp_data[7:0]; + if (temp_strb[1] == 1'b1) ocm_memory[addr][15:8] = temp_data[15:8]; + if (temp_strb[2] == 1'b1) ocm_memory[addr][23:16] = temp_data[23:16]; + if (temp_strb[3] == 1'b1) ocm_memory[addr][31:24] = temp_data[31:24]; + //$display("third write ocm_memory[addr] %0h temp_data %0h ",ocm_memory[addr],temp_data[31:0]); +// ocm_memory[addr] = temp_data; + end +end +`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); +`endif +end +endtask + +/* read_memory */ +task read_mem; +output[max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +integer i; +reg [mem_addr_width-1:0] addr; +reg [data_width-1:0] temp_rd_data; +reg [max_burst_bits-1:0] temp_data; +integer pre_bytes; +integer bytes_left; +integer number_of_reads_first_loc,number_of_extra_reads; +begin +addr = start_addr >> shft_addr_bits; +pre_bytes = start_addr[shft_addr_bits-1:0]; +// if(pre_bytes+no_of_bytes > mem_width) begin +// bytes_left = pre_bytes+no_of_bytes; +// $display(" new0 number of bytes_left %0d",bytes_left); +// end else begin +// bytes_left = no_of_bytes; +// $display(" new1 number of bytes_left %0d",bytes_left); +// end +number_of_reads_first_loc = (mem_width - pre_bytes); +if(pre_bytes > number_of_reads_first_loc) +number_of_extra_reads = (pre_bytes - number_of_reads_first_loc); +else +number_of_extra_reads = 0; +//$display("number_of_reads_first_loc %0d number_of_extra_reads %0d",number_of_reads_first_loc,number_of_extra_reads); + +bytes_left = no_of_bytes-number_of_reads_first_loc; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +`endif + +//$display("start_addr %0h no_of_bytes %0d addr %0h shft_addr_bits %0d",start_addr,no_of_bytes,addr,shft_addr_bits); + +/* Get first data ... if unaligned address */ +temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; + + +//$display("start_addr %0h ocm_memory[%0h] %0h pre_bytes %0d",start_addr,addr,ocm_memory[addr],pre_bytes); +// if(no_of_bytes < mem_width ) begin +// if(bytes_left < mem_width ) begin +if(bytes_left <= 0 ) begin + temp_data = temp_data >> (pre_bytes * 8); + repeat(max_burst_bytes - mem_width) + temp_data = temp_data >> 8; + //$display("temp_data %0h no_of_bytes %0h mem_width %0h",temp_data,no_of_bytes,mem_width); +end else begin + // bytes_left = bytes_left - (mem_width - pre_bytes); + //$display(" else bytes_left %0d ",bytes_left); + addr = addr+1; + /* Got first data */ + while (bytes_left > (mem_width-1) ) begin + temp_data = temp_data >> data_width; + temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; + addr = addr+1; + bytes_left = bytes_left - mem_width; + end + + /* Get last valid data in the burst*/ + temp_rd_data = ocm_memory[addr]; + //$display("second temp_rd_data %0h no_of_bytes %0h ocm_memory[%0h] %0h",temp_rd_data,no_of_bytes,addr,ocm_memory[addr]); + while(bytes_left > 0) begin + temp_data = temp_data >> 8; + //$display("temp_data %0h bytes_left %0d max_burst_bits %0d",temp_data,bytes_left,max_burst_bits); + temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; + temp_rd_data = temp_rd_data >> 8; + bytes_left = bytes_left - 1; + //$display("temp_rd_data %0h bytes_left %0d max_burst_bits %0d",temp_rd_data,bytes_left,max_burst_bits); + end + /* align to the brst_byte length */ + repeat(max_burst_bytes - no_of_bytes) begin + temp_data = temp_data >> 8; + // $display("temp_data %0h no_of_bytes %0d max_burst_bytes %0d",temp_data,no_of_bytes,max_burst_bytes); + end +end +data = temp_data; + //$display("final data %0h ",data); +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +`endif +end +endtask + +// /* read_memory */ +// task read_mem; +// output[max_burst_bits-1 :0] data; +// input [addr_width-1:0] start_addr; +// input [max_burst_bytes_width:0] no_of_bytes; +// integer i; +// reg [mem_addr_width-1:0] addr; +// reg [data_width-1:0] temp_rd_data; +// reg [max_burst_bits-1:0] temp_data; +// integer pre_bytes; +// integer bytes_left; +// begin +// addr = start_addr >> shft_addr_bits; +// pre_bytes = start_addr[shft_addr_bits-1:0]; +// bytes_left = no_of_bytes; +// +// `ifdef XLNX_INT_DBG +// $display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +// `endif +// +// /* Get first data ... if unaligned address */ +// temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; +// +// if(no_of_bytes < mem_width ) begin +// temp_data = temp_data >> (pre_bytes * 8); +// repeat(max_burst_bytes - mem_width) +// temp_data = temp_data >> 8; +// +// end else begin +// bytes_left = bytes_left - (mem_width - pre_bytes); +// addr = addr+1; +// /* Got first data */ +// while (bytes_left > (mem_width-1) ) begin +// temp_data = temp_data >> data_width; +// temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; +// addr = addr+1; +// bytes_left = bytes_left - mem_width; +// end +// +// /* Get last valid data in the burst*/ +// temp_rd_data = ocm_memory[addr]; +// while(bytes_left > 0) begin +// temp_data = temp_data >> 8; +// temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; +// temp_rd_data = temp_rd_data >> 8; +// bytes_left = bytes_left - 1; +// end +// /* align to the brst_byte length */ +// repeat(max_burst_bytes - no_of_bytes) +// temp_data = temp_data >> 8; +// end +// data = temp_data; +// `ifdef XLNX_INT_DBG +// $display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +// `endif +// end +// endtask + +/* backdoor read to memory */ +task peek_mem_to_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; + +integer rd_fd; +integer bytes; +reg [addr_width-1:0] addr; +reg [data_width-1:0] rd_data; +begin +rd_fd = $fopen(file_name,"w"); +bytes = no_of_bytes; + +addr = start_addr >> shft_addr_bits; +while (bytes > 0) begin + rd_data = ocm_memory[addr]; + $fdisplayh(rd_fd,rd_data); + bytes = bytes - 4; + addr = addr + 1; +end +end +endtask + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_intr_wr_mem.v + * + * Date : 2012-11 + * + * Description : Mimics interconnect for Writes between AFI and DDRC/OCM + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_intr_wr_mem( +sw_clk, +rstn, + +full, + +WR_DATA_ACK_OCM, +WR_DATA_ACK_DDR, +WR_ADDR, +WR_DATA, +WR_BYTES, +WR_QOS, +WR_DATA_VALID_OCM, +WR_DATA_VALID_DDR +); + +`include "processing_system7_vip_v1_0_16_local_params.v" +/* local parameters for interconnect wr fifo model */ + parameter wr_bytes_lsb = 0; + parameter wr_bytes_msb = max_burst_bytes_width; + parameter wr_addr_lsb = wr_bytes_msb + 1; + parameter wr_addr_msb = wr_addr_lsb + addr_width-1; + parameter wr_data_lsb = wr_addr_msb + 1; + + parameter data_bus_width = 32; + parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1; + parameter wr_qos_lsb = wr_data_msb + 1; + parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; + parameter wr_strb_lsb = wr_qos_msb + 1; + parameter wr_strb_msb = wr_strb_lsb + ((data_bus_width/8)*axi_burst_len)-1; + + +parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1); +input sw_clk, rstn; +output full; + +input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; +output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; +output reg [max_burst_bits-1:0] WR_DATA; +output reg [addr_width-1:0] WR_ADDR; +output reg [max_burst_bytes_width:0] WR_BYTES; +output reg [axi_qos_width-1:0] WR_QOS; +reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; +reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1]; +wire empty; + +assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; +assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; + +parameter SEND_DATA = 0, WAIT_ACK = 1; +reg state; + +task automatic write_mem; +input [wr_fifo_data_bits-1:0] data; +begin + wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data; + if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) + wr_ptr[intr_cnt_width-2:0] = 0; + else + wr_ptr = wr_ptr + 1; +end +endtask + +always@(negedge rstn or posedge sw_clk) +begin +if(!rstn) begin + wr_ptr = 0; + rd_ptr = 0; + WR_DATA_VALID_DDR = 1'b0; + WR_DATA_VALID_OCM = 1'b0; + WR_QOS = 0; + state = SEND_DATA; +end else begin + case(state) + SEND_DATA :begin + state = SEND_DATA; + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + if(!empty) begin + WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb]; + WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]; + WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; + WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb]; + state = WAIT_ACK; + case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb])) + OCM_MEM : WR_DATA_VALID_OCM = 1; + DDR_MEM : WR_DATA_VALID_DDR = 1; + default : state = SEND_DATA; + endcase + if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin + rd_ptr[intr_cnt_width-2:0] = 0; + end else begin + rd_ptr = rd_ptr+1; + end + end + end + WAIT_ACK :begin + state = WAIT_ACK; + if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + state = SEND_DATA; + end + end + endcase +end +end + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_intr_rd_mem.v + * + * Date : 2012-11 + * + * Description : Mimics interconnect for Reads between AFI and DDRC/OCM + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_intr_rd_mem( +sw_clk, +rstn, + +full, +empty, + +req, +invalid_rd_req, +rd_info, + +RD_DATA_OCM, +RD_DATA_DDR, +RD_DATA_VALID_OCM, +RD_DATA_VALID_DDR + +); +`include "processing_system7_vip_v1_0_16_local_params.v" + +input sw_clk, rstn; +output full, empty; + +input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM; +input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM; +input req, invalid_rd_req; +input [rd_info_bits-1:0] rd_info; + +reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; +reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes +wire full, empty; + + +assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; +assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; + +/* read from the fifo */ +task read_mem; +output [rd_afi_fifo_bits-1:0] data; +begin + data = rd_fifo[rd_ptr[intr_cnt_width-1:0]]; + if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) + rd_ptr[intr_cnt_width-2:0] = 0; + else + rd_ptr = rd_ptr + 1; +end +endtask + +reg state; +reg invalid_rd; +/* write in the fifo */ +always@(negedge rstn or posedge sw_clk) +begin +if(!rstn) begin + wr_ptr = 0; + rd_ptr = 0; + state = 0; + invalid_rd = 0; +end else begin + case (state) + 0 : begin + state = 0; + invalid_rd = 0; + if(req)begin + state = 1; + invalid_rd = invalid_rd_req; + end + end + 1 : begin + state = 1; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin + if(RD_DATA_VALID_DDR) + rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info}; + else if(RD_DATA_VALID_OCM) + rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info}; + else + rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info; + if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) + wr_ptr[intr_cnt_width-2:0] = 0; + else + wr_ptr = wr_ptr + 1; + state = 0; + invalid_rd = 0; + end + end + endcase +end +end + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_fmsw_gp.v + * + * Date : 2012-11 + * + * Description : Mimics FMSW switch. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_fmsw_gp( + sw_clk, + rstn, + + w_qos_gp0, + r_qos_gp0, + wr_ack_ocm_gp0, + wr_ack_ddr_gp0, + wr_data_gp0, + wr_strb_gp0, + wr_addr_gp0, + wr_bytes_gp0, + wr_dv_ocm_gp0, + wr_dv_ddr_gp0, + rd_req_ocm_gp0, + rd_req_ddr_gp0, + rd_req_reg_gp0, + rd_addr_gp0, + rd_bytes_gp0, + rd_data_ocm_gp0, + rd_data_ddr_gp0, + rd_data_reg_gp0, + rd_dv_ocm_gp0, + rd_dv_ddr_gp0, + rd_dv_reg_gp0, + + w_qos_gp1, + r_qos_gp1, + wr_ack_ocm_gp1, + wr_ack_ddr_gp1, + wr_data_gp1, + wr_strb_gp1, + wr_addr_gp1, + wr_bytes_gp1, + wr_dv_ocm_gp1, + wr_dv_ddr_gp1, + rd_req_ocm_gp1, + rd_req_ddr_gp1, + rd_req_reg_gp1, + rd_addr_gp1, + rd_bytes_gp1, + rd_data_ocm_gp1, + rd_data_ddr_gp1, + rd_data_reg_gp1, + rd_dv_ocm_gp1, + rd_dv_ddr_gp1, + rd_dv_reg_gp1, + + ocm_wr_ack, + ocm_wr_dv, + ocm_rd_req, + ocm_rd_dv, + ddr_wr_ack, + ddr_wr_dv, + ddr_rd_req, + ddr_rd_dv, + + reg_rd_req, + reg_rd_dv, + + ocm_wr_qos, + ddr_wr_qos, + ocm_rd_qos, + ddr_rd_qos, + reg_rd_qos, + + ocm_wr_addr, + ocm_wr_data, + ocm_wr_strb, + ocm_wr_bytes, + ocm_rd_addr, + ocm_rd_data, + ocm_rd_bytes, + + ddr_wr_addr, + ddr_wr_data, + ddr_wr_strb, + ddr_wr_bytes, + ddr_rd_addr, + ddr_rd_data, + ddr_rd_bytes, + + reg_rd_addr, + reg_rd_data, + reg_rd_bytes + +); + +`include "processing_system7_vip_v1_0_16_local_params.v" + +input sw_clk; +input rstn; + +input [axi_qos_width-1:0]w_qos_gp0; +input [axi_qos_width-1:0]r_qos_gp0; +input [axi_qos_width-1:0]w_qos_gp1; +input [axi_qos_width-1:0]r_qos_gp1; + +output [axi_qos_width-1:0]ocm_wr_qos; +output [axi_qos_width-1:0]ocm_rd_qos; +output [axi_qos_width-1:0]ddr_wr_qos; +output [axi_qos_width-1:0]ddr_rd_qos; +output [axi_qos_width-1:0]reg_rd_qos; + +output wr_ack_ocm_gp0; +output wr_ack_ddr_gp0; +input [max_burst_bits-1:0] wr_data_gp0; +input [max_burst_bytes-1:0] wr_strb_gp0; +input [addr_width-1:0] wr_addr_gp0; +input [max_burst_bytes_width:0] wr_bytes_gp0; +output wr_dv_ocm_gp0; +output wr_dv_ddr_gp0; + +input rd_req_ocm_gp0; +input rd_req_ddr_gp0; +input rd_req_reg_gp0; +input [addr_width-1:0] rd_addr_gp0; +input [max_burst_bytes_width:0] rd_bytes_gp0; +output [max_burst_bits-1:0] rd_data_ocm_gp0; +output [max_burst_bits-1:0] rd_data_ddr_gp0; +output [max_burst_bits-1:0] rd_data_reg_gp0; +output rd_dv_ocm_gp0; +output rd_dv_ddr_gp0; +output rd_dv_reg_gp0; + +output wr_ack_ocm_gp1; +output wr_ack_ddr_gp1; +input [max_burst_bits-1:0] wr_data_gp1; +input [max_burst_bytes-1:0] wr_strb_gp1; +input [addr_width-1:0] wr_addr_gp1; +input [max_burst_bytes_width:0] wr_bytes_gp1; +output wr_dv_ocm_gp1; +output wr_dv_ddr_gp1; + +input rd_req_ocm_gp1; +input rd_req_ddr_gp1; +input rd_req_reg_gp1; +input [addr_width-1:0] rd_addr_gp1; +input [max_burst_bytes_width:0] rd_bytes_gp1; +output [max_burst_bits-1:0] rd_data_ocm_gp1; +output [max_burst_bits-1:0] rd_data_ddr_gp1; +output [max_burst_bits-1:0] rd_data_reg_gp1; +output rd_dv_ocm_gp1; +output rd_dv_ddr_gp1; +output rd_dv_reg_gp1; + + +input ocm_wr_ack; +output ocm_wr_dv; +output [addr_width-1:0]ocm_wr_addr; +output [max_burst_bits-1:0]ocm_wr_data; +output [max_burst_bytes-1:0]ocm_wr_strb; +output [max_burst_bytes_width:0]ocm_wr_bytes; + +input ocm_rd_dv; +input [max_burst_bits-1:0] ocm_rd_data; +output ocm_rd_req; +output [addr_width-1:0] ocm_rd_addr; +output [max_burst_bytes_width:0] ocm_rd_bytes; + +input ddr_wr_ack; +output ddr_wr_dv; +output [addr_width-1:0]ddr_wr_addr; +output [max_burst_bits-1:0]ddr_wr_data; +output [max_burst_bytes-1:0]ddr_wr_strb; +output [max_burst_bytes_width:0]ddr_wr_bytes; + +input ddr_rd_dv; +input [max_burst_bits-1:0] ddr_rd_data; +output ddr_rd_req; +output [addr_width-1:0] ddr_rd_addr; +output [max_burst_bytes_width:0] ddr_rd_bytes; + +input reg_rd_dv; +input [max_burst_bits-1:0] reg_rd_data; +output reg_rd_req; +output [addr_width-1:0] reg_rd_addr; +output [max_burst_bytes_width:0] reg_rd_bytes; + + + +processing_system7_vip_v1_0_16_arb_wr ocm_gp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_gp0), + .qos2(w_qos_gp1), + .prt_dv1(wr_dv_ocm_gp0), + .prt_dv2(wr_dv_ocm_gp1), + .prt_data1(wr_data_gp0), + .prt_data2(wr_data_gp1), + .prt_strb1(wr_strb_gp0), + .prt_strb2(wr_strb_gp1), + .prt_addr1(wr_addr_gp0), + .prt_addr2(wr_addr_gp1), + .prt_bytes1(wr_bytes_gp0), + .prt_bytes2(wr_bytes_gp1), + .prt_ack1(wr_ack_ocm_gp0), + .prt_ack2(wr_ack_ocm_gp1), + .prt_req(ocm_wr_dv), + .prt_qos(ocm_wr_qos), + .prt_data(ocm_wr_data), + .prt_strb(ocm_wr_strb), + .prt_addr(ocm_wr_addr), + .prt_bytes(ocm_wr_bytes), + .prt_ack(ocm_wr_ack) +); + +processing_system7_vip_v1_0_16_arb_wr ddr_gp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_gp0), + .qos2(w_qos_gp1), + .prt_dv1(wr_dv_ddr_gp0), + .prt_dv2(wr_dv_ddr_gp1), + .prt_data1(wr_data_gp0), + .prt_data2(wr_data_gp1), + .prt_strb1(wr_strb_gp0), + .prt_strb2(wr_strb_gp1), + .prt_addr1(wr_addr_gp0), + .prt_addr2(wr_addr_gp1), + .prt_bytes1(wr_bytes_gp0), + .prt_bytes2(wr_bytes_gp1), + .prt_ack1(wr_ack_ddr_gp0), + .prt_ack2(wr_ack_ddr_gp1), + .prt_req(ddr_wr_dv), + .prt_qos(ddr_wr_qos), + .prt_data(ddr_wr_data), + .prt_strb(ddr_wr_strb), + .prt_addr(ddr_wr_addr), + .prt_bytes(ddr_wr_bytes), + .prt_ack(ddr_wr_ack) +); + +processing_system7_vip_v1_0_16_arb_rd ocm_gp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_gp0), + .qos2(r_qos_gp1), + .prt_req1(rd_req_ocm_gp0), + .prt_req2(rd_req_ocm_gp1), + .prt_data1(rd_data_ocm_gp0), + .prt_data2(rd_data_ocm_gp1), + .prt_addr1(rd_addr_gp0), + .prt_addr2(rd_addr_gp1), + .prt_bytes1(rd_bytes_gp0), + .prt_bytes2(rd_bytes_gp1), + .prt_dv1(rd_dv_ocm_gp0), + .prt_dv2(rd_dv_ocm_gp1), + .prt_req(ocm_rd_req), + .prt_qos(ocm_rd_qos), + .prt_data(ocm_rd_data), + .prt_addr(ocm_rd_addr), + .prt_bytes(ocm_rd_bytes), + .prt_dv(ocm_rd_dv) +); + +processing_system7_vip_v1_0_16_arb_rd ddr_gp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_gp0), + .qos2(r_qos_gp1), + .prt_req1(rd_req_ddr_gp0), + .prt_req2(rd_req_ddr_gp1), + .prt_data1(rd_data_ddr_gp0), + .prt_data2(rd_data_ddr_gp1), + .prt_addr1(rd_addr_gp0), + .prt_addr2(rd_addr_gp1), + .prt_bytes1(rd_bytes_gp0), + .prt_bytes2(rd_bytes_gp1), + .prt_dv1(rd_dv_ddr_gp0), + .prt_dv2(rd_dv_ddr_gp1), + .prt_req(ddr_rd_req), + .prt_qos(ddr_rd_qos), + .prt_data(ddr_rd_data), + .prt_addr(ddr_rd_addr), + .prt_bytes(ddr_rd_bytes), + .prt_dv(ddr_rd_dv) +); + +processing_system7_vip_v1_0_16_arb_rd reg_gp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_gp0), + .qos2(r_qos_gp1), + .prt_req1(rd_req_reg_gp0), + .prt_req2(rd_req_reg_gp1), + .prt_data1(rd_data_reg_gp0), + .prt_data2(rd_data_reg_gp1), + .prt_addr1(rd_addr_gp0), + .prt_addr2(rd_addr_gp1), + .prt_bytes1(rd_bytes_gp0), + .prt_bytes2(rd_bytes_gp1), + .prt_dv1(rd_dv_reg_gp0), + .prt_dv2(rd_dv_reg_gp1), + .prt_req(reg_rd_req), + .prt_qos(reg_rd_qos), + .prt_data(reg_rd_data), + .prt_addr(reg_rd_addr), + .prt_bytes(reg_rd_bytes), + .prt_dv(reg_rd_dv) +); + + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_regc.v + * + * Date : 2012-11 + * + * Description : Controller for Register Map Memory + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_regc( + rstn, + sw_clk, + +/* Goes to port 0 of REG */ + reg_rd_req_port0, + reg_rd_dv_port0, + reg_rd_addr_port0, + reg_rd_data_port0, + reg_rd_bytes_port0, + reg_rd_qos_port0, + + +/* Goes to port 1 of REG */ + reg_rd_req_port1, + reg_rd_dv_port1, + reg_rd_addr_port1, + reg_rd_data_port1, + reg_rd_bytes_port1, + reg_rd_qos_port1 + +); + +input rstn; +input sw_clk; + +input reg_rd_req_port0; +output reg_rd_dv_port0; +input[31:0] reg_rd_addr_port0; +output[1023:0] reg_rd_data_port0; +input[7:0] reg_rd_bytes_port0; +input [3:0] reg_rd_qos_port0; + +input reg_rd_req_port1; +output reg_rd_dv_port1; +input[31:0] reg_rd_addr_port1; +output[1023:0] reg_rd_data_port1; +input[7:0] reg_rd_bytes_port1; +input[3:0] reg_rd_qos_port1; + +wire [3:0] rd_qos; +reg [1023:0] rd_data; +wire [31:0] rd_addr; +wire [7:0] rd_bytes; +reg rd_dv; +wire rd_req; + +processing_system7_vip_v1_0_16_arb_rd reg_read_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(reg_rd_qos_port0), + .qos2(reg_rd_qos_port1), + + .prt_req1(reg_rd_req_port0), + .prt_req2(reg_rd_req_port1), + + .prt_data1(reg_rd_data_port0), + .prt_data2(reg_rd_data_port1), + + .prt_addr1(reg_rd_addr_port0), + .prt_addr2(reg_rd_addr_port1), + + .prt_bytes1(reg_rd_bytes_port0), + .prt_bytes2(reg_rd_bytes_port1), + + .prt_dv1(reg_rd_dv_port0), + .prt_dv2(reg_rd_dv_port1), + + .prt_qos(rd_qos), + .prt_req(rd_req), + .prt_data(rd_data), + .prt_addr(rd_addr), + .prt_bytes(rd_bytes), + .prt_dv(rd_dv) + +); + +processing_system7_vip_v1_0_16_reg_map regm(); + +reg state; +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + rd_dv <= 0; + state <= 0; +end else begin + case(state) + 0:begin + state <= 0; + rd_dv <= 0; + if(rd_req) begin + regm.read_reg_mem(rd_data,rd_addr, rd_bytes); + rd_dv <= 1; + state <= 1; + end + + end + 1:begin + rd_dv <= 0; + state <= 0; + end + + endcase +end /// if +end// always + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_ocmc.v + * + * Date : 2012-11 + * + * Description : Controller for OCM model + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_ocmc( + rstn, + sw_clk, + +/* Goes to port 0 of OCM */ + ocm_wr_ack_port0, + ocm_wr_dv_port0, + ocm_rd_req_port0, + ocm_rd_dv_port0, + ocm_wr_addr_port0, + ocm_wr_data_port0, + ocm_wr_strb_port0, + ocm_wr_bytes_port0, + ocm_rd_addr_port0, + ocm_rd_data_port0, + ocm_rd_bytes_port0, + ocm_wr_qos_port0, + ocm_rd_qos_port0, + + +/* Goes to port 1 of OCM */ + ocm_wr_ack_port1, + ocm_wr_dv_port1, + ocm_rd_req_port1, + ocm_rd_dv_port1, + ocm_wr_addr_port1, + ocm_wr_data_port1, + ocm_wr_strb_port1, + ocm_wr_bytes_port1, + ocm_rd_addr_port1, + ocm_rd_data_port1, + ocm_rd_bytes_port1, + ocm_wr_qos_port1, + ocm_rd_qos_port1 + +); + +`include "processing_system7_vip_v1_0_16_local_params.v" +input rstn; +input sw_clk; + +output ocm_wr_ack_port0; +input ocm_wr_dv_port0; +input ocm_rd_req_port0; +output ocm_rd_dv_port0; +input[addr_width-1:0] ocm_wr_addr_port0; +input[max_burst_bits-1:0] ocm_wr_data_port0; +input[max_burst_bits-1:0] ocm_wr_strb_port0; +input[max_burst_bytes_width:0] ocm_wr_bytes_port0; +input[addr_width-1:0] ocm_rd_addr_port0; +output[max_burst_bits-1:0] ocm_rd_data_port0; +input[max_burst_bytes_width:0] ocm_rd_bytes_port0; +input [axi_qos_width-1:0] ocm_wr_qos_port0; +input [axi_qos_width-1:0] ocm_rd_qos_port0; + +output ocm_wr_ack_port1; +input ocm_wr_dv_port1; +input ocm_rd_req_port1; +output ocm_rd_dv_port1; +input[addr_width-1:0] ocm_wr_addr_port1; +input[max_burst_bits-1:0] ocm_wr_data_port1; +input[max_burst_bits-1:0] ocm_wr_strb_port1; +input[max_burst_bytes_width:0] ocm_wr_bytes_port1; +input[addr_width-1:0] ocm_rd_addr_port1; +output[max_burst_bits-1:0] ocm_rd_data_port1; +input[max_burst_bytes_width:0] ocm_rd_bytes_port1; +input[axi_qos_width-1:0] ocm_wr_qos_port1; +input[axi_qos_width-1:0] ocm_rd_qos_port1; + +wire [axi_qos_width-1:0] wr_qos; +wire wr_req; +wire [max_burst_bits-1:0] wr_data; +wire [max_burst_bytes-1:0] wr_strb; +wire [max_burst_bytes-1:0] ocm_wr_strb_port0,ocm_wr_strb_port1; +wire [addr_width-1:0] wr_addr; +wire [max_burst_bytes_width:0] wr_bytes; +reg wr_ack; + +wire [axi_qos_width-1:0] rd_qos; +reg [max_burst_bits-1:0] rd_data; +wire [addr_width-1:0] rd_addr; +wire [max_burst_bytes_width:0] rd_bytes; +reg rd_dv; +wire rd_req; + +processing_system7_vip_v1_0_16_arb_wr ocm_write_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ocm_wr_qos_port0), + .qos2(ocm_wr_qos_port1), + + .prt_dv1(ocm_wr_dv_port0), + .prt_dv2(ocm_wr_dv_port1), + + .prt_data1(ocm_wr_data_port0), + .prt_data2(ocm_wr_data_port1), + + .prt_strb1(ocm_wr_strb_port0), + .prt_strb2(ocm_wr_strb_port1), + + .prt_addr1(ocm_wr_addr_port0), + .prt_addr2(ocm_wr_addr_port1), + + .prt_bytes1(ocm_wr_bytes_port0), + .prt_bytes2(ocm_wr_bytes_port1), + + .prt_ack1(ocm_wr_ack_port0), + .prt_ack2(ocm_wr_ack_port1), + + .prt_qos(wr_qos), + .prt_req(wr_req), + .prt_data(wr_data), + .prt_strb(wr_strb), + .prt_addr(wr_addr), + .prt_bytes(wr_bytes), + .prt_ack(wr_ack) + +); + +processing_system7_vip_v1_0_16_arb_rd ocm_read_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ocm_rd_qos_port0), + .qos2(ocm_rd_qos_port1), + + .prt_req1(ocm_rd_req_port0), + .prt_req2(ocm_rd_req_port1), + + .prt_data1(ocm_rd_data_port0), + .prt_data2(ocm_rd_data_port1), + + .prt_addr1(ocm_rd_addr_port0), + .prt_addr2(ocm_rd_addr_port1), + + .prt_bytes1(ocm_rd_bytes_port0), + .prt_bytes2(ocm_rd_bytes_port1), + + .prt_dv1(ocm_rd_dv_port0), + .prt_dv2(ocm_rd_dv_port1), + + .prt_qos(rd_qos), + .prt_req(rd_req), + .prt_data(rd_data), + .prt_addr(rd_addr), + .prt_bytes(rd_bytes), + .prt_dv(rd_dv) + +); + +processing_system7_vip_v1_0_16_ocm_mem ocm(); + +reg [1:0] state; +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + wr_ack <= 0; + rd_dv <= 0; + state <= 2'd0; +end else begin + case(state) + 0:begin + state <= 0; + wr_ack <= 0; + rd_dv <= 0; + if(wr_req) begin + ocm.write_mem(wr_data , wr_addr, wr_bytes, wr_strb); + //$display(" ocm_write_data wr_addr %0h wr_data %0h wr_bytes %0h wr_strb %0h",wr_addr,wr_data,wr_bytes,wr_strb); + wr_ack <= 1; + state <= 1; + end + if(rd_req) begin + ocm.read_mem(rd_data,rd_addr, rd_bytes); + //$display(" ocm_read_data rd_addr %0h rd_data %0h rd_bytes %0h ",rd_addr,rd_data,rd_bytes); + rd_dv <= 1; + state <= 1; + end + + end + 1:begin + wr_ack <= 0; + rd_dv <= 0; + state <= 0; + end + + endcase +end /// if +end// always + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_interconnect_model.v + * + * Date : 2012-11 + * + * Description : Mimics Top_interconnect Switch. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_interconnect_model ( + rstn, + sw_clk, + + w_qos_gp0, + w_qos_gp1, + w_qos_hp0, + w_qos_hp1, + w_qos_hp2, + w_qos_hp3, + + r_qos_gp0, + r_qos_gp1, + r_qos_hp0, + r_qos_hp1, + r_qos_hp2, + r_qos_hp3, + + wr_ack_ddr_gp0, + wr_ack_ocm_gp0, + wr_data_gp0, + wr_strb_gp0, + wr_addr_gp0, + wr_bytes_gp0, + wr_dv_ddr_gp0, + wr_dv_ocm_gp0, + + rd_req_ddr_gp0, + rd_req_ocm_gp0, + rd_req_reg_gp0, + rd_addr_gp0, + rd_bytes_gp0, + rd_data_ddr_gp0, + rd_data_ocm_gp0, + rd_data_reg_gp0, + rd_dv_ddr_gp0, + rd_dv_ocm_gp0, + rd_dv_reg_gp0, + + wr_ack_ddr_gp1, + wr_ack_ocm_gp1, + wr_data_gp1, + wr_strb_gp1, + wr_addr_gp1, + wr_bytes_gp1, + wr_dv_ddr_gp1, + wr_dv_ocm_gp1, + rd_req_ddr_gp1, + rd_req_ocm_gp1, + rd_req_reg_gp1, + rd_addr_gp1, + rd_bytes_gp1, + rd_data_ddr_gp1, + rd_data_ocm_gp1, + rd_data_reg_gp1, + rd_dv_ddr_gp1, + rd_dv_ocm_gp1, + rd_dv_reg_gp1, + + wr_ack_ddr_hp0, + wr_ack_ocm_hp0, + wr_data_hp0, + wr_strb_hp0, + wr_addr_hp0, + wr_bytes_hp0, + wr_dv_ddr_hp0, + wr_dv_ocm_hp0, + rd_req_ddr_hp0, + rd_req_ocm_hp0, + rd_addr_hp0, + rd_bytes_hp0, + rd_data_ddr_hp0, + rd_data_ocm_hp0, + rd_dv_ddr_hp0, + rd_dv_ocm_hp0, + + wr_ack_ddr_hp1, + wr_ack_ocm_hp1, + wr_data_hp1, + wr_strb_hp1, + wr_addr_hp1, + wr_bytes_hp1, + wr_dv_ddr_hp1, + wr_dv_ocm_hp1, + rd_req_ddr_hp1, + rd_req_ocm_hp1, + rd_addr_hp1, + rd_bytes_hp1, + rd_data_ddr_hp1, + rd_data_ocm_hp1, + rd_dv_ddr_hp1, + rd_dv_ocm_hp1, + + wr_ack_ddr_hp2, + wr_ack_ocm_hp2, + wr_data_hp2, + wr_strb_hp2, + wr_addr_hp2, + wr_bytes_hp2, + wr_dv_ddr_hp2, + wr_dv_ocm_hp2, + rd_req_ddr_hp2, + rd_req_ocm_hp2, + rd_addr_hp2, + rd_bytes_hp2, + rd_data_ddr_hp2, + rd_data_ocm_hp2, + rd_dv_ddr_hp2, + rd_dv_ocm_hp2, + + wr_ack_ddr_hp3, + wr_ack_ocm_hp3, + wr_data_hp3, + wr_strb_hp3, + wr_addr_hp3, + wr_bytes_hp3, + wr_dv_ddr_hp3, + wr_dv_ocm_hp3, + rd_req_ddr_hp3, + rd_req_ocm_hp3, + rd_addr_hp3, + rd_bytes_hp3, + rd_data_ddr_hp3, + rd_data_ocm_hp3, + rd_dv_ddr_hp3, + rd_dv_ocm_hp3, + +/* Goes to port 1 of DDR */ + ddr_wr_ack_port1, + ddr_wr_dv_port1, + ddr_rd_req_port1, + ddr_rd_dv_port1, + ddr_wr_addr_port1, + ddr_wr_data_port1, + ddr_wr_strb_port1, + ddr_wr_bytes_port1, + ddr_rd_addr_port1, + ddr_rd_data_port1, + ddr_rd_bytes_port1, + ddr_wr_qos_port1, + ddr_rd_qos_port1, + +/* Goes to port2 of DDR */ + ddr_wr_ack_port2, + ddr_wr_dv_port2, + ddr_rd_req_port2, + ddr_rd_dv_port2, + ddr_wr_addr_port2, + ddr_wr_data_port2, + ddr_wr_strb_port2, + ddr_wr_bytes_port2, + ddr_rd_addr_port2, + ddr_rd_data_port2, + ddr_rd_bytes_port2, + ddr_wr_qos_port2, + ddr_rd_qos_port2, + +/* Goes to port3 of DDR */ + ddr_wr_ack_port3, + ddr_wr_dv_port3, + ddr_rd_req_port3, + ddr_rd_dv_port3, + ddr_wr_addr_port3, + ddr_wr_data_port3, + ddr_wr_strb_port3, + ddr_wr_bytes_port3, + ddr_rd_addr_port3, + ddr_rd_data_port3, + ddr_rd_bytes_port3, + ddr_wr_qos_port3, + ddr_rd_qos_port3, + +/* Goes to port1 of OCM */ + ocm_wr_qos_port1, + ocm_rd_qos_port1, + ocm_wr_dv_port1, + ocm_wr_data_port1, + ocm_wr_strb_port1, + ocm_wr_addr_port1, + ocm_wr_bytes_port1, + ocm_wr_ack_port1, + ocm_rd_req_port1, + ocm_rd_data_port1, + ocm_rd_addr_port1, + ocm_rd_bytes_port1, + ocm_rd_dv_port1, + +/* Goes to port1 for RegMap */ + reg_rd_qos_port1, + reg_rd_req_port1, + reg_rd_data_port1, + reg_rd_addr_port1, + reg_rd_bytes_port1, + reg_rd_dv_port1 + +); +`include "processing_system7_vip_v1_0_16_local_params.v" + +input rstn; +input sw_clk; + +input [axi_qos_width-1:0] w_qos_gp0; +input [axi_qos_width-1:0] w_qos_gp1; +input [axi_qos_width-1:0] w_qos_hp0; +input [axi_qos_width-1:0] w_qos_hp1; +input [axi_qos_width-1:0] w_qos_hp2; +input [axi_qos_width-1:0] w_qos_hp3; + +input [axi_qos_width-1:0] r_qos_gp0; +input [axi_qos_width-1:0] r_qos_gp1; +input [axi_qos_width-1:0] r_qos_hp0; +input [axi_qos_width-1:0] r_qos_hp1; +input [axi_qos_width-1:0] r_qos_hp2; +input [axi_qos_width-1:0] r_qos_hp3; + +output [axi_qos_width-1:0] ocm_wr_qos_port1; +output [axi_qos_width-1:0] ocm_rd_qos_port1; + +output wr_ack_ddr_gp0; +output wr_ack_ocm_gp0; +input[max_burst_bits-1:0] wr_data_gp0; +input[max_burst_bytes-1:0] wr_strb_gp0; +input[addr_width-1:0] wr_addr_gp0; +input[max_burst_bytes_width:0] wr_bytes_gp0; +input wr_dv_ddr_gp0; +input wr_dv_ocm_gp0; +input rd_req_ddr_gp0; +input rd_req_ocm_gp0; +input rd_req_reg_gp0; +input[addr_width-1:0] rd_addr_gp0; +input[max_burst_bytes_width:0] rd_bytes_gp0; +output[max_burst_bits-1:0] rd_data_ddr_gp0; +output[max_burst_bits-1:0] rd_data_ocm_gp0; +output[max_burst_bits-1:0] rd_data_reg_gp0; +output rd_dv_ddr_gp0; +output rd_dv_ocm_gp0; +output rd_dv_reg_gp0; + +output wr_ack_ddr_gp1; +output wr_ack_ocm_gp1; +input[max_burst_bits-1:0] wr_data_gp1; +input[max_burst_bytes-1:0] wr_strb_gp1; +input[addr_width-1:0] wr_addr_gp1; +input[max_burst_bytes_width:0] wr_bytes_gp1; +input wr_dv_ddr_gp1; +input wr_dv_ocm_gp1; +input rd_req_ddr_gp1; +input rd_req_ocm_gp1; +input rd_req_reg_gp1; +input[addr_width-1:0] rd_addr_gp1; +input[max_burst_bytes_width:0] rd_bytes_gp1; +output[max_burst_bits-1:0] rd_data_ddr_gp1; +output[max_burst_bits-1:0] rd_data_ocm_gp1; +output[max_burst_bits-1:0] rd_data_reg_gp1; +output rd_dv_ddr_gp1; +output rd_dv_ocm_gp1; +output rd_dv_reg_gp1; + +output wr_ack_ddr_hp0; +output wr_ack_ocm_hp0; +input[max_burst_bits-1:0] wr_data_hp0; +input[max_burst_bytes-1:0] wr_strb_hp0; +input[addr_width-1:0] wr_addr_hp0; +input[max_burst_bytes_width:0] wr_bytes_hp0; +input wr_dv_ddr_hp0; +input wr_dv_ocm_hp0; +input rd_req_ddr_hp0; +input rd_req_ocm_hp0; +input[addr_width-1:0] rd_addr_hp0; +input[max_burst_bytes_width:0] rd_bytes_hp0; +output[max_burst_bits-1:0] rd_data_ddr_hp0; +output[max_burst_bits-1:0] rd_data_ocm_hp0; +output rd_dv_ddr_hp0; +output rd_dv_ocm_hp0; + +output wr_ack_ddr_hp1; +output wr_ack_ocm_hp1; +input[max_burst_bits-1:0] wr_data_hp1; +input[max_burst_bytes-1:0] wr_strb_hp1; +input[addr_width-1:0] wr_addr_hp1; +input[max_burst_bytes_width:0] wr_bytes_hp1; +input wr_dv_ddr_hp1; +input wr_dv_ocm_hp1; +input rd_req_ddr_hp1; +input rd_req_ocm_hp1; +input[addr_width-1:0] rd_addr_hp1; +input[max_burst_bytes_width:0] rd_bytes_hp1; +output[max_burst_bits-1:0] rd_data_ddr_hp1; +output[max_burst_bits-1:0] rd_data_ocm_hp1; +output rd_dv_ddr_hp1; +output rd_dv_ocm_hp1; + +output wr_ack_ddr_hp2; +output wr_ack_ocm_hp2; +input[max_burst_bits-1:0] wr_data_hp2; +input[max_burst_bytes-1:0] wr_strb_hp2; +input[addr_width-1:0] wr_addr_hp2; +input[max_burst_bytes_width:0] wr_bytes_hp2; +input wr_dv_ddr_hp2; +input wr_dv_ocm_hp2; +input rd_req_ddr_hp2; +input rd_req_ocm_hp2; +input[addr_width-1:0] rd_addr_hp2; +input[max_burst_bytes_width:0] rd_bytes_hp2; +output[max_burst_bits-1:0] rd_data_ddr_hp2; +output[max_burst_bits-1:0] rd_data_ocm_hp2; +output rd_dv_ddr_hp2; +output rd_dv_ocm_hp2; + +output wr_ack_ddr_hp3; +output wr_ack_ocm_hp3; +input[max_burst_bits-1:0] wr_data_hp3; +input[max_burst_bytes-1:0] wr_strb_hp3; +input[addr_width-1:0] wr_addr_hp3; +input[max_burst_bytes_width:0] wr_bytes_hp3; +input wr_dv_ddr_hp3; +input wr_dv_ocm_hp3; +input rd_req_ddr_hp3; +input rd_req_ocm_hp3; +input[addr_width-1:0] rd_addr_hp3; +input[max_burst_bytes_width:0] rd_bytes_hp3; +output[max_burst_bits-1:0] rd_data_ddr_hp3; +output[max_burst_bits-1:0] rd_data_ocm_hp3; +output rd_dv_ddr_hp3; +output rd_dv_ocm_hp3; + +/* Goes to port 1 of DDR */ +input ddr_wr_ack_port1; +output ddr_wr_dv_port1; +output ddr_rd_req_port1; +input ddr_rd_dv_port1; +output[addr_width-1:0] ddr_wr_addr_port1; +output[max_burst_bits-1:0] ddr_wr_data_port1; +output[max_burst_bytes-1:0] ddr_wr_strb_port1; +output[max_burst_bytes_width:0] ddr_wr_bytes_port1; +output[addr_width-1:0] ddr_rd_addr_port1; +input[max_burst_bits-1:0] ddr_rd_data_port1; +output[max_burst_bytes_width:0] ddr_rd_bytes_port1; +output [axi_qos_width-1:0] ddr_wr_qos_port1; +output [axi_qos_width-1:0] ddr_rd_qos_port1; + +/* Goes to port2 of DDR */ +input ddr_wr_ack_port2; +output ddr_wr_dv_port2; +output ddr_rd_req_port2; +input ddr_rd_dv_port2; +output[addr_width-1:0] ddr_wr_addr_port2; +output[max_burst_bits-1:0] ddr_wr_data_port2; +output[max_burst_bytes-1:0] ddr_wr_strb_port2; +output[max_burst_bytes_width:0] ddr_wr_bytes_port2; +output[addr_width-1:0] ddr_rd_addr_port2; +input[max_burst_bits-1:0] ddr_rd_data_port2; +output[max_burst_bytes_width:0] ddr_rd_bytes_port2; +output [axi_qos_width-1:0] ddr_wr_qos_port2; +output [axi_qos_width-1:0] ddr_rd_qos_port2; + +/* Goes to port3 of DDR */ +input ddr_wr_ack_port3; +output ddr_wr_dv_port3; +output ddr_rd_req_port3; +input ddr_rd_dv_port3; +output[addr_width-1:0] ddr_wr_addr_port3; +output[max_burst_bits-1:0] ddr_wr_data_port3; +output[max_burst_bytes-1:0] ddr_wr_strb_port3; +output[max_burst_bytes_width:0] ddr_wr_bytes_port3; +output[addr_width-1:0] ddr_rd_addr_port3; +input[max_burst_bits-1:0] ddr_rd_data_port3; +output[max_burst_bytes_width:0] ddr_rd_bytes_port3; +output [axi_qos_width-1:0] ddr_wr_qos_port3; +output [axi_qos_width-1:0] ddr_rd_qos_port3; + +/* Goes to port1 of OCM */ +input ocm_wr_ack_port1; +output ocm_wr_dv_port1; +output ocm_rd_req_port1; +input ocm_rd_dv_port1; +output[max_burst_bits-1:0] ocm_wr_data_port1; +output[max_burst_bytes-1:0] ocm_wr_strb_port1; +output[addr_width-1:0] ocm_wr_addr_port1; +output[max_burst_bytes_width:0] ocm_wr_bytes_port1; +input[max_burst_bits-1:0] ocm_rd_data_port1; +output[addr_width-1:0] ocm_rd_addr_port1; +output[max_burst_bytes_width:0] ocm_rd_bytes_port1; + +/* Goes to port1 of REG */ +output [axi_qos_width-1:0] reg_rd_qos_port1; +output reg_rd_req_port1; +input reg_rd_dv_port1; +input[max_burst_bits-1:0] reg_rd_data_port1; +output[addr_width-1:0] reg_rd_addr_port1; +output[max_burst_bytes_width:0] reg_rd_bytes_port1; + +wire ocm_wr_dv_osw0; +wire ocm_wr_dv_osw1; +wire[max_burst_bits-1:0] ocm_wr_data_osw0; +wire[max_burst_bits-1:0] ocm_wr_data_osw1; +wire[max_burst_bytes-1:0] ocm_wr_strb_osw0; +wire[max_burst_bytes-1:0] ocm_wr_strb_osw1; +wire[addr_width-1:0] ocm_wr_addr_osw0; +wire[addr_width-1:0] ocm_wr_addr_osw1; +wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0; +wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1; +wire ocm_wr_ack_osw0; +wire ocm_wr_ack_osw1; +wire ocm_rd_req_osw0; +wire ocm_rd_req_osw1; +wire[max_burst_bits-1:0] ocm_rd_data_osw0; +wire[max_burst_bits-1:0] ocm_rd_data_osw1; +wire[addr_width-1:0] ocm_rd_addr_osw0; +wire[addr_width-1:0] ocm_rd_addr_osw1; +wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0; +wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1; +wire ocm_rd_dv_osw0; +wire ocm_rd_dv_osw1; + +wire [axi_qos_width-1:0] ocm_wr_qos_osw0; +wire [axi_qos_width-1:0] ocm_wr_qos_osw1; +wire [axi_qos_width-1:0] ocm_rd_qos_osw0; +wire [axi_qos_width-1:0] ocm_rd_qos_osw1; + + +processing_system7_vip_v1_0_16_fmsw_gp fmsw ( + .sw_clk(sw_clk), + .rstn(rstn), + + .w_qos_gp0(w_qos_gp0), + .r_qos_gp0(r_qos_gp0), + .wr_ack_ocm_gp0(wr_ack_ocm_gp0), + .wr_ack_ddr_gp0(wr_ack_ddr_gp0), + .wr_data_gp0(wr_data_gp0), + .wr_strb_gp0(wr_strb_gp0), + .wr_addr_gp0(wr_addr_gp0), + .wr_bytes_gp0(wr_bytes_gp0), + .wr_dv_ocm_gp0(wr_dv_ocm_gp0), + .wr_dv_ddr_gp0(wr_dv_ddr_gp0), + .rd_req_ocm_gp0(rd_req_ocm_gp0), + .rd_req_ddr_gp0(rd_req_ddr_gp0), + .rd_req_reg_gp0(rd_req_reg_gp0), + .rd_addr_gp0(rd_addr_gp0), + .rd_bytes_gp0(rd_bytes_gp0), + .rd_data_ddr_gp0(rd_data_ddr_gp0), + .rd_data_ocm_gp0(rd_data_ocm_gp0), + .rd_data_reg_gp0(rd_data_reg_gp0), + .rd_dv_ocm_gp0(rd_dv_ocm_gp0), + .rd_dv_ddr_gp0(rd_dv_ddr_gp0), + .rd_dv_reg_gp0(rd_dv_reg_gp0), + + .w_qos_gp1(w_qos_gp1), + .r_qos_gp1(r_qos_gp1), + .wr_ack_ocm_gp1(wr_ack_ocm_gp1), + .wr_ack_ddr_gp1(wr_ack_ddr_gp1), + .wr_data_gp1(wr_data_gp1), + .wr_strb_gp1(wr_strb_gp1), + .wr_addr_gp1(wr_addr_gp1), + .wr_bytes_gp1(wr_bytes_gp1), + .wr_dv_ocm_gp1(wr_dv_ocm_gp1), + .wr_dv_ddr_gp1(wr_dv_ddr_gp1), + .rd_req_ocm_gp1(rd_req_ocm_gp1), + .rd_req_ddr_gp1(rd_req_ddr_gp1), + .rd_req_reg_gp1(rd_req_reg_gp1), + .rd_addr_gp1(rd_addr_gp1), + .rd_bytes_gp1(rd_bytes_gp1), + .rd_data_ddr_gp1(rd_data_ddr_gp1), + .rd_data_ocm_gp1(rd_data_ocm_gp1), + .rd_data_reg_gp1(rd_data_reg_gp1), + .rd_dv_ocm_gp1(rd_dv_ocm_gp1), + .rd_dv_ddr_gp1(rd_dv_ddr_gp1), + .rd_dv_reg_gp1(rd_dv_reg_gp1), + + .ocm_wr_ack (ocm_wr_ack_osw0), + .ocm_wr_dv (ocm_wr_dv_osw0), + .ocm_rd_req (ocm_rd_req_osw0), + .ocm_rd_dv (ocm_rd_dv_osw0), + .ocm_wr_addr(ocm_wr_addr_osw0), + .ocm_wr_data(ocm_wr_data_osw0), + .ocm_wr_strb(ocm_wr_strb_osw0), + .ocm_wr_bytes(ocm_wr_bytes_osw0), + .ocm_rd_addr(ocm_rd_addr_osw0), + .ocm_rd_data(ocm_rd_data_osw0), + .ocm_rd_bytes(ocm_rd_bytes_osw0), + + .ocm_wr_qos(ocm_wr_qos_osw0), + .ocm_rd_qos(ocm_rd_qos_osw0), + + .ddr_wr_qos(ddr_wr_qos_port1), + .ddr_rd_qos(ddr_rd_qos_port1), + + .reg_rd_qos(reg_rd_qos_port1), + + .ddr_wr_ack(ddr_wr_ack_port1), + .ddr_wr_dv(ddr_wr_dv_port1), + .ddr_rd_req(ddr_rd_req_port1), + .ddr_rd_dv(ddr_rd_dv_port1), + .ddr_wr_addr(ddr_wr_addr_port1), + .ddr_wr_data(ddr_wr_data_port1), + .ddr_wr_strb(ddr_wr_strb_port1), + .ddr_wr_bytes(ddr_wr_bytes_port1), + .ddr_rd_addr(ddr_rd_addr_port1), + .ddr_rd_data(ddr_rd_data_port1), + .ddr_rd_bytes(ddr_rd_bytes_port1), + + .reg_rd_req(reg_rd_req_port1), + .reg_rd_dv(reg_rd_dv_port1), + .reg_rd_addr(reg_rd_addr_port1), + .reg_rd_data(reg_rd_data_port1), + .reg_rd_bytes(reg_rd_bytes_port1) +); + + +processing_system7_vip_v1_0_16_ssw_hp ssw( + .sw_clk(sw_clk), + .rstn(rstn), + .w_qos_hp0(w_qos_hp0), + .r_qos_hp0(r_qos_hp0), + .w_qos_hp1(w_qos_hp1), + .r_qos_hp1(r_qos_hp1), + .w_qos_hp2(w_qos_hp2), + .r_qos_hp2(r_qos_hp2), + .w_qos_hp3(w_qos_hp3), + .r_qos_hp3(r_qos_hp3), + + .wr_ack_ddr_hp0(wr_ack_ddr_hp0), + .wr_data_hp0(wr_data_hp0), + .wr_strb_hp0(wr_strb_hp0), + .wr_addr_hp0(wr_addr_hp0), + .wr_bytes_hp0(wr_bytes_hp0), + .wr_dv_ddr_hp0(wr_dv_ddr_hp0), + .rd_req_ddr_hp0(rd_req_ddr_hp0), + .rd_addr_hp0(rd_addr_hp0), + .rd_bytes_hp0(rd_bytes_hp0), + .rd_data_ddr_hp0(rd_data_ddr_hp0), + .rd_data_ocm_hp0(rd_data_ocm_hp0), + .rd_dv_ddr_hp0(rd_dv_ddr_hp0), + + .wr_ack_ocm_hp0(wr_ack_ocm_hp0), + .wr_dv_ocm_hp0(wr_dv_ocm_hp0), + .rd_req_ocm_hp0(rd_req_ocm_hp0), + .rd_dv_ocm_hp0(rd_dv_ocm_hp0), + + .wr_ack_ddr_hp1(wr_ack_ddr_hp1), + .wr_data_hp1(wr_data_hp1), + .wr_strb_hp1(wr_strb_hp1), + .wr_addr_hp1(wr_addr_hp1), + .wr_bytes_hp1(wr_bytes_hp1), + .wr_dv_ddr_hp1(wr_dv_ddr_hp1), + .rd_req_ddr_hp1(rd_req_ddr_hp1), + .rd_addr_hp1(rd_addr_hp1), + .rd_bytes_hp1(rd_bytes_hp1), + .rd_data_ddr_hp1(rd_data_ddr_hp1), + .rd_data_ocm_hp1(rd_data_ocm_hp1), + .rd_dv_ddr_hp1(rd_dv_ddr_hp1), + + .wr_ack_ocm_hp1(wr_ack_ocm_hp1), + .wr_dv_ocm_hp1(wr_dv_ocm_hp1), + .rd_req_ocm_hp1(rd_req_ocm_hp1), + .rd_dv_ocm_hp1(rd_dv_ocm_hp1), + + .wr_ack_ddr_hp2(wr_ack_ddr_hp2), + .wr_data_hp2(wr_data_hp2), + .wr_strb_hp2(wr_strb_hp2), + .wr_addr_hp2(wr_addr_hp2), + .wr_bytes_hp2(wr_bytes_hp2), + .wr_dv_ddr_hp2(wr_dv_ddr_hp2), + .rd_req_ddr_hp2(rd_req_ddr_hp2), + .rd_addr_hp2(rd_addr_hp2), + .rd_bytes_hp2(rd_bytes_hp2), + .rd_data_ddr_hp2(rd_data_ddr_hp2), + .rd_data_ocm_hp2(rd_data_ocm_hp2), + .rd_dv_ddr_hp2(rd_dv_ddr_hp2), + + .wr_ack_ocm_hp2(wr_ack_ocm_hp2), + .wr_dv_ocm_hp2(wr_dv_ocm_hp2), + .rd_req_ocm_hp2(rd_req_ocm_hp2), + .rd_dv_ocm_hp2(rd_dv_ocm_hp2), + + .wr_ack_ddr_hp3(wr_ack_ddr_hp3), + .wr_data_hp3(wr_data_hp3), + .wr_strb_hp3(wr_strb_hp3), + .wr_addr_hp3(wr_addr_hp3), + .wr_bytes_hp3(wr_bytes_hp3), + .wr_dv_ddr_hp3(wr_dv_ddr_hp3), + .rd_req_ddr_hp3(rd_req_ddr_hp3), + .rd_addr_hp3(rd_addr_hp3), + .rd_bytes_hp3(rd_bytes_hp3), + .rd_data_ddr_hp3(rd_data_ddr_hp3), + .rd_data_ocm_hp3(rd_data_ocm_hp3), + .rd_dv_ddr_hp3(rd_dv_ddr_hp3), + + .wr_ack_ocm_hp3(wr_ack_ocm_hp3), + .wr_dv_ocm_hp3(wr_dv_ocm_hp3), + .rd_req_ocm_hp3(rd_req_ocm_hp3), + .rd_dv_ocm_hp3(rd_dv_ocm_hp3), + + .ddr_wr_ack0(ddr_wr_ack_port2), + .ddr_wr_dv0(ddr_wr_dv_port2), + .ddr_rd_req0(ddr_rd_req_port2), + .ddr_rd_dv0(ddr_rd_dv_port2), + .ddr_wr_addr0(ddr_wr_addr_port2), + .ddr_wr_data0(ddr_wr_data_port2), + .ddr_wr_strb0(ddr_wr_strb_port2), + .ddr_wr_bytes0(ddr_wr_bytes_port2), + .ddr_rd_addr0(ddr_rd_addr_port2), + .ddr_rd_data0(ddr_rd_data_port2), + .ddr_rd_bytes0(ddr_rd_bytes_port2), + .ddr_wr_qos0(ddr_wr_qos_port2), + .ddr_rd_qos0(ddr_rd_qos_port2), + + .ddr_wr_ack1(ddr_wr_ack_port3), + .ddr_wr_dv1(ddr_wr_dv_port3), + .ddr_rd_req1(ddr_rd_req_port3), + .ddr_rd_dv1(ddr_rd_dv_port3), + .ddr_wr_addr1(ddr_wr_addr_port3), + .ddr_wr_data1(ddr_wr_data_port3), + .ddr_wr_strb1(ddr_wr_strb_port3), + .ddr_wr_bytes1(ddr_wr_bytes_port3), + .ddr_rd_addr1(ddr_rd_addr_port3), + .ddr_rd_data1(ddr_rd_data_port3), + .ddr_rd_bytes1(ddr_rd_bytes_port3), + .ddr_wr_qos1(ddr_wr_qos_port3), + .ddr_rd_qos1(ddr_rd_qos_port3), + + .ocm_wr_qos(ocm_wr_qos_osw1), + .ocm_rd_qos(ocm_rd_qos_osw1), + + .ocm_wr_ack (ocm_wr_ack_osw1), + .ocm_wr_dv (ocm_wr_dv_osw1), + .ocm_rd_req (ocm_rd_req_osw1), + .ocm_rd_dv (ocm_rd_dv_osw1), + .ocm_wr_addr(ocm_wr_addr_osw1), + .ocm_wr_data(ocm_wr_data_osw1), + .ocm_wr_strb(ocm_wr_strb_osw1), + .ocm_wr_bytes(ocm_wr_bytes_osw1), + .ocm_rd_addr(ocm_rd_addr_osw1), + .ocm_rd_data(ocm_rd_data_osw1), + .ocm_rd_bytes(ocm_rd_bytes_osw1) + +); + +processing_system7_vip_v1_0_16_arb_wr osw_wr ( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(ocm_wr_qos_osw0), /// chk + .qos2(ocm_wr_qos_osw1), /// chk + .prt_dv1(ocm_wr_dv_osw0), + .prt_dv2(ocm_wr_dv_osw1), + .prt_data1(ocm_wr_data_osw0), + .prt_data2(ocm_wr_data_osw1), + .prt_strb1(ocm_wr_strb_osw0), + .prt_strb2(ocm_wr_strb_osw1), + .prt_addr1(ocm_wr_addr_osw0), + .prt_addr2(ocm_wr_addr_osw1), + .prt_bytes1(ocm_wr_bytes_osw0), + .prt_bytes2(ocm_wr_bytes_osw1), + .prt_ack1(ocm_wr_ack_osw0), + .prt_ack2(ocm_wr_ack_osw1), + .prt_req(ocm_wr_dv_port1), + .prt_qos(ocm_wr_qos_port1), + .prt_data(ocm_wr_data_port1), + .prt_strb(ocm_wr_strb_port1), + .prt_addr(ocm_wr_addr_port1), + .prt_bytes(ocm_wr_bytes_port1), + .prt_ack(ocm_wr_ack_port1) +); + +processing_system7_vip_v1_0_16_arb_rd osw_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(ocm_rd_qos_osw0), // chk + .qos2(ocm_rd_qos_osw1), // chk + .prt_req1(ocm_rd_req_osw0), + .prt_req2(ocm_rd_req_osw1), + .prt_data1(ocm_rd_data_osw0), + .prt_data2(ocm_rd_data_osw1), + .prt_addr1(ocm_rd_addr_osw0), + .prt_addr2(ocm_rd_addr_osw1), + .prt_bytes1(ocm_rd_bytes_osw0), + .prt_bytes2(ocm_rd_bytes_osw1), + .prt_dv1(ocm_rd_dv_osw0), + .prt_dv2(ocm_rd_dv_osw1), + .prt_req(ocm_rd_req_port1), + .prt_qos(ocm_rd_qos_port1), + .prt_data(ocm_rd_data_port1), + .prt_addr(ocm_rd_addr_port1), + .prt_bytes(ocm_rd_bytes_port1), + .prt_dv(ocm_rd_dv_port1) +); + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_gen_reset.v + * + * Date : 2012-11 + * + * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the + * respective clocks. + *****************************************************************************/ + `timescale 1ns/1ps +module processing_system7_vip_v1_0_16_gen_reset( + por_rst_n, + sys_rst_n, + rst_out_n, + + m_axi_gp0_clk, + m_axi_gp1_clk, + s_axi_gp0_clk, + s_axi_gp1_clk, + s_axi_hp0_clk, + s_axi_hp1_clk, + s_axi_hp2_clk, + s_axi_hp3_clk, + s_axi_acp_clk, + + m_axi_gp0_rstn, + m_axi_gp1_rstn, + s_axi_gp0_rstn, + s_axi_gp1_rstn, + s_axi_hp0_rstn, + s_axi_hp1_rstn, + s_axi_hp2_rstn, + s_axi_hp3_rstn, + s_axi_acp_rstn, + + fclk_reset3_n, + fclk_reset2_n, + fclk_reset1_n, + fclk_reset0_n, + + fpga_acp_reset_n, + fpga_gp_m0_reset_n, + fpga_gp_m1_reset_n, + fpga_gp_s0_reset_n, + fpga_gp_s1_reset_n, + fpga_hp_s0_reset_n, + fpga_hp_s1_reset_n, + fpga_hp_s2_reset_n, + fpga_hp_s3_reset_n + +); + +input por_rst_n; +input sys_rst_n; +input m_axi_gp0_clk; +input m_axi_gp1_clk; +input s_axi_gp0_clk; +input s_axi_gp1_clk; +input s_axi_hp0_clk; +input s_axi_hp1_clk; +input s_axi_hp2_clk; +input s_axi_hp3_clk; +input s_axi_acp_clk; + +output reg m_axi_gp0_rstn; +output reg m_axi_gp1_rstn; +output reg s_axi_gp0_rstn; +output reg s_axi_gp1_rstn; +output reg s_axi_hp0_rstn; +output reg s_axi_hp1_rstn; +output reg s_axi_hp2_rstn; +output reg s_axi_hp3_rstn; +output reg s_axi_acp_rstn; + +output rst_out_n; +output fclk_reset3_n; +output fclk_reset2_n; +output fclk_reset1_n; +output fclk_reset0_n; + +output fpga_acp_reset_n; +output fpga_gp_m0_reset_n; +output fpga_gp_m1_reset_n; +output fpga_gp_s0_reset_n; +output fpga_gp_s1_reset_n; +output fpga_hp_s0_reset_n; +output fpga_hp_s1_reset_n; +output fpga_hp_s2_reset_n; +output fpga_hp_s3_reset_n; + +reg [31:0] fabric_rst_n; + +reg r_m_axi_gp0_rstn; +reg r_m_axi_gp1_rstn; +reg r_s_axi_gp0_rstn; +reg r_s_axi_gp1_rstn; +reg r_s_axi_hp0_rstn; +reg r_s_axi_hp1_rstn; +reg r_s_axi_hp2_rstn; +reg r_s_axi_hp3_rstn; +reg r_s_axi_acp_rstn; + +assign rst_out_n = por_rst_n & sys_rst_n; + +assign fclk_reset0_n = !fabric_rst_n[0]; +assign fclk_reset1_n = !fabric_rst_n[1]; +assign fclk_reset2_n = !fabric_rst_n[2]; +assign fclk_reset3_n = !fabric_rst_n[3]; + +assign fpga_acp_reset_n = !fabric_rst_n[24]; + +assign fpga_hp_s3_reset_n = !fabric_rst_n[23]; +assign fpga_hp_s2_reset_n = !fabric_rst_n[22]; +assign fpga_hp_s1_reset_n = !fabric_rst_n[21]; +assign fpga_hp_s0_reset_n = !fabric_rst_n[20]; + +assign fpga_gp_s1_reset_n = !fabric_rst_n[17]; +assign fpga_gp_s0_reset_n = !fabric_rst_n[16]; +assign fpga_gp_m1_reset_n = !fabric_rst_n[13]; +assign fpga_gp_m0_reset_n = !fabric_rst_n[12]; + +task fpga_soft_reset; +input[31:0] reset_ctrl; + begin + fabric_rst_n[0] = reset_ctrl[0]; + fabric_rst_n[1] = reset_ctrl[1]; + fabric_rst_n[2] = reset_ctrl[2]; + fabric_rst_n[3] = reset_ctrl[3]; + + fabric_rst_n[12] = reset_ctrl[12]; + fabric_rst_n[13] = reset_ctrl[13]; + fabric_rst_n[16] = reset_ctrl[16]; + fabric_rst_n[17] = reset_ctrl[17]; + + fabric_rst_n[20] = reset_ctrl[20]; + fabric_rst_n[21] = reset_ctrl[21]; + fabric_rst_n[22] = reset_ctrl[22]; + fabric_rst_n[23] = reset_ctrl[23]; + + fabric_rst_n[24] = reset_ctrl[24]; + end +endtask + +// task por_srstb_reset; +// input por_reset_ctrl; +// begin +// por_rst_n = por_reset_ctrl; +// sys_rst_n = por_reset_ctrl; +// end +// endtask + +always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f; + +always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + m_axi_gp0_rstn = 1'b0; + else + m_axi_gp0_rstn = 1'b1; + end + +always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + m_axi_gp1_rstn = 1'b0; + else + m_axi_gp1_rstn = 1'b1; + end + +always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_gp0_rstn = 1'b0; + else + s_axi_gp0_rstn = 1'b1; + end + +always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_gp1_rstn = 1'b0; + else + s_axi_gp1_rstn = 1'b1; + end + +always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp0_rstn = 1'b0; + else + s_axi_hp0_rstn = 1'b1; + end + +always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp1_rstn = 1'b0; + else + s_axi_hp1_rstn = 1'b1; + end + +always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp2_rstn = 1'b0; + else + s_axi_hp2_rstn = 1'b1; + end + +always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp3_rstn = 1'b0; + else + s_axi_hp3_rstn = 1'b1; + end + +always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_acp_rstn = 1'b0; + else + s_axi_acp_rstn = 1'b1; + end + + +always@(*) begin + if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin + $display(" Error:processing_system7_vip_v1_0_16_gen_reset. PS_PORB and PS_SRSTB must be driven to known state"); + $finish(); + end +end + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_gen_clock.v + * + * Date : 2012-11 + * + * Description : Module that generates FCLK clocks and internal clock for Zynq VIP. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_gen_clock( + ps_clk, + sw_clk, + + fclk_clk3, + fclk_clk2, + fclk_clk1, + fclk_clk0 +); + +input ps_clk; +output sw_clk; + +output fclk_clk3; +output fclk_clk2; +output fclk_clk1; +output fclk_clk0; + +parameter freq_clk3 = 50; +parameter freq_clk2 = 50; +parameter freq_clk1 = 50; +parameter freq_clk0 = 50; + +bit clk0; +bit clk1; +bit clk2; +bit clk3; +reg sw_clk = 1'b0; + +assign fclk_clk0 = clk0; +assign fclk_clk1 = clk1; +assign fclk_clk2 = clk2; +assign fclk_clk3 = clk3; + +real clk3_p = (1000.00/freq_clk3)/2; +real clk2_p = (1000.00/freq_clk2)/2; +real clk1_p = (1000.00/freq_clk1)/2; +real clk0_p = (1000.00/freq_clk0)/2; + +always #(clk3_p) clk3 = !clk3; +always #(clk2_p) clk2 = !clk2; +always #(clk1_p) clk1 = !clk1; +always #(clk0_p) clk0 = !clk0; + +always #(0.5) sw_clk = !sw_clk; + + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_ddrc.v + * + * Date : 2012-11 + * + * Description : Module that acts as controller for sparse memory (DDR). + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16_ddrc( + rstn, + sw_clk, + +/* Goes to port 0 of DDR */ + ddr_wr_ack_port0, + ddr_wr_dv_port0, + ddr_rd_req_port0, + ddr_rd_dv_port0, + ddr_wr_addr_port0, + ddr_wr_data_port0, + ddr_wr_strb_port0, + ddr_wr_bytes_port0, + ddr_rd_addr_port0, + ddr_rd_data_port0, + ddr_rd_bytes_port0, + ddr_wr_qos_port0, + ddr_rd_qos_port0, + + +/* Goes to port 1 of DDR */ + ddr_wr_ack_port1, + ddr_wr_dv_port1, + ddr_rd_req_port1, + ddr_rd_dv_port1, + ddr_wr_addr_port1, + ddr_wr_data_port1, + ddr_wr_strb_port1, + ddr_wr_bytes_port1, + ddr_rd_addr_port1, + ddr_rd_data_port1, + ddr_rd_bytes_port1, + ddr_wr_qos_port1, + ddr_rd_qos_port1, + +/* Goes to port2 of DDR */ + ddr_wr_ack_port2, + ddr_wr_dv_port2, + ddr_rd_req_port2, + ddr_rd_dv_port2, + ddr_wr_addr_port2, + ddr_wr_data_port2, + ddr_wr_strb_port2, + ddr_wr_bytes_port2, + ddr_rd_addr_port2, + ddr_rd_data_port2, + ddr_rd_bytes_port2, + ddr_wr_qos_port2, + ddr_rd_qos_port2, + +/* Goes to port3 of DDR */ + ddr_wr_ack_port3, + ddr_wr_dv_port3, + ddr_rd_req_port3, + ddr_rd_dv_port3, + ddr_wr_addr_port3, + ddr_wr_data_port3, + ddr_wr_strb_port3, + ddr_wr_bytes_port3, + ddr_rd_addr_port3, + ddr_rd_data_port3, + ddr_rd_bytes_port3, + ddr_wr_qos_port3, + ddr_rd_qos_port3 + +); + +`include "processing_system7_vip_v1_0_16_local_params.v" + +input rstn; +input sw_clk; + +output ddr_wr_ack_port0; +input ddr_wr_dv_port0; +input ddr_rd_req_port0; +output ddr_rd_dv_port0; +input[addr_width-1:0] ddr_wr_addr_port0; +input[max_burst_bits-1:0] ddr_wr_data_port0; +input[max_burst_bytes_width:0] ddr_wr_bytes_port0; +input[max_burst_bytes-1:0] ddr_wr_strb_port0; +input[addr_width-1:0] ddr_rd_addr_port0; +output[max_burst_bits-1:0] ddr_rd_data_port0; +input[max_burst_bytes_width:0] ddr_rd_bytes_port0; +input [axi_qos_width-1:0] ddr_wr_qos_port0; +input [axi_qos_width-1:0] ddr_rd_qos_port0; + +output ddr_wr_ack_port1; +input ddr_wr_dv_port1; +input ddr_rd_req_port1; +output ddr_rd_dv_port1; +input[addr_width-1:0] ddr_wr_addr_port1; +input[max_burst_bits-1:0] ddr_wr_data_port1; +input[max_burst_bytes_width:0] ddr_wr_bytes_port1; +input[max_burst_bytes-1:0] ddr_wr_strb_port1; +input[addr_width-1:0] ddr_rd_addr_port1; +output[max_burst_bits-1:0] ddr_rd_data_port1; +input[max_burst_bytes_width:0] ddr_rd_bytes_port1; +input[axi_qos_width-1:0] ddr_wr_qos_port1; +input[axi_qos_width-1:0] ddr_rd_qos_port1; + +output ddr_wr_ack_port2; +input ddr_wr_dv_port2; +input ddr_rd_req_port2; +output ddr_rd_dv_port2; +input[addr_width-1:0] ddr_wr_addr_port2; +input[max_burst_bits-1:0] ddr_wr_data_port2; +input[max_burst_bytes_width:0] ddr_wr_bytes_port2; +input[max_burst_bytes-1:0] ddr_wr_strb_port2; +input[addr_width-1:0] ddr_rd_addr_port2; +output[max_burst_bits-1:0] ddr_rd_data_port2; +input[max_burst_bytes_width:0] ddr_rd_bytes_port2; +input[axi_qos_width-1:0] ddr_wr_qos_port2; +input[axi_qos_width-1:0] ddr_rd_qos_port2; + +output ddr_wr_ack_port3; +input ddr_wr_dv_port3; +input ddr_rd_req_port3; +output ddr_rd_dv_port3; +input[addr_width-1:0] ddr_wr_addr_port3; +input[max_burst_bits-1:0] ddr_wr_data_port3; +input[max_burst_bytes_width:0] ddr_wr_bytes_port3; +input[max_burst_bytes-1:0] ddr_wr_strb_port3; +input[addr_width-1:0] ddr_rd_addr_port3; +output[max_burst_bits-1:0] ddr_rd_data_port3; +input[max_burst_bytes_width:0] ddr_rd_bytes_port3; +input[axi_qos_width-1:0] ddr_wr_qos_port3; +input[axi_qos_width-1:0] ddr_rd_qos_port3; + +wire [axi_qos_width-1:0] wr_qos; +wire wr_req; +wire [max_burst_bits-1:0] wr_data; +wire [max_burst_bytes-1:0] wr_strb; +wire [addr_width-1:0] wr_addr; +wire [max_burst_bytes_width:0] wr_bytes; +reg wr_ack; + +wire [axi_qos_width-1:0] rd_qos; +reg [max_burst_bits-1:0] rd_data; +wire [addr_width-1:0] rd_addr; +wire [max_burst_bytes_width:0] rd_bytes; +reg rd_dv; +wire rd_req; + +processing_system7_vip_v1_0_16_arb_wr_4 ddr_write_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ddr_wr_qos_port0), + .qos2(ddr_wr_qos_port1), + .qos3(ddr_wr_qos_port2), + .qos4(ddr_wr_qos_port3), + + .prt_dv1(ddr_wr_dv_port0), + .prt_dv2(ddr_wr_dv_port1), + .prt_dv3(ddr_wr_dv_port2), + .prt_dv4(ddr_wr_dv_port3), + + .prt_data1(ddr_wr_data_port0), + .prt_data2(ddr_wr_data_port1), + .prt_data3(ddr_wr_data_port2), + .prt_data4(ddr_wr_data_port3), + + .prt_strb1(ddr_wr_strb_port0), + .prt_strb2(ddr_wr_strb_port1), + .prt_strb3(ddr_wr_strb_port2), + .prt_strb4(ddr_wr_strb_port3), + + .prt_addr1(ddr_wr_addr_port0), + .prt_addr2(ddr_wr_addr_port1), + .prt_addr3(ddr_wr_addr_port2), + .prt_addr4(ddr_wr_addr_port3), + + .prt_bytes1(ddr_wr_bytes_port0), + .prt_bytes2(ddr_wr_bytes_port1), + .prt_bytes3(ddr_wr_bytes_port2), + .prt_bytes4(ddr_wr_bytes_port3), + + .prt_ack1(ddr_wr_ack_port0), + .prt_ack2(ddr_wr_ack_port1), + .prt_ack3(ddr_wr_ack_port2), + .prt_ack4(ddr_wr_ack_port3), + + .prt_qos(wr_qos), + .prt_req(wr_req), + .prt_data(wr_data), + .prt_strb(wr_strb), + .prt_addr(wr_addr), + .prt_bytes(wr_bytes), + .prt_ack(wr_ack) + +); + +processing_system7_vip_v1_0_16_arb_rd_4 ddr_read_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ddr_rd_qos_port0), + .qos2(ddr_rd_qos_port1), + .qos3(ddr_rd_qos_port2), + .qos4(ddr_rd_qos_port3), + + .prt_req1(ddr_rd_req_port0), + .prt_req2(ddr_rd_req_port1), + .prt_req3(ddr_rd_req_port2), + .prt_req4(ddr_rd_req_port3), + + .prt_data1(ddr_rd_data_port0), + .prt_data2(ddr_rd_data_port1), + .prt_data3(ddr_rd_data_port2), + .prt_data4(ddr_rd_data_port3), + + .prt_addr1(ddr_rd_addr_port0), + .prt_addr2(ddr_rd_addr_port1), + .prt_addr3(ddr_rd_addr_port2), + .prt_addr4(ddr_rd_addr_port3), + + .prt_bytes1(ddr_rd_bytes_port0), + .prt_bytes2(ddr_rd_bytes_port1), + .prt_bytes3(ddr_rd_bytes_port2), + .prt_bytes4(ddr_rd_bytes_port3), + + .prt_dv1(ddr_rd_dv_port0), + .prt_dv2(ddr_rd_dv_port1), + .prt_dv3(ddr_rd_dv_port2), + .prt_dv4(ddr_rd_dv_port3), + + .prt_qos(rd_qos), + .prt_req(rd_req), + .prt_data(rd_data), + .prt_addr(rd_addr), + .prt_bytes(rd_bytes), + .prt_dv(rd_dv) + +); + +processing_system7_vip_v1_0_16_sparse_mem ddr(); + +reg [1:0] state; +// always@(posedge sw_clk or negedge rstn) +// begin +// if(!rstn) begin +// wr_ack <= 0; +// rd_dv <= 0; +// state <= 2'd0; +// end else begin +// case(state) +// 0:begin +// state <= 0; +// wr_ack <= 0; +// rd_dv <= 0; +// if(wr_req) begin +// ddr.write_mem(wr_data , wr_addr, wr_bytes); +// wr_ack <= 1; +// state <= 1; +// end +// if(rd_req) begin +// ddr.read_mem(rd_data,rd_addr, rd_bytes); +// rd_dv <= 1; +// state <= 1; +// end +// +// end +// 1:begin +// wr_ack <= 0; +// rd_dv <= 0; +// state <= 0; +// end +// +// endcase +// end /// if +// end// always + + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + wr_ack <= 0; + rd_dv <= 0; + state <= 2'd0; +end else begin + case(state) + 0:begin + state <= 0; + wr_ack <= 0; + rd_dv <= 0; + if(wr_req) begin + //$display("wr_addr %0h,wr_data %0h,wr_bytes %0h , wr_strb %0h ",wr_addr,wr_data,wr_bytes,wr_strb); + ddr.write_mem(wr_data , wr_addr, wr_bytes, wr_strb); + // ddr.write_mem(wr_data , wr_addr, wr_bytes, 16'hFFFF); + wr_ack <= 1; + state <= 1; + end + if(rd_req) begin + ddr.read_mem(rd_data,rd_addr, rd_bytes); + // $display("rd_addr %0h,rd_data %0h , rd_bytes %0h ",rd_addr,rd_data,rd_bytes); + rd_dv <= 1; + state <= 1; + end + + end + 1:begin + wr_ack <= 0; + rd_dv <= 0; + state <= 0; + end + + endcase +end /// if +end// always + + + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_axi_slave.v + * + * Date : 2012-11 + * + * Description : Model that acts as PS AXI Slave port interface. + * It uses AXI3 Slave VIP + *****************************************************************************/ + `timescale 1ns/1ps + +import axi_vip_pkg::*; + +module processing_system7_vip_v1_0_16_axi_slave ( + S_RESETN, + + S_ARREADY, + S_AWREADY, + S_BVALID, + S_RLAST, + S_RVALID, + S_WREADY, + S_BRESP, + S_RRESP, + S_RDATA, + S_BID, + S_RID, + S_ACLK, + S_ARVALID, + S_AWVALID, + S_BREADY, + S_RREADY, + S_WLAST, + S_WVALID, + S_ARBURST, + S_ARLOCK, + S_ARSIZE, + S_AWBURST, + S_AWLOCK, + S_AWSIZE, + S_ARPROT, + S_AWPROT, + S_ARADDR, + S_AWADDR, + S_WDATA, + S_ARCACHE, + S_ARLEN, + S_AWCACHE, + S_AWLEN, + S_WSTRB, + S_ARID, + S_AWID, + S_WID, + + S_AWQOS, + S_ARQOS, + + SW_CLK, + WR_DATA_ACK_OCM, + WR_DATA_ACK_DDR, + WR_ADDR, + WR_DATA, + WR_DATA_STRB, + WR_BYTES, + WR_DATA_VALID_OCM, + WR_DATA_VALID_DDR, + WR_QOS, + + RD_QOS, + RD_REQ_DDR, + RD_REQ_OCM, + RD_REQ_REG, + RD_ADDR, + RD_DATA_OCM, + RD_DATA_DDR, + RD_DATA_REG, + RD_BYTES, + RD_DATA_VALID_OCM, + RD_DATA_VALID_DDR, + RD_DATA_VALID_REG + +); + + parameter enable_this_port = 0; + parameter slave_name = "Slave"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter slave_base_address = 0; + parameter slave_high_address = 4; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + parameter max_wr_outstanding_transactions = 8; + parameter max_rd_outstanding_transactions = 8; + parameter wr_bytes_lsb = 0; + `include "processing_system7_vip_v1_0_16_local_params.v" + parameter wr_bytes_msb = max_burst_bytes_width; + parameter wr_addr_lsb = wr_bytes_msb + 1; + parameter wr_addr_msb = wr_addr_lsb + addr_width-1; + parameter wr_data_lsb = wr_addr_msb + 1; + +parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1); + /* Local parameters only for this module */ + /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles. + This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. + 1-bit extra width than the no.of.bits needed to represent the outstanding transactions + Extra bit helps in generating the empty and full flags + */ + parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1; + parameter wr_qos_lsb = wr_data_msb + 1; + parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; + // parameter wr_strb_lsb = wr_qos_msb + 1; + // parameter wr_strb_msb = wr_strb_lsb + ((data_bus_width/8)*axi_burst_len)-1; + parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1); + parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1); + + /* RESP data */ + // parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1); + // parameter wr_bytes_lsb = 0; + // parameter wr_bytes_msb = max_burst_bytes_width; + // parameter wr_addr_lsb = wr_bytes_msb + 1; + // parameter wr_addr_msb = wr_addr_lsb + addr_width-1; + // parameter wr_data_lsb = wr_addr_msb + 1; + // parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1; + // parameter wr_qos_lsb = wr_data_msb + 1; + // parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; + parameter wr_strb_lsb = wr_qos_msb + 1; + parameter wr_strb_msb = wr_strb_lsb + ((data_bus_width/8)*axi_burst_len)-1; + + /* RESP data */ + parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; + parameter rsp_lsb = 0; + parameter rsp_msb = axi_rsp_width-1; + parameter rsp_id_lsb = rsp_msb + 1; + parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; + + input S_RESETN; + + output S_ARREADY; + output S_AWREADY; + output S_BVALID; + output S_RLAST; + output S_RVALID; + output S_WREADY; + output [axi_rsp_width-1:0] S_BRESP; + output [axi_rsp_width-1:0] S_RRESP; + output [data_bus_width-1:0] S_RDATA; + output [id_bus_width-1:0] S_BID; + output [id_bus_width-1:0] S_RID; + input S_ACLK; + input S_ARVALID; + input S_AWVALID; + input S_BREADY; + input S_RREADY; + input S_WLAST; + input S_WVALID; + input [axi_brst_type_width-1:0] S_ARBURST; + input [axi_lock_width-1:0] S_ARLOCK; + input [axi_size_width-1:0] S_ARSIZE; + input [axi_brst_type_width-1:0] S_AWBURST; + input [axi_lock_width-1:0] S_AWLOCK; + input [axi_size_width-1:0] S_AWSIZE; + input [axi_prot_width-1:0] S_ARPROT; + input [axi_prot_width-1:0] S_AWPROT; + input [address_bus_width-1:0] S_ARADDR; + input [address_bus_width-1:0] S_AWADDR; + input [data_bus_width-1:0] S_WDATA; + input [axi_cache_width-1:0] S_ARCACHE; + input [axi_len_width-1:0] S_ARLEN; + + input [axi_qos_width-1:0] S_ARQOS; + + input [axi_cache_width-1:0] S_AWCACHE; + input [axi_len_width-1:0] S_AWLEN; + + input [axi_qos_width-1:0] S_AWQOS; + input [(data_bus_width/8)-1:0] S_WSTRB; + input [id_bus_width-1:0] S_ARID; + input [id_bus_width-1:0] S_AWID; + input [id_bus_width-1:0] S_WID; + + input SW_CLK; + input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; + output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; + output reg [max_burst_bits-1:0] WR_DATA; + output reg [((data_bus_width/8)*axi_burst_len)-1:0] WR_DATA_STRB; + output reg [addr_width-1:0] WR_ADDR; + output reg [max_burst_bytes_width:0] WR_BYTES; + output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG; + output reg [addr_width-1:0] RD_ADDR; + input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG; + output reg[max_burst_bytes_width:0] RD_BYTES; + input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG; + output reg [axi_qos_width-1:0] WR_QOS, RD_QOS; + wire net_ARVALID; + wire net_AWVALID; + wire net_WVALID; + bit [31:0] static_count; + + real s_aclk_period1; + real s_aclk_period2; + real diff_time = 1; + + axi_slv_agent #(1,address_bus_width, data_bus_width, data_bus_width, id_bus_width,id_bus_width,0,0,0,0,0,1,1,1,1,0,1,1,1,1,1,1) slv; + + axi_vip_v1_1_14_top #( + .C_AXI_PROTOCOL(1), + .C_AXI_INTERFACE_MODE(2), + .C_AXI_ADDR_WIDTH(address_bus_width), + .C_AXI_WDATA_WIDTH(data_bus_width), + .C_AXI_RDATA_WIDTH(data_bus_width), + .C_AXI_WID_WIDTH(id_bus_width), + .C_AXI_RID_WIDTH(id_bus_width), + .C_AXI_AWUSER_WIDTH(0), + .C_AXI_ARUSER_WIDTH(0), + .C_AXI_WUSER_WIDTH(0), + .C_AXI_RUSER_WIDTH(0), + .C_AXI_BUSER_WIDTH(0), + .C_AXI_SUPPORTS_NARROW(1), + .C_AXI_HAS_BURST(1), + .C_AXI_HAS_LOCK(1), + .C_AXI_HAS_CACHE(1), + .C_AXI_HAS_REGION(0), + .C_AXI_HAS_PROT(1), + .C_AXI_HAS_QOS(1), + .C_AXI_HAS_WSTRB(1), + .C_AXI_HAS_BRESP(1), + .C_AXI_HAS_RRESP(1), + .C_AXI_HAS_ARESETN(1) + ) slave ( + .aclk(S_ACLK), + .aclken(1'B1), + .aresetn(S_RESETN), + .s_axi_awid(S_AWID), + .s_axi_awaddr(S_AWADDR), + .s_axi_awlen(S_AWLEN), + .s_axi_awsize(S_AWSIZE), + .s_axi_awburst(S_AWBURST), + .s_axi_awlock(S_AWLOCK), + .s_axi_awcache(S_AWCACHE), + .s_axi_awprot(S_AWPROT), + .s_axi_awregion(4'B0), + .s_axi_awqos(4'h0), + .s_axi_awuser(1'B0), + .s_axi_awvalid(S_AWVALID), + .s_axi_awready(S_AWREADY), + .s_axi_wid(S_WID), + .s_axi_wdata(S_WDATA), + .s_axi_wstrb(S_WSTRB), + .s_axi_wlast(S_WLAST), + .s_axi_wuser(1'B0), + .s_axi_wvalid(S_WVALID), + .s_axi_wready(S_WREADY), + .s_axi_bid(S_BID), + .s_axi_bresp(S_BRESP), + .s_axi_buser(), + .s_axi_bvalid(S_BVALID), + .s_axi_bready(S_BREADY), + .s_axi_arid(S_ARID), + .s_axi_araddr(S_ARADDR), + .s_axi_arlen(S_ARLEN), + .s_axi_arsize(S_ARSIZE), + .s_axi_arburst(S_ARBURST), + .s_axi_arlock(S_ARLOCK), + .s_axi_arcache(S_ARCACHE), + .s_axi_arprot(S_ARPROT), + .s_axi_arregion(4'B0), + .s_axi_arqos(S_ARQOS), + .s_axi_aruser(1'B0), + .s_axi_arvalid(S_ARVALID), + .s_axi_arready(S_ARREADY), + .s_axi_rid(S_RID), + .s_axi_rdata(S_RDATA), + .s_axi_rresp(S_RRESP), + .s_axi_rlast(S_RLAST), + .s_axi_ruser(), + .s_axi_rvalid(S_RVALID), + .s_axi_rready(S_RREADY), + .m_axi_awid(), + .m_axi_awaddr(), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(), + .m_axi_awready(1'b0), + .m_axi_wid(), + .m_axi_wdata(), + .m_axi_wstrb(), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(), + .m_axi_wready(1'b0), + .m_axi_bid(12'h000), + .m_axi_bresp(2'b00), + .m_axi_buser(1'B0), + .m_axi_bvalid(1'b0), + .m_axi_bready(), + .m_axi_arid(), + .m_axi_araddr(), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(), + .m_axi_arregion(), + .m_axi_arqos(), + .m_axi_aruser(), + .m_axi_arvalid(), + .m_axi_arready(1'b0), + .m_axi_rid(12'h000), + .m_axi_rdata(32'h00000000), + .m_axi_rresp(2'b00), + .m_axi_rlast(1'b0), + .m_axi_ruser(1'B0), + .m_axi_rvalid(1'b0), + .m_axi_rready() + ); + + xil_axi_cmd_beat twc, trc; + xil_axi_write_beat twd; + xil_axi_read_beat trd; + axi_transaction twr, trr,trr_get_rd; + axi_transaction trr_rd[$]; + + + axi_ready_gen awready_gen; + axi_ready_gen wready_gen; + axi_ready_gen arready_gen; + integer i,j,k,add_val,size_local,burst_local,len_local,num_bytes; + bit [3:0] a; + bit [15:0] a_16_bits,a_new,a_wrap,a_wrt_val,a_cnt; + + initial begin + slv = new("slv",slave.IF); + twr = new("twr"); + trr = new("trr"); + trr_get_rd = new("trr_get_rd"); + wready_gen = slv.wr_driver.create_ready("wready"); + slv.monitor.axi_wr_cmd_port.set_enabled(); + slv.monitor.axi_wr_beat_port.set_enabled(); + slv.monitor.axi_rd_cmd_port.set_enabled(); + slv.wr_driver.set_transaction_depth(max_wr_outstanding_transactions); + slv.rd_driver.set_transaction_depth(max_rd_outstanding_transactions); + slv.start_slave(); + end + + initial begin + slave.IF.set_enable_xchecks_to_warn(); + repeat(10) @(posedge S_ACLK); + slave.IF.set_enable_xchecks(); + end + + /* Latency type and Debug/Error Control */ + reg[1:0] latency_type = RANDOM_CASE; + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1'b1; + + /* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */ + reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1]; + reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; + wire wr_fifo_empty; + + /* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/ + reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0; + real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received + reg awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received + + /* Address Write Channel handshake*/ + reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1]; + reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1]; + reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1]; + reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1]; + reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1]; + reg aw_flag [0:max_wr_outstanding_transactions-1]; + reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1]; + reg [addr_width-1:0] addr_wr_local; + reg [addr_width-1:0] addr_wr_final; + + reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1]; + reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1]; + wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) + + /* internal fifos to store burst write data, ID & strobes*/ + reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1]; + reg [((data_bus_width/8)*axi_burst_len)-1:0] burst_strb [0:max_wr_outstanding_transactions-1]; + + reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer + reg [max_burst_bytes_width:0] valid_bytes = 0; /// total valid bytes received in a complete burst transfer + reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received + wire wd_fifo_full; + + /* Write Data Channel and Write Response handshake signals*/ + reg [int_wr_cntr_width-1:0] wd_cnt = 0; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; + reg [((data_bus_width/8)*axi_burst_len)-1:0] aligned_wr_strb; + reg [addr_width-1:0] aligned_wr_addr; + reg [max_burst_bytes_width:0] valid_data_bytes; + reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0; + reg [axi_rsp_width-1:0] bresp; + reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_bresp; + reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0; + integer wr_latency_count; + reg wr_delayed; + wire bresp_fifo_empty; + + /* states for managing read/write to WR_FIFO */ + parameter SEND_DATA = 0, WAIT_ACK = 1; + reg state; + + /* Qos*/ + reg [axi_qos_width-1:0] ar_qos, aw_qos; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); + end + end + +//initial slave.set_disable_reset_value_checks(1); + initial begin + repeat(2) @(posedge S_ACLK); + if(!enable_this_port) begin +// slave.set_channel_level_info(0); +// slave.set_function_level_info(0); + end +// slave.RESPONSE_TIMEOUT = 0; + end + /*--------------------------------------------------------------------------------*/ + + /* Set Latency type to be used */ + task set_latency_type; + input[1:0] lat; + begin + if(enable_this_port) + latency_type = lat; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set verbosity to be used */ + task automatic set_verbosity; + input[31:0] verb; + begin + if(enable_this_port) begin + slv.set_verbosity(verb); + end else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. set_verbosity will not be set...",$time, DISP_WARN, slave_name); + end + + end + endtask + /*--------------------------------------------------------------------------------*/ + + + + /* Set ARQoS to be used */ + task automatic set_arqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) begin + ar_qos = qos; + end else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name); + end + + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set AWQoS to be used */ + task set_awqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + aw_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + /* get the wr latency number */ + function [31:0] get_wr_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min; + AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg; + WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min); + 2'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg); + default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* get the rd latency number */ + function [31:0] get_rd_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min; + AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg; + WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min); + 2'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg); + default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max); + endcase + end + endcase + end + endfunction + + /* Store the Clock cycle time period */ + always@(S_RESETN) + begin + if(S_RESETN) begin + diff_time = 1; + @(posedge S_ACLK); + s_aclk_period1 = $realtime; + @(posedge S_ACLK); + s_aclk_period2 = $realtime; + diff_time = s_aclk_period2 - s_aclk_period1; + end + end + /*--------------------------------------------------------------------------------*/ + + /* Check for any WRITE/READs when this port is disabled */ + always@(S_AWVALID or S_WVALID or S_ARVALID) + begin + if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name); + //== $stop; + $finish; + end + end + + /*--------------------------------------------------------------------------------*/ + + + assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0; + assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0; + assign net_WVALID = enable_this_port ? S_WVALID : 1'b0; + + assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0; + assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this + assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this + assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0; + + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) + aw_time_cnt = 0; + else begin + if(net_AWVALID && S_AWREADY) begin + awvalid_receive_time[aw_time_cnt] = $realtime; + awvalid_flag[aw_time_cnt] = 1'b1; + aw_time_cnt = aw_time_cnt + 1; + if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_AWVALID && S_AWREADY) begin + if(S_AWQOS === 0) begin awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos; + end else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS; + end + end + /*--------------------------------------------------------------------------------*/ + + always@(aw_fifo_full) + begin + if(aw_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions); + end + /*--------------------------------------------------------------------------------*/ + + /* Address Write Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + aw_cnt = 0; + end else begin + if(!aw_fifo_full) begin + slv.monitor.axi_wr_cmd_port.get(twc); + // awaddr[aw_cnt[int_wr_cntr_width-2:0]] = twc.addr; + awlen[aw_cnt[int_wr_cntr_width-2:0]] = twc.len; + awsize[aw_cnt[int_wr_cntr_width-2:0]] = twc.size; + awbrst[aw_cnt[int_wr_cntr_width-2:0]] = twc.burst; + awlock[aw_cnt[int_wr_cntr_width-2:0]] = twc.lock; + awcache[aw_cnt[int_wr_cntr_width-2:0]]= twc.cache; + awprot[aw_cnt[int_wr_cntr_width-2:0]] = twc.prot; + awid[aw_cnt[int_wr_cntr_width-2:0]] = twc.id; + aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1; + // aw_cnt = aw_cnt + 1; + size_local = twc.size; + burst_local = twc.burst; + len_local = twc.len; + if(burst_local == AXI_INCR || burst_local == AXI_FIXED) begin + if(data_bus_width === 'd128) begin + if(size_local === 'd0) a = {twc.addr[3:0]}; + if(size_local === 'd1) a = {twc.addr[3:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[3:2],2'b0}; + if(size_local === 'd3) a = {twc.addr[3],3'b0}; + if(size_local === 'd4) a = 'b0; + end else if(data_bus_width === 'd64 ) begin + if(size_local === 'd0) a = {twc.addr[2:0]}; + if(size_local === 'd1) a = {twc.addr[2:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[2],2'b0}; + if(size_local === 'd3) a = 'b0; + end else if(data_bus_width === 'd32 ) begin + if(size_local === 'd0) a = {twc.addr[1:0]}; + if(size_local === 'd1) a = {twc.addr[1],1'b0}; + if(size_local === 'd2) a = 'b0; + end + end if(burst_local == AXI_WRAP) begin + if(data_bus_width === 'd128) begin + if(size_local === 'd0) a = {twc.addr[3:0]}; + if(size_local === 'd1) a = {twc.addr[3:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[3:2],2'b0}; + if(size_local === 'd3) a = {twc.addr[3],3'b0}; + if(size_local === 'd4) a = 'b0; + end else if(data_bus_width === 'd64 ) begin + if(size_local === 'd0) a = {twc.addr[2:0]}; + if(size_local === 'd1) a = {twc.addr[2:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[2],2'b0}; + if(size_local === 'd3) a = 'b0; + end else if(data_bus_width === 'd32 ) begin + if(size_local === 'd0) a = {twc.addr[1:0]}; + if(size_local === 'd1) a = {twc.addr[1],1'b0}; + if(size_local === 'd2) a = 'b0; + end + // a = twc.addr[3:0]; + a_16_bits = twc.addr[7:0]; + num_bytes = ((len_local+1)*(2**size_local)); + // $display("num_bytes %0d num_bytes %0h",num_bytes,num_bytes); + end + addr_wr_local = twc.addr; + if(burst_local == AXI_INCR || burst_local == AXI_FIXED) begin + case(size_local) + 0 : addr_wr_final = {addr_wr_local}; + 1 : addr_wr_final = {addr_wr_local[31:1],1'b0}; + 2 : addr_wr_final = {addr_wr_local[31:2],2'b0}; + 3 : addr_wr_final = {addr_wr_local[31:3],3'b0}; + 4 : addr_wr_final = {addr_wr_local[31:4],4'b0}; + 5 : addr_wr_final = {addr_wr_local[31:5],5'b0}; + 6 : addr_wr_final = {addr_wr_local[31:6],6'b0}; + 7 : addr_wr_final = {addr_wr_local[31:7],7'b0}; + endcase + awaddr[aw_cnt[int_wr_cntr_width-2:0]] = addr_wr_final; + // $display("addr_wr_final %0h",addr_wr_final); + end if(burst_local == AXI_WRAP) begin + awaddr[aw_cnt[int_wr_cntr_width-2:0]] = twc.addr; + // $display(" awaddr[aw_cnt[int_wr_cntr_width-2:0]] %0h",awaddr[aw_cnt[int_wr_cntr_width-2:0]]); + end + aw_cnt = aw_cnt + 1; + // if(data_bus_width === 'd32) a = 0; + // if(data_bus_width === 'd64) a = twc.addr[2:0]; + // if(data_bus_width === 'd128) a = twc.addr[3:0]; + // $display("twc.size %0d twc.len %0d twc.addr %0h a value %0h addr_wr_final %0h awaddr[aw_cnt[int_wr_cntr_width-2:0]] %0h",twc.size,twc.len,twc.addr,a,addr_wr_final ,awaddr[aw_cnt[int_wr_cntr_width-2:0]]); + if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1]; + aw_cnt[int_wr_cntr_width-2:0] = 0; + end + end // if (!aw_fifo_full) + end /// if else + end /// always + /*--------------------------------------------------------------------------------*/ + + + + +// /* Write Data Channel Handshake */ +// always@(negedge S_RESETN or posedge S_ACLK) +// begin +// if(!S_RESETN) begin +// wd_cnt = 0; +// end else begin +// if(!wd_fifo_full && S_WVALID) begin +// slv.monitor.axi_wr_beat_port.get(twd); +// for(i = 0; i < (2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]); i = i+1) begin +// burst_data[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8] = twd.data[i]; +// end +// valid_bytes = valid_bytes+(2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]); +// if (twd.last) begin +// wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1; +// burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]] = valid_bytes; +// valid_bytes = 0; +// wd_cnt = wd_cnt + 1; +// if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin +// wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1]; +// wd_cnt[int_wr_cntr_width-2:0] = 0; +// end +// end +// end /// if +// end /// else +// end /// always + + + /* Write Data Channel Handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wd_cnt = 0; + end else begin + if(!wd_fifo_full && S_WVALID) begin + slv.monitor.axi_wr_beat_port.get(twd); + wait((aw_flag[wd_cnt[int_wr_cntr_width-2:0]] === 'b1)); + case(size_local) + 0 : add_val = 1; + 1 : add_val = 2; + 2 : add_val = 4; + 3 : add_val = 8; + 4 : add_val = 16; + 5 : add_val = 32; + 6 : add_val = 64; + 7 : add_val = 128; + endcase + + // $display(" size_local %0d add_val %0d wd_cnt %0d",size_local,add_val,wd_cnt); +// $display(" data depth : %0d size %0d srrb %0d last %0d burst %0d ",2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]],twd.get_data_size(),twd.get_strb_size(),twd.last,twc.burst); + //$display(" a value is %0d ",a); + // twd.sprint_c(); + for(i = 0; i < (2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]); i = i+1) begin + burst_data[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8] = twd.data[i+a]; + //$display("data burst %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h i %0d a %0d full data %0h",burst_data[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8],twd.data[i],twd.data[i+1],twd.data[i+2],twd.data[i+3],twd.data[i+4],twd.data[i+5],twd.data[i+a],i,a,twd.data[i+a]); + //$display(" wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8) %0d wd_cnt %0d valid_bytes %0d int_wr_cntr_width %0d", wd_cnt[int_wr_cntr_width-2:0],wd_cnt,valid_bytes,int_wr_cntr_width); + burst_strb[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes)+(i*1))+:1] = twd.strb[i+a]; + //$display("burst_strb %0h twd_strb %0h int_wr_cntr_width %0d valid_bytes %0d wd_cnt[int_wr_cntr_width-2:0] %0d twd.strb[i+a] %0b full strb %0h",burst_strb[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes)+(i*1))+:1],twd.strb[i],int_wr_cntr_width,valid_bytes,wd_cnt[int_wr_cntr_width-2:0],twd.strb[i+a],twd.strb[i+a]); + //$display("burst_strb %0h twd.strb[i+1] %0h twd.strb[i+2] %0h twd.strb[i+3] %0h twd.strb[i+4] %0h twd.strb[i+5] %0h twd.strb[i+6] %0h twd.strb[i+7] %0h",twd.strb[i],twd.strb[i+1],twd.strb[i+1],twd.strb[i+2],twd.strb[i+3],twd.strb[i+4],twd.strb[i+5],twd.strb[i+6],twd.strb[i+7]); + + if(i == ((2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]])-1) ) begin + if(burst_local == AXI_FIXED) begin + a = a; + end else if(burst_local == AXI_INCR) begin + a = a+add_val; + end else if(burst_local == AXI_WRAP) begin + a_new = (a_16_bits/num_bytes)*num_bytes; + a_wrap = a_new + (num_bytes); + a = a+add_val; + a_cnt = a_cnt+1; + a_16_bits = a_16_bits+add_val; + a_wrt_val = a_16_bits; + //$display(" new a value for wrap a %0h add_val %0d a_wrap %0h a_wrt_val %0h a_new %0h num_bytes %0h a_cnt %0d ",a,add_val,a_wrap[3:0],a_wrt_val,a_new,num_bytes,a_cnt); + if(a_wrt_val[15:0] >= a_wrap[15:0]) begin + if(data_bus_width === 'd128) + a = a_new[3:0]; + else if(data_bus_width === 'd64) + a = a_new[2:0]; + else if(data_bus_width === 'd32) + a = a_new[1:0]; + //$display(" setting up a_wrap %0h a_new %0h a %0h", a_wrap,a_new,a); + end else begin + a = a; + //$display(" setting incr a_wrap %0h a_new %0h a %0h", a_wrap,a_new ,a ); + end + end + //$display(" new a value a %0h add_val %0d",a,add_val); + end + end + if(burst_local == AXI_INCR) begin + if( a >= (data_bus_width/8) || (burst_local == 0 ) || (twd.last) ) begin + // if( (burst_local == 0 ) || (twd.last) ) begin + a = 0; + //$display("resetting a = %0d ",a); + end + end else if (burst_local == AXI_WRAP) begin + if( ((a >= (data_bus_width/8)) ) || (burst_local == 0 ) || (twd.last) ) begin + a = 0; + //$display("resetting a = %0d ",a); + end + end + + valid_bytes = valid_bytes+(2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]); + //$display("valid bytes in valid_bytes %0d",valid_bytes); + + if (twd.last === 'b1) begin + wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1; + burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]] = valid_bytes; + valid_bytes = 0; + wd_cnt = wd_cnt + 1; + a = 0; + a_cnt = 0; + // $display(" before match max_wr_outstanding_transactions reached %0d wd_cnt %0d",max_wr_outstanding_transactions,wd_cnt); + if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1]; + wd_cnt[int_wr_cntr_width-2:0] = 0; + // $display(" Now max_wr_outstanding_transactions reached %0d ",max_wr_outstanding_transactions); + end + end + end /// if + end /// else + end /// always + + /* Align the wrap data for write transaction */ + task automatic get_wrap_aligned_wr_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data << 8; + temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; + wrp_data = wrp_data << 8; + wrp_bytes = wrp_bytes - 1; + end + wrp_bytes = addr - start_addr; + wrp_data = b_data << (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + /*--------------------------------------------------------------------------------*/ + /* Align the wrap strb for write transaction */ + task automatic get_wrap_aligned_wr_strb; + output [((data_bus_width/8)*axi_burst_len)-1:0] aligned_strb; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [((data_bus_width/8)*axi_burst_len)-1:0] b_strb; + input [max_burst_bytes_width:0] v_bytes; + reg [((data_bus_width/8)*axi_burst_len)-1:0] temp_strb, wrp_strb; + integer wrp_bytes; + integer i; + begin + // $display("addr %0h,b_strb %0h v_bytes %0h",addr,b_strb,v_bytes); + start_addr = (addr/v_bytes) * v_bytes; + // $display("wrap strb start_addr %0h",start_addr); + wrp_bytes = addr - start_addr; + // $display("wrap strb wrp_bytes %0h",wrp_bytes); + wrp_strb = b_strb; + temp_strb = 0; + // $display("wrap strb wrp_strb %0h before shift value1 %0h value2 %0h",wrp_strb,((data_bus_width/8)*axi_burst_len) ,(v_bytes*4)); + // $display("wrap strb wrp_strb %0h before shift value1 %0h value2 %0h",wrp_strb,((data_bus_width/8)*axi_burst_len) ,(v_bytes*4)); + wrp_strb = wrp_strb << (((data_bus_width/8)*axi_burst_len) - (v_bytes)); + // $display("wrap wrp_strb %0h after shift value1 %0h value2 %0h",wrp_strb,((data_bus_width/8)*axi_burst_len) ,(v_bytes*4)); + while(wrp_bytes > 0) begin /// get the strb that is wrapped + temp_strb = temp_strb << 1; + temp_strb[0] = wrp_strb[((data_bus_width/8)*axi_burst_len) : ((data_bus_width/8)*axi_burst_len)-1]; + wrp_strb = wrp_strb << 1; + wrp_bytes = wrp_bytes - 1; + // $display("wrap strb wrp_strb %0h wrp_bytes %0h temp_strb %0h",wrp_strb,wrp_bytes,temp_strb); + end + wrp_bytes = addr - start_addr; + wrp_strb = b_strb << (wrp_bytes); + + aligned_strb = (temp_strb | wrp_strb); + // $display("wrap strb aligned_strb %0h tmep_strb %0h wrp_strb %0h",aligned_strb,temp_strb,wrp_strb); + end + endtask + /*--------------------------------------------------------------------------------*/ + + + /* Calculate the Response for each read/write transaction */ + function [axi_rsp_width-1:0] calculate_resp; + input rd_wr; // indicates Read(1) or Write(0) transaction + input [addr_width-1:0] awaddr; + input [axi_prot_width-1:0] awprot; + reg [axi_rsp_width-1:0] rsp; + begin + rsp = AXI_OK; + /* Address Decode */ + if(decode_address(awaddr) === INVALID_MEM_TYPE) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr); + end + if(!rd_wr && decode_address(awaddr) === REG_MEM) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr); + end + if(secure_access_enabled && awprot[1]) + rsp = AXI_DEC_ERR; // decode error + calculate_resp = rsp; + end + endfunction + /*--------------------------------------------------------------------------------*/ + + + /* Store the Write response for each write transaction */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wr_bresp_cnt = 0; + wr_fifo_wr_ptr = 0; + end else begin + if((wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] === 'b1) && (aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] === 'b1)) begin + // enable_write_bresp <= aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + //#0 enable_write_bresp = 'b1; + enable_write_bresp = 'b1; + // $display("%t enable_write_bresp %0d wr_bresp_cnt %0d",$time ,enable_write_bresp,wr_bresp_cnt[int_wr_cntr_width-2:0]); + end + // enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + /* calculate bresp only when AWVALID && WLAST is received */ + if(enable_write_bresp) begin + aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + // $display("awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] %0h ",awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]]); + bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]); + fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp}; + /* Fill WR data FIFO */ + if(bresp === AXI_OK) begin + if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data + get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address + get_wrap_aligned_wr_strb(aligned_wr_strb,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_strb[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address + end else begin + aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ; + aligned_wr_strb = burst_strb[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + //$display(" got form fifo aligned_wr_addr %0h wr_bresp_cnt[int_wr_cntr_width-2:0]] %0d",aligned_wr_addr,wr_bresp_cnt[int_wr_cntr_width-2:0]); + //$display(" got form fifo aligned_wr_strb %0h wr_bresp_cnt[int_wr_cntr_width-2:0]] %0d",aligned_wr_strb,wr_bresp_cnt[int_wr_cntr_width-2:0]); + end + valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + end else + valid_data_bytes = 0; + + if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] != AXI_WRAP) begin + // wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {burst_strb[wr_bresp_cnt[int_wr_cntr_width-2:0]],awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {aligned_wr_strb,awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + end else begin + wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {aligned_wr_strb,awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + end + wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; + wr_bresp_cnt = wr_bresp_cnt+1; + enable_write_bresp = 'b0; + if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1]; + wr_bresp_cnt[int_wr_cntr_width-2:0] = 0; + end + end + end // else + end // always + /*--------------------------------------------------------------------------------*/ + + + // /* Store the Write response for each write transaction */ + // always@(negedge S_RESETN or posedge S_ACLK) + // begin + // if(!S_RESETN) begin + // wr_bresp_cnt = 0; + // wr_fifo_wr_ptr = 0; + // end else begin + // enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + // /* calculate bresp only when AWVALID && WLAST is received */ + // if(enable_write_bresp) begin + // aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + // wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + // + // bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]); + // fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp}; + // /* Fill WR data FIFO */ + // if(bresp === AXI_OK) begin + // if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data + // get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address + // end else begin + // aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + // aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ; + // end + // valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + // end else + // valid_data_bytes = 0; + + // wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + // wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; + // wr_bresp_cnt = wr_bresp_cnt+1; + // if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + // wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1]; + // wr_bresp_cnt[int_wr_cntr_width-2:0] = 0; + // end + // end + // end // else + // end // always + // /*--------------------------------------------------------------------------------*/ + + /* Send Write Response Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + rd_bresp_cnt = 0; + wr_latency_count = get_wr_lat_number(1); + wr_delayed = 0; + bresp_time_cnt = 0; + end else begin + // if(static_count < 32 ) begin + // // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); + // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); + // //wready_gen.set_low_time(0); + // //wready_gen.set_high_time(1); + // slv.wr_driver.send_wready(wready_gen); + // end + if(awvalid_flag[bresp_time_cnt] && (($realtime - awvalid_receive_time[bresp_time_cnt])/diff_time >= wr_latency_count)) + wr_delayed = 1; + if(!bresp_fifo_empty && wr_delayed) begin + slv.wr_driver.get_wr_reactive(twr); + twr.set_id(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb]); + case(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb]) + 2'b00: twr.set_bresp(XIL_AXI_RESP_OKAY); + 2'b01: twr.set_bresp(XIL_AXI_RESP_EXOKAY); + 2'b10: twr.set_bresp(XIL_AXI_RESP_SLVERR); + 2'b11: twr.set_bresp(XIL_AXI_RESP_DECERR); + endcase + + // if(static_count > 32 ) begin + // // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); + // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); + // // wready_gen.set_low_time(3); + // // wready_gen.set_high_time(3); + // // wready_gen.set_low_time_range(3,6); + // // wready_gen.set_high_time_range(3,6); + // slv.wr_driver.send_wready(wready_gen); + // end + wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); + slv.wr_driver.send_wready(wready_gen); + slv.wr_driver.send(twr); + wr_delayed = 0; + awvalid_flag[bresp_time_cnt] = 1'b0; + bresp_time_cnt = bresp_time_cnt+1; + rd_bresp_cnt = rd_bresp_cnt + 1; + if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1]; + rd_bresp_cnt[int_wr_cntr_width-2:0] = 0; + end + if(bresp_time_cnt === max_wr_outstanding_transactions) begin + bresp_time_cnt = 0; + end + wr_latency_count = get_wr_lat_number(1); + static_count++; + end + static_count++; + end // else + end//always + /*--------------------------------------------------------------------------------*/ + +// /* Send Write Response Channel handshake */ +// always@(negedge S_RESETN or posedge S_ACLK) +// begin +// if(!S_RESETN) begin +// rd_bresp_cnt = 0; +// wr_latency_count = get_wr_lat_number(1); +// wr_delayed = 0; +// bresp_time_cnt = 0; +// end else begin +// if(static_count < 32 ) begin +// wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); +// wready_gen.set_low_time(0); +// wready_gen.set_high_time(1); +// slv.wr_driver.send_wready(wready_gen); +// end +// if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count)) +// wr_delayed = 1; +// if(!bresp_fifo_empty && wr_delayed) begin +// slv.wr_driver.get_wr_reactive(twr); +// twr.set_id(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb]); +// case(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb]) +// 2'b00: twr.set_bresp(XIL_AXI_RESP_OKAY); +// 2'b01: twr.set_bresp(XIL_AXI_RESP_EXOKAY); +// 2'b10: twr.set_bresp(XIL_AXI_RESP_SLVERR); +// 2'b11: twr.set_bresp(XIL_AXI_RESP_DECERR); +// endcase +// if(static_count > 32) begin +// wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); +// wready_gen.set_low_time(3); +// wready_gen.set_high_time(3); +// wready_gen.set_low_time_range(3,6); +// wready_gen.set_high_time_range(3,6); +// slv.wr_driver.send_wready(wready_gen); +// end +// // wr_delayed = 1'b0; +// slv.wr_driver.send(twr); +// wr_delayed = 0; +// awvalid_flag[bresp_time_cnt] = 1'b0; +// bresp_time_cnt = bresp_time_cnt+1; +// rd_bresp_cnt = rd_bresp_cnt + 1; +// if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin +// rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1]; +// rd_bresp_cnt[int_wr_cntr_width-2:0] = 0; +// end +// if(bresp_time_cnt === max_wr_outstanding_transactions) begin +// bresp_time_cnt = 0; +// end +// wr_latency_count = get_wr_lat_number(1); +// static_count++; +// end +// static_count++; +// end // else +//end + /*--------------------------------------------------------------------------------*/ + + /* Reading from the wr_fifo */ + always@(negedge S_RESETN or posedge SW_CLK) begin + if(!S_RESETN) begin + WR_DATA_VALID_DDR = 1'b0; + WR_DATA_VALID_OCM = 1'b0; + wr_fifo_rd_ptr = 0; + state = SEND_DATA; + WR_QOS = 0; + end else begin + case(state) + SEND_DATA :begin + state = SEND_DATA; + WR_DATA_VALID_OCM = 0; + WR_DATA_VALID_DDR = 0; + if(!wr_fifo_empty) begin + WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb]; + WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]; + WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; + WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb]; + WR_DATA_STRB = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_strb_msb : wr_strb_lsb]; + state = WAIT_ACK; + case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb])) + OCM_MEM : WR_DATA_VALID_OCM = 1; + DDR_MEM : WR_DATA_VALID_DDR = 1; + default : state = SEND_DATA; + endcase + wr_fifo_rd_ptr = wr_fifo_rd_ptr+1; + end + end + WAIT_ACK :begin + state = WAIT_ACK; + if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + state = SEND_DATA; + end + end + endcase + end + end + /*--------------------------------------------------------------------------------*/ +/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ + +/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ + + /* READ CHANNELS */ + /* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ + reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0; + real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received + reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received + reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1]; + reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1]; + reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1]; + reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1]; + reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1]; + reg ar_flag [0:max_rd_outstanding_transactions-1]; + reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1]; + reg [addr_width-1:0] addr_local; + reg [addr_width-1:0] addr_final; + reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1]; + reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1]; + wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) + + reg [int_rd_cntr_width-1:0] rd_cnt = 0; + reg [int_rd_cntr_width-1:0] trr_rd_cnt = 0; + reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0; + reg [axi_rsp_width-1:0] rresp; + reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response + + /* Send Read Response & Data Channel handshake */ + integer rd_latency_count; + reg rd_delayed; + reg read_fifo_empty; + + + reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data .. + reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; + wire read_fifo_full; + + assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0; + assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0; + assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0; + + /* Store the arvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) + ar_time_cnt = 0; + else begin + if(net_ARVALID == 'b1 && S_ARREADY == 'b1) begin + arvalid_receive_time[ar_time_cnt] = $time; + arvalid_flag[ar_time_cnt] = 1'b1; + ar_time_cnt = ar_time_cnt + 1; + if((ar_time_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) ) + ar_time_cnt[int_rd_cntr_width-1:0] = 0; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_ARVALID == 'b1 && S_ARREADY == 'b1) begin + if(S_ARQOS === 0) begin + arqos[ar_cnt[int_rd_cntr_width-2:0]] = ar_qos; + end else begin + arqos[ar_cnt[int_rd_cntr_width-2:0]] = S_ARQOS; + end + end + end + /*--------------------------------------------------------------------------------*/ + + always@(ar_fifo_full) + begin + if(ar_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions); + end + /*--------------------------------------------------------------------------------*/ + + /* Address Read Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + ar_cnt = 0; + end else begin + if(!ar_fifo_full) begin + slv.monitor.axi_rd_cmd_port.get(trc); + // araddr[ar_cnt[int_rd_cntr_width-2:0]] = trc.addr; + arlen[ar_cnt[int_rd_cntr_width-2:0]] = trc.len; + arsize[ar_cnt[int_rd_cntr_width-2:0]] = trc.size; + arbrst[ar_cnt[int_rd_cntr_width-2:0]] = trc.burst; + arlock[ar_cnt[int_rd_cntr_width-2:0]] = trc.lock; + arcache[ar_cnt[int_rd_cntr_width-2:0]]= trc.cache; + arprot[ar_cnt[int_rd_cntr_width-2:0]] = trc.prot; + arid[ar_cnt[int_rd_cntr_width-2:0]] = trc.id; + ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1'b1; + size_local = trc.size; + addr_local = trc.addr; + case(size_local) + 0 : addr_final = {addr_local}; + 1 : addr_final = {addr_local[31:1],1'b0}; + 2 : addr_final = {addr_local[31:2],2'b0}; + 3 : addr_final = {addr_local[31:3],3'b0}; + 4 : addr_final = {addr_local[31:4],4'b0}; + 5 : addr_final = {addr_local[31:5],5'b0}; + 6 : addr_final = {addr_local[31:6],6'b0}; + 7 : addr_final = {addr_local[31:7],7'b0}; + endcase + araddr[ar_cnt[int_rd_cntr_width-2:0]] = addr_final; + ar_cnt = ar_cnt+1; + // $display(" %m before resetting ar_cnt %0d max_rd_outstanding_transactions %0d",ar_cnt,max_rd_outstanding_transactions-1); + if(ar_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) begin + // ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1]; + ar_cnt[int_rd_cntr_width-1:0] = 0; + // $display(" %m resetting ar_cnt %0d",ar_cnt); + end + end /// if(!ar_fifo_full) + end /// if else + end /// always*/ + /*--------------------------------------------------------------------------------*/ + + /* Align Wrap data for read transaction*/ + task automatic get_wrap_aligned_rd_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [addr_width-1:0] start_addr; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data >> 8; + temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; + wrp_data = wrp_data >> 8; + wrp_bytes = wrp_bytes - 1; + end + temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); + wrp_bytes = addr - start_addr; + wrp_data = b_data >> (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1; + reg [addr_width-1:0] temp_read_address; + reg [max_burst_bytes_width:0] temp_rd_valid_bytes; + reg rd_fifo_state; + reg invalid_rd_req; + /* get the data from memory && also calculate the rresp*/ + always@(negedge S_RESETN or posedge SW_CLK) + begin + if(!S_RESETN)begin + rd_fifo_wr_ptr = 0; + wr_rresp_cnt =0; + rd_fifo_state = RD_DATA_REQ; + temp_rd_valid_bytes = 0; + temp_read_address = 0; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + invalid_rd_req = 0; + end else begin + case(rd_fifo_state) + RD_DATA_REQ : begin + rd_fifo_state = RD_DATA_REQ; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin + ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0; + rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]); + fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp}; + temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8; + + if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin + temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; + else + temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + if(rresp === AXI_OK) begin + case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]); + OCM_MEM : RD_REQ_OCM = 1; + DDR_MEM : RD_REQ_DDR = 1; + REG_MEM : RD_REQ_REG = 1; + default : invalid_rd_req = 1; + endcase + end else + invalid_rd_req = 1; + + RD_QOS = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + RD_BYTES = temp_rd_valid_bytes; + rd_fifo_state = WAIT_RD_VALID; + wr_rresp_cnt = wr_rresp_cnt + 1; + if(wr_rresp_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) begin + // wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1]; + wr_rresp_cnt[int_rd_cntr_width-1:0] = 0; + end + end + end + WAIT_RD_VALID : begin + rd_fifo_state = WAIT_RD_VALID; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin + if(RD_DATA_VALID_DDR) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR; + else if(RD_DATA_VALID_OCM) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM; + else if(RD_DATA_VALID_REG) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG; + else + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0; + rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + invalid_rd_req = 0; + rd_fifo_state = RD_DATA_REQ; + end + end + endcase + end /// else + end /// always + + /*--------------------------------------------------------------------------------*/ + reg[max_burst_bytes_width:0] rd_v_b; + reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data; + reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data; + reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; + + xil_axi_data_beat new_data; + + /* Read Data Channel handshake */ + //always@(negedge S_RESETN or posedge S_ACLK) + initial begin + forever begin + if(!S_RESETN)begin + // rd_fifo_rd_ptr = 0; + trr_rd_cnt = 0; + // rd_latency_count = get_rd_lat_number(1); + // rd_delayed = 0; + // rresp_time_cnt = 0; + // rd_v_b = 0; + end else begin + //if(net_ARVALID && S_ARREADY) + // trr_rd[trr_rd_cnt] = new("trr_rd[trr_rd_cnt]"); + // trr_rd[trr_rd_cnt] = new($psprintf("trr_rd[%0d]",trr_rd_cnt)); + slv.rd_driver.get_rd_reactive(trr); + trr_rd.push_back(trr.my_clone()); + //$cast(trr_rd[trr_rd_cnt],trr.copy()); + // rd_latency_count = get_rd_lat_number(1); + // $display("%m waiting for next transfer trr_rd_cnt %0d trr.size %0d " ,trr_rd_cnt,trr.size); + // $display("%m waiting for next transfer trr_rd_cnt %0d trr_rd[trr_rd_cnt] %0d" ,trr_rd_cnt,trr_rd[trr_rd_cnt].size); + trr_rd_cnt++; + @(posedge S_ACLK); + end + end // forever + end // initial + + + initial begin + forever begin + if(!S_RESETN)begin + rd_fifo_rd_ptr = 0; + rd_cnt = 0; + rd_latency_count = get_rd_lat_number(1); + rd_delayed = 0; + rresp_time_cnt = 0; + rd_v_b = 0; + end else begin + //if(net_ARVALID && S_ARREADY) + // slv.rd_driver.get_rd_reactive(trr_rd[rresp_time_cnt]); + wait(arvalid_flag[rresp_time_cnt] == 1); + // while(trr_rd[rresp_time_cnttrr_rd_cnt] == null) begin + // @(posedge S_ACLK); + // end + rd_latency_count = get_rd_lat_number(1); + // $display("%m waiting for element form vip rresp_time_cnt %0d ",rresp_time_cnt); + // while(trr_rd.size()< 0 ) begin + // $display("%m got the element form vip rresp_time_cnt %0d ",rresp_time_cnt); + // @(posedge S_ACLK); + // end + // $display("%m got the element form vip rresp_time_cnt %0d ",rresp_time_cnt); + wait(trr_rd.size() > 0); + trr_get_rd = trr_rd.pop_front(); + // $display("%m waiting for next transfer trr_rd_cnt %0d trr_get_rd %0d" ,trr_rd_cnt,trr_get_rd.size); + while ((arvalid_flag[rresp_time_cnt] == 'b1 )&& ((($realtime - arvalid_receive_time[rresp_time_cnt])/diff_time) < rd_latency_count)) begin + @(posedge S_ACLK); + end + + //if(arvalid_flag[rresp_time_cnt] && ((($realtime - arvalid_receive_time[rresp_time_cnt])/diff_time) >= rd_latency_count)) + rd_delayed = 1; + if(!read_fifo_empty && rd_delayed)begin + rd_delayed = 0; + arvalid_flag[rresp_time_cnt] = 1'b0; + rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]])); + temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]]; + rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; + + if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin + get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b); + temp_read_data = temp_wrap_data; + end + temp_read_rsp = 0; + repeat(axi_burst_len) begin + temp_read_rsp = temp_read_rsp >> axi_rsp_width; + temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb]; + end + case (arsize[rd_cnt[int_rd_cntr_width-2:0]]) + 3'b000: trr_get_rd.size = XIL_AXI_SIZE_1BYTE; + 3'b001: trr_get_rd.size = XIL_AXI_SIZE_2BYTE; + 3'b010: trr_get_rd.size = XIL_AXI_SIZE_4BYTE; + 3'b011: trr_get_rd.size = XIL_AXI_SIZE_8BYTE; + 3'b100: trr_get_rd.size = XIL_AXI_SIZE_16BYTE; + 3'b101: trr_get_rd.size = XIL_AXI_SIZE_32BYTE; + 3'b110: trr_get_rd.size = XIL_AXI_SIZE_64BYTE; + 3'b111: trr_get_rd.size = XIL_AXI_SIZE_128BYTE; + endcase + trr_get_rd.len = arlen[rd_cnt[int_rd_cntr_width-2:0]]; + trr_get_rd.id = (arid[rd_cnt[int_rd_cntr_width-2:0]]); +// trr_get_rd.data = new[((2**arsize[rd_cnt[int_rd_cntr_width-2:0]])*(arlen[rd_cnt[int_rd_cntr_width-2:0]]+1))]; + trr_get_rd.rresp = new[((2**arsize[rd_cnt[int_rd_cntr_width-2:0]])*(arlen[rd_cnt[int_rd_cntr_width-2:0]]+1))]; + for(j = 0; j < (arlen[rd_cnt[int_rd_cntr_width-2:0]]+1); j = j+1) begin + for(k = 0; k < (2**arsize[rd_cnt[int_rd_cntr_width-2:0]]); k = k+1) begin + new_data[(k*8)+:8] = temp_read_data[7:0]; + temp_read_data = temp_read_data >> 8; + end + trr_get_rd.set_data_beat(j, new_data); + case(temp_read_rsp[(j*2)+:2]) + 2'b00: trr_get_rd.rresp[j] = XIL_AXI_RESP_OKAY; + 2'b01: trr_get_rd.rresp[j] = XIL_AXI_RESP_EXOKAY; + 2'b10: trr_get_rd.rresp[j] = XIL_AXI_RESP_SLVERR; + 2'b11: trr_get_rd.rresp[j] = XIL_AXI_RESP_DECERR; + endcase + end + slv.rd_driver.send(trr_get_rd); + rd_cnt = rd_cnt + 1; + rresp_time_cnt = rresp_time_cnt+1; + // $display("current rresp_time_cnt %0d rd_cnt %0d",rresp_time_cnt,rd_cnt); + if(rresp_time_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) begin + rresp_time_cnt[int_rd_cntr_width-1:0] = 0; + end + if(rd_cnt[int_rd_cntr_width-1:0] === (max_rd_outstanding_transactions)) begin + // rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1]; + rd_cnt[int_rd_cntr_width-1:0] = 0; + end + rd_latency_count = get_rd_lat_number(1); + end + end /// else + end /// always +end + // /* Read Data Channel handshake */ + // always@(negedge S_RESETN or posedge S_ACLK) + // begin + // if(!S_RESETN)begin + // rd_fifo_rd_ptr = 0; + // rd_cnt = 0; + // rd_latency_count = get_rd_lat_number(1); + // rd_delayed = 0; + // rresp_time_cnt = 0; + // rd_v_b = 0; + // end else begin + // if(net_ARVALID && S_ARREADY) + // slv.rd_driver.get_rd_reactive(trr); + // if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) + // rd_delayed = 1; + // if(!read_fifo_empty && rd_delayed)begin + // rd_delayed = 0; + // arvalid_flag[rresp_time_cnt] = 1'b0; + // rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]])); + // temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]]; + // rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; + + // if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin + // get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b); + // temp_read_data = temp_wrap_data; + // end + // temp_read_rsp = 0; + // repeat(axi_burst_len) begin + // temp_read_rsp = temp_read_rsp >> axi_rsp_width; + // temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb]; + // end + // case (arsize[rd_cnt[int_rd_cntr_width-2:0]]) + // 3'b000: trr.size = XIL_AXI_SIZE_1BYTE; + // 3'b001: trr.size = XIL_AXI_SIZE_2BYTE; + // 3'b010: trr.size = XIL_AXI_SIZE_4BYTE; + // 3'b011: trr.size = XIL_AXI_SIZE_8BYTE; + // 3'b100: trr.size = XIL_AXI_SIZE_16BYTE; + // 3'b101: trr.size = XIL_AXI_SIZE_32BYTE; + // 3'b110: trr.size = XIL_AXI_SIZE_64BYTE; + // 3'b111: trr.size = XIL_AXI_SIZE_128BYTE; + // endcase + // trr.len = arlen[rd_cnt[int_rd_cntr_width-2:0]]; + // trr.id = (arid[rd_cnt[int_rd_cntr_width-2:0]]); +/// / trr.data = new[((2**arsize[rd_cnt[int_rd_cntr_width-2:0]])*(arlen[rd_cnt[int_rd_cntr_width-2:0]]+1))]; + // trr.rresp = new[((2**arsize[rd_cnt[int_rd_cntr_width-2:0]])*(arlen[rd_cnt[int_rd_cntr_width-2:0]]+1))]; + // for(j = 0; j < (arlen[rd_cnt[int_rd_cntr_width-2:0]]+1); j = j+1) begin + // for(k = 0; k < (2**arsize[rd_cnt[int_rd_cntr_width-2:0]]); k = k+1) begin + // new_data[(k*8)+:8] = temp_read_data[7:0]; + // temp_read_data = temp_read_data >> 8; + // end + // trr.set_data_beat(j, new_data); + // case(temp_read_rsp[(j*2)+:2]) + // 2'b00: trr.rresp[j] = XIL_AXI_RESP_OKAY; + // 2'b01: trr.rresp[j] = XIL_AXI_RESP_EXOKAY; + // 2'b10: trr.rresp[j] = XIL_AXI_RESP_SLVERR; + // 2'b11: trr.rresp[j] = XIL_AXI_RESP_DECERR; + // endcase + // end + // slv.rd_driver.send(trr); + // rd_cnt = rd_cnt + 1; + // rresp_time_cnt = rresp_time_cnt+1; + // if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt = 0; + // if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin + // rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1]; + // rd_cnt[int_rd_cntr_width-2:0] = 0; + // end + // rd_latency_count = get_rd_lat_number(1); + // end + // end /// else + // end /// always +endmodule + + +/******************************************************************** + * File : processing_system7_vip_v1_0_16_axi_slave_acp.sv + * + * Date : 2012-11 + * + * Description : Model that acts as PS AXI Slave port interface. + * It uses AXI3 Slave BFM + *****************************************************************************/ + `timescale 1ns/1ps + import axi_vip_pkg::*; + +module processing_system7_vip_v1_0_16_axi_slave_acp ( + S_RESETN, + + S_ARREADY, + S_AWREADY, + S_BVALID, + S_RLAST, + S_RVALID, + S_WREADY, + S_BRESP, + S_RRESP, + S_RDATA, + S_BID, + S_RID, + S_ACLK, + S_ARVALID, + S_AWVALID, + S_BREADY, + S_RREADY, + S_WLAST, + S_WVALID, + S_ARBURST, + S_ARLOCK, + S_ARSIZE, + S_AWBURST, + S_AWLOCK, + S_AWSIZE, + S_ARPROT, + S_AWPROT, + S_ARADDR, + S_AWADDR, + S_WDATA, + S_ARCACHE, + S_ARLEN, + S_AWCACHE, + S_AWLEN, + S_WSTRB, + S_ARID, + S_AWID, + S_WID, + + S_AWQOS, + S_ARQOS, + + SW_CLK, + WR_DATA_ACK_OCM, + WR_DATA_ACK_DDR, + WR_ADDR, + WR_DATA, + WR_DATA_STRB, + WR_BYTES, + WR_DATA_VALID_OCM, + WR_DATA_VALID_DDR, + WR_QOS, + + RD_QOS, + RD_REQ_DDR, + RD_REQ_OCM, + RD_REQ_REG, + RD_ADDR, + RD_DATA_OCM, + RD_DATA_DDR, + RD_DATA_REG, + RD_BYTES, + RD_DATA_VALID_OCM, + RD_DATA_VALID_DDR, + RD_DATA_VALID_REG + +); + parameter enable_this_port = 0; + parameter slave_name = "Slave"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter awuser_bus_width = 1; + parameter aruser_bus_width = 1; + parameter ruser_bus_width = 1; + parameter wuser_bus_width = 1; + parameter buser_bus_width = 1; + parameter slave_base_address = 0; + parameter slave_high_address = 4; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + parameter max_wr_outstanding_transactions = 8; + parameter max_rd_outstanding_transactions = 8; + parameter region_bus_width = 4; + + `include "processing_system7_vip_v1_0_16_local_params.v" + // `include "zynq_ultra_ps_e_vip_v1_0_local_params.sv" + + /* Local parameters only for this module */ + /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles. + This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. + 1-bit extra width than the no.of.bits needed to represent the outstanding transactions + Extra bit helps in generating the empty and full flags */ + parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1); + parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1); + + /* RESP data */ + parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1); + parameter wr_bytes_lsb = 0; + parameter wr_bytes_msb = max_burst_bytes_width; + parameter wr_addr_lsb = wr_bytes_msb + 1; + parameter wr_addr_msb = wr_addr_lsb + addr_width-1; + parameter wr_data_lsb = wr_addr_msb + 1; + parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1; + parameter wr_qos_lsb = wr_data_msb + 1; + parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; + parameter wr_strb_lsb = wr_qos_msb + 1; + parameter wr_strb_msb = wr_strb_lsb + ((data_bus_width/8)*axi_burst_len)-1; + + parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; + parameter rsp_lsb = 0; + parameter rsp_msb = axi_rsp_width-1; + parameter rsp_id_lsb = rsp_msb + 1; + parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; + + input S_RESETN; + + output S_ARREADY; + output S_AWREADY; + output S_BVALID; + output S_RLAST; + output S_RVALID; + output S_WREADY; + output [axi_rsp_width-1:0] S_BRESP; + output [axi_rsp_width-1:0] S_RRESP; + output [data_bus_width-1:0] S_RDATA; + output [id_bus_width-1:0] S_BID; + output [id_bus_width-1:0] S_RID; + input S_ACLK; + input S_ARVALID; + input S_AWVALID; + input S_BREADY; + input S_RREADY; + input S_WLAST; + input S_WVALID; + input [axi_brst_type_width-1:0] S_ARBURST; + input [axi_lock_width-1:0] S_ARLOCK; + input [axi_size_width-1:0] S_ARSIZE; + input [axi_brst_type_width-1:0] S_AWBURST; + input [axi_lock_width-1:0] S_AWLOCK; + input [axi_size_width-1:0] S_AWSIZE; + input [axi_prot_width-1:0] S_ARPROT; + input [axi_prot_width-1:0] S_AWPROT; + input [address_bus_width-1:0] S_ARADDR; + input [address_bus_width-1:0] S_AWADDR; + input [data_bus_width-1:0] S_WDATA; + input [axi_cache_width-1:0] S_ARCACHE; + input [axi_len_width-1:0] S_ARLEN; + + input [axi_qos_width-1:0] S_ARQOS; + // input [aruser_bus_width-1:0] S_ARUSER; + // output [ruser_bus_width-1:0] S_RUSER; + // input [region_bus_width-1:0] S_ARREGION; + + input [axi_cache_width-1:0] S_AWCACHE; + input [axi_len_width-1:0] S_AWLEN; + + input [axi_qos_width-1:0] S_AWQOS; + // input [awuser_bus_width-1:0] S_AWUSER; + // input [wuser_bus_width-1:0] S_WUSER; + // output [buser_bus_width-1:0] S_BUSER; + // input [region_bus_width-1:0] S_AWREGION; + + input [(data_bus_width/8)-1:0] S_WSTRB; + input [id_bus_width-1:0] S_ARID; + input [id_bus_width-1:0] S_AWID; + input [id_bus_width-1:0] S_WID; + + + input SW_CLK; + input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; + output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; + output reg [(data_bus_width*axi_burst_len)-1:0] WR_DATA; + output reg [((data_bus_width/8)*axi_burst_len)-1:0] WR_DATA_STRB; + output reg [addr_width-1:0] WR_ADDR; + output reg [max_burst_bytes_width:0] WR_BYTES; + output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG; + output reg [addr_width-1:0] RD_ADDR; + input [(data_bus_width*axi_burst_len)-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG; + output reg[max_burst_bytes_width:0] RD_BYTES; + input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG; + output reg [axi_qos_width-1:0] WR_QOS, RD_QOS; + wire net_ARVALID; + wire net_AWVALID; + wire net_WVALID; + bit [31:0] static_count; + + real s_aclk_period1; + real s_aclk_period2; + real diff_time = 1; + axi_slv_agent#(1,address_bus_width, data_bus_width, data_bus_width, id_bus_width,id_bus_width,0,0,0,0,0,1,1,1,1,0,1,1,1,1,1,1) slv; + + axi_vip_v1_1_14_top #( + .C_AXI_PROTOCOL(1), + .C_AXI_INTERFACE_MODE(2), + .C_AXI_ADDR_WIDTH(address_bus_width), + .C_AXI_WDATA_WIDTH(data_bus_width), + .C_AXI_RDATA_WIDTH(data_bus_width), + .C_AXI_WID_WIDTH(id_bus_width), + .C_AXI_RID_WIDTH(id_bus_width), + .C_AXI_AWUSER_WIDTH(0), + .C_AXI_ARUSER_WIDTH(0), + .C_AXI_WUSER_WIDTH(0), + .C_AXI_RUSER_WIDTH(0), + .C_AXI_BUSER_WIDTH(0), + .C_AXI_SUPPORTS_NARROW(1), + .C_AXI_HAS_BURST(1), + .C_AXI_HAS_LOCK(1), + .C_AXI_HAS_CACHE(1), + .C_AXI_HAS_REGION(0), + .C_AXI_HAS_PROT(1), + .C_AXI_HAS_QOS(1), + .C_AXI_HAS_WSTRB(1), + .C_AXI_HAS_BRESP(1), + .C_AXI_HAS_RRESP(1), + .C_AXI_HAS_ARESETN(1) + ) slave ( + .aclk(S_ACLK), + .aclken(1'B1), + .aresetn(S_RESETN), + .s_axi_awid(S_AWID), + .s_axi_awaddr(S_AWADDR), + .s_axi_awlen(S_AWLEN), + .s_axi_awsize(S_AWSIZE), + .s_axi_awburst(S_AWBURST), + .s_axi_awlock(S_AWLOCK), + .s_axi_awcache(S_AWCACHE), + .s_axi_awprot(S_AWPROT), + .s_axi_awregion(4'B0), + .s_axi_awqos(4'h0), + .s_axi_awuser(1'B0), + .s_axi_awvalid(S_AWVALID), + .s_axi_awready(S_AWREADY), + .s_axi_wid(S_WID), + .s_axi_wdata(S_WDATA), + .s_axi_wstrb(S_WSTRB), + .s_axi_wlast(S_WLAST), + .s_axi_wuser(1'B0), + .s_axi_wvalid(S_WVALID), + .s_axi_wready(S_WREADY), + .s_axi_bid(S_BID), + .s_axi_bresp(S_BRESP), + .s_axi_buser(), + .s_axi_bvalid(S_BVALID), + .s_axi_bready(S_BREADY), + .s_axi_arid(S_ARID), + .s_axi_araddr(S_ARADDR), + .s_axi_arlen(S_ARLEN), + .s_axi_arsize(S_ARSIZE), + .s_axi_arburst(S_ARBURST), + .s_axi_arlock(S_ARLOCK), + .s_axi_arcache(S_ARCACHE), + .s_axi_arprot(S_ARPROT), + .s_axi_arregion(4'B0), + .s_axi_arqos(S_ARQOS), + .s_axi_aruser(1'B0), + .s_axi_arvalid(S_ARVALID), + .s_axi_arready(S_ARREADY), + .s_axi_rid(S_RID), + .s_axi_rdata(S_RDATA), + .s_axi_rresp(S_RRESP), + .s_axi_rlast(S_RLAST), + .s_axi_ruser(), + .s_axi_rvalid(S_RVALID), + .s_axi_rready(S_RREADY), + .m_axi_awid(), + .m_axi_awaddr(), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(), + .m_axi_awready(1'b0), + .m_axi_wid(), + .m_axi_wdata(), + .m_axi_wstrb(), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(), + .m_axi_wready(1'b0), + .m_axi_bid(12'h000), + .m_axi_bresp(2'b00), + .m_axi_buser(1'B0), + .m_axi_bvalid(1'b0), + .m_axi_bready(), + .m_axi_arid(), + .m_axi_araddr(), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(), + .m_axi_arregion(), + .m_axi_arqos(), + .m_axi_aruser(), + .m_axi_arvalid(), + .m_axi_arready(1'b0), + .m_axi_rid(12'h000), + .m_axi_rdata(32'h00000000), + .m_axi_rresp(2'b00), + .m_axi_rlast(1'b0), + .m_axi_ruser(1'B0), + .m_axi_rvalid(1'b0), + .m_axi_rready() + ); + + + xil_axi_cmd_beat twc, trc; + xil_axi_write_beat twd; + xil_axi_read_beat trd; + axi_transaction twr, trr,trr_get_rd; + axi_transaction trr_rd[$]; + axi_ready_gen awready_gen; + axi_ready_gen wready_gen; + axi_ready_gen arready_gen; + integer i,j,k,add_val,size_local,burst_local,len_local,num_bytes; + bit [3:0] a; + bit [15:0] a_16_bits,a_new,a_wrap,a_wrt_val,a_cnt; + + initial begin + slv = new("slv",slave.IF); + twr = new("twr"); + trr = new("trr"); + trr_get_rd = new("trr_get_rd"); + wready_gen = slv.wr_driver.create_ready("wready"); + slv.monitor.axi_wr_cmd_port.set_enabled(); + slv.monitor.axi_wr_beat_port.set_enabled(); + slv.monitor.axi_rd_cmd_port.set_enabled(); + slv.wr_driver.set_transaction_depth(max_wr_outstanding_transactions); + slv.rd_driver.set_transaction_depth(max_rd_outstanding_transactions); + slv.start_slave(); + end + + initial begin + slave.IF.set_enable_xchecks_to_warn(); + repeat(10) @(posedge S_ACLK); + slave.IF.set_enable_xchecks(); + end + + + /* Latency type and Debug/Error Control */ + reg[1:0] latency_type = RANDOM_CASE; + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1'b1; + + /* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */ + reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1]; + reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; + wire wr_fifo_empty; + + /* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/ + // reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0; + reg [int_wr_cntr_width-1:0] aw_time_cnt = 0, bresp_time_cnt = 0; + real awvalid_receive_time[0:max_wr_outstanding_transactions-1]; // store the time when a new awvalid is received + reg awvalid_flag[0:max_wr_outstanding_transactions-1]; // indicates awvalid is received + + /* Address Write Channel handshake*/ + reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1]; + reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1]; + reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1]; + reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1]; + reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1]; + reg aw_flag [0:max_wr_outstanding_transactions-1]; + reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1]; + reg [addr_width-1:0] addr_wr_local; + reg [addr_width-1:0] addr_wr_final; + reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1]; + reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1]; + wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) + + /* internal fifos to store burst write data, ID & strobes*/ + reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1]; + reg [((data_bus_width/8)*axi_burst_len)-1:0] burst_strb [0:max_wr_outstanding_transactions-1]; + reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer + reg [max_burst_bytes_width:0] valid_bytes = 0; /// total valid bytes received in a complete burst transfer + reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received + wire wd_fifo_full; + + /* Write Data Channel and Write Response handshake signals*/ + reg [int_wr_cntr_width-1:0] wd_cnt = 0; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; + reg [((data_bus_width/8)*axi_burst_len)-1:0] aligned_wr_strb; + reg [addr_width-1:0] aligned_wr_addr; + reg [max_burst_bytes_width:0] valid_data_bytes; + reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0; + reg [axi_rsp_width-1:0] bresp; + reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_bresp; + reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0; + integer wr_latency_count; + reg wr_delayed,wr_fifo_full_flag; + wire bresp_fifo_empty; + + /* states for managing read/write to WR_FIFO */ + parameter SEND_DATA = 0, WAIT_ACK = 1; + reg state; + + /* Qos*/ + reg [axi_qos_width-1:0] ar_qos, aw_qos; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); + end + end + +//initial slave.set_disable_reset_value_checks(1); + initial begin + repeat(2) @(posedge S_ACLK); + if(!enable_this_port) begin + end +// slave.RESPONSE_TIMEOUT = 0; + end + /*--------------------------------------------------------------------------------*/ + + /* Set Latency type to be used */ + task set_latency_type; + input[1:0] lat; + begin + if(enable_this_port) + latency_type = lat; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set verbosity to be used */ + task automatic set_verbosity; + input[31:0] verb; + begin + if(enable_this_port) begin + slv.set_verbosity(verb); + end else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. set_verbosity will not be set...",$time, DISP_WARN, slave_name); + end + + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set ARQoS to be used */ + task automatic set_arqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) begin + ar_qos = qos; + end else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name); + end + + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set AWQoS to be used */ + task set_awqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + aw_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + /* get the wr latency number */ + function [31:0] get_wr_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min; + AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg; + WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min); + 2'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg); + default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* get the rd latency number */ + function [31:0] get_rd_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min; + AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg; + WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min); + 2'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg); + default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the Clock cycle time period */ + always@(S_RESETN) + begin + if(S_RESETN) begin + diff_time = 1; + @(posedge S_ACLK); + s_aclk_period1 = $realtime; + @(posedge S_ACLK); + s_aclk_period2 = $realtime; + diff_time = s_aclk_period2 - s_aclk_period1; + end + end + /*--------------------------------------------------------------------------------*/ + + /* Check for any WRITE/READs when this port is disabled */ + always@(S_AWVALID or S_WVALID or S_ARVALID) + begin + if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name); + // $stop; + $finish; + end + end + + /*--------------------------------------------------------------------------------*/ + + + assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0; + assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0; + assign net_WVALID = enable_this_port ? S_WVALID : 1'b0; + + assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0; + // assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this + // assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-1:0] === rd_bresp_cnt[int_wr_cntr_width-1:0]))?1'b1 :1'b0; /// complete this + assign aw_fifo_full = ((aw_cnt[1] !== rd_bresp_cnt[1]) && (aw_cnt[0] === rd_bresp_cnt[0]))?1'b1 :1'b0; /// complete this + assign wd_fifo_full = ((wd_cnt[1] !== rd_bresp_cnt[1]) && (wd_cnt[0] === rd_bresp_cnt[0]))?1'b1 :1'b0; /// complete this + assign bresp_fifo_empty = ((wr_fifo_full_flag == 1'b0) && (wr_bresp_cnt === rd_bresp_cnt))?1'b1:1'b0; + + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) + aw_time_cnt = 0; + else begin + if(net_AWVALID && S_AWREADY) begin + awvalid_receive_time[aw_time_cnt] = $realtime; + awvalid_flag[aw_time_cnt] = 1'b1; + // $display("setting up awredy flag awvalid_receive_time[aw_time_cnt] %0t awvalid_flag[aw_time_cnt] %0d aw_time_cnt %0d",awvalid_receive_time[aw_time_cnt],awvalid_flag[aw_time_cnt],aw_time_cnt); + aw_time_cnt = aw_time_cnt + 1; + if(aw_time_cnt === max_wr_outstanding_transactions) begin + aw_time_cnt = 0; + // $display("reached max count max_wr_outstanding_transactions %0d aw_time_cnt %0d",max_wr_outstanding_transactions,aw_time_cnt); + end + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_AWVALID && S_AWREADY) begin + if(S_AWQOS === 0) begin awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos; + end else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS; + end + end + /*--------------------------------------------------------------------------------*/ + + always@(aw_fifo_full) + begin + if(aw_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions); + end + /*--------------------------------------------------------------------------------*/ + + /* Address Write Channel handshake*/ + // always@(negedge S_RESETN or posedge S_ACLK) + initial begin + forever begin + if(!S_RESETN) begin + aw_cnt = 0; + end else begin + // if(!aw_fifo_full) begin + // $display(" %0t ACP waitting for aw_fifo_full %0d max_wr_outstanding_transactions %0d",$time, aw_fifo_full,max_wr_outstanding_transactions); + wait(aw_fifo_full == 0) begin + // $display("%0t ACP waitting done for aw_fifo_full %0d max_wr_outstanding_transactions %0d ",$time,aw_fifo_full,max_wr_outstanding_transactions); + slv.monitor.axi_wr_cmd_port.get(twc); + // awaddr[aw_cnt[int_wr_cntr_width-2:0]] = twc.addr; + awlen[aw_cnt[int_wr_cntr_width-1:0]] = twc.len; + awsize[aw_cnt[int_wr_cntr_width-1:0]] = twc.size; + awbrst[aw_cnt[int_wr_cntr_width-1:0]] = twc.burst; + awlock[aw_cnt[int_wr_cntr_width-1:0]] = twc.lock; + awcache[aw_cnt[int_wr_cntr_width-1:0]]= twc.cache; + awprot[aw_cnt[int_wr_cntr_width-1:0]] = twc.prot; + awid[aw_cnt[int_wr_cntr_width-1:0]] = twc.id; + aw_flag[aw_cnt[int_wr_cntr_width-1:0]] = 1'b1; + size_local = twc.size; + burst_local = twc.burst; + len_local = twc.len; + if(burst_local == AXI_INCR || burst_local == AXI_FIXED) begin + if(data_bus_width === 'd128) begin + if(size_local === 'd0) a = {twc.addr[3:0]}; + if(size_local === 'd1) a = {twc.addr[3:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[3:2],2'b0}; + if(size_local === 'd3) a = {twc.addr[3],3'b0}; + if(size_local === 'd4) a = 'b0; + end else if(data_bus_width === 'd64 ) begin + if(size_local === 'd0) a = {twc.addr[2:0]}; + if(size_local === 'd1) a = {twc.addr[2:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[2],2'b0}; + if(size_local === 'd3) a = 'b0; + end else if(data_bus_width === 'd32 ) begin + if(size_local === 'd0) a = {twc.addr[1:0]}; + if(size_local === 'd1) a = {twc.addr[1],1'b0}; + if(size_local === 'd2) a = 'b0; + end + end if(burst_local == AXI_WRAP) begin + if(data_bus_width === 'd128) begin + if(size_local === 'd0) a = {twc.addr[3:0]}; + if(size_local === 'd1) a = {twc.addr[3:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[3:2],2'b0}; + if(size_local === 'd3) a = {twc.addr[3],3'b0}; + if(size_local === 'd4) a = 'b0; + end else if(data_bus_width === 'd64 ) begin + if(size_local === 'd0) a = {twc.addr[2:0]}; + if(size_local === 'd1) a = {twc.addr[2:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[2],2'b0}; + if(size_local === 'd3) a = 'b0; + end else if(data_bus_width === 'd32 ) begin + if(size_local === 'd0) a = {twc.addr[1:0]}; + if(size_local === 'd1) a = {twc.addr[1],1'b0}; + if(size_local === 'd2) a = 'b0; + end + // a = twc.addr[3:0]; + a_16_bits = twc.addr[7:0]; + num_bytes = ((len_local+1)*(2**size_local)); + // $display("num_bytes %0d num_bytes %0h",num_bytes,num_bytes); + end + addr_wr_local = twc.addr; + if(burst_local == AXI_INCR || burst_local == AXI_FIXED) begin + case(size_local) + 0 : addr_wr_final = {addr_wr_local}; + 1 : addr_wr_final = {addr_wr_local[31:1],1'b0}; + 2 : addr_wr_final = {addr_wr_local[31:2],2'b0}; + 3 : addr_wr_final = {addr_wr_local[31:3],3'b0}; + 4 : addr_wr_final = {addr_wr_local[31:4],4'b0}; + 5 : addr_wr_final = {addr_wr_local[31:5],5'b0}; + 6 : addr_wr_final = {addr_wr_local[31:6],6'b0}; + 7 : addr_wr_final = {addr_wr_local[31:7],7'b0}; + endcase + awaddr[aw_cnt[int_wr_cntr_width-1:0]] = addr_wr_final; + // $display("addr_wr_final %0h aw_cnt %0d",addr_wr_final,aw_cnt); + end if(burst_local == AXI_WRAP) begin + awaddr[aw_cnt[int_wr_cntr_width-1:0]] = twc.addr; + // $display(" awaddr[aw_cnt[int_wr_cntr_width-2:0]] %0h",awaddr[aw_cnt[int_wr_cntr_width-1:0]]); + end + aw_cnt = aw_cnt + 1; + // $display(" %0t ACP aw_cnt %0d",$time,aw_cnt); + // if(data_bus_width === 'd32) a = 0; + // if(data_bus_width === 'd64) a = twc.addr[2:0]; + // if(data_bus_width === 'd128) a = twc.addr[3:0]; + // $display(" %0t ACP addr_wr_final %0h size %0d len %0d awaddr[aw_cnt[int_wr_cntr_width-2:0]] %0h twc.id %0h",$time,twc.addr,twc.size,twc.len,awaddr[aw_cnt[int_wr_cntr_width-2:0]],twc.id); + #0; + if(aw_cnt[int_wr_cntr_width-1:0] === (max_wr_outstanding_transactions)) begin + // aw_cnt[int_wr_cntr_width] = ~aw_cnt[int_wr_cntr_width]; + aw_cnt[int_wr_cntr_width-1:0] = 0; + // $display("%0t ACP resetting the aw_cnt[int_wr_cntr_width-2:0] %0d max_wr_outstanding_transactions %0d",$time,aw_cnt,max_wr_outstanding_transactions); + end + end // if (!aw_fifo_full) + end /// if else + end /// forever + end /// always + /*--------------------------------------------------------------------------------*/ + + /* Write Data Channel Handshake */ + // always@(negedge S_RESETN or posedge S_ACLK) + initial begin + forever begin + if(!S_RESETN) begin + wd_cnt = 0; + wr_fifo_full_flag = 0; + end else begin + // $display(" ACP before data channel wd_fifo_full %0d S_WVALID %0d",wd_fifo_full,S_WVALID); + // if(!wd_fifo_full && S_WVALID) begin + // wait(wd_fifo_full == 0 && S_WVALID == 1) begin + wait(wd_fifo_full == 0 ) begin + // $display(" ACP after data channel wd_fifo_full %0d S_WVALID %0d",wd_fifo_full,S_WVALID); + slv.monitor.axi_wr_beat_port.get(twd); + // $display(" ACP got the element from monitor data channel wd_fifo_full %0d S_WVALID %0d",wd_fifo_full,S_WVALID); + wait((aw_flag[wd_cnt[int_wr_cntr_width-1:0]] === 'b1)); + case(size_local) + 0 : add_val = 1; + 1 : add_val = 2; + 2 : add_val = 4; + 3 : add_val = 8; + 4 : add_val = 16; + 5 : add_val = 32; + 6 : add_val = 64; + 7 : add_val = 128; + endcase + + // $display(" ACP size_local %0d add_val %0d wd_cnt %0d",size_local,add_val,wd_cnt); +// $display(" data depth : %0d size %0d srrb %0d last %0d burst %0d ",2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]],twd.get_data_size(),twd.get_strb_size(),twd.last,twc.burst); + //$display(" a value is %0d ",a); + // twd.sprint_c(); + for(i = 0; i < (2**awsize[wr_bresp_cnt[int_wr_cntr_width-1:0]]); i = i+1) begin + burst_data[wd_cnt[int_wr_cntr_width-1:0]][((valid_bytes*8)+(i*8))+:8] = twd.data[i+a]; + //$display("data burst %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h i %0d a %0d full data %0h",burst_data[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8],twd.data[i],twd.data[i+1],twd.data[i+2],twd.data[i+3],twd.data[i+4],twd.data[i+5],twd.data[i+a],i,a,twd.data[i+a]); + //$display(" wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8) %0d wd_cnt %0d valid_bytes %0d int_wr_cntr_width %0d", wd_cnt[int_wr_cntr_width-2:0],wd_cnt,valid_bytes,int_wr_cntr_width); + // $display(" ACP full data %0h",twd.data[i+a]); + burst_strb[wd_cnt[int_wr_cntr_width-1:0]][((valid_bytes)+(i*1))+:1] = twd.strb[i+a]; + // $display("ACP burst_strb %0h twd_strb %0h int_wr_cntr_width %0d valid_bytes %0d wd_cnt[int_wr_cntr_width-1:0] %0d twd.strb[i+a] %0b full strb %0h",burst_strb[wd_cnt[int_wr_cntr_width-1:0]][((valid_bytes)+(i*1))+:1],twd.strb[i],int_wr_cntr_width,valid_bytes,wd_cnt[int_wr_cntr_width-1:0],twd.strb[i+a],twd.strb[i+a]); + // $display("ACP burst_strb %0h twd.strb[i+1] %0h twd.strb[i+2] %0h twd.strb[i+3] %0h twd.strb[i+4] %0h twd.strb[i+5] %0h twd.strb[i+6] %0h twd.strb[i+7] %0h",twd.strb[i],twd.strb[i+1],twd.strb[i+1],twd.strb[i+2],twd.strb[i+3],twd.strb[i+4],twd.strb[i+5],twd.strb[i+6],twd.strb[i+7]); + // $display("ACP full strb %0h",twd.strb[i+a]); + + if(i == ((2**awsize[wr_bresp_cnt[int_wr_cntr_width-1:0]])-1) ) begin + if(burst_local == AXI_FIXED) begin + a = a; + end else if(burst_local == AXI_INCR) begin + a = a+add_val; + end else if(burst_local == AXI_WRAP) begin + a_new = (a_16_bits/num_bytes)*num_bytes; + a_wrap = a_new + (num_bytes); + a = a+add_val; + a_cnt = a_cnt+1; + a_16_bits = a_16_bits+add_val; + a_wrt_val = a_16_bits; + // $display(" ACP new a value for wrap a %0h add_val %0d a_wrap %0h a_wrt_val %0h a_new %0h num_bytes %0h a_cnt %0d ",a,add_val,a_wrap[3:0],a_wrt_val,a_new,num_bytes,a_cnt); + if(a_wrt_val[15:0] >= a_wrap[15:0]) begin + if(data_bus_width === 'd128) + a = a_new[3:0]; + else if(data_bus_width === 'd64) + a = a_new[2:0]; + else if(data_bus_width === 'd32) + a = a_new[1:0]; + //$display(" setting up a_wrap %0h a_new %0h a %0h", a_wrap,a_new,a); + end else begin + a = a; + // $display(" ACP setting incr a_wrap %0h a_new %0h a %0h", a_wrap,a_new ,a ); + end + end + // $display(" ACP new a value a %0h add_val %0d",a,add_val); + end + end + if(burst_local == AXI_INCR) begin + if( a >= (data_bus_width/8) || (burst_local == 0 ) || (twd.last) ) begin + // if( (burst_local == 0 ) || (twd.last) ) begin + a = 0; + //$display("resetting a = %0d ",a); + end + end else if (burst_local == AXI_WRAP) begin + if( ((a >= (data_bus_width/8)) ) || (burst_local == 0 ) || (twd.last) ) begin + a = 0; + //$display("resetting a = %0d ",a); + end + end + + valid_bytes = valid_bytes+(2**awsize[wr_bresp_cnt[int_wr_cntr_width-1:0]]); + $display("ACP valid bytes in valid_bytes %0d",valid_bytes); + + if (twd.last === 'b1) begin + wlast_flag[wd_cnt[int_wr_cntr_width-1:0]] = 1'b1; + burst_valid_bytes[wd_cnt[int_wr_cntr_width-1:0]] = valid_bytes; + valid_bytes = 0; + wd_cnt = wd_cnt + 1; + a = 0; + a_cnt = 0; + // $display(" %0t ACP before match max_wr_outstanding_transactions reached %0d wd_cnt %0d int_wr_cntr_width %0d ",$time,max_wr_outstanding_transactions,wd_cnt,int_wr_cntr_width); + if(wd_cnt[int_wr_cntr_width-1:0] === (max_wr_outstanding_transactions)) begin + // wd_cnt[int_wr_cntr_width] = ~wd_cnt[int_wr_cntr_width]; + wd_cnt[int_wr_cntr_width-1:0] = 0; + // $display(" ACP resetting the wd_cnt %0d Now max_wr_outstanding_transactions reached %0d ",wd_cnt,max_wr_outstanding_transactions); + end + end + end /// if + end /// else + end /// forever + end /// always + +// /* Write Data Channel Handshake */ +// always@(negedge S_RESETN or posedge S_ACLK) +// begin +// if(!S_RESETN) begin +// wd_cnt = 0; +// end else begin +// if(!wd_fifo_full && S_WVALID) begin +// slv.monitor.axi_wr_beat_port.get(twd); +// // twd.do_print(); +// $display(" data depth : %0d size %0d ",2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]],twd.get_data_size()); +// for(i = 0; i < (2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]); i = i+1) begin +// for(int j = 0; j < 2 ; j = j+1) begin +// burst_data[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8] = twd.data[(i*2)+j]; +// $display("data burst %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h i %0d j %0d",burst_data[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8],twd.data[i],twd.data[i+1],twd.data[i+2],twd.data[i+3],twd.data[i+4],twd.data[i+5],i,j); +// // burst_strb[wd_cnt[wd_cnt[int_wr_cntr_width-2:0]]][((valid_bytes*8)+(i*8))+:8/8)] = twd.strb[i]; +// $display("burst_strb %0h",twd.strb[i]); +// end +// end +// valid_bytes = valid_bytes+(2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]); +// if (twd.last) begin +// wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1; +// burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]] = valid_bytes; +// valid_bytes = 0; +// wd_cnt = wd_cnt + 1; +// if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin +// wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1]; +// wd_cnt[int_wr_cntr_width-2:0] = 0; +// end +// end +// end /// if +// end /// else +// end /// always + + /* Align the wrap data for write transaction */ + task automatic get_wrap_aligned_wr_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + // $display("addr %0h,b_data %0h v_bytes %0h",addr,b_data,v_bytes); + start_addr = (addr/v_bytes) * v_bytes; + // $display("wrap start_addr %0h",start_addr); + wrp_bytes = addr - start_addr; + // $display("wrap wrp_bytes %0h",wrp_bytes); + wrp_data = b_data; + temp_data = 0; + wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); + // $display("wrap wrp_data %0h",wrp_data); + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data << 8; + temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; + wrp_data = wrp_data << 8; + wrp_bytes = wrp_bytes - 1; + // $display("wrap wrp_data %0h temp_data %0h wrp_bytes %0h ",wrp_data,temp_data[7:0],wrp_bytes); + end + wrp_bytes = addr - start_addr; + wrp_data = b_data << (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + // $display("temp_data %0h wrp_data %0h aligned_data %0h",temp_data,wrp_data,aligned_data); + end + endtask + + /*--------------------------------------------------------------------------------*/ + /* Align the wrap strb for write transaction */ + task automatic get_wrap_aligned_wr_strb; + output [((data_bus_width/8)*axi_burst_len)-1:0] aligned_strb; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [((data_bus_width/8)*axi_burst_len)-1:0] b_strb; + input [max_burst_bytes_width:0] v_bytes; + reg [((data_bus_width/8)*axi_burst_len)-1:0] temp_strb, wrp_strb; + integer wrp_bytes; + integer i; + begin + // $display("addr %0h,b_strb %0h v_bytes %0h",addr,b_strb,v_bytes); + start_addr = (addr/v_bytes) * v_bytes; + // $display("wrap strb start_addr %0h",start_addr); + wrp_bytes = addr - start_addr; + // $display("wrap strb wrp_bytes %0h",wrp_bytes); + wrp_strb = b_strb; + temp_strb = 0; + // $display("wrap strb wrp_strb %0h before shift value1 %0h value2 %0h",wrp_strb,((data_bus_width/8)*axi_burst_len) ,(v_bytes*4)); + // $display("wrap strb wrp_strb %0h before shift value1 %0h value2 %0h",wrp_strb,((data_bus_width/8)*axi_burst_len) ,(v_bytes*4)); + wrp_strb = wrp_strb << (((data_bus_width/8)*axi_burst_len) - (v_bytes)); + // $display("wrap wrp_strb %0h after shift value1 %0h value2 %0h",wrp_strb,((data_bus_width/8)*axi_burst_len) ,(v_bytes*4)); + while(wrp_bytes > 0) begin /// get the strb that is wrapped + temp_strb = temp_strb << 1; + temp_strb[0] = wrp_strb[((data_bus_width/8)*axi_burst_len) : ((data_bus_width/8)*axi_burst_len)-1]; + wrp_strb = wrp_strb << 1; + wrp_bytes = wrp_bytes - 1; + // $display("wrap strb wrp_strb %0h wrp_bytes %0h temp_strb %0h",wrp_strb,wrp_bytes,temp_strb); + end + wrp_bytes = addr - start_addr; + wrp_strb = b_strb << (wrp_bytes); + + aligned_strb = (temp_strb | wrp_strb); + // $display("wrap strb aligned_strb %0h tmep_strb %0h wrp_strb %0h",aligned_strb,temp_strb,wrp_strb); + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Calculate the Response for each read/write transaction */ + function [axi_rsp_width-1:0] calculate_resp; + input rd_wr; // indicates Read(1) or Write(0) transaction + input [addr_width-1:0] awaddr; + input [axi_prot_width-1:0] awprot; + reg [axi_rsp_width-1:0] rsp; + begin + rsp = AXI_OK; + /* Address Decode */ + if(decode_address(awaddr) === INVALID_MEM_TYPE) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) awaddr %0h",$time, DISP_ERR, slave_name, awaddr,awaddr); + end + if(!rd_wr && decode_address(awaddr) === REG_MEM) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr); + end + if(secure_access_enabled && awprot[1]) + rsp = AXI_DEC_ERR; // decode error + calculate_resp = rsp; + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the Write response for each write transaction */ + // always@(negedge S_RESETN or posedge S_ACLK) + // begin + initial begin + forever begin + if(!S_RESETN) begin + wr_bresp_cnt = 0; + wr_fifo_wr_ptr = 0; + end else begin + // $display("%t ACP enable_write_bresp %0d wr_bresp_cnt %0d",$time ,enable_write_bresp,wr_bresp_cnt[int_wr_cntr_width-1:0]); + // $display("%t ACP aw_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] %0d wlast_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] %0d ",$time,aw_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] , wlast_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]]); + // if((wlast_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] === 'b1) && (aw_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] === 'b1)) begin + wait((wlast_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] === 'b1) && (aw_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] === 'b1)) begin + // enable_write_bresp <= aw_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]]; + //#0 enable_write_bresp = 'b1; + enable_write_bresp = 'b1; + // $display("%t ACP enable_write_bresp %0d wr_bresp_cnt %0d",$time ,enable_write_bresp,wr_bresp_cnt[int_wr_cntr_width-1:0]); + // $display("%t enable_write_bresp %0d wr_bresp_cnt %0d",$time ,enable_write_bresp,wr_bresp_cnt[int_wr_cntr_width-1:0]); + end + // enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]]; + /* calculate bresp only when AWVALID && WLAST is received */ + if(enable_write_bresp) begin + aw_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] = 0; + wlast_flag[wr_bresp_cnt[int_wr_cntr_width-1:0]] = 0; + // $display("awaddr[wr_bresp_cnt[int_wr_cntr_width-1:0]] %0h ",awaddr[wr_bresp_cnt[int_wr_cntr_width-1:0]]); + bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-1:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-1:0]]); + fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-1:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-1:0]],bresp}; + /* Fill WR data FIFO */ + if(bresp === AXI_OK) begin + if(awbrst[wr_bresp_cnt[int_wr_cntr_width-1:0]] === AXI_WRAP) begin /// wrap type? then align the data + get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-1:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-1:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-1:0]]); /// gives wrapped start address + get_wrap_aligned_wr_strb(aligned_wr_strb,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-1:0]],burst_strb[wr_bresp_cnt[int_wr_cntr_width-1:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-1:0]]); /// gives wrapped start address + end else begin + aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-1:0]]; + aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-1:0]] ; + aligned_wr_strb = burst_strb[wr_bresp_cnt[int_wr_cntr_width-1:0]]; + //$display(" got form fifo aligned_wr_addr %0h wr_bresp_cnt[int_wr_cntr_width-1:0]] %0d",aligned_wr_addr,wr_bresp_cnt[int_wr_cntr_width-1:0]); + //$display(" got form fifo aligned_wr_strb %0h wr_bresp_cnt[int_wr_cntr_width-1:0]] %0d",aligned_wr_strb,wr_bresp_cnt[int_wr_cntr_width-1:0]); + end + valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-1:0]]; + end else + valid_data_bytes = 0; + + if(awbrst[wr_bresp_cnt[int_wr_cntr_width-1:0]] != AXI_WRAP) begin + // wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-1:0]] = {burst_strb[wr_bresp_cnt[int_wr_cntr_width-1:0]],awqos[wr_bresp_cnt[int_wr_cntr_width-1:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-1:0]] = {aligned_wr_strb,awqos[wr_bresp_cnt[int_wr_cntr_width-1:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + // $display(" %0t ACP updating the wr_fifo wrap aligned_wr_strb %0h aligned_wr_addr %0h valid_data_bytes %0h",$time,aligned_wr_strb,aligned_wr_addr ,valid_data_bytes); + end else begin + wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-1:0]] = {aligned_wr_strb,awqos[wr_bresp_cnt[int_wr_cntr_width-1:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + // $display(" %0t ACP updating the wr_fifo incr aligned_wr_strb %0h aligned_wr_addr %0h valid_data_bytes %0h",$time,aligned_wr_strb,aligned_wr_addr ,valid_data_bytes); + end + wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1'b1; + wr_bresp_cnt = wr_bresp_cnt+1'b1; + enable_write_bresp = 'b0; + if(wr_bresp_cnt == 2'd2) begin + wr_fifo_full_flag = 1'b1; + end + + // $display(" %0t ACP before resetting the wr_bresp_cnt counter %0d max_wr_outstanding_transactions %0d int_wr_cntr_width %0d wr_fifo_wr_ptr %0d" ,$time, wr_bresp_cnt[int_wr_cntr_width-1:0],max_wr_outstanding_transactions,int_wr_cntr_width,wr_fifo_wr_ptr); + if(wr_bresp_cnt[int_wr_cntr_width-1:0] === (max_wr_outstanding_transactions)) begin + // wr_bresp_cnt[int_wr_cntr_width] = ~ wr_bresp_cnt[int_wr_cntr_width]; + wr_bresp_cnt[int_wr_cntr_width-1:0] = 0; + // $display(" ACP resetting the wr_bresp_cnt counter %0d " , wr_bresp_cnt); + end + + if(wr_fifo_wr_ptr[int_wr_cntr_width-1:0] === (max_wr_outstanding_transactions)) begin + wr_fifo_wr_ptr[int_wr_cntr_width-1:0] = 0; + // $display(" ACP resetting the wr_fifo_wr_ptr counter %0d " , wr_fifo_wr_ptr); + end + + end + end // else + end // alway1 + end // alway1 + /*--------------------------------------------------------------------------------*/ + + /* Send Write Response Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + rd_bresp_cnt = 0; + wr_latency_count = get_wr_lat_number(1); + // wr_latency_count = 5; + wr_delayed = 0; + bresp_time_cnt = 0; + end else begin + // if(static_count < 32 ) begin + // // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); + // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); + // //wready_gen.set_low_time(0); + // //wready_gen.set_high_time(1); + // slv.wr_driver.send_wready(wready_gen); + // end + // $display(" ACP waiting for awvalid_flag[bresp_time_cnt] %0d $realtime %0t awvalid_receive_time[bresp_time_cnt] %0t",awvalid_flag[bresp_time_cnt],$realtime ,awvalid_receive_time[bresp_time_cnt]); + // $display(" ACP waiting for wr_latency_count %0t bresp_time_cnt %0d",wr_latency_count,bresp_time_cnt); + // $display(" ACP waiting for diff_time %0t",diff_time); + if(awvalid_flag[bresp_time_cnt] && (($realtime - awvalid_receive_time[bresp_time_cnt])/diff_time >= wr_latency_count)) begin + wr_delayed = 1; + end + // $display(" ACP waiting for wr_delayed wr_delayed %0d bresp_fifo_empty %0d ",wr_delayed,bresp_fifo_empty); + if(!bresp_fifo_empty && wr_delayed) begin + // $display(" ACP before getting twr wr_delayed %0d bresp_fifo_empty %0d ",wr_delayed,bresp_fifo_empty); + slv.wr_driver.get_wr_reactive(twr); + // $display(" ACP after getting twr wr_delayed %0d bresp_fifo_empty %0d ",wr_delayed,bresp_fifo_empty); + twr.set_id(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-1:0]][rsp_id_msb : rsp_id_lsb]); + case(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-1:0]][rsp_msb : rsp_lsb]) + 2'b00: twr.set_bresp(XIL_AXI_RESP_OKAY); + 2'b01: twr.set_bresp(XIL_AXI_RESP_EXOKAY); + 2'b10: twr.set_bresp(XIL_AXI_RESP_SLVERR); + 2'b11: twr.set_bresp(XIL_AXI_RESP_DECERR); + endcase + // if(static_count > 32 ) begin + // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); + wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); + // wready_gen.set_low_time(3); + // wready_gen.set_high_time(3); + // wready_gen.set_low_time_range(3,6); + // wready_gen.set_high_time_range(3,6); + // slv.wr_driver.send_wready(wready_gen); + // end + slv.wr_driver.send_wready(wready_gen); + slv.wr_driver.send(twr); + // $display("%0t ACP sending the element to driver",$time); + wr_delayed = 0; + awvalid_flag[bresp_time_cnt] = 1'b0; + bresp_time_cnt = bresp_time_cnt+1; + rd_bresp_cnt = rd_bresp_cnt + 1; + if(rd_bresp_cnt == 2'd2) begin + wr_fifo_full_flag = 1'b0; + end + if(rd_bresp_cnt[int_wr_cntr_width-1:0] === (max_wr_outstanding_transactions)) begin + // rd_bresp_cnt[int_wr_cntr_width] = ~ rd_bresp_cnt[int_wr_cntr_width]; + rd_bresp_cnt[int_wr_cntr_width-1:0] = 0; + end + if(bresp_time_cnt[int_wr_cntr_width-1:0] === max_wr_outstanding_transactions) begin + bresp_time_cnt[int_wr_cntr_width-1:0] = 0; + end + wr_latency_count = get_wr_lat_number(1); + // wr_latency_count = 5; + static_count++; + end + static_count++; + end // else + end//always + /*--------------------------------------------------------------------------------*/ + + /* Reading from the wr_fifo */ + always@(negedge S_RESETN or posedge SW_CLK) begin + if(!S_RESETN) begin + WR_DATA_VALID_DDR = 1'b0; + WR_DATA_VALID_OCM = 1'b0; + wr_fifo_rd_ptr = 0; + state = SEND_DATA; + WR_QOS = 0; + end else begin + case(state) + SEND_DATA :begin + state = SEND_DATA; + WR_DATA_VALID_OCM = 0; + WR_DATA_VALID_DDR = 0; + if(!wr_fifo_empty) begin + WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-1:0]][wr_data_msb : wr_data_lsb]; + WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-1:0]][wr_addr_msb : wr_addr_lsb]; + WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-1:0]][wr_bytes_msb : wr_bytes_lsb]; + WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-1:0]][wr_qos_msb : wr_qos_lsb]; + WR_DATA_STRB = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-1:0]][wr_strb_msb : wr_strb_lsb]; + state = WAIT_ACK; + $display("ACP final WR_ADDR %0h WR_DATA %0h WR_DATA_STRB %0h wr_fifo_rd_ptr %0d",WR_ADDR,WR_DATA[31:0],WR_DATA_STRB,wr_fifo_rd_ptr[int_wr_cntr_width-1:0]); + case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-1:0]][wr_addr_msb : wr_addr_lsb])) + OCM_MEM : WR_DATA_VALID_OCM = 1; + DDR_MEM : WR_DATA_VALID_DDR = 1; + default : state = SEND_DATA; + endcase + wr_fifo_rd_ptr = wr_fifo_rd_ptr+1; + if(wr_fifo_rd_ptr[int_wr_cntr_width-1:0] === (max_wr_outstanding_transactions)) begin + wr_fifo_rd_ptr[int_wr_cntr_width] = ~ wr_fifo_rd_ptr[int_wr_cntr_width]; + wr_fifo_rd_ptr[int_wr_cntr_width-1:0] = 0; + // $display(" ACP resetting the wr_fifo_rd_ptr counter %0d " , wr_fifo_rd_ptr); + end + + end + end + WAIT_ACK :begin + state = WAIT_ACK; + if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + state = SEND_DATA; + end + end + endcase + end + end + /*--------------------------------------------------------------------------------*/ +/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ + +/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ + + /* READ CHANNELS */ + /* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ + reg [int_rd_cntr_width-1:0] ar_time_cnt = 0,rresp_time_cnt = 0; + real arvalid_receive_time[0:max_rd_outstanding_transactions-1]; // store the time when a new arvalid is received + reg arvalid_flag[0:max_rd_outstanding_transactions-1]; // store the time when a new arvalid is received + reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1]; + reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1]; + reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1]; + reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1]; + reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1]; + reg ar_flag [0:max_rd_outstanding_transactions-1]; + reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1]; + reg [addr_width-1:0] addr_local; + reg [addr_width-1:0] addr_final; + reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1]; + reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1]; + wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) + + reg [int_rd_cntr_width-1:0] rd_cnt = 0; + reg [int_rd_cntr_width-1:0] trr_rd_cnt = 0; + reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0; + reg [axi_rsp_width-1:0] rresp; + reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response + + /* Send Read Response & Data Channel handshake */ + integer rd_latency_count; + reg rd_delayed; + reg read_fifo_empty; + + reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data .. + reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; + wire read_fifo_full; + + assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-1:0] === rd_fifo_rd_ptr[int_rd_cntr_width-1:0])?1'b1: 1'b0; + assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0; + assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-1:0] === rd_cnt[int_rd_cntr_width-1:0]))?1'b1 :1'b0; + + /* Store the arvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) + ar_time_cnt = 0; + else begin + if(net_ARVALID == 'b1 && S_ARREADY == 'b1) begin + arvalid_receive_time[ar_time_cnt] = $time; + arvalid_flag[ar_time_cnt] = 1'b1; + ar_time_cnt = ar_time_cnt + 1; + // $display(" %m current ar_time_cnt %0d",ar_time_cnt); + if((ar_time_cnt === max_rd_outstanding_transactions) ) begin + ar_time_cnt = 0; + // $display("reached max count max_rd_outstanding_transactions %0d aw_time_cnt %0d",max_rd_outstanding_transactions,ar_time_cnt); + // $display(" resetting the read ar_time_cnt counter %0d", ar_time_cnt); + end + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_ARVALID == 'b1 && S_ARREADY == 'b1) begin + if(S_ARQOS === 0) begin + arqos[ar_cnt[int_rd_cntr_width-1:0]] = ar_qos; + end else begin + arqos[ar_cnt[int_rd_cntr_width-1:0]] = S_ARQOS; + end + end + end + /*--------------------------------------------------------------------------------*/ + + always@(ar_fifo_full) + begin + if(ar_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions); + end + /*--------------------------------------------------------------------------------*/ + + /* Address Read Channel handshake*/ + // always@(negedge S_RESETN or posedge S_ACLK) + // begin + initial begin + forever begin + if(!S_RESETN) begin + ar_cnt = 0; + end else begin + // if(!ar_fifo_full) begin + wait(ar_fifo_full != 1) begin + slv.monitor.axi_rd_cmd_port.get(trc); + // araddr[ar_cnt[int_rd_cntr_width-2:0]] = trc.addr; + arlen[ar_cnt[int_rd_cntr_width-1:0]] = trc.len; + arsize[ar_cnt[int_rd_cntr_width-1:0]] = trc.size; + arbrst[ar_cnt[int_rd_cntr_width-1:0]] = trc.burst; + arlock[ar_cnt[int_rd_cntr_width-1:0]] = trc.lock; + arcache[ar_cnt[int_rd_cntr_width-1:0]]= trc.cache; + arprot[ar_cnt[int_rd_cntr_width-1:0]] = trc.prot; + arid[ar_cnt[int_rd_cntr_width-1:0]] = trc.id; + ar_flag[ar_cnt[int_rd_cntr_width-1:0]] = 1'b1; + size_local = trc.size; + addr_local = trc.addr; + case(size_local) + 0 : addr_final = {addr_local}; + 1 : addr_final = {addr_local[31:1],1'b0}; + 2 : addr_final = {addr_local[31:2],2'b0}; + 3 : addr_final = {addr_local[31:3],3'b0}; + 4 : addr_final = {addr_local[31:4],4'b0}; + 5 : addr_final = {addr_local[31:5],5'b0}; + 6 : addr_final = {addr_local[31:6],6'b0}; + 7 : addr_final = {addr_local[31:7],7'b0}; + endcase + araddr[ar_cnt[int_rd_cntr_width-1:0]] = addr_final; + ar_cnt = ar_cnt+1; + // $display(" READ address addr_final %0h ar_cnt %0d",addr_final,ar_cnt); + if(ar_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) begin + ar_cnt[int_rd_cntr_width] = ~ ar_cnt[int_rd_cntr_width]; + ar_cnt[int_rd_cntr_width-1:0] = 0; + // $display(" reseeting the read ar_cnt %0d",ar_cnt); + end + end /// if(!ar_fifo_full) + end /// if else + end /// forever + end /// always*/ + /*--------------------------------------------------------------------------------*/ + + /* Align Wrap data for read transaction*/ + task automatic get_wrap_aligned_rd_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [addr_width-1:0] start_addr; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data >> 8; + temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; + wrp_data = wrp_data >> 8; + wrp_bytes = wrp_bytes - 1; + end + temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); + wrp_bytes = addr - start_addr; + wrp_data = b_data >> (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1; + reg [addr_width-1:0] temp_read_address; + reg [max_burst_bytes_width:0] temp_rd_valid_bytes; + reg rd_fifo_state; + reg invalid_rd_req; + /* get the data from memory && also calculate the rresp*/ + always@(negedge S_RESETN or posedge SW_CLK) + begin + if(!S_RESETN)begin + rd_fifo_wr_ptr = 0; + wr_rresp_cnt =0; + rd_fifo_state = RD_DATA_REQ; + temp_rd_valid_bytes = 0; + temp_read_address = 0; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + invalid_rd_req = 0; + end else begin + case(rd_fifo_state) + RD_DATA_REQ : begin + rd_fifo_state = RD_DATA_REQ; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + wait(ar_flag[wr_rresp_cnt[int_rd_cntr_width-1:0]] == 1'b1 && read_fifo_full == 0) begin + // $display(" got the element for ar_flag %0h wr_rresp_cnt[int_rd_cntr_width-1:0] %0d ",ar_flag[wr_rresp_cnt[int_rd_cntr_width-1:0]],wr_rresp_cnt[int_rd_cntr_width-1:0]); + ar_flag[wr_rresp_cnt[int_rd_cntr_width-1:0]] = 0; + rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-1:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-1:0]]); + fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-1:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-1:0]],rresp}; + temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-1:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-1:0]]);//data_bus_width/8; + // $display(" got the element for id %0h ",arid[wr_rresp_cnt[int_rd_cntr_width-1:0]]); + + if(arbrst[wr_rresp_cnt[int_rd_cntr_width-1:0]] === AXI_WRAP) /// wrap begin + temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-1:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; + else + temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-1:0]]; + if(rresp === AXI_OK) begin + case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]); + OCM_MEM : RD_REQ_OCM = 1; + DDR_MEM : RD_REQ_DDR = 1; + REG_MEM : RD_REQ_REG = 1; + default : invalid_rd_req = 1; + endcase + end else + invalid_rd_req = 1; + + RD_QOS = arqos[wr_rresp_cnt[int_rd_cntr_width-1:0]]; + RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + RD_BYTES = temp_rd_valid_bytes; + rd_fifo_state = WAIT_RD_VALID; + wr_rresp_cnt = wr_rresp_cnt + 1; + // $display(" before resetting the read wr_rresp_cnt counter %0d", wr_rresp_cnt); + // $display(" final read address RD_ADDR %0h RD_BYTES %0h" , RD_ADDR,RD_BYTES); + if(wr_rresp_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) begin + wr_rresp_cnt[int_rd_cntr_width] = ~ wr_rresp_cnt[int_rd_cntr_width]; + wr_rresp_cnt[int_rd_cntr_width-1:0] = 0; + // $display(" resetting the read wr_rresp_cnt counter %0d", wr_rresp_cnt); + end + end + end + WAIT_RD_VALID : begin + rd_fifo_state = WAIT_RD_VALID; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin + if(RD_DATA_VALID_DDR) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-1:0]] = RD_DATA_DDR; + else if(RD_DATA_VALID_OCM) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-1:0]] = RD_DATA_OCM; + else if(RD_DATA_VALID_REG) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-1:0]] = RD_DATA_REG; + else + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-1:0]] = 0; + rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; + if(rd_fifo_wr_ptr[int_rd_cntr_width-1:0] === (max_rd_outstanding_transactions)) begin + rd_fifo_wr_ptr[int_rd_cntr_width] = ~rd_fifo_wr_ptr[int_rd_cntr_width] ; + rd_fifo_wr_ptr[int_rd_cntr_width-1:0] = 0; + // $display(" resetting the read rd_fifo_wr_ptr counter %0d", rd_fifo_wr_ptr); + end + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + invalid_rd_req = 0; + rd_fifo_state = RD_DATA_REQ; + end + end + endcase + end /// else + end /// always + + /*--------------------------------------------------------------------------------*/ + reg[max_burst_bytes_width:0] rd_v_b; + reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data; + reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data; + reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; + + xil_axi_data_beat new_data; + + + /* Read Data Channel handshake */ + //always@(negedge S_RESETN or posedge S_ACLK) + initial begin + forever begin + if(!S_RESETN)begin + // rd_fifo_rd_ptr = 0; + trr_rd_cnt = 0; + // rd_latency_count = get_rd_lat_number(1); + // rd_delayed = 0; + // rresp_time_cnt = 0; + // rd_v_b = 0; + end else begin + //if(net_ARVALID && S_ARREADY) + // trr_rd[trr_rd_cnt] = new("trr_rd[trr_rd_cnt]"); + // trr_rd[trr_rd_cnt] = new($psprintf("trr_rd[%0d]",trr_rd_cnt)); + slv.rd_driver.get_rd_reactive(trr); + // $display(" got the id form slv trr.id %0h" trr.id); + trr_rd.push_back(trr.my_clone()); + //$cast(trr_rd[trr_rd_cnt],trr.copy()); + // rd_latency_count = get_rd_lat_number(1); + // $display("%m waiting for next transfer trr_rd_cnt %0d trr.size %0d " ,trr_rd_cnt,trr.size); + // $display("%m waiting for next transfer trr_rd_cnt %0d trr_rd[trr_rd_cnt] %0d" ,trr_rd_cnt,trr_rd[trr_rd_cnt].size); + trr_rd_cnt++; + // $display("%m waiting for next transfer trr_rd_cnt %0d" ,trr_rd_cnt); + // @(posedge S_ACLK); + end + end // forever + end // initial + + + initial begin + forever begin + if(!S_RESETN)begin + rd_fifo_rd_ptr = 0; + rd_cnt = 0; + // rd_latency_count = get_rd_lat_number(1); + rd_latency_count = 20; + rd_delayed = 0; + rresp_time_cnt = 0; + rd_v_b = 0; + end else begin + //if(net_ARVALID && S_ARREADY) + // slv.rd_driver.get_rd_reactive(trr_rd[rresp_time_cnt]); + wait(arvalid_flag[rresp_time_cnt] == 1); + // while(trr_rd[rresp_time_cnttrr_rd_cnt] == null) begin + // @(posedge S_ACLK); + // end + // rd_latency_count = get_rd_lat_number(1); + rd_latency_count = 20; + // $display("%m waiting for element form vip rresp_time_cnt %0d ",rresp_time_cnt); + // while(trr_rd.size()< 0 ) begin + // $display("%m got the element form vip rresp_time_cnt %0d ",rresp_time_cnt); + // @(posedge S_ACLK); + // end + // $display("%m got the element form vip rresp_time_cnt %0d ",rresp_time_cnt); + wait(trr_rd.size() > 0); + trr_get_rd = trr_rd.pop_front(); + // $display("%m got the element trr_rd waiting for next transfer rresp_time_cnt %0d trr_get_rd.id %0h" ,rresp_time_cnt,trr_get_rd.id); + while ((arvalid_flag[rresp_time_cnt] == 'b1 )&& ((($realtime - arvalid_receive_time[rresp_time_cnt])/diff_time) < rd_latency_count)) begin + @(posedge S_ACLK); + end + + //if(arvalid_flag[rresp_time_cnt] && ((($realtime - arvalid_receive_time[rresp_time_cnt])/diff_time) >= rd_latency_count)) + rd_delayed = 1; + // $display("%m reading form rd_delayed %0d read_fifo_empty %0d next transfer rresp_time_cnt %0d trr_get_rd.id %0h",rd_delayed ,~read_fifo_empty,rresp_time_cnt,trr_get_rd.id); + if(!read_fifo_empty && rd_delayed)begin + rd_delayed = 0; + // $display("%m reading form rd_delayed %0d next transfer rresp_time_cnt %0d trr_get_rd.id %0h",rd_delayed ,rresp_time_cnt,trr_get_rd.id); + arvalid_flag[rresp_time_cnt] = 1'b0; + rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-1:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-1:0]])); + temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-1:0]]; + rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; + + if(arbrst[rd_cnt[int_rd_cntr_width-1:0]]=== AXI_WRAP) begin + get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-1:0]], temp_read_data, rd_v_b); + temp_read_data = temp_wrap_data; + end + temp_read_rsp = 0; + repeat(axi_burst_len) begin + temp_read_rsp = temp_read_rsp >> axi_rsp_width; + temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-1:0]][rsp_msb : rsp_lsb]; + end + case (arsize[rd_cnt[int_rd_cntr_width-1:0]]) + 3'b000: trr_get_rd.size = XIL_AXI_SIZE_1BYTE; + 3'b001: trr_get_rd.size = XIL_AXI_SIZE_2BYTE; + 3'b010: trr_get_rd.size = XIL_AXI_SIZE_4BYTE; + 3'b011: trr_get_rd.size = XIL_AXI_SIZE_8BYTE; + 3'b100: trr_get_rd.size = XIL_AXI_SIZE_16BYTE; + 3'b101: trr_get_rd.size = XIL_AXI_SIZE_32BYTE; + 3'b110: trr_get_rd.size = XIL_AXI_SIZE_64BYTE; + 3'b111: trr_get_rd.size = XIL_AXI_SIZE_128BYTE; + endcase + trr_get_rd.len = arlen[rd_cnt[int_rd_cntr_width-1:0]]; + trr_get_rd.id = (arid[rd_cnt[int_rd_cntr_width-1:0]]); +// trr_get_rd.data = new[((2**arsize[rd_cnt[int_rd_cntr_width-2:0]])*(arlen[rd_cnt[int_rd_cntr_width-2:0]]+1))]; + trr_get_rd.rresp = new[((2**arsize[rd_cnt[int_rd_cntr_width-1:0]])*(arlen[rd_cnt[int_rd_cntr_width-1:0]]+1))]; + // $display("%m updateing reading form trr_get_rd.id %0d next transfer rresp_time_cnt %0d trr_get_rd.id %0h",trr_get_rd.id,rresp_time_cnt,trr_get_rd.id); + for(j = 0; j < (arlen[rd_cnt[int_rd_cntr_width-1:0]]+1); j = j+1) begin + for(k = 0; k < (2**arsize[rd_cnt[int_rd_cntr_width-1:0]]); k = k+1) begin + new_data[(k*8)+:8] = temp_read_data[7:0]; + temp_read_data = temp_read_data >> 8; + end + trr_get_rd.set_data_beat(j, new_data); + // $display("Read data %0h trr_get_rd.id %0h rd_cnt[int_rd_cntr_width-1:0] %0d",new_data,trr_get_rd.id,rd_cnt[int_rd_cntr_width-1:0]); + case(temp_read_rsp[(j*2)+:2]) + 2'b00: trr_get_rd.rresp[j] = XIL_AXI_RESP_OKAY; + 2'b01: trr_get_rd.rresp[j] = XIL_AXI_RESP_EXOKAY; + 2'b10: trr_get_rd.rresp[j] = XIL_AXI_RESP_SLVERR; + 2'b11: trr_get_rd.rresp[j] = XIL_AXI_RESP_DECERR; + endcase + end + slv.rd_driver.send(trr_get_rd); + rd_cnt = rd_cnt + 1; + rresp_time_cnt = rresp_time_cnt+1; + // $display("current rresp_time_cnt %0d rd_cnt %0d",rresp_time_cnt,rd_cnt[int_rd_cntr_width-1:0]); + if(rd_cnt[int_rd_cntr_width-1:0] === (max_rd_outstanding_transactions)) begin + rd_cnt[int_rd_cntr_width] = ~ rd_cnt[int_rd_cntr_width]; + rd_cnt[int_rd_cntr_width-1:0] = 0; + // $display(" resetting the read rd_cnt counter %0d", rd_cnt); + end + if(rresp_time_cnt[int_rd_cntr_width-1:0] === (max_rd_outstanding_transactions)) begin + rresp_time_cnt[int_rd_cntr_width] = ~ rresp_time_cnt[int_rd_cntr_width] ; + rresp_time_cnt[int_rd_cntr_width-1:0] = 0; + // $display(" resetting the read rresp_time_cnt counter %0d", rresp_time_cnt); + end + if(rd_fifo_rd_ptr[int_rd_cntr_width-1:0] === (max_rd_outstanding_transactions)) begin + rd_fifo_rd_ptr[int_rd_cntr_width] = ~rd_fifo_rd_ptr[int_rd_cntr_width] ; + rd_fifo_rd_ptr[int_rd_cntr_width-1:0] = 0; + // $display(" resetting the read rd_fifo_rd_ptr counter %0d", rd_fifo_rd_ptr); + end + rd_latency_count = get_rd_lat_number(1); + end + end /// else + end /// always +end +endmodule + + + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_axi_master.v + * + * Date : 2012-11 + * + * Description : Model that acts as PS AXI Master port interface. + * It uses AXI3 Master VIP + *****************************************************************************/ + `timescale 1ns/1ps + +import axi_vip_pkg::*; + +module processing_system7_vip_v1_0_16_axi_master ( + M_RESETN, + M_ARVALID, + M_AWVALID, + M_BREADY, + M_RREADY, + M_WLAST, + M_WVALID, + M_ARID, + M_AWID, + M_WID, + M_ARBURST, + M_ARLOCK, + M_ARSIZE, + M_AWBURST, + M_AWLOCK, + M_AWSIZE, + M_ARPROT, + M_AWPROT, + M_ARADDR, + M_AWADDR, + M_WDATA, + M_ARCACHE, + M_ARLEN, + M_AWCACHE, + M_AWLEN, + M_ARQOS, // not connected to AXI VIP + M_AWQOS, // not connected to AXI VIP + M_WSTRB, + M_ACLK, + M_ARREADY, + M_AWREADY, + M_BVALID, + M_RLAST, + M_RVALID, + M_WREADY, + M_BID, + M_RID, + M_BRESP, + M_RRESP, + M_RDATA + +); + parameter enable_this_port = 0; + parameter master_name = "Master"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + parameter ID = 12'hC00; + `include "processing_system7_vip_v1_0_16_local_params.v" + /* IDs for Masters + // l2m1 (CPU000) + 12'b11_000_000_00_00 + 12'b11_010_000_00_00 + 12'b11_011_000_00_00 + 12'b11_100_000_00_00 + 12'b11_101_000_00_00 + 12'b11_110_000_00_00 + 12'b11_111_000_00_00 + // l2m1 (CPU001) + 12'b11_000_001_00_00 + 12'b11_010_001_00_00 + 12'b11_011_001_00_00 + 12'b11_100_001_00_00 + 12'b11_101_001_00_00 + 12'b11_110_001_00_00 + 12'b11_111_001_00_00 + */ + + input M_RESETN; + + output M_ARVALID; + output M_AWVALID; + output M_BREADY; + output M_RREADY; + output M_WLAST; + output M_WVALID; + output [id_bus_width-1:0] M_ARID; + output [id_bus_width-1:0] M_AWID; + output [id_bus_width-1:0] M_WID; + output [axi_brst_type_width-1:0] M_ARBURST; + output [axi_lock_width-1:0] M_ARLOCK; + output [axi_size_width-1:0] M_ARSIZE; + output [axi_brst_type_width-1:0] M_AWBURST; + output [axi_lock_width-1:0] M_AWLOCK; + output [axi_size_width-1:0] M_AWSIZE; + output [axi_prot_width-1:0] M_ARPROT; + output [axi_prot_width-1:0] M_AWPROT; + output [address_bus_width-1:0] M_ARADDR; + output [address_bus_width-1:0] M_AWADDR; + output [data_bus_width-1:0] M_WDATA; + output [axi_cache_width-1:0] M_ARCACHE; + output [axi_len_width-1:0] M_ARLEN; + output [axi_qos_width-1:0] M_ARQOS; // not connected to AXI VIP + output [axi_cache_width-1:0] M_AWCACHE; + output [axi_len_width-1:0] M_AWLEN; + output [axi_qos_width-1:0] M_AWQOS; // not connected to AXI VIP + output [(data_bus_width/8)-1:0] M_WSTRB; + input M_ACLK; + input M_ARREADY; + input M_AWREADY; + input M_BVALID; + input M_RLAST; + input M_RVALID; + input M_WREADY; + input [id_bus_width-1:0] M_BID; + input [id_bus_width-1:0] M_RID; + input [axi_rsp_width-1:0] M_BRESP; + input [axi_rsp_width-1:0] M_RRESP; + input [data_bus_width-1:0] M_RDATA; + + wire net_RESETN; + wire net_RVALID; + wire net_BVALID; + reg DEBUG_INFO = 1'b1; + reg STOP_ON_ERROR = 1'b1; + + integer use_id_no = 0; + + assign M_ARQOS = 'b0; + assign M_AWQOS = 'b0; + assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1'b0; + assign net_RVALID = enable_this_port ? M_RVALID : 1'b0; + assign net_BVALID = enable_this_port ? M_BVALID : 1'b0; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, master_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, master_name); + end + end + + initial master.IF.xilinx_slave_ready_check_enable = 0; + initial begin + repeat(2) @(posedge M_ACLK); + if(!enable_this_port) begin +// master.set_channel_level_info(0); +// master.set_function_level_info(0); + end +// master.RESPONSE_TIMEOUT = 0; + end + + axi_mst_agent #(1,address_bus_width, data_bus_width, data_bus_width, id_bus_width,id_bus_width,0,0,0,0,0,1,1,1,1,0,1,1,1,1,1,1) mst; + + axi_vip_v1_1_14_top #( + .C_AXI_PROTOCOL(1), + .C_AXI_INTERFACE_MODE(0), + .C_AXI_ADDR_WIDTH(address_bus_width), + .C_AXI_WDATA_WIDTH(data_bus_width), + .C_AXI_RDATA_WIDTH(data_bus_width), + .C_AXI_WID_WIDTH(id_bus_width), + .C_AXI_RID_WIDTH(id_bus_width), + .C_AXI_AWUSER_WIDTH(0), + .C_AXI_ARUSER_WIDTH(0), + .C_AXI_WUSER_WIDTH(0), + .C_AXI_RUSER_WIDTH(0), + .C_AXI_BUSER_WIDTH(0), + .C_AXI_SUPPORTS_NARROW(1), + .C_AXI_HAS_BURST(1), + .C_AXI_HAS_LOCK(1), + .C_AXI_HAS_CACHE(1), + .C_AXI_HAS_REGION(0), + .C_AXI_HAS_PROT(1), + .C_AXI_HAS_QOS(1), + .C_AXI_HAS_WSTRB(1), + .C_AXI_HAS_BRESP(1), + .C_AXI_HAS_RRESP(1), + .C_AXI_HAS_ARESETN(1) + ) master ( + .aclk(M_ACLK), + .aclken(1'B1), + .aresetn(net_RESETN), + .s_axi_awid(12'h000), + .s_axi_awaddr(32'B0), + .s_axi_awlen(4'h0), + .s_axi_awsize(3'B0), + .s_axi_awburst(2'B0), + .s_axi_awlock(2'b00), + .s_axi_awcache(4'B0), + .s_axi_awprot(3'B0), + .s_axi_awregion(4'B0), + .s_axi_awqos(4'B0), + .s_axi_awuser(1'B0), + .s_axi_awvalid(1'B0), + .s_axi_awready(), + .s_axi_wid(12'h000), + .s_axi_wdata(32'B0), + .s_axi_wstrb(4'B0), + .s_axi_wlast(1'B0), + .s_axi_wuser(1'B0), + .s_axi_wvalid(1'B0), + .s_axi_wready(), + .s_axi_bid(), + .s_axi_bresp(), + .s_axi_buser(), + .s_axi_bvalid(), + .s_axi_bready(1'B0), + .s_axi_arid(12'h000), + .s_axi_araddr(32'B0), + .s_axi_arlen(4'h0), + .s_axi_arsize(3'B0), + .s_axi_arburst(2'B0), + .s_axi_arlock(2'b00), + .s_axi_arcache(4'B0), + .s_axi_arprot(3'B0), + .s_axi_arregion(4'B0), + .s_axi_arqos(4'B0), + .s_axi_aruser(1'B0), + .s_axi_arvalid(1'B0), + .s_axi_arready(), + .s_axi_rid(), + .s_axi_rdata(), + .s_axi_rresp(), + .s_axi_rlast(), + .s_axi_ruser(), + .s_axi_rvalid(), + .s_axi_rready(1'B0), + .m_axi_awid(M_AWID), + .m_axi_awaddr(M_AWADDR), + .m_axi_awlen(M_AWLEN), + .m_axi_awsize(M_AWSIZE), + .m_axi_awburst(M_AWBURST), + .m_axi_awlock(M_AWLOCK), + .m_axi_awcache(M_AWCACHE), + .m_axi_awprot(M_AWPROT), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(M_AWVALID), + .m_axi_awready(M_AWREADY), + .m_axi_wid(M_WID), + .m_axi_wdata(M_WDATA), + .m_axi_wstrb(M_WSTRB), + .m_axi_wlast(M_WLAST), + .m_axi_wuser(), + .m_axi_wvalid(M_WVALID), + .m_axi_wready(M_WREADY), + .m_axi_bid(M_BID), + .m_axi_bresp(M_BRESP), + .m_axi_buser(1'B0), + .m_axi_bvalid(M_BVALID), + .m_axi_bready(M_BREADY), + .m_axi_arid(M_ARID), + .m_axi_araddr(M_ARADDR), + .m_axi_arlen(M_ARLEN), + .m_axi_arsize(M_ARSIZE), + .m_axi_arburst(M_ARBURST), + .m_axi_arlock(M_ARLOCK), + .m_axi_arcache(M_ARCACHE), + .m_axi_arprot(M_ARPROT), + .m_axi_arregion(), + .m_axi_arqos(M_ARQOS), + .m_axi_aruser(), + .m_axi_arvalid(M_ARVALID), + .m_axi_arready(M_ARREADY), + .m_axi_rid(M_RID), + .m_axi_rdata(M_RDATA), + .m_axi_rresp(M_RRESP), + .m_axi_rlast(M_RLAST), + .m_axi_ruser(1'B0), + .m_axi_rvalid(M_RVALID), + .m_axi_rready(M_RREADY) + ); + + axi_transaction tw, tr; + axi_monitor_transaction tr_m, tw_m; + axi_ready_gen bready_gen; + axi_ready_gen rready_gen; + + initial begin + mst = new("mst",master.IF); + tr_m = new("master monitor trans"); + mst.start_master(); + end + + initial begin + master.IF.set_enable_xchecks_to_warn(); + repeat(10) @(posedge M_ACLK); + master.IF.set_enable_xchecks(); + end + + +/* Call to VIP APIs */ + task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_burst_len*data_bus_width)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response); + integer i; + xil_axi_burst_t burst_i; + xil_axi_size_t size_i; + xil_axi_data_beat new_data; + xil_axi_lock_t lock_i; + reg[11:0] ID2; + integer datasize; + case (burst) + 2'b00: burst_i = XIL_AXI_BURST_TYPE_FIXED; + 2'b01: burst_i = XIL_AXI_BURST_TYPE_INCR; + 2'b10: burst_i = XIL_AXI_BURST_TYPE_WRAP; + 2'b11: burst_i = XIL_AXI_BURST_TYPE_RSVD; + endcase + case (siz) + 3'b000: size_i = XIL_AXI_SIZE_1BYTE; + 3'b001: size_i = XIL_AXI_SIZE_2BYTE; + 3'b010: size_i = XIL_AXI_SIZE_4BYTE; + 3'b011: size_i = XIL_AXI_SIZE_8BYTE; + 3'b100: size_i = XIL_AXI_SIZE_16BYTE; + 3'b101: size_i = XIL_AXI_SIZE_32BYTE; + 3'b110: size_i = XIL_AXI_SIZE_64BYTE; + 3'b111: size_i = XIL_AXI_SIZE_128BYTE; + endcase + case (lck) + 2'b00: lock_i = XIL_AXI_ALOCK_NOLOCK; + 2'b01: lock_i = XIL_AXI_ALOCK_EXCL; + 2'b10: lock_i = XIL_AXI_ALOCK_LOCKED; + 2'b11: lock_i = XIL_AXI_ALOCK_RSVD; + endcase + if(enable_this_port)begin + fork + begin + rready_gen = mst.rd_driver.create_ready("rready"); + rready_gen.set_ready_policy(XIL_AXI_READY_GEN_OSC); + // rready_gen.set_high_time(len+1); + mst.rd_driver.send_rready(rready_gen); + end + begin + tr = mst.rd_driver.create_transaction("write_tran"); + mst.rd_driver.set_transaction_depth(max_outstanding_transactions); + assert(tr.randomize()); + ID2= $urandom(); + if(DEBUG_INFO) + $display($time,"ID2 in read strb task is %0h",ID2); + tr.set_read_cmd(addr,burst_i,ID2,len,size_i); + tr.set_cache(cache); + tr.set_lock(lock_i); + tr.set_prot(prot); + mst.rd_driver.send(tr); + end + join + mst.monitor.item_collected_port.get(tr_m); + datasize = 0; + for(i = 0; i < (len+1); i = i+1) begin + new_data = tr_m.get_data_beat(i); + //$display("axi_master new_data %0h i value %0d",new_data , i ); + for(int k = 0; k < (2**siz); k = k+1) begin + data[(datasize*8)+:8] = new_data[(k*8)+:8]; + //$display("axi_master data %0h new_data %0h k value %0d datasize %0d ",data[(datasize*8)+:8],new_data[(k*8)+:8], k ,datasize ); + datasize = datasize+1; + end + response = response << 2; + response[1:0] = tr_m.rresp[i]; + end + end else begin + $display("[%0d] : %0s : %0s : Port is disabled. 'read_burst' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end + //$display("axi_master data %0h response %0h ",data, response ); + endtask + +// task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response); +// integer i; +// xil_axi_burst_t burst_i; +// xil_axi_size_t size_i; +// xil_axi_data_beat new_data; +// xil_axi_lock_t lock_i; +// integer datasize; +// case (burst) +// 2'b00: burst_i = XIL_AXI_BURST_TYPE_FIXED; +// 2'b01: burst_i = XIL_AXI_BURST_TYPE_INCR; +// 2'b10: burst_i = XIL_AXI_BURST_TYPE_WRAP; +// 2'b11: burst_i = XIL_AXI_BURST_TYPE_RSVD; +// endcase +// case (siz) +// 3'b000: size_i = XIL_AXI_SIZE_1BYTE; +// 3'b001: size_i = XIL_AXI_SIZE_2BYTE; +// 3'b010: size_i = XIL_AXI_SIZE_4BYTE; +// 3'b011: size_i = XIL_AXI_SIZE_8BYTE; +// 3'b100: size_i = XIL_AXI_SIZE_16BYTE; +// 3'b101: size_i = XIL_AXI_SIZE_32BYTE; +// 3'b110: size_i = XIL_AXI_SIZE_64BYTE; +// 3'b111: size_i = XIL_AXI_SIZE_128BYTE; +// endcase +// case (lck) +// 2'b00: lock_i = XIL_AXI_ALOCK_NOLOCK; +// 2'b01: lock_i = XIL_AXI_ALOCK_EXCL; +// 2'b10: lock_i = XIL_AXI_ALOCK_LOCKED; +// 2'b11: lock_i = XIL_AXI_ALOCK_RSVD; +// endcase +// if(enable_this_port)begin +// fork +// begin +// rready_gen = mst.rd_driver.create_ready("rready"); +// rready_gen.set_ready_policy(XIL_AXI_READY_GEN_OSC); +// rready_gen.set_high_time(len+1); +// mst.rd_driver.send_rready(rready_gen); +// end +// begin +// tr = mst.rd_driver.create_transaction("write_tran"); +// mst.rd_driver.set_transaction_depth(max_outstanding_transactions); +// assert(tr.randomize()); +// tr.set_read_cmd(addr,burst_i,ID,len,size_i); +// tr.set_cache(cache); +// tr.set_lock(lock_i); +// tr.set_prot(prot); +// mst.rd_driver.send(tr); +// end +// join +// mst.monitor.item_collected_port.get(tr_m); +// datasize = 0; +// for(i = 0; i < (len+1); i = i+1) begin +// new_data = tr_m.get_data_beat(i); +// for(int k = 0; k < (2**siz); k = k+1) begin +// data[(datasize*8)+:8] = new_data[(k*8)+:8]; +// datasize = datasize+1; +// end +// response = response << 2; +// response[1:0] = tr_m.rresp[i]; +// end +// end else begin +// $display("[%0d] : %0s : %0s : Port is disabled. 'read_burst' will not be executed...",$time, DISP_ERR, master_name); +// if(STOP_ON_ERROR) $stop; +// end +// endtask + task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_burst_len*data_bus_width)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + integer i,j; + xil_axi_burst_t burst_i; + xil_axi_size_t size_i; + xil_axi_lock_t lock_i; + xil_axi_data_beat new_data; + xil_axi_strb_beat new_strb; + + case (burst) + 2'b00: burst_i = XIL_AXI_BURST_TYPE_FIXED; + 2'b01: burst_i = XIL_AXI_BURST_TYPE_INCR; + 2'b10: burst_i = XIL_AXI_BURST_TYPE_WRAP; + 2'b11: burst_i = XIL_AXI_BURST_TYPE_RSVD; + endcase + case (siz) + 3'b000: size_i = XIL_AXI_SIZE_1BYTE; + 3'b001: size_i = XIL_AXI_SIZE_2BYTE; + 3'b010: size_i = XIL_AXI_SIZE_4BYTE; + 3'b011: size_i = XIL_AXI_SIZE_8BYTE; + 3'b100: size_i = XIL_AXI_SIZE_16BYTE; + 3'b101: size_i = XIL_AXI_SIZE_32BYTE; + 3'b110: size_i = XIL_AXI_SIZE_64BYTE; + 3'b111: size_i = XIL_AXI_SIZE_128BYTE; + endcase + case (lck) + 2'b00: lock_i = XIL_AXI_ALOCK_NOLOCK; + 2'b01: lock_i = XIL_AXI_ALOCK_EXCL; + 2'b10: lock_i = XIL_AXI_ALOCK_LOCKED; + 2'b11: lock_i = XIL_AXI_ALOCK_RSVD; + endcase + if(enable_this_port)begin + fork + begin + bready_gen = mst.wr_driver.create_ready("bready"); + bready_gen.set_ready_policy(XIL_AXI_READY_GEN_OSC); + // bready_gen.set_high_time(1); + mst.wr_driver.send_bready(bready_gen); + end + begin + tw = mst.wr_driver.create_transaction("write_tran"); + mst.wr_driver.set_transaction_depth(max_outstanding_transactions); + assert(tw.randomize()); + tw.set_write_cmd(addr,burst_i,ID,len,size_i); + tw.set_cache(cache); + tw.set_lock(lock_i); + tw.set_prot(prot); + for(i = 0; i < (len+1); i = i+1) begin + for(j = 0; j < (2**siz); j = j+1) begin + new_data[j*8+:8] = data[7:0]; + new_strb[j*1+:1] = 1'b1; + data = data >> 8; + // $display(" addr %0h i %0d J %0d data %0h new_strb %0d axi_mgp_data_width %0d",addr,i,j,data,new_strb[j*1+:1],axi_mgp_data_width); + end + tw.set_data_beat(i, new_data); + tw.set_strb_beat(i, new_strb); + // $display(" addr %0h i %0d J %0d new_data %0h new_strb %0d ",addr,i,j,new_data,new_strb); + end + mst.wr_driver.send(tw); + end + join + mst.monitor.item_collected_port.get(tw_m); + response = tw_m.bresp; + end else begin + // $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end + endtask + +// task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); +// integer i,j; +// xil_axi_burst_t burst_i; +// xil_axi_size_t size_i; +// xil_axi_lock_t lock_i; +// xil_axi_data_beat new_data; +// xil_axi_strb_beat new_strb; +// +// case (burst) +// 2'b00: burst_i = XIL_AXI_BURST_TYPE_FIXED; +// 2'b01: burst_i = XIL_AXI_BURST_TYPE_INCR; +// 2'b10: burst_i = XIL_AXI_BURST_TYPE_WRAP; +// 2'b11: burst_i = XIL_AXI_BURST_TYPE_RSVD; +// endcase +// case (siz) +// 3'b000: size_i = XIL_AXI_SIZE_1BYTE; +// 3'b001: size_i = XIL_AXI_SIZE_2BYTE; +// 3'b010: size_i = XIL_AXI_SIZE_4BYTE; +// 3'b011: size_i = XIL_AXI_SIZE_8BYTE; +// 3'b100: size_i = XIL_AXI_SIZE_16BYTE; +// 3'b101: size_i = XIL_AXI_SIZE_32BYTE; +// 3'b110: size_i = XIL_AXI_SIZE_64BYTE; +// 3'b111: size_i = XIL_AXI_SIZE_128BYTE; +// endcase +// case (lck) +// 2'b00: lock_i = XIL_AXI_ALOCK_NOLOCK; +// 2'b01: lock_i = XIL_AXI_ALOCK_EXCL; +// 2'b10: lock_i = XIL_AXI_ALOCK_LOCKED; +// 2'b11: lock_i = XIL_AXI_ALOCK_RSVD; +// endcase +// if(enable_this_port)begin +// fork +// begin +// bready_gen = mst.wr_driver.create_ready("bready"); +// bready_gen.set_ready_policy(XIL_AXI_READY_GEN_OSC); +// bready_gen.set_high_time(1); +// mst.wr_driver.send_bready(bready_gen); +// end +// begin +// tw = mst.wr_driver.create_transaction("write_tran"); +// mst.wr_driver.set_transaction_depth(max_outstanding_transactions); +// assert(tw.randomize()); +// tw.set_write_cmd(addr,burst_i,ID,len,size_i); +// tw.set_cache(cache); +// tw.set_lock(lock_i); +// tw.set_prot(prot); +// for(i = 0; i < (len+1); i = i+1) begin +// for(j = 0; j < (2**siz); j = j+1) begin +// new_data[j*8+:8] = data[7:0]; +// new_strb[j*1+:1] = 1'b1; +// data = data >> 8; +// end +// tw.set_data_beat(i, new_data); +// tw.set_strb_beat(i, new_strb); +// end +// mst.wr_driver.send(tw); +// end +// join +// mst.monitor.item_collected_port.get(tw_m); +// response = tw_m.bresp; +// end else begin +// $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst' will not be executed...",$time, DISP_ERR, master_name); +// if(STOP_ON_ERROR) $stop; +// end +// endtask + task automatic write_burst_strb(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [((axi_burst_len*data_bus_width))-1:0] data,input strb_en,input [((axi_burst_len*data_bus_width)/8)-1:0] strb,input integer datasize, output [axi_rsp_width-1:0] response); + integer i,j; + xil_axi_burst_t burst_i; + xil_axi_size_t size_i; + xil_axi_lock_t lock_i; + xil_axi_data_beat new_data; + xil_axi_strb_beat new_strb; + reg[11:0] ID1; + + // $display(" write_burst_strb addr %0h trnsfr_lngth %0d siz %0d burst %0d wr_data %0h strb %0h",addr,len,siz,burst,data,strb); + case (burst) + 2'b00: burst_i = XIL_AXI_BURST_TYPE_FIXED; + 2'b01: burst_i = XIL_AXI_BURST_TYPE_INCR; + 2'b10: burst_i = XIL_AXI_BURST_TYPE_WRAP; + 2'b11: burst_i = XIL_AXI_BURST_TYPE_RSVD; + endcase + case (siz) + 3'b000: size_i = XIL_AXI_SIZE_1BYTE; + 3'b001: size_i = XIL_AXI_SIZE_2BYTE; + 3'b010: size_i = XIL_AXI_SIZE_4BYTE; + 3'b011: size_i = XIL_AXI_SIZE_8BYTE; + 3'b100: size_i = XIL_AXI_SIZE_16BYTE; + 3'b101: size_i = XIL_AXI_SIZE_32BYTE; + 3'b110: size_i = XIL_AXI_SIZE_64BYTE; + 3'b111: size_i = XIL_AXI_SIZE_128BYTE; + endcase + case (lck) + 2'b00: lock_i = XIL_AXI_ALOCK_NOLOCK; + 2'b01: lock_i = XIL_AXI_ALOCK_EXCL; + 2'b10: lock_i = XIL_AXI_ALOCK_LOCKED; + 2'b11: lock_i = XIL_AXI_ALOCK_RSVD; + endcase + if(enable_this_port)begin + fork + begin + bready_gen = mst.wr_driver.create_ready("bready"); + bready_gen.set_ready_policy(XIL_AXI_READY_GEN_OSC); + // bready_gen.set_high_time(1); + mst.wr_driver.send_bready(bready_gen); + end + begin + tw = mst.wr_driver.create_transaction("write_tran"); + mst.wr_driver.set_transaction_depth(max_outstanding_transactions); + assert(tw.randomize()); + ID1= $urandom(); + if(DEBUG_INFO) + $display($time,"ID1 in strb task is %0h",ID1); + tw.set_write_cmd(addr,burst_i,ID1,len,size_i); + tw.set_cache(cache); + tw.set_lock(lock_i); + tw.set_prot(prot); + if(strb_en == 0) begin + for(i = 0; i < (len+1); i = i+1) begin + for(j = 0; j < (2**siz); j = j+1) begin + new_data[j*8+:8] = data[7:0]; + new_strb[j*1+:1] = 1'b1; + data = data >> 8; + end + tw.set_data_beat(i, new_data); + tw.set_strb_beat(i, new_strb); + end + end + else begin + for(i = 0; i < (len+1); i = i+1) begin + for(j = 0; j < (2**siz); j = j+1) begin + new_data[j*8+:8] = data[7:0]; + new_strb[j*1+:1] = strb[0]; + data = data >> 8; + strb = strb >> 1; + end + tw.set_data_beat(i, new_data); + tw.set_strb_beat(i, new_strb); + // $display(" write_burst_strb new_data %0h new_strb %0h ",new_data,new_strb); + end + end + mst.wr_driver.send(tw); + end + join + mst.monitor.item_collected_port.get(tw_m); + response = tw_m.bresp; + end else begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_strb' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end + endtask + + task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_burst_len*data_bus_width)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + integer i; + if(enable_this_port)begin + write_burst(addr,len,siz,burst,lck,cache,prot,data,datasize,response); + end else begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_concurrent' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end + endtask + +// task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); +// integer i; +// if(enable_this_port)begin +// write_burst(addr,len,siz,burst,lck,cache,prot,data,datasize,response); +// end else begin +// $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_concurrent' will not be executed...",$time, DISP_ERR, master_name); +// if(STOP_ON_ERROR) $stop; +// end +// endtask + + /* Write data from file */ + task automatic write_from_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] wr_size; + output [axi_rsp_width-1:0] response; + reg [axi_rsp_width-1:0] wresp,rwrsp; + reg [addr_width-1:0] addr; + reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data; + integer bytes; + integer trnsfr_bytes; + integer wr_fd; + integer succ; + integer trnsfr_lngth; + reg concurrent; + integer i; + int siz_in_bytes; + + reg [id_bus_width-1:0] wr_id; + reg [axi_size_width-1:0] siz; + reg [axi_brst_type_width-1:0] burst; + reg [axi_lock_width-1:0] lck; + reg [axi_cache_width-1:0] cache; + reg [axi_prot_width-1:0] prot; + begin + if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_from_file' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end else begin + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + + addr = start_addr; + bytes = wr_size; + wresp = 0; + concurrent = $random; + if(bytes > (axi_burst_len * data_bus_width/8)) begin + trnsfr_bytes = (axi_burst_len * data_bus_width/8); + trnsfr_lngth = axi_burst_len-1; + siz_in_bytes = (data_bus_width/8); + end else begin + trnsfr_bytes = bytes; + end + + if(bytes > (axi_burst_len * data_bus_width/8)) begin + trnsfr_lngth = axi_burst_len-1; + end else if(bytes%(data_bus_width/8) == 0) begin + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + siz_in_bytes = (data_bus_width/8); + end else begin + trnsfr_lngth = bytes/(data_bus_width/8); + siz_in_bytes = (data_bus_width/8); + end + + wr_id = ID; + wr_fd = $fopen(file_name,"r"); + + while (bytes > 0) begin + case(siz_in_bytes) + 1 : siz = 0; + 2 : siz = 1; + 4 : siz = 2; + 8 : siz = 3; + 16 : siz = 4; + 32 : siz = 5; + 64 : siz = 6; + 128 : siz = 7; + endcase + + repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction + wr_data = wr_data >> data_bus_width; + succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) .. + end + write_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp); + bytes = bytes - trnsfr_bytes; + addr = addr + trnsfr_bytes; + if(bytes >= (axi_burst_len * data_bus_width/8) ) + trnsfr_bytes = (axi_burst_len * data_bus_width/8); // + else + trnsfr_bytes = bytes; + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + wresp = wresp | rwrsp; + end /// while + response = wresp; + end + end + endtask + +// /* Write data from file */ +// task automatic write_from_file; +// input [(max_chars*8)-1:0] file_name; +// input [addr_width-1:0] start_addr; +// input [int_width-1:0] wr_size; +// output [axi_rsp_width-1:0] response; +// reg [axi_rsp_width-1:0] wresp,rwrsp; +// reg [addr_width-1:0] addr; +// reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data; +// integer bytes; +// integer trnsfr_bytes; +// integer wr_fd; +// integer succ; +// integer trnsfr_lngth; +// reg concurrent; +// integer i; +// +// reg [id_bus_width-1:0] wr_id; +// reg [axi_size_width-1:0] siz; +// reg [axi_brst_type_width-1:0] burst; +// reg [axi_lock_width-1:0] lck; +// reg [axi_cache_width-1:0] cache; +// reg [axi_prot_width-1:0] prot; +// begin +// if(!enable_this_port) begin +// $display("[%0d] : %0s : %0s : Port is disabled. 'write_from_file' will not be executed...",$time, DISP_ERR, master_name); +// if(STOP_ON_ERROR) $stop; +// end else begin +// siz = 2; +// burst = 1; +// lck = 0; +// cache = 0; +// prot = 0; +// +// addr = start_addr; +// bytes = wr_size; +// wresp = 0; +// concurrent = $random; +// if(bytes > (axi_burst_len * data_bus_width/8)) +// trnsfr_bytes = (axi_burst_len * data_bus_width/8); +// else +// trnsfr_bytes = bytes; +// +// if(bytes > (axi_burst_len * data_bus_width/8)) +// trnsfr_lngth = axi_burst_len-1; +// else if(bytes%(data_bus_width/8) == 0) +// trnsfr_lngth = bytes/(data_bus_width/8) - 1; +// else +// trnsfr_lngth = bytes/(data_bus_width/8); +// +// wr_id = ID; +// wr_fd = $fopen(file_name,"r"); +// +// while (bytes > 0) begin +// repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction +// wr_data = wr_data >> data_bus_width; +// succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) .. +// end +// write_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp); +// bytes = bytes - trnsfr_bytes; +// addr = addr + trnsfr_bytes; +// if(bytes >= (axi_burst_len * data_bus_width/8) ) +// trnsfr_bytes = (axi_burst_len * data_bus_width/8); // +// else +// trnsfr_bytes = bytes; +// +// if(bytes > (axi_burst_len * data_bus_width/8)) +// trnsfr_lngth = axi_burst_len-1; +// else if(bytes%(data_bus_width/8) == 0) +// trnsfr_lngth = bytes/(data_bus_width/8) - 1; +// else +// trnsfr_lngth = bytes/(data_bus_width/8); +// +// wresp = wresp | rwrsp; +// end /// while +// response = wresp; +// end +// end +// endtask + +/* Read data to file */ + task automatic read_to_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] rd_size; + output [axi_rsp_width-1:0] response; + reg [axi_rsp_width-1:0] rresp, rrrsp; + reg [addr_width-1:0] addr; + integer bytes; + integer trnsfr_lngth; + reg [(axi_burst_len*data_bus_width)-1 :0] rd_data; + integer rd_fd; + reg [id_bus_width-1:0] rd_id; + + reg [axi_size_width-1:0] siz; + int siz_in_bytes; + reg [axi_brst_type_width-1:0] burst; + reg [axi_lock_width-1:0] lck; + reg [axi_cache_width-1:0] cache; + reg [axi_prot_width-1:0] prot; + begin + if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'read_to_file' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end else begin + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + + addr = start_addr; + rresp = 0; + bytes = rd_size; + + rd_id = ID; + + if(bytes > (axi_burst_len * data_bus_width/8)) begin + trnsfr_lngth = axi_burst_len-1; + siz_in_bytes = (data_bus_width/8); + end + else if(bytes%(data_bus_width/8) == 0) begin + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + siz_in_bytes = (data_bus_width/8); + end + else begin + trnsfr_lngth = bytes/(data_bus_width/8); + siz_in_bytes = (data_bus_width/8); + end + + rd_fd = $fopen(file_name,"w"); + + while (bytes > 0) begin + case(siz_in_bytes) + 1 : siz = 0; + 2 : siz = 1; + 4 : siz = 2; + 8 : siz = 3; + 16 : siz = 4; + 32 : siz = 5; + 64 : siz = 6; + 128 : siz = 7; + endcase + read_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp); + repeat(trnsfr_lngth+1) begin + $fdisplayh(rd_fd,rd_data[data_bus_width-1:0]); + rd_data = rd_data >> data_bus_width; + end + + addr = addr + (trnsfr_lngth+1)*4; + + if(bytes >= (axi_burst_len * data_bus_width/8) ) + bytes = bytes - (axi_burst_len * data_bus_width/8); // + else + bytes = 0; + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + rresp = rresp | rrrsp; + end /// while + response = rresp; + end + end + endtask + +// task automatic read_to_file; +// input [(max_chars*8)-1:0] file_name; +// input [addr_width-1:0] start_addr; +// input [int_width-1:0] rd_size; +// output [axi_rsp_width-1:0] response; +// reg [axi_rsp_width-1:0] rresp, rrrsp; +// reg [addr_width-1:0] addr; +// integer bytes; +// integer trnsfr_lngth; +// reg [(axi_burst_len*data_bus_width)-1 :0] rd_data; +// integer rd_fd; +// reg [id_bus_width-1:0] rd_id; +// +// reg [axi_size_width-1:0] siz; +// reg [axi_brst_type_width-1:0] burst; +// reg [axi_lock_width-1:0] lck; +// reg [axi_cache_width-1:0] cache; +// reg [axi_prot_width-1:0] prot; +// begin +// if(!enable_this_port) begin +// $display("[%0d] : %0s : %0s : Port is disabled. 'read_to_file' will not be executed...",$time, DISP_ERR, master_name); +// if(STOP_ON_ERROR) $stop; +// end else begin +// siz = 2; +// burst = 1; +// lck = 0; +// cache = 0; +// prot = 0; +// +// addr = start_addr; +// rresp = 0; +// bytes = rd_size; +// +// rd_id = ID; +// +// if(bytes > (axi_burst_len * data_bus_width/8)) +// trnsfr_lngth = axi_burst_len-1; +// else if(bytes%(data_bus_width/8) == 0) +// trnsfr_lngth = bytes/(data_bus_width/8) - 1; +// else +// trnsfr_lngth = bytes/(data_bus_width/8); +// +// rd_fd = $fopen(file_name,"w"); +// +// while (bytes > 0) begin +// read_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp); +// repeat(trnsfr_lngth+1) begin +// $fdisplayh(rd_fd,rd_data[data_bus_width-1:0]); +// rd_data = rd_data >> data_bus_width; +// end +// +// addr = addr + (trnsfr_lngth+1)*4; +// +// if(bytes >= (axi_burst_len * data_bus_width/8) ) +// bytes = bytes - (axi_burst_len * data_bus_width/8); // +// else +// bytes = 0; +// +// if(bytes > (axi_burst_len * data_bus_width/8)) +// trnsfr_lngth = axi_burst_len-1; +// else if(bytes%(data_bus_width/8) == 0) +// trnsfr_lngth = bytes/(data_bus_width/8) - 1; +// else +// trnsfr_lngth = bytes/(data_bus_width/8); +// +// rresp = rresp | rrrsp; +// end /// while +// response = rresp; +// end +// end +// endtask + +/* Write data (used for transfer size <= 128 Bytes */ + task automatic write_data; + input [addr_width-1:0] start_addr; + input [max_transfer_bytes_width:0] wr_size; + input [((axi_burst_len*data_bus_width))-1:0] w_data; + output [axi_rsp_width-1:0] response; + reg [axi_rsp_width-1:0] wresp,rwrsp; + reg [addr_width-1:0] addr; + reg [addr_width-1:0] mask_addr; + reg [7:0] bytes,tmp_bytes; + reg[127:0] strb; + // reg [max_transfer_bytes_width*8:0] wr_strb; + reg [((axi_burst_len*data_bus_width)/8):0] wr_strb; + integer trnsfr_bytes,strb_cnt; + reg [((axi_burst_len*data_bus_width))-1:0] wr_data; + integer trnsfr_lngth; + reg concurrent; + + reg [id_bus_width-1:0] wr_id; + reg [axi_size_width-1:0] siz; + int siz_in_bytes,j; + reg [axi_brst_type_width-1:0] burst; + reg [axi_lock_width-1:0] lck; + reg [axi_cache_width-1:0] cache; + reg [axi_prot_width-1:0] prot; + reg[11:0] ID_tmp; + + + integer pad_bytes; + begin + if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_data' will not be executed...",$time, DISP_ERR, master_name); + //==if(STOP_ON_ERROR) $stop; + if(STOP_ON_ERROR) $finish; + end else begin + addr = start_addr; + bytes = wr_size; + wresp = 0; + wr_data = w_data; + concurrent = $random; + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + wr_strb = 0; + pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; + ID_tmp = $urandom(); + //== wr_id = ID; + wr_id = ID_tmp; + if(DEBUG_INFO) + $display("wr_id called with wr_size %0h ",wr_id); + // $display("outside pad_bytes %0d ",pad_bytes); + if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address + trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = axi_burst_len-1; + siz_in_bytes = (data_bus_width/8); + // $display("0 pad_bytes %0d ",pad_bytes); + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) begin + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + siz_in_bytes = (data_bus_width/8); + // $display("1 pad_bytes %0d ",pad_bytes); + end else begin + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + siz_in_bytes = (data_bus_width/8); + // $display("2 pad_bytes %0d ",pad_bytes); + end + end + + if(bytes > siz_in_bytes) begin + strb_cnt = ((bytes/siz_in_bytes)*siz_in_bytes) + (bytes%siz_in_bytes); + // $display("strb_cnt %0d (bytes/siz_in_bytes) %0d (bytes) %0d",strb_cnt,bytes/siz_in_bytes,bytes%siz_in_bytes); + end begin + strb_cnt = bytes ; + // $display("strb_cnt %0d max_transfer_bytes_width %0d",strb_cnt,max_transfer_bytes_width); + end + + while (bytes > 0) begin + case(siz_in_bytes) + 1 : siz = 0; + 2 : siz = 1; + 4 : siz = 2; + 8 : siz = 3; + 16 : siz = 4; + 32 : siz = 5; + 64 : siz = 6; + 128 : siz = 7; + endcase + // $display("bytes %0d",bytes); + // $display("addr %0h trnsfr_lngth %0d siz %0d burst %0d wr_data %0h trnsfr_bytes %0d siz_in_bytes %0d ",addr,trnsfr_lngth,siz,burst,wr_data,trnsfr_bytes,siz_in_bytes); + mask_addr = addr[27:0] & (~(1 << siz)); + // $display("mask_addr %0h addr %0h (~(1 << siz)) %0h ((1 << siz)) %0h size %0d ",mask_addr,addr,(~(1 << siz)), ((1 << siz)),siz); + if(pad_bytes != 0) begin + wr_data = (wr_data << (mask_addr[3:0]*8) ); + // $display(" pading bytes wr_data %0h ",wr_data); + end else begin + wr_data = wr_data; + // $display(" non pading bytes wr_data %0h ",wr_data); + end + + // $display("wr_data %0h",wr_data); + for(j=0;j> (trnsfr_bytes*8); + // $display("wr_data %0h",wr_data); + // $display("trnsfr_bytes %0d",trnsfr_bytes); + bytes = bytes - trnsfr_bytes; + addr = addr + trnsfr_bytes; + // $display("addr %0d",addr); + if(bytes > (axi_burst_len * data_bus_width/8)) begin + trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = axi_burst_len-1; + pad_bytes = 0; + // $display("trnsfr_lngth %0d pad_bytes %0d",trnsfr_lngth,pad_bytes); + end else begin + trnsfr_bytes = bytes; + // $display(" 1 trnsfr_bytes %0d",trnsfr_bytes); + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) begin + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + // $display("2 trnsfr_lngth %0d",trnsfr_lngth); + end else begin + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + pad_bytes = 0; + // $display("3 trnsfr_lngth %0d pad_bytes %0d",trnsfr_lngth,pad_bytes); + end + end + wresp = wresp | rwrsp; + end /// while + response = wresp; + end + end + endtask + +// task automatic write_data; +// input [addr_width-1:0] start_addr; +// input [max_transfer_bytes_width:0] wr_size; +// input [(max_transfer_bytes*8)-1:0] w_data; +// output [axi_rsp_width-1:0] response; +// reg [axi_rsp_width-1:0] wresp,rwrsp; +// reg [addr_width-1:0] addr; +// reg [7:0] bytes,tmp_bytes; +// integer trnsfr_bytes; +// reg [(max_transfer_bytes*8)-1:0] wr_data; +// integer trnsfr_lngth; +// reg concurrent; +// +// reg [id_bus_width-1:0] wr_id; +// reg [axi_size_width-1:0] siz; +// reg [axi_brst_type_width-1:0] burst; +// reg [axi_lock_width-1:0] lck; +// reg [axi_cache_width-1:0] cache; +// reg [axi_prot_width-1:0] prot; +// +// integer pad_bytes; +// begin +// if(!enable_this_port) begin +// $display("[%0d] : %0s : %0s : Port is disabled. 'write_data' will not be executed...",$time, DISP_ERR, master_name); +// if(STOP_ON_ERROR) $stop; +// end else begin +// addr = start_addr; +// bytes = wr_size; +// wresp = 0; +// wr_data = w_data; +// concurrent = $random; +// siz = 2; +// burst = 1; +// lck = 0; +// cache = 0; +// prot = 0; +// pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; +// wr_id = ID; +// if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address +// trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0]; +// trnsfr_lngth = axi_burst_len-1; +// end else begin +// trnsfr_bytes = bytes; +// tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; +// if(tmp_bytes%(data_bus_width/8) == 0) +// trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; +// else +// trnsfr_lngth = tmp_bytes/(data_bus_width/8); +// end +// +// while (bytes > 0) begin +// write_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp); +// wr_data = wr_data >> (trnsfr_bytes*8); +// bytes = bytes - trnsfr_bytes; +// addr = addr + trnsfr_bytes; +// if(bytes > (axi_burst_len * data_bus_width/8)) begin +// trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; +// trnsfr_lngth = axi_burst_len-1; +// end else begin +// trnsfr_bytes = bytes; +// tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; +// if(tmp_bytes%(data_bus_width/8) == 0) +// trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; +// else +// trnsfr_lngth = tmp_bytes/(data_bus_width/8); +// end +// wresp = wresp | rwrsp; +// end /// while +// response = wresp; +// end +// end +// endtask + +/* Read data (used for transfer size <= 128 Bytes */ + task automatic read_data; + input [addr_width-1:0] start_addr; + input [max_transfer_bytes_width:0] rd_size; + // output [(axi_burst_len*data_bus_width)-1:0] r_data; + output [(max_transfer_bytes*8)-1:0] r_data; + output [axi_rsp_width-1:0] response; + reg [axi_rsp_width-1:0] rresp,rdrsp; + reg [addr_width-1:0] addr; + reg [max_transfer_bytes_width:0] bytes,tmp_bytes; + integer trnsfr_bytes; + // reg [(axi_burst_len*data_bus_width)-1:0] rd_data; + reg [(max_transfer_bytes*8)-1:0] rd_data; + reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data; + integer total_rcvd_bytes; + integer trnsfr_lngth; + integer i; + reg [id_bus_width-1:0] rd_id; + + reg [axi_size_width-1:0] siz; + int siz_in_bytes; + reg [axi_brst_type_width-1:0] burst; + reg [axi_lock_width-1:0] lck; + reg [axi_cache_width-1:0] cache; + reg [axi_prot_width-1:0] prot; + + integer pad_bytes; + + begin + if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'read_data' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end else begin + addr = start_addr; + bytes = rd_size; + rresp = 0; + total_rcvd_bytes = 0; + rd_data = 0; + rd_id = ID; + + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; + + if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address + trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = axi_burst_len-1; + siz_in_bytes = (data_bus_width/8); + // $display("0 pad_bytes %0d ",pad_bytes); + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) begin + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + siz_in_bytes = (data_bus_width/8); + // $display("1 pad_bytes %0d ",pad_bytes); + end + else begin + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + siz_in_bytes = (data_bus_width/8); + // $display("2 pad_bytes %0d ",pad_bytes); + end + end + while (bytes > 0) begin + case(siz_in_bytes) + 1 : siz = 0; + 2 : siz = 1; + 4 : siz = 2; + 8 : siz = 3; + 16 : siz = 4; + 32 : siz = 5; + 64 : siz = 6; + 128 : siz = 7; + endcase + read_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp); + //$display(" axi_master read_data rcv_rd_data %0h rdrsp %0h",rcv_rd_data, rdrsp); + for(i = 0; i < trnsfr_bytes; i = i+1) begin + rd_data = rd_data >> 8; + rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0]; + rcv_rd_data = rcv_rd_data >> 8; + total_rcvd_bytes = total_rcvd_bytes+1; + //$display(" axi_master read_data rcv_rd_data %0h rd_data %0h total_rcvd_bytes %0d",rcv_rd_data, rd_data,total_rcvd_bytes); + // $display(" axi_master max_transfer_bytes %0d",max_transfer_bytes); + end + bytes = bytes - trnsfr_bytes; + addr = addr + trnsfr_bytes; + if(bytes > (axi_burst_len * data_bus_width/8)) begin + trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = 15; + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + end + rresp = rresp | rdrsp; + end /// while + rd_data = rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8; + r_data = rd_data; + //$display(" afi_master read_data r_data %0h",r_data); + response = rresp; + end + end + endtask + +// task automatic read_data; +// input [addr_width-1:0] start_addr; +// input [max_transfer_bytes_width:0] rd_size; +// output [(max_transfer_bytes*8)-1:0] r_data; +// output [axi_rsp_width-1:0] response; +// reg [axi_rsp_width-1:0] rresp,rdrsp; +// reg [addr_width-1:0] addr; +// reg [max_transfer_bytes_width:0] bytes,tmp_bytes; +// integer trnsfr_bytes; +// reg [(max_transfer_bytes*8)-1 : 0] rd_data; +// reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data; +// integer total_rcvd_bytes; +// integer trnsfr_lngth; +// integer i; +// reg [id_bus_width-1:0] rd_id; +// +// reg [axi_size_width-1:0] siz; +// reg [axi_brst_type_width-1:0] burst; +// reg [axi_lock_width-1:0] lck; +// reg [axi_cache_width-1:0] cache; +// reg [axi_prot_width-1:0] prot; +// +// integer pad_bytes; +// +// begin +// if(!enable_this_port) begin +// $display("[%0d] : %0s : %0s : Port is disabled. 'read_data' will not be executed...",$time, DISP_ERR, master_name); +// if(STOP_ON_ERROR) $stop; +// end else begin +// addr = start_addr; +// bytes = rd_size; +// rresp = 0; +// total_rcvd_bytes = 0; +// rd_data = 0; +// rd_id = ID; +// +// siz = 2; +// burst = 1; +// lck = 0; +// cache = 0; +// prot = 0; +// pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; +// +// if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address +// trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; +// trnsfr_lngth = axi_burst_len-1; +// end else begin +// trnsfr_bytes = bytes; +// tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; +// if(tmp_bytes%(data_bus_width/8) == 0) +// trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; +// else +// trnsfr_lngth = tmp_bytes/(data_bus_width/8); +// end +// while (bytes > 0) begin +// read_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp); +// for(i = 0; i < trnsfr_bytes; i = i+1) begin +// rd_data = rd_data >> 8; +// rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0]; +// rcv_rd_data = rcv_rd_data >> 8; +// total_rcvd_bytes = total_rcvd_bytes+1; +// end +// bytes = bytes - trnsfr_bytes; +// addr = addr + trnsfr_bytes; +// if(bytes > (axi_burst_len * data_bus_width/8)) begin +// trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; +// trnsfr_lngth = 15; +// end else begin +// trnsfr_bytes = bytes; +// tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; +// if(tmp_bytes%(data_bus_width/8) == 0) +// trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; +// else +// trnsfr_lngth = tmp_bytes/(data_bus_width/8); +// end +// rresp = rresp | rdrsp; +// end /// while +// rd_data = rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8; +// r_data = rd_data; +// response = rresp; +// end +// end +// endtask + + +/* Wait Register Update in PL */ +/* Issue a series of 1 burst length reads until the expected data pattern is received */ + +task automatic wait_reg_update; +input [addr_width-1:0] addri; +input [data_width-1:0] datai; +input [data_width-1:0] maski; +input [int_width-1:0] time_interval; +input [int_width-1:0] time_out; +output [data_width-1:0] data_o; +output upd_done; + +reg [addr_width-1:0] addr; +reg [data_width-1:0] data_i; +reg [data_width-1:0] mask_i; +integer time_int; +integer timeout; + +reg [axi_rsp_width-1:0] rdrsp; +reg [id_bus_width-1:0] rd_id; +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; +reg [data_width-1:0] rcv_data; +integer trnsfr_lngth; +reg rd_loop; +reg timed_out; +integer i; +integer cycle_cnt; + +begin +addr = addri; +data_i = datai; +mask_i = maski; +time_int = time_interval; +timeout = time_out; +timed_out = 0; +cycle_cnt = 0; + +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'wait_reg_update' will not be executed...",$time, DISP_ERR, master_name); + upd_done = 0; + if(STOP_ON_ERROR) $stop; +end else begin + rd_id = ID; + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + trnsfr_lngth = 0; + rd_loop = 1; + fork + begin + while(!timed_out & rd_loop) begin + cycle_cnt = cycle_cnt + 1; + if(cycle_cnt >= timeout) timed_out = 1; + @(posedge M_ACLK); + end + end + begin + while (rd_loop) begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) ",$time, master_name, DISP_INFO, addr); + read_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp); + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reading Register returned (0x%0h) ",$time, master_name, DISP_INFO, rcv_data); + if(((rcv_data & ~mask_i) === (data_i & ~mask_i)) | timed_out) + rd_loop = 0; + else + repeat(time_int) @(posedge M_ACLK); + end /// while + end + join + data_o = rcv_data & ~mask_i; + if(timed_out) begin + $display("[%0d] : %0s : %0s : 'wait_reg_update' timed out ... Register is not updated ",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end else + upd_done = 1; +end +end +endtask + + /* Set verbosity to be used */ + task automatic set_verbosity; + input[31:0] verb; + begin + if(enable_this_port) begin + mst.set_verbosity(verb); + end else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, master_name); + end + + end + endtask + +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16_afi_slave.v + * + * Date : 2012-11 + * + * Description : Model that acts as AFI port interface. It uses AXI3 Slave VIP + * from xilinx. + *****************************************************************************/ + `timescale 1ns/1ps + +import axi_vip_pkg::*; + +module processing_system7_vip_v1_0_16_afi_slave ( + S_RESETN, + + S_ARREADY, + S_AWREADY, + S_BVALID, + S_RLAST, + S_RVALID, + S_WREADY, + S_BRESP, + S_RRESP, + S_RDATA, + S_BID, + S_RID, + S_ACLK, + S_ARVALID, + S_AWVALID, + S_BREADY, + S_RREADY, + S_WLAST, + S_WVALID, + S_ARBURST, + S_ARLOCK, + S_ARSIZE, + S_AWBURST, + S_AWLOCK, + S_AWSIZE, + S_ARPROT, + S_AWPROT, + S_ARADDR, + S_AWADDR, + S_WDATA, + S_ARCACHE, + S_ARLEN, + S_AWCACHE, + S_AWLEN, + S_WSTRB, + S_ARID, + S_AWID, + S_WID, + + S_AWQOS, + S_ARQOS, + + SW_CLK, + WR_DATA_ACK_OCM, + WR_DATA_ACK_DDR, + WR_ADDR, + WR_DATA, + WR_BYTES, + WR_DATA_STRB, + WR_DATA_VALID_OCM, + WR_DATA_VALID_DDR, + WR_QOS, + + RD_REQ_DDR, + RD_REQ_OCM, + RD_ADDR, + RD_DATA_OCM, + RD_DATA_DDR, + RD_BYTES, + RD_QOS, + RD_DATA_VALID_OCM, + RD_DATA_VALID_DDR, + S_RDISSUECAP1_EN, + S_WRISSUECAP1_EN, + S_RCOUNT, + S_WCOUNT, + S_RACOUNT, + S_WACOUNT + +); + parameter enable_this_port = 0; + parameter slave_name = "Slave"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter slave_base_address = 0; + parameter slave_high_address = 4; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + parameter max_wr_outstanding_transactions = 8; + parameter max_rd_outstanding_transactions = 8; + + `include "processing_system7_vip_v1_0_16_local_params.v" + + /* Local parameters only for this module */ + /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles. + This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. + 1-bit extra width than the no.of.bits needed to represent the outstanding transactions + Extra bit helps in generating the empty and full flags + */ + parameter int_cntr_width = clogb2(max_outstanding_transactions)+1; + parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1); + parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1); + + /* RESP data */ + parameter wr_afi_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1); + + parameter wr_bytes_lsb = 0; + parameter wr_bytes_msb = max_burst_bytes_width; + parameter wr_addr_lsb = wr_bytes_msb + 1; + parameter wr_addr_msb = wr_addr_lsb + addr_width-1; + parameter wr_data_lsb = wr_addr_msb + 1; + parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1; + parameter wr_afi_bytes_lsb = 0; + parameter wr_afi_bytes_msb = max_burst_bytes_width; + parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1; + parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1; + parameter wr_afi_data_lsb = wr_afi_addr_msb + 1; + parameter wr_afi_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1; + parameter wr_afi_rsp_lsb = axi_rsp_width-1; + parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1; + parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1; + parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1; + parameter wr_afi_ln_lsb = wr_afi_id_msb + 1; + parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1; + parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1; + parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1; + + parameter wr_qos_lsb = wr_data_msb + 1; + parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; + parameter wr_strb_lsb = wr_qos_msb + 1; + parameter wr_strb_msb = wr_strb_lsb + ((data_bus_width/8)*axi_burst_len)-1; + + /* RESP data */ + parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; + parameter rsp_lsb = 0; + parameter rsp_msb = axi_rsp_width-1; + parameter rsp_id_lsb = rsp_msb + 1; + parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; + + input S_RESETN; + + output S_ARREADY; + output S_AWREADY; + output S_BVALID; + output S_RLAST; + output S_RVALID; + output S_WREADY; + output [axi_rsp_width-1:0] S_BRESP; + output [axi_rsp_width-1:0] S_RRESP; + output [data_bus_width-1:0] S_RDATA; + output [id_bus_width-1:0] S_BID; + output [id_bus_width-1:0] S_RID; + input S_ACLK; + input S_ARVALID; + input S_AWVALID; + input S_BREADY; + input S_RREADY; + input S_WLAST; + input S_WVALID; + input [axi_brst_type_width-1:0] S_ARBURST; + input [axi_lock_width-1:0] S_ARLOCK; + input [axi_size_width-1:0] S_ARSIZE; + input [axi_brst_type_width-1:0] S_AWBURST; + input [axi_lock_width-1:0] S_AWLOCK; + input [axi_size_width-1:0] S_AWSIZE; + input [axi_prot_width-1:0] S_ARPROT; + input [axi_prot_width-1:0] S_AWPROT; + input [address_bus_width-1:0] S_ARADDR; + input [address_bus_width-1:0] S_AWADDR; + input [data_bus_width-1:0] S_WDATA; + input [axi_cache_width-1:0] S_ARCACHE; + input [axi_len_width-1:0] S_ARLEN; + + input [axi_qos_width-1:0] S_ARQOS; + + input [axi_cache_width-1:0] S_AWCACHE; + input [axi_len_width-1:0] S_AWLEN; + + input [axi_qos_width-1:0] S_AWQOS; + input [(data_bus_width/8)-1:0] S_WSTRB; + input [id_bus_width-1:0] S_ARID; + input [id_bus_width-1:0] S_AWID; + input [id_bus_width-1:0] S_WID; + + input SW_CLK; + input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; + output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; + output reg [max_burst_bits-1:0] WR_DATA; + output reg [addr_width-1:0] WR_ADDR; + output reg [max_transfer_bytes_width:0] WR_BYTES; + output reg [((data_bus_width/8)*axi_burst_len)-1:0] WR_DATA_STRB; + // output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG; + output reg RD_REQ_OCM, RD_REQ_DDR; + output reg [addr_width-1:0] RD_ADDR; + input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM; + // input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG; + output reg[max_transfer_bytes_width:0] RD_BYTES; + input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR; + // input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG; + output reg [axi_qos_width-1:0] WR_QOS; + output reg [axi_qos_width-1:0] RD_QOS; + + input S_RDISSUECAP1_EN; + input S_WRISSUECAP1_EN; + + output [7:0] S_RCOUNT; + output [7:0] S_WCOUNT; + output [2:0] S_RACOUNT; + output [5:0] S_WACOUNT; + + wire net_ARVALID; + wire net_AWVALID; + wire net_WVALID; + bit [31:0] static_count; + + real s_aclk_period1; + real s_aclk_period2; + real diff_time = 1; + // real s_aclk_period; + + axi_slv_agent #(1,address_bus_width, data_bus_width, data_bus_width, id_bus_width,id_bus_width,0,0,0,0,0,1,1,1,1,0,1,1,1,1,1,1) slv; + + axi_vip_v1_1_14_top #( + .C_AXI_PROTOCOL(1), + .C_AXI_INTERFACE_MODE(2), + .C_AXI_ADDR_WIDTH(address_bus_width), + .C_AXI_WDATA_WIDTH(data_bus_width), + .C_AXI_RDATA_WIDTH(data_bus_width), + .C_AXI_WID_WIDTH(id_bus_width), + .C_AXI_RID_WIDTH(id_bus_width), + .C_AXI_AWUSER_WIDTH(0), + .C_AXI_ARUSER_WIDTH(0), + .C_AXI_WUSER_WIDTH(0), + .C_AXI_RUSER_WIDTH(0), + .C_AXI_BUSER_WIDTH(0), + .C_AXI_SUPPORTS_NARROW(1), + .C_AXI_HAS_BURST(1), + .C_AXI_HAS_LOCK(1), + .C_AXI_HAS_CACHE(1), + .C_AXI_HAS_REGION(0), + .C_AXI_HAS_PROT(1), + .C_AXI_HAS_QOS(1), + .C_AXI_HAS_WSTRB(1), + .C_AXI_HAS_BRESP(1), + .C_AXI_HAS_RRESP(1), + .C_AXI_HAS_ARESETN(1) + ) slave ( + .aclk(S_ACLK), + .aclken(1'B1), + .aresetn(S_RESETN), + .s_axi_awid(S_AWID), + .s_axi_awaddr(S_AWADDR), + .s_axi_awlen(S_AWLEN), + .s_axi_awsize(S_AWSIZE), + .s_axi_awburst(S_AWBURST), + .s_axi_awlock(S_AWLOCK), + .s_axi_awcache(S_AWCACHE), + .s_axi_awprot(S_AWPROT), + .s_axi_awregion(4'B0), + .s_axi_awqos(S_AWQOS), + .s_axi_awuser(1'B0), + .s_axi_awvalid(S_AWVALID), + .s_axi_awready(S_AWREADY), + .s_axi_wid(S_WID), + .s_axi_wdata(S_WDATA), + .s_axi_wstrb(S_WSTRB), + .s_axi_wlast(S_WLAST), + .s_axi_wuser(1'B0), + .s_axi_wvalid(S_WVALID), + .s_axi_wready(S_WREADY), + .s_axi_bid(S_BID), + .s_axi_bresp(S_BRESP), + .s_axi_buser(), + .s_axi_bvalid(S_BVALID), + .s_axi_bready(S_BREADY), + .s_axi_arid(S_ARID), + .s_axi_araddr(S_ARADDR), + .s_axi_arlen(S_ARLEN), + .s_axi_arsize(S_ARSIZE), + .s_axi_arburst(S_ARBURST), + .s_axi_arlock(S_ARLOCK), + .s_axi_arcache(S_ARCACHE), + .s_axi_arprot(S_ARPROT), + .s_axi_arregion(4'B0), + .s_axi_arqos(S_ARQOS), + .s_axi_aruser(1'B0), + .s_axi_arvalid(S_ARVALID), + .s_axi_arready(S_ARREADY), + .s_axi_rid(S_RID), + .s_axi_rdata(S_RDATA), + .s_axi_rresp(S_RRESP), + .s_axi_rlast(S_RLAST), + .s_axi_ruser(), + .s_axi_rvalid(S_RVALID), + .s_axi_rready(S_RREADY), + .m_axi_awid(), + .m_axi_awaddr(), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(), + .m_axi_awready(1'b0), + .m_axi_wid(), + .m_axi_wdata(), + .m_axi_wstrb(), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(), + .m_axi_wready(1'b0), + .m_axi_bid(12'h000), + .m_axi_bresp(2'b00), + .m_axi_buser(1'B0), + .m_axi_bvalid(1'b0), + .m_axi_bready(), + .m_axi_arid(), + .m_axi_araddr(), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(), + .m_axi_arregion(), + .m_axi_arqos(), + .m_axi_aruser(), + .m_axi_arvalid(), + .m_axi_arready(1'b0), + .m_axi_rid(12'h000), + .m_axi_rdata(32'h00000000), + .m_axi_rresp(2'b00), + .m_axi_rlast(1'b0), + .m_axi_ruser(1'B0), + .m_axi_rvalid(1'b0), + .m_axi_rready() + ); + + xil_axi_cmd_beat twc, trc; + xil_axi_write_beat twd; + xil_axi_read_beat trd; + axi_transaction twr, trr,trr_get_rd; + axi_transaction trr_rd[$]; + axi_ready_gen awready_gen; + axi_ready_gen wready_gen; + axi_ready_gen arready_gen; + integer i,j,k,add_val,size_local,burst_local,len_local,num_bytes; + bit [3:0] a; + bit [15:0] a_16_bits,a_new,a_wrap,a_wrt_val,a_cnt; + + initial begin + slv = new("slv",slave.IF); + twr = new("twr"); + trr = new("trr"); + trr_get_rd = new("trr_get_rd"); + wready_gen = slv.wr_driver.create_ready("wready"); + slv.monitor.axi_wr_cmd_port.set_enabled(); + slv.monitor.axi_wr_beat_port.set_enabled(); + slv.monitor.axi_rd_cmd_port.set_enabled(); + // slv.wr_driver.set_transaction_depth(max_outstanding_transactions); + // slv.rd_driver.set_transaction_depth(max_outstanding_transactions); + slv.wr_driver.set_transaction_depth(max_wr_outstanding_transactions); + slv.rd_driver.set_transaction_depth(max_rd_outstanding_transactions); + slv.start_slave(); + end + + initial begin + slave.IF.set_enable_xchecks_to_warn(); + repeat(10) @(posedge S_ACLK); + slave.IF.set_enable_xchecks(); + end + + wire wr_intr_fifo_full; + reg temp_wr_intr_fifo_full; + + /* Interconnect WR_FIFO model instance */ + // processing_system7_vip_v1_0_16_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR); + + /* Register the async 'full' signal to S_ACLK clock */ + always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full; + + /* Latency type and Debug/Error Control */ + reg[1:0] latency_type = RANDOM_CASE; + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1'b1; + + /* Internal nets/regs for calling slave VIP API's*/ + reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1]; + reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; + wire wr_fifo_empty; + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0; + real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received + reg awvalid_flag[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received + + /* Address Write Channel handshake*/ + reg[int_wr_cntr_width-1:0] aw_cnt = 0;// + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1]; + reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1]; + reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1]; + reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1]; + reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1]; + reg aw_flag [0:max_wr_outstanding_transactions-1]; + reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1]; + reg [addr_width-1:0] addr_wr_local; + reg [addr_width-1:0] addr_wr_final; + reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1]; + reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1]; + wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) + + /* internal fifos to store burst write data, ID & strobes*/ + reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1]; + reg [((data_bus_width/8)*axi_burst_len)-1:0] burst_strb [0:max_wr_outstanding_transactions-1]; + reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer + reg [max_burst_bytes_width:0] valid_bytes = 0; /// total valid bytes received in a complete burst transfer + reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received + wire wd_fifo_full; + + /* Write Data Channel and Write Response handshake signals*/ + reg [int_wr_cntr_width-1:0] wd_cnt = 0; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; + reg [((data_bus_width/8)*axi_burst_len)-1:0] aligned_wr_strb; + reg [addr_width-1:0] aligned_wr_addr; + reg [max_burst_bytes_width:0] valid_data_bytes; + reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0; + reg [axi_rsp_width-1:0] bresp; + reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_bresp; + reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0; + integer wr_latency_count; + reg wr_delayed; + wire bresp_fifo_empty; + + /* keep track of count values */ + reg[7:0] wcount; + reg[5:0] wacount; + + /* states for managing read/write to WR_FIFO */ + parameter SEND_DATA = 0, WAIT_ACK = 1; + reg state; + + /* Qos*/ + reg [axi_qos_width-1:0] ar_qos=0, aw_qos=0; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); + end + end + /*--------------------------------------------------------------------------------*/ + +// /* Store the Clock cycle time period */ +// +// always@(S_RESETN) +// begin +// if(S_RESETN) begin +// @(posedge S_ACLK); +// s_aclk_period = $time; +// @(posedge S_ACLK); +// s_aclk_period = $time - s_aclk_period; +// end +// end + /*--------------------------------------------------------------------------------*/ + +//initial slave.set_disable_reset_value_checks(1); + initial begin + repeat(2) @(posedge S_ACLK); + if(!enable_this_port) begin +// slave.set_channel_level_info(0); +// slave.set_function_level_info(0); + end +// slave.RESPONSE_TIMEOUT = 0; + end + /*--------------------------------------------------------------------------------*/ + + /* Set Latency type to be used */ + task set_latency_type; + input[1:0] lat; + begin + if(enable_this_port) + latency_type = lat; + else begin + //if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set verbosity to be used */ + task automatic set_verbosity; + input[31:0] verb; + begin + if(enable_this_port) begin + slv.set_verbosity(verb); + end else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. set_verbosity will not be set...",$time, DISP_WARN, slave_name); + end + + end + endtask + /*--------------------------------------------------------------------------------*/ + + + + /* Set ARQoS to be used */ + task automatic set_arqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) begin + ar_qos = qos; + end else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set AWQoS to be used */ + task set_awqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + aw_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* get the wr latency number */ + function [31:0] get_wr_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : get_wr_lat_number = afi_wr_min; + AVG_CASE : get_wr_lat_number = afi_wr_avg; + WORST_CASE : get_wr_lat_number = afi_wr_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min); + 2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg); + default : get_wr_lat_number = ($random()%60+ afi_wr_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* get the rd latency number */ + function [31:0] get_rd_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : get_rd_lat_number = afi_rd_min; + AVG_CASE : get_rd_lat_number = afi_rd_avg; + WORST_CASE : get_rd_lat_number = afi_rd_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min); + 2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg); + default : get_rd_lat_number = ($random()%60+ afi_rd_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the Clock cycle time period */ + always@(S_RESETN) + begin + if(S_RESETN) begin + diff_time = 1; + @(posedge S_ACLK); + s_aclk_period1 = $realtime; + @(posedge S_ACLK); + s_aclk_period2 = $realtime; + diff_time = s_aclk_period2 - s_aclk_period1; + end + end + /*--------------------------------------------------------------------------------*/ + + + /* Check for any WRITE/READs when this port is disabled */ + always@(S_AWVALID or S_WVALID or S_ARVALID) + begin + if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name); + //$stop; + $finish; + end + end + + /*--------------------------------------------------------------------------------*/ + + assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0; + assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0; + assign net_WVALID = enable_this_port ? S_WVALID : 1'b0; + + assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0; + assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this + assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this + assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0; + assign bresp_fifo_full = ((wr_bresp_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wr_bresp_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1:1'b0; + + assign S_WCOUNT = wcount; + assign S_WACOUNT = wacount; + + // FIFO_STATUS (only if AFI port) 1- full + function automatic wrfifo_full ; + input [axi_len_width:0] fifo_space_exp; + integer fifo_space_left; + begin + fifo_space_left = afi_fifo_locations - wcount; + if(fifo_space_left < fifo_space_exp) + wrfifo_full = 1; + else + wrfifo_full = 0; + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) + aw_time_cnt = 0; + else begin + if(net_AWVALID && S_AWREADY) begin + awvalid_receive_time[aw_time_cnt] = $realtime; + awvalid_flag[aw_time_cnt] = 1'b1; + aw_time_cnt = aw_time_cnt + 1; + if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0; + end + end // else + end /// always + + // always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID ) + // begin + // if(!S_RESETN) + // aw_time_cnt = 0; + // else begin + // if(S_AWVALID) begin + // awvalid_receive_time[aw_time_cnt] = $time; + // awvalid_flag[aw_time_cnt] = 1'b1; + // aw_time_cnt = aw_time_cnt + 1; + // end + // end // else + // end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_AWVALID && S_AWREADY) begin + if(S_AWQOS === 0) begin awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos; + if(DEBUG_INFO) $display(" afi_slave aw_qos %0h aw_cnt[int_wr_cntr_width-2:0] %0d int_wr_cntr_width %0d",aw_qos,aw_cnt[int_wr_cntr_width-2:0],int_wr_cntr_width); + end else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS; + end + end + /*--------------------------------------------------------------------------------*/ + + always@(aw_fifo_full) + begin + if(aw_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions); + end + + /* Address Write Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + aw_cnt = 0; + end else begin + if(!aw_fifo_full) begin + slv.monitor.axi_wr_cmd_port.get(twc); + // awaddr[aw_cnt[int_wr_cntr_width-2:0]] = twc.addr; + awlen[aw_cnt[int_wr_cntr_width-2:0]] = twc.len; + awsize[aw_cnt[int_wr_cntr_width-2:0]] = twc.size; + awbrst[aw_cnt[int_wr_cntr_width-2:0]] = twc.burst; + awlock[aw_cnt[int_wr_cntr_width-2:0]] = twc.lock; + awcache[aw_cnt[int_wr_cntr_width-2:0]]= twc.cache; + awprot[aw_cnt[int_wr_cntr_width-2:0]] = twc.prot; + awid[aw_cnt[int_wr_cntr_width-2:0]] = twc.id; + aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1; + // aw_cnt = aw_cnt + 1; + size_local = twc.size; + burst_local = twc.burst; + len_local = twc.len; + if(burst_local == AXI_INCR || burst_local == AXI_FIXED) begin + if(data_bus_width === 'd128) begin + if(size_local === 'd0) a = {twc.addr[3:0]}; + if(size_local === 'd1) a = {twc.addr[3:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[3:2],2'b0}; + if(size_local === 'd3) a = {twc.addr[3],3'b0}; + if(size_local === 'd4) a = 'b0; + end else if(data_bus_width === 'd64 ) begin + if(size_local === 'd0) a = {twc.addr[2:0]}; + if(size_local === 'd1) a = {twc.addr[2:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[2],2'b0}; + if(size_local === 'd3) a = 'b0; + end else if(data_bus_width === 'd32 ) begin + if(size_local === 'd0) a = {twc.addr[1:0]}; + if(size_local === 'd1) a = {twc.addr[1],1'b0}; + if(size_local === 'd2) a = 'b0; + end + end if(burst_local == AXI_WRAP) begin + if(data_bus_width === 'd128) begin + if(size_local === 'd0) a = {twc.addr[3:0]}; + if(size_local === 'd1) a = {twc.addr[3:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[3:2],2'b0}; + if(size_local === 'd3) a = {twc.addr[3],3'b0}; + if(size_local === 'd4) a = 'b0; + end else if(data_bus_width === 'd64 ) begin + if(size_local === 'd0) a = {twc.addr[2:0]}; + if(size_local === 'd1) a = {twc.addr[2:1],1'b0}; + if(size_local === 'd2) a = {twc.addr[2],2'b0}; + if(size_local === 'd3) a = 'b0; + end else if(data_bus_width === 'd32 ) begin + if(size_local === 'd0) a = {twc.addr[1:0]}; + if(size_local === 'd1) a = {twc.addr[1],1'b0}; + if(size_local === 'd2) a = 'b0; + end + // a = twc.addr[3:0]; + a_16_bits = twc.addr[7:0]; + num_bytes = ((len_local+1)*(2**size_local)); + // $display("num_bytes %0d num_bytes %0h",num_bytes,num_bytes); + end + addr_wr_local = twc.addr; + if(burst_local == AXI_INCR || burst_local == AXI_FIXED) begin + case(size_local) + 0 : addr_wr_final = {addr_wr_local}; + 1 : addr_wr_final = {addr_wr_local[31:1],1'b0}; + 2 : addr_wr_final = {addr_wr_local[31:2],2'b0}; + 3 : addr_wr_final = {addr_wr_local[31:3],3'b0}; + 4 : addr_wr_final = {addr_wr_local[31:4],4'b0}; + 5 : addr_wr_final = {addr_wr_local[31:5],5'b0}; + 6 : addr_wr_final = {addr_wr_local[31:6],6'b0}; + 7 : addr_wr_final = {addr_wr_local[31:7],7'b0}; + endcase + awaddr[aw_cnt[int_wr_cntr_width-2:0]] = addr_wr_final; + // $display("addr_wr_final %0h",addr_wr_final); + end if(burst_local == AXI_WRAP) begin + awaddr[aw_cnt[int_wr_cntr_width-2:0]] = twc.addr; + // $display(" awaddr[aw_cnt[int_wr_cntr_width-2:0]] %0h",awaddr[aw_cnt[int_wr_cntr_width-2:0]]); + end + aw_cnt = aw_cnt + 1; + //== $display($time,"awcnt isssss %0d",aw_cnt); + // if(data_bus_width === 'd32) a = 0; + // if(data_bus_width === 'd64) a = twc.addr[2:0]; + // if(data_bus_width === 'd128) a = twc.addr[3:0]; + // $display("twc.size %0d twc.len %0d twc.addr %0h a value %0h addr_wr_final %0h awaddr[aw_cnt[int_wr_cntr_width-2:0]] %0h",twc.size,twc.len,twc.addr,a,addr_wr_final ,awaddr[aw_cnt[int_wr_cntr_width-2:0]]); + if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1]; + aw_cnt[int_wr_cntr_width-2:0] = 0; + if(DEBUG_INFO) $display($time," In if condition of AFI slave "); + + end + end // if (!aw_fifo_full) + end /// if else + end /// always + +// /*--------------------------------------------------------------------------------*/ +// /* Address Write Channel handshake*/ +// always@(negedge S_RESETN or posedge S_ACLK) +// begin +// if(!S_RESETN) begin +// aw_cnt = 0; +// wacount = 0; +// end else begin +// if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin +// slv.monitor.axi_wr_cmd_port.get(twc); +// awaddr[aw_cnt[int_wr_cntr_width-2:0]] = twc.addr; +// awlen[aw_cnt[int_wr_cntr_width-2:0]] = twc.len; +// awsize[aw_cnt[int_wr_cntr_width-2:0]] = twc.size; +// awbrst[aw_cnt[int_wr_cntr_width-2:0]] = twc.burst; +// awlock[aw_cnt[int_wr_cntr_width-2:0]] = twc.lock; +// awcache[aw_cnt[int_wr_cntr_width-2:0]]= twc.cache; +// awprot[aw_cnt[int_wr_cntr_width-2:0]] = twc.prot; +// awid[aw_cnt[int_wr_cntr_width-2:0]] = twc.id; +// aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1; +// aw_cnt = aw_cnt + 1; +// wacount = wacount + 1; +// end // if (!aw_fifo_full) +// end /// if else +// end /// always +// /*--------------------------------------------------------------------------------*/ + /* Write Data Channel Handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wd_cnt = 0; + end else begin + if(!wd_fifo_full && S_WVALID) begin + slv.monitor.axi_wr_beat_port.get(twd); + wait((aw_flag[wd_cnt[int_wr_cntr_width-2:0]] === 'b1)); + case(size_local) + 0 : add_val = 1; + 1 : add_val = 2; + 2 : add_val = 4; + 3 : add_val = 8; + 4 : add_val = 16; + 5 : add_val = 32; + 6 : add_val = 64; + 7 : add_val = 128; + endcase + + // $display(" size_local %0d add_val %0d wd_cnt %0d",size_local,add_val,wd_cnt); +// $display(" data depth : %0d size %0d srrb %0d last %0d burst %0d ",2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]],twd.get_data_size(),twd.get_strb_size(),twd.last,twc.burst); + //$display(" a value is %0d ",a); + // twd.sprint_c(); + for(i = 0; i < (2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]); i = i+1) begin + burst_data[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8] = twd.data[i+a]; + //$display("data burst %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h twd.data %0h i %0d a %0d full data %0h",burst_data[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8],twd.data[i],twd.data[i+1],twd.data[i+2],twd.data[i+3],twd.data[i+4],twd.data[i+5],twd.data[i+a],i,a,twd.data[i+a]); + //$display(" wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8) %0d wd_cnt %0d valid_bytes %0d int_wr_cntr_width %0d", wd_cnt[int_wr_cntr_width-2:0],wd_cnt,valid_bytes,int_wr_cntr_width); + burst_strb[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes)+(i*1))+:1] = twd.strb[i+a]; + //$display("burst_strb %0h twd_strb %0h int_wr_cntr_width %0d valid_bytes %0d wd_cnt[int_wr_cntr_width-2:0] %0d twd.strb[i+a] %0b full strb %0h",burst_strb[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes)+(i*1))+:1],twd.strb[i],int_wr_cntr_width,valid_bytes,wd_cnt[int_wr_cntr_width-2:0],twd.strb[i+a],twd.strb[i+a]); + //$display("burst_strb %0h twd.strb[i+1] %0h twd.strb[i+2] %0h twd.strb[i+3] %0h twd.strb[i+4] %0h twd.strb[i+5] %0h twd.strb[i+6] %0h twd.strb[i+7] %0h",twd.strb[i],twd.strb[i+1],twd.strb[i+1],twd.strb[i+2],twd.strb[i+3],twd.strb[i+4],twd.strb[i+5],twd.strb[i+6],twd.strb[i+7]); + + if(i == ((2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]])-1) ) begin + if(burst_local == AXI_FIXED) begin + a = a; + end else if(burst_local == AXI_INCR) begin + a = a+add_val; + end else if(burst_local == AXI_WRAP) begin + a_new = (a_16_bits/num_bytes)*num_bytes; + a_wrap = a_new + (num_bytes); + a = a+add_val; + a_cnt = a_cnt+1; + a_16_bits = a_16_bits+add_val; + a_wrt_val = a_16_bits; + //$display(" new a value for wrap a %0h add_val %0d a_wrap %0h a_wrt_val %0h a_new %0h num_bytes %0h a_cnt %0d ",a,add_val,a_wrap[3:0],a_wrt_val,a_new,num_bytes,a_cnt); + if(a_wrt_val[15:0] >= a_wrap[15:0]) begin + if(data_bus_width === 'd128) + a = a_new[3:0]; + else if(data_bus_width === 'd64) + a = a_new[2:0]; + else if(data_bus_width === 'd32) + a = a_new[1:0]; + //$display(" setting up a_wrap %0h a_new %0h a %0h", a_wrap,a_new,a); + end else begin + a = a; + //$display(" setting incr a_wrap %0h a_new %0h a %0h", a_wrap,a_new ,a ); + end + end + //$display(" new a value a %0h add_val %0d",a,add_val); + end + end + if(burst_local == AXI_INCR) begin + if( a >= (data_bus_width/8) || (burst_local == 0 ) || (twd.last) ) begin + // if( (burst_local == 0 ) || (twd.last) ) begin + a = 0; + //$display("resetting a = %0d ",a); + end + end else if (burst_local == AXI_WRAP) begin + if( ((a >= (data_bus_width/8)) ) || (burst_local == 0 ) || (twd.last) ) begin + a = 0; + //$display("resetting a = %0d ",a); + end + end + + valid_bytes = valid_bytes+(2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]); + //$display("afi_slave valid bytes in valid_bytes %0h",valid_bytes); + + if (twd.last === 'b1) begin + wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1; + burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]] = valid_bytes; + valid_bytes = 0; + wd_cnt = wd_cnt + 1; + a = 0; + a_cnt = 0; + // $display(" before match max_wr_outstanding_transactions reached %0d wd_cnt %0d",max_wr_outstanding_transactions,wd_cnt); + if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1]; + wd_cnt[int_wr_cntr_width-2:0] = 0; + // $display(" Now max_wr_outstanding_transactions reached %0d ",max_wr_outstanding_transactions); + end + end + end /// if + end /// else + end /// always + + + /* Align the wrap data for write transaction */ + task automatic get_wrap_aligned_wr_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data << 8; + temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; + wrp_data = wrp_data << 8; + wrp_bytes = wrp_bytes - 1; + end + wrp_bytes = addr - start_addr; + wrp_data = b_data << (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------------*/ + /* Align the wrap strb for write transaction */ + task automatic get_wrap_aligned_wr_strb; + output [((data_bus_width/8)*axi_burst_len)-1:0] aligned_strb; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [((data_bus_width/8)*axi_burst_len)-1:0] b_strb; + input [max_burst_bytes_width:0] v_bytes; + reg [((data_bus_width/8)*axi_burst_len)-1:0] temp_strb, wrp_strb; + integer wrp_bytes; + integer i; + begin + // $display("addr %0h,b_strb %0h v_bytes %0h",addr,b_strb,v_bytes); + start_addr = (addr/v_bytes) * v_bytes; + // $display("wrap strb start_addr %0h",start_addr); + wrp_bytes = addr - start_addr; + // $display("wrap strb wrp_bytes %0h",wrp_bytes); + wrp_strb = b_strb; + temp_strb = 0; + // $display("wrap strb wrp_strb %0h before shift value1 %0h value2 %0h",wrp_strb,((data_bus_width/8)*axi_burst_len) ,(v_bytes*4)); + // $display("wrap strb wrp_strb %0h before shift value1 %0h value2 %0h",wrp_strb,((data_bus_width/8)*axi_burst_len) ,(v_bytes*4)); + wrp_strb = wrp_strb << (((data_bus_width/8)*axi_burst_len) - (v_bytes)); + // $display("wrap wrp_strb %0h after shift value1 %0h value2 %0h",wrp_strb,((data_bus_width/8)*axi_burst_len) ,(v_bytes*4)); + while(wrp_bytes > 0) begin /// get the strb that is wrapped + temp_strb = temp_strb << 1; + temp_strb[0] = wrp_strb[((data_bus_width/8)*axi_burst_len) : ((data_bus_width/8)*axi_burst_len)-1]; + wrp_strb = wrp_strb << 1; + wrp_bytes = wrp_bytes - 1; + // $display("wrap strb wrp_strb %0h wrp_bytes %0h temp_strb %0h",wrp_strb,wrp_bytes,temp_strb); + end + wrp_bytes = addr - start_addr; + wrp_strb = b_strb << (wrp_bytes); + + aligned_strb = (temp_strb | wrp_strb); + // $display("wrap strb aligned_strb %0h tmep_strb %0h wrp_strb %0h",aligned_strb,temp_strb,wrp_strb); + end + endtask + /*--------------------------------------------------------------------------------*/ + /* Calculate the Response for each read/write transaction */ + function [axi_rsp_width-1:0] calculate_resp; + input rd_wr; // indicates Read(1) or Write(0) transaction + input [addr_width-1:0] awaddr; + input [axi_prot_width-1:0] awprot; + reg [axi_rsp_width-1:0] rsp; + begin + rsp = AXI_OK; + /* Address Decode */ + if(decode_address(awaddr) === INVALID_MEM_TYPE) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) awaddr %0h",$time, DISP_ERR, slave_name, awaddr,awaddr); + end + if(!rd_wr && decode_address(awaddr) === REG_MEM) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr); + end + if(secure_access_enabled && awprot[1]) + rsp = AXI_DEC_ERR; // decode error + calculate_resp = rsp; + end + endfunction + /*--------------------------------------------------------------------------------*/ +// +// +// /* Calculate the Response for each read/write transaction */ +// function [axi_rsp_width-1:0] calculate_resp; +// input [addr_width-1:0] awaddr; +// input [axi_prot_width-1:0] awprot; +// reg [axi_rsp_width-1:0] rsp; +// begin +// rsp = AXI_OK; +// /* Address Decode */ +// if(decode_address(awaddr) === INVALID_MEM_TYPE) begin +// rsp = AXI_SLV_ERR; //slave error +// $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr); +// end +// else if(decode_address(awaddr) === REG_MEM) begin +// rsp = AXI_SLV_ERR; //slave error +// $display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr); +// end +// if(secure_access_enabled && awprot[1]) +// rsp = AXI_DEC_ERR; // decode error +// calculate_resp = rsp; +// end +// endfunction + /*--------------------------------------------------------------------------------*/ + reg[max_burst_bits-1:0] temp_wr_data; + + /* Store the Write response for each write transaction */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wr_bresp_cnt = 0; + wr_fifo_wr_ptr = 0; + end else begin + if((wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] === 'b1) && (aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] === 'b1)) begin + // enable_write_bresp <= aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + //#0 enable_write_bresp = 'b1; + enable_write_bresp = 'b1; + // $display("%t enable_write_bresp %0d wr_bresp_cnt %0d",$time ,enable_write_bresp,wr_bresp_cnt[int_wr_cntr_width-2:0]); + end + // enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + /* calculate bresp only when AWVALID && WLAST is received */ + if(enable_write_bresp) begin + aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + // $display("awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] %0h ",awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]]); + bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]); + fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp}; + /* Fill WR data FIFO */ + if(bresp === AXI_OK) begin + if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data + get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address + get_wrap_aligned_wr_strb(aligned_wr_strb,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_strb[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address + end else begin + aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ; + aligned_wr_strb = burst_strb[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + //$display(" got form fifo aligned_wr_addr %0h wr_bresp_cnt[int_wr_cntr_width-2:0]] %0d",aligned_wr_addr,wr_bresp_cnt[int_wr_cntr_width-2:0]); + //$display(" got form fifo aligned_wr_strb %0h wr_bresp_cnt[int_wr_cntr_width-2:0]] %0d",aligned_wr_strb,wr_bresp_cnt[int_wr_cntr_width-2:0]); + end + valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + //$display(" afi_slave aligned_wr_strb %0h",aligned_wr_strb); + end else + valid_data_bytes = 0; + + if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] != AXI_WRAP) begin + // wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {burst_strb[wr_bresp_cnt[int_wr_cntr_width-2:0]],awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {aligned_wr_strb,awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + //$display("afi_slave wr_fifo[wr_fifo_wr_ptr[int_wr_cntyyr_width-2:0]] %0h",wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]]); + end else begin + wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {aligned_wr_strb,awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + //$display("afi_slave wr_fifo[wr_fifo_wr_ptr[int_wr_cntyyr_width-2:0]] %0h",wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]]); + end + wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; + wr_bresp_cnt = wr_bresp_cnt+1; + enable_write_bresp = 'b0; + if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1]; + wr_bresp_cnt[int_wr_cntr_width-2:0] = 0; + end + end + end // else + end // always + /*--------------------------------------------------------------------------------*/ + + +// /* Store the Write response for each write transaction */ +// always@(negedge S_RESETN or posedge S_ACLK) +// begin +// if(!S_RESETN) begin +// wr_fifo_wr_ptr = 0; +// wcount = 0; +// end else begin +// enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]]; +// /* calculate bresp only when AWVALID && WLAST is received */ +// if(enable_write_bresp) begin +// aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0; +// wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0; +// +// bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]); +// /* Fill AFI_WR_data FIFO */ +// if(bresp === AXI_OK ) begin +// if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data +// get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address +// end else begin +// aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]]; +// aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ; +// end +// valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]; +// end else +// valid_data_bytes = 0; +// temp_wr_data = aligned_wr_data; +// wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes}; +// wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1; +// wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; +// end +// end // else +// end // always + /*--------------------------------------------------------------------------------*/ + + /* Send Write Response Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + rd_bresp_cnt = 0; + wr_latency_count = get_wr_lat_number(1); + wr_delayed = 0; + bresp_time_cnt = 0; + end else begin + // if(static_count < 32 ) begin + // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); + //wready_gen.set_low_time(0); + //wready_gen.set_high_time(1); + // slv.wr_driver.send_wready(wready_gen); + // end + if(awvalid_flag[bresp_time_cnt] && (($realtime - awvalid_receive_time[bresp_time_cnt])/diff_time >= wr_latency_count)) + wr_delayed = 1; + if(!bresp_fifo_empty && wr_delayed) begin + slv.wr_driver.get_wr_reactive(twr); + twr.set_id(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb]); + case(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb]) + 2'b00: twr.set_bresp(XIL_AXI_RESP_OKAY); + 2'b01: twr.set_bresp(XIL_AXI_RESP_EXOKAY); + 2'b10: twr.set_bresp(XIL_AXI_RESP_SLVERR); + 2'b11: twr.set_bresp(XIL_AXI_RESP_DECERR); + endcase + // if(static_count > 32 ) begin + // // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); + // wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); + // // wready_gen.set_low_time(3); + // // wready_gen.set_high_time(3); + // // wready_gen.set_low_time_range(3,6); + // // wready_gen.set_high_time_range(3,6); + // slv.wr_driver.send_wready(wready_gen); + // end + wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); + slv.wr_driver.send_wready(wready_gen); + slv.wr_driver.send(twr); + wr_delayed = 0; + awvalid_flag[bresp_time_cnt] = 1'b0; + bresp_time_cnt = bresp_time_cnt+1; + rd_bresp_cnt = rd_bresp_cnt + 1; + if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1]; + rd_bresp_cnt[int_wr_cntr_width-2:0] = 0; + end + if(bresp_time_cnt === max_wr_outstanding_transactions) begin + bresp_time_cnt = 0; + end + wr_latency_count = get_wr_lat_number(1); + static_count++; + end + static_count++; + end // else + end//always + /*--------------------------------------------------------------------------------*/ +// /* Send Write Response Channel handshake */ +// always@(negedge S_RESETN or posedge S_ACLK) +// begin +// if(!S_RESETN) begin +// rd_bresp_cnt = 0; +// wr_latency_count = get_wr_lat_number(1); +// wr_delayed = 0; +// bresp_time_cnt = 0; +// end else begin +// wr_delayed = 1'b0; +// if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count)) +// wr_delayed = 1; +// if(!bresp_fifo_empty && wr_delayed) begin +// slv.wr_driver.get_wr_reactive(twr); +// twr.set_id(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb]); +// case(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb]) +// 2'b00: twr.set_bresp(XIL_AXI_RESP_OKAY); +// 2'b01: twr.set_bresp(XIL_AXI_RESP_EXOKAY); +// 2'b10: twr.set_bresp(XIL_AXI_RESP_SLVERR); +// 2'b11: twr.set_bresp(XIL_AXI_RESP_DECERR); +// endcase +// slv.wr_driver.send(twr); +// wr_delayed = 0; +// awvalid_flag[bresp_time_cnt] = 1'b0; +// bresp_time_cnt = bresp_time_cnt+1; +// rd_bresp_cnt = rd_bresp_cnt + 1; +// wr_latency_count = get_wr_lat_number(1); +// end +// end // else +// end//always +// /*--------------------------------------------------------------------------------*/ + + /* Write Response Channel handshake */ + reg wr_int_state; + /* Reading from the wr_fifo and sending to Interconnect fifo*/ + always@(negedge S_RESETN or posedge SW_CLK) begin + if(!S_RESETN) begin + WR_DATA_VALID_DDR = 1'b0; + WR_DATA_VALID_OCM = 1'b0; + //== WR_DATA_STRB = 'b0; + wr_fifo_rd_ptr = 0; + state = SEND_DATA; + WR_QOS = 0; + end else begin + case(state) + SEND_DATA :begin + state = SEND_DATA; + WR_DATA_VALID_OCM = 0; + WR_DATA_VALID_DDR = 0; + if(!wr_fifo_empty) begin + WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb]; + WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]; + WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; + WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb]; + WR_DATA_STRB = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_strb_msb : wr_strb_lsb]; + //$display(" afi_slave WR_DATA_STRB %0h wr_strb_msb %0d wr_strb_lsb %0d",WR_DATA_STRB,wr_strb_msb,wr_strb_lsb); + state = WAIT_ACK; + case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb])) + OCM_MEM : WR_DATA_VALID_OCM = 1; + DDR_MEM : WR_DATA_VALID_DDR = 1; + default : state = SEND_DATA; + endcase + wr_fifo_rd_ptr = wr_fifo_rd_ptr+1; + end + end + WAIT_ACK :begin + state = WAIT_ACK; + if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + state = SEND_DATA; + end + end + endcase + end + + + end + + // always@(negedge S_RESETN or posedge S_ACLK) + // begin + // if(!S_RESETN) begin + // wr_int_state = 1'b0; + // wr_bresp_cnt = 0; + // wr_fifo_rd_ptr = 0; + // end else begin + // case(wr_int_state) + // 1'b0 : begin + // wr_int_state = 1'b0; + // if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin + // wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes + // wr_int_state = 1'b1; + // /* start filling the write response fifo at the same time */ + // fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp + // wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length + // wacount = wacount - 1; + // wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1; + // wr_bresp_cnt = wr_bresp_cnt+1; + // end + // end + // 1'b1 : begin + // wr_int_state = 0; + // end + // endcase + // end + // end + /*--------------------------------------------------------------------------------*/ +/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ + +/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ + +/* READ CHANNELS */ +/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ + reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0; + real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received + reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received + reg [int_rd_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info + +/* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1]; + reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1]; + reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1]; + reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1]; + reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1]; + reg ar_flag [0:max_rd_outstanding_transactions-1]; + reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1]; + reg [addr_width-1:0] addr_local; + reg [addr_width-1:0] addr_final; + reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1]; + reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1]; + wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) + + reg [int_rd_cntr_width-1:0] rd_cnt = 0; + reg [int_rd_cntr_width-1:0] trr_rd_cnt = 0; + reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0; + reg [axi_rsp_width-1:0] rresp; + + reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_rresp; + + /* Send Read Response & Data Channel handshake */ + integer rd_latency_count; + reg rd_delayed; + reg read_fifo_empty; + + reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data .. + // reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_rd_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes + reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; + wire read_fifo_full; + + reg [7:0] rcount; + reg [2:0] racount; + + wire rd_intr_fifo_full, rd_intr_fifo_empty; + + assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0; + + /* signals to communicate with interconnect RD_FIFO model */ + reg rd_req, invalid_rd_req; + + /* REad control Info + 56:25 : Address (32) + 24:22 : Size (3) + 21:20 : BRST (2) + 19:16 : LEN (4) + 15:10 : RID (6) + 9:8 : RRSP (2) + 7:0 : byte cnt (8) + */ + reg [rd_info_bits-1:0] read_control_info; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data; + reg temp_rd_intr_fifo_empty; + + processing_system7_vip_v1_0_16_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR); + + assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0; + assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0; + assign S_RCOUNT = rcount; + assign S_RACOUNT = racount; + + /* Register the asynch signal empty coming from Interconnect READ FIFO */ + always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty; + + // FIFO_STATUS (only if AFI port) 1- full + function automatic rdfifo_full ; + input [axi_len_width:0] fifo_space_exp; + integer fifo_space_left; + begin + fifo_space_left = afi_fifo_locations - rcount; + if(fifo_space_left < fifo_space_exp) + rdfifo_full = 1; + else + rdfifo_full = 0; + end + endfunction + + /* Store the arvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) + ar_time_cnt = 0; + else begin + if(net_ARVALID == 'b1 && S_ARREADY == 'b1) begin + arvalid_receive_time[ar_time_cnt[int_rd_cntr_width-2:0]] = $time; + arvalid_flag[ar_time_cnt[int_rd_cntr_width-2:0]] = 1'b1; + ar_time_cnt = ar_time_cnt + 1; + if((ar_time_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) ) + ar_time_cnt[int_rd_cntr_width-1:0] = 0; + end + end // else + end /// always +// /* Store the arvalid receive time --- necessary for calculating the bresp latency */ +// always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID ) +// begin +// if(!S_RESETN) +// ar_time_cnt = 0; +// else begin +// if(S_ARVALID) begin +// arvalid_receive_time[ar_time_cnt] = $time; +// arvalid_flag[ar_time_cnt] = 1'b1; +// ar_time_cnt = ar_time_cnt + 1; +// end +// end // else +// end /// always + /*--------------------------------------------------------------------------------*/ + + always@(ar_fifo_full) + begin + if(ar_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions); + end + /*--------------------------------------------------------------------------------*/ + + always@(posedge S_ACLK) + begin + if(net_ARVALID == 'b1 && S_ARREADY == 'b1) begin + if(S_ARQOS === 0) begin + arqos[ar_cnt[int_rd_cntr_width-2:0]] = ar_qos; + end else begin + arqos[ar_cnt[int_rd_cntr_width-2:0]] = S_ARQOS; + end + end + end +// always@(posedge S_ACLK) +// begin +// if(net_ARVALID && S_ARREADY) begin +// if(S_ARQOS === 0) arqos[ar_cnt[int_rd_cntr_width-2:0]] = ar_qos; +// else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS; +// end +// end + + /* Address Read Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + ar_cnt = 0; + + end else begin + if(!ar_fifo_full) begin + slv.monitor.axi_rd_cmd_port.get(trc); + // araddr[ar_cnt[int_rd_cntr_width-2:0]] = trc.addr; + arlen[ar_cnt[int_rd_cntr_width-2:0]] = trc.len; + arsize[ar_cnt[int_rd_cntr_width-2:0]] = trc.size; + arbrst[ar_cnt[int_rd_cntr_width-2:0]] = trc.burst; + arlock[ar_cnt[int_rd_cntr_width-2:0]] = trc.lock; + arcache[ar_cnt[int_rd_cntr_width-2:0]]= trc.cache; + arprot[ar_cnt[int_rd_cntr_width-2:0]] = trc.prot; + arid[ar_cnt[int_rd_cntr_width-2:0]] = trc.id; + ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1'b1; + size_local = trc.size; + addr_local = trc.addr; + case(size_local) + 0 : addr_final = {addr_local}; + 1 : addr_final = {addr_local[31:1],1'b0}; + 2 : addr_final = {addr_local[31:2],2'b0}; + 3 : addr_final = {addr_local[31:3],3'b0}; + 4 : addr_final = {addr_local[31:4],4'b0}; + 5 : addr_final = {addr_local[31:5],5'b0}; + 6 : addr_final = {addr_local[31:6],6'b0}; + 7 : addr_final = {addr_local[31:7],7'b0}; + endcase + araddr[ar_cnt[int_rd_cntr_width-2:0]] = addr_final; + ar_cnt = ar_cnt+1; + if(ar_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) begin + // ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1]; + ar_cnt[int_rd_cntr_width-1:0] = 0; + end + end /// if(!ar_fifo_full) + end /// if else + end /// always*/ + +// /* Address Read Channel handshake*/ +// always@(negedge S_RESETN or posedge S_ACLK) +// begin +// if(!S_RESETN) begin +// ar_cnt = 0; +// racount = 0; +// end else begin +// if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full +// slv.monitor.axi_rd_cmd_port.get(trc); +// araddr[ar_cnt[int_cntr_width-2:0]] = trc.addr; +// arlen[ar_cnt[int_cntr_width-2:0]] = trc.len; +// arsize[ar_cnt[int_cntr_width-2:0]] = trc.size; +// arbrst[ar_cnt[int_cntr_width-2:0]] = trc.burst; +// arlock[ar_cnt[int_cntr_width-2:0]] = trc.lock; +// arcache[ar_cnt[int_cntr_width-2:0]]= trc.cache; +// arprot[ar_cnt[int_cntr_width-2:0]] = trc.prot; +// arid[ar_cnt[int_cntr_width-2:0]] = trc.id; +// ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1; +// ar_cnt = ar_cnt+1; +// racount = racount + 1; +// end /// if(!ar_fifo_full) +// end /// if else +// end /// always*/ + + /*--------------------------------------------------------------------------------*/ + + /* Align Wrap data for read transaction*/ + task automatic get_wrap_aligned_rd_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [addr_width-1:0] start_addr; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data >> 8; + temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; + wrp_data = wrp_data >> 8; + wrp_bytes = wrp_bytes - 1; + end + temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); + wrp_bytes = addr - start_addr; + wrp_data = b_data >> (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1; + reg rd_fifo_state; + reg [addr_width-1:0] temp_read_address; + reg [max_burst_bytes_width:0] temp_rd_valid_bytes; + /* get the data from memory && also calculate the rresp*/ + /* get the data from memory && also calculate the rresp*/ + always@(negedge S_RESETN or posedge SW_CLK) + begin + if(!S_RESETN)begin + rd_fifo_wr_ptr = 0; + wr_rresp_cnt =0; + rd_fifo_state = RD_DATA_REQ; + temp_rd_valid_bytes = 0; + temp_read_address = 0; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + // RD_REQ_REG = 0; + + RD_QOS = 0; + invalid_rd_req = 0; + end else begin + case(rd_fifo_state) + RD_DATA_REQ : begin + rd_fifo_state = RD_DATA_REQ; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + // RD_REQ_REG = 0; + RD_QOS = 0; + if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin + ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0; + rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]); + fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp}; + temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8; + + if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin + temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; + else + temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + + if(rresp === AXI_OK) begin + case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]); + OCM_MEM : RD_REQ_OCM = 1; + DDR_MEM : RD_REQ_DDR = 1; + // REG_MEM : RD_REQ_REG = 1; + default : invalid_rd_req = 1; + endcase + end else + invalid_rd_req = 1; + + RD_QOS = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + RD_BYTES = temp_rd_valid_bytes; + rd_fifo_state = WAIT_RD_VALID; + + + + + wr_rresp_cnt = wr_rresp_cnt + 1; + if(wr_rresp_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) begin + // wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1]; + wr_rresp_cnt[int_rd_cntr_width-1:0] = 0; + end + end + end + WAIT_RD_VALID : begin + rd_fifo_state = WAIT_RD_VALID; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin + // if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin + if(RD_DATA_VALID_DDR) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR; + else if(RD_DATA_VALID_OCM) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM; + // else if(RD_DATA_VALID_REG) + // read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG; + else + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0; + rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + // RD_REQ_REG = 0; + RD_QOS = 0; + invalid_rd_req = 0; + rd_fifo_state = RD_DATA_REQ; + end + end + endcase + end /// else + end /// always + + /*--------------------------------------------------------------------------------*/ +// always@(negedge S_RESETN or posedge SW_CLK) +// begin +// if(!S_RESETN)begin +// wr_rresp_cnt =0; +// rd_fifo_state = RD_DATA_REQ; +// temp_rd_valid_bytes = 0; +// temp_read_address = 0; +// RD_REQ_DDR = 1'b0; +// RD_REQ_OCM = 1'b0; +// rd_req = 0; +// invalid_rd_req= 0; +// RD_QOS = 0; +// end else begin +// case(rd_fifo_state) +// RD_DATA_REQ : begin +// rd_fifo_state = RD_DATA_REQ; +// RD_REQ_DDR = 1'b0; +// RD_REQ_OCM = 1'b0; +// invalid_rd_req = 0; +// if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition +// ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0; +// rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]); +// temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8; +// +// if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin +// temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; +// else +// temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]]; +// +// if(rresp === AXI_OK) begin +// case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]); +// OCM_MEM : RD_REQ_OCM = 1; +// DDR_MEM : RD_REQ_DDR = 1; +// default : invalid_rd_req = 1; +// endcase +// end else +// invalid_rd_req = 1; +// RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]]; +// RD_BYTES = temp_rd_valid_bytes; +// RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]]; +// rd_fifo_state = WAIT_RD_VALID; +// rd_req = 1; +// racount = racount - 1; +// read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes }; +// wr_rresp_cnt = wr_rresp_cnt + 1; +// end +// end +// WAIT_RD_VALID : begin +// rd_fifo_state = WAIT_RD_VALID; +// rd_req = 0; +// if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin +// RD_REQ_DDR = 1'b0; +// RD_REQ_OCM = 1'b0; +// invalid_rd_req = 0; +// rd_fifo_state = RD_DATA_REQ; +// end +// end +// endcase +// end /// else +// end /// always + /*--------------------------------------------------------------------------------*/ + + /* thread to fill in the AFI RD_FIFO */ + reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes + reg tmp_state; + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN)begin + rd_fifo_wr_ptr = 0; + rcount = 0; + tmp_state = 0; + end else begin + case(tmp_state) + 0 : begin + tmp_state = 0; + if(!temp_rd_intr_fifo_empty) begin + rd_intr_fifo.read_mem(temp_rd_data); + tmp_state = 1; + end + end + 1 : begin + tmp_state = 1; + if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = temp_rd_data; + rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; + rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length + tmp_state = 0; + end + end + endcase + end + end + /*--------------------------------------------------------------------------------*/ + + reg[max_burst_bytes_width:0] rd_v_b; + reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes + reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data; + reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data; + reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; + + xil_axi_data_beat new_data; + /* Read Data Channel handshake */ + //always@(negedge S_RESETN or posedge S_ACLK) + initial begin + forever begin + if(!S_RESETN)begin + // rd_fifo_rd_ptr = 0; + trr_rd_cnt = 0; + // rd_latency_count = get_rd_lat_number(1); + // rd_delayed = 0; + // rresp_time_cnt = 0; + // rd_v_b = 0; + end else begin + //if(net_ARVALID && S_ARREADY) + // trr_rd[trr_rd_cnt] = new("trr_rd[trr_rd_cnt]"); + // trr_rd[trr_rd_cnt] = new($psprintf("trr_rd[%0d]",trr_rd_cnt)); + slv.rd_driver.get_rd_reactive(trr); + trr_rd.push_back(trr.my_clone()); + //$cast(trr_rd[trr_rd_cnt],trr.copy()); + // rd_latency_count = get_rd_lat_number(1); + // $display("%m waiting for next transfer trr_rd_cnt %0d trr.size %0d " ,trr_rd_cnt,trr.size); + // $display("%m waiting for next transfer trr_rd_cnt %0d trr_rd[trr_rd_cnt] %0d" ,trr_rd_cnt,trr_rd[trr_rd_cnt].size); + trr_rd_cnt++; + @(posedge S_ACLK); + end + end // forever + end // initial + + + initial begin + if(DEBUG_INFO) $display($time," BEFORE checking line ...... %0d",S_RESETN); + forever begin + if(DEBUG_INFO) $display($time," AFTER checking line ...... %0d",S_RESETN); + if(!S_RESETN)begin + $monitor($time," checking line ......"); + rd_fifo_rd_ptr = 0; + rd_cnt = 0; + rd_latency_count = get_rd_lat_number(1); + rd_delayed = 0; + rresp_time_cnt = 0; + rd_v_b = 0; + end else begin + $monitor($time," else checking line ......%0d",S_RESETN); + //if(net_ARVALID && S_ARREADY) + // slv.rd_driver.get_rd_reactive(trr_rd[rresp_time_cnt]); + wait(arvalid_flag[rresp_time_cnt[int_rd_cntr_width-2:0]] == 1); + // while(trr_rd[rresp_time_cnttrr_rd_cnt] == null) begin + // @(posedge S_ACLK); + // end + rd_latency_count = get_rd_lat_number(1); + // $display("%m waiting for element form vip rresp_time_cnt %0d ",rresp_time_cnt); + // while(trr_rd.size()< 0 ) begin + // $display("%m got the element form vip rresp_time_cnt %0d ",rresp_time_cnt); + // @(posedge S_ACLK); + // end + // $display("%m got the element form vip rresp_time_cnt %0d ",rresp_time_cnt); + wait(trr_rd.size() > 0); + trr_get_rd = trr_rd.pop_front(); + // $display("%m waiting for next transfer trr_rd_cnt %0d trr_get_rd %0d" ,trr_rd_cnt,trr_get_rd.size); + while ((arvalid_flag[rresp_time_cnt[int_rd_cntr_width-2:0]] == 'b1 )&& ((($realtime - arvalid_receive_time[rresp_time_cnt[int_rd_cntr_width-2:0]])/diff_time) < rd_latency_count)) begin + @(posedge S_ACLK); + end + + //if(arvalid_flag[rresp_time_cnt] && ((($realtime - arvalid_receive_time[rresp_time_cnt])/diff_time) >= rd_latency_count)) + rd_delayed = 1; + + if(!read_fifo_empty && rd_delayed)begin + rd_delayed = 0; + arvalid_flag[rresp_time_cnt[int_rd_cntr_width-2:0]] = 1'b0; + rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]])); + temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]]; + rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; + + if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin + get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b); + temp_read_data = temp_wrap_data; + end + temp_read_rsp = 0; + repeat(axi_burst_len) begin + temp_read_rsp = temp_read_rsp >> axi_rsp_width; + temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb]; + end + case (arsize[rd_cnt[int_rd_cntr_width-2:0]]) + 3'b000: trr_get_rd.size = XIL_AXI_SIZE_1BYTE; + 3'b001: trr_get_rd.size = XIL_AXI_SIZE_2BYTE; + 3'b010: trr_get_rd.size = XIL_AXI_SIZE_4BYTE; + 3'b011: trr_get_rd.size = XIL_AXI_SIZE_8BYTE; + 3'b100: trr_get_rd.size = XIL_AXI_SIZE_16BYTE; + 3'b101: trr_get_rd.size = XIL_AXI_SIZE_32BYTE; + 3'b110: trr_get_rd.size = XIL_AXI_SIZE_64BYTE; + 3'b111: trr_get_rd.size = XIL_AXI_SIZE_128BYTE; + endcase + trr_get_rd.len = arlen[rd_cnt[int_rd_cntr_width-2:0]]; + trr_get_rd.id = (arid[rd_cnt[int_rd_cntr_width-2:0]]); +// trr_get_rd.data = new[((2**arsize[rd_cnt[int_rd_cntr_width-2:0]])*(arlen[rd_cnt[int_rd_cntr_width-2:0]]+1))]; + trr_get_rd.rresp = new[((2**arsize[rd_cnt[int_rd_cntr_width-2:0]])*(arlen[rd_cnt[int_rd_cntr_width-2:0]]+1))]; + for(j = 0; j < (arlen[rd_cnt[int_rd_cntr_width-2:0]]+1); j = j+1) begin + for(k = 0; k < (2**arsize[rd_cnt[int_rd_cntr_width-2:0]]); k = k+1) begin + new_data[(k*8)+:8] = temp_read_data[7:0]; + temp_read_data = temp_read_data >> 8; + end + trr_get_rd.set_data_beat(j, new_data); + case(temp_read_rsp[(j*2)+:2]) + 2'b00: trr_get_rd.rresp[j] = XIL_AXI_RESP_OKAY; + 2'b01: trr_get_rd.rresp[j] = XIL_AXI_RESP_EXOKAY; + 2'b10: trr_get_rd.rresp[j] = XIL_AXI_RESP_SLVERR; + 2'b11: trr_get_rd.rresp[j] = XIL_AXI_RESP_DECERR; + endcase + end + slv.rd_driver.send(trr_get_rd); + rd_cnt = rd_cnt + 1; + + rresp_time_cnt = rresp_time_cnt+1; + if(DEBUG_INFO) $display(" %m current rresp_time_cnt %0d rd_cnt %0d max_rd_outstanding_transactions %0d",rresp_time_cnt,rd_cnt,max_rd_outstanding_transactions); + if(rresp_time_cnt[int_rd_cntr_width-1:0] === max_rd_outstanding_transactions) begin + // rresp_time_cnt[int_rd_cntr_width-1] = ~ rresp_time_cnt[int_rd_cntr_width-1]; + rresp_time_cnt[int_rd_cntr_width-1:0] = 0; + if(DEBUG_INFO) $display(" %m resetting rresp_time_cnt %0d max_rd_outstanding_transactions %0d",rresp_time_cnt,max_rd_outstanding_transactions); + end + + if(rd_cnt[int_rd_cntr_width-1:0] === (max_rd_outstanding_transactions)) begin + // rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1]; + rd_cnt[int_rd_cntr_width-1:0] = 0; + if(DEBUG_INFO) $display(" %m resetting rd_cnt %0d max_rd_outstanding_transactions %0d",rd_cnt,max_rd_outstanding_transactions); + end + rd_latency_count = get_rd_lat_number(1); + + end + end /// else + end /// always +end + + +// /* Read Data Channel handshake */ +// always@(negedge S_RESETN or posedge S_ACLK) +// begin +// if(!S_RESETN)begin +// rd_fifo_rd_ptr = 0; +// rd_latency_count = get_rd_lat_number(1); +// rd_delayed = 0; +// rresp_time_cnt = 0; +// rd_v_b = 0; +// end else begin +// if(net_ARVALID && S_ARREADY) +// slv.rd_driver.get_rd_reactive(trr); +// if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin +// rd_delayed = 1; +// end +// if(!read_fifo_empty && rd_delayed)begin +// rd_delayed = 0; +// arvalid_flag[rresp_time_cnt] = 1'b0; +// tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]]; +// rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]); +// temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb]; +// if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin +// get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b); +// temp_read_data = aligned_rd_data; +// end +// temp_read_rsp = 0; +// repeat(axi_burst_len) begin +// temp_read_rsp = temp_read_rsp >> axi_rsp_width; +// temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb]; +// end +// case (tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]) +// 3'b000: trr.size = XIL_AXI_SIZE_1BYTE; +// 3'b001: trr.size = XIL_AXI_SIZE_2BYTE; +// 3'b010: trr.size = XIL_AXI_SIZE_4BYTE; +// 3'b011: trr.size = XIL_AXI_SIZE_8BYTE; +// 3'b100: trr.size = XIL_AXI_SIZE_16BYTE; +// 3'b101: trr.size = XIL_AXI_SIZE_32BYTE; +// 3'b110: trr.size = XIL_AXI_SIZE_64BYTE; +// 3'b111: trr.size = XIL_AXI_SIZE_128BYTE; +// endcase +// trr.len = tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]; +// trr.id = (tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb]); +// // trr.data = new[((2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb])*(tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1))]; +// trr.rresp = new[((2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb])*(tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1))]; +// for(j = 0; j < (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1); j = j+1) begin +// for(k = 0; k < (2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]); k = k+1) begin +// new_data[(k*8)+:8] = temp_read_data[7:0]; +// temp_read_data = temp_read_data >> 8; +// end +// trr.set_data_beat(j, new_data); +// case(temp_read_rsp[(j*2)+:2]) +// 2'b00: trr.rresp[j] = XIL_AXI_RESP_OKAY; +// 2'b01: trr.rresp[j] = XIL_AXI_RESP_EXOKAY; +// 2'b10: trr.rresp[j] = XIL_AXI_RESP_SLVERR; +// 2'b11: trr.rresp[j] = XIL_AXI_RESP_DECERR; +// endcase +// end +// // trr.last = 1; +// slv.rd_driver.send(trr); +// rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ; +// rresp_time_cnt = rresp_time_cnt+1; +// rd_latency_count = get_rd_lat_number(1); +// rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; +// end +// end /// else +// end /// always +endmodule + + +/***************************************************************************** + * File : processing_system7_vip_v1_0_16.v + * + * Date : 2012-11 + * + * Description : Processing_system7_vip Top (zynq_vip top) + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_vip_v1_0_16 + ( + CAN0_PHY_TX, + CAN0_PHY_RX, + CAN1_PHY_TX, + CAN1_PHY_RX, + ENET0_GMII_TX_EN, + ENET0_GMII_TX_ER, + ENET0_MDIO_MDC, + ENET0_MDIO_O, + ENET0_MDIO_T, + ENET0_PTP_DELAY_REQ_RX, + ENET0_PTP_DELAY_REQ_TX, + ENET0_PTP_PDELAY_REQ_RX, + ENET0_PTP_PDELAY_REQ_TX, + ENET0_PTP_PDELAY_RESP_RX, + ENET0_PTP_PDELAY_RESP_TX, + ENET0_PTP_SYNC_FRAME_RX, + ENET0_PTP_SYNC_FRAME_TX, + ENET0_SOF_RX, + ENET0_SOF_TX, + ENET0_GMII_TXD, + ENET0_GMII_COL, + ENET0_GMII_CRS, + ENET0_EXT_INTIN, + ENET0_GMII_RX_CLK, + ENET0_GMII_RX_DV, + ENET0_GMII_RX_ER, + ENET0_GMII_TX_CLK, + ENET0_MDIO_I, + ENET0_GMII_RXD, + ENET1_GMII_TX_EN, + ENET1_GMII_TX_ER, + ENET1_MDIO_MDC, + ENET1_MDIO_O, + ENET1_MDIO_T, + ENET1_PTP_DELAY_REQ_RX, + ENET1_PTP_DELAY_REQ_TX, + ENET1_PTP_PDELAY_REQ_RX, + ENET1_PTP_PDELAY_REQ_TX, + ENET1_PTP_PDELAY_RESP_RX, + ENET1_PTP_PDELAY_RESP_TX, + ENET1_PTP_SYNC_FRAME_RX, + ENET1_PTP_SYNC_FRAME_TX, + ENET1_SOF_RX, + ENET1_SOF_TX, + ENET1_GMII_TXD, + ENET1_GMII_COL, + ENET1_GMII_CRS, + ENET1_EXT_INTIN, + ENET1_GMII_RX_CLK, + ENET1_GMII_RX_DV, + ENET1_GMII_RX_ER, + ENET1_GMII_TX_CLK, + ENET1_MDIO_I, + ENET1_GMII_RXD, + GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + I2C1_SDA_I, + I2C1_SDA_O, + I2C1_SDA_T, + I2C1_SCL_I, + I2C1_SCL_O, + I2C1_SCL_T, + PJTAG_TCK, + PJTAG_TMS, + PJTAG_TD_I, + PJTAG_TD_T, + PJTAG_TD_O, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SDIO1_CLK, + SDIO1_CLK_FB, + SDIO1_CMD_O, + SDIO1_CMD_I, + SDIO1_CMD_T, + SDIO1_DATA_I, + SDIO1_DATA_O, + SDIO1_DATA_T, + SDIO1_LED, + SDIO1_CDN, + SDIO1_WP, + SDIO1_BUSPOW, + SDIO1_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_DTRN, + UART0_RTSN, + UART0_TX, + UART0_CTSN, + UART0_DCDN, + UART0_DSRN, + UART0_RIN, + UART0_RX, + UART1_DTRN, + UART1_RTSN, + UART1_TX, + UART1_CTSN, + UART1_DCDN, + UART1_DSRN, + UART1_RIN, + UART1_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC0_CLK0_IN, + TTC0_CLK1_IN, + TTC0_CLK2_IN, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + TTC1_CLK0_IN, + TTC1_CLK1_IN, + TTC1_CLK2_IN, + WDT_CLK_IN, + WDT_RST_OUT, + TRACE_CLK, + TRACE_CTL, + TRACE_DATA, + USB0_PORT_INDCTL, + USB1_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB1_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + USB1_VBUS_PWRFAULT, + SRAM_INTIN, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + M_AXI_GP1_ARVALID, + M_AXI_GP1_AWVALID, + M_AXI_GP1_BREADY, + M_AXI_GP1_RREADY, + M_AXI_GP1_WLAST, + M_AXI_GP1_WVALID, + M_AXI_GP1_ARID, + M_AXI_GP1_AWID, + M_AXI_GP1_WID, + M_AXI_GP1_ARBURST, + M_AXI_GP1_ARLOCK, + M_AXI_GP1_ARSIZE, + M_AXI_GP1_AWBURST, + M_AXI_GP1_AWLOCK, + M_AXI_GP1_AWSIZE, + M_AXI_GP1_ARPROT, + M_AXI_GP1_AWPROT, + M_AXI_GP1_ARADDR, + M_AXI_GP1_AWADDR, + M_AXI_GP1_WDATA, + M_AXI_GP1_ARCACHE, + M_AXI_GP1_ARLEN, + M_AXI_GP1_ARQOS, + M_AXI_GP1_AWCACHE, + M_AXI_GP1_AWLEN, + M_AXI_GP1_AWQOS, + M_AXI_GP1_WSTRB, + M_AXI_GP1_ACLK, + M_AXI_GP1_ARREADY, + M_AXI_GP1_AWREADY, + M_AXI_GP1_BVALID, + M_AXI_GP1_RLAST, + M_AXI_GP1_RVALID, + M_AXI_GP1_WREADY, + M_AXI_GP1_BID, + M_AXI_GP1_RID, + M_AXI_GP1_BRESP, + M_AXI_GP1_RRESP, + M_AXI_GP1_RDATA, + S_AXI_GP0_ARREADY, + S_AXI_GP0_AWREADY, + S_AXI_GP0_BVALID, + S_AXI_GP0_RLAST, + S_AXI_GP0_RVALID, + S_AXI_GP0_WREADY, + S_AXI_GP0_BRESP, + S_AXI_GP0_RRESP, + S_AXI_GP0_RDATA, + S_AXI_GP0_BID, + S_AXI_GP0_RID, + S_AXI_GP0_ACLK, + S_AXI_GP0_ARVALID, + S_AXI_GP0_AWVALID, + S_AXI_GP0_BREADY, + S_AXI_GP0_RREADY, + S_AXI_GP0_WLAST, + S_AXI_GP0_WVALID, + S_AXI_GP0_ARBURST, + S_AXI_GP0_ARLOCK, + S_AXI_GP0_ARSIZE, + S_AXI_GP0_AWBURST, + S_AXI_GP0_AWLOCK, + S_AXI_GP0_AWSIZE, + S_AXI_GP0_ARPROT, + S_AXI_GP0_AWPROT, + S_AXI_GP0_ARADDR, + S_AXI_GP0_AWADDR, + S_AXI_GP0_WDATA, + S_AXI_GP0_ARCACHE, + S_AXI_GP0_ARLEN, + S_AXI_GP0_ARQOS, + S_AXI_GP0_AWCACHE, + S_AXI_GP0_AWLEN, + S_AXI_GP0_AWQOS, + S_AXI_GP0_WSTRB, + S_AXI_GP0_ARID, + S_AXI_GP0_AWID, + S_AXI_GP0_WID, + S_AXI_GP1_ARREADY, + S_AXI_GP1_AWREADY, + S_AXI_GP1_BVALID, + S_AXI_GP1_RLAST, + S_AXI_GP1_RVALID, + S_AXI_GP1_WREADY, + S_AXI_GP1_BRESP, + S_AXI_GP1_RRESP, + S_AXI_GP1_RDATA, + S_AXI_GP1_BID, + S_AXI_GP1_RID, + S_AXI_GP1_ACLK, + S_AXI_GP1_ARVALID, + S_AXI_GP1_AWVALID, + S_AXI_GP1_BREADY, + S_AXI_GP1_RREADY, + S_AXI_GP1_WLAST, + S_AXI_GP1_WVALID, + S_AXI_GP1_ARBURST, + S_AXI_GP1_ARLOCK, + S_AXI_GP1_ARSIZE, + S_AXI_GP1_AWBURST, + S_AXI_GP1_AWLOCK, + S_AXI_GP1_AWSIZE, + S_AXI_GP1_ARPROT, + S_AXI_GP1_AWPROT, + S_AXI_GP1_ARADDR, + S_AXI_GP1_AWADDR, + S_AXI_GP1_WDATA, + S_AXI_GP1_ARCACHE, + S_AXI_GP1_ARLEN, + S_AXI_GP1_ARQOS, + S_AXI_GP1_AWCACHE, + S_AXI_GP1_AWLEN, + S_AXI_GP1_AWQOS, + S_AXI_GP1_WSTRB, + S_AXI_GP1_ARID, + S_AXI_GP1_AWID, + S_AXI_GP1_WID, + S_AXI_ACP_AWREADY, + S_AXI_ACP_ARREADY, + S_AXI_ACP_BVALID, + S_AXI_ACP_RLAST, + S_AXI_ACP_RVALID, + S_AXI_ACP_WREADY, + S_AXI_ACP_BRESP, + S_AXI_ACP_RRESP, + S_AXI_ACP_BID, + S_AXI_ACP_RID, + S_AXI_ACP_RDATA, + S_AXI_ACP_ACLK, + S_AXI_ACP_ARVALID, + S_AXI_ACP_AWVALID, + S_AXI_ACP_BREADY, + S_AXI_ACP_RREADY, + S_AXI_ACP_WLAST, + S_AXI_ACP_WVALID, + S_AXI_ACP_ARID, + S_AXI_ACP_ARPROT, + S_AXI_ACP_AWID, + S_AXI_ACP_AWPROT, + S_AXI_ACP_WID, + S_AXI_ACP_ARADDR, + S_AXI_ACP_AWADDR, + S_AXI_ACP_ARCACHE, + S_AXI_ACP_ARLEN, + S_AXI_ACP_ARQOS, + S_AXI_ACP_AWCACHE, + S_AXI_ACP_AWLEN, + S_AXI_ACP_AWQOS, + S_AXI_ACP_ARBURST, + S_AXI_ACP_ARLOCK, + S_AXI_ACP_ARSIZE, + S_AXI_ACP_AWBURST, + S_AXI_ACP_AWLOCK, + S_AXI_ACP_AWSIZE, + S_AXI_ACP_ARUSER, + S_AXI_ACP_AWUSER, + S_AXI_ACP_WDATA, + S_AXI_ACP_WSTRB, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + S_AXI_HP1_ARREADY, + S_AXI_HP1_AWREADY, + S_AXI_HP1_BVALID, + S_AXI_HP1_RLAST, + S_AXI_HP1_RVALID, + S_AXI_HP1_WREADY, + S_AXI_HP1_BRESP, + S_AXI_HP1_RRESP, + S_AXI_HP1_BID, + S_AXI_HP1_RID, + S_AXI_HP1_RDATA, + S_AXI_HP1_RCOUNT, + S_AXI_HP1_WCOUNT, + S_AXI_HP1_RACOUNT, + S_AXI_HP1_WACOUNT, + S_AXI_HP1_ACLK, + S_AXI_HP1_ARVALID, + S_AXI_HP1_AWVALID, + S_AXI_HP1_BREADY, + S_AXI_HP1_RDISSUECAP1_EN, + S_AXI_HP1_RREADY, + S_AXI_HP1_WLAST, + S_AXI_HP1_WRISSUECAP1_EN, + S_AXI_HP1_WVALID, + S_AXI_HP1_ARBURST, + S_AXI_HP1_ARLOCK, + S_AXI_HP1_ARSIZE, + S_AXI_HP1_AWBURST, + S_AXI_HP1_AWLOCK, + S_AXI_HP1_AWSIZE, + S_AXI_HP1_ARPROT, + S_AXI_HP1_AWPROT, + S_AXI_HP1_ARADDR, + S_AXI_HP1_AWADDR, + S_AXI_HP1_ARCACHE, + S_AXI_HP1_ARLEN, + S_AXI_HP1_ARQOS, + S_AXI_HP1_AWCACHE, + S_AXI_HP1_AWLEN, + S_AXI_HP1_AWQOS, + S_AXI_HP1_ARID, + S_AXI_HP1_AWID, + S_AXI_HP1_WID, + S_AXI_HP1_WDATA, + S_AXI_HP1_WSTRB, + S_AXI_HP2_ARREADY, + S_AXI_HP2_AWREADY, + S_AXI_HP2_BVALID, + S_AXI_HP2_RLAST, + S_AXI_HP2_RVALID, + S_AXI_HP2_WREADY, + S_AXI_HP2_BRESP, + S_AXI_HP2_RRESP, + S_AXI_HP2_BID, + S_AXI_HP2_RID, + S_AXI_HP2_RDATA, + S_AXI_HP2_RCOUNT, + S_AXI_HP2_WCOUNT, + S_AXI_HP2_RACOUNT, + S_AXI_HP2_WACOUNT, + S_AXI_HP2_ACLK, + S_AXI_HP2_ARVALID, + S_AXI_HP2_AWVALID, + S_AXI_HP2_BREADY, + S_AXI_HP2_RDISSUECAP1_EN, + S_AXI_HP2_RREADY, + S_AXI_HP2_WLAST, + S_AXI_HP2_WRISSUECAP1_EN, + S_AXI_HP2_WVALID, + S_AXI_HP2_ARBURST, + S_AXI_HP2_ARLOCK, + S_AXI_HP2_ARSIZE, + S_AXI_HP2_AWBURST, + S_AXI_HP2_AWLOCK, + S_AXI_HP2_AWSIZE, + S_AXI_HP2_ARPROT, + S_AXI_HP2_AWPROT, + S_AXI_HP2_ARADDR, + S_AXI_HP2_AWADDR, + S_AXI_HP2_ARCACHE, + S_AXI_HP2_ARLEN, + S_AXI_HP2_ARQOS, + S_AXI_HP2_AWCACHE, + S_AXI_HP2_AWLEN, + S_AXI_HP2_AWQOS, + S_AXI_HP2_ARID, + S_AXI_HP2_AWID, + S_AXI_HP2_WID, + S_AXI_HP2_WDATA, + S_AXI_HP2_WSTRB, + S_AXI_HP3_ARREADY, + S_AXI_HP3_AWREADY, + S_AXI_HP3_BVALID, + S_AXI_HP3_RLAST, + S_AXI_HP3_RVALID, + S_AXI_HP3_WREADY, + S_AXI_HP3_BRESP, + S_AXI_HP3_RRESP, + S_AXI_HP3_BID, + S_AXI_HP3_RID, + S_AXI_HP3_RDATA, + S_AXI_HP3_RCOUNT, + S_AXI_HP3_WCOUNT, + S_AXI_HP3_RACOUNT, + S_AXI_HP3_WACOUNT, + S_AXI_HP3_ACLK, + S_AXI_HP3_ARVALID, + S_AXI_HP3_AWVALID, + S_AXI_HP3_BREADY, + S_AXI_HP3_RDISSUECAP1_EN, + S_AXI_HP3_RREADY, + S_AXI_HP3_WLAST, + S_AXI_HP3_WRISSUECAP1_EN, + S_AXI_HP3_WVALID, + S_AXI_HP3_ARBURST, + S_AXI_HP3_ARLOCK, + S_AXI_HP3_ARSIZE, + S_AXI_HP3_AWBURST, + S_AXI_HP3_AWLOCK, + S_AXI_HP3_AWSIZE, + S_AXI_HP3_ARPROT, + S_AXI_HP3_AWPROT, + S_AXI_HP3_ARADDR, + S_AXI_HP3_AWADDR, + S_AXI_HP3_ARCACHE, + S_AXI_HP3_ARLEN, + S_AXI_HP3_ARQOS, + S_AXI_HP3_AWCACHE, + S_AXI_HP3_AWLEN, + S_AXI_HP3_AWQOS, + S_AXI_HP3_ARID, + S_AXI_HP3_AWID, + S_AXI_HP3_WID, + S_AXI_HP3_WDATA, + S_AXI_HP3_WSTRB, + DMA0_DATYPE, + DMA0_DAVALID, + DMA0_DRREADY, + DMA0_ACLK, + DMA0_DAREADY, + DMA0_DRLAST, + DMA0_DRVALID, + DMA0_DRTYPE, + DMA1_DATYPE, + DMA1_DAVALID, + DMA1_DRREADY, + DMA1_ACLK, + DMA1_DAREADY, + DMA1_DRLAST, + DMA1_DRVALID, + DMA1_DRTYPE, + DMA2_DATYPE, + DMA2_DAVALID, + DMA2_DRREADY, + DMA2_ACLK, + DMA2_DAREADY, + DMA2_DRLAST, + DMA2_DRVALID, + DMA3_DRVALID, + DMA3_DATYPE, + DMA3_DAVALID, + DMA3_DRREADY, + DMA3_ACLK, + DMA3_DAREADY, + DMA3_DRLAST, + DMA2_DRTYPE, + DMA3_DRTYPE, + FTMD_TRACEIN_DATA, + FTMD_TRACEIN_VALID, + FTMD_TRACEIN_CLK, + FTMD_TRACEIN_ATID, + FTMT_F2P_TRIG, + FTMT_F2P_TRIGACK, + FTMT_F2P_DEBUG, + FTMT_P2F_TRIGACK, + FTMT_P2F_TRIG, + FTMT_P2F_DEBUG, + FCLK_CLK3, + FCLK_CLK2, + FCLK_CLK1, + FCLK_CLK0, + FCLK_CLKTRIG3_N, + FCLK_CLKTRIG2_N, + FCLK_CLKTRIG1_N, + FCLK_CLKTRIG0_N, + FCLK_RESET3_N, + FCLK_RESET2_N, + FCLK_RESET1_N, + FCLK_RESET0_N, + FPGA_IDLE_N, + DDR_ARB, + IRQ_F2P, + Core0_nFIQ, + Core0_nIRQ, + Core1_nFIQ, + Core1_nIRQ, + EVENT_EVENTO, + EVENT_STANDBYWFE, + EVENT_STANDBYWFI, + EVENT_EVENTI, + MIO, + DDR_Clk, + DDR_Clk_n, + DDR_CKE, + DDR_CS_n, + DDR_RAS_n, + DDR_CAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_ODT, + DDR_DRSTB, + DDR_DQ, + DDR_DM, + DDR_DQS, + DDR_DQS_n, + DDR_VRN, + DDR_VRP, + PS_SRSTB, + PS_CLK, + PS_PORB, + IRQ_P2F_DMAC_ABORT, + IRQ_P2F_DMAC0, + IRQ_P2F_DMAC1, + IRQ_P2F_DMAC2, + IRQ_P2F_DMAC3, + IRQ_P2F_DMAC4, + IRQ_P2F_DMAC5, + IRQ_P2F_DMAC6, + IRQ_P2F_DMAC7, + IRQ_P2F_SMC, + IRQ_P2F_QSPI, + IRQ_P2F_CTI, + IRQ_P2F_GPIO, + IRQ_P2F_USB0, + IRQ_P2F_ENET0, + IRQ_P2F_ENET_WAKE0, + IRQ_P2F_SDIO0, + IRQ_P2F_I2C0, + IRQ_P2F_SPI0, + IRQ_P2F_UART0, + IRQ_P2F_CAN0, + IRQ_P2F_USB1, + IRQ_P2F_ENET1, + IRQ_P2F_ENET_WAKE1, + IRQ_P2F_SDIO1, + IRQ_P2F_I2C1, + IRQ_P2F_SPI1, + IRQ_P2F_UART1, + IRQ_P2F_CAN1 + ); + + + /* parameters for gen_clk */ + parameter C_FCLK_CLK0_FREQ = 50; + parameter C_FCLK_CLK1_FREQ = 50; + parameter C_FCLK_CLK3_FREQ = 50; + parameter C_FCLK_CLK2_FREQ = 50; + + parameter C_HIGH_OCM_EN = 0; + + + /* parameters for HP ports */ + parameter C_USE_S_AXI_HP0 = 0; + parameter C_USE_S_AXI_HP1 = 0; + parameter C_USE_S_AXI_HP2 = 0; + parameter C_USE_S_AXI_HP3 = 0; + + parameter C_S_AXI_HP0_DATA_WIDTH = 32; + parameter C_S_AXI_HP1_DATA_WIDTH = 32; + parameter C_S_AXI_HP2_DATA_WIDTH = 32; + parameter C_S_AXI_HP3_DATA_WIDTH = 32; + + parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; + parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; + parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; + parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; + +/* Do we need these + parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */ + + parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000; + + parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF; + + /* parameters for GP and ACP ports */ + parameter C_USE_M_AXI_GP0 = 0; + parameter C_USE_M_AXI_GP1 = 0; + parameter C_USE_S_AXI_GP0 = 1; + parameter C_USE_S_AXI_GP1 = 1; + + /* Do we need this? + parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0; + parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0; + + parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/ + + parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000; + + parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF; + + parameter C_USE_S_AXI_ACP = 1; + parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF; + + `include "processing_system7_vip_v1_0_16_local_params.v" + + output CAN0_PHY_TX; + input CAN0_PHY_RX; + output CAN1_PHY_TX; + input CAN1_PHY_RX; + output ENET0_GMII_TX_EN; + output ENET0_GMII_TX_ER; + output ENET0_MDIO_MDC; + output ENET0_MDIO_O; + output ENET0_MDIO_T; + output ENET0_PTP_DELAY_REQ_RX; + output ENET0_PTP_DELAY_REQ_TX; + output ENET0_PTP_PDELAY_REQ_RX; + output ENET0_PTP_PDELAY_REQ_TX; + output ENET0_PTP_PDELAY_RESP_RX; + output ENET0_PTP_PDELAY_RESP_TX; + output ENET0_PTP_SYNC_FRAME_RX; + output ENET0_PTP_SYNC_FRAME_TX; + output ENET0_SOF_RX; + output ENET0_SOF_TX; + output [7:0] ENET0_GMII_TXD; + input ENET0_GMII_COL; + input ENET0_GMII_CRS; + input ENET0_EXT_INTIN; + input ENET0_GMII_RX_CLK; + input ENET0_GMII_RX_DV; + input ENET0_GMII_RX_ER; + input ENET0_GMII_TX_CLK; + input ENET0_MDIO_I; + input [7:0] ENET0_GMII_RXD; + output ENET1_GMII_TX_EN; + output ENET1_GMII_TX_ER; + output ENET1_MDIO_MDC; + output ENET1_MDIO_O; + output ENET1_MDIO_T; + output ENET1_PTP_DELAY_REQ_RX; + output ENET1_PTP_DELAY_REQ_TX; + output ENET1_PTP_PDELAY_REQ_RX; + output ENET1_PTP_PDELAY_REQ_TX; + output ENET1_PTP_PDELAY_RESP_RX; + output ENET1_PTP_PDELAY_RESP_TX; + output ENET1_PTP_SYNC_FRAME_RX; + output ENET1_PTP_SYNC_FRAME_TX; + output ENET1_SOF_RX; + output ENET1_SOF_TX; + output [7:0] ENET1_GMII_TXD; + input ENET1_GMII_COL; + input ENET1_GMII_CRS; + input ENET1_EXT_INTIN; + input ENET1_GMII_RX_CLK; + input ENET1_GMII_RX_DV; + input ENET1_GMII_RX_ER; + input ENET1_GMII_TX_CLK; + input ENET1_MDIO_I; + input [7:0] ENET1_GMII_RXD; + input [63:0] GPIO_I; + output [63:0] GPIO_O; + output [63:0] GPIO_T; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + input I2C1_SDA_I; + output I2C1_SDA_O; + output I2C1_SDA_T; + input I2C1_SCL_I; + output I2C1_SCL_O; + output I2C1_SCL_T; + input PJTAG_TCK; + input PJTAG_TMS; + input PJTAG_TD_I; + output PJTAG_TD_T; + output PJTAG_TD_O; + output SDIO0_CLK; + input SDIO0_CLK_FB; + output SDIO0_CMD_O; + input SDIO0_CMD_I; + output SDIO0_CMD_T; + input [3:0] SDIO0_DATA_I; + output [3:0] SDIO0_DATA_O; + output [3:0] SDIO0_DATA_T; + output SDIO0_LED; + input SDIO0_CDN; + input SDIO0_WP; + output SDIO0_BUSPOW; + output [2:0] SDIO0_BUSVOLT; + output SDIO1_CLK; + input SDIO1_CLK_FB; + output SDIO1_CMD_O; + input SDIO1_CMD_I; + output SDIO1_CMD_T; + input [3:0] SDIO1_DATA_I; + output [3:0] SDIO1_DATA_O; + output [3:0] SDIO1_DATA_T; + output SDIO1_LED; + input SDIO1_CDN; + input SDIO1_WP; + output SDIO1_BUSPOW; + output [2:0] SDIO1_BUSVOLT; + input SPI0_SCLK_I; + output SPI0_SCLK_O; + output SPI0_SCLK_T; + input SPI0_MOSI_I; + output SPI0_MOSI_O; + output SPI0_MOSI_T; + input SPI0_MISO_I; + output SPI0_MISO_O; + output SPI0_MISO_T; + input SPI0_SS_I; + output SPI0_SS_O; + output SPI0_SS1_O; + output SPI0_SS2_O; + output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output UART0_DTRN; + output UART0_RTSN; + output UART0_TX; + input UART0_CTSN; + input UART0_DCDN; + input UART0_DSRN; + input UART0_RIN; + input UART0_RX; + output UART1_DTRN; + output UART1_RTSN; + output UART1_TX; + input UART1_CTSN; + input UART1_DCDN; + input UART1_DSRN; + input UART1_RIN; + input UART1_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + input TTC0_CLK0_IN; + input TTC0_CLK1_IN; + input TTC0_CLK2_IN; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + input TTC1_CLK0_IN; + input TTC1_CLK1_IN; + input TTC1_CLK2_IN; + input WDT_CLK_IN; + output WDT_RST_OUT; + input TRACE_CLK; + output TRACE_CTL; + output [31:0] TRACE_DATA; + output [1:0] USB0_PORT_INDCTL; + output [1:0] USB1_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + output USB1_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + input USB1_VBUS_PWRFAULT; + input SRAM_INTIN; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID; + output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID; + output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID; + output [1:0] M_AXI_GP0_ARBURST; + output [1:0] M_AXI_GP0_ARLOCK; + output [2:0] M_AXI_GP0_ARSIZE; + output [1:0] M_AXI_GP0_AWBURST; + output [1:0] M_AXI_GP0_AWLOCK; + output [2:0] M_AXI_GP0_AWSIZE; + output [2:0] M_AXI_GP0_ARPROT; + output [2:0] M_AXI_GP0_AWPROT; + output [31:0] M_AXI_GP0_ARADDR; + output [31:0] M_AXI_GP0_AWADDR; + output [31:0] M_AXI_GP0_WDATA; + output [3:0] M_AXI_GP0_ARCACHE; + output [3:0] M_AXI_GP0_ARLEN; + output [3:0] M_AXI_GP0_ARQOS; + output [3:0] M_AXI_GP0_AWCACHE; + output [3:0] M_AXI_GP0_AWLEN; + output [3:0] M_AXI_GP0_AWQOS; + output [3:0] M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID; + input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID; + input [1:0] M_AXI_GP0_BRESP; + input [1:0] M_AXI_GP0_RRESP; + input [31:0] M_AXI_GP0_RDATA; + output M_AXI_GP1_ARVALID; + output M_AXI_GP1_AWVALID; + output M_AXI_GP1_BREADY; + output M_AXI_GP1_RREADY; + output M_AXI_GP1_WLAST; + output M_AXI_GP1_WVALID; + output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID; + output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID; + output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID; + output [1:0] M_AXI_GP1_ARBURST; + output [1:0] M_AXI_GP1_ARLOCK; + output [2:0] M_AXI_GP1_ARSIZE; + output [1:0] M_AXI_GP1_AWBURST; + output [1:0] M_AXI_GP1_AWLOCK; + output [2:0] M_AXI_GP1_AWSIZE; + output [2:0] M_AXI_GP1_ARPROT; + output [2:0] M_AXI_GP1_AWPROT; + output [31:0] M_AXI_GP1_ARADDR; + output [31:0] M_AXI_GP1_AWADDR; + output [31:0] M_AXI_GP1_WDATA; + output [3:0] M_AXI_GP1_ARCACHE; + output [3:0] M_AXI_GP1_ARLEN; + output [3:0] M_AXI_GP1_ARQOS; + output [3:0] M_AXI_GP1_AWCACHE; + output [3:0] M_AXI_GP1_AWLEN; + output [3:0] M_AXI_GP1_AWQOS; + output [3:0] M_AXI_GP1_WSTRB; + input M_AXI_GP1_ACLK; + input M_AXI_GP1_ARREADY; + input M_AXI_GP1_AWREADY; + input M_AXI_GP1_BVALID; + input M_AXI_GP1_RLAST; + input M_AXI_GP1_RVALID; + input M_AXI_GP1_WREADY; + input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID; + input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID; + input [1:0] M_AXI_GP1_BRESP; + input [1:0] M_AXI_GP1_RRESP; + input [31:0] M_AXI_GP1_RDATA; + output S_AXI_GP0_ARREADY; + output S_AXI_GP0_AWREADY; + output S_AXI_GP0_BVALID; + output S_AXI_GP0_RLAST; + output S_AXI_GP0_RVALID; + output S_AXI_GP0_WREADY; + output [1:0] S_AXI_GP0_BRESP; + output [1:0] S_AXI_GP0_RRESP; + output [31:0] S_AXI_GP0_RDATA; + output [5:0] S_AXI_GP0_BID; + output [5:0] S_AXI_GP0_RID; + input S_AXI_GP0_ACLK; + input S_AXI_GP0_ARVALID; + input S_AXI_GP0_AWVALID; + input S_AXI_GP0_BREADY; + input S_AXI_GP0_RREADY; + input S_AXI_GP0_WLAST; + input S_AXI_GP0_WVALID; + input [1:0] S_AXI_GP0_ARBURST; + input [1:0] S_AXI_GP0_ARLOCK; + input [2:0] S_AXI_GP0_ARSIZE; + input [1:0] S_AXI_GP0_AWBURST; + input [1:0] S_AXI_GP0_AWLOCK; + input [2:0] S_AXI_GP0_AWSIZE; + input [2:0] S_AXI_GP0_ARPROT; + input [2:0] S_AXI_GP0_AWPROT; + input [31:0] S_AXI_GP0_ARADDR; + input [31:0] S_AXI_GP0_AWADDR; + input [31:0] S_AXI_GP0_WDATA; + input [3:0] S_AXI_GP0_ARCACHE; + input [3:0] S_AXI_GP0_ARLEN; + input [3:0] S_AXI_GP0_ARQOS; + input [3:0] S_AXI_GP0_AWCACHE; + input [3:0] S_AXI_GP0_AWLEN; + input [3:0] S_AXI_GP0_AWQOS; + input [3:0] S_AXI_GP0_WSTRB; + input [5:0] S_AXI_GP0_ARID; + input [5:0] S_AXI_GP0_AWID; + input [5:0] S_AXI_GP0_WID; + output S_AXI_GP1_ARREADY; + output S_AXI_GP1_AWREADY; + output S_AXI_GP1_BVALID; + output S_AXI_GP1_RLAST; + output S_AXI_GP1_RVALID; + output S_AXI_GP1_WREADY; + output [1:0] S_AXI_GP1_BRESP; + output [1:0] S_AXI_GP1_RRESP; + output [31:0] S_AXI_GP1_RDATA; + output [5:0] S_AXI_GP1_BID; + output [5:0] S_AXI_GP1_RID; + input S_AXI_GP1_ACLK; + input S_AXI_GP1_ARVALID; + input S_AXI_GP1_AWVALID; + input S_AXI_GP1_BREADY; + input S_AXI_GP1_RREADY; + input S_AXI_GP1_WLAST; + input S_AXI_GP1_WVALID; + input [1:0] S_AXI_GP1_ARBURST; + input [1:0] S_AXI_GP1_ARLOCK; + input [2:0] S_AXI_GP1_ARSIZE; + input [1:0] S_AXI_GP1_AWBURST; + input [1:0] S_AXI_GP1_AWLOCK; + input [2:0] S_AXI_GP1_AWSIZE; + input [2:0] S_AXI_GP1_ARPROT; + input [2:0] S_AXI_GP1_AWPROT; + input [31:0] S_AXI_GP1_ARADDR; + input [31:0] S_AXI_GP1_AWADDR; + input [31:0] S_AXI_GP1_WDATA; + input [3:0] S_AXI_GP1_ARCACHE; + input [3:0] S_AXI_GP1_ARLEN; + input [3:0] S_AXI_GP1_ARQOS; + input [3:0] S_AXI_GP1_AWCACHE; + input [3:0] S_AXI_GP1_AWLEN; + input [3:0] S_AXI_GP1_AWQOS; + input [3:0] S_AXI_GP1_WSTRB; + input [5:0] S_AXI_GP1_ARID; + input [5:0] S_AXI_GP1_AWID; + input [5:0] S_AXI_GP1_WID; + output S_AXI_ACP_AWREADY; + output S_AXI_ACP_ARREADY; + output S_AXI_ACP_BVALID; + output S_AXI_ACP_RLAST; + output S_AXI_ACP_RVALID; + output S_AXI_ACP_WREADY; + output [1:0] S_AXI_ACP_BRESP; + output [1:0] S_AXI_ACP_RRESP; + output [2:0] S_AXI_ACP_BID; + output [2:0] S_AXI_ACP_RID; + output [63:0] S_AXI_ACP_RDATA; + input S_AXI_ACP_ACLK; + input S_AXI_ACP_ARVALID; + input S_AXI_ACP_AWVALID; + input S_AXI_ACP_BREADY; + input S_AXI_ACP_RREADY; + input S_AXI_ACP_WLAST; + input S_AXI_ACP_WVALID; + input [2:0] S_AXI_ACP_ARID; + input [2:0] S_AXI_ACP_ARPROT; + input [2:0] S_AXI_ACP_AWID; + input [2:0] S_AXI_ACP_AWPROT; + input [2:0] S_AXI_ACP_WID; + input [31:0] S_AXI_ACP_ARADDR; + input [31:0] S_AXI_ACP_AWADDR; + input [3:0] S_AXI_ACP_ARCACHE; + input [3:0] S_AXI_ACP_ARLEN; + input [3:0] S_AXI_ACP_ARQOS; + input [3:0] S_AXI_ACP_AWCACHE; + input [3:0] S_AXI_ACP_AWLEN; + input [3:0] S_AXI_ACP_AWQOS; + input [1:0] S_AXI_ACP_ARBURST; + input [1:0] S_AXI_ACP_ARLOCK; + input [2:0] S_AXI_ACP_ARSIZE; + input [1:0] S_AXI_ACP_AWBURST; + input [1:0] S_AXI_ACP_AWLOCK; + input [2:0] S_AXI_ACP_AWSIZE; + input [4:0] S_AXI_ACP_ARUSER; + input [4:0] S_AXI_ACP_AWUSER; + input [63:0] S_AXI_ACP_WDATA; + input [7:0] S_AXI_ACP_WSTRB; + output S_AXI_HP0_ARREADY; + output S_AXI_HP0_AWREADY; + output S_AXI_HP0_BVALID; + output S_AXI_HP0_RLAST; + output S_AXI_HP0_RVALID; + output S_AXI_HP0_WREADY; + output [1:0] S_AXI_HP0_BRESP; + output [1:0] S_AXI_HP0_RRESP; + output [5:0] S_AXI_HP0_BID; + output [5:0] S_AXI_HP0_RID; + output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA; + output [7:0] S_AXI_HP0_RCOUNT; + output [7:0] S_AXI_HP0_WCOUNT; + output [2:0] S_AXI_HP0_RACOUNT; + output [5:0] S_AXI_HP0_WACOUNT; + input S_AXI_HP0_ACLK; + input S_AXI_HP0_ARVALID; + input S_AXI_HP0_AWVALID; + input S_AXI_HP0_BREADY; + input S_AXI_HP0_RDISSUECAP1_EN; + input S_AXI_HP0_RREADY; + input S_AXI_HP0_WLAST; + input S_AXI_HP0_WRISSUECAP1_EN; + input S_AXI_HP0_WVALID; + input [1:0] S_AXI_HP0_ARBURST; + input [1:0] S_AXI_HP0_ARLOCK; + input [2:0] S_AXI_HP0_ARSIZE; + input [1:0] S_AXI_HP0_AWBURST; + input [1:0] S_AXI_HP0_AWLOCK; + input [2:0] S_AXI_HP0_AWSIZE; + input [2:0] S_AXI_HP0_ARPROT; + input [2:0] S_AXI_HP0_AWPROT; + input [31:0] S_AXI_HP0_ARADDR; + input [31:0] S_AXI_HP0_AWADDR; + input [3:0] S_AXI_HP0_ARCACHE; + input [3:0] S_AXI_HP0_ARLEN; + input [3:0] S_AXI_HP0_ARQOS; + input [3:0] S_AXI_HP0_AWCACHE; + input [3:0] S_AXI_HP0_AWLEN; + input [3:0] S_AXI_HP0_AWQOS; + input [5:0] S_AXI_HP0_ARID; + input [5:0] S_AXI_HP0_AWID; + input [5:0] S_AXI_HP0_WID; + input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA; + input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB; + output S_AXI_HP1_ARREADY; + output S_AXI_HP1_AWREADY; + output S_AXI_HP1_BVALID; + output S_AXI_HP1_RLAST; + output S_AXI_HP1_RVALID; + output S_AXI_HP1_WREADY; + output [1:0] S_AXI_HP1_BRESP; + output [1:0] S_AXI_HP1_RRESP; + output [5:0] S_AXI_HP1_BID; + output [5:0] S_AXI_HP1_RID; + output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA; + output [7:0] S_AXI_HP1_RCOUNT; + output [7:0] S_AXI_HP1_WCOUNT; + output [2:0] S_AXI_HP1_RACOUNT; + output [5:0] S_AXI_HP1_WACOUNT; + input S_AXI_HP1_ACLK; + input S_AXI_HP1_ARVALID; + input S_AXI_HP1_AWVALID; + input S_AXI_HP1_BREADY; + input S_AXI_HP1_RDISSUECAP1_EN; + input S_AXI_HP1_RREADY; + input S_AXI_HP1_WLAST; + input S_AXI_HP1_WRISSUECAP1_EN; + input S_AXI_HP1_WVALID; + input [1:0] S_AXI_HP1_ARBURST; + input [1:0] S_AXI_HP1_ARLOCK; + input [2:0] S_AXI_HP1_ARSIZE; + input [1:0] S_AXI_HP1_AWBURST; + input [1:0] S_AXI_HP1_AWLOCK; + input [2:0] S_AXI_HP1_AWSIZE; + input [2:0] S_AXI_HP1_ARPROT; + input [2:0] S_AXI_HP1_AWPROT; + input [31:0] S_AXI_HP1_ARADDR; + input [31:0] S_AXI_HP1_AWADDR; + input [3:0] S_AXI_HP1_ARCACHE; + input [3:0] S_AXI_HP1_ARLEN; + input [3:0] S_AXI_HP1_ARQOS; + input [3:0] S_AXI_HP1_AWCACHE; + input [3:0] S_AXI_HP1_AWLEN; + input [3:0] S_AXI_HP1_AWQOS; + input [5:0] S_AXI_HP1_ARID; + input [5:0] S_AXI_HP1_AWID; + input [5:0] S_AXI_HP1_WID; + input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA; + input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB; + output S_AXI_HP2_ARREADY; + output S_AXI_HP2_AWREADY; + output S_AXI_HP2_BVALID; + output S_AXI_HP2_RLAST; + output S_AXI_HP2_RVALID; + output S_AXI_HP2_WREADY; + output [1:0] S_AXI_HP2_BRESP; + output [1:0] S_AXI_HP2_RRESP; + output [5:0] S_AXI_HP2_BID; + output [5:0] S_AXI_HP2_RID; + output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA; + output [7:0] S_AXI_HP2_RCOUNT; + output [7:0] S_AXI_HP2_WCOUNT; + output [2:0] S_AXI_HP2_RACOUNT; + output [5:0] S_AXI_HP2_WACOUNT; + input S_AXI_HP2_ACLK; + input S_AXI_HP2_ARVALID; + input S_AXI_HP2_AWVALID; + input S_AXI_HP2_BREADY; + input S_AXI_HP2_RDISSUECAP1_EN; + input S_AXI_HP2_RREADY; + input S_AXI_HP2_WLAST; + input S_AXI_HP2_WRISSUECAP1_EN; + input S_AXI_HP2_WVALID; + input [1:0] S_AXI_HP2_ARBURST; + input [1:0] S_AXI_HP2_ARLOCK; + input [2:0] S_AXI_HP2_ARSIZE; + input [1:0] S_AXI_HP2_AWBURST; + input [1:0] S_AXI_HP2_AWLOCK; + input [2:0] S_AXI_HP2_AWSIZE; + input [2:0] S_AXI_HP2_ARPROT; + input [2:0] S_AXI_HP2_AWPROT; + input [31:0] S_AXI_HP2_ARADDR; + input [31:0] S_AXI_HP2_AWADDR; + input [3:0] S_AXI_HP2_ARCACHE; + input [3:0] S_AXI_HP2_ARLEN; + input [3:0] S_AXI_HP2_ARQOS; + input [3:0] S_AXI_HP2_AWCACHE; + input [3:0] S_AXI_HP2_AWLEN; + input [3:0] S_AXI_HP2_AWQOS; + input [5:0] S_AXI_HP2_ARID; + input [5:0] S_AXI_HP2_AWID; + input [5:0] S_AXI_HP2_WID; + input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA; + input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB; + output S_AXI_HP3_ARREADY; + output S_AXI_HP3_AWREADY; + output S_AXI_HP3_BVALID; + output S_AXI_HP3_RLAST; + output S_AXI_HP3_RVALID; + output S_AXI_HP3_WREADY; + output [1:0] S_AXI_HP3_BRESP; + output [1:0] S_AXI_HP3_RRESP; + output [5:0] S_AXI_HP3_BID; + output [5:0] S_AXI_HP3_RID; + output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA; + output [7:0] S_AXI_HP3_RCOUNT; + output [7:0] S_AXI_HP3_WCOUNT; + output [2:0] S_AXI_HP3_RACOUNT; + output [5:0] S_AXI_HP3_WACOUNT; + input S_AXI_HP3_ACLK; + input S_AXI_HP3_ARVALID; + input S_AXI_HP3_AWVALID; + input S_AXI_HP3_BREADY; + input S_AXI_HP3_RDISSUECAP1_EN; + input S_AXI_HP3_RREADY; + input S_AXI_HP3_WLAST; + input S_AXI_HP3_WRISSUECAP1_EN; + input S_AXI_HP3_WVALID; + input [1:0] S_AXI_HP3_ARBURST; + input [1:0] S_AXI_HP3_ARLOCK; + input [2:0] S_AXI_HP3_ARSIZE; + input [1:0] S_AXI_HP3_AWBURST; + input [1:0] S_AXI_HP3_AWLOCK; + input [2:0] S_AXI_HP3_AWSIZE; + input [2:0] S_AXI_HP3_ARPROT; + input [2:0] S_AXI_HP3_AWPROT; + input [31:0] S_AXI_HP3_ARADDR; + input [31:0] S_AXI_HP3_AWADDR; + input [3:0] S_AXI_HP3_ARCACHE; + input [3:0] S_AXI_HP3_ARLEN; + input [3:0] S_AXI_HP3_ARQOS; + input [3:0] S_AXI_HP3_AWCACHE; + input [3:0] S_AXI_HP3_AWLEN; + input [3:0] S_AXI_HP3_AWQOS; + input [5:0] S_AXI_HP3_ARID; + input [5:0] S_AXI_HP3_AWID; + input [5:0] S_AXI_HP3_WID; + input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA; + input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB; + output [1:0] DMA0_DATYPE; + output DMA0_DAVALID; + output DMA0_DRREADY; + input DMA0_ACLK; + input DMA0_DAREADY; + input DMA0_DRLAST; + input DMA0_DRVALID; + input [1:0] DMA0_DRTYPE; + output [1:0] DMA1_DATYPE; + output DMA1_DAVALID; + output DMA1_DRREADY; + input DMA1_ACLK; + input DMA1_DAREADY; + input DMA1_DRLAST; + input DMA1_DRVALID; + input [1:0] DMA1_DRTYPE; + output [1:0] DMA2_DATYPE; + output DMA2_DAVALID; + output DMA2_DRREADY; + input DMA2_ACLK; + input DMA2_DAREADY; + input DMA2_DRLAST; + input DMA2_DRVALID; + input DMA3_DRVALID; + output [1:0] DMA3_DATYPE; + output DMA3_DAVALID; + output DMA3_DRREADY; + input DMA3_ACLK; + input DMA3_DAREADY; + input DMA3_DRLAST; + input [1:0] DMA2_DRTYPE; + input [1:0] DMA3_DRTYPE; + input [31:0] FTMD_TRACEIN_DATA; + input FTMD_TRACEIN_VALID; + input FTMD_TRACEIN_CLK; + input [3:0] FTMD_TRACEIN_ATID; + input [3:0] FTMT_F2P_TRIG; + output [3:0] FTMT_F2P_TRIGACK; + input [31:0] FTMT_F2P_DEBUG; + input [3:0] FTMT_P2F_TRIGACK; + output [3:0] FTMT_P2F_TRIG; + output [31:0] FTMT_P2F_DEBUG; + output FCLK_CLK3; + output FCLK_CLK2; + output FCLK_CLK1; + output FCLK_CLK0; + input FCLK_CLKTRIG3_N; + input FCLK_CLKTRIG2_N; + input FCLK_CLKTRIG1_N; + input FCLK_CLKTRIG0_N; + output FCLK_RESET3_N; + output FCLK_RESET2_N; + output FCLK_RESET1_N; + output FCLK_RESET0_N; + input FPGA_IDLE_N; + input [3:0] DDR_ARB; + input [irq_width-1:0] IRQ_F2P; + input Core0_nFIQ; + input Core0_nIRQ; + input Core1_nFIQ; + input Core1_nIRQ; + output EVENT_EVENTO; + output [1:0] EVENT_STANDBYWFE; + output [1:0] EVENT_STANDBYWFI; + input EVENT_EVENTI; + inout [53:0] MIO; + inout DDR_Clk; + inout DDR_Clk_n; + inout DDR_CKE; + inout DDR_CS_n; + inout DDR_RAS_n; + inout DDR_CAS_n; + output DDR_WEB; + inout [2:0] DDR_BankAddr; + inout [14:0] DDR_Addr; + inout DDR_ODT; + inout DDR_DRSTB; + inout [31:0] DDR_DQ; + inout [3:0] DDR_DM; + inout [3:0] DDR_DQS; + inout [3:0] DDR_DQS_n; + inout DDR_VRN; + inout DDR_VRP; +/* Reset Input & Clock Input */ + input PS_SRSTB; + input PS_CLK; + input PS_PORB; + output IRQ_P2F_DMAC_ABORT; + output IRQ_P2F_DMAC0; + output IRQ_P2F_DMAC1; + output IRQ_P2F_DMAC2; + output IRQ_P2F_DMAC3; + output IRQ_P2F_DMAC4; + output IRQ_P2F_DMAC5; + output IRQ_P2F_DMAC6; + output IRQ_P2F_DMAC7; + output IRQ_P2F_SMC; + output IRQ_P2F_QSPI; + output IRQ_P2F_CTI; + output IRQ_P2F_GPIO; + output IRQ_P2F_USB0; + output IRQ_P2F_ENET0; + output IRQ_P2F_ENET_WAKE0; + output IRQ_P2F_SDIO0; + output IRQ_P2F_I2C0; + output IRQ_P2F_SPI0; + output IRQ_P2F_UART0; + output IRQ_P2F_CAN0; + output IRQ_P2F_USB1; + output IRQ_P2F_ENET1; + output IRQ_P2F_ENET_WAKE1; + output IRQ_P2F_SDIO1; + output IRQ_P2F_I2C1; + output IRQ_P2F_SPI1; + output IRQ_P2F_UART1; + output IRQ_P2F_CAN1; + + + /* Internal wires/nets used for connectivity */ + wire net_rstn; + wire net_sw_clk; + wire net_ocm_clk; + wire net_arbiter_clk; + + wire net_axi_mgp0_rstn; + wire net_axi_mgp1_rstn; + wire net_axi_gp0_rstn; + wire net_axi_gp1_rstn; + wire net_axi_hp0_rstn; + wire net_axi_hp1_rstn; + wire net_axi_hp2_rstn; + wire net_axi_hp3_rstn; + wire net_axi_acp_rstn; + wire [4:0] net_axi_acp_awuser; + wire [4:0] net_axi_acp_aruser; + + + /* Dummy */ + assign net_axi_acp_awuser = S_AXI_ACP_AWUSER; + assign net_axi_acp_aruser = S_AXI_ACP_ARUSER; + + /* Global variables */ + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1; + + /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ + reg mem_update_key = 1; + reg reg_update_key_0 = 1; + reg reg_update_key_1 = 1; + + /* assignments and semantic checks for unused ports */ + `include "processing_system7_vip_v1_0_16_unused_ports.v" + + /* include api definition */ + `include "processing_system7_vip_v1_0_16_apis.v" + + /* Reset Generator */ + processing_system7_vip_v1_0_16_gen_reset gen_rst(.por_rst_n(PS_PORB), + .sys_rst_n(PS_SRSTB), + .rst_out_n(net_rstn), + + .m_axi_gp0_clk(M_AXI_GP0_ACLK), + .m_axi_gp1_clk(M_AXI_GP1_ACLK), + .s_axi_gp0_clk(S_AXI_GP0_ACLK), + .s_axi_gp1_clk(S_AXI_GP1_ACLK), + .s_axi_hp0_clk(S_AXI_HP0_ACLK), + .s_axi_hp1_clk(S_AXI_HP1_ACLK), + .s_axi_hp2_clk(S_AXI_HP2_ACLK), + .s_axi_hp3_clk(S_AXI_HP3_ACLK), + .s_axi_acp_clk(S_AXI_ACP_ACLK), + + .m_axi_gp0_rstn(net_axi_mgp0_rstn), + .m_axi_gp1_rstn(net_axi_mgp1_rstn), + .s_axi_gp0_rstn(net_axi_gp0_rstn), + .s_axi_gp1_rstn(net_axi_gp1_rstn), + .s_axi_hp0_rstn(net_axi_hp0_rstn), + .s_axi_hp1_rstn(net_axi_hp1_rstn), + .s_axi_hp2_rstn(net_axi_hp2_rstn), + .s_axi_hp3_rstn(net_axi_hp3_rstn), + .s_axi_acp_rstn(net_axi_acp_rstn), + + .fclk_reset3_n(FCLK_RESET3_N), + .fclk_reset2_n(FCLK_RESET2_N), + .fclk_reset1_n(FCLK_RESET1_N), + .fclk_reset0_n(FCLK_RESET0_N), + + .fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP) + .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN), + .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN), + .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN), + .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN), + .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN), + .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN), + .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN), + .fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN) + ); + + /* Clock Generator */ + processing_system7_vip_v1_0_16_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ) + gen_clk(.ps_clk(PS_CLK), + .sw_clk(net_sw_clk), + + .fclk_clk3(FCLK_CLK3), + .fclk_clk2(FCLK_CLK2), + .fclk_clk1(FCLK_CLK1), + .fclk_clk0(FCLK_CLK0) + ); + + wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1; + wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1; + wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1; + wire [max_burst_bytes-1:0] net_wr_strb_gp0, net_wr_strb_gp1; + wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1; + wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1; + wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1; + + wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1; + wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1; + wire net_rd_req_reg_gp0, net_rd_req_reg_gp1; + wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1; + wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1; + wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1; + wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1; + wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1; + wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1; + wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1; + wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1; + wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1; + + wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3; + wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3; + wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3; + wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3; + wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3; + wire [max_burst_bytes-1:0] net_wr_strb_hp0, net_wr_strb_hp1, net_wr_strb_hp2, net_wr_strb_hp3; + wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3; + wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3; + wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3; + + wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3; + wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3; + wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3; + wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3; + wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3; + wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3; + wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3; + wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3; + wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3; + + wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp; + wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp; + wire [max_burst_bits-1:0] net_wr_data_acp; + wire [max_burst_bytes-1:0] net_wr_strb_acp; + wire [addr_width-1:0] net_wr_addr_acp; + wire [max_burst_bytes_width:0] net_wr_bytes_acp; + wire [axi_qos_width-1:0] net_wr_qos_acp; + + wire net_rd_req_ddr_acp, net_rd_req_ocm_acp; + wire [addr_width-1:0] net_rd_addr_acp; + wire [max_burst_bytes_width:0] net_rd_bytes_acp; + wire [max_burst_bits-1:0] net_rd_data_ddr_acp; + wire [max_burst_bits-1:0] net_rd_data_ocm_acp; + wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp; + wire [axi_qos_width-1:0] net_rd_qos_acp; + + wire ocm_wr_ack_port0; + wire ocm_wr_dv_port0; + wire ocm_rd_req_port0; + wire ocm_rd_dv_port0; + wire [addr_width-1:0] ocm_wr_addr_port0; + wire [max_burst_bits-1:0] ocm_wr_data_port0; + wire [max_burst_bytes-1:0] ocm_wr_strb_port0; + wire [max_burst_bytes_width:0] ocm_wr_bytes_port0; + wire [addr_width-1:0] ocm_rd_addr_port0; + wire [max_burst_bits-1:0] ocm_rd_data_port0; + wire [max_burst_bytes_width:0] ocm_rd_bytes_port0; + wire [axi_qos_width-1:0] ocm_wr_qos_port0; + wire [axi_qos_width-1:0] ocm_rd_qos_port0; + + wire ocm_wr_ack_port1; + wire ocm_wr_dv_port1; + wire ocm_rd_req_port1; + wire ocm_rd_dv_port1; + wire [addr_width-1:0] ocm_wr_addr_port1; + wire [max_burst_bits-1:0] ocm_wr_data_port1; + wire [max_burst_bytes-1:0] ocm_wr_strb_port1; + wire [max_burst_bytes_width:0] ocm_wr_bytes_port1; + wire [addr_width-1:0] ocm_rd_addr_port1; + wire [max_burst_bits-1:0] ocm_rd_data_port1; + wire [max_burst_bytes_width:0] ocm_rd_bytes_port1; + wire [axi_qos_width-1:0] ocm_wr_qos_port1; + wire [axi_qos_width-1:0] ocm_rd_qos_port1; + + wire ddr_wr_ack_port0; + wire ddr_wr_dv_port0; + wire ddr_rd_req_port0; + wire ddr_rd_dv_port0; + wire[addr_width-1:0] ddr_wr_addr_port0; + wire[max_burst_bits-1:0] ddr_wr_data_port0; + wire[max_burst_bytes-1:0] ddr_wr_strb_port0; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port0; + wire[addr_width-1:0] ddr_rd_addr_port0; + wire[max_burst_bits-1:0] ddr_rd_data_port0; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port0; + wire [axi_qos_width-1:0] ddr_wr_qos_port0; + wire [axi_qos_width-1:0] ddr_rd_qos_port0; + + wire ddr_wr_ack_port1; + wire ddr_wr_dv_port1; + wire ddr_rd_req_port1; + wire ddr_rd_dv_port1; + wire[addr_width-1:0] ddr_wr_addr_port1; + wire[max_burst_bits-1:0] ddr_wr_data_port1; + wire[max_burst_bytes-1:0] ddr_wr_strb_port1; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port1; + wire[addr_width-1:0] ddr_rd_addr_port1; + wire[max_burst_bits-1:0] ddr_rd_data_port1; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port1; + wire[axi_qos_width-1:0] ddr_wr_qos_port1; + wire[axi_qos_width-1:0] ddr_rd_qos_port1; + + wire ddr_wr_ack_port2; + wire ddr_wr_dv_port2; + wire ddr_rd_req_port2; + wire ddr_rd_dv_port2; + wire[addr_width-1:0] ddr_wr_addr_port2; + wire[max_burst_bits-1:0] ddr_wr_data_port2; + wire[max_burst_bytes-1:0] ddr_wr_strb_port2; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port2; + wire[addr_width-1:0] ddr_rd_addr_port2; + wire[max_burst_bits-1:0] ddr_rd_data_port2; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port2; + wire[axi_qos_width-1:0] ddr_wr_qos_port2; + wire[axi_qos_width-1:0] ddr_rd_qos_port2; + + wire ddr_wr_ack_port3; + wire ddr_wr_dv_port3; + wire ddr_rd_req_port3; + wire ddr_rd_dv_port3; + wire[addr_width-1:0] ddr_wr_addr_port3; + wire[max_burst_bits-1:0] ddr_wr_data_port3; + wire[max_burst_bytes-1:0] ddr_wr_strb_port3; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port3; + wire[addr_width-1:0] ddr_rd_addr_port3; + wire[max_burst_bits-1:0] ddr_rd_data_port3; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port3; + wire[axi_qos_width-1:0] ddr_wr_qos_port3; + wire[axi_qos_width-1:0] ddr_rd_qos_port3; + + wire reg_rd_req_port0; + wire reg_rd_dv_port0; + wire[addr_width-1:0] reg_rd_addr_port0; + wire[max_burst_bits-1:0] reg_rd_data_port0; + wire[max_burst_bytes_width:0] reg_rd_bytes_port0; + wire [axi_qos_width-1:0] reg_rd_qos_port0; + + wire reg_rd_req_port1; + wire reg_rd_dv_port1; + wire[addr_width-1:0] reg_rd_addr_port1; + wire[max_burst_bits-1:0] reg_rd_data_port1; + wire[max_burst_bytes_width:0] reg_rd_bytes_port1; + wire [axi_qos_width-1:0] reg_rd_qos_port1; + + wire [11:0] M_AXI_GP0_AWID_FULL; + wire [11:0] M_AXI_GP0_WID_FULL; + wire [11:0] M_AXI_GP0_ARID_FULL; + + wire [11:0] M_AXI_GP0_BID_FULL; + wire [11:0] M_AXI_GP0_RID_FULL; + + wire [11:0] M_AXI_GP1_AWID_FULL; + wire [11:0] M_AXI_GP1_WID_FULL; + wire [11:0] M_AXI_GP1_ARID_FULL; + + wire [11:0] M_AXI_GP1_BID_FULL; + wire [11:0] M_AXI_GP1_RID_FULL; + + + function [5:0] compress_id; + input [11:0] id; + begin + compress_id = id[5:0]; + end + endfunction + + function [11:0] uncompress_id; + input [5:0] id; + begin + uncompress_id = {6'b110000, id[5:0]}; + end + endfunction + + assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; + assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; + assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; + assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; + assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; + + + assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; + assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; + assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; + assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; + assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; + + + + + processing_system7_vip_v1_0_16_interconnect_model icm ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + .w_qos_gp0(net_wr_qos_gp0), + .w_qos_gp1(net_wr_qos_gp1), + .w_qos_hp0(net_wr_qos_hp0), + .w_qos_hp1(net_wr_qos_hp1), + .w_qos_hp2(net_wr_qos_hp2), + .w_qos_hp3(net_wr_qos_hp3), + + .r_qos_gp0(net_rd_qos_gp0), + .r_qos_gp1(net_rd_qos_gp1), + .r_qos_hp0(net_rd_qos_hp0), + .r_qos_hp1(net_rd_qos_hp1), + .r_qos_hp2(net_rd_qos_hp2), + .r_qos_hp3(net_rd_qos_hp3), + + /* GP Slave ports access */ + .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0), + .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0), + .wr_data_gp0(net_wr_data_gp0), + .wr_strb_gp0(net_wr_strb_gp0), + .wr_addr_gp0(net_wr_addr_gp0), + .wr_bytes_gp0(net_wr_bytes_gp0), + .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0), + .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0), + .rd_req_ddr_gp0(net_rd_req_ddr_gp0), + .rd_req_ocm_gp0(net_rd_req_ocm_gp0), + .rd_req_reg_gp0(net_rd_req_reg_gp0), + .rd_addr_gp0(net_rd_addr_gp0), + .rd_bytes_gp0(net_rd_bytes_gp0), + .rd_data_ddr_gp0(net_rd_data_ddr_gp0), + .rd_data_ocm_gp0(net_rd_data_ocm_gp0), + .rd_data_reg_gp0(net_rd_data_reg_gp0), + .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0), + .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0), + .rd_dv_reg_gp0(net_rd_dv_reg_gp0), + + .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1), + .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1), + .wr_data_gp1(net_wr_data_gp1), + .wr_strb_gp1(net_wr_strb_gp1), + .wr_addr_gp1(net_wr_addr_gp1), + .wr_bytes_gp1(net_wr_bytes_gp1), + .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1), + .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1), + .rd_req_ddr_gp1(net_rd_req_ddr_gp1), + .rd_req_ocm_gp1(net_rd_req_ocm_gp1), + .rd_req_reg_gp1(net_rd_req_reg_gp1), + .rd_addr_gp1(net_rd_addr_gp1), + .rd_bytes_gp1(net_rd_bytes_gp1), + .rd_data_ddr_gp1(net_rd_data_ddr_gp1), + .rd_data_ocm_gp1(net_rd_data_ocm_gp1), + .rd_data_reg_gp1(net_rd_data_reg_gp1), + .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1), + .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1), + .rd_dv_reg_gp1(net_rd_dv_reg_gp1), + + /* HP Slave ports access */ + .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0), + .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0), + .wr_data_hp0(net_wr_data_hp0), + .wr_strb_hp0(net_wr_strb_hp0), + .wr_addr_hp0(net_wr_addr_hp0), + .wr_bytes_hp0(net_wr_bytes_hp0), + .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0), + .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0), + .rd_req_ddr_hp0(net_rd_req_ddr_hp0), + .rd_req_ocm_hp0(net_rd_req_ocm_hp0), + .rd_addr_hp0(net_rd_addr_hp0), + .rd_bytes_hp0(net_rd_bytes_hp0), + .rd_data_ddr_hp0(net_rd_data_ddr_hp0), + .rd_data_ocm_hp0(net_rd_data_ocm_hp0), + .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0), + .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0), + + .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1), + .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1), + .wr_data_hp1(net_wr_data_hp1), + .wr_strb_hp1(net_wr_strb_hp1), + .wr_addr_hp1(net_wr_addr_hp1), + .wr_bytes_hp1(net_wr_bytes_hp1), + .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1), + .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1), + .rd_req_ddr_hp1(net_rd_req_ddr_hp1), + .rd_req_ocm_hp1(net_rd_req_ocm_hp1), + .rd_addr_hp1(net_rd_addr_hp1), + .rd_bytes_hp1(net_rd_bytes_hp1), + .rd_data_ddr_hp1(net_rd_data_ddr_hp1), + .rd_data_ocm_hp1(net_rd_data_ocm_hp1), + .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1), + .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1), + + .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2), + .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2), + .wr_data_hp2(net_wr_data_hp2), + .wr_strb_hp2(net_wr_strb_hp2), + .wr_addr_hp2(net_wr_addr_hp2), + .wr_bytes_hp2(net_wr_bytes_hp2), + .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2), + .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2), + .rd_req_ddr_hp2(net_rd_req_ddr_hp2), + .rd_req_ocm_hp2(net_rd_req_ocm_hp2), + .rd_addr_hp2(net_rd_addr_hp2), + .rd_bytes_hp2(net_rd_bytes_hp2), + .rd_data_ddr_hp2(net_rd_data_ddr_hp2), + .rd_data_ocm_hp2(net_rd_data_ocm_hp2), + .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2), + .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2), + + .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3), + .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3), + .wr_data_hp3(net_wr_data_hp3), + .wr_strb_hp3(net_wr_strb_hp3), + .wr_addr_hp3(net_wr_addr_hp3), + .wr_bytes_hp3(net_wr_bytes_hp3), + .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3), + .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3), + .rd_req_ddr_hp3(net_rd_req_ddr_hp3), + .rd_req_ocm_hp3(net_rd_req_ocm_hp3), + .rd_addr_hp3(net_rd_addr_hp3), + .rd_bytes_hp3(net_rd_bytes_hp3), + .rd_data_ddr_hp3(net_rd_data_ddr_hp3), + .rd_data_ocm_hp3(net_rd_data_ocm_hp3), + .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3), + .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3), + + /* Goes to port 1 of DDR */ + .ddr_wr_ack_port1(ddr_wr_ack_port1), + .ddr_wr_dv_port1(ddr_wr_dv_port1), + .ddr_rd_req_port1(ddr_rd_req_port1), + .ddr_rd_dv_port1 (ddr_rd_dv_port1), + .ddr_wr_addr_port1(ddr_wr_addr_port1), + .ddr_wr_data_port1(ddr_wr_data_port1), + .ddr_wr_strb_port1(ddr_wr_strb_port1), + .ddr_wr_bytes_port1(ddr_wr_bytes_port1), + .ddr_rd_addr_port1(ddr_rd_addr_port1), + .ddr_rd_data_port1(ddr_rd_data_port1), + .ddr_rd_bytes_port1(ddr_rd_bytes_port1), + .ddr_wr_qos_port1(ddr_wr_qos_port1), + .ddr_rd_qos_port1(ddr_rd_qos_port1), + + /* Goes to port2 of DDR */ + .ddr_wr_ack_port2 (ddr_wr_ack_port2), + .ddr_wr_dv_port2 (ddr_wr_dv_port2), + .ddr_rd_req_port2 (ddr_rd_req_port2), + .ddr_rd_dv_port2 (ddr_rd_dv_port2), + .ddr_wr_addr_port2(ddr_wr_addr_port2), + .ddr_wr_data_port2(ddr_wr_data_port2), + .ddr_wr_strb_port2(ddr_wr_strb_port2), + .ddr_wr_bytes_port2(ddr_wr_bytes_port2), + .ddr_rd_addr_port2(ddr_rd_addr_port2), + .ddr_rd_data_port2(ddr_rd_data_port2), + .ddr_rd_bytes_port2(ddr_rd_bytes_port2), + .ddr_wr_qos_port2 (ddr_wr_qos_port2), + .ddr_rd_qos_port2 (ddr_rd_qos_port2), + + /* Goes to port3 of DDR */ + .ddr_wr_ack_port3 (ddr_wr_ack_port3), + .ddr_wr_dv_port3 (ddr_wr_dv_port3), + .ddr_rd_req_port3 (ddr_rd_req_port3), + .ddr_rd_dv_port3 (ddr_rd_dv_port3), + .ddr_wr_addr_port3(ddr_wr_addr_port3), + .ddr_wr_data_port3(ddr_wr_data_port3), + .ddr_wr_strb_port3(ddr_wr_strb_port3), + .ddr_wr_bytes_port3(ddr_wr_bytes_port3), + .ddr_rd_addr_port3(ddr_rd_addr_port3), + .ddr_rd_data_port3(ddr_rd_data_port3), + .ddr_rd_bytes_port3(ddr_rd_bytes_port3), + .ddr_wr_qos_port3 (ddr_wr_qos_port3), + .ddr_rd_qos_port3 (ddr_rd_qos_port3), + + /* Goes to port 0 of OCM */ + .ocm_wr_ack_port1 (ocm_wr_ack_port1), + .ocm_wr_dv_port1 (ocm_wr_dv_port1), + .ocm_rd_req_port1 (ocm_rd_req_port1), + .ocm_rd_dv_port1 (ocm_rd_dv_port1), + .ocm_wr_addr_port1(ocm_wr_addr_port1), + .ocm_wr_data_port1(ocm_wr_data_port1), + .ocm_wr_strb_port1(ocm_wr_strb_port1), + .ocm_wr_bytes_port1(ocm_wr_bytes_port1), + .ocm_rd_addr_port1(ocm_rd_addr_port1), + .ocm_rd_data_port1(ocm_rd_data_port1), + .ocm_rd_bytes_port1(ocm_rd_bytes_port1), + .ocm_wr_qos_port1(ocm_wr_qos_port1), + .ocm_rd_qos_port1(ocm_rd_qos_port1), + + /* Goes to port 0 of REG */ + .reg_rd_qos_port1 (reg_rd_qos_port1) , + .reg_rd_req_port1 (reg_rd_req_port1), + .reg_rd_dv_port1 (reg_rd_dv_port1), + .reg_rd_addr_port1(reg_rd_addr_port1), + .reg_rd_data_port1(reg_rd_data_port1), + .reg_rd_bytes_port1(reg_rd_bytes_port1) + ); + + processing_system7_vip_v1_0_16_ddrc ddrc ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + /* Goes to port 0 of DDR */ + .ddr_wr_ack_port0 (ddr_wr_ack_port0), + .ddr_wr_dv_port0 (ddr_wr_dv_port0), + .ddr_rd_req_port0 (ddr_rd_req_port0), + .ddr_rd_dv_port0 (ddr_rd_dv_port0), + + .ddr_wr_addr_port0(net_wr_addr_acp), + .ddr_wr_data_port0(net_wr_data_acp), + .ddr_wr_strb_port0(net_wr_strb_acp), + .ddr_wr_bytes_port0(net_wr_bytes_acp), + + .ddr_rd_addr_port0(net_rd_addr_acp), + .ddr_rd_bytes_port0(net_rd_bytes_acp), + + .ddr_rd_data_port0(ddr_rd_data_port0), + + .ddr_wr_qos_port0 (net_wr_qos_acp), + .ddr_rd_qos_port0 (net_rd_qos_acp), + + + /* Goes to port 1 of DDR */ + .ddr_wr_ack_port1 (ddr_wr_ack_port1), + .ddr_wr_dv_port1 (ddr_wr_dv_port1), + .ddr_rd_req_port1 (ddr_rd_req_port1), + .ddr_rd_dv_port1 (ddr_rd_dv_port1), + .ddr_wr_addr_port1(ddr_wr_addr_port1), + .ddr_wr_data_port1(ddr_wr_data_port1), + .ddr_wr_strb_port1(ddr_wr_strb_port1), + .ddr_wr_bytes_port1(ddr_wr_bytes_port1), + .ddr_rd_addr_port1(ddr_rd_addr_port1), + .ddr_rd_data_port1(ddr_rd_data_port1), + .ddr_rd_bytes_port1(ddr_rd_bytes_port1), + .ddr_wr_qos_port1 (ddr_wr_qos_port1), + .ddr_rd_qos_port1 (ddr_rd_qos_port1), + + /* Goes to port2 of DDR */ + .ddr_wr_ack_port2 (ddr_wr_ack_port2), + .ddr_wr_dv_port2 (ddr_wr_dv_port2), + .ddr_rd_req_port2 (ddr_rd_req_port2), + .ddr_rd_dv_port2 (ddr_rd_dv_port2), + .ddr_wr_addr_port2(ddr_wr_addr_port2), + .ddr_wr_data_port2(ddr_wr_data_port2), + .ddr_wr_strb_port2(ddr_wr_strb_port2), + .ddr_wr_bytes_port2(ddr_wr_bytes_port2), + .ddr_rd_addr_port2(ddr_rd_addr_port2), + .ddr_rd_data_port2(ddr_rd_data_port2), + .ddr_rd_bytes_port2(ddr_rd_bytes_port2), + .ddr_wr_qos_port2 (ddr_wr_qos_port2), + .ddr_rd_qos_port2 (ddr_rd_qos_port2), + + /* Goes to port3 of DDR */ + .ddr_wr_ack_port3 (ddr_wr_ack_port3), + .ddr_wr_dv_port3 (ddr_wr_dv_port3), + .ddr_rd_req_port3 (ddr_rd_req_port3), + .ddr_rd_dv_port3 (ddr_rd_dv_port3), + .ddr_wr_addr_port3(ddr_wr_addr_port3), + .ddr_wr_data_port3(ddr_wr_data_port3), + .ddr_wr_strb_port3(ddr_wr_strb_port3), + .ddr_wr_bytes_port3(ddr_wr_bytes_port3), + .ddr_rd_addr_port3(ddr_rd_addr_port3), + .ddr_rd_data_port3(ddr_rd_data_port3), + .ddr_rd_bytes_port3(ddr_rd_bytes_port3), + .ddr_wr_qos_port3 (ddr_wr_qos_port3), + .ddr_rd_qos_port3 (ddr_rd_qos_port3) + + ); + + processing_system7_vip_v1_0_16_ocmc ocmc ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + /* Goes to port 0 of OCM */ + .ocm_wr_ack_port0 (ocm_wr_ack_port0), + .ocm_wr_dv_port0 (ocm_wr_dv_port0), + .ocm_rd_req_port0 (ocm_rd_req_port0), + .ocm_rd_dv_port0 (ocm_rd_dv_port0), + + .ocm_wr_addr_port0(net_wr_addr_acp), + .ocm_wr_data_port0(net_wr_data_acp), + .ocm_wr_strb_port0(net_wr_strb_acp), + .ocm_wr_bytes_port0(net_wr_bytes_acp), + + .ocm_rd_addr_port0(net_rd_addr_acp), + .ocm_rd_bytes_port0(net_rd_bytes_acp), + + .ocm_rd_data_port0(ocm_rd_data_port0), + + .ocm_wr_qos_port0 (net_wr_qos_acp), + .ocm_rd_qos_port0 (net_rd_qos_acp), + + /* Goes to port 1 of OCM */ + .ocm_wr_ack_port1 (ocm_wr_ack_port1), + .ocm_wr_dv_port1 (ocm_wr_dv_port1), + .ocm_rd_req_port1 (ocm_rd_req_port1), + .ocm_rd_dv_port1 (ocm_rd_dv_port1), + .ocm_wr_addr_port1(ocm_wr_addr_port1), + .ocm_wr_data_port1(ocm_wr_data_port1), + .ocm_wr_strb_port1(ocm_wr_strb_port1), + .ocm_wr_bytes_port1(ocm_wr_bytes_port1), + .ocm_rd_addr_port1(ocm_rd_addr_port1), + .ocm_rd_data_port1(ocm_rd_data_port1), + .ocm_rd_bytes_port1(ocm_rd_bytes_port1), + .ocm_wr_qos_port1(ocm_wr_qos_port1), + .ocm_rd_qos_port1(ocm_rd_qos_port1) + + ); + + processing_system7_vip_v1_0_16_regc regc ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + /* Goes to port 0 of REG */ + .reg_rd_req_port0 (reg_rd_req_port0), + .reg_rd_dv_port0 (reg_rd_dv_port0), + .reg_rd_addr_port0(net_rd_addr_acp), + .reg_rd_bytes_port0(net_rd_bytes_acp), + .reg_rd_data_port0(reg_rd_data_port0), + .reg_rd_qos_port0 (net_rd_qos_acp), + + /* Goes to port 1 of REG */ + .reg_rd_req_port1 (reg_rd_req_port1), + .reg_rd_dv_port1 (reg_rd_dv_port1), + .reg_rd_addr_port1(reg_rd_addr_port1), + .reg_rd_data_port1(reg_rd_data_port1), + .reg_rd_bytes_port1(reg_rd_bytes_port1), + .reg_rd_qos_port1(reg_rd_qos_port1) + + ); + + /* include axi_gp port instantiations */ + `include "processing_system7_vip_v1_0_16_axi_gp.v" + + /* include axi_hp port instantiations */ + `include "processing_system7_vip_v1_0_16_axi_hp.v" + + /* include axi_acp port instantiations */ + `include "processing_system7_vip_v1_0_16_axi_acp.v" + +endmodule + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v new file mode 100644 index 0000000..d6ec7f8 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v @@ -0,0 +1,670 @@ +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// axis to vector +// A generic module to merge all axi signals into one signal called payload. +// This is strictly wires, so no clk, reset, aclken, valid/ready are required. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_axi2vector # +( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter integer C_AXI_PROTOCOL = 0, + parameter integer C_AXI_ID_WIDTH = 4, + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_DATA_WIDTH = 32, + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, + parameter integer C_AXI_AWUSER_WIDTH = 1, + parameter integer C_AXI_WUSER_WIDTH = 1, + parameter integer C_AXI_BUSER_WIDTH = 1, + parameter integer C_AXI_ARUSER_WIDTH = 1, + parameter integer C_AXI_RUSER_WIDTH = 1, + parameter integer C_AWPAYLOAD_WIDTH = 61, + parameter integer C_WPAYLOAD_WIDTH = 73, + parameter integer C_BPAYLOAD_WIDTH = 6, + parameter integer C_ARPAYLOAD_WIDTH = 61, + parameter integer C_RPAYLOAD_WIDTH = 69 +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + // Slave Interface Write Address Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [3-1:0] s_axi_awsize, + input wire [2-1:0] s_axi_awburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [4-1:0] s_axi_awcache, + input wire [3-1:0] s_axi_awprot, + input wire [4-1:0] s_axi_awregion, + input wire [4-1:0] s_axi_awqos, + input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + + // Slave Interface Write Data Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid, + input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output wire [2-1:0] s_axi_bresp, + output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + + // Slave Interface Read Address Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [3-1:0] s_axi_arsize, + input wire [2-1:0] s_axi_arburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [4-1:0] s_axi_arcache, + input wire [3-1:0] s_axi_arprot, + input wire [4-1:0] s_axi_arregion, + input wire [4-1:0] s_axi_arqos, + input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + + // Slave Interface Read Data Ports + output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [2-1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + + // payloads + output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload, + output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload, + input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload, + output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload, + input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload +); + +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +`include "axi_infrastructure_v1_1_0.vh" + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +// AXI4, AXI4LITE, AXI3 packing +assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr; +assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot; + +assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata; +assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb; + +assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH]; + +assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr; +assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot; + +assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH]; +assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH]; + +generate + if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing + assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize; + assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst; + assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache; + assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen; + assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock; + assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid; + assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos; + + assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast; + if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing + assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid; + end + else begin : gen_no_axi3_wid_packing + end + + assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH]; + + assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize; + assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst; + assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache; + assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen; + assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock; + assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid; + assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos; + + assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH]; + assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH]; + + if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals + assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion; + assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion; + end + else begin : gen_no_region_signals + end + if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals + assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser; + assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser; + assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH]; + assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser; + assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH]; + end + else begin : gen_no_user_signals + assign s_axi_buser = 'b0; + assign s_axi_ruser = 'b0; + end + end + else begin : gen_axi4lite_packing + assign s_axi_bid = 'b0; + assign s_axi_buser = 'b0; + + assign s_axi_rlast = 1'b1; + assign s_axi_rid = 'b0; + assign s_axi_ruser = 'b0; + end +endgenerate +endmodule + +`default_nettype wire + + +// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// Description: SRL based FIFO for AXIS/AXI Channels. +//-------------------------------------------------------------------------- + + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_axic_srl_fifo #( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter C_FAMILY = "virtex7", + parameter integer C_PAYLOAD_WIDTH = 1, + parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + input wire aclk, // Clock + input wire aresetn, // Reset + input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data + input wire s_valid, // Input data valid + output reg s_ready, // Input data ready + output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data + output reg m_valid, // Output data valid + input wire m_ready // Output data ready +); +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +// ceiling logb2 +function integer f_clogb2 (input integer size); + integer s; + begin + s = size; + s = s - 1; + for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) + s = s >> 1; + end +endfunction // clogb2 + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// +localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// +reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; +wire [4-1:0] fifo_addr; +wire push; +wire pop ; +reg areset_r1; + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +always @(posedge aclk) begin + areset_r1 <= ~aresetn; +end + +always @(posedge aclk) begin + if (~aresetn) begin + fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}}; + end + else begin + fifo_index <= push & ~pop ? fifo_index + 1'b1 : + ~push & pop ? fifo_index - 1'b1 : + fifo_index; + end +end + +assign push = s_valid & s_ready; + +always @(posedge aclk) begin + if (~aresetn) begin + s_ready <= 1'b0; + end + else begin + s_ready <= areset_r1 ? 1'b1 : + push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 : + ~push & pop ? 1'b1 : + s_ready; + end +end + +assign pop = m_valid & m_ready; + +always @(posedge aclk) begin + if (~aresetn) begin + m_valid <= 1'b0; + end + else begin + m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 : + push & ~pop ? 1'b1 : + m_valid; + end +end + +generate + if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr + assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; + assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}}; + end + else begin : gen_fifo_addr + assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; + end +endgenerate + + +generate + genvar i; + for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit + SRL16E + u_srl_fifo( + .Q ( m_payload[i] ) , + .A0 ( fifo_addr[0] ) , + .A1 ( fifo_addr[1] ) , + .A2 ( fifo_addr[2] ) , + .A3 ( fifo_addr[3] ) , + .CE ( push ) , + .CLK ( aclk ) , + .D ( s_payload[i] ) + ); + end +endgenerate + +endmodule + +`default_nettype wire + + +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// axi to vector +// A generic module to merge all axi signals into one signal called payload. +// This is strictly wires, so no clk, reset, aclken, valid/ready are required. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_vector2axi # +( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter integer C_AXI_PROTOCOL = 0, + parameter integer C_AXI_ID_WIDTH = 4, + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_DATA_WIDTH = 32, + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, + parameter integer C_AXI_AWUSER_WIDTH = 1, + parameter integer C_AXI_WUSER_WIDTH = 1, + parameter integer C_AXI_BUSER_WIDTH = 1, + parameter integer C_AXI_ARUSER_WIDTH = 1, + parameter integer C_AXI_RUSER_WIDTH = 1, + parameter integer C_AWPAYLOAD_WIDTH = 61, + parameter integer C_WPAYLOAD_WIDTH = 73, + parameter integer C_BPAYLOAD_WIDTH = 6, + parameter integer C_ARPAYLOAD_WIDTH = 61, + parameter integer C_RPAYLOAD_WIDTH = 69 +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + // Slave Interface Write Address Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [3-1:0] m_axi_awsize, + output wire [2-1:0] m_axi_awburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [4-1:0] m_axi_awcache, + output wire [3-1:0] m_axi_awprot, + output wire [4-1:0] m_axi_awregion, + output wire [4-1:0] m_axi_awqos, + output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + + // Slave Interface Write Data Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, + output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + + // Slave Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [2-1:0] m_axi_bresp, + input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + + // Slave Interface Read Address Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [3-1:0] m_axi_arsize, + output wire [2-1:0] m_axi_arburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [4-1:0] m_axi_arcache, + output wire [3-1:0] m_axi_arprot, + output wire [4-1:0] m_axi_arregion, + output wire [4-1:0] m_axi_arqos, + output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + + // Slave Interface Read Data Ports + input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [2-1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + + // payloads + input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, + input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, + output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, + input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, + output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload +); + +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +`include "axi_infrastructure_v1_1_0.vh" + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +// AXI4, AXI4LITE, AXI3 packing +assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; +assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; + +assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; +assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; + +assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; + +assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; +assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; + +assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; +assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; + +generate + if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing + assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; + assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; + assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; + assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; + assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; + assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; + assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; + + assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; + if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing + assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; + end + else begin : gen_no_axi3_wid_packing + assign m_axi_wid = 1'b0; + end + + assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; + + assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; + assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; + assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; + assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; + assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; + assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; + assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; + + assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; + assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; + + if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals + assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; + assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; + end + else begin : gen_no_region_signals + assign m_axi_awregion = 'b0; + assign m_axi_arregion = 'b0; + end + if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals + assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; + assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; + assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; + assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; + assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; + end + else begin : gen_no_user_signals + assign m_axi_awuser = 'b0; + assign m_axi_wuser = 'b0; + assign m_axi_aruser = 'b0; + end + end + else begin : gen_axi4lite_packing + assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; + assign m_axi_awburst = 'b0; + assign m_axi_awcache = 'b0; + assign m_axi_awlen = 'b0; + assign m_axi_awlock = 'b0; + assign m_axi_awid = 'b0; + assign m_axi_awqos = 'b0; + + assign m_axi_wlast = 1'b1; + assign m_axi_wid = 'b0; + + + assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; + assign m_axi_arburst = 'b0; + assign m_axi_arcache = 'b0; + assign m_axi_arlen = 'b0; + assign m_axi_arlock = 'b0; + assign m_axi_arid = 'b0; + assign m_axi_arqos = 'b0; + + assign m_axi_awregion = 'b0; + assign m_axi_arregion = 'b0; + + assign m_axi_awuser = 'b0; + assign m_axi_wuser = 'b0; + assign m_axi_aruser = 'b0; + end +endgenerate +endmodule + +`default_nettype wire + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/ed63/hdl/axi_vip_v1_1_vl_rfs.sv b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/ed63/hdl/axi_vip_v1_1_vl_rfs.sv new file mode 100644 index 0000000..589cf87 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/ipshared/ed63/hdl/axi_vip_v1_1_vl_rfs.sv @@ -0,0 +1,633 @@ +// (c) Copyright 2016 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// AXI VIP wrapper +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// axi_vip +// +//-------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_vip_v1_1_14_top # + ( + parameter C_AXI_PROTOCOL = 0, + parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_WDATA_WIDTH = 32, + parameter integer C_AXI_RDATA_WIDTH = 32, + parameter integer C_AXI_WID_WIDTH = 0, + parameter integer C_AXI_RID_WIDTH = 0, + parameter integer C_AXI_AWUSER_WIDTH = 0, + parameter integer C_AXI_ARUSER_WIDTH = 0, + parameter integer C_AXI_WUSER_WIDTH = 0, + parameter integer C_AXI_RUSER_WIDTH = 0, + parameter integer C_AXI_BUSER_WIDTH = 0, + parameter integer C_AXI_SUPPORTS_NARROW = 1, + parameter integer C_AXI_HAS_BURST = 1, + parameter integer C_AXI_HAS_LOCK = 1, + parameter integer C_AXI_HAS_CACHE = 1, + parameter integer C_AXI_HAS_REGION = 1, + parameter integer C_AXI_HAS_PROT = 1, + parameter integer C_AXI_HAS_QOS = 1, + parameter integer C_AXI_HAS_WSTRB = 1, + parameter integer C_AXI_HAS_BRESP = 1, + parameter integer C_AXI_HAS_RRESP = 1, + parameter integer C_AXI_HAS_ARESETN = 1 + ) + ( + //NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE + //Please refer xgui tcl and coreinfo.yml + + // System Signals + input wire aclk, + input wire aclken, + input wire aresetn, + + // Slave Interface Write Address Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [3-1:0] s_axi_awsize, + input wire [2-1:0] s_axi_awburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [4-1:0] s_axi_awcache, + input wire [3-1:0] s_axi_awprot, + input wire [4-1:0] s_axi_awregion, + input wire [4-1:0] s_axi_awqos, + input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input wire s_axi_awvalid, + output wire s_axi_awready, + + // Slave Interface Write Data Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid, + input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata, + input wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input wire s_axi_wvalid, + output wire s_axi_wready, + + // Slave Interface Write Response Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid, + output wire [2-1:0] s_axi_bresp, + output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + output wire s_axi_bvalid, + input wire s_axi_bready, + + // Slave Interface Read Address Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [3-1:0] s_axi_arsize, + input wire [2-1:0] s_axi_arburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [4-1:0] s_axi_arcache, + input wire [3-1:0] s_axi_arprot, + input wire [4-1:0] s_axi_arregion, + input wire [4-1:0] s_axi_arqos, + input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input wire s_axi_arvalid, + output wire s_axi_arready, + + // Slave Interface Read Data Ports + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid, + output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata, + output wire [2-1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output wire s_axi_rvalid, + input wire s_axi_rready, + + // Master Interface Write Address Port + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [3-1:0] m_axi_awsize, + output wire [2-1:0] m_axi_awburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [4-1:0] m_axi_awcache, + output wire [3-1:0] m_axi_awprot, + output wire [4-1:0] m_axi_awregion, + output wire [4-1:0] m_axi_awqos, + output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output wire m_axi_awvalid, + input wire m_axi_awready, + + // Master Interface Write Data Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid, + output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata, + output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output wire m_axi_wvalid, + input wire m_axi_wready, + + // Master Interface Write Response Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid, + input wire [2-1:0] m_axi_bresp, + input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + input wire m_axi_bvalid, + output wire m_axi_bready, + + // Master Interface Read Address Port + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid, + output wire [ C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [3-1:0] m_axi_arsize, + output wire [2-1:0] m_axi_arburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [4-1:0] m_axi_arcache, + output wire [3-1:0] m_axi_arprot, + output wire [4-1:0] m_axi_arregion, + output wire [4-1:0] m_axi_arqos, + output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output wire m_axi_arvalid, + input wire m_axi_arready, + + // Master Interface Read Data Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid, + input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata, + input wire [2-1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input wire m_axi_rvalid, + output wire m_axi_rready + ); + + /********************************************************************************************** + * NOTE: + * C_AXI_INTERFACE_MODE =0 -- MASTER MODE, + * C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE + * C_AXI_INTERFACE_MODE =2 -- SLAVE MODE + * Please refer xgui tcl and coreinfo.yml + * User can change PASS_THROUGH VIP to run time master mode or run time slave mode during + * the simulation + *********************************************************************************************/ + + /********************************************************************************************** + * Master_mode means that either the dut is statically being configured to be in master mode + * or it statically being configured to be pass-through mode and switched to be in master mode + * in run time. + + * Slave mode means that either the dut is statically being configured to be in slave mode + * or it statically being configured to be pass-through mode and switched to be in slave mode + * in run time. + + * Pass-through mode means that either the dut is statically being configured to be in + * pass-through mode or it statically being configured to be pass-through mode and switched + * to be in master/slave mode and then switch back to be in pass-through mode in run time + *********************************************************************************************/ + + logic runtime_master =0; + logic runtime_slave =0; + + wire run_slave_mode; + wire run_master_mode; + wire run_passth_mode; + wire compile_master_mode; + wire compile_slave_mode; + wire master_mode; + wire slave_mode; + + assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0); + assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0; + assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0); + + assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ; + assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ; + + assign master_mode = compile_master_mode || run_master_mode; + assign slave_mode = compile_slave_mode || run_slave_mode; + + // Slave Interface Write Address Ports Internal + assign IF.AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}}; + assign IF.AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}}; + assign IF.AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}}; + assign IF.AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}}; + assign IF.AWBURST = slave_mode? s_axi_awburst : {2{1'bz}}; + assign IF.AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}}; + assign IF.AWCACHE = slave_mode? s_axi_awcache : {4{1'bz}}; + assign IF.AWPROT = slave_mode? s_axi_awprot : {3{1'bz}}; + assign IF.AWREGION = slave_mode? s_axi_awregion : {4{1'bz}}; + assign IF.AWQOS = slave_mode? s_axi_awqos : {4{1'bz}}; + assign IF.AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}}; + assign IF.AWVALID = slave_mode? s_axi_awvalid : {1'bz}; + assign s_axi_awready = slave_mode? IF.AWREADY : {1'b0}; + + // Slave Interface Write Data Ports + assign IF.WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}}; + assign IF.WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}}; + assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}}; + assign IF.WLAST = slave_mode? s_axi_wlast: {1'bz}; + assign IF.WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}}; + assign IF.WVALID = slave_mode? s_axi_wvalid : {1'bz}; + assign s_axi_wready = slave_mode? IF.WREADY : {1'b0}; + + // Slave Interface Write Response Ports + assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}}; + assign s_axi_bresp = slave_mode? IF.BRESP : {2{1'b0}}; + assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}}; + assign s_axi_bvalid = slave_mode? IF.BVALID : {1{1'b0}}; + assign IF.BREADY = slave_mode? s_axi_bready :{1{1'bz}}; + + // Slave Interface Read Address Ports + assign IF.ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}}; + assign IF.ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ; + assign IF.ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}}; + assign IF.ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}}; + assign IF.ARBURST = slave_mode? s_axi_arburst : {2{1'bz}}; + assign IF.ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}}; + assign IF.ARCACHE = slave_mode? s_axi_arcache : {4{1'bz}}; + assign IF.ARPROT = slave_mode? s_axi_arprot : {3{1'bz}}; + assign IF.ARREGION = slave_mode? s_axi_arregion :{4{1'bz}} ; + assign IF.ARQOS = slave_mode? s_axi_arqos : {4{1'bz}}; + assign IF.ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}}; + assign IF.ARVALID = slave_mode? s_axi_arvalid : {1'bz}; + assign s_axi_arready = slave_mode? IF.ARREADY : {1'b0}; + + //Slave Interface Read Data Ports + assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}}; + assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}}; + assign s_axi_rresp = slave_mode? IF.RRESP : {2{1'b0}}; + assign s_axi_rlast = slave_mode? IF.RLAST : {{1'b0}}; + assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}}; + assign s_axi_rvalid = slave_mode? IF.RVALID : {{1'b0}}; + assign IF.RREADY = slave_mode? s_axi_rready:{{1'bz}}; + + // Master Interface Write Address Port + assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}}; + assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}}; + assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}}; + assign m_axi_awsize = master_mode? IF.AWSIZE : {3{1'b0}}; + assign m_axi_awburst = master_mode? IF.AWBURST : {2{1'b0}}; + assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}}; + assign m_axi_awcache = master_mode? IF.AWCACHE : {4{1'b0}}; + assign m_axi_awprot = master_mode? IF.AWPROT : {3{1'b0}}; + assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}}; + assign m_axi_awqos = master_mode? IF.AWQOS : {4{1'b0}}; + assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}}; + assign m_axi_awvalid = master_mode? IF.AWVALID :{1'b0}; + assign IF.AWREADY = master_mode? m_axi_awready :{1'bz}; + + // Master Interface Write Data Ports Internal + assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}}; + assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}}; + assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}}; + assign m_axi_wlast = master_mode? IF.WLAST : {1'b0}; + assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}}; + assign m_axi_wvalid = master_mode? IF.WVALID : {1'b0}; + assign IF.WREADY = master_mode? m_axi_wready : {1'bz}; + + // Master Interface Write Response Ports Internal + assign IF.BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}}; + assign IF.BRESP = master_mode? m_axi_bresp : {2{1'bz}}; + assign IF.BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}}; + assign IF.BVALID = master_mode? m_axi_bvalid : 1'bz; + assign m_axi_bready = master_mode? IF.BREADY : 1'b0; + + // Master Interface Read Address Port Internal + assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}}; + assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}}; + assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}}; + assign m_axi_arsize = master_mode? IF.ARSIZE : {3{1'b0}}; + assign m_axi_arburst = master_mode? IF.ARBURST : {2{1'b0}}; + assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}}; + assign m_axi_arcache = master_mode?IF.ARCACHE : {4{1'b0}}; + assign m_axi_arprot = master_mode? IF.ARPROT : {3{1'b0}}; + assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}}; + assign m_axi_arqos = master_mode? IF.ARQOS : {4{1'b0}}; + assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}}; + assign m_axi_arvalid = master_mode? IF.ARVALID :{1'b0}; + assign IF.ARREADY = master_mode? m_axi_arready : {1{1'bz}}; + + // Master Interface Read Data Ports Internal + assign IF.RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}}; + assign IF.RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}}; + assign IF.RRESP = master_mode? m_axi_rresp : {2{1'bz}}; + assign IF.RLAST = master_mode? m_axi_rlast : {1{1'bz}}; + assign IF.RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}}; + assign IF.RVALID = master_mode? m_axi_rvalid : {1{1'bz}}; + assign m_axi_rready = master_mode? IF.RREADY : {1{1'b0}}; + + axi_vip_if #( + .C_AXI_PROTOCOL(C_AXI_PROTOCOL), + .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ), + .C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ), + .C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ), + .C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ), + .C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ), + .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ), + .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ), + .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ), + .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ), + .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ), + .C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW), + .C_AXI_HAS_BURST(C_AXI_HAS_BURST), + .C_AXI_HAS_LOCK(C_AXI_HAS_LOCK), + .C_AXI_HAS_CACHE(C_AXI_HAS_CACHE), + .C_AXI_HAS_REGION(C_AXI_HAS_REGION), + .C_AXI_HAS_PROT(C_AXI_HAS_PROT), + .C_AXI_HAS_QOS(C_AXI_HAS_QOS), + .C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB), + .C_AXI_HAS_BRESP(C_AXI_HAS_BRESP), + .C_AXI_HAS_RRESP(C_AXI_HAS_RRESP), + .C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN) + ) IF ( + .ACLK(aclk), + .ARESET_N(aresetn), + .ACLKEN(aclken) + ); + + + //synthesis translate_off + initial begin + $display("XilinxAXIVIP: Found at Path: %m"); + end + + //set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode + generate + initial begin + if(C_AXI_INTERFACE_MODE ==0) begin + IF.set_intf_master; + end else if(C_AXI_INTERFACE_MODE ==2) begin + IF.set_intf_slave; + end else if(C_AXI_INTERFACE_MODE ==1) begin + $display("This AXI VIP is in passthrough mode"); + end else begin + $fatal(0,"This AXI VIP's mode is out of range"); + end + end + endgenerate + + /* + Function: set_passthrough_mode + Sets AXI VIP passthrough into run time passthrough mode + */ + function void set_passthrough_mode(); + if (C_AXI_INTERFACE_MODE == 1) begin + runtime_master = 0; + runtime_slave = 0; + IF.set_intf_monitor(); + end else begin + $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP"); + end + endfunction: set_passthrough_mode + + /* + Function: set_master_mode + Sets AXI VIP passthrough into run time master mode + */ + function void set_master_mode(); + if (C_AXI_INTERFACE_MODE == 1) begin + runtime_master = 1; + runtime_slave = 0; + IF.set_intf_master(); + end else begin + $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP "); + end + endfunction : set_master_mode + + /* + Function: set_slave_mode + Sets AXI VIP passthrough into run time slave mode + */ + function void set_slave_mode(); + if (C_AXI_INTERFACE_MODE == 1) begin + runtime_master = 0; + runtime_slave = 1; + IF.set_intf_slave(); + end else begin + $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP"); + end + endfunction : set_slave_mode + + /* + Function: set_xilinx_slave_ready_check + Sets xilinx_slave_ready_check_enable of IF to be 1 + */ + function void set_xilinx_slave_ready_check(); + IF.xilinx_slave_ready_check_enable = 1; + endfunction + + /* + Function: clr_xilinx_slave_ready_check + Sets xilinx_slave_ready_check_enable of IF to be 0 + */ + function void clr_xilinx_slave_ready_check(); + IF.xilinx_slave_ready_check_enable = 0; + endfunction + + /* + Function: set_max_aw_wait_cycles (not available in VIVADO Simulator) + Sets max_aw_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_aw_wait_cycles(input integer unsigned new_num); + IF.PC.max_aw_wait_cycles = new_num; + endfunction : set_max_aw_wait_cycles + + /* + Function: set_max_ar_wait_cycles (not available in VIVADO Simulator) + Sets max_ar_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_ar_wait_cycles(input integer unsigned new_num); + IF.PC.max_ar_wait_cycles = new_num; + endfunction : set_max_ar_wait_cycles + + /* + Function: set_max_r_wait_cycles (not available in VIVADO Simulator) + Sets max_r_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_r_wait_cycles(input integer unsigned new_num); + IF.PC.max_r_wait_cycles = new_num; + endfunction : set_max_r_wait_cycles + + /* + Function: set_max_b_wait_cycles (not available in VIVADO Simulator) + Sets max_b_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_b_wait_cycles(input integer unsigned new_num); + IF.PC.max_b_wait_cycles = new_num; + endfunction : set_max_b_wait_cycles + + /* + Function: set_max_w_wait_cycles (not available in VIVADO Simulator) + Sets max_w_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_w_wait_cycles(input integer unsigned new_num); + IF.PC.max_w_wait_cycles = new_num; + endfunction : set_max_w_wait_cycles + + /* + Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator) + Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_wlast_wait_cycles(input integer unsigned new_num); + IF.PC.max_wlast_to_awvalid_wait_cycles = new_num; + endfunction : set_max_wlast_wait_cycles + + /* + Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator) + Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_rtransfers_wait_cycles(input integer unsigned new_num); + IF.PC.max_rtransfers_wait_cycles = new_num; + endfunction : set_max_rtransfers_wait_cycles + + /* + Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator) + Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_wtransfers_wait_cycles(input integer unsigned new_num); + IF.PC.max_wtransfers_wait_cycles = new_num; + endfunction : set_max_wtransfers_wait_cycles + + /* + Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator) + Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_wlcmd_wait_cycles(input integer unsigned new_num); + IF.PC.max_wlcmd_wait_cycles = new_num; + endfunction : set_max_wlcmd_wait_cycles + + /* + Function: get_max_aw_wait_cycles (not available in VIVADO Simulator) + Returns max_aw_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_aw_wait_cycles(); + return(IF.PC.max_aw_wait_cycles); + endfunction : get_max_aw_wait_cycles + + /* + Function: get_max_ar_wait_cycles (not available in VIVADO Simulator) + Returns max_ar_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_ar_wait_cycles(); + return(IF.PC.max_ar_wait_cycles); + endfunction : get_max_ar_wait_cycles + + /* + Function: get_max_r_wait_cycles (not available in VIVADO Simulator) + Returns max_r_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_r_wait_cycles(); + return(IF.PC.max_r_wait_cycles); + endfunction : get_max_r_wait_cycles + + /* + Function: get_max_b_wait_cycles (not available in VIVADO Simulator) + Returns max_b_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_b_wait_cycles(); + return(IF.PC.max_b_wait_cycles); + endfunction : get_max_b_wait_cycles + + /* + Function: get_max_w_wait_cycles (not available in VIVADO Simulator) + Returns max_w_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_w_wait_cycles(); + return(IF.PC.max_w_wait_cycles); + endfunction :get_max_w_wait_cycles + + /* + Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator) + Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_wlast_wait_cycles(); + return(IF.PC.max_wlast_to_awvalid_wait_cycles); + endfunction :get_max_wlast_wait_cycles + + /* + Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator) + Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_rtransfers_wait_cycles(); + return(IF.PC.max_rtransfers_wait_cycles); + endfunction :get_max_rtransfers_wait_cycles + + /* + Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator) + Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_wtransfers_wait_cycles(); + return(IF.PC.max_wtransfers_wait_cycles); + endfunction :get_max_wtransfers_wait_cycles + + /* + Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator) + Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_wlcmd_wait_cycles(); + return(IF.PC.max_wlcmd_wait_cycles); + endfunction :get_max_wlcmd_wait_cycles + + /* + Function: set_fatal_to_warnings (not available in VIVADO Simulator) + Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1 + */ + function void set_fatal_to_warnings(); + IF.PC.fatal_to_warnings = 1; + endfunction : set_fatal_to_warnings + + /* + Function: clr_fatal_to_warnings (not available in VIVADO Simulator) + Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0 + */ + function void clr_fatal_to_warnings(); + IF.PC.fatal_to_warnings = 0; + endfunction : clr_fatal_to_warnings + //synthesis translate_on + +endmodule // axi_vip_v1_1_14_top + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/sim/design_3.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/sim/design_3.vhd new file mode 100644 index 0000000..5f98066 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/sim/design_3.vhd @@ -0,0 +1,6016 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Tue Dec 10 18:59:40 2024 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target design_3.bd +--Design : design_3 +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity PS_imp_Z714CR is + port ( + DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_cas_n : inout STD_LOGIC; + DDR_ck_n : inout STD_LOGIC; + DDR_ck_p : inout STD_LOGIC; + DDR_cke : inout STD_LOGIC; + DDR_cs_n : inout STD_LOGIC; + DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_odt : inout STD_LOGIC; + DDR_ras_n : inout STD_LOGIC; + DDR_reset_n : inout STD_LOGIC; + DDR_we_n : inout STD_LOGIC; + FCLK_CLK0 : out STD_LOGIC; + FCLK_CLK3 : out STD_LOGIC; + FIXED_IO_ddr_vrn : inout STD_LOGIC; + FIXED_IO_ddr_vrp : inout STD_LOGIC; + FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + FIXED_IO_ps_clk : inout STD_LOGIC; + FIXED_IO_ps_porb : inout STD_LOGIC; + FIXED_IO_ps_srstb : inout STD_LOGIC; + In0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + In1 : in STD_LOGIC; + M_AXI_GP0_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_arready : in STD_LOGIC; + M_AXI_GP0_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_arvalid : out STD_LOGIC; + M_AXI_GP0_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_awready : in STD_LOGIC; + M_AXI_GP0_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_awvalid : out STD_LOGIC; + M_AXI_GP0_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_bready : out STD_LOGIC; + M_AXI_GP0_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_bvalid : in STD_LOGIC; + M_AXI_GP0_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_rlast : in STD_LOGIC; + M_AXI_GP0_rready : out STD_LOGIC; + M_AXI_GP0_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_rvalid : in STD_LOGIC; + M_AXI_GP0_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_wlast : out STD_LOGIC; + M_AXI_GP0_wready : in STD_LOGIC; + M_AXI_GP0_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_wvalid : out STD_LOGIC; + S_AXI_ACP_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_arready : out STD_LOGIC; + S_AXI_ACP_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_arvalid : in STD_LOGIC; + S_AXI_ACP_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_awready : out STD_LOGIC; + S_AXI_ACP_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_awvalid : in STD_LOGIC; + S_AXI_ACP_bready : in STD_LOGIC; + S_AXI_ACP_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_bvalid : out STD_LOGIC; + S_AXI_ACP_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_rlast : out STD_LOGIC; + S_AXI_ACP_rready : in STD_LOGIC; + S_AXI_ACP_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_rvalid : out STD_LOGIC; + S_AXI_ACP_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_wlast : in STD_LOGIC; + S_AXI_ACP_wready : out STD_LOGIC; + S_AXI_ACP_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_ACP_wvalid : in STD_LOGIC; + S_AXI_HP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_arready : out STD_LOGIC; + S_AXI_HP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_arvalid : in STD_LOGIC; + S_AXI_HP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_awready : out STD_LOGIC; + S_AXI_HP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_awvalid : in STD_LOGIC; + S_AXI_HP0_bready : in STD_LOGIC; + S_AXI_HP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_bvalid : out STD_LOGIC; + S_AXI_HP0_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_rlast : out STD_LOGIC; + S_AXI_HP0_rready : in STD_LOGIC; + S_AXI_HP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_rvalid : out STD_LOGIC; + S_AXI_HP0_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_wlast : in STD_LOGIC; + S_AXI_HP0_wready : out STD_LOGIC; + S_AXI_HP0_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_wvalid : in STD_LOGIC; + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end PS_imp_Z714CR; + +architecture STRUCTURE of PS_imp_Z714CR is + component design_3_processing_system7_0_0 is + port ( + SDIO0_WP : in STD_LOGIC; + TTC0_WAVE0_OUT : out STD_LOGIC; + TTC0_WAVE1_OUT : out STD_LOGIC; + TTC0_WAVE2_OUT : out STD_LOGIC; + USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); + USB0_VBUS_PWRSELECT : out STD_LOGIC; + USB0_VBUS_PWRFAULT : in STD_LOGIC; + M_AXI_GP0_ARVALID : out STD_LOGIC; + M_AXI_GP0_AWVALID : out STD_LOGIC; + M_AXI_GP0_BREADY : out STD_LOGIC; + M_AXI_GP0_RREADY : out STD_LOGIC; + M_AXI_GP0_WLAST : out STD_LOGIC; + M_AXI_GP0_WVALID : out STD_LOGIC; + M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ACLK : in STD_LOGIC; + M_AXI_GP0_ARREADY : in STD_LOGIC; + M_AXI_GP0_AWREADY : in STD_LOGIC; + M_AXI_GP0_BVALID : in STD_LOGIC; + M_AXI_GP0_RLAST : in STD_LOGIC; + M_AXI_GP0_RVALID : in STD_LOGIC; + M_AXI_GP0_WREADY : in STD_LOGIC; + M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_ARREADY : out STD_LOGIC; + S_AXI_ACP_AWREADY : out STD_LOGIC; + S_AXI_ACP_BVALID : out STD_LOGIC; + S_AXI_ACP_RLAST : out STD_LOGIC; + S_AXI_ACP_RVALID : out STD_LOGIC; + S_AXI_ACP_WREADY : out STD_LOGIC; + S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_ACLK : in STD_LOGIC; + S_AXI_ACP_ARVALID : in STD_LOGIC; + S_AXI_ACP_AWVALID : in STD_LOGIC; + S_AXI_ACP_BREADY : in STD_LOGIC; + S_AXI_ACP_RREADY : in STD_LOGIC; + S_AXI_ACP_WLAST : in STD_LOGIC; + S_AXI_ACP_WVALID : in STD_LOGIC; + S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); + S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); + S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_ARREADY : out STD_LOGIC; + S_AXI_HP0_AWREADY : out STD_LOGIC; + S_AXI_HP0_BVALID : out STD_LOGIC; + S_AXI_HP0_RLAST : out STD_LOGIC; + S_AXI_HP0_RVALID : out STD_LOGIC; + S_AXI_HP0_WREADY : out STD_LOGIC; + S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_ACLK : in STD_LOGIC; + S_AXI_HP0_ARVALID : in STD_LOGIC; + S_AXI_HP0_AWVALID : in STD_LOGIC; + S_AXI_HP0_BREADY : in STD_LOGIC; + S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_RREADY : in STD_LOGIC; + S_AXI_HP0_WLAST : in STD_LOGIC; + S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_WVALID : in STD_LOGIC; + S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 ); + FCLK_CLK0 : out STD_LOGIC; + FCLK_CLK1 : out STD_LOGIC; + FCLK_CLK2 : out STD_LOGIC; + FCLK_CLK3 : out STD_LOGIC; + FCLK_RESET0_N : out STD_LOGIC; + MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + DDR_CAS_n : inout STD_LOGIC; + DDR_CKE : inout STD_LOGIC; + DDR_Clk_n : inout STD_LOGIC; + DDR_Clk : inout STD_LOGIC; + DDR_CS_n : inout STD_LOGIC; + DDR_DRSTB : inout STD_LOGIC; + DDR_ODT : inout STD_LOGIC; + DDR_RAS_n : inout STD_LOGIC; + DDR_WEB : inout STD_LOGIC; + DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_VRN : inout STD_LOGIC; + DDR_VRP : inout STD_LOGIC; + DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + PS_SRSTB : inout STD_LOGIC; + PS_CLK : inout STD_LOGIC; + PS_PORB : inout STD_LOGIC + ); + end component design_3_processing_system7_0_0; + component design_3_rst_ps7_0_100M_0 is + port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component design_3_rst_ps7_0_100M_0; + component design_3_xlconcat_0_0 is + port ( + In0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + In1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + dout : out STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component design_3_xlconcat_0_0; + component design_3_xlconstant_0_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component design_3_xlconstant_0_0; + signal In0_1 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal In1_1 : STD_LOGIC; + signal S_AXI_ACP_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXI_ACP_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_ARREADY : STD_LOGIC; + signal S_AXI_ACP_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_1_ARVALID : STD_LOGIC; + signal S_AXI_ACP_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXI_ACP_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_AWREADY : STD_LOGIC; + signal S_AXI_ACP_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_1_AWVALID : STD_LOGIC; + signal S_AXI_ACP_1_BREADY : STD_LOGIC; + signal S_AXI_ACP_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_BVALID : STD_LOGIC; + signal S_AXI_ACP_1_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal S_AXI_ACP_1_RLAST : STD_LOGIC; + signal S_AXI_ACP_1_RREADY : STD_LOGIC; + signal S_AXI_ACP_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_RVALID : STD_LOGIC; + signal S_AXI_ACP_1_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal S_AXI_ACP_1_WLAST : STD_LOGIC; + signal S_AXI_ACP_1_WREADY : STD_LOGIC; + signal S_AXI_ACP_1_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal S_AXI_ACP_1_WVALID : STD_LOGIC; + signal S_AXI_ACP_2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXI_ACP_2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_2_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_ARREADY : STD_LOGIC; + signal S_AXI_ACP_2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_2_ARVALID : STD_LOGIC; + signal S_AXI_ACP_2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXI_ACP_2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_2_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_AWREADY : STD_LOGIC; + signal S_AXI_ACP_2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_2_AWVALID : STD_LOGIC; + signal S_AXI_ACP_2_BREADY : STD_LOGIC; + signal S_AXI_ACP_2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_BVALID : STD_LOGIC; + signal S_AXI_ACP_2_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal S_AXI_ACP_2_RLAST : STD_LOGIC; + signal S_AXI_ACP_2_RREADY : STD_LOGIC; + signal S_AXI_ACP_2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_RVALID : STD_LOGIC; + signal S_AXI_ACP_2_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal S_AXI_ACP_2_WLAST : STD_LOGIC; + signal S_AXI_ACP_2_WREADY : STD_LOGIC; + signal S_AXI_ACP_2_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal S_AXI_ACP_2_WVALID : STD_LOGIC; + signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_DDR_CAS_N : STD_LOGIC; + signal processing_system7_0_DDR_CKE : STD_LOGIC; + signal processing_system7_0_DDR_CK_N : STD_LOGIC; + signal processing_system7_0_DDR_CK_P : STD_LOGIC; + signal processing_system7_0_DDR_CS_N : STD_LOGIC; + signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_ODT : STD_LOGIC; + signal processing_system7_0_DDR_RAS_N : STD_LOGIC; + signal processing_system7_0_DDR_RESET_N : STD_LOGIC; + signal processing_system7_0_DDR_WE_N : STD_LOGIC; + signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; + signal processing_system7_0_FCLK_CLK3 : STD_LOGIC; + signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC; + signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC; + signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC; + signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); + signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC; + signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC; + signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC; + signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_processing_system7_0_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC; + signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_rst_ps7_0_100M_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); +begin + FCLK_CLK0 <= processing_system7_0_FCLK_CLK0; + FCLK_CLK3 <= processing_system7_0_FCLK_CLK3; + In0_1(0) <= In0(0); + In1_1 <= In1; + M_AXI_GP0_araddr(31 downto 0) <= processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0); + M_AXI_GP0_arburst(1 downto 0) <= processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0); + M_AXI_GP0_arcache(3 downto 0) <= processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0); + M_AXI_GP0_arid(11 downto 0) <= processing_system7_0_M_AXI_GP0_ARID(11 downto 0); + M_AXI_GP0_arlen(3 downto 0) <= processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0); + M_AXI_GP0_arlock(1 downto 0) <= processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0); + M_AXI_GP0_arprot(2 downto 0) <= processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0); + M_AXI_GP0_arqos(3 downto 0) <= processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0); + M_AXI_GP0_arsize(2 downto 0) <= processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0); + M_AXI_GP0_arvalid <= processing_system7_0_M_AXI_GP0_ARVALID; + M_AXI_GP0_awaddr(31 downto 0) <= processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0); + M_AXI_GP0_awburst(1 downto 0) <= processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0); + M_AXI_GP0_awcache(3 downto 0) <= processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0); + M_AXI_GP0_awid(11 downto 0) <= processing_system7_0_M_AXI_GP0_AWID(11 downto 0); + M_AXI_GP0_awlen(3 downto 0) <= processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0); + M_AXI_GP0_awlock(1 downto 0) <= processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0); + M_AXI_GP0_awprot(2 downto 0) <= processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0); + M_AXI_GP0_awqos(3 downto 0) <= processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0); + M_AXI_GP0_awsize(2 downto 0) <= processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0); + M_AXI_GP0_awvalid <= processing_system7_0_M_AXI_GP0_AWVALID; + M_AXI_GP0_bready <= processing_system7_0_M_AXI_GP0_BREADY; + M_AXI_GP0_rready <= processing_system7_0_M_AXI_GP0_RREADY; + M_AXI_GP0_wdata(31 downto 0) <= processing_system7_0_M_AXI_GP0_WDATA(31 downto 0); + M_AXI_GP0_wid(11 downto 0) <= processing_system7_0_M_AXI_GP0_WID(11 downto 0); + M_AXI_GP0_wlast <= processing_system7_0_M_AXI_GP0_WLAST; + M_AXI_GP0_wstrb(3 downto 0) <= processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0); + M_AXI_GP0_wvalid <= processing_system7_0_M_AXI_GP0_WVALID; + S_AXI_ACP_1_ARADDR(31 downto 0) <= S_AXI_HP0_araddr(31 downto 0); + S_AXI_ACP_1_ARBURST(1 downto 0) <= S_AXI_HP0_arburst(1 downto 0); + S_AXI_ACP_1_ARCACHE(3 downto 0) <= S_AXI_HP0_arcache(3 downto 0); + S_AXI_ACP_1_ARLEN(3 downto 0) <= S_AXI_HP0_arlen(3 downto 0); + S_AXI_ACP_1_ARLOCK(1 downto 0) <= S_AXI_HP0_arlock(1 downto 0); + S_AXI_ACP_1_ARPROT(2 downto 0) <= S_AXI_HP0_arprot(2 downto 0); + S_AXI_ACP_1_ARQOS(3 downto 0) <= S_AXI_HP0_arqos(3 downto 0); + S_AXI_ACP_1_ARSIZE(2 downto 0) <= S_AXI_HP0_arsize(2 downto 0); + S_AXI_ACP_1_ARVALID <= S_AXI_HP0_arvalid; + S_AXI_ACP_1_AWADDR(31 downto 0) <= S_AXI_HP0_awaddr(31 downto 0); + S_AXI_ACP_1_AWBURST(1 downto 0) <= S_AXI_HP0_awburst(1 downto 0); + S_AXI_ACP_1_AWCACHE(3 downto 0) <= S_AXI_HP0_awcache(3 downto 0); + S_AXI_ACP_1_AWLEN(3 downto 0) <= S_AXI_HP0_awlen(3 downto 0); + S_AXI_ACP_1_AWLOCK(1 downto 0) <= S_AXI_HP0_awlock(1 downto 0); + S_AXI_ACP_1_AWPROT(2 downto 0) <= S_AXI_HP0_awprot(2 downto 0); + S_AXI_ACP_1_AWQOS(3 downto 0) <= S_AXI_HP0_awqos(3 downto 0); + S_AXI_ACP_1_AWSIZE(2 downto 0) <= S_AXI_HP0_awsize(2 downto 0); + S_AXI_ACP_1_AWVALID <= S_AXI_HP0_awvalid; + S_AXI_ACP_1_BREADY <= S_AXI_HP0_bready; + S_AXI_ACP_1_RREADY <= S_AXI_HP0_rready; + S_AXI_ACP_1_WDATA(63 downto 0) <= S_AXI_HP0_wdata(63 downto 0); + S_AXI_ACP_1_WLAST <= S_AXI_HP0_wlast; + S_AXI_ACP_1_WSTRB(7 downto 0) <= S_AXI_HP0_wstrb(7 downto 0); + S_AXI_ACP_1_WVALID <= S_AXI_HP0_wvalid; + S_AXI_ACP_2_ARADDR(31 downto 0) <= S_AXI_ACP_araddr(31 downto 0); + S_AXI_ACP_2_ARBURST(1 downto 0) <= S_AXI_ACP_arburst(1 downto 0); + S_AXI_ACP_2_ARCACHE(3 downto 0) <= S_AXI_ACP_arcache(3 downto 0); + S_AXI_ACP_2_ARLEN(3 downto 0) <= S_AXI_ACP_arlen(3 downto 0); + S_AXI_ACP_2_ARLOCK(1 downto 0) <= S_AXI_ACP_arlock(1 downto 0); + S_AXI_ACP_2_ARPROT(2 downto 0) <= S_AXI_ACP_arprot(2 downto 0); + S_AXI_ACP_2_ARQOS(3 downto 0) <= S_AXI_ACP_arqos(3 downto 0); + S_AXI_ACP_2_ARSIZE(2 downto 0) <= S_AXI_ACP_arsize(2 downto 0); + S_AXI_ACP_2_ARVALID <= S_AXI_ACP_arvalid; + S_AXI_ACP_2_AWADDR(31 downto 0) <= S_AXI_ACP_awaddr(31 downto 0); + S_AXI_ACP_2_AWBURST(1 downto 0) <= S_AXI_ACP_awburst(1 downto 0); + S_AXI_ACP_2_AWCACHE(3 downto 0) <= S_AXI_ACP_awcache(3 downto 0); + S_AXI_ACP_2_AWLEN(3 downto 0) <= S_AXI_ACP_awlen(3 downto 0); + S_AXI_ACP_2_AWLOCK(1 downto 0) <= S_AXI_ACP_awlock(1 downto 0); + S_AXI_ACP_2_AWPROT(2 downto 0) <= S_AXI_ACP_awprot(2 downto 0); + S_AXI_ACP_2_AWQOS(3 downto 0) <= S_AXI_ACP_awqos(3 downto 0); + S_AXI_ACP_2_AWSIZE(2 downto 0) <= S_AXI_ACP_awsize(2 downto 0); + S_AXI_ACP_2_AWVALID <= S_AXI_ACP_awvalid; + S_AXI_ACP_2_BREADY <= S_AXI_ACP_bready; + S_AXI_ACP_2_RREADY <= S_AXI_ACP_rready; + S_AXI_ACP_2_WDATA(63 downto 0) <= S_AXI_ACP_wdata(63 downto 0); + S_AXI_ACP_2_WLAST <= S_AXI_ACP_wlast; + S_AXI_ACP_2_WSTRB(7 downto 0) <= S_AXI_ACP_wstrb(7 downto 0); + S_AXI_ACP_2_WVALID <= S_AXI_ACP_wvalid; + S_AXI_ACP_arready <= S_AXI_ACP_2_ARREADY; + S_AXI_ACP_awready <= S_AXI_ACP_2_AWREADY; + S_AXI_ACP_bresp(1 downto 0) <= S_AXI_ACP_2_BRESP(1 downto 0); + S_AXI_ACP_bvalid <= S_AXI_ACP_2_BVALID; + S_AXI_ACP_rdata(63 downto 0) <= S_AXI_ACP_2_RDATA(63 downto 0); + S_AXI_ACP_rlast <= S_AXI_ACP_2_RLAST; + S_AXI_ACP_rresp(1 downto 0) <= S_AXI_ACP_2_RRESP(1 downto 0); + S_AXI_ACP_rvalid <= S_AXI_ACP_2_RVALID; + S_AXI_ACP_wready <= S_AXI_ACP_2_WREADY; + S_AXI_HP0_arready <= S_AXI_ACP_1_ARREADY; + S_AXI_HP0_awready <= S_AXI_ACP_1_AWREADY; + S_AXI_HP0_bresp(1 downto 0) <= S_AXI_ACP_1_BRESP(1 downto 0); + S_AXI_HP0_bvalid <= S_AXI_ACP_1_BVALID; + S_AXI_HP0_rdata(63 downto 0) <= S_AXI_ACP_1_RDATA(63 downto 0); + S_AXI_HP0_rlast <= S_AXI_ACP_1_RLAST; + S_AXI_HP0_rresp(1 downto 0) <= S_AXI_ACP_1_RRESP(1 downto 0); + S_AXI_HP0_rvalid <= S_AXI_ACP_1_RVALID; + S_AXI_HP0_wready <= S_AXI_ACP_1_WREADY; + peripheral_aresetn(0) <= rst_ps7_0_100M_peripheral_aresetn(0); + processing_system7_0_M_AXI_GP0_ARREADY <= M_AXI_GP0_arready; + processing_system7_0_M_AXI_GP0_AWREADY <= M_AXI_GP0_awready; + processing_system7_0_M_AXI_GP0_BID(11 downto 0) <= M_AXI_GP0_bid(11 downto 0); + processing_system7_0_M_AXI_GP0_BRESP(1 downto 0) <= M_AXI_GP0_bresp(1 downto 0); + processing_system7_0_M_AXI_GP0_BVALID <= M_AXI_GP0_bvalid; + processing_system7_0_M_AXI_GP0_RDATA(31 downto 0) <= M_AXI_GP0_rdata(31 downto 0); + processing_system7_0_M_AXI_GP0_RID(11 downto 0) <= M_AXI_GP0_rid(11 downto 0); + processing_system7_0_M_AXI_GP0_RLAST <= M_AXI_GP0_rlast; + processing_system7_0_M_AXI_GP0_RRESP(1 downto 0) <= M_AXI_GP0_rresp(1 downto 0); + processing_system7_0_M_AXI_GP0_RVALID <= M_AXI_GP0_rvalid; + processing_system7_0_M_AXI_GP0_WREADY <= M_AXI_GP0_wready; +processing_system7_0: component design_3_processing_system7_0_0 + port map ( + DDR_Addr(14 downto 0) => DDR_addr(14 downto 0), + DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0), + DDR_CAS_n => DDR_cas_n, + DDR_CKE => DDR_cke, + DDR_CS_n => DDR_cs_n, + DDR_Clk => DDR_ck_p, + DDR_Clk_n => DDR_ck_n, + DDR_DM(3 downto 0) => DDR_dm(3 downto 0), + DDR_DQ(31 downto 0) => DDR_dq(31 downto 0), + DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0), + DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0), + DDR_DRSTB => DDR_reset_n, + DDR_ODT => DDR_odt, + DDR_RAS_n => DDR_ras_n, + DDR_VRN => FIXED_IO_ddr_vrn, + DDR_VRP => FIXED_IO_ddr_vrp, + DDR_WEB => DDR_we_n, + FCLK_CLK0 => processing_system7_0_FCLK_CLK0, + FCLK_CLK1 => NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED, + FCLK_CLK2 => NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED, + FCLK_CLK3 => processing_system7_0_FCLK_CLK3, + FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N, + IRQ_F2P(1 downto 0) => xlconcat_0_dout(1 downto 0), + MIO(53 downto 0) => FIXED_IO_mio(53 downto 0), + M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0, + M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), + M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), + M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), + M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), + M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), + M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), + M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), + M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), + M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY, + M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), + M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID, + M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), + M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), + M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), + M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), + M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), + M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), + M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), + M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), + M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY, + M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), + M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID, + M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), + M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY, + M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), + M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID, + M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), + M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), + M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST, + M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY, + M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), + M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID, + M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), + M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), + M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST, + M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY, + M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), + M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID, + PS_CLK => FIXED_IO_ps_clk, + PS_PORB => FIXED_IO_ps_porb, + PS_SRSTB => FIXED_IO_ps_srstb, + SDIO0_WP => xlconstant_0_dout(0), + S_AXI_ACP_ACLK => processing_system7_0_FCLK_CLK0, + S_AXI_ACP_ARADDR(31 downto 0) => S_AXI_ACP_2_ARADDR(31 downto 0), + S_AXI_ACP_ARBURST(1 downto 0) => S_AXI_ACP_2_ARBURST(1 downto 0), + S_AXI_ACP_ARCACHE(3 downto 0) => S_AXI_ACP_2_ARCACHE(3 downto 0), + S_AXI_ACP_ARID(2 downto 0) => B"000", + S_AXI_ACP_ARLEN(3 downto 0) => S_AXI_ACP_2_ARLEN(3 downto 0), + S_AXI_ACP_ARLOCK(1 downto 0) => S_AXI_ACP_2_ARLOCK(1 downto 0), + S_AXI_ACP_ARPROT(2 downto 0) => S_AXI_ACP_2_ARPROT(2 downto 0), + S_AXI_ACP_ARQOS(3 downto 0) => S_AXI_ACP_2_ARQOS(3 downto 0), + S_AXI_ACP_ARREADY => S_AXI_ACP_2_ARREADY, + S_AXI_ACP_ARSIZE(2 downto 0) => S_AXI_ACP_2_ARSIZE(2 downto 0), + S_AXI_ACP_ARUSER(4 downto 0) => B"00000", + S_AXI_ACP_ARVALID => S_AXI_ACP_2_ARVALID, + S_AXI_ACP_AWADDR(31 downto 0) => S_AXI_ACP_2_AWADDR(31 downto 0), + S_AXI_ACP_AWBURST(1 downto 0) => S_AXI_ACP_2_AWBURST(1 downto 0), + S_AXI_ACP_AWCACHE(3 downto 0) => S_AXI_ACP_2_AWCACHE(3 downto 0), + S_AXI_ACP_AWID(2 downto 0) => B"000", + S_AXI_ACP_AWLEN(3 downto 0) => S_AXI_ACP_2_AWLEN(3 downto 0), + S_AXI_ACP_AWLOCK(1 downto 0) => S_AXI_ACP_2_AWLOCK(1 downto 0), + S_AXI_ACP_AWPROT(2 downto 0) => S_AXI_ACP_2_AWPROT(2 downto 0), + S_AXI_ACP_AWQOS(3 downto 0) => S_AXI_ACP_2_AWQOS(3 downto 0), + S_AXI_ACP_AWREADY => S_AXI_ACP_2_AWREADY, + S_AXI_ACP_AWSIZE(2 downto 0) => S_AXI_ACP_2_AWSIZE(2 downto 0), + S_AXI_ACP_AWUSER(4 downto 0) => B"00000", + S_AXI_ACP_AWVALID => S_AXI_ACP_2_AWVALID, + S_AXI_ACP_BID(2 downto 0) => NLW_processing_system7_0_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), + S_AXI_ACP_BREADY => S_AXI_ACP_2_BREADY, + S_AXI_ACP_BRESP(1 downto 0) => S_AXI_ACP_2_BRESP(1 downto 0), + S_AXI_ACP_BVALID => S_AXI_ACP_2_BVALID, + S_AXI_ACP_RDATA(63 downto 0) => S_AXI_ACP_2_RDATA(63 downto 0), + S_AXI_ACP_RID(2 downto 0) => NLW_processing_system7_0_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), + S_AXI_ACP_RLAST => S_AXI_ACP_2_RLAST, + S_AXI_ACP_RREADY => S_AXI_ACP_2_RREADY, + S_AXI_ACP_RRESP(1 downto 0) => S_AXI_ACP_2_RRESP(1 downto 0), + S_AXI_ACP_RVALID => S_AXI_ACP_2_RVALID, + S_AXI_ACP_WDATA(63 downto 0) => S_AXI_ACP_2_WDATA(63 downto 0), + S_AXI_ACP_WID(2 downto 0) => B"000", + S_AXI_ACP_WLAST => S_AXI_ACP_2_WLAST, + S_AXI_ACP_WREADY => S_AXI_ACP_2_WREADY, + S_AXI_ACP_WSTRB(7 downto 0) => S_AXI_ACP_2_WSTRB(7 downto 0), + S_AXI_ACP_WVALID => S_AXI_ACP_2_WVALID, + S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0, + S_AXI_HP0_ARADDR(31 downto 0) => S_AXI_ACP_1_ARADDR(31 downto 0), + S_AXI_HP0_ARBURST(1 downto 0) => S_AXI_ACP_1_ARBURST(1 downto 0), + S_AXI_HP0_ARCACHE(3 downto 0) => S_AXI_ACP_1_ARCACHE(3 downto 0), + S_AXI_HP0_ARID(5 downto 0) => B"000000", + S_AXI_HP0_ARLEN(3 downto 0) => S_AXI_ACP_1_ARLEN(3 downto 0), + S_AXI_HP0_ARLOCK(1 downto 0) => S_AXI_ACP_1_ARLOCK(1 downto 0), + S_AXI_HP0_ARPROT(2 downto 0) => S_AXI_ACP_1_ARPROT(2 downto 0), + S_AXI_HP0_ARQOS(3 downto 0) => S_AXI_ACP_1_ARQOS(3 downto 0), + S_AXI_HP0_ARREADY => S_AXI_ACP_1_ARREADY, + S_AXI_HP0_ARSIZE(2 downto 0) => S_AXI_ACP_1_ARSIZE(2 downto 0), + S_AXI_HP0_ARVALID => S_AXI_ACP_1_ARVALID, + S_AXI_HP0_AWADDR(31 downto 0) => S_AXI_ACP_1_AWADDR(31 downto 0), + S_AXI_HP0_AWBURST(1 downto 0) => S_AXI_ACP_1_AWBURST(1 downto 0), + S_AXI_HP0_AWCACHE(3 downto 0) => S_AXI_ACP_1_AWCACHE(3 downto 0), + S_AXI_HP0_AWID(5 downto 0) => B"000000", + S_AXI_HP0_AWLEN(3 downto 0) => S_AXI_ACP_1_AWLEN(3 downto 0), + S_AXI_HP0_AWLOCK(1 downto 0) => S_AXI_ACP_1_AWLOCK(1 downto 0), + S_AXI_HP0_AWPROT(2 downto 0) => S_AXI_ACP_1_AWPROT(2 downto 0), + S_AXI_HP0_AWQOS(3 downto 0) => S_AXI_ACP_1_AWQOS(3 downto 0), + S_AXI_HP0_AWREADY => S_AXI_ACP_1_AWREADY, + S_AXI_HP0_AWSIZE(2 downto 0) => S_AXI_ACP_1_AWSIZE(2 downto 0), + S_AXI_HP0_AWVALID => S_AXI_ACP_1_AWVALID, + S_AXI_HP0_BID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), + S_AXI_HP0_BREADY => S_AXI_ACP_1_BREADY, + S_AXI_HP0_BRESP(1 downto 0) => S_AXI_ACP_1_BRESP(1 downto 0), + S_AXI_HP0_BVALID => S_AXI_ACP_1_BVALID, + S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), + S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP0_RDATA(63 downto 0) => S_AXI_ACP_1_RDATA(63 downto 0), + S_AXI_HP0_RDISSUECAP1_EN => '0', + S_AXI_HP0_RID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), + S_AXI_HP0_RLAST => S_AXI_ACP_1_RLAST, + S_AXI_HP0_RREADY => S_AXI_ACP_1_RREADY, + S_AXI_HP0_RRESP(1 downto 0) => S_AXI_ACP_1_RRESP(1 downto 0), + S_AXI_HP0_RVALID => S_AXI_ACP_1_RVALID, + S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), + S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP0_WDATA(63 downto 0) => S_AXI_ACP_1_WDATA(63 downto 0), + S_AXI_HP0_WID(5 downto 0) => B"000000", + S_AXI_HP0_WLAST => S_AXI_ACP_1_WLAST, + S_AXI_HP0_WREADY => S_AXI_ACP_1_WREADY, + S_AXI_HP0_WRISSUECAP1_EN => '0', + S_AXI_HP0_WSTRB(7 downto 0) => S_AXI_ACP_1_WSTRB(7 downto 0), + S_AXI_HP0_WVALID => S_AXI_ACP_1_WVALID, + TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED, + TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED, + TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED, + USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), + USB0_VBUS_PWRFAULT => '0', + USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED + ); +rst_ps7_0_100M: component design_3_rst_ps7_0_100M_0 + port map ( + aux_reset_in => '1', + bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0), + dcm_locked => '1', + ext_reset_in => processing_system7_0_FCLK_RESET0_N, + interconnect_aresetn(0) => NLW_rst_ps7_0_100M_interconnect_aresetn_UNCONNECTED(0), + mb_debug_sys_rst => '0', + mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED, + peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0), + peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0), + slowest_sync_clk => processing_system7_0_FCLK_CLK0 + ); +xlconcat_0: component design_3_xlconcat_0_0 + port map ( + In0(0) => In0_1(0), + In1(0) => In1_1, + dout(1 downto 0) => xlconcat_0_dout(1 downto 0) + ); +xlconstant_0: component design_3_xlconstant_0_0 + port map ( + dout(0) => xlconstant_0_dout(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity VideoSubsystem_imp_RHI5N8 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_AXIL1_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL1_arready : out STD_LOGIC; + S_AXIL1_arvalid : in STD_LOGIC; + S_AXIL1_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL1_awready : out STD_LOGIC; + S_AXIL1_awvalid : in STD_LOGIC; + S_AXIL1_bready : in STD_LOGIC; + S_AXIL1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL1_bvalid : out STD_LOGIC; + S_AXIL1_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL1_rready : in STD_LOGIC; + S_AXIL1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL1_rvalid : out STD_LOGIC; + S_AXIL1_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL1_wready : out STD_LOGIC; + S_AXIL1_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL1_wvalid : in STD_LOGIC; + S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_arready : out STD_LOGIC; + S_AXIL_arvalid : in STD_LOGIC; + S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_awready : out STD_LOGIC; + S_AXIL_awvalid : in STD_LOGIC; + S_AXIL_bready : in STD_LOGIC; + S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_bvalid : out STD_LOGIC; + S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_rready : in STD_LOGIC; + S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_rvalid : out STD_LOGIC; + S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_wready : out STD_LOGIC; + S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_wvalid : in STD_LOGIC; + VS2MM_INTERRUPT : out STD_LOGIC + ); +end VideoSubsystem_imp_RHI5N8; + +architecture STRUCTURE of VideoSubsystem_imp_RHI5N8 is + component design_3_axis_downsizer_0_0 is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC + ); + end component design_3_axis_downsizer_0_0; + component design_3_axis_upsizer_0_0 is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC + ); + end component design_3_axis_upsizer_0_0; + component design_3_axis_linemem_single_0_0 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_tlast : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tuser : out STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + end component design_3_axis_linemem_single_0_0; + component design_3_axis_video_filter_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC; + S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 14 downto 0 ); + S_AXIL_AWVALID : in STD_LOGIC; + S_AXIL_AWREADY : out STD_LOGIC; + S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_WVALID : in STD_LOGIC; + S_AXIL_WREADY : out STD_LOGIC; + S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_BVALID : out STD_LOGIC; + S_AXIL_BREADY : in STD_LOGIC; + S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 14 downto 0 ); + S_AXIL_ARVALID : in STD_LOGIC; + S_AXIL_ARREADY : out STD_LOGIC; + S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_RVALID : out STD_LOGIC; + S_AXIL_RREADY : in STD_LOGIC; + S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component design_3_axis_video_filter_0_0; + component design_3_axi_2d_mmvs_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ); + MM2VS_INTERRUPT : out STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ); + VS2MM_INTERRUPT : out STD_LOGIC; + S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIL_AWVALID : in STD_LOGIC; + S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_WVALID : in STD_LOGIC; + S_AXIL_WREADY : out STD_LOGIC; + S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_BVALID : out STD_LOGIC; + S_AXIL_AWREADY : out STD_LOGIC; + S_AXIL_BREADY : in STD_LOGIC; + S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIL_ARVALID : in STD_LOGIC; + S_AXIL_RREADY : in STD_LOGIC; + S_AXIL_ARREADY : out STD_LOGIC; + S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_RVALID : out STD_LOGIC; + M_AXI_ARREADY : in STD_LOGIC; + M_AXI_ARVALID : out STD_LOGIC; + M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_RREADY : out STD_LOGIC; + M_AXI_RVALID : in STD_LOGIC; + M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_RLAST : in STD_LOGIC; + M_AXI_AWREADY : in STD_LOGIC; + M_AXI_AWVALID : out STD_LOGIC; + M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WREADY : in STD_LOGIC; + M_AXI_WVALID : out STD_LOGIC; + M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WLAST : out STD_LOGIC; + M_AXI_WID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_BREADY : out STD_LOGIC; + M_AXI_BVALID : in STD_LOGIC; + M_AXI_BID : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component design_3_axi_2d_mmvs_0_0; + signal Net : STD_LOGIC; + signal Net1 : STD_LOGIC; + signal S_AXIL1_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_ARREADY : STD_LOGIC; + signal S_AXIL1_1_ARVALID : STD_LOGIC; + signal S_AXIL1_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_AWREADY : STD_LOGIC; + signal S_AXIL1_1_AWVALID : STD_LOGIC; + signal S_AXIL1_1_BREADY : STD_LOGIC; + signal S_AXIL1_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL1_1_BVALID : STD_LOGIC; + signal S_AXIL1_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_RREADY : STD_LOGIC; + signal S_AXIL1_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL1_1_RVALID : STD_LOGIC; + signal S_AXIL1_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_WREADY : STD_LOGIC; + signal S_AXIL1_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL1_1_WVALID : STD_LOGIC; + signal S_AXIL_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_ARREADY : STD_LOGIC; + signal S_AXIL_1_ARVALID : STD_LOGIC; + signal S_AXIL_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_AWREADY : STD_LOGIC; + signal S_AXIL_1_AWVALID : STD_LOGIC; + signal S_AXIL_1_BREADY : STD_LOGIC; + signal S_AXIL_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL_1_BVALID : STD_LOGIC; + signal S_AXIL_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_RREADY : STD_LOGIC; + signal S_AXIL_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL_1_RVALID : STD_LOGIC; + signal S_AXIL_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_WREADY : STD_LOGIC; + signal S_AXIL_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL_1_WVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXIS_TLAST : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXIS_TREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXIS_TVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXI_BREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_BVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXI_RLAST : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_RREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_RVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_WLAST : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_WREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_WVALID : STD_LOGIC; + signal axi_2d_mmvs_0_VS2MM_INTERRUPT : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TUSER : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_linemem_single_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal axis_linemem_single_0_m_axis_TLAST : STD_LOGIC; + signal axis_linemem_single_0_m_axis_TREADY : STD_LOGIC; + signal axis_linemem_single_0_m_axis_TUSER : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axis_linemem_single_0_m_axis_TVALID : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_video_filter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axis_video_filter_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_video_filter_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_video_filter_0_M_AXIS_TUSER : STD_LOGIC; + signal axis_video_filter_0_M_AXIS_TVALID : STD_LOGIC; + signal NLW_axi_2d_mmvs_0_MM2VS_INTERRUPT_UNCONNECTED : STD_LOGIC; + signal NLW_axi_2d_mmvs_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); +begin + M_AXI_araddr(31 downto 0) <= axi_2d_mmvs_0_M_AXI_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= axi_2d_mmvs_0_M_AXI_ARBURST(1 downto 0); + M_AXI_arcache(3 downto 0) <= axi_2d_mmvs_0_M_AXI_ARCACHE(3 downto 0); + M_AXI_arid(0) <= axi_2d_mmvs_0_M_AXI_ARID(0); + M_AXI_arlen(3 downto 0) <= axi_2d_mmvs_0_M_AXI_ARLEN(3 downto 0); + M_AXI_arprot(2 downto 0) <= axi_2d_mmvs_0_M_AXI_ARPROT(2 downto 0); + M_AXI_arsize(2 downto 0) <= axi_2d_mmvs_0_M_AXI_ARSIZE(2 downto 0); + M_AXI_arvalid <= axi_2d_mmvs_0_M_AXI_ARVALID; + M_AXI_awaddr(31 downto 0) <= axi_2d_mmvs_0_M_AXI_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= axi_2d_mmvs_0_M_AXI_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= axi_2d_mmvs_0_M_AXI_AWCACHE(3 downto 0); + M_AXI_awid(0) <= axi_2d_mmvs_0_M_AXI_AWID(0); + M_AXI_awlen(3 downto 0) <= axi_2d_mmvs_0_M_AXI_AWLEN(3 downto 0); + M_AXI_awprot(2 downto 0) <= axi_2d_mmvs_0_M_AXI_AWPROT(2 downto 0); + M_AXI_awsize(2 downto 0) <= axi_2d_mmvs_0_M_AXI_AWSIZE(2 downto 0); + M_AXI_awvalid <= axi_2d_mmvs_0_M_AXI_AWVALID; + M_AXI_bready <= axi_2d_mmvs_0_M_AXI_BREADY; + M_AXI_rready <= axi_2d_mmvs_0_M_AXI_RREADY; + M_AXI_wdata(31 downto 0) <= axi_2d_mmvs_0_M_AXI_WDATA(31 downto 0); + M_AXI_wlast <= axi_2d_mmvs_0_M_AXI_WLAST; + M_AXI_wstrb(3 downto 0) <= axi_2d_mmvs_0_M_AXI_WSTRB(3 downto 0); + M_AXI_wvalid <= axi_2d_mmvs_0_M_AXI_WVALID; + Net <= ACLK; + Net1 <= ARESETN; + S_AXIL1_1_ARADDR(31 downto 0) <= S_AXIL1_araddr(31 downto 0); + S_AXIL1_1_ARVALID <= S_AXIL1_arvalid; + S_AXIL1_1_AWADDR(31 downto 0) <= S_AXIL1_awaddr(31 downto 0); + S_AXIL1_1_AWVALID <= S_AXIL1_awvalid; + S_AXIL1_1_BREADY <= S_AXIL1_bready; + S_AXIL1_1_RREADY <= S_AXIL1_rready; + S_AXIL1_1_WDATA(31 downto 0) <= S_AXIL1_wdata(31 downto 0); + S_AXIL1_1_WSTRB(3 downto 0) <= S_AXIL1_wstrb(3 downto 0); + S_AXIL1_1_WVALID <= S_AXIL1_wvalid; + S_AXIL1_arready <= S_AXIL1_1_ARREADY; + S_AXIL1_awready <= S_AXIL1_1_AWREADY; + S_AXIL1_bresp(1 downto 0) <= S_AXIL1_1_BRESP(1 downto 0); + S_AXIL1_bvalid <= S_AXIL1_1_BVALID; + S_AXIL1_rdata(31 downto 0) <= S_AXIL1_1_RDATA(31 downto 0); + S_AXIL1_rresp(1 downto 0) <= S_AXIL1_1_RRESP(1 downto 0); + S_AXIL1_rvalid <= S_AXIL1_1_RVALID; + S_AXIL1_wready <= S_AXIL1_1_WREADY; + S_AXIL_1_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0); + S_AXIL_1_ARVALID <= S_AXIL_arvalid; + S_AXIL_1_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0); + S_AXIL_1_AWVALID <= S_AXIL_awvalid; + S_AXIL_1_BREADY <= S_AXIL_bready; + S_AXIL_1_RREADY <= S_AXIL_rready; + S_AXIL_1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0); + S_AXIL_1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0); + S_AXIL_1_WVALID <= S_AXIL_wvalid; + S_AXIL_arready <= S_AXIL_1_ARREADY; + S_AXIL_awready <= S_AXIL_1_AWREADY; + S_AXIL_bresp(1 downto 0) <= S_AXIL_1_BRESP(1 downto 0); + S_AXIL_bvalid <= S_AXIL_1_BVALID; + S_AXIL_rdata(31 downto 0) <= S_AXIL_1_RDATA(31 downto 0); + S_AXIL_rresp(1 downto 0) <= S_AXIL_1_RRESP(1 downto 0); + S_AXIL_rvalid <= S_AXIL_1_RVALID; + S_AXIL_wready <= S_AXIL_1_WREADY; + VS2MM_INTERRUPT <= axi_2d_mmvs_0_VS2MM_INTERRUPT; + axi_2d_mmvs_0_M_AXI_ARREADY <= M_AXI_arready; + axi_2d_mmvs_0_M_AXI_AWREADY <= M_AXI_awready; + axi_2d_mmvs_0_M_AXI_BID(0) <= M_AXI_bid(0); + axi_2d_mmvs_0_M_AXI_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + axi_2d_mmvs_0_M_AXI_BVALID <= M_AXI_bvalid; + axi_2d_mmvs_0_M_AXI_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + axi_2d_mmvs_0_M_AXI_RID(0) <= M_AXI_rid(0); + axi_2d_mmvs_0_M_AXI_RLAST <= M_AXI_rlast; + axi_2d_mmvs_0_M_AXI_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + axi_2d_mmvs_0_M_AXI_RVALID <= M_AXI_rvalid; + axi_2d_mmvs_0_M_AXI_WREADY <= M_AXI_wready; +axi_2d_mmvs_0: component design_3_axi_2d_mmvs_0_0 + port map ( + ACLK => Net, + ARESETN => Net1, + MM2VS_INTERRUPT => NLW_axi_2d_mmvs_0_MM2VS_INTERRUPT_UNCONNECTED, + M_AXIS_TDATA(31 downto 0) => axi_2d_mmvs_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axi_2d_mmvs_0_M_AXIS_TLAST, + M_AXIS_TREADY => axi_2d_mmvs_0_M_AXIS_TREADY, + M_AXIS_TUSER(0) => axi_2d_mmvs_0_M_AXIS_TUSER(0), + M_AXIS_TVALID => axi_2d_mmvs_0_M_AXIS_TVALID, + M_AXI_ARADDR(31 downto 0) => axi_2d_mmvs_0_M_AXI_ARADDR(31 downto 0), + M_AXI_ARBURST(1 downto 0) => axi_2d_mmvs_0_M_AXI_ARBURST(1 downto 0), + M_AXI_ARCACHE(3 downto 0) => axi_2d_mmvs_0_M_AXI_ARCACHE(3 downto 0), + M_AXI_ARID(0) => axi_2d_mmvs_0_M_AXI_ARID(0), + M_AXI_ARLEN(3 downto 0) => axi_2d_mmvs_0_M_AXI_ARLEN(3 downto 0), + M_AXI_ARPROT(2 downto 0) => axi_2d_mmvs_0_M_AXI_ARPROT(2 downto 0), + M_AXI_ARREADY => axi_2d_mmvs_0_M_AXI_ARREADY, + M_AXI_ARSIZE(2 downto 0) => axi_2d_mmvs_0_M_AXI_ARSIZE(2 downto 0), + M_AXI_ARVALID => axi_2d_mmvs_0_M_AXI_ARVALID, + M_AXI_AWADDR(31 downto 0) => axi_2d_mmvs_0_M_AXI_AWADDR(31 downto 0), + M_AXI_AWBURST(1 downto 0) => axi_2d_mmvs_0_M_AXI_AWBURST(1 downto 0), + M_AXI_AWCACHE(3 downto 0) => axi_2d_mmvs_0_M_AXI_AWCACHE(3 downto 0), + M_AXI_AWID(0) => axi_2d_mmvs_0_M_AXI_AWID(0), + M_AXI_AWLEN(3 downto 0) => axi_2d_mmvs_0_M_AXI_AWLEN(3 downto 0), + M_AXI_AWPROT(2 downto 0) => axi_2d_mmvs_0_M_AXI_AWPROT(2 downto 0), + M_AXI_AWREADY => axi_2d_mmvs_0_M_AXI_AWREADY, + M_AXI_AWSIZE(2 downto 0) => axi_2d_mmvs_0_M_AXI_AWSIZE(2 downto 0), + M_AXI_AWVALID => axi_2d_mmvs_0_M_AXI_AWVALID, + M_AXI_BID(0) => axi_2d_mmvs_0_M_AXI_BID(0), + M_AXI_BREADY => axi_2d_mmvs_0_M_AXI_BREADY, + M_AXI_BRESP(1 downto 0) => axi_2d_mmvs_0_M_AXI_BRESP(1 downto 0), + M_AXI_BVALID => axi_2d_mmvs_0_M_AXI_BVALID, + M_AXI_RDATA(31 downto 0) => axi_2d_mmvs_0_M_AXI_RDATA(31 downto 0), + M_AXI_RID(0) => axi_2d_mmvs_0_M_AXI_RID(0), + M_AXI_RLAST => axi_2d_mmvs_0_M_AXI_RLAST, + M_AXI_RREADY => axi_2d_mmvs_0_M_AXI_RREADY, + M_AXI_RRESP(1 downto 0) => axi_2d_mmvs_0_M_AXI_RRESP(1 downto 0), + M_AXI_RVALID => axi_2d_mmvs_0_M_AXI_RVALID, + M_AXI_WDATA(31 downto 0) => axi_2d_mmvs_0_M_AXI_WDATA(31 downto 0), + M_AXI_WID(0) => NLW_axi_2d_mmvs_0_M_AXI_WID_UNCONNECTED(0), + M_AXI_WLAST => axi_2d_mmvs_0_M_AXI_WLAST, + M_AXI_WREADY => axi_2d_mmvs_0_M_AXI_WREADY, + M_AXI_WSTRB(3 downto 0) => axi_2d_mmvs_0_M_AXI_WSTRB(3 downto 0), + M_AXI_WVALID => axi_2d_mmvs_0_M_AXI_WVALID, + S_AXIL_ARADDR(15 downto 0) => S_AXIL1_1_ARADDR(15 downto 0), + S_AXIL_ARREADY => S_AXIL1_1_ARREADY, + S_AXIL_ARVALID => S_AXIL1_1_ARVALID, + S_AXIL_AWADDR(15 downto 0) => S_AXIL1_1_AWADDR(15 downto 0), + S_AXIL_AWREADY => S_AXIL1_1_AWREADY, + S_AXIL_AWVALID => S_AXIL1_1_AWVALID, + S_AXIL_BREADY => S_AXIL1_1_BREADY, + S_AXIL_BRESP(1 downto 0) => S_AXIL1_1_BRESP(1 downto 0), + S_AXIL_BVALID => S_AXIL1_1_BVALID, + S_AXIL_RDATA(31 downto 0) => S_AXIL1_1_RDATA(31 downto 0), + S_AXIL_RREADY => S_AXIL1_1_RREADY, + S_AXIL_RRESP(1 downto 0) => S_AXIL1_1_RRESP(1 downto 0), + S_AXIL_RVALID => S_AXIL1_1_RVALID, + S_AXIL_WDATA(31 downto 0) => S_AXIL1_1_WDATA(31 downto 0), + S_AXIL_WREADY => S_AXIL1_1_WREADY, + S_AXIL_WSTRB(3 downto 0) => S_AXIL1_1_WSTRB(3 downto 0), + S_AXIL_WVALID => S_AXIL1_1_WVALID, + S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + S_AXIS_TUSER(0) => axis_upsizer_0_M_AXIS_TUSER, + S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + VS2MM_INTERRUPT => axi_2d_mmvs_0_VS2MM_INTERRUPT + ); +axis_downsizer_0: component design_3_axis_downsizer_0_0 + port map ( + AXIS_ACLK => Net, + AXIS_ARESETN => Net1, + M_AXIS_TDATA(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0), + M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY, + M_AXIS_TUSER => axis_downsizer_0_M_AXIS_TUSER, + M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID, + S_AXIS_TDATA(31 downto 0) => axi_2d_mmvs_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axi_2d_mmvs_0_M_AXIS_TLAST, + S_AXIS_TREADY => axi_2d_mmvs_0_M_AXIS_TREADY, + S_AXIS_TUSER => axi_2d_mmvs_0_M_AXIS_TUSER(0), + S_AXIS_TVALID => axi_2d_mmvs_0_M_AXIS_TVALID + ); +axis_linemem_single_0: component design_3_axis_linemem_single_0_0 + port map ( + aclk => Net, + aresetn => Net1, + m_axis_tdata(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0), + m_axis_tlast => axis_linemem_single_0_m_axis_TLAST, + m_axis_tready => axis_linemem_single_0_m_axis_TREADY, + m_axis_tuser(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0), + m_axis_tvalid => axis_linemem_single_0_m_axis_TVALID, + s_axis_tdata(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0), + s_axis_tlast => axis_downsizer_0_M_AXIS_TLAST, + s_axis_tready => axis_downsizer_0_M_AXIS_TREADY, + s_axis_tuser(0) => axis_downsizer_0_M_AXIS_TUSER, + s_axis_tvalid => axis_downsizer_0_M_AXIS_TVALID + ); +axis_upsizer_0: component design_3_axis_upsizer_0_0 + port map ( + AXIS_ACLK => Net, + AXIS_ARESETN => Net1, + M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + M_AXIS_TUSER => axis_upsizer_0_M_AXIS_TUSER, + M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + S_AXIS_TDATA(7 downto 0) => axis_video_filter_0_M_AXIS_TDATA(7 downto 0), + S_AXIS_TLAST => axis_video_filter_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_video_filter_0_M_AXIS_TREADY, + S_AXIS_TUSER => axis_video_filter_0_M_AXIS_TUSER, + S_AXIS_TVALID => axis_video_filter_0_M_AXIS_TVALID + ); +axis_video_filter_0: component design_3_axis_video_filter_0_0 + port map ( + ACLK => Net, + ARESETN => Net1, + M_AXIS_TDATA(7 downto 0) => axis_video_filter_0_M_AXIS_TDATA(7 downto 0), + M_AXIS_TLAST => axis_video_filter_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_video_filter_0_M_AXIS_TREADY, + M_AXIS_TUSER => axis_video_filter_0_M_AXIS_TUSER, + M_AXIS_TVALID => axis_video_filter_0_M_AXIS_TVALID, + S_AXIL_ARADDR(14 downto 0) => S_AXIL_1_ARADDR(14 downto 0), + S_AXIL_ARREADY => S_AXIL_1_ARREADY, + S_AXIL_ARVALID => S_AXIL_1_ARVALID, + S_AXIL_AWADDR(14 downto 0) => S_AXIL_1_AWADDR(14 downto 0), + S_AXIL_AWREADY => S_AXIL_1_AWREADY, + S_AXIL_AWVALID => S_AXIL_1_AWVALID, + S_AXIL_BREADY => S_AXIL_1_BREADY, + S_AXIL_BRESP(1 downto 0) => S_AXIL_1_BRESP(1 downto 0), + S_AXIL_BVALID => S_AXIL_1_BVALID, + S_AXIL_RDATA(31 downto 0) => S_AXIL_1_RDATA(31 downto 0), + S_AXIL_RREADY => S_AXIL_1_RREADY, + S_AXIL_RRESP(1 downto 0) => S_AXIL_1_RRESP(1 downto 0), + S_AXIL_RVALID => S_AXIL_1_RVALID, + S_AXIL_WDATA(31 downto 0) => S_AXIL_1_WDATA(31 downto 0), + S_AXIL_WREADY => S_AXIL_1_WREADY, + S_AXIL_WSTRB(3 downto 0) => S_AXIL_1_WSTRB(3 downto 0), + S_AXIL_WVALID => S_AXIL_1_WVALID, + S_AXIS_TDATA(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0), + S_AXIS_TLAST => axis_linemem_single_0_m_axis_TLAST, + S_AXIS_TREADY => axis_linemem_single_0_m_axis_TREADY, + S_AXIS_TUSER(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0), + S_AXIS_TVALID => axis_linemem_single_0_m_axis_TVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ZYNQ_BASE_imp_1TRJPP2 is + port ( + BUTTON_0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + HDMI_CLK_N_0 : out STD_LOGIC; + HDMI_CLK_P_0 : out STD_LOGIC; + HDMI_DATA_N_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_DATA_P_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + LED_0 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ACLK : in STD_LOGIC; + M_AXI_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + RGB_LED_0 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + SWITCH_0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_arready : out STD_LOGIC; + S_AXIL_arvalid : in STD_LOGIC; + S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_awready : out STD_LOGIC; + S_AXIL_awvalid : in STD_LOGIC; + S_AXIL_bready : in STD_LOGIC; + S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_bvalid : out STD_LOGIC; + S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_rready : in STD_LOGIC; + S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_rvalid : out STD_LOGIC; + S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_wready : out STD_LOGIC; + S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_wvalid : in STD_LOGIC; + VIDEO_CLK : in STD_LOGIC; + VIDEO_INTERRUPT : out STD_LOGIC + ); +end ZYNQ_BASE_imp_1TRJPP2; + +architecture STRUCTURE of ZYNQ_BASE_imp_1TRJPP2 is + component design_3_zynq_base_hdmi_0_0 is + port ( + VIDEO_CLK : in STD_LOGIC; + VIDEO_RESETN : in STD_LOGIC; + HDMI_DATA_P : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_DATA_N : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_CLK_P : out STD_LOGIC; + HDMI_CLK_N : out STD_LOGIC; + VIDEO_INTERRUPT : out STD_LOGIC; + SWITCH : in STD_LOGIC_VECTOR ( 3 downto 0 ); + BUTTON : in STD_LOGIC_VECTOR ( 3 downto 0 ); + LED : out STD_LOGIC_VECTOR ( 3 downto 0 ); + RGB_LED : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXIL_ACLK : in STD_LOGIC; + S_AXIL_ARESETN : in STD_LOGIC; + S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIL_AWVALID : in STD_LOGIC; + S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_WVALID : in STD_LOGIC; + S_AXIL_BREADY : in STD_LOGIC; + S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIL_ARVALID : in STD_LOGIC; + S_AXIL_RREADY : in STD_LOGIC; + S_AXIL_ARREADY : out STD_LOGIC; + S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_RVALID : out STD_LOGIC; + S_AXIL_WREADY : out STD_LOGIC; + S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_BVALID : out STD_LOGIC; + S_AXIL_AWREADY : out STD_LOGIC; + M_AXI_ACLK : in STD_LOGIC; + M_AXI_ARESETN : in STD_LOGIC; + M_AXI_ARREADY : in STD_LOGIC; + M_AXI_ARVALID : out STD_LOGIC; + M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ARID : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_RREADY : out STD_LOGIC; + M_AXI_RVALID : in STD_LOGIC; + M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_RLAST : in STD_LOGIC; + M_AXI_RID : in STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_AWREADY : in STD_LOGIC; + M_AXI_AWVALID : out STD_LOGIC; + M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WREADY : in STD_LOGIC; + M_AXI_WVALID : out STD_LOGIC; + M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WLAST : out STD_LOGIC; + M_AXI_BREADY : out STD_LOGIC; + M_AXI_BVALID : in STD_LOGIC; + M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component design_3_zynq_base_hdmi_0_0; + signal BUTTON_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal SWITCH_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; + signal processing_system7_0_FCLK_CLK3 : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC; + signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_CLK_N : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_CLK_P : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_DATA_N : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_HDMI_DATA_P : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_LED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_BVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WVALID : STD_LOGIC; + signal zynq_base_hdmi_0_RGB_LED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal zynq_base_hdmi_0_VIDEO_INTERRUPT : STD_LOGIC; +begin + BUTTON_0_1(3 downto 0) <= BUTTON_0(3 downto 0); + HDMI_CLK_N_0 <= zynq_base_hdmi_0_HDMI_CLK_N; + HDMI_CLK_P_0 <= zynq_base_hdmi_0_HDMI_CLK_P; + HDMI_DATA_N_0(2 downto 0) <= zynq_base_hdmi_0_HDMI_DATA_N(2 downto 0); + HDMI_DATA_P_0(2 downto 0) <= zynq_base_hdmi_0_HDMI_DATA_P(2 downto 0); + LED_0(3 downto 0) <= zynq_base_hdmi_0_LED(3 downto 0); + M_AXI_araddr(31 downto 0) <= zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0); + M_AXI_arcache(3 downto 0) <= zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0); + M_AXI_arid(3 downto 0) <= zynq_base_hdmi_0_M_AXI_ARID(3 downto 0); + M_AXI_arlen(3 downto 0) <= zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0); + M_AXI_arprot(2 downto 0) <= zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0); + M_AXI_arsize(2 downto 0) <= zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0); + M_AXI_arvalid <= zynq_base_hdmi_0_M_AXI_ARVALID; + M_AXI_awaddr(31 downto 0) <= zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0); + M_AXI_awlen(3 downto 0) <= zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0); + M_AXI_awprot(2 downto 0) <= zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0); + M_AXI_awsize(2 downto 0) <= zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0); + M_AXI_awvalid <= zynq_base_hdmi_0_M_AXI_AWVALID; + M_AXI_bready <= zynq_base_hdmi_0_M_AXI_BREADY; + M_AXI_rready <= zynq_base_hdmi_0_M_AXI_RREADY; + M_AXI_wdata(31 downto 0) <= zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0); + M_AXI_wlast <= zynq_base_hdmi_0_M_AXI_WLAST; + M_AXI_wstrb(3 downto 0) <= zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0); + M_AXI_wvalid <= zynq_base_hdmi_0_M_AXI_WVALID; + RGB_LED_0(5 downto 0) <= zynq_base_hdmi_0_RGB_LED(5 downto 0); + SWITCH_0_1(3 downto 0) <= SWITCH_0(3 downto 0); + S_AXIL_arready <= ps7_0_axi_periph_M00_AXI_ARREADY; + S_AXIL_awready <= ps7_0_axi_periph_M00_AXI_AWREADY; + S_AXIL_bresp(1 downto 0) <= ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0); + S_AXIL_bvalid <= ps7_0_axi_periph_M00_AXI_BVALID; + S_AXIL_rdata(31 downto 0) <= ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0); + S_AXIL_rresp(1 downto 0) <= ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0); + S_AXIL_rvalid <= ps7_0_axi_periph_M00_AXI_RVALID; + S_AXIL_wready <= ps7_0_axi_periph_M00_AXI_WREADY; + VIDEO_INTERRUPT <= zynq_base_hdmi_0_VIDEO_INTERRUPT; + processing_system7_0_FCLK_CLK0 <= M_AXI_ACLK; + processing_system7_0_FCLK_CLK3 <= VIDEO_CLK; + ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0); + ps7_0_axi_periph_M00_AXI_ARVALID <= S_AXIL_arvalid; + ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0); + ps7_0_axi_periph_M00_AXI_AWVALID <= S_AXIL_awvalid; + ps7_0_axi_periph_M00_AXI_BREADY <= S_AXIL_bready; + ps7_0_axi_periph_M00_AXI_RREADY <= S_AXIL_rready; + ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0); + ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0); + ps7_0_axi_periph_M00_AXI_WVALID <= S_AXIL_wvalid; + rst_ps7_0_100M_peripheral_aresetn <= M_AXI_ARESETN; + zynq_base_hdmi_0_M_AXI_ARREADY <= M_AXI_arready; + zynq_base_hdmi_0_M_AXI_AWREADY <= M_AXI_awready; + zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + zynq_base_hdmi_0_M_AXI_BVALID <= M_AXI_bvalid; + zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + zynq_base_hdmi_0_M_AXI_RID(3 downto 0) <= M_AXI_rid(3 downto 0); + zynq_base_hdmi_0_M_AXI_RLAST <= M_AXI_rlast; + zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + zynq_base_hdmi_0_M_AXI_RVALID <= M_AXI_rvalid; + zynq_base_hdmi_0_M_AXI_WREADY <= M_AXI_wready; +zynq_base_hdmi_0: component design_3_zynq_base_hdmi_0_0 + port map ( + BUTTON(3 downto 0) => BUTTON_0_1(3 downto 0), + HDMI_CLK_N => zynq_base_hdmi_0_HDMI_CLK_N, + HDMI_CLK_P => zynq_base_hdmi_0_HDMI_CLK_P, + HDMI_DATA_N(2 downto 0) => zynq_base_hdmi_0_HDMI_DATA_N(2 downto 0), + HDMI_DATA_P(2 downto 0) => zynq_base_hdmi_0_HDMI_DATA_P(2 downto 0), + LED(3 downto 0) => zynq_base_hdmi_0_LED(3 downto 0), + M_AXI_ACLK => processing_system7_0_FCLK_CLK0, + M_AXI_ARADDR(31 downto 0) => zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0), + M_AXI_ARBURST(1 downto 0) => zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0), + M_AXI_ARCACHE(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0), + M_AXI_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M_AXI_ARID(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARID(3 downto 0), + M_AXI_ARLEN(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0), + M_AXI_ARPROT(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0), + M_AXI_ARREADY => zynq_base_hdmi_0_M_AXI_ARREADY, + M_AXI_ARSIZE(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0), + M_AXI_ARVALID => zynq_base_hdmi_0_M_AXI_ARVALID, + M_AXI_AWADDR(31 downto 0) => zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0), + M_AXI_AWBURST(1 downto 0) => zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0), + M_AXI_AWCACHE(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0), + M_AXI_AWLEN(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0), + M_AXI_AWPROT(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0), + M_AXI_AWREADY => zynq_base_hdmi_0_M_AXI_AWREADY, + M_AXI_AWSIZE(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0), + M_AXI_AWVALID => zynq_base_hdmi_0_M_AXI_AWVALID, + M_AXI_BREADY => zynq_base_hdmi_0_M_AXI_BREADY, + M_AXI_BRESP(1 downto 0) => zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0), + M_AXI_BVALID => zynq_base_hdmi_0_M_AXI_BVALID, + M_AXI_RDATA(31 downto 0) => zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0), + M_AXI_RID(3 downto 0) => zynq_base_hdmi_0_M_AXI_RID(3 downto 0), + M_AXI_RLAST => zynq_base_hdmi_0_M_AXI_RLAST, + M_AXI_RREADY => zynq_base_hdmi_0_M_AXI_RREADY, + M_AXI_RRESP(1 downto 0) => zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0), + M_AXI_RVALID => zynq_base_hdmi_0_M_AXI_RVALID, + M_AXI_WDATA(31 downto 0) => zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0), + M_AXI_WLAST => zynq_base_hdmi_0_M_AXI_WLAST, + M_AXI_WREADY => zynq_base_hdmi_0_M_AXI_WREADY, + M_AXI_WSTRB(3 downto 0) => zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0), + M_AXI_WVALID => zynq_base_hdmi_0_M_AXI_WVALID, + RGB_LED(5 downto 0) => zynq_base_hdmi_0_RGB_LED(5 downto 0), + SWITCH(3 downto 0) => SWITCH_0_1(3 downto 0), + S_AXIL_ACLK => processing_system7_0_FCLK_CLK0, + S_AXIL_ARADDR(15 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(15 downto 0), + S_AXIL_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + S_AXIL_ARREADY => ps7_0_axi_periph_M00_AXI_ARREADY, + S_AXIL_ARVALID => ps7_0_axi_periph_M00_AXI_ARVALID, + S_AXIL_AWADDR(15 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(15 downto 0), + S_AXIL_AWREADY => ps7_0_axi_periph_M00_AXI_AWREADY, + S_AXIL_AWVALID => ps7_0_axi_periph_M00_AXI_AWVALID, + S_AXIL_BREADY => ps7_0_axi_periph_M00_AXI_BREADY, + S_AXIL_BRESP(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), + S_AXIL_BVALID => ps7_0_axi_periph_M00_AXI_BVALID, + S_AXIL_RDATA(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), + S_AXIL_RREADY => ps7_0_axi_periph_M00_AXI_RREADY, + S_AXIL_RRESP(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), + S_AXIL_RVALID => ps7_0_axi_periph_M00_AXI_RVALID, + S_AXIL_WDATA(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), + S_AXIL_WREADY => ps7_0_axi_periph_M00_AXI_WREADY, + S_AXIL_WSTRB(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), + S_AXIL_WVALID => ps7_0_axi_periph_M00_AXI_WVALID, + VIDEO_CLK => processing_system7_0_FCLK_CLK3, + VIDEO_INTERRUPT => zynq_base_hdmi_0_VIDEO_INTERRUPT, + VIDEO_RESETN => rst_ps7_0_100M_peripheral_aresetn + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity m00_couplers_imp_XFWZ5U is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end m00_couplers_imp_XFWZ5U; + +architecture STRUCTURE of m00_couplers_imp_XFWZ5U is + signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC; + signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC; + signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC; + signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC; + signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0); + M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0); + M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID; + M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY; + M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID; + S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY; + S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY; + S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0); + S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID; + S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0); + S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0); + S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID; + S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY; + m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready; + m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid; + m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready; + m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid; + m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready; + m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid; + m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready; + m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid; + m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready; + m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity m01_couplers_imp_164MWV7 is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end m01_couplers_imp_164MWV7; + +architecture STRUCTURE of m01_couplers_imp_164MWV7 is + signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC; + signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC; + signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC; + signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC; + signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0); + M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0); + M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID; + M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY; + M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID; + S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY; + S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY; + S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0); + S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID; + S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0); + S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0); + S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID; + S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY; + m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready; + m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid; + m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready; + m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid; + m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready; + m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid; + m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready; + m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid; + m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready; + m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity m02_couplers_imp_YRUE81 is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end m02_couplers_imp_YRUE81; + +architecture STRUCTURE of m02_couplers_imp_YRUE81 is + signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC; + signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC; + signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC; + signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC; + signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0); + M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0); + M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID; + M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY; + M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID; + S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY; + S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY; + S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0); + S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID; + S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0); + S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0); + S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID; + S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY; + m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready; + m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid; + m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready; + m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid; + m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready; + m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid; + m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready; + m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid; + m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready; + m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity s00_couplers_imp_1UA4Y98 is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_rlast : out STD_LOGIC; + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wlast : in STD_LOGIC; + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end s00_couplers_imp_1UA4Y98; + +architecture STRUCTURE of s00_couplers_imp_1UA4Y98 is + component design_3_auto_us_1 is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC + ); + end component design_3_auto_us_1; + signal S_ACLK_1 : STD_LOGIC; + signal S_ARESETN_1 : STD_LOGIC; + signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_us_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_AWVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_BREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_BVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_us_to_s00_couplers_RLAST : STD_LOGIC; + signal auto_us_to_s00_couplers_RREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_RVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_us_to_s00_couplers_WLAST : STD_LOGIC; + signal auto_us_to_s00_couplers_WREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal auto_us_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_AWREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_AWVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_auto_us_BREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_BVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_auto_us_RLAST : STD_LOGIC; + signal s00_couplers_to_auto_us_RREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_RVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_WLAST : STD_LOGIC; + signal s00_couplers_to_auto_us_WREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0); + M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0); + M_AXI_arlen(3 downto 0) <= auto_us_to_s00_couplers_ARLEN(3 downto 0); + M_AXI_arlock(1 downto 0) <= auto_us_to_s00_couplers_ARLOCK(1 downto 0); + M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0); + M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0); + M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0); + M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= auto_us_to_s00_couplers_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= auto_us_to_s00_couplers_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= auto_us_to_s00_couplers_AWCACHE(3 downto 0); + M_AXI_awlen(3 downto 0) <= auto_us_to_s00_couplers_AWLEN(3 downto 0); + M_AXI_awlock(1 downto 0) <= auto_us_to_s00_couplers_AWLOCK(1 downto 0); + M_AXI_awprot(2 downto 0) <= auto_us_to_s00_couplers_AWPROT(2 downto 0); + M_AXI_awqos(3 downto 0) <= auto_us_to_s00_couplers_AWQOS(3 downto 0); + M_AXI_awsize(2 downto 0) <= auto_us_to_s00_couplers_AWSIZE(2 downto 0); + M_AXI_awvalid <= auto_us_to_s00_couplers_AWVALID; + M_AXI_bready <= auto_us_to_s00_couplers_BREADY; + M_AXI_rready <= auto_us_to_s00_couplers_RREADY; + M_AXI_wdata(63 downto 0) <= auto_us_to_s00_couplers_WDATA(63 downto 0); + M_AXI_wlast <= auto_us_to_s00_couplers_WLAST; + M_AXI_wstrb(7 downto 0) <= auto_us_to_s00_couplers_WSTRB(7 downto 0); + M_AXI_wvalid <= auto_us_to_s00_couplers_WVALID; + S_ACLK_1 <= S_ACLK; + S_ARESETN_1 <= S_ARESETN; + S_AXI_arready <= s00_couplers_to_auto_us_ARREADY; + S_AXI_awready <= s00_couplers_to_auto_us_AWREADY; + S_AXI_bid(0) <= s00_couplers_to_auto_us_BID(0); + S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_us_BRESP(1 downto 0); + S_AXI_bvalid <= s00_couplers_to_auto_us_BVALID; + S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0); + S_AXI_rid(0) <= s00_couplers_to_auto_us_RID(0); + S_AXI_rlast <= s00_couplers_to_auto_us_RLAST; + S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0); + S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID; + S_AXI_wready <= s00_couplers_to_auto_us_WREADY; + auto_us_to_s00_couplers_ARREADY <= M_AXI_arready; + auto_us_to_s00_couplers_AWREADY <= M_AXI_awready; + auto_us_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + auto_us_to_s00_couplers_BVALID <= M_AXI_bvalid; + auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); + auto_us_to_s00_couplers_RLAST <= M_AXI_rlast; + auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid; + auto_us_to_s00_couplers_WREADY <= M_AXI_wready; + s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); + s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); + s00_couplers_to_auto_us_ARID(0) <= S_AXI_arid(0); + s00_couplers_to_auto_us_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); + s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); + s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); + s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid; + s00_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + s00_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); + s00_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); + s00_couplers_to_auto_us_AWID(0) <= S_AXI_awid(0); + s00_couplers_to_auto_us_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); + s00_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); + s00_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); + s00_couplers_to_auto_us_AWVALID <= S_AXI_awvalid; + s00_couplers_to_auto_us_BREADY <= S_AXI_bready; + s00_couplers_to_auto_us_RREADY <= S_AXI_rready; + s00_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + s00_couplers_to_auto_us_WLAST <= S_AXI_wlast; + s00_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + s00_couplers_to_auto_us_WVALID <= S_AXI_wvalid; +auto_us: component design_3_auto_us_1 + port map ( + m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0), + m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0), + m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0), + m_axi_arlen(3 downto 0) => auto_us_to_s00_couplers_ARLEN(3 downto 0), + m_axi_arlock(1 downto 0) => auto_us_to_s00_couplers_ARLOCK(1 downto 0), + m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0), + m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0), + m_axi_arready => auto_us_to_s00_couplers_ARREADY, + m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0), + m_axi_arvalid => auto_us_to_s00_couplers_ARVALID, + m_axi_awaddr(31 downto 0) => auto_us_to_s00_couplers_AWADDR(31 downto 0), + m_axi_awburst(1 downto 0) => auto_us_to_s00_couplers_AWBURST(1 downto 0), + m_axi_awcache(3 downto 0) => auto_us_to_s00_couplers_AWCACHE(3 downto 0), + m_axi_awlen(3 downto 0) => auto_us_to_s00_couplers_AWLEN(3 downto 0), + m_axi_awlock(1 downto 0) => auto_us_to_s00_couplers_AWLOCK(1 downto 0), + m_axi_awprot(2 downto 0) => auto_us_to_s00_couplers_AWPROT(2 downto 0), + m_axi_awqos(3 downto 0) => auto_us_to_s00_couplers_AWQOS(3 downto 0), + m_axi_awready => auto_us_to_s00_couplers_AWREADY, + m_axi_awsize(2 downto 0) => auto_us_to_s00_couplers_AWSIZE(2 downto 0), + m_axi_awvalid => auto_us_to_s00_couplers_AWVALID, + m_axi_bready => auto_us_to_s00_couplers_BREADY, + m_axi_bresp(1 downto 0) => auto_us_to_s00_couplers_BRESP(1 downto 0), + m_axi_bvalid => auto_us_to_s00_couplers_BVALID, + m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0), + m_axi_rlast => auto_us_to_s00_couplers_RLAST, + m_axi_rready => auto_us_to_s00_couplers_RREADY, + m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0), + m_axi_rvalid => auto_us_to_s00_couplers_RVALID, + m_axi_wdata(63 downto 0) => auto_us_to_s00_couplers_WDATA(63 downto 0), + m_axi_wlast => auto_us_to_s00_couplers_WLAST, + m_axi_wready => auto_us_to_s00_couplers_WREADY, + m_axi_wstrb(7 downto 0) => auto_us_to_s00_couplers_WSTRB(7 downto 0), + m_axi_wvalid => auto_us_to_s00_couplers_WVALID, + s_axi_aclk => S_ACLK_1, + s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0), + s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0), + s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0), + s_axi_aresetn => S_ARESETN_1, + s_axi_arid(0) => s00_couplers_to_auto_us_ARID(0), + s_axi_arlen(3 downto 0) => s00_couplers_to_auto_us_ARLEN(3 downto 0), + s_axi_arlock(1 downto 0) => B"00", + s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0), + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => s00_couplers_to_auto_us_ARREADY, + s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0), + s_axi_arvalid => s00_couplers_to_auto_us_ARVALID, + s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_us_AWADDR(31 downto 0), + s_axi_awburst(1 downto 0) => s00_couplers_to_auto_us_AWBURST(1 downto 0), + s_axi_awcache(3 downto 0) => s00_couplers_to_auto_us_AWCACHE(3 downto 0), + s_axi_awid(0) => s00_couplers_to_auto_us_AWID(0), + s_axi_awlen(3 downto 0) => s00_couplers_to_auto_us_AWLEN(3 downto 0), + s_axi_awlock(1 downto 0) => B"00", + s_axi_awprot(2 downto 0) => s00_couplers_to_auto_us_AWPROT(2 downto 0), + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => s00_couplers_to_auto_us_AWREADY, + s_axi_awsize(2 downto 0) => s00_couplers_to_auto_us_AWSIZE(2 downto 0), + s_axi_awvalid => s00_couplers_to_auto_us_AWVALID, + s_axi_bid(0) => s00_couplers_to_auto_us_BID(0), + s_axi_bready => s00_couplers_to_auto_us_BREADY, + s_axi_bresp(1 downto 0) => s00_couplers_to_auto_us_BRESP(1 downto 0), + s_axi_bvalid => s00_couplers_to_auto_us_BVALID, + s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0), + s_axi_rid(0) => s00_couplers_to_auto_us_RID(0), + s_axi_rlast => s00_couplers_to_auto_us_RLAST, + s_axi_rready => s00_couplers_to_auto_us_RREADY, + s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0), + s_axi_rvalid => s00_couplers_to_auto_us_RVALID, + s_axi_wdata(31 downto 0) => s00_couplers_to_auto_us_WDATA(31 downto 0), + s_axi_wlast => s00_couplers_to_auto_us_WLAST, + s_axi_wready => s00_couplers_to_auto_us_WREADY, + s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_us_WSTRB(3 downto 0), + s_axi_wvalid => s00_couplers_to_auto_us_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity s00_couplers_imp_1VXU3HN is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_rlast : out STD_LOGIC; + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wlast : in STD_LOGIC; + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end s00_couplers_imp_1VXU3HN; + +architecture STRUCTURE of s00_couplers_imp_1VXU3HN is + component design_3_auto_us_0 is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC + ); + end component design_3_auto_us_0; + signal S_ACLK_1 : STD_LOGIC; + signal S_ARESETN_1 : STD_LOGIC; + signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_us_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_AWVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_BREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_BVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_us_to_s00_couplers_RLAST : STD_LOGIC; + signal auto_us_to_s00_couplers_RREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_RVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_us_to_s00_couplers_WLAST : STD_LOGIC; + signal auto_us_to_s00_couplers_WREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal auto_us_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_AWREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_AWVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_BREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_BVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_RLAST : STD_LOGIC; + signal s00_couplers_to_auto_us_RREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_RVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_WLAST : STD_LOGIC; + signal s00_couplers_to_auto_us_WREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_WVALID : STD_LOGIC; + signal NLW_auto_us_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); +begin + M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0); + M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0); + M_AXI_arlen(3 downto 0) <= auto_us_to_s00_couplers_ARLEN(3 downto 0); + M_AXI_arlock(1 downto 0) <= auto_us_to_s00_couplers_ARLOCK(1 downto 0); + M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0); + M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0); + M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0); + M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= auto_us_to_s00_couplers_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= auto_us_to_s00_couplers_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= auto_us_to_s00_couplers_AWCACHE(3 downto 0); + M_AXI_awlen(3 downto 0) <= auto_us_to_s00_couplers_AWLEN(3 downto 0); + M_AXI_awlock(1 downto 0) <= auto_us_to_s00_couplers_AWLOCK(1 downto 0); + M_AXI_awprot(2 downto 0) <= auto_us_to_s00_couplers_AWPROT(2 downto 0); + M_AXI_awqos(3 downto 0) <= auto_us_to_s00_couplers_AWQOS(3 downto 0); + M_AXI_awsize(2 downto 0) <= auto_us_to_s00_couplers_AWSIZE(2 downto 0); + M_AXI_awvalid <= auto_us_to_s00_couplers_AWVALID; + M_AXI_bready <= auto_us_to_s00_couplers_BREADY; + M_AXI_rready <= auto_us_to_s00_couplers_RREADY; + M_AXI_wdata(63 downto 0) <= auto_us_to_s00_couplers_WDATA(63 downto 0); + M_AXI_wlast <= auto_us_to_s00_couplers_WLAST; + M_AXI_wstrb(7 downto 0) <= auto_us_to_s00_couplers_WSTRB(7 downto 0); + M_AXI_wvalid <= auto_us_to_s00_couplers_WVALID; + S_ACLK_1 <= S_ACLK; + S_ARESETN_1 <= S_ARESETN; + S_AXI_arready <= s00_couplers_to_auto_us_ARREADY; + S_AXI_awready <= s00_couplers_to_auto_us_AWREADY; + S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_us_BRESP(1 downto 0); + S_AXI_bvalid <= s00_couplers_to_auto_us_BVALID; + S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0); + S_AXI_rid(3 downto 0) <= s00_couplers_to_auto_us_RID(3 downto 0); + S_AXI_rlast <= s00_couplers_to_auto_us_RLAST; + S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0); + S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID; + S_AXI_wready <= s00_couplers_to_auto_us_WREADY; + auto_us_to_s00_couplers_ARREADY <= M_AXI_arready; + auto_us_to_s00_couplers_AWREADY <= M_AXI_awready; + auto_us_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + auto_us_to_s00_couplers_BVALID <= M_AXI_bvalid; + auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); + auto_us_to_s00_couplers_RLAST <= M_AXI_rlast; + auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid; + auto_us_to_s00_couplers_WREADY <= M_AXI_wready; + s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); + s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); + s00_couplers_to_auto_us_ARID(3 downto 0) <= S_AXI_arid(3 downto 0); + s00_couplers_to_auto_us_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); + s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); + s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); + s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid; + s00_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + s00_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); + s00_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); + s00_couplers_to_auto_us_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); + s00_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); + s00_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); + s00_couplers_to_auto_us_AWVALID <= S_AXI_awvalid; + s00_couplers_to_auto_us_BREADY <= S_AXI_bready; + s00_couplers_to_auto_us_RREADY <= S_AXI_rready; + s00_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + s00_couplers_to_auto_us_WLAST <= S_AXI_wlast; + s00_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + s00_couplers_to_auto_us_WVALID <= S_AXI_wvalid; +auto_us: component design_3_auto_us_0 + port map ( + m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0), + m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0), + m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0), + m_axi_arlen(3 downto 0) => auto_us_to_s00_couplers_ARLEN(3 downto 0), + m_axi_arlock(1 downto 0) => auto_us_to_s00_couplers_ARLOCK(1 downto 0), + m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0), + m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0), + m_axi_arready => auto_us_to_s00_couplers_ARREADY, + m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0), + m_axi_arvalid => auto_us_to_s00_couplers_ARVALID, + m_axi_awaddr(31 downto 0) => auto_us_to_s00_couplers_AWADDR(31 downto 0), + m_axi_awburst(1 downto 0) => auto_us_to_s00_couplers_AWBURST(1 downto 0), + m_axi_awcache(3 downto 0) => auto_us_to_s00_couplers_AWCACHE(3 downto 0), + m_axi_awlen(3 downto 0) => auto_us_to_s00_couplers_AWLEN(3 downto 0), + m_axi_awlock(1 downto 0) => auto_us_to_s00_couplers_AWLOCK(1 downto 0), + m_axi_awprot(2 downto 0) => auto_us_to_s00_couplers_AWPROT(2 downto 0), + m_axi_awqos(3 downto 0) => auto_us_to_s00_couplers_AWQOS(3 downto 0), + m_axi_awready => auto_us_to_s00_couplers_AWREADY, + m_axi_awsize(2 downto 0) => auto_us_to_s00_couplers_AWSIZE(2 downto 0), + m_axi_awvalid => auto_us_to_s00_couplers_AWVALID, + m_axi_bready => auto_us_to_s00_couplers_BREADY, + m_axi_bresp(1 downto 0) => auto_us_to_s00_couplers_BRESP(1 downto 0), + m_axi_bvalid => auto_us_to_s00_couplers_BVALID, + m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0), + m_axi_rlast => auto_us_to_s00_couplers_RLAST, + m_axi_rready => auto_us_to_s00_couplers_RREADY, + m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0), + m_axi_rvalid => auto_us_to_s00_couplers_RVALID, + m_axi_wdata(63 downto 0) => auto_us_to_s00_couplers_WDATA(63 downto 0), + m_axi_wlast => auto_us_to_s00_couplers_WLAST, + m_axi_wready => auto_us_to_s00_couplers_WREADY, + m_axi_wstrb(7 downto 0) => auto_us_to_s00_couplers_WSTRB(7 downto 0), + m_axi_wvalid => auto_us_to_s00_couplers_WVALID, + s_axi_aclk => S_ACLK_1, + s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0), + s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0), + s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0), + s_axi_aresetn => S_ARESETN_1, + s_axi_arid(3 downto 0) => s00_couplers_to_auto_us_ARID(3 downto 0), + s_axi_arlen(3 downto 0) => s00_couplers_to_auto_us_ARLEN(3 downto 0), + s_axi_arlock(1 downto 0) => B"00", + s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0), + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => s00_couplers_to_auto_us_ARREADY, + s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0), + s_axi_arvalid => s00_couplers_to_auto_us_ARVALID, + s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_us_AWADDR(31 downto 0), + s_axi_awburst(1 downto 0) => s00_couplers_to_auto_us_AWBURST(1 downto 0), + s_axi_awcache(3 downto 0) => s00_couplers_to_auto_us_AWCACHE(3 downto 0), + s_axi_awid(3 downto 0) => B"0000", + s_axi_awlen(3 downto 0) => s00_couplers_to_auto_us_AWLEN(3 downto 0), + s_axi_awlock(1 downto 0) => B"00", + s_axi_awprot(2 downto 0) => s00_couplers_to_auto_us_AWPROT(2 downto 0), + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => s00_couplers_to_auto_us_AWREADY, + s_axi_awsize(2 downto 0) => s00_couplers_to_auto_us_AWSIZE(2 downto 0), + s_axi_awvalid => s00_couplers_to_auto_us_AWVALID, + s_axi_bid(3 downto 0) => NLW_auto_us_s_axi_bid_UNCONNECTED(3 downto 0), + s_axi_bready => s00_couplers_to_auto_us_BREADY, + s_axi_bresp(1 downto 0) => s00_couplers_to_auto_us_BRESP(1 downto 0), + s_axi_bvalid => s00_couplers_to_auto_us_BVALID, + s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0), + s_axi_rid(3 downto 0) => s00_couplers_to_auto_us_RID(3 downto 0), + s_axi_rlast => s00_couplers_to_auto_us_RLAST, + s_axi_rready => s00_couplers_to_auto_us_RREADY, + s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0), + s_axi_rvalid => s00_couplers_to_auto_us_RVALID, + s_axi_wdata(31 downto 0) => s00_couplers_to_auto_us_WDATA(31 downto 0), + s_axi_wlast => s00_couplers_to_auto_us_WLAST, + s_axi_wready => s00_couplers_to_auto_us_WREADY, + s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_us_WSTRB(3 downto 0), + s_axi_wvalid => s00_couplers_to_auto_us_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity s00_couplers_imp_ZZSSAO is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_rlast : out STD_LOGIC; + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_wlast : in STD_LOGIC; + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end s00_couplers_imp_ZZSSAO; + +architecture STRUCTURE of s00_couplers_imp_ZZSSAO is + component design_3_auto_pc_0 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC + ); + end component design_3_auto_pc_0; + signal S_ACLK_1 : STD_LOGIC; + signal S_ARESETN_1 : STD_LOGIC; + signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC; + signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC; + signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC; + signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC; + signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC; + signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC; + signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0); + M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0); + M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0); + M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0); + M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID; + M_AXI_bready <= auto_pc_to_s00_couplers_BREADY; + M_AXI_rready <= auto_pc_to_s00_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID; + S_ACLK_1 <= S_ACLK; + S_ARESETN_1 <= S_ARESETN; + S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY; + S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY; + S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0); + S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0); + S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID; + S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0); + S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0); + S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST; + S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0); + S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID; + S_AXI_wready <= s00_couplers_to_auto_pc_WREADY; + auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready; + auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready; + auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid; + auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid; + auto_pc_to_s00_couplers_WREADY <= M_AXI_wready; + s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); + s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); + s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); + s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); + s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0); + s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); + s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); + s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); + s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; + s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); + s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); + s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); + s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); + s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0); + s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); + s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); + s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); + s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; + s00_couplers_to_auto_pc_BREADY <= S_AXI_bready; + s00_couplers_to_auto_pc_RREADY <= S_AXI_rready; + s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0); + s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; + s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; +auto_pc: component design_3_auto_pc_0 + port map ( + aclk => S_ACLK_1, + aresetn => S_ARESETN_1, + m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0), + m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0), + m_axi_arready => auto_pc_to_s00_couplers_ARREADY, + m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID, + m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0), + m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0), + m_axi_awready => auto_pc_to_s00_couplers_AWREADY, + m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID, + m_axi_bready => auto_pc_to_s00_couplers_BREADY, + m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0), + m_axi_bvalid => auto_pc_to_s00_couplers_BVALID, + m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0), + m_axi_rready => auto_pc_to_s00_couplers_RREADY, + m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0), + m_axi_rvalid => auto_pc_to_s00_couplers_RVALID, + m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0), + m_axi_wready => auto_pc_to_s00_couplers_WREADY, + m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0), + m_axi_wvalid => auto_pc_to_s00_couplers_WVALID, + s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0), + s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0), + s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0), + s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0), + s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0), + s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0), + s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0), + s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0), + s_axi_arready => s00_couplers_to_auto_pc_ARREADY, + s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0), + s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID, + s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0), + s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0), + s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0), + s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0), + s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0), + s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0), + s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0), + s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0), + s_axi_awready => s00_couplers_to_auto_pc_AWREADY, + s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0), + s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID, + s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0), + s_axi_bready => s00_couplers_to_auto_pc_BREADY, + s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0), + s_axi_bvalid => s00_couplers_to_auto_pc_BVALID, + s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0), + s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0), + s_axi_rlast => s00_couplers_to_auto_pc_RLAST, + s_axi_rready => s00_couplers_to_auto_pc_RREADY, + s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0), + s_axi_rvalid => s00_couplers_to_auto_pc_RVALID, + s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0), + s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0), + s_axi_wlast => s00_couplers_to_auto_pc_WLAST, + s_axi_wready => s00_couplers_to_auto_pc_WREADY, + s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0), + s_axi_wvalid => s00_couplers_to_auto_pc_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_3_axi_interconnect_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M00_ACLK : in STD_LOGIC; + M00_ARESETN : in STD_LOGIC; + M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arready : in STD_LOGIC; + M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_arvalid : out STD_LOGIC; + M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awready : in STD_LOGIC; + M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awvalid : out STD_LOGIC; + M00_AXI_bready : out STD_LOGIC; + M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_bvalid : in STD_LOGIC; + M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_rlast : in STD_LOGIC; + M00_AXI_rready : out STD_LOGIC; + M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_rvalid : in STD_LOGIC; + M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_wlast : out STD_LOGIC; + M00_AXI_wready : in STD_LOGIC; + M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M00_AXI_wvalid : out STD_LOGIC; + S00_ACLK : in STD_LOGIC; + S00_ARESETN : in STD_LOGIC; + S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arready : out STD_LOGIC; + S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arvalid : in STD_LOGIC; + S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awready : out STD_LOGIC; + S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awvalid : in STD_LOGIC; + S00_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI_bready : in STD_LOGIC; + S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_bvalid : out STD_LOGIC; + S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI_rlast : out STD_LOGIC; + S00_AXI_rready : in STD_LOGIC; + S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_rvalid : out STD_LOGIC; + S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_wlast : in STD_LOGIC; + S00_AXI_wready : out STD_LOGIC; + S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_wvalid : in STD_LOGIC + ); +end design_3_axi_interconnect_0_0; + +architecture STRUCTURE of design_3_axi_interconnect_0_0 is + signal S00_ACLK_1 : STD_LOGIC; + signal S00_ARESETN_1 : STD_LOGIC; + signal axi_interconnect_0_ACLK_net : STD_LOGIC; + signal axi_interconnect_0_ARESETN_net : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_RLAST : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_WLAST : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC; +begin + M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0); + M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0); + M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0); + M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARLEN(3 downto 0); + M00_AXI_arlock(1 downto 0) <= s00_couplers_to_axi_interconnect_0_ARLOCK(1 downto 0); + M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0); + M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0); + M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0); + M00_AXI_arvalid <= s00_couplers_to_axi_interconnect_0_ARVALID; + M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0); + M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0); + M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0); + M00_AXI_awlen(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWLEN(3 downto 0); + M00_AXI_awlock(1 downto 0) <= s00_couplers_to_axi_interconnect_0_AWLOCK(1 downto 0); + M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0); + M00_AXI_awqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0); + M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0); + M00_AXI_awvalid <= s00_couplers_to_axi_interconnect_0_AWVALID; + M00_AXI_bready <= s00_couplers_to_axi_interconnect_0_BREADY; + M00_AXI_rready <= s00_couplers_to_axi_interconnect_0_RREADY; + M00_AXI_wdata(63 downto 0) <= s00_couplers_to_axi_interconnect_0_WDATA(63 downto 0); + M00_AXI_wlast <= s00_couplers_to_axi_interconnect_0_WLAST; + M00_AXI_wstrb(7 downto 0) <= s00_couplers_to_axi_interconnect_0_WSTRB(7 downto 0); + M00_AXI_wvalid <= s00_couplers_to_axi_interconnect_0_WVALID; + S00_ACLK_1 <= S00_ACLK; + S00_ARESETN_1 <= S00_ARESETN; + S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY; + S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY; + S00_AXI_bid(0) <= axi_interconnect_0_to_s00_couplers_BID(0); + S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0); + S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID; + S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0); + S00_AXI_rid(0) <= axi_interconnect_0_to_s00_couplers_RID(0); + S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST; + S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0); + S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID; + S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY; + axi_interconnect_0_ACLK_net <= M00_ACLK; + axi_interconnect_0_ARESETN_net <= M00_ARESETN; + axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); + axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); + axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); + axi_interconnect_0_to_s00_couplers_ARID(0) <= S00_AXI_arid(0); + axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); + axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); + axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); + axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid; + axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); + axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); + axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); + axi_interconnect_0_to_s00_couplers_AWID(0) <= S00_AXI_awid(0); + axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); + axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); + axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); + axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid; + axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready; + axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready; + axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); + axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast; + axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); + axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid; + s00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready; + s00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready; + s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); + s00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid; + s00_couplers_to_axi_interconnect_0_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0); + s00_couplers_to_axi_interconnect_0_RLAST <= M00_AXI_rlast; + s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); + s00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid; + s00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready; +s00_couplers: entity work.s00_couplers_imp_1UA4Y98 + port map ( + M_ACLK => axi_interconnect_0_ACLK_net, + M_ARESETN => axi_interconnect_0_ARESETN_net, + M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0), + M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARLEN(3 downto 0), + M_AXI_arlock(1 downto 0) => s00_couplers_to_axi_interconnect_0_ARLOCK(1 downto 0), + M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0), + M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0), + M_AXI_arready => s00_couplers_to_axi_interconnect_0_ARREADY, + M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0), + M_AXI_arvalid => s00_couplers_to_axi_interconnect_0_ARVALID, + M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0), + M_AXI_awlen(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWLEN(3 downto 0), + M_AXI_awlock(1 downto 0) => s00_couplers_to_axi_interconnect_0_AWLOCK(1 downto 0), + M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0), + M_AXI_awqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0), + M_AXI_awready => s00_couplers_to_axi_interconnect_0_AWREADY, + M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0), + M_AXI_awvalid => s00_couplers_to_axi_interconnect_0_AWVALID, + M_AXI_bready => s00_couplers_to_axi_interconnect_0_BREADY, + M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0), + M_AXI_bvalid => s00_couplers_to_axi_interconnect_0_BVALID, + M_AXI_rdata(63 downto 0) => s00_couplers_to_axi_interconnect_0_RDATA(63 downto 0), + M_AXI_rlast => s00_couplers_to_axi_interconnect_0_RLAST, + M_AXI_rready => s00_couplers_to_axi_interconnect_0_RREADY, + M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0), + M_AXI_rvalid => s00_couplers_to_axi_interconnect_0_RVALID, + M_AXI_wdata(63 downto 0) => s00_couplers_to_axi_interconnect_0_WDATA(63 downto 0), + M_AXI_wlast => s00_couplers_to_axi_interconnect_0_WLAST, + M_AXI_wready => s00_couplers_to_axi_interconnect_0_WREADY, + M_AXI_wstrb(7 downto 0) => s00_couplers_to_axi_interconnect_0_WSTRB(7 downto 0), + M_AXI_wvalid => s00_couplers_to_axi_interconnect_0_WVALID, + S_ACLK => S00_ACLK_1, + S_ARESETN => S00_ARESETN_1, + S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0), + S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0), + S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0), + S_AXI_arid(0) => axi_interconnect_0_to_s00_couplers_ARID(0), + S_AXI_arlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0), + S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0), + S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY, + S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0), + S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID, + S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0), + S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0), + S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0), + S_AXI_awid(0) => axi_interconnect_0_to_s00_couplers_AWID(0), + S_AXI_awlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0), + S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0), + S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY, + S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0), + S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID, + S_AXI_bid(0) => axi_interconnect_0_to_s00_couplers_BID(0), + S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY, + S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0), + S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID, + S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0), + S_AXI_rid(0) => axi_interconnect_0_to_s00_couplers_RID(0), + S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST, + S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY, + S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0), + S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID, + S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0), + S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST, + S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0), + S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_3_axi_mem_intercon_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M00_ACLK : in STD_LOGIC; + M00_ARESETN : in STD_LOGIC; + M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arready : in STD_LOGIC; + M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_arvalid : out STD_LOGIC; + M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awready : in STD_LOGIC; + M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awvalid : out STD_LOGIC; + M00_AXI_bready : out STD_LOGIC; + M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_bvalid : in STD_LOGIC; + M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_rlast : in STD_LOGIC; + M00_AXI_rready : out STD_LOGIC; + M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_rvalid : in STD_LOGIC; + M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_wlast : out STD_LOGIC; + M00_AXI_wready : in STD_LOGIC; + M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M00_AXI_wvalid : out STD_LOGIC; + S00_ACLK : in STD_LOGIC; + S00_ARESETN : in STD_LOGIC; + S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arready : out STD_LOGIC; + S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arvalid : in STD_LOGIC; + S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awready : out STD_LOGIC; + S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awvalid : in STD_LOGIC; + S00_AXI_bready : in STD_LOGIC; + S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_bvalid : out STD_LOGIC; + S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_rlast : out STD_LOGIC; + S00_AXI_rready : in STD_LOGIC; + S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_rvalid : out STD_LOGIC; + S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_wlast : in STD_LOGIC; + S00_AXI_wready : out STD_LOGIC; + S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_wvalid : in STD_LOGIC + ); +end design_3_axi_mem_intercon_0; + +architecture STRUCTURE of design_3_axi_mem_intercon_0 is + signal S00_ACLK_1 : STD_LOGIC; + signal S00_ARESETN_1 : STD_LOGIC; + signal axi_mem_intercon_ACLK_net : STD_LOGIC; + signal axi_mem_intercon_ARESETN_net : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC; +begin + M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0); + M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0); + M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0); + M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0); + M00_AXI_arlock(1 downto 0) <= s00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0); + M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0); + M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0); + M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0); + M00_AXI_arvalid <= s00_couplers_to_axi_mem_intercon_ARVALID; + M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0); + M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0); + M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0); + M00_AXI_awlen(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0); + M00_AXI_awlock(1 downto 0) <= s00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0); + M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0); + M00_AXI_awqos(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0); + M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0); + M00_AXI_awvalid <= s00_couplers_to_axi_mem_intercon_AWVALID; + M00_AXI_bready <= s00_couplers_to_axi_mem_intercon_BREADY; + M00_AXI_rready <= s00_couplers_to_axi_mem_intercon_RREADY; + M00_AXI_wdata(63 downto 0) <= s00_couplers_to_axi_mem_intercon_WDATA(63 downto 0); + M00_AXI_wlast <= s00_couplers_to_axi_mem_intercon_WLAST; + M00_AXI_wstrb(7 downto 0) <= s00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0); + M00_AXI_wvalid <= s00_couplers_to_axi_mem_intercon_WVALID; + S00_ACLK_1 <= S00_ACLK; + S00_ARESETN_1 <= S00_ARESETN; + S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY; + S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY; + S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0); + S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID; + S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0); + S00_AXI_rid(3 downto 0) <= axi_mem_intercon_to_s00_couplers_RID(3 downto 0); + S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST; + S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0); + S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID; + S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY; + axi_mem_intercon_ACLK_net <= M00_ACLK; + axi_mem_intercon_ARESETN_net <= M00_ARESETN; + axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); + axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); + axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); + axi_mem_intercon_to_s00_couplers_ARID(3 downto 0) <= S00_AXI_arid(3 downto 0); + axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); + axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); + axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); + axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid; + axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); + axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); + axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); + axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); + axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); + axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); + axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid; + axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready; + axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready; + axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); + axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast; + axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); + axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid; + s00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready; + s00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready; + s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); + s00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid; + s00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0); + s00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast; + s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); + s00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid; + s00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready; +s00_couplers: entity work.s00_couplers_imp_1VXU3HN + port map ( + M_ACLK => axi_mem_intercon_ACLK_net, + M_ARESETN => axi_mem_intercon_ARESETN_net, + M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0), + M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0), + M_AXI_arlock(1 downto 0) => s00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0), + M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0), + M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0), + M_AXI_arready => s00_couplers_to_axi_mem_intercon_ARREADY, + M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0), + M_AXI_arvalid => s00_couplers_to_axi_mem_intercon_ARVALID, + M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0), + M_AXI_awlen(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0), + M_AXI_awlock(1 downto 0) => s00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0), + M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0), + M_AXI_awqos(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0), + M_AXI_awready => s00_couplers_to_axi_mem_intercon_AWREADY, + M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0), + M_AXI_awvalid => s00_couplers_to_axi_mem_intercon_AWVALID, + M_AXI_bready => s00_couplers_to_axi_mem_intercon_BREADY, + M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0), + M_AXI_bvalid => s00_couplers_to_axi_mem_intercon_BVALID, + M_AXI_rdata(63 downto 0) => s00_couplers_to_axi_mem_intercon_RDATA(63 downto 0), + M_AXI_rlast => s00_couplers_to_axi_mem_intercon_RLAST, + M_AXI_rready => s00_couplers_to_axi_mem_intercon_RREADY, + M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0), + M_AXI_rvalid => s00_couplers_to_axi_mem_intercon_RVALID, + M_AXI_wdata(63 downto 0) => s00_couplers_to_axi_mem_intercon_WDATA(63 downto 0), + M_AXI_wlast => s00_couplers_to_axi_mem_intercon_WLAST, + M_AXI_wready => s00_couplers_to_axi_mem_intercon_WREADY, + M_AXI_wstrb(7 downto 0) => s00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0), + M_AXI_wvalid => s00_couplers_to_axi_mem_intercon_WVALID, + S_ACLK => S00_ACLK_1, + S_ARESETN => S00_ARESETN_1, + S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0), + S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0), + S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0), + S_AXI_arid(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARID(3 downto 0), + S_AXI_arlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0), + S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0), + S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY, + S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0), + S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID, + S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0), + S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0), + S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0), + S_AXI_awlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0), + S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0), + S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY, + S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0), + S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID, + S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY, + S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0), + S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID, + S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0), + S_AXI_rid(3 downto 0) => axi_mem_intercon_to_s00_couplers_RID(3 downto 0), + S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST, + S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY, + S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0), + S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID, + S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0), + S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST, + S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0), + S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_3_ps7_0_axi_periph_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M00_ACLK : in STD_LOGIC; + M00_ARESETN : in STD_LOGIC; + M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_arready : in STD_LOGIC; + M00_AXI_arvalid : out STD_LOGIC; + M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_awready : in STD_LOGIC; + M00_AXI_awvalid : out STD_LOGIC; + M00_AXI_bready : out STD_LOGIC; + M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_bvalid : in STD_LOGIC; + M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_rready : out STD_LOGIC; + M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_rvalid : in STD_LOGIC; + M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_wready : in STD_LOGIC; + M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_wvalid : out STD_LOGIC; + M01_ACLK : in STD_LOGIC; + M01_ARESETN : in STD_LOGIC; + M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_arready : in STD_LOGIC; + M01_AXI_arvalid : out STD_LOGIC; + M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_awready : in STD_LOGIC; + M01_AXI_awvalid : out STD_LOGIC; + M01_AXI_bready : out STD_LOGIC; + M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M01_AXI_bvalid : in STD_LOGIC; + M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_rready : out STD_LOGIC; + M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M01_AXI_rvalid : in STD_LOGIC; + M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_wready : in STD_LOGIC; + M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M01_AXI_wvalid : out STD_LOGIC; + M02_ACLK : in STD_LOGIC; + M02_ARESETN : in STD_LOGIC; + M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_arready : in STD_LOGIC; + M02_AXI_arvalid : out STD_LOGIC; + M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_awready : in STD_LOGIC; + M02_AXI_awvalid : out STD_LOGIC; + M02_AXI_bready : out STD_LOGIC; + M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M02_AXI_bvalid : in STD_LOGIC; + M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_rready : out STD_LOGIC; + M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M02_AXI_rvalid : in STD_LOGIC; + M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_wready : in STD_LOGIC; + M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M02_AXI_wvalid : out STD_LOGIC; + S00_ACLK : in STD_LOGIC; + S00_ARESETN : in STD_LOGIC; + S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arready : out STD_LOGIC; + S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arvalid : in STD_LOGIC; + S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awready : out STD_LOGIC; + S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awvalid : in STD_LOGIC; + S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_bready : in STD_LOGIC; + S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_bvalid : out STD_LOGIC; + S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_rlast : out STD_LOGIC; + S00_AXI_rready : in STD_LOGIC; + S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_rvalid : out STD_LOGIC; + S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_wlast : in STD_LOGIC; + S00_AXI_wready : out STD_LOGIC; + S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_wvalid : in STD_LOGIC + ); +end design_3_ps7_0_axi_periph_0; + +architecture STRUCTURE of design_3_ps7_0_axi_periph_0 is + component design_3_xbar_0 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + end component design_3_xbar_0; + signal m00_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC; + signal ps7_0_axi_periph_ACLK_net : STD_LOGIC; + signal ps7_0_axi_periph_ARESETN_net : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_ARVALID : STD_LOGIC; + signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_AWVALID : STD_LOGIC; + signal s00_couplers_to_xbar_BREADY : STD_LOGIC; + signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_xbar_RREADY : STD_LOGIC; + signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_xbar_WVALID : STD_LOGIC; + signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_ARREADY : STD_LOGIC; + signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_AWREADY : STD_LOGIC; + signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m00_couplers_BVALID : STD_LOGIC; + signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m00_couplers_RVALID : STD_LOGIC; + signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_WREADY : STD_LOGIC; + signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal xbar_to_m01_couplers_ARREADY : STD_LOGIC; + signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal xbar_to_m01_couplers_AWREADY : STD_LOGIC; + signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m01_couplers_BVALID : STD_LOGIC; + signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m01_couplers_RVALID : STD_LOGIC; + signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal xbar_to_m01_couplers_WREADY : STD_LOGIC; + signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 ); + signal xbar_to_m02_couplers_ARREADY : STD_LOGIC; + signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 ); + signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 ); + signal xbar_to_m02_couplers_AWREADY : STD_LOGIC; + signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 ); + signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 ); + signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m02_couplers_BVALID : STD_LOGIC; + signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 ); + signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m02_couplers_RVALID : STD_LOGIC; + signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 ); + signal xbar_to_m02_couplers_WREADY : STD_LOGIC; + signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 ); + signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 ); + signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); +begin + M00_AXI_araddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0); + M00_AXI_arvalid <= m00_couplers_to_ps7_0_axi_periph_ARVALID; + M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0); + M00_AXI_awvalid <= m00_couplers_to_ps7_0_axi_periph_AWVALID; + M00_AXI_bready <= m00_couplers_to_ps7_0_axi_periph_BREADY; + M00_AXI_rready <= m00_couplers_to_ps7_0_axi_periph_RREADY; + M00_AXI_wdata(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0); + M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0); + M00_AXI_wvalid <= m00_couplers_to_ps7_0_axi_periph_WVALID; + M01_AXI_araddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0); + M01_AXI_arvalid <= m01_couplers_to_ps7_0_axi_periph_ARVALID; + M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0); + M01_AXI_awvalid <= m01_couplers_to_ps7_0_axi_periph_AWVALID; + M01_AXI_bready <= m01_couplers_to_ps7_0_axi_periph_BREADY; + M01_AXI_rready <= m01_couplers_to_ps7_0_axi_periph_RREADY; + M01_AXI_wdata(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0); + M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0); + M01_AXI_wvalid <= m01_couplers_to_ps7_0_axi_periph_WVALID; + M02_AXI_araddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0); + M02_AXI_arvalid <= m02_couplers_to_ps7_0_axi_periph_ARVALID; + M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0); + M02_AXI_awvalid <= m02_couplers_to_ps7_0_axi_periph_AWVALID; + M02_AXI_bready <= m02_couplers_to_ps7_0_axi_periph_BREADY; + M02_AXI_rready <= m02_couplers_to_ps7_0_axi_periph_RREADY; + M02_AXI_wdata(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0); + M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0); + M02_AXI_wvalid <= m02_couplers_to_ps7_0_axi_periph_WVALID; + S00_AXI_arready <= ps7_0_axi_periph_to_s00_couplers_ARREADY; + S00_AXI_awready <= ps7_0_axi_periph_to_s00_couplers_AWREADY; + S00_AXI_bid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0); + S00_AXI_bresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0); + S00_AXI_bvalid <= ps7_0_axi_periph_to_s00_couplers_BVALID; + S00_AXI_rdata(31 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0); + S00_AXI_rid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0); + S00_AXI_rlast <= ps7_0_axi_periph_to_s00_couplers_RLAST; + S00_AXI_rresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0); + S00_AXI_rvalid <= ps7_0_axi_periph_to_s00_couplers_RVALID; + S00_AXI_wready <= ps7_0_axi_periph_to_s00_couplers_WREADY; + m00_couplers_to_ps7_0_axi_periph_ARREADY <= M00_AXI_arready; + m00_couplers_to_ps7_0_axi_periph_AWREADY <= M00_AXI_awready; + m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); + m00_couplers_to_ps7_0_axi_periph_BVALID <= M00_AXI_bvalid; + m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0); + m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); + m00_couplers_to_ps7_0_axi_periph_RVALID <= M00_AXI_rvalid; + m00_couplers_to_ps7_0_axi_periph_WREADY <= M00_AXI_wready; + m01_couplers_to_ps7_0_axi_periph_ARREADY <= M01_AXI_arready; + m01_couplers_to_ps7_0_axi_periph_AWREADY <= M01_AXI_awready; + m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0); + m01_couplers_to_ps7_0_axi_periph_BVALID <= M01_AXI_bvalid; + m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0); + m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0); + m01_couplers_to_ps7_0_axi_periph_RVALID <= M01_AXI_rvalid; + m01_couplers_to_ps7_0_axi_periph_WREADY <= M01_AXI_wready; + m02_couplers_to_ps7_0_axi_periph_ARREADY <= M02_AXI_arready; + m02_couplers_to_ps7_0_axi_periph_AWREADY <= M02_AXI_awready; + m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0); + m02_couplers_to_ps7_0_axi_periph_BVALID <= M02_AXI_bvalid; + m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0); + m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0); + m02_couplers_to_ps7_0_axi_periph_RVALID <= M02_AXI_rvalid; + m02_couplers_to_ps7_0_axi_periph_WREADY <= M02_AXI_wready; + ps7_0_axi_periph_ACLK_net <= ACLK; + ps7_0_axi_periph_ARESETN_net <= ARESETN; + ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid; + ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid; + ps7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready; + ps7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready; + ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); + ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0); + ps7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast; + ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid; +m00_couplers: entity work.m00_couplers_imp_XFWZ5U + port map ( + M_ACLK => ps7_0_axi_periph_ACLK_net, + M_ARESETN => ps7_0_axi_periph_ARESETN_net, + M_AXI_araddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0), + M_AXI_arready => m00_couplers_to_ps7_0_axi_periph_ARREADY, + M_AXI_arvalid => m00_couplers_to_ps7_0_axi_periph_ARVALID, + M_AXI_awaddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0), + M_AXI_awready => m00_couplers_to_ps7_0_axi_periph_AWREADY, + M_AXI_awvalid => m00_couplers_to_ps7_0_axi_periph_AWVALID, + M_AXI_bready => m00_couplers_to_ps7_0_axi_periph_BREADY, + M_AXI_bresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0), + M_AXI_bvalid => m00_couplers_to_ps7_0_axi_periph_BVALID, + M_AXI_rdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0), + M_AXI_rready => m00_couplers_to_ps7_0_axi_periph_RREADY, + M_AXI_rresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0), + M_AXI_rvalid => m00_couplers_to_ps7_0_axi_periph_RVALID, + M_AXI_wdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0), + M_AXI_wready => m00_couplers_to_ps7_0_axi_periph_WREADY, + M_AXI_wstrb(3 downto 0) => m00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0), + M_AXI_wvalid => m00_couplers_to_ps7_0_axi_periph_WVALID, + S_ACLK => ps7_0_axi_periph_ACLK_net, + S_ARESETN => ps7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), + S_AXI_arready => xbar_to_m00_couplers_ARREADY, + S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0), + S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), + S_AXI_awready => xbar_to_m00_couplers_AWREADY, + S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0), + S_AXI_bready => xbar_to_m00_couplers_BREADY(0), + S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), + S_AXI_bvalid => xbar_to_m00_couplers_BVALID, + S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0), + S_AXI_rready => xbar_to_m00_couplers_RREADY(0), + S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), + S_AXI_rvalid => xbar_to_m00_couplers_RVALID, + S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0), + S_AXI_wready => xbar_to_m00_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0), + S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0) + ); +m01_couplers: entity work.m01_couplers_imp_164MWV7 + port map ( + M_ACLK => ps7_0_axi_periph_ACLK_net, + M_ARESETN => ps7_0_axi_periph_ARESETN_net, + M_AXI_araddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0), + M_AXI_arready => m01_couplers_to_ps7_0_axi_periph_ARREADY, + M_AXI_arvalid => m01_couplers_to_ps7_0_axi_periph_ARVALID, + M_AXI_awaddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0), + M_AXI_awready => m01_couplers_to_ps7_0_axi_periph_AWREADY, + M_AXI_awvalid => m01_couplers_to_ps7_0_axi_periph_AWVALID, + M_AXI_bready => m01_couplers_to_ps7_0_axi_periph_BREADY, + M_AXI_bresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0), + M_AXI_bvalid => m01_couplers_to_ps7_0_axi_periph_BVALID, + M_AXI_rdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0), + M_AXI_rready => m01_couplers_to_ps7_0_axi_periph_RREADY, + M_AXI_rresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0), + M_AXI_rvalid => m01_couplers_to_ps7_0_axi_periph_RVALID, + M_AXI_wdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0), + M_AXI_wready => m01_couplers_to_ps7_0_axi_periph_WREADY, + M_AXI_wstrb(3 downto 0) => m01_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0), + M_AXI_wvalid => m01_couplers_to_ps7_0_axi_periph_WVALID, + S_ACLK => ps7_0_axi_periph_ACLK_net, + S_ARESETN => ps7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32), + S_AXI_arready => xbar_to_m01_couplers_ARREADY, + S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1), + S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32), + S_AXI_awready => xbar_to_m01_couplers_AWREADY, + S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1), + S_AXI_bready => xbar_to_m01_couplers_BREADY(1), + S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0), + S_AXI_bvalid => xbar_to_m01_couplers_BVALID, + S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0), + S_AXI_rready => xbar_to_m01_couplers_RREADY(1), + S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0), + S_AXI_rvalid => xbar_to_m01_couplers_RVALID, + S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32), + S_AXI_wready => xbar_to_m01_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4), + S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1) + ); +m02_couplers: entity work.m02_couplers_imp_YRUE81 + port map ( + M_ACLK => ps7_0_axi_periph_ACLK_net, + M_ARESETN => ps7_0_axi_periph_ARESETN_net, + M_AXI_araddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0), + M_AXI_arready => m02_couplers_to_ps7_0_axi_periph_ARREADY, + M_AXI_arvalid => m02_couplers_to_ps7_0_axi_periph_ARVALID, + M_AXI_awaddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0), + M_AXI_awready => m02_couplers_to_ps7_0_axi_periph_AWREADY, + M_AXI_awvalid => m02_couplers_to_ps7_0_axi_periph_AWVALID, + M_AXI_bready => m02_couplers_to_ps7_0_axi_periph_BREADY, + M_AXI_bresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0), + M_AXI_bvalid => m02_couplers_to_ps7_0_axi_periph_BVALID, + M_AXI_rdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0), + M_AXI_rready => m02_couplers_to_ps7_0_axi_periph_RREADY, + M_AXI_rresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0), + M_AXI_rvalid => m02_couplers_to_ps7_0_axi_periph_RVALID, + M_AXI_wdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0), + M_AXI_wready => m02_couplers_to_ps7_0_axi_periph_WREADY, + M_AXI_wstrb(3 downto 0) => m02_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0), + M_AXI_wvalid => m02_couplers_to_ps7_0_axi_periph_WVALID, + S_ACLK => ps7_0_axi_periph_ACLK_net, + S_ARESETN => ps7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64), + S_AXI_arready => xbar_to_m02_couplers_ARREADY, + S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2), + S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64), + S_AXI_awready => xbar_to_m02_couplers_AWREADY, + S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2), + S_AXI_bready => xbar_to_m02_couplers_BREADY(2), + S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0), + S_AXI_bvalid => xbar_to_m02_couplers_BVALID, + S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0), + S_AXI_rready => xbar_to_m02_couplers_RREADY(2), + S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0), + S_AXI_rvalid => xbar_to_m02_couplers_RVALID, + S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64), + S_AXI_wready => xbar_to_m02_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8), + S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2) + ); +s00_couplers: entity work.s00_couplers_imp_ZZSSAO + port map ( + M_ACLK => ps7_0_axi_periph_ACLK_net, + M_ARESETN => ps7_0_axi_periph_ARESETN_net, + M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), + M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), + M_AXI_arready => s00_couplers_to_xbar_ARREADY(0), + M_AXI_arvalid => s00_couplers_to_xbar_ARVALID, + M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0), + M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0), + M_AXI_awready => s00_couplers_to_xbar_AWREADY(0), + M_AXI_awvalid => s00_couplers_to_xbar_AWVALID, + M_AXI_bready => s00_couplers_to_xbar_BREADY, + M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0), + M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0), + M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0), + M_AXI_rready => s00_couplers_to_xbar_RREADY, + M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), + M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0), + M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0), + M_AXI_wready => s00_couplers_to_xbar_WREADY(0), + M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0), + M_AXI_wvalid => s00_couplers_to_xbar_WVALID, + S_ACLK => ps7_0_axi_periph_ACLK_net, + S_ARESETN => ps7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0), + S_AXI_arburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0), + S_AXI_arcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0), + S_AXI_arid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0), + S_AXI_arlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0), + S_AXI_arlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0), + S_AXI_arprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0), + S_AXI_arqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0), + S_AXI_arready => ps7_0_axi_periph_to_s00_couplers_ARREADY, + S_AXI_arsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0), + S_AXI_arvalid => ps7_0_axi_periph_to_s00_couplers_ARVALID, + S_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0), + S_AXI_awburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0), + S_AXI_awcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0), + S_AXI_awid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0), + S_AXI_awlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0), + S_AXI_awlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0), + S_AXI_awprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0), + S_AXI_awqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0), + S_AXI_awready => ps7_0_axi_periph_to_s00_couplers_AWREADY, + S_AXI_awsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0), + S_AXI_awvalid => ps7_0_axi_periph_to_s00_couplers_AWVALID, + S_AXI_bid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0), + S_AXI_bready => ps7_0_axi_periph_to_s00_couplers_BREADY, + S_AXI_bresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0), + S_AXI_bvalid => ps7_0_axi_periph_to_s00_couplers_BVALID, + S_AXI_rdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0), + S_AXI_rid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0), + S_AXI_rlast => ps7_0_axi_periph_to_s00_couplers_RLAST, + S_AXI_rready => ps7_0_axi_periph_to_s00_couplers_RREADY, + S_AXI_rresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0), + S_AXI_rvalid => ps7_0_axi_periph_to_s00_couplers_RVALID, + S_AXI_wdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0), + S_AXI_wid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0), + S_AXI_wlast => ps7_0_axi_periph_to_s00_couplers_WLAST, + S_AXI_wready => ps7_0_axi_periph_to_s00_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0), + S_AXI_wvalid => ps7_0_axi_periph_to_s00_couplers_WVALID + ); +xbar: component design_3_xbar_0 + port map ( + aclk => ps7_0_axi_periph_ACLK_net, + aresetn => ps7_0_axi_periph_ARESETN_net, + m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64), + m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32), + m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), + m_axi_arprot(8 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(8 downto 0), + m_axi_arready(2) => xbar_to_m02_couplers_ARREADY, + m_axi_arready(1) => xbar_to_m01_couplers_ARREADY, + m_axi_arready(0) => xbar_to_m00_couplers_ARREADY, + m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2), + m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1), + m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0), + m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64), + m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32), + m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), + m_axi_awprot(8 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(8 downto 0), + m_axi_awready(2) => xbar_to_m02_couplers_AWREADY, + m_axi_awready(1) => xbar_to_m01_couplers_AWREADY, + m_axi_awready(0) => xbar_to_m00_couplers_AWREADY, + m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2), + m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1), + m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0), + m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2), + m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1), + m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0), + m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0), + m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0), + m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), + m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID, + m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID, + m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID, + m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0), + m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0), + m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0), + m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2), + m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1), + m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0), + m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0), + m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0), + m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), + m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID, + m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID, + m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID, + m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64), + m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32), + m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0), + m_axi_wready(2) => xbar_to_m02_couplers_WREADY, + m_axi_wready(1) => xbar_to_m01_couplers_WREADY, + m_axi_wready(0) => xbar_to_m00_couplers_WREADY, + m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8), + m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4), + m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0), + m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2), + m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1), + m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0), + s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), + s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), + s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0), + s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID, + s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0), + s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0), + s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0), + s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID, + s_axi_bready(0) => s00_couplers_to_xbar_BREADY, + s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0), + s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0), + s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0), + s_axi_rready(0) => s00_couplers_to_xbar_RREADY, + s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), + s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0), + s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0), + s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0), + s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0), + s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AXI_Intercon_imp_1AN5YJY is + port ( + ACLK : in STD_LOGIC; + M00_AXI1_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI1_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI1_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_arready : in STD_LOGIC; + M00_AXI1_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI1_arvalid : out STD_LOGIC; + M00_AXI1_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI1_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI1_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_awready : in STD_LOGIC; + M00_AXI1_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI1_awvalid : out STD_LOGIC; + M00_AXI1_bready : out STD_LOGIC; + M00_AXI1_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_bvalid : in STD_LOGIC; + M00_AXI1_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI1_rlast : in STD_LOGIC; + M00_AXI1_rready : out STD_LOGIC; + M00_AXI1_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_rvalid : in STD_LOGIC; + M00_AXI1_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI1_wlast : out STD_LOGIC; + M00_AXI1_wready : in STD_LOGIC; + M00_AXI1_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M00_AXI1_wvalid : out STD_LOGIC; + M00_AXI2_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI2_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI2_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_arready : in STD_LOGIC; + M00_AXI2_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI2_arvalid : out STD_LOGIC; + M00_AXI2_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI2_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI2_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_awready : in STD_LOGIC; + M00_AXI2_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI2_awvalid : out STD_LOGIC; + M00_AXI2_bready : out STD_LOGIC; + M00_AXI2_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_bvalid : in STD_LOGIC; + M00_AXI2_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI2_rlast : in STD_LOGIC; + M00_AXI2_rready : out STD_LOGIC; + M00_AXI2_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_rvalid : in STD_LOGIC; + M00_AXI2_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI2_wlast : out STD_LOGIC; + M00_AXI2_wready : in STD_LOGIC; + M00_AXI2_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M00_AXI2_wvalid : out STD_LOGIC; + M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_arready : in STD_LOGIC; + M00_AXI_arvalid : out STD_LOGIC; + M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_awready : in STD_LOGIC; + M00_AXI_awvalid : out STD_LOGIC; + M00_AXI_bready : out STD_LOGIC; + M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_bvalid : in STD_LOGIC; + M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_rready : out STD_LOGIC; + M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_rvalid : in STD_LOGIC; + M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_wready : in STD_LOGIC; + M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_wvalid : out STD_LOGIC; + M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_arready : in STD_LOGIC; + M01_AXI_arvalid : out STD_LOGIC; + M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_awready : in STD_LOGIC; + M01_AXI_awvalid : out STD_LOGIC; + M01_AXI_bready : out STD_LOGIC; + M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M01_AXI_bvalid : in STD_LOGIC; + M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_rready : out STD_LOGIC; + M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M01_AXI_rvalid : in STD_LOGIC; + M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_wready : in STD_LOGIC; + M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M01_AXI_wvalid : out STD_LOGIC; + M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_arready : in STD_LOGIC; + M02_AXI_arvalid : out STD_LOGIC; + M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_awready : in STD_LOGIC; + M02_AXI_awvalid : out STD_LOGIC; + M02_AXI_bready : out STD_LOGIC; + M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M02_AXI_bvalid : in STD_LOGIC; + M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_rready : out STD_LOGIC; + M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M02_AXI_rvalid : in STD_LOGIC; + M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_wready : in STD_LOGIC; + M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M02_AXI_wvalid : out STD_LOGIC; + S00_ARESETN : in STD_LOGIC; + S00_AXI1_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI1_arready : out STD_LOGIC; + S00_AXI1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI1_arvalid : in STD_LOGIC; + S00_AXI1_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI1_awready : out STD_LOGIC; + S00_AXI1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI1_awvalid : in STD_LOGIC; + S00_AXI1_bready : in STD_LOGIC; + S00_AXI1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI1_bvalid : out STD_LOGIC; + S00_AXI1_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI1_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_rlast : out STD_LOGIC; + S00_AXI1_rready : in STD_LOGIC; + S00_AXI1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI1_rvalid : out STD_LOGIC; + S00_AXI1_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI1_wlast : in STD_LOGIC; + S00_AXI1_wready : out STD_LOGIC; + S00_AXI1_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_wvalid : in STD_LOGIC; + S00_AXI2_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI2_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI2_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI2_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI2_arready : out STD_LOGIC; + S00_AXI2_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI2_arvalid : in STD_LOGIC; + S00_AXI2_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI2_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI2_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI2_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI2_awready : out STD_LOGIC; + S00_AXI2_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI2_awvalid : in STD_LOGIC; + S00_AXI2_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI2_bready : in STD_LOGIC; + S00_AXI2_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI2_bvalid : out STD_LOGIC; + S00_AXI2_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI2_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI2_rlast : out STD_LOGIC; + S00_AXI2_rready : in STD_LOGIC; + S00_AXI2_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI2_rvalid : out STD_LOGIC; + S00_AXI2_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI2_wlast : in STD_LOGIC; + S00_AXI2_wready : out STD_LOGIC; + S00_AXI2_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_wvalid : in STD_LOGIC; + S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arready : out STD_LOGIC; + S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arvalid : in STD_LOGIC; + S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awready : out STD_LOGIC; + S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awvalid : in STD_LOGIC; + S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_bready : in STD_LOGIC; + S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_bvalid : out STD_LOGIC; + S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_rlast : out STD_LOGIC; + S00_AXI_rready : in STD_LOGIC; + S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_rvalid : out STD_LOGIC; + S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_wlast : in STD_LOGIC; + S00_AXI_wready : out STD_LOGIC; + S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_wvalid : in STD_LOGIC + ); +end AXI_Intercon_imp_1AN5YJY; + +architecture STRUCTURE of AXI_Intercon_imp_1AN5YJY is + signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_ARREADY : STD_LOGIC; + signal Conn1_ARVALID : STD_LOGIC; + signal Conn1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_AWREADY : STD_LOGIC; + signal Conn1_AWVALID : STD_LOGIC; + signal Conn1_BREADY : STD_LOGIC; + signal Conn1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn1_BVALID : STD_LOGIC; + signal Conn1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_RREADY : STD_LOGIC; + signal Conn1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn1_RVALID : STD_LOGIC; + signal Conn1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_WREADY : STD_LOGIC; + signal Conn1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn1_WVALID : STD_LOGIC; + signal Conn2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_ARREADY : STD_LOGIC; + signal Conn2_ARVALID : STD_LOGIC; + signal Conn2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_AWREADY : STD_LOGIC; + signal Conn2_AWVALID : STD_LOGIC; + signal Conn2_BREADY : STD_LOGIC; + signal Conn2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_BVALID : STD_LOGIC; + signal Conn2_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_RREADY : STD_LOGIC; + signal Conn2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_RVALID : STD_LOGIC; + signal Conn2_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_WREADY : STD_LOGIC; + signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn2_WVALID : STD_LOGIC; + signal S00_AXI2_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S00_AXI2_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S00_AXI2_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal S00_AXI2_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S00_AXI2_1_ARREADY : STD_LOGIC; + signal S00_AXI2_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S00_AXI2_1_ARVALID : STD_LOGIC; + signal S00_AXI2_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S00_AXI2_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S00_AXI2_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal S00_AXI2_1_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S00_AXI2_1_AWREADY : STD_LOGIC; + signal S00_AXI2_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S00_AXI2_1_AWVALID : STD_LOGIC; + signal S00_AXI2_1_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal S00_AXI2_1_BREADY : STD_LOGIC; + signal S00_AXI2_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S00_AXI2_1_BVALID : STD_LOGIC; + signal S00_AXI2_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S00_AXI2_1_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal S00_AXI2_1_RLAST : STD_LOGIC; + signal S00_AXI2_1_RREADY : STD_LOGIC; + signal S00_AXI2_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S00_AXI2_1_RVALID : STD_LOGIC; + signal S00_AXI2_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S00_AXI2_1_WLAST : STD_LOGIC; + signal S00_AXI2_1_WREADY : STD_LOGIC; + signal S00_AXI2_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_WVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_interconnect_0_M00_AXI_RLAST : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_interconnect_0_M00_AXI_WLAST : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC; + signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC; + signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_BVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WVALID : STD_LOGIC; +begin + Conn1_ARREADY <= M01_AXI_arready; + Conn1_AWREADY <= M01_AXI_awready; + Conn1_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0); + Conn1_BVALID <= M01_AXI_bvalid; + Conn1_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0); + Conn1_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0); + Conn1_RVALID <= M01_AXI_rvalid; + Conn1_WREADY <= M01_AXI_wready; + Conn2_ARREADY <= M02_AXI_arready; + Conn2_AWREADY <= M02_AXI_awready; + Conn2_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0); + Conn2_BVALID <= M02_AXI_bvalid; + Conn2_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0); + Conn2_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0); + Conn2_RVALID <= M02_AXI_rvalid; + Conn2_WREADY <= M02_AXI_wready; + M00_AXI1_araddr(31 downto 0) <= axi_mem_intercon_M00_AXI_ARADDR(31 downto 0); + M00_AXI1_arburst(1 downto 0) <= axi_mem_intercon_M00_AXI_ARBURST(1 downto 0); + M00_AXI1_arcache(3 downto 0) <= axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0); + M00_AXI1_arlen(3 downto 0) <= axi_mem_intercon_M00_AXI_ARLEN(3 downto 0); + M00_AXI1_arlock(1 downto 0) <= axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0); + M00_AXI1_arprot(2 downto 0) <= axi_mem_intercon_M00_AXI_ARPROT(2 downto 0); + M00_AXI1_arqos(3 downto 0) <= axi_mem_intercon_M00_AXI_ARQOS(3 downto 0); + M00_AXI1_arsize(2 downto 0) <= axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0); + M00_AXI1_arvalid <= axi_mem_intercon_M00_AXI_ARVALID; + M00_AXI1_awaddr(31 downto 0) <= axi_mem_intercon_M00_AXI_AWADDR(31 downto 0); + M00_AXI1_awburst(1 downto 0) <= axi_mem_intercon_M00_AXI_AWBURST(1 downto 0); + M00_AXI1_awcache(3 downto 0) <= axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0); + M00_AXI1_awlen(3 downto 0) <= axi_mem_intercon_M00_AXI_AWLEN(3 downto 0); + M00_AXI1_awlock(1 downto 0) <= axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0); + M00_AXI1_awprot(2 downto 0) <= axi_mem_intercon_M00_AXI_AWPROT(2 downto 0); + M00_AXI1_awqos(3 downto 0) <= axi_mem_intercon_M00_AXI_AWQOS(3 downto 0); + M00_AXI1_awsize(2 downto 0) <= axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0); + M00_AXI1_awvalid <= axi_mem_intercon_M00_AXI_AWVALID; + M00_AXI1_bready <= axi_mem_intercon_M00_AXI_BREADY; + M00_AXI1_rready <= axi_mem_intercon_M00_AXI_RREADY; + M00_AXI1_wdata(63 downto 0) <= axi_mem_intercon_M00_AXI_WDATA(63 downto 0); + M00_AXI1_wlast <= axi_mem_intercon_M00_AXI_WLAST; + M00_AXI1_wstrb(7 downto 0) <= axi_mem_intercon_M00_AXI_WSTRB(7 downto 0); + M00_AXI1_wvalid <= axi_mem_intercon_M00_AXI_WVALID; + M00_AXI2_araddr(31 downto 0) <= axi_interconnect_0_M00_AXI_ARADDR(31 downto 0); + M00_AXI2_arburst(1 downto 0) <= axi_interconnect_0_M00_AXI_ARBURST(1 downto 0); + M00_AXI2_arcache(3 downto 0) <= axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0); + M00_AXI2_arlen(3 downto 0) <= axi_interconnect_0_M00_AXI_ARLEN(3 downto 0); + M00_AXI2_arlock(1 downto 0) <= axi_interconnect_0_M00_AXI_ARLOCK(1 downto 0); + M00_AXI2_arprot(2 downto 0) <= axi_interconnect_0_M00_AXI_ARPROT(2 downto 0); + M00_AXI2_arqos(3 downto 0) <= axi_interconnect_0_M00_AXI_ARQOS(3 downto 0); + M00_AXI2_arsize(2 downto 0) <= axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0); + M00_AXI2_arvalid <= axi_interconnect_0_M00_AXI_ARVALID; + M00_AXI2_awaddr(31 downto 0) <= axi_interconnect_0_M00_AXI_AWADDR(31 downto 0); + M00_AXI2_awburst(1 downto 0) <= axi_interconnect_0_M00_AXI_AWBURST(1 downto 0); + M00_AXI2_awcache(3 downto 0) <= axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0); + M00_AXI2_awlen(3 downto 0) <= axi_interconnect_0_M00_AXI_AWLEN(3 downto 0); + M00_AXI2_awlock(1 downto 0) <= axi_interconnect_0_M00_AXI_AWLOCK(1 downto 0); + M00_AXI2_awprot(2 downto 0) <= axi_interconnect_0_M00_AXI_AWPROT(2 downto 0); + M00_AXI2_awqos(3 downto 0) <= axi_interconnect_0_M00_AXI_AWQOS(3 downto 0); + M00_AXI2_awsize(2 downto 0) <= axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0); + M00_AXI2_awvalid <= axi_interconnect_0_M00_AXI_AWVALID; + M00_AXI2_bready <= axi_interconnect_0_M00_AXI_BREADY; + M00_AXI2_rready <= axi_interconnect_0_M00_AXI_RREADY; + M00_AXI2_wdata(63 downto 0) <= axi_interconnect_0_M00_AXI_WDATA(63 downto 0); + M00_AXI2_wlast <= axi_interconnect_0_M00_AXI_WLAST; + M00_AXI2_wstrb(7 downto 0) <= axi_interconnect_0_M00_AXI_WSTRB(7 downto 0); + M00_AXI2_wvalid <= axi_interconnect_0_M00_AXI_WVALID; + M00_AXI_araddr(31 downto 0) <= ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0); + M00_AXI_arvalid <= ps7_0_axi_periph_M00_AXI_ARVALID; + M00_AXI_awaddr(31 downto 0) <= ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0); + M00_AXI_awvalid <= ps7_0_axi_periph_M00_AXI_AWVALID; + M00_AXI_bready <= ps7_0_axi_periph_M00_AXI_BREADY; + M00_AXI_rready <= ps7_0_axi_periph_M00_AXI_RREADY; + M00_AXI_wdata(31 downto 0) <= ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0); + M00_AXI_wstrb(3 downto 0) <= ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0); + M00_AXI_wvalid <= ps7_0_axi_periph_M00_AXI_WVALID; + M01_AXI_araddr(31 downto 0) <= Conn1_ARADDR(31 downto 0); + M01_AXI_arvalid <= Conn1_ARVALID; + M01_AXI_awaddr(31 downto 0) <= Conn1_AWADDR(31 downto 0); + M01_AXI_awvalid <= Conn1_AWVALID; + M01_AXI_bready <= Conn1_BREADY; + M01_AXI_rready <= Conn1_RREADY; + M01_AXI_wdata(31 downto 0) <= Conn1_WDATA(31 downto 0); + M01_AXI_wstrb(3 downto 0) <= Conn1_WSTRB(3 downto 0); + M01_AXI_wvalid <= Conn1_WVALID; + M02_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0); + M02_AXI_arvalid <= Conn2_ARVALID; + M02_AXI_awaddr(31 downto 0) <= Conn2_AWADDR(31 downto 0); + M02_AXI_awvalid <= Conn2_AWVALID; + M02_AXI_bready <= Conn2_BREADY; + M02_AXI_rready <= Conn2_RREADY; + M02_AXI_wdata(31 downto 0) <= Conn2_WDATA(31 downto 0); + M02_AXI_wstrb(3 downto 0) <= Conn2_WSTRB(3 downto 0); + M02_AXI_wvalid <= Conn2_WVALID; + S00_AXI1_arready <= zynq_base_hdmi_0_M_AXI_ARREADY; + S00_AXI1_awready <= zynq_base_hdmi_0_M_AXI_AWREADY; + S00_AXI1_bresp(1 downto 0) <= zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0); + S00_AXI1_bvalid <= zynq_base_hdmi_0_M_AXI_BVALID; + S00_AXI1_rdata(31 downto 0) <= zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0); + S00_AXI1_rid(3 downto 0) <= zynq_base_hdmi_0_M_AXI_RID(3 downto 0); + S00_AXI1_rlast <= zynq_base_hdmi_0_M_AXI_RLAST; + S00_AXI1_rresp(1 downto 0) <= zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0); + S00_AXI1_rvalid <= zynq_base_hdmi_0_M_AXI_RVALID; + S00_AXI1_wready <= zynq_base_hdmi_0_M_AXI_WREADY; + S00_AXI2_1_ARADDR(31 downto 0) <= S00_AXI2_araddr(31 downto 0); + S00_AXI2_1_ARBURST(1 downto 0) <= S00_AXI2_arburst(1 downto 0); + S00_AXI2_1_ARCACHE(3 downto 0) <= S00_AXI2_arcache(3 downto 0); + S00_AXI2_1_ARID(0) <= S00_AXI2_arid(0); + S00_AXI2_1_ARLEN(3 downto 0) <= S00_AXI2_arlen(3 downto 0); + S00_AXI2_1_ARPROT(2 downto 0) <= S00_AXI2_arprot(2 downto 0); + S00_AXI2_1_ARSIZE(2 downto 0) <= S00_AXI2_arsize(2 downto 0); + S00_AXI2_1_ARVALID <= S00_AXI2_arvalid; + S00_AXI2_1_AWADDR(31 downto 0) <= S00_AXI2_awaddr(31 downto 0); + S00_AXI2_1_AWBURST(1 downto 0) <= S00_AXI2_awburst(1 downto 0); + S00_AXI2_1_AWCACHE(3 downto 0) <= S00_AXI2_awcache(3 downto 0); + S00_AXI2_1_AWID(0) <= S00_AXI2_awid(0); + S00_AXI2_1_AWLEN(3 downto 0) <= S00_AXI2_awlen(3 downto 0); + S00_AXI2_1_AWPROT(2 downto 0) <= S00_AXI2_awprot(2 downto 0); + S00_AXI2_1_AWSIZE(2 downto 0) <= S00_AXI2_awsize(2 downto 0); + S00_AXI2_1_AWVALID <= S00_AXI2_awvalid; + S00_AXI2_1_BREADY <= S00_AXI2_bready; + S00_AXI2_1_RREADY <= S00_AXI2_rready; + S00_AXI2_1_WDATA(31 downto 0) <= S00_AXI2_wdata(31 downto 0); + S00_AXI2_1_WLAST <= S00_AXI2_wlast; + S00_AXI2_1_WSTRB(3 downto 0) <= S00_AXI2_wstrb(3 downto 0); + S00_AXI2_1_WVALID <= S00_AXI2_wvalid; + S00_AXI2_arready <= S00_AXI2_1_ARREADY; + S00_AXI2_awready <= S00_AXI2_1_AWREADY; + S00_AXI2_bid(0) <= S00_AXI2_1_BID(0); + S00_AXI2_bresp(1 downto 0) <= S00_AXI2_1_BRESP(1 downto 0); + S00_AXI2_bvalid <= S00_AXI2_1_BVALID; + S00_AXI2_rdata(31 downto 0) <= S00_AXI2_1_RDATA(31 downto 0); + S00_AXI2_rid(0) <= S00_AXI2_1_RID(0); + S00_AXI2_rlast <= S00_AXI2_1_RLAST; + S00_AXI2_rresp(1 downto 0) <= S00_AXI2_1_RRESP(1 downto 0); + S00_AXI2_rvalid <= S00_AXI2_1_RVALID; + S00_AXI2_wready <= S00_AXI2_1_WREADY; + S00_AXI_arready <= processing_system7_0_M_AXI_GP0_ARREADY; + S00_AXI_awready <= processing_system7_0_M_AXI_GP0_AWREADY; + S00_AXI_bid(11 downto 0) <= processing_system7_0_M_AXI_GP0_BID(11 downto 0); + S00_AXI_bresp(1 downto 0) <= processing_system7_0_M_AXI_GP0_BRESP(1 downto 0); + S00_AXI_bvalid <= processing_system7_0_M_AXI_GP0_BVALID; + S00_AXI_rdata(31 downto 0) <= processing_system7_0_M_AXI_GP0_RDATA(31 downto 0); + S00_AXI_rid(11 downto 0) <= processing_system7_0_M_AXI_GP0_RID(11 downto 0); + S00_AXI_rlast <= processing_system7_0_M_AXI_GP0_RLAST; + S00_AXI_rresp(1 downto 0) <= processing_system7_0_M_AXI_GP0_RRESP(1 downto 0); + S00_AXI_rvalid <= processing_system7_0_M_AXI_GP0_RVALID; + S00_AXI_wready <= processing_system7_0_M_AXI_GP0_WREADY; + axi_interconnect_0_M00_AXI_ARREADY <= M00_AXI2_arready; + axi_interconnect_0_M00_AXI_AWREADY <= M00_AXI2_awready; + axi_interconnect_0_M00_AXI_BRESP(1 downto 0) <= M00_AXI2_bresp(1 downto 0); + axi_interconnect_0_M00_AXI_BVALID <= M00_AXI2_bvalid; + axi_interconnect_0_M00_AXI_RDATA(63 downto 0) <= M00_AXI2_rdata(63 downto 0); + axi_interconnect_0_M00_AXI_RLAST <= M00_AXI2_rlast; + axi_interconnect_0_M00_AXI_RRESP(1 downto 0) <= M00_AXI2_rresp(1 downto 0); + axi_interconnect_0_M00_AXI_RVALID <= M00_AXI2_rvalid; + axi_interconnect_0_M00_AXI_WREADY <= M00_AXI2_wready; + axi_mem_intercon_M00_AXI_ARREADY <= M00_AXI1_arready; + axi_mem_intercon_M00_AXI_AWREADY <= M00_AXI1_awready; + axi_mem_intercon_M00_AXI_BRESP(1 downto 0) <= M00_AXI1_bresp(1 downto 0); + axi_mem_intercon_M00_AXI_BVALID <= M00_AXI1_bvalid; + axi_mem_intercon_M00_AXI_RDATA(63 downto 0) <= M00_AXI1_rdata(63 downto 0); + axi_mem_intercon_M00_AXI_RLAST <= M00_AXI1_rlast; + axi_mem_intercon_M00_AXI_RRESP(1 downto 0) <= M00_AXI1_rresp(1 downto 0); + axi_mem_intercon_M00_AXI_RVALID <= M00_AXI1_rvalid; + axi_mem_intercon_M00_AXI_WREADY <= M00_AXI1_wready; + processing_system7_0_FCLK_CLK0 <= ACLK; + processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); + processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); + processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); + processing_system7_0_M_AXI_GP0_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0); + processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); + processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0); + processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); + processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0); + processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); + processing_system7_0_M_AXI_GP0_ARVALID <= S00_AXI_arvalid; + processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); + processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); + processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); + processing_system7_0_M_AXI_GP0_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0); + processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); + processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0); + processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); + processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0); + processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); + processing_system7_0_M_AXI_GP0_AWVALID <= S00_AXI_awvalid; + processing_system7_0_M_AXI_GP0_BREADY <= S00_AXI_bready; + processing_system7_0_M_AXI_GP0_RREADY <= S00_AXI_rready; + processing_system7_0_M_AXI_GP0_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); + processing_system7_0_M_AXI_GP0_WID(11 downto 0) <= S00_AXI_wid(11 downto 0); + processing_system7_0_M_AXI_GP0_WLAST <= S00_AXI_wlast; + processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); + processing_system7_0_M_AXI_GP0_WVALID <= S00_AXI_wvalid; + ps7_0_axi_periph_M00_AXI_ARREADY <= M00_AXI_arready; + ps7_0_axi_periph_M00_AXI_AWREADY <= M00_AXI_awready; + ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); + ps7_0_axi_periph_M00_AXI_BVALID <= M00_AXI_bvalid; + ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0); + ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); + ps7_0_axi_periph_M00_AXI_RVALID <= M00_AXI_rvalid; + ps7_0_axi_periph_M00_AXI_WREADY <= M00_AXI_wready; + rst_ps7_0_100M_peripheral_aresetn <= S00_ARESETN; + zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0) <= S00_AXI1_araddr(31 downto 0); + zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0) <= S00_AXI1_arburst(1 downto 0); + zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0) <= S00_AXI1_arcache(3 downto 0); + zynq_base_hdmi_0_M_AXI_ARID(3 downto 0) <= S00_AXI1_arid(3 downto 0); + zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0) <= S00_AXI1_arlen(3 downto 0); + zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0) <= S00_AXI1_arprot(2 downto 0); + zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0) <= S00_AXI1_arsize(2 downto 0); + zynq_base_hdmi_0_M_AXI_ARVALID <= S00_AXI1_arvalid; + zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0) <= S00_AXI1_awaddr(31 downto 0); + zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0) <= S00_AXI1_awburst(1 downto 0); + zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0) <= S00_AXI1_awcache(3 downto 0); + zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0) <= S00_AXI1_awlen(3 downto 0); + zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0) <= S00_AXI1_awprot(2 downto 0); + zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0) <= S00_AXI1_awsize(2 downto 0); + zynq_base_hdmi_0_M_AXI_AWVALID <= S00_AXI1_awvalid; + zynq_base_hdmi_0_M_AXI_BREADY <= S00_AXI1_bready; + zynq_base_hdmi_0_M_AXI_RREADY <= S00_AXI1_rready; + zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0) <= S00_AXI1_wdata(31 downto 0); + zynq_base_hdmi_0_M_AXI_WLAST <= S00_AXI1_wlast; + zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0) <= S00_AXI1_wstrb(3 downto 0); + zynq_base_hdmi_0_M_AXI_WVALID <= S00_AXI1_wvalid; +axi_interconnect_0: entity work.design_3_axi_interconnect_0_0 + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_ACLK => processing_system7_0_FCLK_CLK0, + M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0), + M00_AXI_arburst(1 downto 0) => axi_interconnect_0_M00_AXI_ARBURST(1 downto 0), + M00_AXI_arcache(3 downto 0) => axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0), + M00_AXI_arlen(3 downto 0) => axi_interconnect_0_M00_AXI_ARLEN(3 downto 0), + M00_AXI_arlock(1 downto 0) => axi_interconnect_0_M00_AXI_ARLOCK(1 downto 0), + M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0), + M00_AXI_arqos(3 downto 0) => axi_interconnect_0_M00_AXI_ARQOS(3 downto 0), + M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY, + M00_AXI_arsize(2 downto 0) => axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0), + M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID, + M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0), + M00_AXI_awburst(1 downto 0) => axi_interconnect_0_M00_AXI_AWBURST(1 downto 0), + M00_AXI_awcache(3 downto 0) => axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0), + M00_AXI_awlen(3 downto 0) => axi_interconnect_0_M00_AXI_AWLEN(3 downto 0), + M00_AXI_awlock(1 downto 0) => axi_interconnect_0_M00_AXI_AWLOCK(1 downto 0), + M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0), + M00_AXI_awqos(3 downto 0) => axi_interconnect_0_M00_AXI_AWQOS(3 downto 0), + M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY, + M00_AXI_awsize(2 downto 0) => axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0), + M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID, + M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY, + M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0), + M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID, + M00_AXI_rdata(63 downto 0) => axi_interconnect_0_M00_AXI_RDATA(63 downto 0), + M00_AXI_rlast => axi_interconnect_0_M00_AXI_RLAST, + M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY, + M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0), + M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID, + M00_AXI_wdata(63 downto 0) => axi_interconnect_0_M00_AXI_WDATA(63 downto 0), + M00_AXI_wlast => axi_interconnect_0_M00_AXI_WLAST, + M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY, + M00_AXI_wstrb(7 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(7 downto 0), + M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID, + S00_ACLK => processing_system7_0_FCLK_CLK0, + S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + S00_AXI_araddr(31 downto 0) => S00_AXI2_1_ARADDR(31 downto 0), + S00_AXI_arburst(1 downto 0) => S00_AXI2_1_ARBURST(1 downto 0), + S00_AXI_arcache(3 downto 0) => S00_AXI2_1_ARCACHE(3 downto 0), + S00_AXI_arid(0) => S00_AXI2_1_ARID(0), + S00_AXI_arlen(3 downto 0) => S00_AXI2_1_ARLEN(3 downto 0), + S00_AXI_arprot(2 downto 0) => S00_AXI2_1_ARPROT(2 downto 0), + S00_AXI_arready => S00_AXI2_1_ARREADY, + S00_AXI_arsize(2 downto 0) => S00_AXI2_1_ARSIZE(2 downto 0), + S00_AXI_arvalid => S00_AXI2_1_ARVALID, + S00_AXI_awaddr(31 downto 0) => S00_AXI2_1_AWADDR(31 downto 0), + S00_AXI_awburst(1 downto 0) => S00_AXI2_1_AWBURST(1 downto 0), + S00_AXI_awcache(3 downto 0) => S00_AXI2_1_AWCACHE(3 downto 0), + S00_AXI_awid(0) => S00_AXI2_1_AWID(0), + S00_AXI_awlen(3 downto 0) => S00_AXI2_1_AWLEN(3 downto 0), + S00_AXI_awprot(2 downto 0) => S00_AXI2_1_AWPROT(2 downto 0), + S00_AXI_awready => S00_AXI2_1_AWREADY, + S00_AXI_awsize(2 downto 0) => S00_AXI2_1_AWSIZE(2 downto 0), + S00_AXI_awvalid => S00_AXI2_1_AWVALID, + S00_AXI_bid(0) => S00_AXI2_1_BID(0), + S00_AXI_bready => S00_AXI2_1_BREADY, + S00_AXI_bresp(1 downto 0) => S00_AXI2_1_BRESP(1 downto 0), + S00_AXI_bvalid => S00_AXI2_1_BVALID, + S00_AXI_rdata(31 downto 0) => S00_AXI2_1_RDATA(31 downto 0), + S00_AXI_rid(0) => S00_AXI2_1_RID(0), + S00_AXI_rlast => S00_AXI2_1_RLAST, + S00_AXI_rready => S00_AXI2_1_RREADY, + S00_AXI_rresp(1 downto 0) => S00_AXI2_1_RRESP(1 downto 0), + S00_AXI_rvalid => S00_AXI2_1_RVALID, + S00_AXI_wdata(31 downto 0) => S00_AXI2_1_WDATA(31 downto 0), + S00_AXI_wlast => S00_AXI2_1_WLAST, + S00_AXI_wready => S00_AXI2_1_WREADY, + S00_AXI_wstrb(3 downto 0) => S00_AXI2_1_WSTRB(3 downto 0), + S00_AXI_wvalid => S00_AXI2_1_WVALID + ); +axi_mem_intercon: entity work.design_3_axi_mem_intercon_0 + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_ACLK => processing_system7_0_FCLK_CLK0, + M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), + M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), + M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), + M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), + M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), + M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), + M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), + M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY, + M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), + M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID, + M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), + M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), + M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), + M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), + M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), + M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), + M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), + M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY, + M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), + M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID, + M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY, + M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), + M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID, + M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), + M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST, + M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY, + M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), + M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID, + M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), + M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST, + M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY, + M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), + M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID, + S00_ACLK => processing_system7_0_FCLK_CLK0, + S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + S00_AXI_araddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0), + S00_AXI_arburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0), + S00_AXI_arcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0), + S00_AXI_arid(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARID(3 downto 0), + S00_AXI_arlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0), + S00_AXI_arprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0), + S00_AXI_arready => zynq_base_hdmi_0_M_AXI_ARREADY, + S00_AXI_arsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0), + S00_AXI_arvalid => zynq_base_hdmi_0_M_AXI_ARVALID, + S00_AXI_awaddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0), + S00_AXI_awburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0), + S00_AXI_awcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0), + S00_AXI_awlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0), + S00_AXI_awprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0), + S00_AXI_awready => zynq_base_hdmi_0_M_AXI_AWREADY, + S00_AXI_awsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0), + S00_AXI_awvalid => zynq_base_hdmi_0_M_AXI_AWVALID, + S00_AXI_bready => zynq_base_hdmi_0_M_AXI_BREADY, + S00_AXI_bresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0), + S00_AXI_bvalid => zynq_base_hdmi_0_M_AXI_BVALID, + S00_AXI_rdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0), + S00_AXI_rid(3 downto 0) => zynq_base_hdmi_0_M_AXI_RID(3 downto 0), + S00_AXI_rlast => zynq_base_hdmi_0_M_AXI_RLAST, + S00_AXI_rready => zynq_base_hdmi_0_M_AXI_RREADY, + S00_AXI_rresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0), + S00_AXI_rvalid => zynq_base_hdmi_0_M_AXI_RVALID, + S00_AXI_wdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0), + S00_AXI_wlast => zynq_base_hdmi_0_M_AXI_WLAST, + S00_AXI_wready => zynq_base_hdmi_0_M_AXI_WREADY, + S00_AXI_wstrb(3 downto 0) => zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0), + S00_AXI_wvalid => zynq_base_hdmi_0_M_AXI_WVALID + ); +ps7_0_axi_periph: entity work.design_3_ps7_0_axi_periph_0 + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_ACLK => processing_system7_0_FCLK_CLK0, + M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0), + M00_AXI_arready => ps7_0_axi_periph_M00_AXI_ARREADY, + M00_AXI_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID, + M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0), + M00_AXI_awready => ps7_0_axi_periph_M00_AXI_AWREADY, + M00_AXI_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID, + M00_AXI_bready => ps7_0_axi_periph_M00_AXI_BREADY, + M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), + M00_AXI_bvalid => ps7_0_axi_periph_M00_AXI_BVALID, + M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), + M00_AXI_rready => ps7_0_axi_periph_M00_AXI_RREADY, + M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), + M00_AXI_rvalid => ps7_0_axi_periph_M00_AXI_RVALID, + M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), + M00_AXI_wready => ps7_0_axi_periph_M00_AXI_WREADY, + M00_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), + M00_AXI_wvalid => ps7_0_axi_periph_M00_AXI_WVALID, + M01_ACLK => processing_system7_0_FCLK_CLK0, + M01_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M01_AXI_araddr(31 downto 0) => Conn1_ARADDR(31 downto 0), + M01_AXI_arready => Conn1_ARREADY, + M01_AXI_arvalid => Conn1_ARVALID, + M01_AXI_awaddr(31 downto 0) => Conn1_AWADDR(31 downto 0), + M01_AXI_awready => Conn1_AWREADY, + M01_AXI_awvalid => Conn1_AWVALID, + M01_AXI_bready => Conn1_BREADY, + M01_AXI_bresp(1 downto 0) => Conn1_BRESP(1 downto 0), + M01_AXI_bvalid => Conn1_BVALID, + M01_AXI_rdata(31 downto 0) => Conn1_RDATA(31 downto 0), + M01_AXI_rready => Conn1_RREADY, + M01_AXI_rresp(1 downto 0) => Conn1_RRESP(1 downto 0), + M01_AXI_rvalid => Conn1_RVALID, + M01_AXI_wdata(31 downto 0) => Conn1_WDATA(31 downto 0), + M01_AXI_wready => Conn1_WREADY, + M01_AXI_wstrb(3 downto 0) => Conn1_WSTRB(3 downto 0), + M01_AXI_wvalid => Conn1_WVALID, + M02_ACLK => processing_system7_0_FCLK_CLK0, + M02_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M02_AXI_araddr(31 downto 0) => Conn2_ARADDR(31 downto 0), + M02_AXI_arready => Conn2_ARREADY, + M02_AXI_arvalid => Conn2_ARVALID, + M02_AXI_awaddr(31 downto 0) => Conn2_AWADDR(31 downto 0), + M02_AXI_awready => Conn2_AWREADY, + M02_AXI_awvalid => Conn2_AWVALID, + M02_AXI_bready => Conn2_BREADY, + M02_AXI_bresp(1 downto 0) => Conn2_BRESP(1 downto 0), + M02_AXI_bvalid => Conn2_BVALID, + M02_AXI_rdata(31 downto 0) => Conn2_RDATA(31 downto 0), + M02_AXI_rready => Conn2_RREADY, + M02_AXI_rresp(1 downto 0) => Conn2_RRESP(1 downto 0), + M02_AXI_rvalid => Conn2_RVALID, + M02_AXI_wdata(31 downto 0) => Conn2_WDATA(31 downto 0), + M02_AXI_wready => Conn2_WREADY, + M02_AXI_wstrb(3 downto 0) => Conn2_WSTRB(3 downto 0), + M02_AXI_wvalid => Conn2_WVALID, + S00_ACLK => processing_system7_0_FCLK_CLK0, + S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), + S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), + S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), + S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), + S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), + S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), + S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), + S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), + S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY, + S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), + S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID, + S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), + S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), + S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), + S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), + S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), + S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), + S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), + S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), + S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY, + S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), + S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID, + S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), + S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY, + S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), + S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID, + S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), + S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), + S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST, + S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY, + S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), + S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID, + S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), + S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), + S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST, + S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY, + S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), + S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_3 is + port ( + BUTTON : in STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_cas_n : inout STD_LOGIC; + DDR_ck_n : inout STD_LOGIC; + DDR_ck_p : inout STD_LOGIC; + DDR_cke : inout STD_LOGIC; + DDR_cs_n : inout STD_LOGIC; + DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_odt : inout STD_LOGIC; + DDR_ras_n : inout STD_LOGIC; + DDR_reset_n : inout STD_LOGIC; + DDR_we_n : inout STD_LOGIC; + FIXED_IO_ddr_vrn : inout STD_LOGIC; + FIXED_IO_ddr_vrp : inout STD_LOGIC; + FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + FIXED_IO_ps_clk : inout STD_LOGIC; + FIXED_IO_ps_porb : inout STD_LOGIC; + FIXED_IO_ps_srstb : inout STD_LOGIC; + HDMI_CLK_N : out STD_LOGIC; + HDMI_CLK_P : out STD_LOGIC; + HDMI_DATA_N : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_DATA_P : out STD_LOGIC_VECTOR ( 2 downto 0 ); + LED : out STD_LOGIC_VECTOR ( 3 downto 0 ); + RGB_LED : out STD_LOGIC_VECTOR ( 5 downto 0 ); + SWITCH : in STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of design_3 : entity is "design_3,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_3,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=27,numReposBlks=14,numNonXlnxBlks=1,numHierBlks=13,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of design_3 : entity is "design_3.hwdef"; +end design_3; + +architecture STRUCTURE of design_3 is + signal AXI_Intercon_M00_AXI2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARVALID : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWVALID : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_BREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_BVALID : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal AXI_Intercon_M00_AXI2_RLAST : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_RREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_RVALID : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal AXI_Intercon_M00_AXI2_WLAST : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_WREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal AXI_Intercon_M00_AXI2_WVALID : STD_LOGIC; + signal BUTTON_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal SWITCH_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL1_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_ARREADY : STD_LOGIC; + signal S_AXIL1_1_ARVALID : STD_LOGIC; + signal S_AXIL1_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_AWREADY : STD_LOGIC; + signal S_AXIL1_1_AWVALID : STD_LOGIC; + signal S_AXIL1_1_BREADY : STD_LOGIC; + signal S_AXIL1_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL1_1_BVALID : STD_LOGIC; + signal S_AXIL1_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_RREADY : STD_LOGIC; + signal S_AXIL1_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL1_1_RVALID : STD_LOGIC; + signal S_AXIL1_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_WREADY : STD_LOGIC; + signal S_AXIL1_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL1_1_WVALID : STD_LOGIC; + signal S_AXIL_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_ARREADY : STD_LOGIC; + signal S_AXIL_1_ARVALID : STD_LOGIC; + signal S_AXIL_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_AWREADY : STD_LOGIC; + signal S_AXIL_1_AWVALID : STD_LOGIC; + signal S_AXIL_1_BREADY : STD_LOGIC; + signal S_AXIL_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL_1_BVALID : STD_LOGIC; + signal S_AXIL_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_RREADY : STD_LOGIC; + signal S_AXIL_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL_1_RVALID : STD_LOGIC; + signal S_AXIL_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_WREADY : STD_LOGIC; + signal S_AXIL_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL_1_WVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal VideoSubsystem_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal VideoSubsystem_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal VideoSubsystem_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal VideoSubsystem_M_AXI_ARREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal VideoSubsystem_M_AXI_ARVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal VideoSubsystem_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal VideoSubsystem_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal VideoSubsystem_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal VideoSubsystem_M_AXI_AWREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal VideoSubsystem_M_AXI_AWVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal VideoSubsystem_M_AXI_BREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal VideoSubsystem_M_AXI_BVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal VideoSubsystem_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal VideoSubsystem_M_AXI_RLAST : STD_LOGIC; + signal VideoSubsystem_M_AXI_RREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal VideoSubsystem_M_AXI_RVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal VideoSubsystem_M_AXI_WLAST : STD_LOGIC; + signal VideoSubsystem_M_AXI_WREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_WVALID : STD_LOGIC; + signal VideoSubsystem_VS2MM_INTERRUPT : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC; + signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_DDR_CAS_N : STD_LOGIC; + signal processing_system7_0_DDR_CKE : STD_LOGIC; + signal processing_system7_0_DDR_CK_N : STD_LOGIC; + signal processing_system7_0_DDR_CK_P : STD_LOGIC; + signal processing_system7_0_DDR_CS_N : STD_LOGIC; + signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_ODT : STD_LOGIC; + signal processing_system7_0_DDR_RAS_N : STD_LOGIC; + signal processing_system7_0_DDR_RESET_N : STD_LOGIC; + signal processing_system7_0_DDR_WE_N : STD_LOGIC; + signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; + signal processing_system7_0_FCLK_CLK3 : STD_LOGIC; + signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC; + signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC; + signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); + signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC; + signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC; + signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC; + signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); + signal zynq_base_hdmi_0_HDMI_CLK_N : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_CLK_P : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_DATA_N : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_HDMI_DATA_P : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_LED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_BVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WVALID : STD_LOGIC; + signal zynq_base_hdmi_0_RGB_LED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal zynq_base_hdmi_0_VIDEO_INTERRUPT : STD_LOGIC; + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_INFO of DDR_cas_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; + attribute X_INTERFACE_INFO of DDR_ck_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; + attribute X_INTERFACE_INFO of DDR_ck_p : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; + attribute X_INTERFACE_INFO of DDR_cke : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; + attribute X_INTERFACE_INFO of DDR_cs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; + attribute X_INTERFACE_INFO of DDR_odt : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; + attribute X_INTERFACE_INFO of DDR_ras_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; + attribute X_INTERFACE_INFO of DDR_reset_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; + attribute X_INTERFACE_INFO of DDR_we_n : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; + attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrn : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; + attribute X_INTERFACE_PARAMETER : string; + attribute X_INTERFACE_PARAMETER of FIXED_IO_ddr_vrn : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; + attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrp : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; + attribute X_INTERFACE_INFO of FIXED_IO_ps_clk : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; + attribute X_INTERFACE_INFO of FIXED_IO_ps_porb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; + attribute X_INTERFACE_INFO of FIXED_IO_ps_srstb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; + attribute X_INTERFACE_INFO of DDR_addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; + attribute X_INTERFACE_PARAMETER of DDR_addr : signal is "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250"; + attribute X_INTERFACE_INFO of DDR_ba : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; + attribute X_INTERFACE_INFO of DDR_dm : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; + attribute X_INTERFACE_INFO of DDR_dq : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; + attribute X_INTERFACE_INFO of DDR_dqs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; + attribute X_INTERFACE_INFO of DDR_dqs_p : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; + attribute X_INTERFACE_INFO of FIXED_IO_mio : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; +begin + BUTTON_0_1(3 downto 0) <= BUTTON(3 downto 0); + HDMI_CLK_N <= zynq_base_hdmi_0_HDMI_CLK_N; + HDMI_CLK_P <= zynq_base_hdmi_0_HDMI_CLK_P; + HDMI_DATA_N(2 downto 0) <= zynq_base_hdmi_0_HDMI_DATA_N(2 downto 0); + HDMI_DATA_P(2 downto 0) <= zynq_base_hdmi_0_HDMI_DATA_P(2 downto 0); + LED(3 downto 0) <= zynq_base_hdmi_0_LED(3 downto 0); + RGB_LED(5 downto 0) <= zynq_base_hdmi_0_RGB_LED(5 downto 0); + SWITCH_0_1(3 downto 0) <= SWITCH(3 downto 0); +AXI_Intercon: entity work.AXI_Intercon_imp_1AN5YJY + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + M00_AXI1_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), + M00_AXI1_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), + M00_AXI1_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), + M00_AXI1_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), + M00_AXI1_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), + M00_AXI1_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), + M00_AXI1_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), + M00_AXI1_arready => axi_mem_intercon_M00_AXI_ARREADY, + M00_AXI1_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), + M00_AXI1_arvalid => axi_mem_intercon_M00_AXI_ARVALID, + M00_AXI1_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), + M00_AXI1_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), + M00_AXI1_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), + M00_AXI1_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), + M00_AXI1_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), + M00_AXI1_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), + M00_AXI1_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), + M00_AXI1_awready => axi_mem_intercon_M00_AXI_AWREADY, + M00_AXI1_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), + M00_AXI1_awvalid => axi_mem_intercon_M00_AXI_AWVALID, + M00_AXI1_bready => axi_mem_intercon_M00_AXI_BREADY, + M00_AXI1_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), + M00_AXI1_bvalid => axi_mem_intercon_M00_AXI_BVALID, + M00_AXI1_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), + M00_AXI1_rlast => axi_mem_intercon_M00_AXI_RLAST, + M00_AXI1_rready => axi_mem_intercon_M00_AXI_RREADY, + M00_AXI1_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), + M00_AXI1_rvalid => axi_mem_intercon_M00_AXI_RVALID, + M00_AXI1_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), + M00_AXI1_wlast => axi_mem_intercon_M00_AXI_WLAST, + M00_AXI1_wready => axi_mem_intercon_M00_AXI_WREADY, + M00_AXI1_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), + M00_AXI1_wvalid => axi_mem_intercon_M00_AXI_WVALID, + M00_AXI2_araddr(31 downto 0) => AXI_Intercon_M00_AXI2_ARADDR(31 downto 0), + M00_AXI2_arburst(1 downto 0) => AXI_Intercon_M00_AXI2_ARBURST(1 downto 0), + M00_AXI2_arcache(3 downto 0) => AXI_Intercon_M00_AXI2_ARCACHE(3 downto 0), + M00_AXI2_arlen(3 downto 0) => AXI_Intercon_M00_AXI2_ARLEN(3 downto 0), + M00_AXI2_arlock(1 downto 0) => AXI_Intercon_M00_AXI2_ARLOCK(1 downto 0), + M00_AXI2_arprot(2 downto 0) => AXI_Intercon_M00_AXI2_ARPROT(2 downto 0), + M00_AXI2_arqos(3 downto 0) => AXI_Intercon_M00_AXI2_ARQOS(3 downto 0), + M00_AXI2_arready => AXI_Intercon_M00_AXI2_ARREADY, + M00_AXI2_arsize(2 downto 0) => AXI_Intercon_M00_AXI2_ARSIZE(2 downto 0), + M00_AXI2_arvalid => AXI_Intercon_M00_AXI2_ARVALID, + M00_AXI2_awaddr(31 downto 0) => AXI_Intercon_M00_AXI2_AWADDR(31 downto 0), + M00_AXI2_awburst(1 downto 0) => AXI_Intercon_M00_AXI2_AWBURST(1 downto 0), + M00_AXI2_awcache(3 downto 0) => AXI_Intercon_M00_AXI2_AWCACHE(3 downto 0), + M00_AXI2_awlen(3 downto 0) => AXI_Intercon_M00_AXI2_AWLEN(3 downto 0), + M00_AXI2_awlock(1 downto 0) => AXI_Intercon_M00_AXI2_AWLOCK(1 downto 0), + M00_AXI2_awprot(2 downto 0) => AXI_Intercon_M00_AXI2_AWPROT(2 downto 0), + M00_AXI2_awqos(3 downto 0) => AXI_Intercon_M00_AXI2_AWQOS(3 downto 0), + M00_AXI2_awready => AXI_Intercon_M00_AXI2_AWREADY, + M00_AXI2_awsize(2 downto 0) => AXI_Intercon_M00_AXI2_AWSIZE(2 downto 0), + M00_AXI2_awvalid => AXI_Intercon_M00_AXI2_AWVALID, + M00_AXI2_bready => AXI_Intercon_M00_AXI2_BREADY, + M00_AXI2_bresp(1 downto 0) => AXI_Intercon_M00_AXI2_BRESP(1 downto 0), + M00_AXI2_bvalid => AXI_Intercon_M00_AXI2_BVALID, + M00_AXI2_rdata(63 downto 0) => AXI_Intercon_M00_AXI2_RDATA(63 downto 0), + M00_AXI2_rlast => AXI_Intercon_M00_AXI2_RLAST, + M00_AXI2_rready => AXI_Intercon_M00_AXI2_RREADY, + M00_AXI2_rresp(1 downto 0) => AXI_Intercon_M00_AXI2_RRESP(1 downto 0), + M00_AXI2_rvalid => AXI_Intercon_M00_AXI2_RVALID, + M00_AXI2_wdata(63 downto 0) => AXI_Intercon_M00_AXI2_WDATA(63 downto 0), + M00_AXI2_wlast => AXI_Intercon_M00_AXI2_WLAST, + M00_AXI2_wready => AXI_Intercon_M00_AXI2_WREADY, + M00_AXI2_wstrb(7 downto 0) => AXI_Intercon_M00_AXI2_WSTRB(7 downto 0), + M00_AXI2_wvalid => AXI_Intercon_M00_AXI2_WVALID, + M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0), + M00_AXI_arready => ps7_0_axi_periph_M00_AXI_ARREADY, + M00_AXI_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID, + M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0), + M00_AXI_awready => ps7_0_axi_periph_M00_AXI_AWREADY, + M00_AXI_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID, + M00_AXI_bready => ps7_0_axi_periph_M00_AXI_BREADY, + M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), + M00_AXI_bvalid => ps7_0_axi_periph_M00_AXI_BVALID, + M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), + M00_AXI_rready => ps7_0_axi_periph_M00_AXI_RREADY, + M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), + M00_AXI_rvalid => ps7_0_axi_periph_M00_AXI_RVALID, + M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), + M00_AXI_wready => ps7_0_axi_periph_M00_AXI_WREADY, + M00_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), + M00_AXI_wvalid => ps7_0_axi_periph_M00_AXI_WVALID, + M01_AXI_araddr(31 downto 0) => S_AXIL_1_ARADDR(31 downto 0), + M01_AXI_arready => S_AXIL_1_ARREADY, + M01_AXI_arvalid => S_AXIL_1_ARVALID, + M01_AXI_awaddr(31 downto 0) => S_AXIL_1_AWADDR(31 downto 0), + M01_AXI_awready => S_AXIL_1_AWREADY, + M01_AXI_awvalid => S_AXIL_1_AWVALID, + M01_AXI_bready => S_AXIL_1_BREADY, + M01_AXI_bresp(1 downto 0) => S_AXIL_1_BRESP(1 downto 0), + M01_AXI_bvalid => S_AXIL_1_BVALID, + M01_AXI_rdata(31 downto 0) => S_AXIL_1_RDATA(31 downto 0), + M01_AXI_rready => S_AXIL_1_RREADY, + M01_AXI_rresp(1 downto 0) => S_AXIL_1_RRESP(1 downto 0), + M01_AXI_rvalid => S_AXIL_1_RVALID, + M01_AXI_wdata(31 downto 0) => S_AXIL_1_WDATA(31 downto 0), + M01_AXI_wready => S_AXIL_1_WREADY, + M01_AXI_wstrb(3 downto 0) => S_AXIL_1_WSTRB(3 downto 0), + M01_AXI_wvalid => S_AXIL_1_WVALID, + M02_AXI_araddr(31 downto 0) => S_AXIL1_1_ARADDR(31 downto 0), + M02_AXI_arready => S_AXIL1_1_ARREADY, + M02_AXI_arvalid => S_AXIL1_1_ARVALID, + M02_AXI_awaddr(31 downto 0) => S_AXIL1_1_AWADDR(31 downto 0), + M02_AXI_awready => S_AXIL1_1_AWREADY, + M02_AXI_awvalid => S_AXIL1_1_AWVALID, + M02_AXI_bready => S_AXIL1_1_BREADY, + M02_AXI_bresp(1 downto 0) => S_AXIL1_1_BRESP(1 downto 0), + M02_AXI_bvalid => S_AXIL1_1_BVALID, + M02_AXI_rdata(31 downto 0) => S_AXIL1_1_RDATA(31 downto 0), + M02_AXI_rready => S_AXIL1_1_RREADY, + M02_AXI_rresp(1 downto 0) => S_AXIL1_1_RRESP(1 downto 0), + M02_AXI_rvalid => S_AXIL1_1_RVALID, + M02_AXI_wdata(31 downto 0) => S_AXIL1_1_WDATA(31 downto 0), + M02_AXI_wready => S_AXIL1_1_WREADY, + M02_AXI_wstrb(3 downto 0) => S_AXIL1_1_WSTRB(3 downto 0), + M02_AXI_wvalid => S_AXIL1_1_WVALID, + S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0), + S00_AXI1_araddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0), + S00_AXI1_arburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0), + S00_AXI1_arcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0), + S00_AXI1_arid(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARID(3 downto 0), + S00_AXI1_arlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0), + S00_AXI1_arprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0), + S00_AXI1_arready => zynq_base_hdmi_0_M_AXI_ARREADY, + S00_AXI1_arsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0), + S00_AXI1_arvalid => zynq_base_hdmi_0_M_AXI_ARVALID, + S00_AXI1_awaddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0), + S00_AXI1_awburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0), + S00_AXI1_awcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0), + S00_AXI1_awlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0), + S00_AXI1_awprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0), + S00_AXI1_awready => zynq_base_hdmi_0_M_AXI_AWREADY, + S00_AXI1_awsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0), + S00_AXI1_awvalid => zynq_base_hdmi_0_M_AXI_AWVALID, + S00_AXI1_bready => zynq_base_hdmi_0_M_AXI_BREADY, + S00_AXI1_bresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0), + S00_AXI1_bvalid => zynq_base_hdmi_0_M_AXI_BVALID, + S00_AXI1_rdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0), + S00_AXI1_rid(3 downto 0) => zynq_base_hdmi_0_M_AXI_RID(3 downto 0), + S00_AXI1_rlast => zynq_base_hdmi_0_M_AXI_RLAST, + S00_AXI1_rready => zynq_base_hdmi_0_M_AXI_RREADY, + S00_AXI1_rresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0), + S00_AXI1_rvalid => zynq_base_hdmi_0_M_AXI_RVALID, + S00_AXI1_wdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0), + S00_AXI1_wlast => zynq_base_hdmi_0_M_AXI_WLAST, + S00_AXI1_wready => zynq_base_hdmi_0_M_AXI_WREADY, + S00_AXI1_wstrb(3 downto 0) => zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0), + S00_AXI1_wvalid => zynq_base_hdmi_0_M_AXI_WVALID, + S00_AXI2_araddr(31 downto 0) => VideoSubsystem_M_AXI_ARADDR(31 downto 0), + S00_AXI2_arburst(1 downto 0) => VideoSubsystem_M_AXI_ARBURST(1 downto 0), + S00_AXI2_arcache(3 downto 0) => VideoSubsystem_M_AXI_ARCACHE(3 downto 0), + S00_AXI2_arid(0) => VideoSubsystem_M_AXI_ARID(0), + S00_AXI2_arlen(3 downto 0) => VideoSubsystem_M_AXI_ARLEN(3 downto 0), + S00_AXI2_arprot(2 downto 0) => VideoSubsystem_M_AXI_ARPROT(2 downto 0), + S00_AXI2_arready => VideoSubsystem_M_AXI_ARREADY, + S00_AXI2_arsize(2 downto 0) => VideoSubsystem_M_AXI_ARSIZE(2 downto 0), + S00_AXI2_arvalid => VideoSubsystem_M_AXI_ARVALID, + S00_AXI2_awaddr(31 downto 0) => VideoSubsystem_M_AXI_AWADDR(31 downto 0), + S00_AXI2_awburst(1 downto 0) => VideoSubsystem_M_AXI_AWBURST(1 downto 0), + S00_AXI2_awcache(3 downto 0) => VideoSubsystem_M_AXI_AWCACHE(3 downto 0), + S00_AXI2_awid(0) => VideoSubsystem_M_AXI_AWID(0), + S00_AXI2_awlen(3 downto 0) => VideoSubsystem_M_AXI_AWLEN(3 downto 0), + S00_AXI2_awprot(2 downto 0) => VideoSubsystem_M_AXI_AWPROT(2 downto 0), + S00_AXI2_awready => VideoSubsystem_M_AXI_AWREADY, + S00_AXI2_awsize(2 downto 0) => VideoSubsystem_M_AXI_AWSIZE(2 downto 0), + S00_AXI2_awvalid => VideoSubsystem_M_AXI_AWVALID, + S00_AXI2_bid(0) => VideoSubsystem_M_AXI_BID(0), + S00_AXI2_bready => VideoSubsystem_M_AXI_BREADY, + S00_AXI2_bresp(1 downto 0) => VideoSubsystem_M_AXI_BRESP(1 downto 0), + S00_AXI2_bvalid => VideoSubsystem_M_AXI_BVALID, + S00_AXI2_rdata(31 downto 0) => VideoSubsystem_M_AXI_RDATA(31 downto 0), + S00_AXI2_rid(0) => VideoSubsystem_M_AXI_RID(0), + S00_AXI2_rlast => VideoSubsystem_M_AXI_RLAST, + S00_AXI2_rready => VideoSubsystem_M_AXI_RREADY, + S00_AXI2_rresp(1 downto 0) => VideoSubsystem_M_AXI_RRESP(1 downto 0), + S00_AXI2_rvalid => VideoSubsystem_M_AXI_RVALID, + S00_AXI2_wdata(31 downto 0) => VideoSubsystem_M_AXI_WDATA(31 downto 0), + S00_AXI2_wlast => VideoSubsystem_M_AXI_WLAST, + S00_AXI2_wready => VideoSubsystem_M_AXI_WREADY, + S00_AXI2_wstrb(3 downto 0) => VideoSubsystem_M_AXI_WSTRB(3 downto 0), + S00_AXI2_wvalid => VideoSubsystem_M_AXI_WVALID, + S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), + S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), + S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), + S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), + S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), + S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), + S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), + S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), + S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY, + S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), + S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID, + S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), + S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), + S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), + S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), + S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), + S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), + S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), + S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), + S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY, + S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), + S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID, + S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), + S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY, + S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), + S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID, + S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), + S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), + S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST, + S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY, + S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), + S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID, + S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), + S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), + S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST, + S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY, + S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), + S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID + ); +PS: entity work.PS_imp_Z714CR + port map ( + DDR_addr(14 downto 0) => DDR_addr(14 downto 0), + DDR_ba(2 downto 0) => DDR_ba(2 downto 0), + DDR_cas_n => DDR_cas_n, + DDR_ck_n => DDR_ck_n, + DDR_ck_p => DDR_ck_p, + DDR_cke => DDR_cke, + DDR_cs_n => DDR_cs_n, + DDR_dm(3 downto 0) => DDR_dm(3 downto 0), + DDR_dq(31 downto 0) => DDR_dq(31 downto 0), + DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), + DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), + DDR_odt => DDR_odt, + DDR_ras_n => DDR_ras_n, + DDR_reset_n => DDR_reset_n, + DDR_we_n => DDR_we_n, + FCLK_CLK0 => processing_system7_0_FCLK_CLK0, + FCLK_CLK3 => processing_system7_0_FCLK_CLK3, + FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, + FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), + FIXED_IO_ps_clk => FIXED_IO_ps_clk, + FIXED_IO_ps_porb => FIXED_IO_ps_porb, + FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, + In0(0) => zynq_base_hdmi_0_VIDEO_INTERRUPT, + In1 => VideoSubsystem_VS2MM_INTERRUPT, + M_AXI_GP0_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), + M_AXI_GP0_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), + M_AXI_GP0_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), + M_AXI_GP0_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), + M_AXI_GP0_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), + M_AXI_GP0_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), + M_AXI_GP0_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), + M_AXI_GP0_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), + M_AXI_GP0_arready => processing_system7_0_M_AXI_GP0_ARREADY, + M_AXI_GP0_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), + M_AXI_GP0_arvalid => processing_system7_0_M_AXI_GP0_ARVALID, + M_AXI_GP0_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), + M_AXI_GP0_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), + M_AXI_GP0_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), + M_AXI_GP0_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), + M_AXI_GP0_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), + M_AXI_GP0_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), + M_AXI_GP0_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), + M_AXI_GP0_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), + M_AXI_GP0_awready => processing_system7_0_M_AXI_GP0_AWREADY, + M_AXI_GP0_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), + M_AXI_GP0_awvalid => processing_system7_0_M_AXI_GP0_AWVALID, + M_AXI_GP0_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), + M_AXI_GP0_bready => processing_system7_0_M_AXI_GP0_BREADY, + M_AXI_GP0_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), + M_AXI_GP0_bvalid => processing_system7_0_M_AXI_GP0_BVALID, + M_AXI_GP0_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), + M_AXI_GP0_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), + M_AXI_GP0_rlast => processing_system7_0_M_AXI_GP0_RLAST, + M_AXI_GP0_rready => processing_system7_0_M_AXI_GP0_RREADY, + M_AXI_GP0_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), + M_AXI_GP0_rvalid => processing_system7_0_M_AXI_GP0_RVALID, + M_AXI_GP0_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), + M_AXI_GP0_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), + M_AXI_GP0_wlast => processing_system7_0_M_AXI_GP0_WLAST, + M_AXI_GP0_wready => processing_system7_0_M_AXI_GP0_WREADY, + M_AXI_GP0_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), + M_AXI_GP0_wvalid => processing_system7_0_M_AXI_GP0_WVALID, + S_AXI_ACP_araddr(31 downto 0) => AXI_Intercon_M00_AXI2_ARADDR(31 downto 0), + S_AXI_ACP_arburst(1 downto 0) => AXI_Intercon_M00_AXI2_ARBURST(1 downto 0), + S_AXI_ACP_arcache(3 downto 0) => AXI_Intercon_M00_AXI2_ARCACHE(3 downto 0), + S_AXI_ACP_arlen(3 downto 0) => AXI_Intercon_M00_AXI2_ARLEN(3 downto 0), + S_AXI_ACP_arlock(1 downto 0) => AXI_Intercon_M00_AXI2_ARLOCK(1 downto 0), + S_AXI_ACP_arprot(2 downto 0) => AXI_Intercon_M00_AXI2_ARPROT(2 downto 0), + S_AXI_ACP_arqos(3 downto 0) => AXI_Intercon_M00_AXI2_ARQOS(3 downto 0), + S_AXI_ACP_arready => AXI_Intercon_M00_AXI2_ARREADY, + S_AXI_ACP_arsize(2 downto 0) => AXI_Intercon_M00_AXI2_ARSIZE(2 downto 0), + S_AXI_ACP_arvalid => AXI_Intercon_M00_AXI2_ARVALID, + S_AXI_ACP_awaddr(31 downto 0) => AXI_Intercon_M00_AXI2_AWADDR(31 downto 0), + S_AXI_ACP_awburst(1 downto 0) => AXI_Intercon_M00_AXI2_AWBURST(1 downto 0), + S_AXI_ACP_awcache(3 downto 0) => AXI_Intercon_M00_AXI2_AWCACHE(3 downto 0), + S_AXI_ACP_awlen(3 downto 0) => AXI_Intercon_M00_AXI2_AWLEN(3 downto 0), + S_AXI_ACP_awlock(1 downto 0) => AXI_Intercon_M00_AXI2_AWLOCK(1 downto 0), + S_AXI_ACP_awprot(2 downto 0) => AXI_Intercon_M00_AXI2_AWPROT(2 downto 0), + S_AXI_ACP_awqos(3 downto 0) => AXI_Intercon_M00_AXI2_AWQOS(3 downto 0), + S_AXI_ACP_awready => AXI_Intercon_M00_AXI2_AWREADY, + S_AXI_ACP_awsize(2 downto 0) => AXI_Intercon_M00_AXI2_AWSIZE(2 downto 0), + S_AXI_ACP_awvalid => AXI_Intercon_M00_AXI2_AWVALID, + S_AXI_ACP_bready => AXI_Intercon_M00_AXI2_BREADY, + S_AXI_ACP_bresp(1 downto 0) => AXI_Intercon_M00_AXI2_BRESP(1 downto 0), + S_AXI_ACP_bvalid => AXI_Intercon_M00_AXI2_BVALID, + S_AXI_ACP_rdata(63 downto 0) => AXI_Intercon_M00_AXI2_RDATA(63 downto 0), + S_AXI_ACP_rlast => AXI_Intercon_M00_AXI2_RLAST, + S_AXI_ACP_rready => AXI_Intercon_M00_AXI2_RREADY, + S_AXI_ACP_rresp(1 downto 0) => AXI_Intercon_M00_AXI2_RRESP(1 downto 0), + S_AXI_ACP_rvalid => AXI_Intercon_M00_AXI2_RVALID, + S_AXI_ACP_wdata(63 downto 0) => AXI_Intercon_M00_AXI2_WDATA(63 downto 0), + S_AXI_ACP_wlast => AXI_Intercon_M00_AXI2_WLAST, + S_AXI_ACP_wready => AXI_Intercon_M00_AXI2_WREADY, + S_AXI_ACP_wstrb(7 downto 0) => AXI_Intercon_M00_AXI2_WSTRB(7 downto 0), + S_AXI_ACP_wvalid => AXI_Intercon_M00_AXI2_WVALID, + S_AXI_HP0_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), + S_AXI_HP0_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), + S_AXI_HP0_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), + S_AXI_HP0_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), + S_AXI_HP0_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), + S_AXI_HP0_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), + S_AXI_HP0_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), + S_AXI_HP0_arready => axi_mem_intercon_M00_AXI_ARREADY, + S_AXI_HP0_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), + S_AXI_HP0_arvalid => axi_mem_intercon_M00_AXI_ARVALID, + S_AXI_HP0_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), + S_AXI_HP0_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), + S_AXI_HP0_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), + S_AXI_HP0_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), + S_AXI_HP0_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), + S_AXI_HP0_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), + S_AXI_HP0_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), + S_AXI_HP0_awready => axi_mem_intercon_M00_AXI_AWREADY, + S_AXI_HP0_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), + S_AXI_HP0_awvalid => axi_mem_intercon_M00_AXI_AWVALID, + S_AXI_HP0_bready => axi_mem_intercon_M00_AXI_BREADY, + S_AXI_HP0_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), + S_AXI_HP0_bvalid => axi_mem_intercon_M00_AXI_BVALID, + S_AXI_HP0_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), + S_AXI_HP0_rlast => axi_mem_intercon_M00_AXI_RLAST, + S_AXI_HP0_rready => axi_mem_intercon_M00_AXI_RREADY, + S_AXI_HP0_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), + S_AXI_HP0_rvalid => axi_mem_intercon_M00_AXI_RVALID, + S_AXI_HP0_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), + S_AXI_HP0_wlast => axi_mem_intercon_M00_AXI_WLAST, + S_AXI_HP0_wready => axi_mem_intercon_M00_AXI_WREADY, + S_AXI_HP0_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), + S_AXI_HP0_wvalid => axi_mem_intercon_M00_AXI_WVALID, + peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0) + ); +VideoSubsystem: entity work.VideoSubsystem_imp_RHI5N8 + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + ARESETN => rst_ps7_0_100M_peripheral_aresetn(0), + M_AXI_araddr(31 downto 0) => VideoSubsystem_M_AXI_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => VideoSubsystem_M_AXI_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => VideoSubsystem_M_AXI_ARCACHE(3 downto 0), + M_AXI_arid(0) => VideoSubsystem_M_AXI_ARID(0), + M_AXI_arlen(3 downto 0) => VideoSubsystem_M_AXI_ARLEN(3 downto 0), + M_AXI_arprot(2 downto 0) => VideoSubsystem_M_AXI_ARPROT(2 downto 0), + M_AXI_arready => VideoSubsystem_M_AXI_ARREADY, + M_AXI_arsize(2 downto 0) => VideoSubsystem_M_AXI_ARSIZE(2 downto 0), + M_AXI_arvalid => VideoSubsystem_M_AXI_ARVALID, + M_AXI_awaddr(31 downto 0) => VideoSubsystem_M_AXI_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => VideoSubsystem_M_AXI_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => VideoSubsystem_M_AXI_AWCACHE(3 downto 0), + M_AXI_awid(0) => VideoSubsystem_M_AXI_AWID(0), + M_AXI_awlen(3 downto 0) => VideoSubsystem_M_AXI_AWLEN(3 downto 0), + M_AXI_awprot(2 downto 0) => VideoSubsystem_M_AXI_AWPROT(2 downto 0), + M_AXI_awready => VideoSubsystem_M_AXI_AWREADY, + M_AXI_awsize(2 downto 0) => VideoSubsystem_M_AXI_AWSIZE(2 downto 0), + M_AXI_awvalid => VideoSubsystem_M_AXI_AWVALID, + M_AXI_bid(0) => VideoSubsystem_M_AXI_BID(0), + M_AXI_bready => VideoSubsystem_M_AXI_BREADY, + M_AXI_bresp(1 downto 0) => VideoSubsystem_M_AXI_BRESP(1 downto 0), + M_AXI_bvalid => VideoSubsystem_M_AXI_BVALID, + M_AXI_rdata(31 downto 0) => VideoSubsystem_M_AXI_RDATA(31 downto 0), + M_AXI_rid(0) => VideoSubsystem_M_AXI_RID(0), + M_AXI_rlast => VideoSubsystem_M_AXI_RLAST, + M_AXI_rready => VideoSubsystem_M_AXI_RREADY, + M_AXI_rresp(1 downto 0) => VideoSubsystem_M_AXI_RRESP(1 downto 0), + M_AXI_rvalid => VideoSubsystem_M_AXI_RVALID, + M_AXI_wdata(31 downto 0) => VideoSubsystem_M_AXI_WDATA(31 downto 0), + M_AXI_wlast => VideoSubsystem_M_AXI_WLAST, + M_AXI_wready => VideoSubsystem_M_AXI_WREADY, + M_AXI_wstrb(3 downto 0) => VideoSubsystem_M_AXI_WSTRB(3 downto 0), + M_AXI_wvalid => VideoSubsystem_M_AXI_WVALID, + S_AXIL1_araddr(31 downto 0) => S_AXIL1_1_ARADDR(31 downto 0), + S_AXIL1_arready => S_AXIL1_1_ARREADY, + S_AXIL1_arvalid => S_AXIL1_1_ARVALID, + S_AXIL1_awaddr(31 downto 0) => S_AXIL1_1_AWADDR(31 downto 0), + S_AXIL1_awready => S_AXIL1_1_AWREADY, + S_AXIL1_awvalid => S_AXIL1_1_AWVALID, + S_AXIL1_bready => S_AXIL1_1_BREADY, + S_AXIL1_bresp(1 downto 0) => S_AXIL1_1_BRESP(1 downto 0), + S_AXIL1_bvalid => S_AXIL1_1_BVALID, + S_AXIL1_rdata(31 downto 0) => S_AXIL1_1_RDATA(31 downto 0), + S_AXIL1_rready => S_AXIL1_1_RREADY, + S_AXIL1_rresp(1 downto 0) => S_AXIL1_1_RRESP(1 downto 0), + S_AXIL1_rvalid => S_AXIL1_1_RVALID, + S_AXIL1_wdata(31 downto 0) => S_AXIL1_1_WDATA(31 downto 0), + S_AXIL1_wready => S_AXIL1_1_WREADY, + S_AXIL1_wstrb(3 downto 0) => S_AXIL1_1_WSTRB(3 downto 0), + S_AXIL1_wvalid => S_AXIL1_1_WVALID, + S_AXIL_araddr(31 downto 0) => S_AXIL_1_ARADDR(31 downto 0), + S_AXIL_arready => S_AXIL_1_ARREADY, + S_AXIL_arvalid => S_AXIL_1_ARVALID, + S_AXIL_awaddr(31 downto 0) => S_AXIL_1_AWADDR(31 downto 0), + S_AXIL_awready => S_AXIL_1_AWREADY, + S_AXIL_awvalid => S_AXIL_1_AWVALID, + S_AXIL_bready => S_AXIL_1_BREADY, + S_AXIL_bresp(1 downto 0) => S_AXIL_1_BRESP(1 downto 0), + S_AXIL_bvalid => S_AXIL_1_BVALID, + S_AXIL_rdata(31 downto 0) => S_AXIL_1_RDATA(31 downto 0), + S_AXIL_rready => S_AXIL_1_RREADY, + S_AXIL_rresp(1 downto 0) => S_AXIL_1_RRESP(1 downto 0), + S_AXIL_rvalid => S_AXIL_1_RVALID, + S_AXIL_wdata(31 downto 0) => S_AXIL_1_WDATA(31 downto 0), + S_AXIL_wready => S_AXIL_1_WREADY, + S_AXIL_wstrb(3 downto 0) => S_AXIL_1_WSTRB(3 downto 0), + S_AXIL_wvalid => S_AXIL_1_WVALID, + VS2MM_INTERRUPT => VideoSubsystem_VS2MM_INTERRUPT + ); +ZYNQ_BASE: entity work.ZYNQ_BASE_imp_1TRJPP2 + port map ( + BUTTON_0(3 downto 0) => BUTTON_0_1(3 downto 0), + HDMI_CLK_N_0 => zynq_base_hdmi_0_HDMI_CLK_N, + HDMI_CLK_P_0 => zynq_base_hdmi_0_HDMI_CLK_P, + HDMI_DATA_N_0(2 downto 0) => zynq_base_hdmi_0_HDMI_DATA_N(2 downto 0), + HDMI_DATA_P_0(2 downto 0) => zynq_base_hdmi_0_HDMI_DATA_P(2 downto 0), + LED_0(3 downto 0) => zynq_base_hdmi_0_LED(3 downto 0), + M_AXI_ACLK => processing_system7_0_FCLK_CLK0, + M_AXI_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0), + M_AXI_araddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0), + M_AXI_arid(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARID(3 downto 0), + M_AXI_arlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0), + M_AXI_arprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0), + M_AXI_arready => zynq_base_hdmi_0_M_AXI_ARREADY, + M_AXI_arsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0), + M_AXI_arvalid => zynq_base_hdmi_0_M_AXI_ARVALID, + M_AXI_awaddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0), + M_AXI_awlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0), + M_AXI_awprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0), + M_AXI_awready => zynq_base_hdmi_0_M_AXI_AWREADY, + M_AXI_awsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0), + M_AXI_awvalid => zynq_base_hdmi_0_M_AXI_AWVALID, + M_AXI_bready => zynq_base_hdmi_0_M_AXI_BREADY, + M_AXI_bresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0), + M_AXI_bvalid => zynq_base_hdmi_0_M_AXI_BVALID, + M_AXI_rdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0), + M_AXI_rid(3 downto 0) => zynq_base_hdmi_0_M_AXI_RID(3 downto 0), + M_AXI_rlast => zynq_base_hdmi_0_M_AXI_RLAST, + M_AXI_rready => zynq_base_hdmi_0_M_AXI_RREADY, + M_AXI_rresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0), + M_AXI_rvalid => zynq_base_hdmi_0_M_AXI_RVALID, + M_AXI_wdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0), + M_AXI_wlast => zynq_base_hdmi_0_M_AXI_WLAST, + M_AXI_wready => zynq_base_hdmi_0_M_AXI_WREADY, + M_AXI_wstrb(3 downto 0) => zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0), + M_AXI_wvalid => zynq_base_hdmi_0_M_AXI_WVALID, + RGB_LED_0(5 downto 0) => zynq_base_hdmi_0_RGB_LED(5 downto 0), + SWITCH_0(3 downto 0) => SWITCH_0_1(3 downto 0), + S_AXIL_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0), + S_AXIL_arready => ps7_0_axi_periph_M00_AXI_ARREADY, + S_AXIL_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID, + S_AXIL_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0), + S_AXIL_awready => ps7_0_axi_periph_M00_AXI_AWREADY, + S_AXIL_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID, + S_AXIL_bready => ps7_0_axi_periph_M00_AXI_BREADY, + S_AXIL_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), + S_AXIL_bvalid => ps7_0_axi_periph_M00_AXI_BVALID, + S_AXIL_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), + S_AXIL_rready => ps7_0_axi_periph_M00_AXI_RREADY, + S_AXIL_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), + S_AXIL_rvalid => ps7_0_axi_periph_M00_AXI_RVALID, + S_AXIL_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), + S_AXIL_wready => ps7_0_axi_periph_M00_AXI_WREADY, + S_AXIL_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), + S_AXIL_wvalid => ps7_0_axi_periph_M00_AXI_WVALID, + VIDEO_CLK => processing_system7_0_FCLK_CLK3, + VIDEO_INTERRUPT => zynq_base_hdmi_0_VIDEO_INTERRUPT + ); +end STRUCTURE; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/synth/design_3.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/synth/design_3.vhd new file mode 100644 index 0000000..5f98066 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_3/synth/design_3.vhd @@ -0,0 +1,6016 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +--Date : Tue Dec 10 18:59:40 2024 +--Host : BiermannSurface running 64-bit major release (build 9200) +--Command : generate_target design_3.bd +--Design : design_3 +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity PS_imp_Z714CR is + port ( + DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_cas_n : inout STD_LOGIC; + DDR_ck_n : inout STD_LOGIC; + DDR_ck_p : inout STD_LOGIC; + DDR_cke : inout STD_LOGIC; + DDR_cs_n : inout STD_LOGIC; + DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_odt : inout STD_LOGIC; + DDR_ras_n : inout STD_LOGIC; + DDR_reset_n : inout STD_LOGIC; + DDR_we_n : inout STD_LOGIC; + FCLK_CLK0 : out STD_LOGIC; + FCLK_CLK3 : out STD_LOGIC; + FIXED_IO_ddr_vrn : inout STD_LOGIC; + FIXED_IO_ddr_vrp : inout STD_LOGIC; + FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + FIXED_IO_ps_clk : inout STD_LOGIC; + FIXED_IO_ps_porb : inout STD_LOGIC; + FIXED_IO_ps_srstb : inout STD_LOGIC; + In0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + In1 : in STD_LOGIC; + M_AXI_GP0_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_arready : in STD_LOGIC; + M_AXI_GP0_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_arvalid : out STD_LOGIC; + M_AXI_GP0_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_awready : in STD_LOGIC; + M_AXI_GP0_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_awvalid : out STD_LOGIC; + M_AXI_GP0_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_bready : out STD_LOGIC; + M_AXI_GP0_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_bvalid : in STD_LOGIC; + M_AXI_GP0_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_rlast : in STD_LOGIC; + M_AXI_GP0_rready : out STD_LOGIC; + M_AXI_GP0_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_rvalid : in STD_LOGIC; + M_AXI_GP0_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_wlast : out STD_LOGIC; + M_AXI_GP0_wready : in STD_LOGIC; + M_AXI_GP0_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_wvalid : out STD_LOGIC; + S_AXI_ACP_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_arready : out STD_LOGIC; + S_AXI_ACP_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_arvalid : in STD_LOGIC; + S_AXI_ACP_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_awready : out STD_LOGIC; + S_AXI_ACP_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_awvalid : in STD_LOGIC; + S_AXI_ACP_bready : in STD_LOGIC; + S_AXI_ACP_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_bvalid : out STD_LOGIC; + S_AXI_ACP_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_rlast : out STD_LOGIC; + S_AXI_ACP_rready : in STD_LOGIC; + S_AXI_ACP_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_rvalid : out STD_LOGIC; + S_AXI_ACP_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_wlast : in STD_LOGIC; + S_AXI_ACP_wready : out STD_LOGIC; + S_AXI_ACP_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_ACP_wvalid : in STD_LOGIC; + S_AXI_HP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_arready : out STD_LOGIC; + S_AXI_HP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_arvalid : in STD_LOGIC; + S_AXI_HP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_awready : out STD_LOGIC; + S_AXI_HP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_awvalid : in STD_LOGIC; + S_AXI_HP0_bready : in STD_LOGIC; + S_AXI_HP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_bvalid : out STD_LOGIC; + S_AXI_HP0_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_rlast : out STD_LOGIC; + S_AXI_HP0_rready : in STD_LOGIC; + S_AXI_HP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_rvalid : out STD_LOGIC; + S_AXI_HP0_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_wlast : in STD_LOGIC; + S_AXI_HP0_wready : out STD_LOGIC; + S_AXI_HP0_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_wvalid : in STD_LOGIC; + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end PS_imp_Z714CR; + +architecture STRUCTURE of PS_imp_Z714CR is + component design_3_processing_system7_0_0 is + port ( + SDIO0_WP : in STD_LOGIC; + TTC0_WAVE0_OUT : out STD_LOGIC; + TTC0_WAVE1_OUT : out STD_LOGIC; + TTC0_WAVE2_OUT : out STD_LOGIC; + USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); + USB0_VBUS_PWRSELECT : out STD_LOGIC; + USB0_VBUS_PWRFAULT : in STD_LOGIC; + M_AXI_GP0_ARVALID : out STD_LOGIC; + M_AXI_GP0_AWVALID : out STD_LOGIC; + M_AXI_GP0_BREADY : out STD_LOGIC; + M_AXI_GP0_RREADY : out STD_LOGIC; + M_AXI_GP0_WLAST : out STD_LOGIC; + M_AXI_GP0_WVALID : out STD_LOGIC; + M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ACLK : in STD_LOGIC; + M_AXI_GP0_ARREADY : in STD_LOGIC; + M_AXI_GP0_AWREADY : in STD_LOGIC; + M_AXI_GP0_BVALID : in STD_LOGIC; + M_AXI_GP0_RLAST : in STD_LOGIC; + M_AXI_GP0_RVALID : in STD_LOGIC; + M_AXI_GP0_WREADY : in STD_LOGIC; + M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_ARREADY : out STD_LOGIC; + S_AXI_ACP_AWREADY : out STD_LOGIC; + S_AXI_ACP_BVALID : out STD_LOGIC; + S_AXI_ACP_RLAST : out STD_LOGIC; + S_AXI_ACP_RVALID : out STD_LOGIC; + S_AXI_ACP_WREADY : out STD_LOGIC; + S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_ACLK : in STD_LOGIC; + S_AXI_ACP_ARVALID : in STD_LOGIC; + S_AXI_ACP_AWVALID : in STD_LOGIC; + S_AXI_ACP_BREADY : in STD_LOGIC; + S_AXI_ACP_RREADY : in STD_LOGIC; + S_AXI_ACP_WLAST : in STD_LOGIC; + S_AXI_ACP_WVALID : in STD_LOGIC; + S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); + S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); + S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_ARREADY : out STD_LOGIC; + S_AXI_HP0_AWREADY : out STD_LOGIC; + S_AXI_HP0_BVALID : out STD_LOGIC; + S_AXI_HP0_RLAST : out STD_LOGIC; + S_AXI_HP0_RVALID : out STD_LOGIC; + S_AXI_HP0_WREADY : out STD_LOGIC; + S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_ACLK : in STD_LOGIC; + S_AXI_HP0_ARVALID : in STD_LOGIC; + S_AXI_HP0_AWVALID : in STD_LOGIC; + S_AXI_HP0_BREADY : in STD_LOGIC; + S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_RREADY : in STD_LOGIC; + S_AXI_HP0_WLAST : in STD_LOGIC; + S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_WVALID : in STD_LOGIC; + S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 ); + FCLK_CLK0 : out STD_LOGIC; + FCLK_CLK1 : out STD_LOGIC; + FCLK_CLK2 : out STD_LOGIC; + FCLK_CLK3 : out STD_LOGIC; + FCLK_RESET0_N : out STD_LOGIC; + MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + DDR_CAS_n : inout STD_LOGIC; + DDR_CKE : inout STD_LOGIC; + DDR_Clk_n : inout STD_LOGIC; + DDR_Clk : inout STD_LOGIC; + DDR_CS_n : inout STD_LOGIC; + DDR_DRSTB : inout STD_LOGIC; + DDR_ODT : inout STD_LOGIC; + DDR_RAS_n : inout STD_LOGIC; + DDR_WEB : inout STD_LOGIC; + DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_VRN : inout STD_LOGIC; + DDR_VRP : inout STD_LOGIC; + DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + PS_SRSTB : inout STD_LOGIC; + PS_CLK : inout STD_LOGIC; + PS_PORB : inout STD_LOGIC + ); + end component design_3_processing_system7_0_0; + component design_3_rst_ps7_0_100M_0 is + port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component design_3_rst_ps7_0_100M_0; + component design_3_xlconcat_0_0 is + port ( + In0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + In1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + dout : out STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component design_3_xlconcat_0_0; + component design_3_xlconstant_0_0 is + port ( + dout : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component design_3_xlconstant_0_0; + signal In0_1 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal In1_1 : STD_LOGIC; + signal S_AXI_ACP_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXI_ACP_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_ARREADY : STD_LOGIC; + signal S_AXI_ACP_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_1_ARVALID : STD_LOGIC; + signal S_AXI_ACP_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXI_ACP_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_1_AWREADY : STD_LOGIC; + signal S_AXI_ACP_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_1_AWVALID : STD_LOGIC; + signal S_AXI_ACP_1_BREADY : STD_LOGIC; + signal S_AXI_ACP_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_BVALID : STD_LOGIC; + signal S_AXI_ACP_1_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal S_AXI_ACP_1_RLAST : STD_LOGIC; + signal S_AXI_ACP_1_RREADY : STD_LOGIC; + signal S_AXI_ACP_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_1_RVALID : STD_LOGIC; + signal S_AXI_ACP_1_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal S_AXI_ACP_1_WLAST : STD_LOGIC; + signal S_AXI_ACP_1_WREADY : STD_LOGIC; + signal S_AXI_ACP_1_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal S_AXI_ACP_1_WVALID : STD_LOGIC; + signal S_AXI_ACP_2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXI_ACP_2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_2_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_ARREADY : STD_LOGIC; + signal S_AXI_ACP_2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_2_ARVALID : STD_LOGIC; + signal S_AXI_ACP_2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXI_ACP_2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_2_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXI_ACP_2_AWREADY : STD_LOGIC; + signal S_AXI_ACP_2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S_AXI_ACP_2_AWVALID : STD_LOGIC; + signal S_AXI_ACP_2_BREADY : STD_LOGIC; + signal S_AXI_ACP_2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_BVALID : STD_LOGIC; + signal S_AXI_ACP_2_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal S_AXI_ACP_2_RLAST : STD_LOGIC; + signal S_AXI_ACP_2_RREADY : STD_LOGIC; + signal S_AXI_ACP_2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXI_ACP_2_RVALID : STD_LOGIC; + signal S_AXI_ACP_2_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal S_AXI_ACP_2_WLAST : STD_LOGIC; + signal S_AXI_ACP_2_WREADY : STD_LOGIC; + signal S_AXI_ACP_2_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal S_AXI_ACP_2_WVALID : STD_LOGIC; + signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_DDR_CAS_N : STD_LOGIC; + signal processing_system7_0_DDR_CKE : STD_LOGIC; + signal processing_system7_0_DDR_CK_N : STD_LOGIC; + signal processing_system7_0_DDR_CK_P : STD_LOGIC; + signal processing_system7_0_DDR_CS_N : STD_LOGIC; + signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_ODT : STD_LOGIC; + signal processing_system7_0_DDR_RAS_N : STD_LOGIC; + signal processing_system7_0_DDR_RESET_N : STD_LOGIC; + signal processing_system7_0_DDR_WE_N : STD_LOGIC; + signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; + signal processing_system7_0_FCLK_CLK3 : STD_LOGIC; + signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC; + signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC; + signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC; + signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); + signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC; + signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC; + signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC; + signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; + signal NLW_processing_system7_0_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_processing_system7_0_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC; + signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_rst_ps7_0_100M_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); +begin + FCLK_CLK0 <= processing_system7_0_FCLK_CLK0; + FCLK_CLK3 <= processing_system7_0_FCLK_CLK3; + In0_1(0) <= In0(0); + In1_1 <= In1; + M_AXI_GP0_araddr(31 downto 0) <= processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0); + M_AXI_GP0_arburst(1 downto 0) <= processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0); + M_AXI_GP0_arcache(3 downto 0) <= processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0); + M_AXI_GP0_arid(11 downto 0) <= processing_system7_0_M_AXI_GP0_ARID(11 downto 0); + M_AXI_GP0_arlen(3 downto 0) <= processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0); + M_AXI_GP0_arlock(1 downto 0) <= processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0); + M_AXI_GP0_arprot(2 downto 0) <= processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0); + M_AXI_GP0_arqos(3 downto 0) <= processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0); + M_AXI_GP0_arsize(2 downto 0) <= processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0); + M_AXI_GP0_arvalid <= processing_system7_0_M_AXI_GP0_ARVALID; + M_AXI_GP0_awaddr(31 downto 0) <= processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0); + M_AXI_GP0_awburst(1 downto 0) <= processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0); + M_AXI_GP0_awcache(3 downto 0) <= processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0); + M_AXI_GP0_awid(11 downto 0) <= processing_system7_0_M_AXI_GP0_AWID(11 downto 0); + M_AXI_GP0_awlen(3 downto 0) <= processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0); + M_AXI_GP0_awlock(1 downto 0) <= processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0); + M_AXI_GP0_awprot(2 downto 0) <= processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0); + M_AXI_GP0_awqos(3 downto 0) <= processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0); + M_AXI_GP0_awsize(2 downto 0) <= processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0); + M_AXI_GP0_awvalid <= processing_system7_0_M_AXI_GP0_AWVALID; + M_AXI_GP0_bready <= processing_system7_0_M_AXI_GP0_BREADY; + M_AXI_GP0_rready <= processing_system7_0_M_AXI_GP0_RREADY; + M_AXI_GP0_wdata(31 downto 0) <= processing_system7_0_M_AXI_GP0_WDATA(31 downto 0); + M_AXI_GP0_wid(11 downto 0) <= processing_system7_0_M_AXI_GP0_WID(11 downto 0); + M_AXI_GP0_wlast <= processing_system7_0_M_AXI_GP0_WLAST; + M_AXI_GP0_wstrb(3 downto 0) <= processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0); + M_AXI_GP0_wvalid <= processing_system7_0_M_AXI_GP0_WVALID; + S_AXI_ACP_1_ARADDR(31 downto 0) <= S_AXI_HP0_araddr(31 downto 0); + S_AXI_ACP_1_ARBURST(1 downto 0) <= S_AXI_HP0_arburst(1 downto 0); + S_AXI_ACP_1_ARCACHE(3 downto 0) <= S_AXI_HP0_arcache(3 downto 0); + S_AXI_ACP_1_ARLEN(3 downto 0) <= S_AXI_HP0_arlen(3 downto 0); + S_AXI_ACP_1_ARLOCK(1 downto 0) <= S_AXI_HP0_arlock(1 downto 0); + S_AXI_ACP_1_ARPROT(2 downto 0) <= S_AXI_HP0_arprot(2 downto 0); + S_AXI_ACP_1_ARQOS(3 downto 0) <= S_AXI_HP0_arqos(3 downto 0); + S_AXI_ACP_1_ARSIZE(2 downto 0) <= S_AXI_HP0_arsize(2 downto 0); + S_AXI_ACP_1_ARVALID <= S_AXI_HP0_arvalid; + S_AXI_ACP_1_AWADDR(31 downto 0) <= S_AXI_HP0_awaddr(31 downto 0); + S_AXI_ACP_1_AWBURST(1 downto 0) <= S_AXI_HP0_awburst(1 downto 0); + S_AXI_ACP_1_AWCACHE(3 downto 0) <= S_AXI_HP0_awcache(3 downto 0); + S_AXI_ACP_1_AWLEN(3 downto 0) <= S_AXI_HP0_awlen(3 downto 0); + S_AXI_ACP_1_AWLOCK(1 downto 0) <= S_AXI_HP0_awlock(1 downto 0); + S_AXI_ACP_1_AWPROT(2 downto 0) <= S_AXI_HP0_awprot(2 downto 0); + S_AXI_ACP_1_AWQOS(3 downto 0) <= S_AXI_HP0_awqos(3 downto 0); + S_AXI_ACP_1_AWSIZE(2 downto 0) <= S_AXI_HP0_awsize(2 downto 0); + S_AXI_ACP_1_AWVALID <= S_AXI_HP0_awvalid; + S_AXI_ACP_1_BREADY <= S_AXI_HP0_bready; + S_AXI_ACP_1_RREADY <= S_AXI_HP0_rready; + S_AXI_ACP_1_WDATA(63 downto 0) <= S_AXI_HP0_wdata(63 downto 0); + S_AXI_ACP_1_WLAST <= S_AXI_HP0_wlast; + S_AXI_ACP_1_WSTRB(7 downto 0) <= S_AXI_HP0_wstrb(7 downto 0); + S_AXI_ACP_1_WVALID <= S_AXI_HP0_wvalid; + S_AXI_ACP_2_ARADDR(31 downto 0) <= S_AXI_ACP_araddr(31 downto 0); + S_AXI_ACP_2_ARBURST(1 downto 0) <= S_AXI_ACP_arburst(1 downto 0); + S_AXI_ACP_2_ARCACHE(3 downto 0) <= S_AXI_ACP_arcache(3 downto 0); + S_AXI_ACP_2_ARLEN(3 downto 0) <= S_AXI_ACP_arlen(3 downto 0); + S_AXI_ACP_2_ARLOCK(1 downto 0) <= S_AXI_ACP_arlock(1 downto 0); + S_AXI_ACP_2_ARPROT(2 downto 0) <= S_AXI_ACP_arprot(2 downto 0); + S_AXI_ACP_2_ARQOS(3 downto 0) <= S_AXI_ACP_arqos(3 downto 0); + S_AXI_ACP_2_ARSIZE(2 downto 0) <= S_AXI_ACP_arsize(2 downto 0); + S_AXI_ACP_2_ARVALID <= S_AXI_ACP_arvalid; + S_AXI_ACP_2_AWADDR(31 downto 0) <= S_AXI_ACP_awaddr(31 downto 0); + S_AXI_ACP_2_AWBURST(1 downto 0) <= S_AXI_ACP_awburst(1 downto 0); + S_AXI_ACP_2_AWCACHE(3 downto 0) <= S_AXI_ACP_awcache(3 downto 0); + S_AXI_ACP_2_AWLEN(3 downto 0) <= S_AXI_ACP_awlen(3 downto 0); + S_AXI_ACP_2_AWLOCK(1 downto 0) <= S_AXI_ACP_awlock(1 downto 0); + S_AXI_ACP_2_AWPROT(2 downto 0) <= S_AXI_ACP_awprot(2 downto 0); + S_AXI_ACP_2_AWQOS(3 downto 0) <= S_AXI_ACP_awqos(3 downto 0); + S_AXI_ACP_2_AWSIZE(2 downto 0) <= S_AXI_ACP_awsize(2 downto 0); + S_AXI_ACP_2_AWVALID <= S_AXI_ACP_awvalid; + S_AXI_ACP_2_BREADY <= S_AXI_ACP_bready; + S_AXI_ACP_2_RREADY <= S_AXI_ACP_rready; + S_AXI_ACP_2_WDATA(63 downto 0) <= S_AXI_ACP_wdata(63 downto 0); + S_AXI_ACP_2_WLAST <= S_AXI_ACP_wlast; + S_AXI_ACP_2_WSTRB(7 downto 0) <= S_AXI_ACP_wstrb(7 downto 0); + S_AXI_ACP_2_WVALID <= S_AXI_ACP_wvalid; + S_AXI_ACP_arready <= S_AXI_ACP_2_ARREADY; + S_AXI_ACP_awready <= S_AXI_ACP_2_AWREADY; + S_AXI_ACP_bresp(1 downto 0) <= S_AXI_ACP_2_BRESP(1 downto 0); + S_AXI_ACP_bvalid <= S_AXI_ACP_2_BVALID; + S_AXI_ACP_rdata(63 downto 0) <= S_AXI_ACP_2_RDATA(63 downto 0); + S_AXI_ACP_rlast <= S_AXI_ACP_2_RLAST; + S_AXI_ACP_rresp(1 downto 0) <= S_AXI_ACP_2_RRESP(1 downto 0); + S_AXI_ACP_rvalid <= S_AXI_ACP_2_RVALID; + S_AXI_ACP_wready <= S_AXI_ACP_2_WREADY; + S_AXI_HP0_arready <= S_AXI_ACP_1_ARREADY; + S_AXI_HP0_awready <= S_AXI_ACP_1_AWREADY; + S_AXI_HP0_bresp(1 downto 0) <= S_AXI_ACP_1_BRESP(1 downto 0); + S_AXI_HP0_bvalid <= S_AXI_ACP_1_BVALID; + S_AXI_HP0_rdata(63 downto 0) <= S_AXI_ACP_1_RDATA(63 downto 0); + S_AXI_HP0_rlast <= S_AXI_ACP_1_RLAST; + S_AXI_HP0_rresp(1 downto 0) <= S_AXI_ACP_1_RRESP(1 downto 0); + S_AXI_HP0_rvalid <= S_AXI_ACP_1_RVALID; + S_AXI_HP0_wready <= S_AXI_ACP_1_WREADY; + peripheral_aresetn(0) <= rst_ps7_0_100M_peripheral_aresetn(0); + processing_system7_0_M_AXI_GP0_ARREADY <= M_AXI_GP0_arready; + processing_system7_0_M_AXI_GP0_AWREADY <= M_AXI_GP0_awready; + processing_system7_0_M_AXI_GP0_BID(11 downto 0) <= M_AXI_GP0_bid(11 downto 0); + processing_system7_0_M_AXI_GP0_BRESP(1 downto 0) <= M_AXI_GP0_bresp(1 downto 0); + processing_system7_0_M_AXI_GP0_BVALID <= M_AXI_GP0_bvalid; + processing_system7_0_M_AXI_GP0_RDATA(31 downto 0) <= M_AXI_GP0_rdata(31 downto 0); + processing_system7_0_M_AXI_GP0_RID(11 downto 0) <= M_AXI_GP0_rid(11 downto 0); + processing_system7_0_M_AXI_GP0_RLAST <= M_AXI_GP0_rlast; + processing_system7_0_M_AXI_GP0_RRESP(1 downto 0) <= M_AXI_GP0_rresp(1 downto 0); + processing_system7_0_M_AXI_GP0_RVALID <= M_AXI_GP0_rvalid; + processing_system7_0_M_AXI_GP0_WREADY <= M_AXI_GP0_wready; +processing_system7_0: component design_3_processing_system7_0_0 + port map ( + DDR_Addr(14 downto 0) => DDR_addr(14 downto 0), + DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0), + DDR_CAS_n => DDR_cas_n, + DDR_CKE => DDR_cke, + DDR_CS_n => DDR_cs_n, + DDR_Clk => DDR_ck_p, + DDR_Clk_n => DDR_ck_n, + DDR_DM(3 downto 0) => DDR_dm(3 downto 0), + DDR_DQ(31 downto 0) => DDR_dq(31 downto 0), + DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0), + DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0), + DDR_DRSTB => DDR_reset_n, + DDR_ODT => DDR_odt, + DDR_RAS_n => DDR_ras_n, + DDR_VRN => FIXED_IO_ddr_vrn, + DDR_VRP => FIXED_IO_ddr_vrp, + DDR_WEB => DDR_we_n, + FCLK_CLK0 => processing_system7_0_FCLK_CLK0, + FCLK_CLK1 => NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED, + FCLK_CLK2 => NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED, + FCLK_CLK3 => processing_system7_0_FCLK_CLK3, + FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N, + IRQ_F2P(1 downto 0) => xlconcat_0_dout(1 downto 0), + MIO(53 downto 0) => FIXED_IO_mio(53 downto 0), + M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0, + M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), + M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), + M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), + M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), + M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), + M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), + M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), + M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), + M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY, + M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), + M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID, + M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), + M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), + M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), + M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), + M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), + M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), + M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), + M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), + M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY, + M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), + M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID, + M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), + M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY, + M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), + M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID, + M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), + M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), + M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST, + M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY, + M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), + M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID, + M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), + M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), + M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST, + M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY, + M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), + M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID, + PS_CLK => FIXED_IO_ps_clk, + PS_PORB => FIXED_IO_ps_porb, + PS_SRSTB => FIXED_IO_ps_srstb, + SDIO0_WP => xlconstant_0_dout(0), + S_AXI_ACP_ACLK => processing_system7_0_FCLK_CLK0, + S_AXI_ACP_ARADDR(31 downto 0) => S_AXI_ACP_2_ARADDR(31 downto 0), + S_AXI_ACP_ARBURST(1 downto 0) => S_AXI_ACP_2_ARBURST(1 downto 0), + S_AXI_ACP_ARCACHE(3 downto 0) => S_AXI_ACP_2_ARCACHE(3 downto 0), + S_AXI_ACP_ARID(2 downto 0) => B"000", + S_AXI_ACP_ARLEN(3 downto 0) => S_AXI_ACP_2_ARLEN(3 downto 0), + S_AXI_ACP_ARLOCK(1 downto 0) => S_AXI_ACP_2_ARLOCK(1 downto 0), + S_AXI_ACP_ARPROT(2 downto 0) => S_AXI_ACP_2_ARPROT(2 downto 0), + S_AXI_ACP_ARQOS(3 downto 0) => S_AXI_ACP_2_ARQOS(3 downto 0), + S_AXI_ACP_ARREADY => S_AXI_ACP_2_ARREADY, + S_AXI_ACP_ARSIZE(2 downto 0) => S_AXI_ACP_2_ARSIZE(2 downto 0), + S_AXI_ACP_ARUSER(4 downto 0) => B"00000", + S_AXI_ACP_ARVALID => S_AXI_ACP_2_ARVALID, + S_AXI_ACP_AWADDR(31 downto 0) => S_AXI_ACP_2_AWADDR(31 downto 0), + S_AXI_ACP_AWBURST(1 downto 0) => S_AXI_ACP_2_AWBURST(1 downto 0), + S_AXI_ACP_AWCACHE(3 downto 0) => S_AXI_ACP_2_AWCACHE(3 downto 0), + S_AXI_ACP_AWID(2 downto 0) => B"000", + S_AXI_ACP_AWLEN(3 downto 0) => S_AXI_ACP_2_AWLEN(3 downto 0), + S_AXI_ACP_AWLOCK(1 downto 0) => S_AXI_ACP_2_AWLOCK(1 downto 0), + S_AXI_ACP_AWPROT(2 downto 0) => S_AXI_ACP_2_AWPROT(2 downto 0), + S_AXI_ACP_AWQOS(3 downto 0) => S_AXI_ACP_2_AWQOS(3 downto 0), + S_AXI_ACP_AWREADY => S_AXI_ACP_2_AWREADY, + S_AXI_ACP_AWSIZE(2 downto 0) => S_AXI_ACP_2_AWSIZE(2 downto 0), + S_AXI_ACP_AWUSER(4 downto 0) => B"00000", + S_AXI_ACP_AWVALID => S_AXI_ACP_2_AWVALID, + S_AXI_ACP_BID(2 downto 0) => NLW_processing_system7_0_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), + S_AXI_ACP_BREADY => S_AXI_ACP_2_BREADY, + S_AXI_ACP_BRESP(1 downto 0) => S_AXI_ACP_2_BRESP(1 downto 0), + S_AXI_ACP_BVALID => S_AXI_ACP_2_BVALID, + S_AXI_ACP_RDATA(63 downto 0) => S_AXI_ACP_2_RDATA(63 downto 0), + S_AXI_ACP_RID(2 downto 0) => NLW_processing_system7_0_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), + S_AXI_ACP_RLAST => S_AXI_ACP_2_RLAST, + S_AXI_ACP_RREADY => S_AXI_ACP_2_RREADY, + S_AXI_ACP_RRESP(1 downto 0) => S_AXI_ACP_2_RRESP(1 downto 0), + S_AXI_ACP_RVALID => S_AXI_ACP_2_RVALID, + S_AXI_ACP_WDATA(63 downto 0) => S_AXI_ACP_2_WDATA(63 downto 0), + S_AXI_ACP_WID(2 downto 0) => B"000", + S_AXI_ACP_WLAST => S_AXI_ACP_2_WLAST, + S_AXI_ACP_WREADY => S_AXI_ACP_2_WREADY, + S_AXI_ACP_WSTRB(7 downto 0) => S_AXI_ACP_2_WSTRB(7 downto 0), + S_AXI_ACP_WVALID => S_AXI_ACP_2_WVALID, + S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0, + S_AXI_HP0_ARADDR(31 downto 0) => S_AXI_ACP_1_ARADDR(31 downto 0), + S_AXI_HP0_ARBURST(1 downto 0) => S_AXI_ACP_1_ARBURST(1 downto 0), + S_AXI_HP0_ARCACHE(3 downto 0) => S_AXI_ACP_1_ARCACHE(3 downto 0), + S_AXI_HP0_ARID(5 downto 0) => B"000000", + S_AXI_HP0_ARLEN(3 downto 0) => S_AXI_ACP_1_ARLEN(3 downto 0), + S_AXI_HP0_ARLOCK(1 downto 0) => S_AXI_ACP_1_ARLOCK(1 downto 0), + S_AXI_HP0_ARPROT(2 downto 0) => S_AXI_ACP_1_ARPROT(2 downto 0), + S_AXI_HP0_ARQOS(3 downto 0) => S_AXI_ACP_1_ARQOS(3 downto 0), + S_AXI_HP0_ARREADY => S_AXI_ACP_1_ARREADY, + S_AXI_HP0_ARSIZE(2 downto 0) => S_AXI_ACP_1_ARSIZE(2 downto 0), + S_AXI_HP0_ARVALID => S_AXI_ACP_1_ARVALID, + S_AXI_HP0_AWADDR(31 downto 0) => S_AXI_ACP_1_AWADDR(31 downto 0), + S_AXI_HP0_AWBURST(1 downto 0) => S_AXI_ACP_1_AWBURST(1 downto 0), + S_AXI_HP0_AWCACHE(3 downto 0) => S_AXI_ACP_1_AWCACHE(3 downto 0), + S_AXI_HP0_AWID(5 downto 0) => B"000000", + S_AXI_HP0_AWLEN(3 downto 0) => S_AXI_ACP_1_AWLEN(3 downto 0), + S_AXI_HP0_AWLOCK(1 downto 0) => S_AXI_ACP_1_AWLOCK(1 downto 0), + S_AXI_HP0_AWPROT(2 downto 0) => S_AXI_ACP_1_AWPROT(2 downto 0), + S_AXI_HP0_AWQOS(3 downto 0) => S_AXI_ACP_1_AWQOS(3 downto 0), + S_AXI_HP0_AWREADY => S_AXI_ACP_1_AWREADY, + S_AXI_HP0_AWSIZE(2 downto 0) => S_AXI_ACP_1_AWSIZE(2 downto 0), + S_AXI_HP0_AWVALID => S_AXI_ACP_1_AWVALID, + S_AXI_HP0_BID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), + S_AXI_HP0_BREADY => S_AXI_ACP_1_BREADY, + S_AXI_HP0_BRESP(1 downto 0) => S_AXI_ACP_1_BRESP(1 downto 0), + S_AXI_HP0_BVALID => S_AXI_ACP_1_BVALID, + S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), + S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP0_RDATA(63 downto 0) => S_AXI_ACP_1_RDATA(63 downto 0), + S_AXI_HP0_RDISSUECAP1_EN => '0', + S_AXI_HP0_RID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), + S_AXI_HP0_RLAST => S_AXI_ACP_1_RLAST, + S_AXI_HP0_RREADY => S_AXI_ACP_1_RREADY, + S_AXI_HP0_RRESP(1 downto 0) => S_AXI_ACP_1_RRESP(1 downto 0), + S_AXI_HP0_RVALID => S_AXI_ACP_1_RVALID, + S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), + S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP0_WDATA(63 downto 0) => S_AXI_ACP_1_WDATA(63 downto 0), + S_AXI_HP0_WID(5 downto 0) => B"000000", + S_AXI_HP0_WLAST => S_AXI_ACP_1_WLAST, + S_AXI_HP0_WREADY => S_AXI_ACP_1_WREADY, + S_AXI_HP0_WRISSUECAP1_EN => '0', + S_AXI_HP0_WSTRB(7 downto 0) => S_AXI_ACP_1_WSTRB(7 downto 0), + S_AXI_HP0_WVALID => S_AXI_ACP_1_WVALID, + TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED, + TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED, + TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED, + USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), + USB0_VBUS_PWRFAULT => '0', + USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED + ); +rst_ps7_0_100M: component design_3_rst_ps7_0_100M_0 + port map ( + aux_reset_in => '1', + bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0), + dcm_locked => '1', + ext_reset_in => processing_system7_0_FCLK_RESET0_N, + interconnect_aresetn(0) => NLW_rst_ps7_0_100M_interconnect_aresetn_UNCONNECTED(0), + mb_debug_sys_rst => '0', + mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED, + peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0), + peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0), + slowest_sync_clk => processing_system7_0_FCLK_CLK0 + ); +xlconcat_0: component design_3_xlconcat_0_0 + port map ( + In0(0) => In0_1(0), + In1(0) => In1_1, + dout(1 downto 0) => xlconcat_0_dout(1 downto 0) + ); +xlconstant_0: component design_3_xlconstant_0_0 + port map ( + dout(0) => xlconstant_0_dout(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity VideoSubsystem_imp_RHI5N8 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_AXIL1_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL1_arready : out STD_LOGIC; + S_AXIL1_arvalid : in STD_LOGIC; + S_AXIL1_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL1_awready : out STD_LOGIC; + S_AXIL1_awvalid : in STD_LOGIC; + S_AXIL1_bready : in STD_LOGIC; + S_AXIL1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL1_bvalid : out STD_LOGIC; + S_AXIL1_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL1_rready : in STD_LOGIC; + S_AXIL1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL1_rvalid : out STD_LOGIC; + S_AXIL1_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL1_wready : out STD_LOGIC; + S_AXIL1_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL1_wvalid : in STD_LOGIC; + S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_arready : out STD_LOGIC; + S_AXIL_arvalid : in STD_LOGIC; + S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_awready : out STD_LOGIC; + S_AXIL_awvalid : in STD_LOGIC; + S_AXIL_bready : in STD_LOGIC; + S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_bvalid : out STD_LOGIC; + S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_rready : in STD_LOGIC; + S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_rvalid : out STD_LOGIC; + S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_wready : out STD_LOGIC; + S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_wvalid : in STD_LOGIC; + VS2MM_INTERRUPT : out STD_LOGIC + ); +end VideoSubsystem_imp_RHI5N8; + +architecture STRUCTURE of VideoSubsystem_imp_RHI5N8 is + component design_3_axis_downsizer_0_0 is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC + ); + end component design_3_axis_downsizer_0_0; + component design_3_axis_upsizer_0_0 is + port ( + AXIS_ACLK : in STD_LOGIC; + AXIS_ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC + ); + end component design_3_axis_upsizer_0_0; + component design_3_axis_linemem_single_0_0 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_tlast : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tuser : out STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + end component design_3_axis_linemem_single_0_0; + component design_3_axis_video_filter_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC; + S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 14 downto 0 ); + S_AXIL_AWVALID : in STD_LOGIC; + S_AXIL_AWREADY : out STD_LOGIC; + S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_WVALID : in STD_LOGIC; + S_AXIL_WREADY : out STD_LOGIC; + S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_BVALID : out STD_LOGIC; + S_AXIL_BREADY : in STD_LOGIC; + S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 14 downto 0 ); + S_AXIL_ARVALID : in STD_LOGIC; + S_AXIL_ARREADY : out STD_LOGIC; + S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_RVALID : out STD_LOGIC; + S_AXIL_RREADY : in STD_LOGIC; + S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component design_3_axis_video_filter_0_0; + component design_3_axi_2d_mmvs_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M_AXIS_TVALID : out STD_LOGIC; + M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXIS_TLAST : out STD_LOGIC; + M_AXIS_TREADY : in STD_LOGIC; + M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ); + MM2VS_INTERRUPT : out STD_LOGIC; + S_AXIS_TVALID : in STD_LOGIC; + S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIS_TLAST : in STD_LOGIC; + S_AXIS_TREADY : out STD_LOGIC; + S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ); + VS2MM_INTERRUPT : out STD_LOGIC; + S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIL_AWVALID : in STD_LOGIC; + S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_WVALID : in STD_LOGIC; + S_AXIL_WREADY : out STD_LOGIC; + S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_BVALID : out STD_LOGIC; + S_AXIL_AWREADY : out STD_LOGIC; + S_AXIL_BREADY : in STD_LOGIC; + S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIL_ARVALID : in STD_LOGIC; + S_AXIL_RREADY : in STD_LOGIC; + S_AXIL_ARREADY : out STD_LOGIC; + S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_RVALID : out STD_LOGIC; + M_AXI_ARREADY : in STD_LOGIC; + M_AXI_ARVALID : out STD_LOGIC; + M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_RREADY : out STD_LOGIC; + M_AXI_RVALID : in STD_LOGIC; + M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_RLAST : in STD_LOGIC; + M_AXI_AWREADY : in STD_LOGIC; + M_AXI_AWVALID : out STD_LOGIC; + M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WREADY : in STD_LOGIC; + M_AXI_WVALID : out STD_LOGIC; + M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WLAST : out STD_LOGIC; + M_AXI_WID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_BREADY : out STD_LOGIC; + M_AXI_BVALID : in STD_LOGIC; + M_AXI_BID : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component design_3_axi_2d_mmvs_0_0; + signal Net : STD_LOGIC; + signal Net1 : STD_LOGIC; + signal S_AXIL1_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_ARREADY : STD_LOGIC; + signal S_AXIL1_1_ARVALID : STD_LOGIC; + signal S_AXIL1_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_AWREADY : STD_LOGIC; + signal S_AXIL1_1_AWVALID : STD_LOGIC; + signal S_AXIL1_1_BREADY : STD_LOGIC; + signal S_AXIL1_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL1_1_BVALID : STD_LOGIC; + signal S_AXIL1_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_RREADY : STD_LOGIC; + signal S_AXIL1_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL1_1_RVALID : STD_LOGIC; + signal S_AXIL1_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_WREADY : STD_LOGIC; + signal S_AXIL1_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL1_1_WVALID : STD_LOGIC; + signal S_AXIL_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_ARREADY : STD_LOGIC; + signal S_AXIL_1_ARVALID : STD_LOGIC; + signal S_AXIL_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_AWREADY : STD_LOGIC; + signal S_AXIL_1_AWVALID : STD_LOGIC; + signal S_AXIL_1_BREADY : STD_LOGIC; + signal S_AXIL_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL_1_BVALID : STD_LOGIC; + signal S_AXIL_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_RREADY : STD_LOGIC; + signal S_AXIL_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL_1_RVALID : STD_LOGIC; + signal S_AXIL_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_WREADY : STD_LOGIC; + signal S_AXIL_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL_1_WVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXIS_TLAST : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXIS_TREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXIS_TVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_ARVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_AWVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXI_BREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_BVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_2d_mmvs_0_M_AXI_RLAST : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_RREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_RVALID : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_WLAST : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_WREADY : STD_LOGIC; + signal axi_2d_mmvs_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_2d_mmvs_0_M_AXI_WVALID : STD_LOGIC; + signal axi_2d_mmvs_0_VS2MM_INTERRUPT : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TUSER : STD_LOGIC; + signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_linemem_single_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal axis_linemem_single_0_m_axis_TLAST : STD_LOGIC; + signal axis_linemem_single_0_m_axis_TREADY : STD_LOGIC; + signal axis_linemem_single_0_m_axis_TUSER : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axis_linemem_single_0_m_axis_TVALID : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC; + signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_video_filter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axis_video_filter_0_M_AXIS_TLAST : STD_LOGIC; + signal axis_video_filter_0_M_AXIS_TREADY : STD_LOGIC; + signal axis_video_filter_0_M_AXIS_TUSER : STD_LOGIC; + signal axis_video_filter_0_M_AXIS_TVALID : STD_LOGIC; + signal NLW_axi_2d_mmvs_0_MM2VS_INTERRUPT_UNCONNECTED : STD_LOGIC; + signal NLW_axi_2d_mmvs_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); +begin + M_AXI_araddr(31 downto 0) <= axi_2d_mmvs_0_M_AXI_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= axi_2d_mmvs_0_M_AXI_ARBURST(1 downto 0); + M_AXI_arcache(3 downto 0) <= axi_2d_mmvs_0_M_AXI_ARCACHE(3 downto 0); + M_AXI_arid(0) <= axi_2d_mmvs_0_M_AXI_ARID(0); + M_AXI_arlen(3 downto 0) <= axi_2d_mmvs_0_M_AXI_ARLEN(3 downto 0); + M_AXI_arprot(2 downto 0) <= axi_2d_mmvs_0_M_AXI_ARPROT(2 downto 0); + M_AXI_arsize(2 downto 0) <= axi_2d_mmvs_0_M_AXI_ARSIZE(2 downto 0); + M_AXI_arvalid <= axi_2d_mmvs_0_M_AXI_ARVALID; + M_AXI_awaddr(31 downto 0) <= axi_2d_mmvs_0_M_AXI_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= axi_2d_mmvs_0_M_AXI_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= axi_2d_mmvs_0_M_AXI_AWCACHE(3 downto 0); + M_AXI_awid(0) <= axi_2d_mmvs_0_M_AXI_AWID(0); + M_AXI_awlen(3 downto 0) <= axi_2d_mmvs_0_M_AXI_AWLEN(3 downto 0); + M_AXI_awprot(2 downto 0) <= axi_2d_mmvs_0_M_AXI_AWPROT(2 downto 0); + M_AXI_awsize(2 downto 0) <= axi_2d_mmvs_0_M_AXI_AWSIZE(2 downto 0); + M_AXI_awvalid <= axi_2d_mmvs_0_M_AXI_AWVALID; + M_AXI_bready <= axi_2d_mmvs_0_M_AXI_BREADY; + M_AXI_rready <= axi_2d_mmvs_0_M_AXI_RREADY; + M_AXI_wdata(31 downto 0) <= axi_2d_mmvs_0_M_AXI_WDATA(31 downto 0); + M_AXI_wlast <= axi_2d_mmvs_0_M_AXI_WLAST; + M_AXI_wstrb(3 downto 0) <= axi_2d_mmvs_0_M_AXI_WSTRB(3 downto 0); + M_AXI_wvalid <= axi_2d_mmvs_0_M_AXI_WVALID; + Net <= ACLK; + Net1 <= ARESETN; + S_AXIL1_1_ARADDR(31 downto 0) <= S_AXIL1_araddr(31 downto 0); + S_AXIL1_1_ARVALID <= S_AXIL1_arvalid; + S_AXIL1_1_AWADDR(31 downto 0) <= S_AXIL1_awaddr(31 downto 0); + S_AXIL1_1_AWVALID <= S_AXIL1_awvalid; + S_AXIL1_1_BREADY <= S_AXIL1_bready; + S_AXIL1_1_RREADY <= S_AXIL1_rready; + S_AXIL1_1_WDATA(31 downto 0) <= S_AXIL1_wdata(31 downto 0); + S_AXIL1_1_WSTRB(3 downto 0) <= S_AXIL1_wstrb(3 downto 0); + S_AXIL1_1_WVALID <= S_AXIL1_wvalid; + S_AXIL1_arready <= S_AXIL1_1_ARREADY; + S_AXIL1_awready <= S_AXIL1_1_AWREADY; + S_AXIL1_bresp(1 downto 0) <= S_AXIL1_1_BRESP(1 downto 0); + S_AXIL1_bvalid <= S_AXIL1_1_BVALID; + S_AXIL1_rdata(31 downto 0) <= S_AXIL1_1_RDATA(31 downto 0); + S_AXIL1_rresp(1 downto 0) <= S_AXIL1_1_RRESP(1 downto 0); + S_AXIL1_rvalid <= S_AXIL1_1_RVALID; + S_AXIL1_wready <= S_AXIL1_1_WREADY; + S_AXIL_1_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0); + S_AXIL_1_ARVALID <= S_AXIL_arvalid; + S_AXIL_1_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0); + S_AXIL_1_AWVALID <= S_AXIL_awvalid; + S_AXIL_1_BREADY <= S_AXIL_bready; + S_AXIL_1_RREADY <= S_AXIL_rready; + S_AXIL_1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0); + S_AXIL_1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0); + S_AXIL_1_WVALID <= S_AXIL_wvalid; + S_AXIL_arready <= S_AXIL_1_ARREADY; + S_AXIL_awready <= S_AXIL_1_AWREADY; + S_AXIL_bresp(1 downto 0) <= S_AXIL_1_BRESP(1 downto 0); + S_AXIL_bvalid <= S_AXIL_1_BVALID; + S_AXIL_rdata(31 downto 0) <= S_AXIL_1_RDATA(31 downto 0); + S_AXIL_rresp(1 downto 0) <= S_AXIL_1_RRESP(1 downto 0); + S_AXIL_rvalid <= S_AXIL_1_RVALID; + S_AXIL_wready <= S_AXIL_1_WREADY; + VS2MM_INTERRUPT <= axi_2d_mmvs_0_VS2MM_INTERRUPT; + axi_2d_mmvs_0_M_AXI_ARREADY <= M_AXI_arready; + axi_2d_mmvs_0_M_AXI_AWREADY <= M_AXI_awready; + axi_2d_mmvs_0_M_AXI_BID(0) <= M_AXI_bid(0); + axi_2d_mmvs_0_M_AXI_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + axi_2d_mmvs_0_M_AXI_BVALID <= M_AXI_bvalid; + axi_2d_mmvs_0_M_AXI_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + axi_2d_mmvs_0_M_AXI_RID(0) <= M_AXI_rid(0); + axi_2d_mmvs_0_M_AXI_RLAST <= M_AXI_rlast; + axi_2d_mmvs_0_M_AXI_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + axi_2d_mmvs_0_M_AXI_RVALID <= M_AXI_rvalid; + axi_2d_mmvs_0_M_AXI_WREADY <= M_AXI_wready; +axi_2d_mmvs_0: component design_3_axi_2d_mmvs_0_0 + port map ( + ACLK => Net, + ARESETN => Net1, + MM2VS_INTERRUPT => NLW_axi_2d_mmvs_0_MM2VS_INTERRUPT_UNCONNECTED, + M_AXIS_TDATA(31 downto 0) => axi_2d_mmvs_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axi_2d_mmvs_0_M_AXIS_TLAST, + M_AXIS_TREADY => axi_2d_mmvs_0_M_AXIS_TREADY, + M_AXIS_TUSER(0) => axi_2d_mmvs_0_M_AXIS_TUSER(0), + M_AXIS_TVALID => axi_2d_mmvs_0_M_AXIS_TVALID, + M_AXI_ARADDR(31 downto 0) => axi_2d_mmvs_0_M_AXI_ARADDR(31 downto 0), + M_AXI_ARBURST(1 downto 0) => axi_2d_mmvs_0_M_AXI_ARBURST(1 downto 0), + M_AXI_ARCACHE(3 downto 0) => axi_2d_mmvs_0_M_AXI_ARCACHE(3 downto 0), + M_AXI_ARID(0) => axi_2d_mmvs_0_M_AXI_ARID(0), + M_AXI_ARLEN(3 downto 0) => axi_2d_mmvs_0_M_AXI_ARLEN(3 downto 0), + M_AXI_ARPROT(2 downto 0) => axi_2d_mmvs_0_M_AXI_ARPROT(2 downto 0), + M_AXI_ARREADY => axi_2d_mmvs_0_M_AXI_ARREADY, + M_AXI_ARSIZE(2 downto 0) => axi_2d_mmvs_0_M_AXI_ARSIZE(2 downto 0), + M_AXI_ARVALID => axi_2d_mmvs_0_M_AXI_ARVALID, + M_AXI_AWADDR(31 downto 0) => axi_2d_mmvs_0_M_AXI_AWADDR(31 downto 0), + M_AXI_AWBURST(1 downto 0) => axi_2d_mmvs_0_M_AXI_AWBURST(1 downto 0), + M_AXI_AWCACHE(3 downto 0) => axi_2d_mmvs_0_M_AXI_AWCACHE(3 downto 0), + M_AXI_AWID(0) => axi_2d_mmvs_0_M_AXI_AWID(0), + M_AXI_AWLEN(3 downto 0) => axi_2d_mmvs_0_M_AXI_AWLEN(3 downto 0), + M_AXI_AWPROT(2 downto 0) => axi_2d_mmvs_0_M_AXI_AWPROT(2 downto 0), + M_AXI_AWREADY => axi_2d_mmvs_0_M_AXI_AWREADY, + M_AXI_AWSIZE(2 downto 0) => axi_2d_mmvs_0_M_AXI_AWSIZE(2 downto 0), + M_AXI_AWVALID => axi_2d_mmvs_0_M_AXI_AWVALID, + M_AXI_BID(0) => axi_2d_mmvs_0_M_AXI_BID(0), + M_AXI_BREADY => axi_2d_mmvs_0_M_AXI_BREADY, + M_AXI_BRESP(1 downto 0) => axi_2d_mmvs_0_M_AXI_BRESP(1 downto 0), + M_AXI_BVALID => axi_2d_mmvs_0_M_AXI_BVALID, + M_AXI_RDATA(31 downto 0) => axi_2d_mmvs_0_M_AXI_RDATA(31 downto 0), + M_AXI_RID(0) => axi_2d_mmvs_0_M_AXI_RID(0), + M_AXI_RLAST => axi_2d_mmvs_0_M_AXI_RLAST, + M_AXI_RREADY => axi_2d_mmvs_0_M_AXI_RREADY, + M_AXI_RRESP(1 downto 0) => axi_2d_mmvs_0_M_AXI_RRESP(1 downto 0), + M_AXI_RVALID => axi_2d_mmvs_0_M_AXI_RVALID, + M_AXI_WDATA(31 downto 0) => axi_2d_mmvs_0_M_AXI_WDATA(31 downto 0), + M_AXI_WID(0) => NLW_axi_2d_mmvs_0_M_AXI_WID_UNCONNECTED(0), + M_AXI_WLAST => axi_2d_mmvs_0_M_AXI_WLAST, + M_AXI_WREADY => axi_2d_mmvs_0_M_AXI_WREADY, + M_AXI_WSTRB(3 downto 0) => axi_2d_mmvs_0_M_AXI_WSTRB(3 downto 0), + M_AXI_WVALID => axi_2d_mmvs_0_M_AXI_WVALID, + S_AXIL_ARADDR(15 downto 0) => S_AXIL1_1_ARADDR(15 downto 0), + S_AXIL_ARREADY => S_AXIL1_1_ARREADY, + S_AXIL_ARVALID => S_AXIL1_1_ARVALID, + S_AXIL_AWADDR(15 downto 0) => S_AXIL1_1_AWADDR(15 downto 0), + S_AXIL_AWREADY => S_AXIL1_1_AWREADY, + S_AXIL_AWVALID => S_AXIL1_1_AWVALID, + S_AXIL_BREADY => S_AXIL1_1_BREADY, + S_AXIL_BRESP(1 downto 0) => S_AXIL1_1_BRESP(1 downto 0), + S_AXIL_BVALID => S_AXIL1_1_BVALID, + S_AXIL_RDATA(31 downto 0) => S_AXIL1_1_RDATA(31 downto 0), + S_AXIL_RREADY => S_AXIL1_1_RREADY, + S_AXIL_RRESP(1 downto 0) => S_AXIL1_1_RRESP(1 downto 0), + S_AXIL_RVALID => S_AXIL1_1_RVALID, + S_AXIL_WDATA(31 downto 0) => S_AXIL1_1_WDATA(31 downto 0), + S_AXIL_WREADY => S_AXIL1_1_WREADY, + S_AXIL_WSTRB(3 downto 0) => S_AXIL1_1_WSTRB(3 downto 0), + S_AXIL_WVALID => S_AXIL1_1_WVALID, + S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + S_AXIS_TUSER(0) => axis_upsizer_0_M_AXIS_TUSER, + S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + VS2MM_INTERRUPT => axi_2d_mmvs_0_VS2MM_INTERRUPT + ); +axis_downsizer_0: component design_3_axis_downsizer_0_0 + port map ( + AXIS_ACLK => Net, + AXIS_ARESETN => Net1, + M_AXIS_TDATA(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0), + M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY, + M_AXIS_TUSER => axis_downsizer_0_M_AXIS_TUSER, + M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID, + S_AXIS_TDATA(31 downto 0) => axi_2d_mmvs_0_M_AXIS_TDATA(31 downto 0), + S_AXIS_TLAST => axi_2d_mmvs_0_M_AXIS_TLAST, + S_AXIS_TREADY => axi_2d_mmvs_0_M_AXIS_TREADY, + S_AXIS_TUSER => axi_2d_mmvs_0_M_AXIS_TUSER(0), + S_AXIS_TVALID => axi_2d_mmvs_0_M_AXIS_TVALID + ); +axis_linemem_single_0: component design_3_axis_linemem_single_0_0 + port map ( + aclk => Net, + aresetn => Net1, + m_axis_tdata(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0), + m_axis_tlast => axis_linemem_single_0_m_axis_TLAST, + m_axis_tready => axis_linemem_single_0_m_axis_TREADY, + m_axis_tuser(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0), + m_axis_tvalid => axis_linemem_single_0_m_axis_TVALID, + s_axis_tdata(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0), + s_axis_tlast => axis_downsizer_0_M_AXIS_TLAST, + s_axis_tready => axis_downsizer_0_M_AXIS_TREADY, + s_axis_tuser(0) => axis_downsizer_0_M_AXIS_TUSER, + s_axis_tvalid => axis_downsizer_0_M_AXIS_TVALID + ); +axis_upsizer_0: component design_3_axis_upsizer_0_0 + port map ( + AXIS_ACLK => Net, + AXIS_ARESETN => Net1, + M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0), + M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY, + M_AXIS_TUSER => axis_upsizer_0_M_AXIS_TUSER, + M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID, + S_AXIS_TDATA(7 downto 0) => axis_video_filter_0_M_AXIS_TDATA(7 downto 0), + S_AXIS_TLAST => axis_video_filter_0_M_AXIS_TLAST, + S_AXIS_TREADY => axis_video_filter_0_M_AXIS_TREADY, + S_AXIS_TUSER => axis_video_filter_0_M_AXIS_TUSER, + S_AXIS_TVALID => axis_video_filter_0_M_AXIS_TVALID + ); +axis_video_filter_0: component design_3_axis_video_filter_0_0 + port map ( + ACLK => Net, + ARESETN => Net1, + M_AXIS_TDATA(7 downto 0) => axis_video_filter_0_M_AXIS_TDATA(7 downto 0), + M_AXIS_TLAST => axis_video_filter_0_M_AXIS_TLAST, + M_AXIS_TREADY => axis_video_filter_0_M_AXIS_TREADY, + M_AXIS_TUSER => axis_video_filter_0_M_AXIS_TUSER, + M_AXIS_TVALID => axis_video_filter_0_M_AXIS_TVALID, + S_AXIL_ARADDR(14 downto 0) => S_AXIL_1_ARADDR(14 downto 0), + S_AXIL_ARREADY => S_AXIL_1_ARREADY, + S_AXIL_ARVALID => S_AXIL_1_ARVALID, + S_AXIL_AWADDR(14 downto 0) => S_AXIL_1_AWADDR(14 downto 0), + S_AXIL_AWREADY => S_AXIL_1_AWREADY, + S_AXIL_AWVALID => S_AXIL_1_AWVALID, + S_AXIL_BREADY => S_AXIL_1_BREADY, + S_AXIL_BRESP(1 downto 0) => S_AXIL_1_BRESP(1 downto 0), + S_AXIL_BVALID => S_AXIL_1_BVALID, + S_AXIL_RDATA(31 downto 0) => S_AXIL_1_RDATA(31 downto 0), + S_AXIL_RREADY => S_AXIL_1_RREADY, + S_AXIL_RRESP(1 downto 0) => S_AXIL_1_RRESP(1 downto 0), + S_AXIL_RVALID => S_AXIL_1_RVALID, + S_AXIL_WDATA(31 downto 0) => S_AXIL_1_WDATA(31 downto 0), + S_AXIL_WREADY => S_AXIL_1_WREADY, + S_AXIL_WSTRB(3 downto 0) => S_AXIL_1_WSTRB(3 downto 0), + S_AXIL_WVALID => S_AXIL_1_WVALID, + S_AXIS_TDATA(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0), + S_AXIS_TLAST => axis_linemem_single_0_m_axis_TLAST, + S_AXIS_TREADY => axis_linemem_single_0_m_axis_TREADY, + S_AXIS_TUSER(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0), + S_AXIS_TVALID => axis_linemem_single_0_m_axis_TVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ZYNQ_BASE_imp_1TRJPP2 is + port ( + BUTTON_0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + HDMI_CLK_N_0 : out STD_LOGIC; + HDMI_CLK_P_0 : out STD_LOGIC; + HDMI_DATA_N_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_DATA_P_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + LED_0 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ACLK : in STD_LOGIC; + M_AXI_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + RGB_LED_0 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + SWITCH_0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_arready : out STD_LOGIC; + S_AXIL_arvalid : in STD_LOGIC; + S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_awready : out STD_LOGIC; + S_AXIL_awvalid : in STD_LOGIC; + S_AXIL_bready : in STD_LOGIC; + S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_bvalid : out STD_LOGIC; + S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_rready : in STD_LOGIC; + S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_rvalid : out STD_LOGIC; + S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_wready : out STD_LOGIC; + S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_wvalid : in STD_LOGIC; + VIDEO_CLK : in STD_LOGIC; + VIDEO_INTERRUPT : out STD_LOGIC + ); +end ZYNQ_BASE_imp_1TRJPP2; + +architecture STRUCTURE of ZYNQ_BASE_imp_1TRJPP2 is + component design_3_zynq_base_hdmi_0_0 is + port ( + VIDEO_CLK : in STD_LOGIC; + VIDEO_RESETN : in STD_LOGIC; + HDMI_DATA_P : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_DATA_N : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_CLK_P : out STD_LOGIC; + HDMI_CLK_N : out STD_LOGIC; + VIDEO_INTERRUPT : out STD_LOGIC; + SWITCH : in STD_LOGIC_VECTOR ( 3 downto 0 ); + BUTTON : in STD_LOGIC_VECTOR ( 3 downto 0 ); + LED : out STD_LOGIC_VECTOR ( 3 downto 0 ); + RGB_LED : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXIL_ACLK : in STD_LOGIC; + S_AXIL_ARESETN : in STD_LOGIC; + S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIL_AWVALID : in STD_LOGIC; + S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXIL_WVALID : in STD_LOGIC; + S_AXIL_BREADY : in STD_LOGIC; + S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 ); + S_AXIL_ARVALID : in STD_LOGIC; + S_AXIL_RREADY : in STD_LOGIC; + S_AXIL_ARREADY : out STD_LOGIC; + S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_RVALID : out STD_LOGIC; + S_AXIL_WREADY : out STD_LOGIC; + S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXIL_BVALID : out STD_LOGIC; + S_AXIL_AWREADY : out STD_LOGIC; + M_AXI_ACLK : in STD_LOGIC; + M_AXI_ARESETN : in STD_LOGIC; + M_AXI_ARREADY : in STD_LOGIC; + M_AXI_ARVALID : out STD_LOGIC; + M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_ARID : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_RREADY : out STD_LOGIC; + M_AXI_RVALID : in STD_LOGIC; + M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_RLAST : in STD_LOGIC; + M_AXI_RID : in STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_AWREADY : in STD_LOGIC; + M_AXI_AWVALID : out STD_LOGIC; + M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WREADY : in STD_LOGIC; + M_AXI_WVALID : out STD_LOGIC; + M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_WLAST : out STD_LOGIC; + M_AXI_BREADY : out STD_LOGIC; + M_AXI_BVALID : in STD_LOGIC; + M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component design_3_zynq_base_hdmi_0_0; + signal BUTTON_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal SWITCH_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; + signal processing_system7_0_FCLK_CLK3 : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC; + signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_CLK_N : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_CLK_P : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_DATA_N : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_HDMI_DATA_P : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_LED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_BVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WVALID : STD_LOGIC; + signal zynq_base_hdmi_0_RGB_LED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal zynq_base_hdmi_0_VIDEO_INTERRUPT : STD_LOGIC; +begin + BUTTON_0_1(3 downto 0) <= BUTTON_0(3 downto 0); + HDMI_CLK_N_0 <= zynq_base_hdmi_0_HDMI_CLK_N; + HDMI_CLK_P_0 <= zynq_base_hdmi_0_HDMI_CLK_P; + HDMI_DATA_N_0(2 downto 0) <= zynq_base_hdmi_0_HDMI_DATA_N(2 downto 0); + HDMI_DATA_P_0(2 downto 0) <= zynq_base_hdmi_0_HDMI_DATA_P(2 downto 0); + LED_0(3 downto 0) <= zynq_base_hdmi_0_LED(3 downto 0); + M_AXI_araddr(31 downto 0) <= zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0); + M_AXI_arcache(3 downto 0) <= zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0); + M_AXI_arid(3 downto 0) <= zynq_base_hdmi_0_M_AXI_ARID(3 downto 0); + M_AXI_arlen(3 downto 0) <= zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0); + M_AXI_arprot(2 downto 0) <= zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0); + M_AXI_arsize(2 downto 0) <= zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0); + M_AXI_arvalid <= zynq_base_hdmi_0_M_AXI_ARVALID; + M_AXI_awaddr(31 downto 0) <= zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0); + M_AXI_awlen(3 downto 0) <= zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0); + M_AXI_awprot(2 downto 0) <= zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0); + M_AXI_awsize(2 downto 0) <= zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0); + M_AXI_awvalid <= zynq_base_hdmi_0_M_AXI_AWVALID; + M_AXI_bready <= zynq_base_hdmi_0_M_AXI_BREADY; + M_AXI_rready <= zynq_base_hdmi_0_M_AXI_RREADY; + M_AXI_wdata(31 downto 0) <= zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0); + M_AXI_wlast <= zynq_base_hdmi_0_M_AXI_WLAST; + M_AXI_wstrb(3 downto 0) <= zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0); + M_AXI_wvalid <= zynq_base_hdmi_0_M_AXI_WVALID; + RGB_LED_0(5 downto 0) <= zynq_base_hdmi_0_RGB_LED(5 downto 0); + SWITCH_0_1(3 downto 0) <= SWITCH_0(3 downto 0); + S_AXIL_arready <= ps7_0_axi_periph_M00_AXI_ARREADY; + S_AXIL_awready <= ps7_0_axi_periph_M00_AXI_AWREADY; + S_AXIL_bresp(1 downto 0) <= ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0); + S_AXIL_bvalid <= ps7_0_axi_periph_M00_AXI_BVALID; + S_AXIL_rdata(31 downto 0) <= ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0); + S_AXIL_rresp(1 downto 0) <= ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0); + S_AXIL_rvalid <= ps7_0_axi_periph_M00_AXI_RVALID; + S_AXIL_wready <= ps7_0_axi_periph_M00_AXI_WREADY; + VIDEO_INTERRUPT <= zynq_base_hdmi_0_VIDEO_INTERRUPT; + processing_system7_0_FCLK_CLK0 <= M_AXI_ACLK; + processing_system7_0_FCLK_CLK3 <= VIDEO_CLK; + ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0); + ps7_0_axi_periph_M00_AXI_ARVALID <= S_AXIL_arvalid; + ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0); + ps7_0_axi_periph_M00_AXI_AWVALID <= S_AXIL_awvalid; + ps7_0_axi_periph_M00_AXI_BREADY <= S_AXIL_bready; + ps7_0_axi_periph_M00_AXI_RREADY <= S_AXIL_rready; + ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0); + ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0); + ps7_0_axi_periph_M00_AXI_WVALID <= S_AXIL_wvalid; + rst_ps7_0_100M_peripheral_aresetn <= M_AXI_ARESETN; + zynq_base_hdmi_0_M_AXI_ARREADY <= M_AXI_arready; + zynq_base_hdmi_0_M_AXI_AWREADY <= M_AXI_awready; + zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + zynq_base_hdmi_0_M_AXI_BVALID <= M_AXI_bvalid; + zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + zynq_base_hdmi_0_M_AXI_RID(3 downto 0) <= M_AXI_rid(3 downto 0); + zynq_base_hdmi_0_M_AXI_RLAST <= M_AXI_rlast; + zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + zynq_base_hdmi_0_M_AXI_RVALID <= M_AXI_rvalid; + zynq_base_hdmi_0_M_AXI_WREADY <= M_AXI_wready; +zynq_base_hdmi_0: component design_3_zynq_base_hdmi_0_0 + port map ( + BUTTON(3 downto 0) => BUTTON_0_1(3 downto 0), + HDMI_CLK_N => zynq_base_hdmi_0_HDMI_CLK_N, + HDMI_CLK_P => zynq_base_hdmi_0_HDMI_CLK_P, + HDMI_DATA_N(2 downto 0) => zynq_base_hdmi_0_HDMI_DATA_N(2 downto 0), + HDMI_DATA_P(2 downto 0) => zynq_base_hdmi_0_HDMI_DATA_P(2 downto 0), + LED(3 downto 0) => zynq_base_hdmi_0_LED(3 downto 0), + M_AXI_ACLK => processing_system7_0_FCLK_CLK0, + M_AXI_ARADDR(31 downto 0) => zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0), + M_AXI_ARBURST(1 downto 0) => zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0), + M_AXI_ARCACHE(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0), + M_AXI_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M_AXI_ARID(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARID(3 downto 0), + M_AXI_ARLEN(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0), + M_AXI_ARPROT(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0), + M_AXI_ARREADY => zynq_base_hdmi_0_M_AXI_ARREADY, + M_AXI_ARSIZE(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0), + M_AXI_ARVALID => zynq_base_hdmi_0_M_AXI_ARVALID, + M_AXI_AWADDR(31 downto 0) => zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0), + M_AXI_AWBURST(1 downto 0) => zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0), + M_AXI_AWCACHE(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0), + M_AXI_AWLEN(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0), + M_AXI_AWPROT(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0), + M_AXI_AWREADY => zynq_base_hdmi_0_M_AXI_AWREADY, + M_AXI_AWSIZE(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0), + M_AXI_AWVALID => zynq_base_hdmi_0_M_AXI_AWVALID, + M_AXI_BREADY => zynq_base_hdmi_0_M_AXI_BREADY, + M_AXI_BRESP(1 downto 0) => zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0), + M_AXI_BVALID => zynq_base_hdmi_0_M_AXI_BVALID, + M_AXI_RDATA(31 downto 0) => zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0), + M_AXI_RID(3 downto 0) => zynq_base_hdmi_0_M_AXI_RID(3 downto 0), + M_AXI_RLAST => zynq_base_hdmi_0_M_AXI_RLAST, + M_AXI_RREADY => zynq_base_hdmi_0_M_AXI_RREADY, + M_AXI_RRESP(1 downto 0) => zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0), + M_AXI_RVALID => zynq_base_hdmi_0_M_AXI_RVALID, + M_AXI_WDATA(31 downto 0) => zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0), + M_AXI_WLAST => zynq_base_hdmi_0_M_AXI_WLAST, + M_AXI_WREADY => zynq_base_hdmi_0_M_AXI_WREADY, + M_AXI_WSTRB(3 downto 0) => zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0), + M_AXI_WVALID => zynq_base_hdmi_0_M_AXI_WVALID, + RGB_LED(5 downto 0) => zynq_base_hdmi_0_RGB_LED(5 downto 0), + SWITCH(3 downto 0) => SWITCH_0_1(3 downto 0), + S_AXIL_ACLK => processing_system7_0_FCLK_CLK0, + S_AXIL_ARADDR(15 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(15 downto 0), + S_AXIL_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + S_AXIL_ARREADY => ps7_0_axi_periph_M00_AXI_ARREADY, + S_AXIL_ARVALID => ps7_0_axi_periph_M00_AXI_ARVALID, + S_AXIL_AWADDR(15 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(15 downto 0), + S_AXIL_AWREADY => ps7_0_axi_periph_M00_AXI_AWREADY, + S_AXIL_AWVALID => ps7_0_axi_periph_M00_AXI_AWVALID, + S_AXIL_BREADY => ps7_0_axi_periph_M00_AXI_BREADY, + S_AXIL_BRESP(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), + S_AXIL_BVALID => ps7_0_axi_periph_M00_AXI_BVALID, + S_AXIL_RDATA(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), + S_AXIL_RREADY => ps7_0_axi_periph_M00_AXI_RREADY, + S_AXIL_RRESP(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), + S_AXIL_RVALID => ps7_0_axi_periph_M00_AXI_RVALID, + S_AXIL_WDATA(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), + S_AXIL_WREADY => ps7_0_axi_periph_M00_AXI_WREADY, + S_AXIL_WSTRB(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), + S_AXIL_WVALID => ps7_0_axi_periph_M00_AXI_WVALID, + VIDEO_CLK => processing_system7_0_FCLK_CLK3, + VIDEO_INTERRUPT => zynq_base_hdmi_0_VIDEO_INTERRUPT, + VIDEO_RESETN => rst_ps7_0_100M_peripheral_aresetn + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity m00_couplers_imp_XFWZ5U is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end m00_couplers_imp_XFWZ5U; + +architecture STRUCTURE of m00_couplers_imp_XFWZ5U is + signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC; + signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC; + signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC; + signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC; + signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC; + signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0); + M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0); + M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID; + M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY; + M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID; + S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY; + S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY; + S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0); + S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID; + S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0); + S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0); + S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID; + S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY; + m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready; + m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid; + m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready; + m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid; + m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready; + m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid; + m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready; + m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid; + m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready; + m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity m01_couplers_imp_164MWV7 is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end m01_couplers_imp_164MWV7; + +architecture STRUCTURE of m01_couplers_imp_164MWV7 is + signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC; + signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC; + signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC; + signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC; + signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC; + signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0); + M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0); + M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID; + M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY; + M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID; + S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY; + S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY; + S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0); + S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID; + S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0); + S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0); + S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID; + S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY; + m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready; + m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid; + m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready; + m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid; + m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready; + m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid; + m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready; + m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid; + m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready; + m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity m02_couplers_imp_YRUE81 is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end m02_couplers_imp_YRUE81; + +architecture STRUCTURE of m02_couplers_imp_YRUE81 is + signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC; + signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC; + signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC; + signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC; + signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC; + signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0); + M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0); + M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID; + M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY; + M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID; + S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY; + S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY; + S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0); + S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID; + S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0); + S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0); + S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID; + S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY; + m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready; + m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid; + m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready; + m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid; + m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready; + m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid; + m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready; + m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid; + m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready; + m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity s00_couplers_imp_1UA4Y98 is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_rlast : out STD_LOGIC; + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wlast : in STD_LOGIC; + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end s00_couplers_imp_1UA4Y98; + +architecture STRUCTURE of s00_couplers_imp_1UA4Y98 is + component design_3_auto_us_1 is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC + ); + end component design_3_auto_us_1; + signal S_ACLK_1 : STD_LOGIC; + signal S_ARESETN_1 : STD_LOGIC; + signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_us_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_AWVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_BREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_BVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_us_to_s00_couplers_RLAST : STD_LOGIC; + signal auto_us_to_s00_couplers_RREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_RVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_us_to_s00_couplers_WLAST : STD_LOGIC; + signal auto_us_to_s00_couplers_WREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal auto_us_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_AWREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_AWVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_auto_us_BREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_BVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_auto_us_RLAST : STD_LOGIC; + signal s00_couplers_to_auto_us_RREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_RVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_WLAST : STD_LOGIC; + signal s00_couplers_to_auto_us_WREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0); + M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0); + M_AXI_arlen(3 downto 0) <= auto_us_to_s00_couplers_ARLEN(3 downto 0); + M_AXI_arlock(1 downto 0) <= auto_us_to_s00_couplers_ARLOCK(1 downto 0); + M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0); + M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0); + M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0); + M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= auto_us_to_s00_couplers_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= auto_us_to_s00_couplers_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= auto_us_to_s00_couplers_AWCACHE(3 downto 0); + M_AXI_awlen(3 downto 0) <= auto_us_to_s00_couplers_AWLEN(3 downto 0); + M_AXI_awlock(1 downto 0) <= auto_us_to_s00_couplers_AWLOCK(1 downto 0); + M_AXI_awprot(2 downto 0) <= auto_us_to_s00_couplers_AWPROT(2 downto 0); + M_AXI_awqos(3 downto 0) <= auto_us_to_s00_couplers_AWQOS(3 downto 0); + M_AXI_awsize(2 downto 0) <= auto_us_to_s00_couplers_AWSIZE(2 downto 0); + M_AXI_awvalid <= auto_us_to_s00_couplers_AWVALID; + M_AXI_bready <= auto_us_to_s00_couplers_BREADY; + M_AXI_rready <= auto_us_to_s00_couplers_RREADY; + M_AXI_wdata(63 downto 0) <= auto_us_to_s00_couplers_WDATA(63 downto 0); + M_AXI_wlast <= auto_us_to_s00_couplers_WLAST; + M_AXI_wstrb(7 downto 0) <= auto_us_to_s00_couplers_WSTRB(7 downto 0); + M_AXI_wvalid <= auto_us_to_s00_couplers_WVALID; + S_ACLK_1 <= S_ACLK; + S_ARESETN_1 <= S_ARESETN; + S_AXI_arready <= s00_couplers_to_auto_us_ARREADY; + S_AXI_awready <= s00_couplers_to_auto_us_AWREADY; + S_AXI_bid(0) <= s00_couplers_to_auto_us_BID(0); + S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_us_BRESP(1 downto 0); + S_AXI_bvalid <= s00_couplers_to_auto_us_BVALID; + S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0); + S_AXI_rid(0) <= s00_couplers_to_auto_us_RID(0); + S_AXI_rlast <= s00_couplers_to_auto_us_RLAST; + S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0); + S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID; + S_AXI_wready <= s00_couplers_to_auto_us_WREADY; + auto_us_to_s00_couplers_ARREADY <= M_AXI_arready; + auto_us_to_s00_couplers_AWREADY <= M_AXI_awready; + auto_us_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + auto_us_to_s00_couplers_BVALID <= M_AXI_bvalid; + auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); + auto_us_to_s00_couplers_RLAST <= M_AXI_rlast; + auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid; + auto_us_to_s00_couplers_WREADY <= M_AXI_wready; + s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); + s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); + s00_couplers_to_auto_us_ARID(0) <= S_AXI_arid(0); + s00_couplers_to_auto_us_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); + s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); + s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); + s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid; + s00_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + s00_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); + s00_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); + s00_couplers_to_auto_us_AWID(0) <= S_AXI_awid(0); + s00_couplers_to_auto_us_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); + s00_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); + s00_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); + s00_couplers_to_auto_us_AWVALID <= S_AXI_awvalid; + s00_couplers_to_auto_us_BREADY <= S_AXI_bready; + s00_couplers_to_auto_us_RREADY <= S_AXI_rready; + s00_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + s00_couplers_to_auto_us_WLAST <= S_AXI_wlast; + s00_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + s00_couplers_to_auto_us_WVALID <= S_AXI_wvalid; +auto_us: component design_3_auto_us_1 + port map ( + m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0), + m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0), + m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0), + m_axi_arlen(3 downto 0) => auto_us_to_s00_couplers_ARLEN(3 downto 0), + m_axi_arlock(1 downto 0) => auto_us_to_s00_couplers_ARLOCK(1 downto 0), + m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0), + m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0), + m_axi_arready => auto_us_to_s00_couplers_ARREADY, + m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0), + m_axi_arvalid => auto_us_to_s00_couplers_ARVALID, + m_axi_awaddr(31 downto 0) => auto_us_to_s00_couplers_AWADDR(31 downto 0), + m_axi_awburst(1 downto 0) => auto_us_to_s00_couplers_AWBURST(1 downto 0), + m_axi_awcache(3 downto 0) => auto_us_to_s00_couplers_AWCACHE(3 downto 0), + m_axi_awlen(3 downto 0) => auto_us_to_s00_couplers_AWLEN(3 downto 0), + m_axi_awlock(1 downto 0) => auto_us_to_s00_couplers_AWLOCK(1 downto 0), + m_axi_awprot(2 downto 0) => auto_us_to_s00_couplers_AWPROT(2 downto 0), + m_axi_awqos(3 downto 0) => auto_us_to_s00_couplers_AWQOS(3 downto 0), + m_axi_awready => auto_us_to_s00_couplers_AWREADY, + m_axi_awsize(2 downto 0) => auto_us_to_s00_couplers_AWSIZE(2 downto 0), + m_axi_awvalid => auto_us_to_s00_couplers_AWVALID, + m_axi_bready => auto_us_to_s00_couplers_BREADY, + m_axi_bresp(1 downto 0) => auto_us_to_s00_couplers_BRESP(1 downto 0), + m_axi_bvalid => auto_us_to_s00_couplers_BVALID, + m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0), + m_axi_rlast => auto_us_to_s00_couplers_RLAST, + m_axi_rready => auto_us_to_s00_couplers_RREADY, + m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0), + m_axi_rvalid => auto_us_to_s00_couplers_RVALID, + m_axi_wdata(63 downto 0) => auto_us_to_s00_couplers_WDATA(63 downto 0), + m_axi_wlast => auto_us_to_s00_couplers_WLAST, + m_axi_wready => auto_us_to_s00_couplers_WREADY, + m_axi_wstrb(7 downto 0) => auto_us_to_s00_couplers_WSTRB(7 downto 0), + m_axi_wvalid => auto_us_to_s00_couplers_WVALID, + s_axi_aclk => S_ACLK_1, + s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0), + s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0), + s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0), + s_axi_aresetn => S_ARESETN_1, + s_axi_arid(0) => s00_couplers_to_auto_us_ARID(0), + s_axi_arlen(3 downto 0) => s00_couplers_to_auto_us_ARLEN(3 downto 0), + s_axi_arlock(1 downto 0) => B"00", + s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0), + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => s00_couplers_to_auto_us_ARREADY, + s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0), + s_axi_arvalid => s00_couplers_to_auto_us_ARVALID, + s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_us_AWADDR(31 downto 0), + s_axi_awburst(1 downto 0) => s00_couplers_to_auto_us_AWBURST(1 downto 0), + s_axi_awcache(3 downto 0) => s00_couplers_to_auto_us_AWCACHE(3 downto 0), + s_axi_awid(0) => s00_couplers_to_auto_us_AWID(0), + s_axi_awlen(3 downto 0) => s00_couplers_to_auto_us_AWLEN(3 downto 0), + s_axi_awlock(1 downto 0) => B"00", + s_axi_awprot(2 downto 0) => s00_couplers_to_auto_us_AWPROT(2 downto 0), + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => s00_couplers_to_auto_us_AWREADY, + s_axi_awsize(2 downto 0) => s00_couplers_to_auto_us_AWSIZE(2 downto 0), + s_axi_awvalid => s00_couplers_to_auto_us_AWVALID, + s_axi_bid(0) => s00_couplers_to_auto_us_BID(0), + s_axi_bready => s00_couplers_to_auto_us_BREADY, + s_axi_bresp(1 downto 0) => s00_couplers_to_auto_us_BRESP(1 downto 0), + s_axi_bvalid => s00_couplers_to_auto_us_BVALID, + s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0), + s_axi_rid(0) => s00_couplers_to_auto_us_RID(0), + s_axi_rlast => s00_couplers_to_auto_us_RLAST, + s_axi_rready => s00_couplers_to_auto_us_RREADY, + s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0), + s_axi_rvalid => s00_couplers_to_auto_us_RVALID, + s_axi_wdata(31 downto 0) => s00_couplers_to_auto_us_WDATA(31 downto 0), + s_axi_wlast => s00_couplers_to_auto_us_WLAST, + s_axi_wready => s00_couplers_to_auto_us_WREADY, + s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_us_WSTRB(3 downto 0), + s_axi_wvalid => s00_couplers_to_auto_us_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity s00_couplers_imp_1VXU3HN is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_rlast : out STD_LOGIC; + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wlast : in STD_LOGIC; + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end s00_couplers_imp_1VXU3HN; + +architecture STRUCTURE of s00_couplers_imp_1VXU3HN is + component design_3_auto_us_0 is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC + ); + end component design_3_auto_us_0; + signal S_ACLK_1 : STD_LOGIC; + signal S_ARESETN_1 : STD_LOGIC; + signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_us_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_us_to_s00_couplers_AWREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_us_to_s00_couplers_AWVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_BREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_BVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_us_to_s00_couplers_RLAST : STD_LOGIC; + signal auto_us_to_s00_couplers_RREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_us_to_s00_couplers_RVALID : STD_LOGIC; + signal auto_us_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_us_to_s00_couplers_WLAST : STD_LOGIC; + signal auto_us_to_s00_couplers_WREADY : STD_LOGIC; + signal auto_us_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal auto_us_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_AWREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_us_AWVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_BREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_BVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_RLAST : STD_LOGIC; + signal s00_couplers_to_auto_us_RREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_us_RVALID : STD_LOGIC; + signal s00_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_us_WLAST : STD_LOGIC; + signal s00_couplers_to_auto_us_WREADY : STD_LOGIC; + signal s00_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_us_WVALID : STD_LOGIC; + signal NLW_auto_us_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); +begin + M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0); + M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0); + M_AXI_arlen(3 downto 0) <= auto_us_to_s00_couplers_ARLEN(3 downto 0); + M_AXI_arlock(1 downto 0) <= auto_us_to_s00_couplers_ARLOCK(1 downto 0); + M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0); + M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0); + M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0); + M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= auto_us_to_s00_couplers_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= auto_us_to_s00_couplers_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= auto_us_to_s00_couplers_AWCACHE(3 downto 0); + M_AXI_awlen(3 downto 0) <= auto_us_to_s00_couplers_AWLEN(3 downto 0); + M_AXI_awlock(1 downto 0) <= auto_us_to_s00_couplers_AWLOCK(1 downto 0); + M_AXI_awprot(2 downto 0) <= auto_us_to_s00_couplers_AWPROT(2 downto 0); + M_AXI_awqos(3 downto 0) <= auto_us_to_s00_couplers_AWQOS(3 downto 0); + M_AXI_awsize(2 downto 0) <= auto_us_to_s00_couplers_AWSIZE(2 downto 0); + M_AXI_awvalid <= auto_us_to_s00_couplers_AWVALID; + M_AXI_bready <= auto_us_to_s00_couplers_BREADY; + M_AXI_rready <= auto_us_to_s00_couplers_RREADY; + M_AXI_wdata(63 downto 0) <= auto_us_to_s00_couplers_WDATA(63 downto 0); + M_AXI_wlast <= auto_us_to_s00_couplers_WLAST; + M_AXI_wstrb(7 downto 0) <= auto_us_to_s00_couplers_WSTRB(7 downto 0); + M_AXI_wvalid <= auto_us_to_s00_couplers_WVALID; + S_ACLK_1 <= S_ACLK; + S_ARESETN_1 <= S_ARESETN; + S_AXI_arready <= s00_couplers_to_auto_us_ARREADY; + S_AXI_awready <= s00_couplers_to_auto_us_AWREADY; + S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_us_BRESP(1 downto 0); + S_AXI_bvalid <= s00_couplers_to_auto_us_BVALID; + S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0); + S_AXI_rid(3 downto 0) <= s00_couplers_to_auto_us_RID(3 downto 0); + S_AXI_rlast <= s00_couplers_to_auto_us_RLAST; + S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0); + S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID; + S_AXI_wready <= s00_couplers_to_auto_us_WREADY; + auto_us_to_s00_couplers_ARREADY <= M_AXI_arready; + auto_us_to_s00_couplers_AWREADY <= M_AXI_awready; + auto_us_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + auto_us_to_s00_couplers_BVALID <= M_AXI_bvalid; + auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); + auto_us_to_s00_couplers_RLAST <= M_AXI_rlast; + auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid; + auto_us_to_s00_couplers_WREADY <= M_AXI_wready; + s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); + s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); + s00_couplers_to_auto_us_ARID(3 downto 0) <= S_AXI_arid(3 downto 0); + s00_couplers_to_auto_us_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); + s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); + s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); + s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid; + s00_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + s00_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); + s00_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); + s00_couplers_to_auto_us_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); + s00_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); + s00_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); + s00_couplers_to_auto_us_AWVALID <= S_AXI_awvalid; + s00_couplers_to_auto_us_BREADY <= S_AXI_bready; + s00_couplers_to_auto_us_RREADY <= S_AXI_rready; + s00_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + s00_couplers_to_auto_us_WLAST <= S_AXI_wlast; + s00_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + s00_couplers_to_auto_us_WVALID <= S_AXI_wvalid; +auto_us: component design_3_auto_us_0 + port map ( + m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0), + m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0), + m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0), + m_axi_arlen(3 downto 0) => auto_us_to_s00_couplers_ARLEN(3 downto 0), + m_axi_arlock(1 downto 0) => auto_us_to_s00_couplers_ARLOCK(1 downto 0), + m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0), + m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0), + m_axi_arready => auto_us_to_s00_couplers_ARREADY, + m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0), + m_axi_arvalid => auto_us_to_s00_couplers_ARVALID, + m_axi_awaddr(31 downto 0) => auto_us_to_s00_couplers_AWADDR(31 downto 0), + m_axi_awburst(1 downto 0) => auto_us_to_s00_couplers_AWBURST(1 downto 0), + m_axi_awcache(3 downto 0) => auto_us_to_s00_couplers_AWCACHE(3 downto 0), + m_axi_awlen(3 downto 0) => auto_us_to_s00_couplers_AWLEN(3 downto 0), + m_axi_awlock(1 downto 0) => auto_us_to_s00_couplers_AWLOCK(1 downto 0), + m_axi_awprot(2 downto 0) => auto_us_to_s00_couplers_AWPROT(2 downto 0), + m_axi_awqos(3 downto 0) => auto_us_to_s00_couplers_AWQOS(3 downto 0), + m_axi_awready => auto_us_to_s00_couplers_AWREADY, + m_axi_awsize(2 downto 0) => auto_us_to_s00_couplers_AWSIZE(2 downto 0), + m_axi_awvalid => auto_us_to_s00_couplers_AWVALID, + m_axi_bready => auto_us_to_s00_couplers_BREADY, + m_axi_bresp(1 downto 0) => auto_us_to_s00_couplers_BRESP(1 downto 0), + m_axi_bvalid => auto_us_to_s00_couplers_BVALID, + m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0), + m_axi_rlast => auto_us_to_s00_couplers_RLAST, + m_axi_rready => auto_us_to_s00_couplers_RREADY, + m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0), + m_axi_rvalid => auto_us_to_s00_couplers_RVALID, + m_axi_wdata(63 downto 0) => auto_us_to_s00_couplers_WDATA(63 downto 0), + m_axi_wlast => auto_us_to_s00_couplers_WLAST, + m_axi_wready => auto_us_to_s00_couplers_WREADY, + m_axi_wstrb(7 downto 0) => auto_us_to_s00_couplers_WSTRB(7 downto 0), + m_axi_wvalid => auto_us_to_s00_couplers_WVALID, + s_axi_aclk => S_ACLK_1, + s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0), + s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0), + s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0), + s_axi_aresetn => S_ARESETN_1, + s_axi_arid(3 downto 0) => s00_couplers_to_auto_us_ARID(3 downto 0), + s_axi_arlen(3 downto 0) => s00_couplers_to_auto_us_ARLEN(3 downto 0), + s_axi_arlock(1 downto 0) => B"00", + s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0), + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => s00_couplers_to_auto_us_ARREADY, + s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0), + s_axi_arvalid => s00_couplers_to_auto_us_ARVALID, + s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_us_AWADDR(31 downto 0), + s_axi_awburst(1 downto 0) => s00_couplers_to_auto_us_AWBURST(1 downto 0), + s_axi_awcache(3 downto 0) => s00_couplers_to_auto_us_AWCACHE(3 downto 0), + s_axi_awid(3 downto 0) => B"0000", + s_axi_awlen(3 downto 0) => s00_couplers_to_auto_us_AWLEN(3 downto 0), + s_axi_awlock(1 downto 0) => B"00", + s_axi_awprot(2 downto 0) => s00_couplers_to_auto_us_AWPROT(2 downto 0), + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => s00_couplers_to_auto_us_AWREADY, + s_axi_awsize(2 downto 0) => s00_couplers_to_auto_us_AWSIZE(2 downto 0), + s_axi_awvalid => s00_couplers_to_auto_us_AWVALID, + s_axi_bid(3 downto 0) => NLW_auto_us_s_axi_bid_UNCONNECTED(3 downto 0), + s_axi_bready => s00_couplers_to_auto_us_BREADY, + s_axi_bresp(1 downto 0) => s00_couplers_to_auto_us_BRESP(1 downto 0), + s_axi_bvalid => s00_couplers_to_auto_us_BVALID, + s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0), + s_axi_rid(3 downto 0) => s00_couplers_to_auto_us_RID(3 downto 0), + s_axi_rlast => s00_couplers_to_auto_us_RLAST, + s_axi_rready => s00_couplers_to_auto_us_RREADY, + s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0), + s_axi_rvalid => s00_couplers_to_auto_us_RVALID, + s_axi_wdata(31 downto 0) => s00_couplers_to_auto_us_WDATA(31 downto 0), + s_axi_wlast => s00_couplers_to_auto_us_WLAST, + s_axi_wready => s00_couplers_to_auto_us_WREADY, + s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_us_WSTRB(3 downto 0), + s_axi_wvalid => s00_couplers_to_auto_us_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity s00_couplers_imp_ZZSSAO is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_rlast : out STD_LOGIC; + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S_AXI_wlast : in STD_LOGIC; + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end s00_couplers_imp_ZZSSAO; + +architecture STRUCTURE of s00_couplers_imp_ZZSSAO is + component design_3_auto_pc_0 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC + ); + end component design_3_auto_pc_0; + signal S_ACLK_1 : STD_LOGIC; + signal S_ARESETN_1 : STD_LOGIC; + signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC; + signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC; + signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC; + signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC; + signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC; + signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC; + signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC; + signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC; + signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC; + signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0); + M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0); + M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0); + M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0); + M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID; + M_AXI_bready <= auto_pc_to_s00_couplers_BREADY; + M_AXI_rready <= auto_pc_to_s00_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID; + S_ACLK_1 <= S_ACLK; + S_ARESETN_1 <= S_ARESETN; + S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY; + S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY; + S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0); + S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0); + S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID; + S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0); + S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0); + S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST; + S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0); + S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID; + S_AXI_wready <= s00_couplers_to_auto_pc_WREADY; + auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready; + auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready; + auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid; + auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid; + auto_pc_to_s00_couplers_WREADY <= M_AXI_wready; + s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); + s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); + s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); + s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); + s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0); + s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); + s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); + s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); + s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; + s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); + s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); + s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); + s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); + s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0); + s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); + s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); + s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); + s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; + s00_couplers_to_auto_pc_BREADY <= S_AXI_bready; + s00_couplers_to_auto_pc_RREADY <= S_AXI_rready; + s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0); + s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; + s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; +auto_pc: component design_3_auto_pc_0 + port map ( + aclk => S_ACLK_1, + aresetn => S_ARESETN_1, + m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0), + m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0), + m_axi_arready => auto_pc_to_s00_couplers_ARREADY, + m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID, + m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0), + m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0), + m_axi_awready => auto_pc_to_s00_couplers_AWREADY, + m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID, + m_axi_bready => auto_pc_to_s00_couplers_BREADY, + m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0), + m_axi_bvalid => auto_pc_to_s00_couplers_BVALID, + m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0), + m_axi_rready => auto_pc_to_s00_couplers_RREADY, + m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0), + m_axi_rvalid => auto_pc_to_s00_couplers_RVALID, + m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0), + m_axi_wready => auto_pc_to_s00_couplers_WREADY, + m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0), + m_axi_wvalid => auto_pc_to_s00_couplers_WVALID, + s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0), + s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0), + s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0), + s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0), + s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0), + s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0), + s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0), + s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0), + s_axi_arready => s00_couplers_to_auto_pc_ARREADY, + s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0), + s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID, + s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0), + s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0), + s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0), + s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0), + s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0), + s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0), + s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0), + s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0), + s_axi_awready => s00_couplers_to_auto_pc_AWREADY, + s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0), + s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID, + s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0), + s_axi_bready => s00_couplers_to_auto_pc_BREADY, + s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0), + s_axi_bvalid => s00_couplers_to_auto_pc_BVALID, + s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0), + s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0), + s_axi_rlast => s00_couplers_to_auto_pc_RLAST, + s_axi_rready => s00_couplers_to_auto_pc_RREADY, + s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0), + s_axi_rvalid => s00_couplers_to_auto_pc_RVALID, + s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0), + s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0), + s_axi_wlast => s00_couplers_to_auto_pc_WLAST, + s_axi_wready => s00_couplers_to_auto_pc_WREADY, + s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0), + s_axi_wvalid => s00_couplers_to_auto_pc_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_3_axi_interconnect_0_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M00_ACLK : in STD_LOGIC; + M00_ARESETN : in STD_LOGIC; + M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arready : in STD_LOGIC; + M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_arvalid : out STD_LOGIC; + M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awready : in STD_LOGIC; + M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awvalid : out STD_LOGIC; + M00_AXI_bready : out STD_LOGIC; + M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_bvalid : in STD_LOGIC; + M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_rlast : in STD_LOGIC; + M00_AXI_rready : out STD_LOGIC; + M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_rvalid : in STD_LOGIC; + M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_wlast : out STD_LOGIC; + M00_AXI_wready : in STD_LOGIC; + M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M00_AXI_wvalid : out STD_LOGIC; + S00_ACLK : in STD_LOGIC; + S00_ARESETN : in STD_LOGIC; + S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arready : out STD_LOGIC; + S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arvalid : in STD_LOGIC; + S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awready : out STD_LOGIC; + S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awvalid : in STD_LOGIC; + S00_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI_bready : in STD_LOGIC; + S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_bvalid : out STD_LOGIC; + S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI_rlast : out STD_LOGIC; + S00_AXI_rready : in STD_LOGIC; + S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_rvalid : out STD_LOGIC; + S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_wlast : in STD_LOGIC; + S00_AXI_wready : out STD_LOGIC; + S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_wvalid : in STD_LOGIC + ); +end design_3_axi_interconnect_0_0; + +architecture STRUCTURE of design_3_axi_interconnect_0_0 is + signal S00_ACLK_1 : STD_LOGIC; + signal S00_ARESETN_1 : STD_LOGIC; + signal axi_interconnect_0_ACLK_net : STD_LOGIC; + signal axi_interconnect_0_ARESETN_net : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC; + signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_RLAST : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_WLAST : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC; + signal s00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC; +begin + M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0); + M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0); + M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0); + M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARLEN(3 downto 0); + M00_AXI_arlock(1 downto 0) <= s00_couplers_to_axi_interconnect_0_ARLOCK(1 downto 0); + M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0); + M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0); + M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0); + M00_AXI_arvalid <= s00_couplers_to_axi_interconnect_0_ARVALID; + M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0); + M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0); + M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0); + M00_AXI_awlen(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWLEN(3 downto 0); + M00_AXI_awlock(1 downto 0) <= s00_couplers_to_axi_interconnect_0_AWLOCK(1 downto 0); + M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0); + M00_AXI_awqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0); + M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0); + M00_AXI_awvalid <= s00_couplers_to_axi_interconnect_0_AWVALID; + M00_AXI_bready <= s00_couplers_to_axi_interconnect_0_BREADY; + M00_AXI_rready <= s00_couplers_to_axi_interconnect_0_RREADY; + M00_AXI_wdata(63 downto 0) <= s00_couplers_to_axi_interconnect_0_WDATA(63 downto 0); + M00_AXI_wlast <= s00_couplers_to_axi_interconnect_0_WLAST; + M00_AXI_wstrb(7 downto 0) <= s00_couplers_to_axi_interconnect_0_WSTRB(7 downto 0); + M00_AXI_wvalid <= s00_couplers_to_axi_interconnect_0_WVALID; + S00_ACLK_1 <= S00_ACLK; + S00_ARESETN_1 <= S00_ARESETN; + S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY; + S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY; + S00_AXI_bid(0) <= axi_interconnect_0_to_s00_couplers_BID(0); + S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0); + S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID; + S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0); + S00_AXI_rid(0) <= axi_interconnect_0_to_s00_couplers_RID(0); + S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST; + S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0); + S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID; + S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY; + axi_interconnect_0_ACLK_net <= M00_ACLK; + axi_interconnect_0_ARESETN_net <= M00_ARESETN; + axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); + axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); + axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); + axi_interconnect_0_to_s00_couplers_ARID(0) <= S00_AXI_arid(0); + axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); + axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); + axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); + axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid; + axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); + axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); + axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); + axi_interconnect_0_to_s00_couplers_AWID(0) <= S00_AXI_awid(0); + axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); + axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); + axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); + axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid; + axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready; + axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready; + axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); + axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast; + axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); + axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid; + s00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready; + s00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready; + s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); + s00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid; + s00_couplers_to_axi_interconnect_0_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0); + s00_couplers_to_axi_interconnect_0_RLAST <= M00_AXI_rlast; + s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); + s00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid; + s00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready; +s00_couplers: entity work.s00_couplers_imp_1UA4Y98 + port map ( + M_ACLK => axi_interconnect_0_ACLK_net, + M_ARESETN => axi_interconnect_0_ARESETN_net, + M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0), + M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARLEN(3 downto 0), + M_AXI_arlock(1 downto 0) => s00_couplers_to_axi_interconnect_0_ARLOCK(1 downto 0), + M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0), + M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0), + M_AXI_arready => s00_couplers_to_axi_interconnect_0_ARREADY, + M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0), + M_AXI_arvalid => s00_couplers_to_axi_interconnect_0_ARVALID, + M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0), + M_AXI_awlen(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWLEN(3 downto 0), + M_AXI_awlock(1 downto 0) => s00_couplers_to_axi_interconnect_0_AWLOCK(1 downto 0), + M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0), + M_AXI_awqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0), + M_AXI_awready => s00_couplers_to_axi_interconnect_0_AWREADY, + M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0), + M_AXI_awvalid => s00_couplers_to_axi_interconnect_0_AWVALID, + M_AXI_bready => s00_couplers_to_axi_interconnect_0_BREADY, + M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0), + M_AXI_bvalid => s00_couplers_to_axi_interconnect_0_BVALID, + M_AXI_rdata(63 downto 0) => s00_couplers_to_axi_interconnect_0_RDATA(63 downto 0), + M_AXI_rlast => s00_couplers_to_axi_interconnect_0_RLAST, + M_AXI_rready => s00_couplers_to_axi_interconnect_0_RREADY, + M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0), + M_AXI_rvalid => s00_couplers_to_axi_interconnect_0_RVALID, + M_AXI_wdata(63 downto 0) => s00_couplers_to_axi_interconnect_0_WDATA(63 downto 0), + M_AXI_wlast => s00_couplers_to_axi_interconnect_0_WLAST, + M_AXI_wready => s00_couplers_to_axi_interconnect_0_WREADY, + M_AXI_wstrb(7 downto 0) => s00_couplers_to_axi_interconnect_0_WSTRB(7 downto 0), + M_AXI_wvalid => s00_couplers_to_axi_interconnect_0_WVALID, + S_ACLK => S00_ACLK_1, + S_ARESETN => S00_ARESETN_1, + S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0), + S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0), + S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0), + S_AXI_arid(0) => axi_interconnect_0_to_s00_couplers_ARID(0), + S_AXI_arlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0), + S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0), + S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY, + S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0), + S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID, + S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0), + S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0), + S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0), + S_AXI_awid(0) => axi_interconnect_0_to_s00_couplers_AWID(0), + S_AXI_awlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0), + S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0), + S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY, + S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0), + S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID, + S_AXI_bid(0) => axi_interconnect_0_to_s00_couplers_BID(0), + S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY, + S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0), + S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID, + S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0), + S_AXI_rid(0) => axi_interconnect_0_to_s00_couplers_RID(0), + S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST, + S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY, + S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0), + S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID, + S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0), + S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST, + S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0), + S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_3_axi_mem_intercon_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M00_ACLK : in STD_LOGIC; + M00_ARESETN : in STD_LOGIC; + M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arready : in STD_LOGIC; + M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_arvalid : out STD_LOGIC; + M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awready : in STD_LOGIC; + M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awvalid : out STD_LOGIC; + M00_AXI_bready : out STD_LOGIC; + M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_bvalid : in STD_LOGIC; + M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_rlast : in STD_LOGIC; + M00_AXI_rready : out STD_LOGIC; + M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_rvalid : in STD_LOGIC; + M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_wlast : out STD_LOGIC; + M00_AXI_wready : in STD_LOGIC; + M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M00_AXI_wvalid : out STD_LOGIC; + S00_ACLK : in STD_LOGIC; + S00_ARESETN : in STD_LOGIC; + S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arready : out STD_LOGIC; + S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arvalid : in STD_LOGIC; + S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awready : out STD_LOGIC; + S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awvalid : in STD_LOGIC; + S00_AXI_bready : in STD_LOGIC; + S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_bvalid : out STD_LOGIC; + S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_rlast : out STD_LOGIC; + S00_AXI_rready : in STD_LOGIC; + S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_rvalid : out STD_LOGIC; + S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_wlast : in STD_LOGIC; + S00_AXI_wready : out STD_LOGIC; + S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_wvalid : in STD_LOGIC + ); +end design_3_axi_mem_intercon_0; + +architecture STRUCTURE of design_3_axi_mem_intercon_0 is + signal S00_ACLK_1 : STD_LOGIC; + signal S00_ARESETN_1 : STD_LOGIC; + signal axi_mem_intercon_ACLK_net : STD_LOGIC; + signal axi_mem_intercon_ARESETN_net : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC; + signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC; + signal s00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC; +begin + M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0); + M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0); + M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0); + M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0); + M00_AXI_arlock(1 downto 0) <= s00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0); + M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0); + M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0); + M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0); + M00_AXI_arvalid <= s00_couplers_to_axi_mem_intercon_ARVALID; + M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0); + M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0); + M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0); + M00_AXI_awlen(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0); + M00_AXI_awlock(1 downto 0) <= s00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0); + M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0); + M00_AXI_awqos(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0); + M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0); + M00_AXI_awvalid <= s00_couplers_to_axi_mem_intercon_AWVALID; + M00_AXI_bready <= s00_couplers_to_axi_mem_intercon_BREADY; + M00_AXI_rready <= s00_couplers_to_axi_mem_intercon_RREADY; + M00_AXI_wdata(63 downto 0) <= s00_couplers_to_axi_mem_intercon_WDATA(63 downto 0); + M00_AXI_wlast <= s00_couplers_to_axi_mem_intercon_WLAST; + M00_AXI_wstrb(7 downto 0) <= s00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0); + M00_AXI_wvalid <= s00_couplers_to_axi_mem_intercon_WVALID; + S00_ACLK_1 <= S00_ACLK; + S00_ARESETN_1 <= S00_ARESETN; + S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY; + S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY; + S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0); + S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID; + S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0); + S00_AXI_rid(3 downto 0) <= axi_mem_intercon_to_s00_couplers_RID(3 downto 0); + S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST; + S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0); + S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID; + S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY; + axi_mem_intercon_ACLK_net <= M00_ACLK; + axi_mem_intercon_ARESETN_net <= M00_ARESETN; + axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); + axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); + axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); + axi_mem_intercon_to_s00_couplers_ARID(3 downto 0) <= S00_AXI_arid(3 downto 0); + axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); + axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); + axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); + axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid; + axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); + axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); + axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); + axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); + axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); + axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); + axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid; + axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready; + axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready; + axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); + axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast; + axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); + axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid; + s00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready; + s00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready; + s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); + s00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid; + s00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0); + s00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast; + s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); + s00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid; + s00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready; +s00_couplers: entity work.s00_couplers_imp_1VXU3HN + port map ( + M_ACLK => axi_mem_intercon_ACLK_net, + M_ARESETN => axi_mem_intercon_ARESETN_net, + M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0), + M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0), + M_AXI_arlock(1 downto 0) => s00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0), + M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0), + M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0), + M_AXI_arready => s00_couplers_to_axi_mem_intercon_ARREADY, + M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0), + M_AXI_arvalid => s00_couplers_to_axi_mem_intercon_ARVALID, + M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0), + M_AXI_awlen(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0), + M_AXI_awlock(1 downto 0) => s00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0), + M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0), + M_AXI_awqos(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0), + M_AXI_awready => s00_couplers_to_axi_mem_intercon_AWREADY, + M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0), + M_AXI_awvalid => s00_couplers_to_axi_mem_intercon_AWVALID, + M_AXI_bready => s00_couplers_to_axi_mem_intercon_BREADY, + M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0), + M_AXI_bvalid => s00_couplers_to_axi_mem_intercon_BVALID, + M_AXI_rdata(63 downto 0) => s00_couplers_to_axi_mem_intercon_RDATA(63 downto 0), + M_AXI_rlast => s00_couplers_to_axi_mem_intercon_RLAST, + M_AXI_rready => s00_couplers_to_axi_mem_intercon_RREADY, + M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0), + M_AXI_rvalid => s00_couplers_to_axi_mem_intercon_RVALID, + M_AXI_wdata(63 downto 0) => s00_couplers_to_axi_mem_intercon_WDATA(63 downto 0), + M_AXI_wlast => s00_couplers_to_axi_mem_intercon_WLAST, + M_AXI_wready => s00_couplers_to_axi_mem_intercon_WREADY, + M_AXI_wstrb(7 downto 0) => s00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0), + M_AXI_wvalid => s00_couplers_to_axi_mem_intercon_WVALID, + S_ACLK => S00_ACLK_1, + S_ARESETN => S00_ARESETN_1, + S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0), + S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0), + S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0), + S_AXI_arid(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARID(3 downto 0), + S_AXI_arlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0), + S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0), + S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY, + S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0), + S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID, + S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0), + S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0), + S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0), + S_AXI_awlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0), + S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0), + S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY, + S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0), + S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID, + S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY, + S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0), + S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID, + S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0), + S_AXI_rid(3 downto 0) => axi_mem_intercon_to_s00_couplers_RID(3 downto 0), + S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST, + S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY, + S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0), + S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID, + S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0), + S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST, + S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0), + S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_3_ps7_0_axi_periph_0 is + port ( + ACLK : in STD_LOGIC; + ARESETN : in STD_LOGIC; + M00_ACLK : in STD_LOGIC; + M00_ARESETN : in STD_LOGIC; + M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_arready : in STD_LOGIC; + M00_AXI_arvalid : out STD_LOGIC; + M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_awready : in STD_LOGIC; + M00_AXI_awvalid : out STD_LOGIC; + M00_AXI_bready : out STD_LOGIC; + M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_bvalid : in STD_LOGIC; + M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_rready : out STD_LOGIC; + M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_rvalid : in STD_LOGIC; + M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_wready : in STD_LOGIC; + M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_wvalid : out STD_LOGIC; + M01_ACLK : in STD_LOGIC; + M01_ARESETN : in STD_LOGIC; + M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_arready : in STD_LOGIC; + M01_AXI_arvalid : out STD_LOGIC; + M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_awready : in STD_LOGIC; + M01_AXI_awvalid : out STD_LOGIC; + M01_AXI_bready : out STD_LOGIC; + M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M01_AXI_bvalid : in STD_LOGIC; + M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_rready : out STD_LOGIC; + M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M01_AXI_rvalid : in STD_LOGIC; + M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_wready : in STD_LOGIC; + M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M01_AXI_wvalid : out STD_LOGIC; + M02_ACLK : in STD_LOGIC; + M02_ARESETN : in STD_LOGIC; + M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_arready : in STD_LOGIC; + M02_AXI_arvalid : out STD_LOGIC; + M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_awready : in STD_LOGIC; + M02_AXI_awvalid : out STD_LOGIC; + M02_AXI_bready : out STD_LOGIC; + M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M02_AXI_bvalid : in STD_LOGIC; + M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_rready : out STD_LOGIC; + M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M02_AXI_rvalid : in STD_LOGIC; + M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_wready : in STD_LOGIC; + M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M02_AXI_wvalid : out STD_LOGIC; + S00_ACLK : in STD_LOGIC; + S00_ARESETN : in STD_LOGIC; + S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arready : out STD_LOGIC; + S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arvalid : in STD_LOGIC; + S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awready : out STD_LOGIC; + S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awvalid : in STD_LOGIC; + S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_bready : in STD_LOGIC; + S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_bvalid : out STD_LOGIC; + S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_rlast : out STD_LOGIC; + S00_AXI_rready : in STD_LOGIC; + S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_rvalid : out STD_LOGIC; + S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_wlast : in STD_LOGIC; + S00_AXI_wready : out STD_LOGIC; + S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_wvalid : in STD_LOGIC + ); +end design_3_ps7_0_axi_periph_0; + +architecture STRUCTURE of design_3_ps7_0_axi_periph_0 is + component design_3_xbar_0 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + end component design_3_xbar_0; + signal m00_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC; + signal m00_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC; + signal m01_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m01_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC; + signal m02_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m02_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC; + signal ps7_0_axi_periph_ACLK_net : STD_LOGIC; + signal ps7_0_axi_periph_ARESETN_net : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC; + signal ps7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC; + signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_ARVALID : STD_LOGIC; + signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_AWVALID : STD_LOGIC; + signal s00_couplers_to_xbar_BREADY : STD_LOGIC; + signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_xbar_RREADY : STD_LOGIC; + signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_xbar_WVALID : STD_LOGIC; + signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_ARREADY : STD_LOGIC; + signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_AWREADY : STD_LOGIC; + signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m00_couplers_BVALID : STD_LOGIC; + signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m00_couplers_RVALID : STD_LOGIC; + signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_WREADY : STD_LOGIC; + signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal xbar_to_m01_couplers_ARREADY : STD_LOGIC; + signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal xbar_to_m01_couplers_AWREADY : STD_LOGIC; + signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m01_couplers_BVALID : STD_LOGIC; + signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m01_couplers_RVALID : STD_LOGIC; + signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal xbar_to_m01_couplers_WREADY : STD_LOGIC; + signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 ); + signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 ); + signal xbar_to_m02_couplers_ARREADY : STD_LOGIC; + signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 ); + signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 ); + signal xbar_to_m02_couplers_AWREADY : STD_LOGIC; + signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 ); + signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 ); + signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m02_couplers_BVALID : STD_LOGIC; + signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 ); + signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m02_couplers_RVALID : STD_LOGIC; + signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 ); + signal xbar_to_m02_couplers_WREADY : STD_LOGIC; + signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 ); + signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 ); + signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); +begin + M00_AXI_araddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0); + M00_AXI_arvalid <= m00_couplers_to_ps7_0_axi_periph_ARVALID; + M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0); + M00_AXI_awvalid <= m00_couplers_to_ps7_0_axi_periph_AWVALID; + M00_AXI_bready <= m00_couplers_to_ps7_0_axi_periph_BREADY; + M00_AXI_rready <= m00_couplers_to_ps7_0_axi_periph_RREADY; + M00_AXI_wdata(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0); + M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0); + M00_AXI_wvalid <= m00_couplers_to_ps7_0_axi_periph_WVALID; + M01_AXI_araddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0); + M01_AXI_arvalid <= m01_couplers_to_ps7_0_axi_periph_ARVALID; + M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0); + M01_AXI_awvalid <= m01_couplers_to_ps7_0_axi_periph_AWVALID; + M01_AXI_bready <= m01_couplers_to_ps7_0_axi_periph_BREADY; + M01_AXI_rready <= m01_couplers_to_ps7_0_axi_periph_RREADY; + M01_AXI_wdata(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0); + M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0); + M01_AXI_wvalid <= m01_couplers_to_ps7_0_axi_periph_WVALID; + M02_AXI_araddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0); + M02_AXI_arvalid <= m02_couplers_to_ps7_0_axi_periph_ARVALID; + M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0); + M02_AXI_awvalid <= m02_couplers_to_ps7_0_axi_periph_AWVALID; + M02_AXI_bready <= m02_couplers_to_ps7_0_axi_periph_BREADY; + M02_AXI_rready <= m02_couplers_to_ps7_0_axi_periph_RREADY; + M02_AXI_wdata(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0); + M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0); + M02_AXI_wvalid <= m02_couplers_to_ps7_0_axi_periph_WVALID; + S00_AXI_arready <= ps7_0_axi_periph_to_s00_couplers_ARREADY; + S00_AXI_awready <= ps7_0_axi_periph_to_s00_couplers_AWREADY; + S00_AXI_bid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0); + S00_AXI_bresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0); + S00_AXI_bvalid <= ps7_0_axi_periph_to_s00_couplers_BVALID; + S00_AXI_rdata(31 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0); + S00_AXI_rid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0); + S00_AXI_rlast <= ps7_0_axi_periph_to_s00_couplers_RLAST; + S00_AXI_rresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0); + S00_AXI_rvalid <= ps7_0_axi_periph_to_s00_couplers_RVALID; + S00_AXI_wready <= ps7_0_axi_periph_to_s00_couplers_WREADY; + m00_couplers_to_ps7_0_axi_periph_ARREADY <= M00_AXI_arready; + m00_couplers_to_ps7_0_axi_periph_AWREADY <= M00_AXI_awready; + m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); + m00_couplers_to_ps7_0_axi_periph_BVALID <= M00_AXI_bvalid; + m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0); + m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); + m00_couplers_to_ps7_0_axi_periph_RVALID <= M00_AXI_rvalid; + m00_couplers_to_ps7_0_axi_periph_WREADY <= M00_AXI_wready; + m01_couplers_to_ps7_0_axi_periph_ARREADY <= M01_AXI_arready; + m01_couplers_to_ps7_0_axi_periph_AWREADY <= M01_AXI_awready; + m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0); + m01_couplers_to_ps7_0_axi_periph_BVALID <= M01_AXI_bvalid; + m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0); + m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0); + m01_couplers_to_ps7_0_axi_periph_RVALID <= M01_AXI_rvalid; + m01_couplers_to_ps7_0_axi_periph_WREADY <= M01_AXI_wready; + m02_couplers_to_ps7_0_axi_periph_ARREADY <= M02_AXI_arready; + m02_couplers_to_ps7_0_axi_periph_AWREADY <= M02_AXI_awready; + m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0); + m02_couplers_to_ps7_0_axi_periph_BVALID <= M02_AXI_bvalid; + m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0); + m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0); + m02_couplers_to_ps7_0_axi_periph_RVALID <= M02_AXI_rvalid; + m02_couplers_to_ps7_0_axi_periph_WREADY <= M02_AXI_wready; + ps7_0_axi_periph_ACLK_net <= ACLK; + ps7_0_axi_periph_ARESETN_net <= ARESETN; + ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); + ps7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid; + ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); + ps7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid; + ps7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready; + ps7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready; + ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); + ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0); + ps7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast; + ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); + ps7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid; +m00_couplers: entity work.m00_couplers_imp_XFWZ5U + port map ( + M_ACLK => ps7_0_axi_periph_ACLK_net, + M_ARESETN => ps7_0_axi_periph_ARESETN_net, + M_AXI_araddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0), + M_AXI_arready => m00_couplers_to_ps7_0_axi_periph_ARREADY, + M_AXI_arvalid => m00_couplers_to_ps7_0_axi_periph_ARVALID, + M_AXI_awaddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0), + M_AXI_awready => m00_couplers_to_ps7_0_axi_periph_AWREADY, + M_AXI_awvalid => m00_couplers_to_ps7_0_axi_periph_AWVALID, + M_AXI_bready => m00_couplers_to_ps7_0_axi_periph_BREADY, + M_AXI_bresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0), + M_AXI_bvalid => m00_couplers_to_ps7_0_axi_periph_BVALID, + M_AXI_rdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0), + M_AXI_rready => m00_couplers_to_ps7_0_axi_periph_RREADY, + M_AXI_rresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0), + M_AXI_rvalid => m00_couplers_to_ps7_0_axi_periph_RVALID, + M_AXI_wdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0), + M_AXI_wready => m00_couplers_to_ps7_0_axi_periph_WREADY, + M_AXI_wstrb(3 downto 0) => m00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0), + M_AXI_wvalid => m00_couplers_to_ps7_0_axi_periph_WVALID, + S_ACLK => ps7_0_axi_periph_ACLK_net, + S_ARESETN => ps7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), + S_AXI_arready => xbar_to_m00_couplers_ARREADY, + S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0), + S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), + S_AXI_awready => xbar_to_m00_couplers_AWREADY, + S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0), + S_AXI_bready => xbar_to_m00_couplers_BREADY(0), + S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), + S_AXI_bvalid => xbar_to_m00_couplers_BVALID, + S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0), + S_AXI_rready => xbar_to_m00_couplers_RREADY(0), + S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), + S_AXI_rvalid => xbar_to_m00_couplers_RVALID, + S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0), + S_AXI_wready => xbar_to_m00_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0), + S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0) + ); +m01_couplers: entity work.m01_couplers_imp_164MWV7 + port map ( + M_ACLK => ps7_0_axi_periph_ACLK_net, + M_ARESETN => ps7_0_axi_periph_ARESETN_net, + M_AXI_araddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0), + M_AXI_arready => m01_couplers_to_ps7_0_axi_periph_ARREADY, + M_AXI_arvalid => m01_couplers_to_ps7_0_axi_periph_ARVALID, + M_AXI_awaddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0), + M_AXI_awready => m01_couplers_to_ps7_0_axi_periph_AWREADY, + M_AXI_awvalid => m01_couplers_to_ps7_0_axi_periph_AWVALID, + M_AXI_bready => m01_couplers_to_ps7_0_axi_periph_BREADY, + M_AXI_bresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0), + M_AXI_bvalid => m01_couplers_to_ps7_0_axi_periph_BVALID, + M_AXI_rdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0), + M_AXI_rready => m01_couplers_to_ps7_0_axi_periph_RREADY, + M_AXI_rresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0), + M_AXI_rvalid => m01_couplers_to_ps7_0_axi_periph_RVALID, + M_AXI_wdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0), + M_AXI_wready => m01_couplers_to_ps7_0_axi_periph_WREADY, + M_AXI_wstrb(3 downto 0) => m01_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0), + M_AXI_wvalid => m01_couplers_to_ps7_0_axi_periph_WVALID, + S_ACLK => ps7_0_axi_periph_ACLK_net, + S_ARESETN => ps7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32), + S_AXI_arready => xbar_to_m01_couplers_ARREADY, + S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1), + S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32), + S_AXI_awready => xbar_to_m01_couplers_AWREADY, + S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1), + S_AXI_bready => xbar_to_m01_couplers_BREADY(1), + S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0), + S_AXI_bvalid => xbar_to_m01_couplers_BVALID, + S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0), + S_AXI_rready => xbar_to_m01_couplers_RREADY(1), + S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0), + S_AXI_rvalid => xbar_to_m01_couplers_RVALID, + S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32), + S_AXI_wready => xbar_to_m01_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4), + S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1) + ); +m02_couplers: entity work.m02_couplers_imp_YRUE81 + port map ( + M_ACLK => ps7_0_axi_periph_ACLK_net, + M_ARESETN => ps7_0_axi_periph_ARESETN_net, + M_AXI_araddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0), + M_AXI_arready => m02_couplers_to_ps7_0_axi_periph_ARREADY, + M_AXI_arvalid => m02_couplers_to_ps7_0_axi_periph_ARVALID, + M_AXI_awaddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0), + M_AXI_awready => m02_couplers_to_ps7_0_axi_periph_AWREADY, + M_AXI_awvalid => m02_couplers_to_ps7_0_axi_periph_AWVALID, + M_AXI_bready => m02_couplers_to_ps7_0_axi_periph_BREADY, + M_AXI_bresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0), + M_AXI_bvalid => m02_couplers_to_ps7_0_axi_periph_BVALID, + M_AXI_rdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0), + M_AXI_rready => m02_couplers_to_ps7_0_axi_periph_RREADY, + M_AXI_rresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0), + M_AXI_rvalid => m02_couplers_to_ps7_0_axi_periph_RVALID, + M_AXI_wdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0), + M_AXI_wready => m02_couplers_to_ps7_0_axi_periph_WREADY, + M_AXI_wstrb(3 downto 0) => m02_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0), + M_AXI_wvalid => m02_couplers_to_ps7_0_axi_periph_WVALID, + S_ACLK => ps7_0_axi_periph_ACLK_net, + S_ARESETN => ps7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64), + S_AXI_arready => xbar_to_m02_couplers_ARREADY, + S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2), + S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64), + S_AXI_awready => xbar_to_m02_couplers_AWREADY, + S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2), + S_AXI_bready => xbar_to_m02_couplers_BREADY(2), + S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0), + S_AXI_bvalid => xbar_to_m02_couplers_BVALID, + S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0), + S_AXI_rready => xbar_to_m02_couplers_RREADY(2), + S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0), + S_AXI_rvalid => xbar_to_m02_couplers_RVALID, + S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64), + S_AXI_wready => xbar_to_m02_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8), + S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2) + ); +s00_couplers: entity work.s00_couplers_imp_ZZSSAO + port map ( + M_ACLK => ps7_0_axi_periph_ACLK_net, + M_ARESETN => ps7_0_axi_periph_ARESETN_net, + M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), + M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), + M_AXI_arready => s00_couplers_to_xbar_ARREADY(0), + M_AXI_arvalid => s00_couplers_to_xbar_ARVALID, + M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0), + M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0), + M_AXI_awready => s00_couplers_to_xbar_AWREADY(0), + M_AXI_awvalid => s00_couplers_to_xbar_AWVALID, + M_AXI_bready => s00_couplers_to_xbar_BREADY, + M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0), + M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0), + M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0), + M_AXI_rready => s00_couplers_to_xbar_RREADY, + M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), + M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0), + M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0), + M_AXI_wready => s00_couplers_to_xbar_WREADY(0), + M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0), + M_AXI_wvalid => s00_couplers_to_xbar_WVALID, + S_ACLK => ps7_0_axi_periph_ACLK_net, + S_ARESETN => ps7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0), + S_AXI_arburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0), + S_AXI_arcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0), + S_AXI_arid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0), + S_AXI_arlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0), + S_AXI_arlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0), + S_AXI_arprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0), + S_AXI_arqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0), + S_AXI_arready => ps7_0_axi_periph_to_s00_couplers_ARREADY, + S_AXI_arsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0), + S_AXI_arvalid => ps7_0_axi_periph_to_s00_couplers_ARVALID, + S_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0), + S_AXI_awburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0), + S_AXI_awcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0), + S_AXI_awid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0), + S_AXI_awlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0), + S_AXI_awlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0), + S_AXI_awprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0), + S_AXI_awqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0), + S_AXI_awready => ps7_0_axi_periph_to_s00_couplers_AWREADY, + S_AXI_awsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0), + S_AXI_awvalid => ps7_0_axi_periph_to_s00_couplers_AWVALID, + S_AXI_bid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0), + S_AXI_bready => ps7_0_axi_periph_to_s00_couplers_BREADY, + S_AXI_bresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0), + S_AXI_bvalid => ps7_0_axi_periph_to_s00_couplers_BVALID, + S_AXI_rdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0), + S_AXI_rid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0), + S_AXI_rlast => ps7_0_axi_periph_to_s00_couplers_RLAST, + S_AXI_rready => ps7_0_axi_periph_to_s00_couplers_RREADY, + S_AXI_rresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0), + S_AXI_rvalid => ps7_0_axi_periph_to_s00_couplers_RVALID, + S_AXI_wdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0), + S_AXI_wid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0), + S_AXI_wlast => ps7_0_axi_periph_to_s00_couplers_WLAST, + S_AXI_wready => ps7_0_axi_periph_to_s00_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0), + S_AXI_wvalid => ps7_0_axi_periph_to_s00_couplers_WVALID + ); +xbar: component design_3_xbar_0 + port map ( + aclk => ps7_0_axi_periph_ACLK_net, + aresetn => ps7_0_axi_periph_ARESETN_net, + m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64), + m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32), + m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), + m_axi_arprot(8 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(8 downto 0), + m_axi_arready(2) => xbar_to_m02_couplers_ARREADY, + m_axi_arready(1) => xbar_to_m01_couplers_ARREADY, + m_axi_arready(0) => xbar_to_m00_couplers_ARREADY, + m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2), + m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1), + m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0), + m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64), + m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32), + m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), + m_axi_awprot(8 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(8 downto 0), + m_axi_awready(2) => xbar_to_m02_couplers_AWREADY, + m_axi_awready(1) => xbar_to_m01_couplers_AWREADY, + m_axi_awready(0) => xbar_to_m00_couplers_AWREADY, + m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2), + m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1), + m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0), + m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2), + m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1), + m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0), + m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0), + m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0), + m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), + m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID, + m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID, + m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID, + m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0), + m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0), + m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0), + m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2), + m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1), + m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0), + m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0), + m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0), + m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), + m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID, + m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID, + m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID, + m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64), + m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32), + m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0), + m_axi_wready(2) => xbar_to_m02_couplers_WREADY, + m_axi_wready(1) => xbar_to_m01_couplers_WREADY, + m_axi_wready(0) => xbar_to_m00_couplers_WREADY, + m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8), + m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4), + m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0), + m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2), + m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1), + m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0), + s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), + s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), + s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0), + s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID, + s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0), + s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0), + s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0), + s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID, + s_axi_bready(0) => s00_couplers_to_xbar_BREADY, + s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0), + s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0), + s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0), + s_axi_rready(0) => s00_couplers_to_xbar_RREADY, + s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), + s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0), + s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0), + s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0), + s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0), + s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity AXI_Intercon_imp_1AN5YJY is + port ( + ACLK : in STD_LOGIC; + M00_AXI1_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI1_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI1_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_arready : in STD_LOGIC; + M00_AXI1_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI1_arvalid : out STD_LOGIC; + M00_AXI1_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI1_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI1_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI1_awready : in STD_LOGIC; + M00_AXI1_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI1_awvalid : out STD_LOGIC; + M00_AXI1_bready : out STD_LOGIC; + M00_AXI1_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_bvalid : in STD_LOGIC; + M00_AXI1_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI1_rlast : in STD_LOGIC; + M00_AXI1_rready : out STD_LOGIC; + M00_AXI1_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI1_rvalid : in STD_LOGIC; + M00_AXI1_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI1_wlast : out STD_LOGIC; + M00_AXI1_wready : in STD_LOGIC; + M00_AXI1_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M00_AXI1_wvalid : out STD_LOGIC; + M00_AXI2_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI2_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI2_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_arready : in STD_LOGIC; + M00_AXI2_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI2_arvalid : out STD_LOGIC; + M00_AXI2_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI2_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI2_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI2_awready : in STD_LOGIC; + M00_AXI2_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI2_awvalid : out STD_LOGIC; + M00_AXI2_bready : out STD_LOGIC; + M00_AXI2_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_bvalid : in STD_LOGIC; + M00_AXI2_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI2_rlast : in STD_LOGIC; + M00_AXI2_rready : out STD_LOGIC; + M00_AXI2_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI2_rvalid : in STD_LOGIC; + M00_AXI2_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI2_wlast : out STD_LOGIC; + M00_AXI2_wready : in STD_LOGIC; + M00_AXI2_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M00_AXI2_wvalid : out STD_LOGIC; + M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_arready : in STD_LOGIC; + M00_AXI_arvalid : out STD_LOGIC; + M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_awready : in STD_LOGIC; + M00_AXI_awvalid : out STD_LOGIC; + M00_AXI_bready : out STD_LOGIC; + M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_bvalid : in STD_LOGIC; + M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_rready : out STD_LOGIC; + M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_rvalid : in STD_LOGIC; + M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_wready : in STD_LOGIC; + M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_wvalid : out STD_LOGIC; + M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_arready : in STD_LOGIC; + M01_AXI_arvalid : out STD_LOGIC; + M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_awready : in STD_LOGIC; + M01_AXI_awvalid : out STD_LOGIC; + M01_AXI_bready : out STD_LOGIC; + M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M01_AXI_bvalid : in STD_LOGIC; + M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_rready : out STD_LOGIC; + M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M01_AXI_rvalid : in STD_LOGIC; + M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M01_AXI_wready : in STD_LOGIC; + M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M01_AXI_wvalid : out STD_LOGIC; + M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_arready : in STD_LOGIC; + M02_AXI_arvalid : out STD_LOGIC; + M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_awready : in STD_LOGIC; + M02_AXI_awvalid : out STD_LOGIC; + M02_AXI_bready : out STD_LOGIC; + M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M02_AXI_bvalid : in STD_LOGIC; + M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_rready : out STD_LOGIC; + M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M02_AXI_rvalid : in STD_LOGIC; + M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M02_AXI_wready : in STD_LOGIC; + M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M02_AXI_wvalid : out STD_LOGIC; + S00_ARESETN : in STD_LOGIC; + S00_AXI1_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI1_arready : out STD_LOGIC; + S00_AXI1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI1_arvalid : in STD_LOGIC; + S00_AXI1_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI1_awready : out STD_LOGIC; + S00_AXI1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI1_awvalid : in STD_LOGIC; + S00_AXI1_bready : in STD_LOGIC; + S00_AXI1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI1_bvalid : out STD_LOGIC; + S00_AXI1_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI1_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_rlast : out STD_LOGIC; + S00_AXI1_rready : in STD_LOGIC; + S00_AXI1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI1_rvalid : out STD_LOGIC; + S00_AXI1_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI1_wlast : in STD_LOGIC; + S00_AXI1_wready : out STD_LOGIC; + S00_AXI1_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI1_wvalid : in STD_LOGIC; + S00_AXI2_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI2_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI2_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI2_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI2_arready : out STD_LOGIC; + S00_AXI2_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI2_arvalid : in STD_LOGIC; + S00_AXI2_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI2_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI2_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI2_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI2_awready : out STD_LOGIC; + S00_AXI2_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI2_awvalid : in STD_LOGIC; + S00_AXI2_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI2_bready : in STD_LOGIC; + S00_AXI2_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI2_bvalid : out STD_LOGIC; + S00_AXI2_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI2_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S00_AXI2_rlast : out STD_LOGIC; + S00_AXI2_rready : in STD_LOGIC; + S00_AXI2_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI2_rvalid : out STD_LOGIC; + S00_AXI2_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI2_wlast : in STD_LOGIC; + S00_AXI2_wready : out STD_LOGIC; + S00_AXI2_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI2_wvalid : in STD_LOGIC; + S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_arready : out STD_LOGIC; + S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_arvalid : in STD_LOGIC; + S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_awready : out STD_LOGIC; + S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S00_AXI_awvalid : in STD_LOGIC; + S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_bready : in STD_LOGIC; + S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_bvalid : out STD_LOGIC; + S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_rlast : out STD_LOGIC; + S00_AXI_rready : in STD_LOGIC; + S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S00_AXI_rvalid : out STD_LOGIC; + S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + S00_AXI_wlast : in STD_LOGIC; + S00_AXI_wready : out STD_LOGIC; + S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S00_AXI_wvalid : in STD_LOGIC + ); +end AXI_Intercon_imp_1AN5YJY; + +architecture STRUCTURE of AXI_Intercon_imp_1AN5YJY is + signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_ARREADY : STD_LOGIC; + signal Conn1_ARVALID : STD_LOGIC; + signal Conn1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_AWREADY : STD_LOGIC; + signal Conn1_AWVALID : STD_LOGIC; + signal Conn1_BREADY : STD_LOGIC; + signal Conn1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn1_BVALID : STD_LOGIC; + signal Conn1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_RREADY : STD_LOGIC; + signal Conn1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn1_RVALID : STD_LOGIC; + signal Conn1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn1_WREADY : STD_LOGIC; + signal Conn1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn1_WVALID : STD_LOGIC; + signal Conn2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_ARREADY : STD_LOGIC; + signal Conn2_ARVALID : STD_LOGIC; + signal Conn2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_AWREADY : STD_LOGIC; + signal Conn2_AWVALID : STD_LOGIC; + signal Conn2_BREADY : STD_LOGIC; + signal Conn2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_BVALID : STD_LOGIC; + signal Conn2_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_RREADY : STD_LOGIC; + signal Conn2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Conn2_RVALID : STD_LOGIC; + signal Conn2_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal Conn2_WREADY : STD_LOGIC; + signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Conn2_WVALID : STD_LOGIC; + signal S00_AXI2_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S00_AXI2_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S00_AXI2_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal S00_AXI2_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S00_AXI2_1_ARREADY : STD_LOGIC; + signal S00_AXI2_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S00_AXI2_1_ARVALID : STD_LOGIC; + signal S00_AXI2_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S00_AXI2_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S00_AXI2_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal S00_AXI2_1_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S00_AXI2_1_AWREADY : STD_LOGIC; + signal S00_AXI2_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal S00_AXI2_1_AWVALID : STD_LOGIC; + signal S00_AXI2_1_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal S00_AXI2_1_BREADY : STD_LOGIC; + signal S00_AXI2_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S00_AXI2_1_BVALID : STD_LOGIC; + signal S00_AXI2_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S00_AXI2_1_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal S00_AXI2_1_RLAST : STD_LOGIC; + signal S00_AXI2_1_RREADY : STD_LOGIC; + signal S00_AXI2_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S00_AXI2_1_RVALID : STD_LOGIC; + signal S00_AXI2_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S00_AXI2_1_WLAST : STD_LOGIC; + signal S00_AXI2_1_WREADY : STD_LOGIC; + signal S00_AXI2_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S00_AXI2_1_WVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_interconnect_0_M00_AXI_RLAST : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_interconnect_0_M00_AXI_WLAST : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC; + signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC; + signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC; + signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_BVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WVALID : STD_LOGIC; +begin + Conn1_ARREADY <= M01_AXI_arready; + Conn1_AWREADY <= M01_AXI_awready; + Conn1_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0); + Conn1_BVALID <= M01_AXI_bvalid; + Conn1_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0); + Conn1_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0); + Conn1_RVALID <= M01_AXI_rvalid; + Conn1_WREADY <= M01_AXI_wready; + Conn2_ARREADY <= M02_AXI_arready; + Conn2_AWREADY <= M02_AXI_awready; + Conn2_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0); + Conn2_BVALID <= M02_AXI_bvalid; + Conn2_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0); + Conn2_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0); + Conn2_RVALID <= M02_AXI_rvalid; + Conn2_WREADY <= M02_AXI_wready; + M00_AXI1_araddr(31 downto 0) <= axi_mem_intercon_M00_AXI_ARADDR(31 downto 0); + M00_AXI1_arburst(1 downto 0) <= axi_mem_intercon_M00_AXI_ARBURST(1 downto 0); + M00_AXI1_arcache(3 downto 0) <= axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0); + M00_AXI1_arlen(3 downto 0) <= axi_mem_intercon_M00_AXI_ARLEN(3 downto 0); + M00_AXI1_arlock(1 downto 0) <= axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0); + M00_AXI1_arprot(2 downto 0) <= axi_mem_intercon_M00_AXI_ARPROT(2 downto 0); + M00_AXI1_arqos(3 downto 0) <= axi_mem_intercon_M00_AXI_ARQOS(3 downto 0); + M00_AXI1_arsize(2 downto 0) <= axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0); + M00_AXI1_arvalid <= axi_mem_intercon_M00_AXI_ARVALID; + M00_AXI1_awaddr(31 downto 0) <= axi_mem_intercon_M00_AXI_AWADDR(31 downto 0); + M00_AXI1_awburst(1 downto 0) <= axi_mem_intercon_M00_AXI_AWBURST(1 downto 0); + M00_AXI1_awcache(3 downto 0) <= axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0); + M00_AXI1_awlen(3 downto 0) <= axi_mem_intercon_M00_AXI_AWLEN(3 downto 0); + M00_AXI1_awlock(1 downto 0) <= axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0); + M00_AXI1_awprot(2 downto 0) <= axi_mem_intercon_M00_AXI_AWPROT(2 downto 0); + M00_AXI1_awqos(3 downto 0) <= axi_mem_intercon_M00_AXI_AWQOS(3 downto 0); + M00_AXI1_awsize(2 downto 0) <= axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0); + M00_AXI1_awvalid <= axi_mem_intercon_M00_AXI_AWVALID; + M00_AXI1_bready <= axi_mem_intercon_M00_AXI_BREADY; + M00_AXI1_rready <= axi_mem_intercon_M00_AXI_RREADY; + M00_AXI1_wdata(63 downto 0) <= axi_mem_intercon_M00_AXI_WDATA(63 downto 0); + M00_AXI1_wlast <= axi_mem_intercon_M00_AXI_WLAST; + M00_AXI1_wstrb(7 downto 0) <= axi_mem_intercon_M00_AXI_WSTRB(7 downto 0); + M00_AXI1_wvalid <= axi_mem_intercon_M00_AXI_WVALID; + M00_AXI2_araddr(31 downto 0) <= axi_interconnect_0_M00_AXI_ARADDR(31 downto 0); + M00_AXI2_arburst(1 downto 0) <= axi_interconnect_0_M00_AXI_ARBURST(1 downto 0); + M00_AXI2_arcache(3 downto 0) <= axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0); + M00_AXI2_arlen(3 downto 0) <= axi_interconnect_0_M00_AXI_ARLEN(3 downto 0); + M00_AXI2_arlock(1 downto 0) <= axi_interconnect_0_M00_AXI_ARLOCK(1 downto 0); + M00_AXI2_arprot(2 downto 0) <= axi_interconnect_0_M00_AXI_ARPROT(2 downto 0); + M00_AXI2_arqos(3 downto 0) <= axi_interconnect_0_M00_AXI_ARQOS(3 downto 0); + M00_AXI2_arsize(2 downto 0) <= axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0); + M00_AXI2_arvalid <= axi_interconnect_0_M00_AXI_ARVALID; + M00_AXI2_awaddr(31 downto 0) <= axi_interconnect_0_M00_AXI_AWADDR(31 downto 0); + M00_AXI2_awburst(1 downto 0) <= axi_interconnect_0_M00_AXI_AWBURST(1 downto 0); + M00_AXI2_awcache(3 downto 0) <= axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0); + M00_AXI2_awlen(3 downto 0) <= axi_interconnect_0_M00_AXI_AWLEN(3 downto 0); + M00_AXI2_awlock(1 downto 0) <= axi_interconnect_0_M00_AXI_AWLOCK(1 downto 0); + M00_AXI2_awprot(2 downto 0) <= axi_interconnect_0_M00_AXI_AWPROT(2 downto 0); + M00_AXI2_awqos(3 downto 0) <= axi_interconnect_0_M00_AXI_AWQOS(3 downto 0); + M00_AXI2_awsize(2 downto 0) <= axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0); + M00_AXI2_awvalid <= axi_interconnect_0_M00_AXI_AWVALID; + M00_AXI2_bready <= axi_interconnect_0_M00_AXI_BREADY; + M00_AXI2_rready <= axi_interconnect_0_M00_AXI_RREADY; + M00_AXI2_wdata(63 downto 0) <= axi_interconnect_0_M00_AXI_WDATA(63 downto 0); + M00_AXI2_wlast <= axi_interconnect_0_M00_AXI_WLAST; + M00_AXI2_wstrb(7 downto 0) <= axi_interconnect_0_M00_AXI_WSTRB(7 downto 0); + M00_AXI2_wvalid <= axi_interconnect_0_M00_AXI_WVALID; + M00_AXI_araddr(31 downto 0) <= ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0); + M00_AXI_arvalid <= ps7_0_axi_periph_M00_AXI_ARVALID; + M00_AXI_awaddr(31 downto 0) <= ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0); + M00_AXI_awvalid <= ps7_0_axi_periph_M00_AXI_AWVALID; + M00_AXI_bready <= ps7_0_axi_periph_M00_AXI_BREADY; + M00_AXI_rready <= ps7_0_axi_periph_M00_AXI_RREADY; + M00_AXI_wdata(31 downto 0) <= ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0); + M00_AXI_wstrb(3 downto 0) <= ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0); + M00_AXI_wvalid <= ps7_0_axi_periph_M00_AXI_WVALID; + M01_AXI_araddr(31 downto 0) <= Conn1_ARADDR(31 downto 0); + M01_AXI_arvalid <= Conn1_ARVALID; + M01_AXI_awaddr(31 downto 0) <= Conn1_AWADDR(31 downto 0); + M01_AXI_awvalid <= Conn1_AWVALID; + M01_AXI_bready <= Conn1_BREADY; + M01_AXI_rready <= Conn1_RREADY; + M01_AXI_wdata(31 downto 0) <= Conn1_WDATA(31 downto 0); + M01_AXI_wstrb(3 downto 0) <= Conn1_WSTRB(3 downto 0); + M01_AXI_wvalid <= Conn1_WVALID; + M02_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0); + M02_AXI_arvalid <= Conn2_ARVALID; + M02_AXI_awaddr(31 downto 0) <= Conn2_AWADDR(31 downto 0); + M02_AXI_awvalid <= Conn2_AWVALID; + M02_AXI_bready <= Conn2_BREADY; + M02_AXI_rready <= Conn2_RREADY; + M02_AXI_wdata(31 downto 0) <= Conn2_WDATA(31 downto 0); + M02_AXI_wstrb(3 downto 0) <= Conn2_WSTRB(3 downto 0); + M02_AXI_wvalid <= Conn2_WVALID; + S00_AXI1_arready <= zynq_base_hdmi_0_M_AXI_ARREADY; + S00_AXI1_awready <= zynq_base_hdmi_0_M_AXI_AWREADY; + S00_AXI1_bresp(1 downto 0) <= zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0); + S00_AXI1_bvalid <= zynq_base_hdmi_0_M_AXI_BVALID; + S00_AXI1_rdata(31 downto 0) <= zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0); + S00_AXI1_rid(3 downto 0) <= zynq_base_hdmi_0_M_AXI_RID(3 downto 0); + S00_AXI1_rlast <= zynq_base_hdmi_0_M_AXI_RLAST; + S00_AXI1_rresp(1 downto 0) <= zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0); + S00_AXI1_rvalid <= zynq_base_hdmi_0_M_AXI_RVALID; + S00_AXI1_wready <= zynq_base_hdmi_0_M_AXI_WREADY; + S00_AXI2_1_ARADDR(31 downto 0) <= S00_AXI2_araddr(31 downto 0); + S00_AXI2_1_ARBURST(1 downto 0) <= S00_AXI2_arburst(1 downto 0); + S00_AXI2_1_ARCACHE(3 downto 0) <= S00_AXI2_arcache(3 downto 0); + S00_AXI2_1_ARID(0) <= S00_AXI2_arid(0); + S00_AXI2_1_ARLEN(3 downto 0) <= S00_AXI2_arlen(3 downto 0); + S00_AXI2_1_ARPROT(2 downto 0) <= S00_AXI2_arprot(2 downto 0); + S00_AXI2_1_ARSIZE(2 downto 0) <= S00_AXI2_arsize(2 downto 0); + S00_AXI2_1_ARVALID <= S00_AXI2_arvalid; + S00_AXI2_1_AWADDR(31 downto 0) <= S00_AXI2_awaddr(31 downto 0); + S00_AXI2_1_AWBURST(1 downto 0) <= S00_AXI2_awburst(1 downto 0); + S00_AXI2_1_AWCACHE(3 downto 0) <= S00_AXI2_awcache(3 downto 0); + S00_AXI2_1_AWID(0) <= S00_AXI2_awid(0); + S00_AXI2_1_AWLEN(3 downto 0) <= S00_AXI2_awlen(3 downto 0); + S00_AXI2_1_AWPROT(2 downto 0) <= S00_AXI2_awprot(2 downto 0); + S00_AXI2_1_AWSIZE(2 downto 0) <= S00_AXI2_awsize(2 downto 0); + S00_AXI2_1_AWVALID <= S00_AXI2_awvalid; + S00_AXI2_1_BREADY <= S00_AXI2_bready; + S00_AXI2_1_RREADY <= S00_AXI2_rready; + S00_AXI2_1_WDATA(31 downto 0) <= S00_AXI2_wdata(31 downto 0); + S00_AXI2_1_WLAST <= S00_AXI2_wlast; + S00_AXI2_1_WSTRB(3 downto 0) <= S00_AXI2_wstrb(3 downto 0); + S00_AXI2_1_WVALID <= S00_AXI2_wvalid; + S00_AXI2_arready <= S00_AXI2_1_ARREADY; + S00_AXI2_awready <= S00_AXI2_1_AWREADY; + S00_AXI2_bid(0) <= S00_AXI2_1_BID(0); + S00_AXI2_bresp(1 downto 0) <= S00_AXI2_1_BRESP(1 downto 0); + S00_AXI2_bvalid <= S00_AXI2_1_BVALID; + S00_AXI2_rdata(31 downto 0) <= S00_AXI2_1_RDATA(31 downto 0); + S00_AXI2_rid(0) <= S00_AXI2_1_RID(0); + S00_AXI2_rlast <= S00_AXI2_1_RLAST; + S00_AXI2_rresp(1 downto 0) <= S00_AXI2_1_RRESP(1 downto 0); + S00_AXI2_rvalid <= S00_AXI2_1_RVALID; + S00_AXI2_wready <= S00_AXI2_1_WREADY; + S00_AXI_arready <= processing_system7_0_M_AXI_GP0_ARREADY; + S00_AXI_awready <= processing_system7_0_M_AXI_GP0_AWREADY; + S00_AXI_bid(11 downto 0) <= processing_system7_0_M_AXI_GP0_BID(11 downto 0); + S00_AXI_bresp(1 downto 0) <= processing_system7_0_M_AXI_GP0_BRESP(1 downto 0); + S00_AXI_bvalid <= processing_system7_0_M_AXI_GP0_BVALID; + S00_AXI_rdata(31 downto 0) <= processing_system7_0_M_AXI_GP0_RDATA(31 downto 0); + S00_AXI_rid(11 downto 0) <= processing_system7_0_M_AXI_GP0_RID(11 downto 0); + S00_AXI_rlast <= processing_system7_0_M_AXI_GP0_RLAST; + S00_AXI_rresp(1 downto 0) <= processing_system7_0_M_AXI_GP0_RRESP(1 downto 0); + S00_AXI_rvalid <= processing_system7_0_M_AXI_GP0_RVALID; + S00_AXI_wready <= processing_system7_0_M_AXI_GP0_WREADY; + axi_interconnect_0_M00_AXI_ARREADY <= M00_AXI2_arready; + axi_interconnect_0_M00_AXI_AWREADY <= M00_AXI2_awready; + axi_interconnect_0_M00_AXI_BRESP(1 downto 0) <= M00_AXI2_bresp(1 downto 0); + axi_interconnect_0_M00_AXI_BVALID <= M00_AXI2_bvalid; + axi_interconnect_0_M00_AXI_RDATA(63 downto 0) <= M00_AXI2_rdata(63 downto 0); + axi_interconnect_0_M00_AXI_RLAST <= M00_AXI2_rlast; + axi_interconnect_0_M00_AXI_RRESP(1 downto 0) <= M00_AXI2_rresp(1 downto 0); + axi_interconnect_0_M00_AXI_RVALID <= M00_AXI2_rvalid; + axi_interconnect_0_M00_AXI_WREADY <= M00_AXI2_wready; + axi_mem_intercon_M00_AXI_ARREADY <= M00_AXI1_arready; + axi_mem_intercon_M00_AXI_AWREADY <= M00_AXI1_awready; + axi_mem_intercon_M00_AXI_BRESP(1 downto 0) <= M00_AXI1_bresp(1 downto 0); + axi_mem_intercon_M00_AXI_BVALID <= M00_AXI1_bvalid; + axi_mem_intercon_M00_AXI_RDATA(63 downto 0) <= M00_AXI1_rdata(63 downto 0); + axi_mem_intercon_M00_AXI_RLAST <= M00_AXI1_rlast; + axi_mem_intercon_M00_AXI_RRESP(1 downto 0) <= M00_AXI1_rresp(1 downto 0); + axi_mem_intercon_M00_AXI_RVALID <= M00_AXI1_rvalid; + axi_mem_intercon_M00_AXI_WREADY <= M00_AXI1_wready; + processing_system7_0_FCLK_CLK0 <= ACLK; + processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); + processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); + processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); + processing_system7_0_M_AXI_GP0_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0); + processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); + processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0); + processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); + processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0); + processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); + processing_system7_0_M_AXI_GP0_ARVALID <= S00_AXI_arvalid; + processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); + processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); + processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); + processing_system7_0_M_AXI_GP0_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0); + processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); + processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0); + processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); + processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0); + processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); + processing_system7_0_M_AXI_GP0_AWVALID <= S00_AXI_awvalid; + processing_system7_0_M_AXI_GP0_BREADY <= S00_AXI_bready; + processing_system7_0_M_AXI_GP0_RREADY <= S00_AXI_rready; + processing_system7_0_M_AXI_GP0_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); + processing_system7_0_M_AXI_GP0_WID(11 downto 0) <= S00_AXI_wid(11 downto 0); + processing_system7_0_M_AXI_GP0_WLAST <= S00_AXI_wlast; + processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); + processing_system7_0_M_AXI_GP0_WVALID <= S00_AXI_wvalid; + ps7_0_axi_periph_M00_AXI_ARREADY <= M00_AXI_arready; + ps7_0_axi_periph_M00_AXI_AWREADY <= M00_AXI_awready; + ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); + ps7_0_axi_periph_M00_AXI_BVALID <= M00_AXI_bvalid; + ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0); + ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); + ps7_0_axi_periph_M00_AXI_RVALID <= M00_AXI_rvalid; + ps7_0_axi_periph_M00_AXI_WREADY <= M00_AXI_wready; + rst_ps7_0_100M_peripheral_aresetn <= S00_ARESETN; + zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0) <= S00_AXI1_araddr(31 downto 0); + zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0) <= S00_AXI1_arburst(1 downto 0); + zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0) <= S00_AXI1_arcache(3 downto 0); + zynq_base_hdmi_0_M_AXI_ARID(3 downto 0) <= S00_AXI1_arid(3 downto 0); + zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0) <= S00_AXI1_arlen(3 downto 0); + zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0) <= S00_AXI1_arprot(2 downto 0); + zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0) <= S00_AXI1_arsize(2 downto 0); + zynq_base_hdmi_0_M_AXI_ARVALID <= S00_AXI1_arvalid; + zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0) <= S00_AXI1_awaddr(31 downto 0); + zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0) <= S00_AXI1_awburst(1 downto 0); + zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0) <= S00_AXI1_awcache(3 downto 0); + zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0) <= S00_AXI1_awlen(3 downto 0); + zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0) <= S00_AXI1_awprot(2 downto 0); + zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0) <= S00_AXI1_awsize(2 downto 0); + zynq_base_hdmi_0_M_AXI_AWVALID <= S00_AXI1_awvalid; + zynq_base_hdmi_0_M_AXI_BREADY <= S00_AXI1_bready; + zynq_base_hdmi_0_M_AXI_RREADY <= S00_AXI1_rready; + zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0) <= S00_AXI1_wdata(31 downto 0); + zynq_base_hdmi_0_M_AXI_WLAST <= S00_AXI1_wlast; + zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0) <= S00_AXI1_wstrb(3 downto 0); + zynq_base_hdmi_0_M_AXI_WVALID <= S00_AXI1_wvalid; +axi_interconnect_0: entity work.design_3_axi_interconnect_0_0 + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_ACLK => processing_system7_0_FCLK_CLK0, + M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0), + M00_AXI_arburst(1 downto 0) => axi_interconnect_0_M00_AXI_ARBURST(1 downto 0), + M00_AXI_arcache(3 downto 0) => axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0), + M00_AXI_arlen(3 downto 0) => axi_interconnect_0_M00_AXI_ARLEN(3 downto 0), + M00_AXI_arlock(1 downto 0) => axi_interconnect_0_M00_AXI_ARLOCK(1 downto 0), + M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0), + M00_AXI_arqos(3 downto 0) => axi_interconnect_0_M00_AXI_ARQOS(3 downto 0), + M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY, + M00_AXI_arsize(2 downto 0) => axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0), + M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID, + M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0), + M00_AXI_awburst(1 downto 0) => axi_interconnect_0_M00_AXI_AWBURST(1 downto 0), + M00_AXI_awcache(3 downto 0) => axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0), + M00_AXI_awlen(3 downto 0) => axi_interconnect_0_M00_AXI_AWLEN(3 downto 0), + M00_AXI_awlock(1 downto 0) => axi_interconnect_0_M00_AXI_AWLOCK(1 downto 0), + M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0), + M00_AXI_awqos(3 downto 0) => axi_interconnect_0_M00_AXI_AWQOS(3 downto 0), + M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY, + M00_AXI_awsize(2 downto 0) => axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0), + M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID, + M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY, + M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0), + M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID, + M00_AXI_rdata(63 downto 0) => axi_interconnect_0_M00_AXI_RDATA(63 downto 0), + M00_AXI_rlast => axi_interconnect_0_M00_AXI_RLAST, + M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY, + M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0), + M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID, + M00_AXI_wdata(63 downto 0) => axi_interconnect_0_M00_AXI_WDATA(63 downto 0), + M00_AXI_wlast => axi_interconnect_0_M00_AXI_WLAST, + M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY, + M00_AXI_wstrb(7 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(7 downto 0), + M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID, + S00_ACLK => processing_system7_0_FCLK_CLK0, + S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + S00_AXI_araddr(31 downto 0) => S00_AXI2_1_ARADDR(31 downto 0), + S00_AXI_arburst(1 downto 0) => S00_AXI2_1_ARBURST(1 downto 0), + S00_AXI_arcache(3 downto 0) => S00_AXI2_1_ARCACHE(3 downto 0), + S00_AXI_arid(0) => S00_AXI2_1_ARID(0), + S00_AXI_arlen(3 downto 0) => S00_AXI2_1_ARLEN(3 downto 0), + S00_AXI_arprot(2 downto 0) => S00_AXI2_1_ARPROT(2 downto 0), + S00_AXI_arready => S00_AXI2_1_ARREADY, + S00_AXI_arsize(2 downto 0) => S00_AXI2_1_ARSIZE(2 downto 0), + S00_AXI_arvalid => S00_AXI2_1_ARVALID, + S00_AXI_awaddr(31 downto 0) => S00_AXI2_1_AWADDR(31 downto 0), + S00_AXI_awburst(1 downto 0) => S00_AXI2_1_AWBURST(1 downto 0), + S00_AXI_awcache(3 downto 0) => S00_AXI2_1_AWCACHE(3 downto 0), + S00_AXI_awid(0) => S00_AXI2_1_AWID(0), + S00_AXI_awlen(3 downto 0) => S00_AXI2_1_AWLEN(3 downto 0), + S00_AXI_awprot(2 downto 0) => S00_AXI2_1_AWPROT(2 downto 0), + S00_AXI_awready => S00_AXI2_1_AWREADY, + S00_AXI_awsize(2 downto 0) => S00_AXI2_1_AWSIZE(2 downto 0), + S00_AXI_awvalid => S00_AXI2_1_AWVALID, + S00_AXI_bid(0) => S00_AXI2_1_BID(0), + S00_AXI_bready => S00_AXI2_1_BREADY, + S00_AXI_bresp(1 downto 0) => S00_AXI2_1_BRESP(1 downto 0), + S00_AXI_bvalid => S00_AXI2_1_BVALID, + S00_AXI_rdata(31 downto 0) => S00_AXI2_1_RDATA(31 downto 0), + S00_AXI_rid(0) => S00_AXI2_1_RID(0), + S00_AXI_rlast => S00_AXI2_1_RLAST, + S00_AXI_rready => S00_AXI2_1_RREADY, + S00_AXI_rresp(1 downto 0) => S00_AXI2_1_RRESP(1 downto 0), + S00_AXI_rvalid => S00_AXI2_1_RVALID, + S00_AXI_wdata(31 downto 0) => S00_AXI2_1_WDATA(31 downto 0), + S00_AXI_wlast => S00_AXI2_1_WLAST, + S00_AXI_wready => S00_AXI2_1_WREADY, + S00_AXI_wstrb(3 downto 0) => S00_AXI2_1_WSTRB(3 downto 0), + S00_AXI_wvalid => S00_AXI2_1_WVALID + ); +axi_mem_intercon: entity work.design_3_axi_mem_intercon_0 + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_ACLK => processing_system7_0_FCLK_CLK0, + M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), + M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), + M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), + M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), + M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), + M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), + M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), + M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY, + M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), + M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID, + M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), + M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), + M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), + M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), + M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), + M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), + M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), + M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY, + M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), + M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID, + M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY, + M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), + M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID, + M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), + M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST, + M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY, + M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), + M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID, + M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), + M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST, + M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY, + M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), + M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID, + S00_ACLK => processing_system7_0_FCLK_CLK0, + S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + S00_AXI_araddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0), + S00_AXI_arburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0), + S00_AXI_arcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0), + S00_AXI_arid(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARID(3 downto 0), + S00_AXI_arlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0), + S00_AXI_arprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0), + S00_AXI_arready => zynq_base_hdmi_0_M_AXI_ARREADY, + S00_AXI_arsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0), + S00_AXI_arvalid => zynq_base_hdmi_0_M_AXI_ARVALID, + S00_AXI_awaddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0), + S00_AXI_awburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0), + S00_AXI_awcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0), + S00_AXI_awlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0), + S00_AXI_awprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0), + S00_AXI_awready => zynq_base_hdmi_0_M_AXI_AWREADY, + S00_AXI_awsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0), + S00_AXI_awvalid => zynq_base_hdmi_0_M_AXI_AWVALID, + S00_AXI_bready => zynq_base_hdmi_0_M_AXI_BREADY, + S00_AXI_bresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0), + S00_AXI_bvalid => zynq_base_hdmi_0_M_AXI_BVALID, + S00_AXI_rdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0), + S00_AXI_rid(3 downto 0) => zynq_base_hdmi_0_M_AXI_RID(3 downto 0), + S00_AXI_rlast => zynq_base_hdmi_0_M_AXI_RLAST, + S00_AXI_rready => zynq_base_hdmi_0_M_AXI_RREADY, + S00_AXI_rresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0), + S00_AXI_rvalid => zynq_base_hdmi_0_M_AXI_RVALID, + S00_AXI_wdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0), + S00_AXI_wlast => zynq_base_hdmi_0_M_AXI_WLAST, + S00_AXI_wready => zynq_base_hdmi_0_M_AXI_WREADY, + S00_AXI_wstrb(3 downto 0) => zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0), + S00_AXI_wvalid => zynq_base_hdmi_0_M_AXI_WVALID + ); +ps7_0_axi_periph: entity work.design_3_ps7_0_axi_periph_0 + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_ACLK => processing_system7_0_FCLK_CLK0, + M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0), + M00_AXI_arready => ps7_0_axi_periph_M00_AXI_ARREADY, + M00_AXI_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID, + M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0), + M00_AXI_awready => ps7_0_axi_periph_M00_AXI_AWREADY, + M00_AXI_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID, + M00_AXI_bready => ps7_0_axi_periph_M00_AXI_BREADY, + M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), + M00_AXI_bvalid => ps7_0_axi_periph_M00_AXI_BVALID, + M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), + M00_AXI_rready => ps7_0_axi_periph_M00_AXI_RREADY, + M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), + M00_AXI_rvalid => ps7_0_axi_periph_M00_AXI_RVALID, + M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), + M00_AXI_wready => ps7_0_axi_periph_M00_AXI_WREADY, + M00_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), + M00_AXI_wvalid => ps7_0_axi_periph_M00_AXI_WVALID, + M01_ACLK => processing_system7_0_FCLK_CLK0, + M01_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M01_AXI_araddr(31 downto 0) => Conn1_ARADDR(31 downto 0), + M01_AXI_arready => Conn1_ARREADY, + M01_AXI_arvalid => Conn1_ARVALID, + M01_AXI_awaddr(31 downto 0) => Conn1_AWADDR(31 downto 0), + M01_AXI_awready => Conn1_AWREADY, + M01_AXI_awvalid => Conn1_AWVALID, + M01_AXI_bready => Conn1_BREADY, + M01_AXI_bresp(1 downto 0) => Conn1_BRESP(1 downto 0), + M01_AXI_bvalid => Conn1_BVALID, + M01_AXI_rdata(31 downto 0) => Conn1_RDATA(31 downto 0), + M01_AXI_rready => Conn1_RREADY, + M01_AXI_rresp(1 downto 0) => Conn1_RRESP(1 downto 0), + M01_AXI_rvalid => Conn1_RVALID, + M01_AXI_wdata(31 downto 0) => Conn1_WDATA(31 downto 0), + M01_AXI_wready => Conn1_WREADY, + M01_AXI_wstrb(3 downto 0) => Conn1_WSTRB(3 downto 0), + M01_AXI_wvalid => Conn1_WVALID, + M02_ACLK => processing_system7_0_FCLK_CLK0, + M02_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + M02_AXI_araddr(31 downto 0) => Conn2_ARADDR(31 downto 0), + M02_AXI_arready => Conn2_ARREADY, + M02_AXI_arvalid => Conn2_ARVALID, + M02_AXI_awaddr(31 downto 0) => Conn2_AWADDR(31 downto 0), + M02_AXI_awready => Conn2_AWREADY, + M02_AXI_awvalid => Conn2_AWVALID, + M02_AXI_bready => Conn2_BREADY, + M02_AXI_bresp(1 downto 0) => Conn2_BRESP(1 downto 0), + M02_AXI_bvalid => Conn2_BVALID, + M02_AXI_rdata(31 downto 0) => Conn2_RDATA(31 downto 0), + M02_AXI_rready => Conn2_RREADY, + M02_AXI_rresp(1 downto 0) => Conn2_RRESP(1 downto 0), + M02_AXI_rvalid => Conn2_RVALID, + M02_AXI_wdata(31 downto 0) => Conn2_WDATA(31 downto 0), + M02_AXI_wready => Conn2_WREADY, + M02_AXI_wstrb(3 downto 0) => Conn2_WSTRB(3 downto 0), + M02_AXI_wvalid => Conn2_WVALID, + S00_ACLK => processing_system7_0_FCLK_CLK0, + S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn, + S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), + S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), + S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), + S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), + S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), + S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), + S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), + S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), + S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY, + S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), + S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID, + S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), + S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), + S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), + S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), + S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), + S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), + S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), + S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), + S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY, + S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), + S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID, + S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), + S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY, + S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), + S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID, + S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), + S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), + S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST, + S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY, + S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), + S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID, + S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), + S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), + S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST, + S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY, + S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), + S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_3 is + port ( + BUTTON : in STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_cas_n : inout STD_LOGIC; + DDR_ck_n : inout STD_LOGIC; + DDR_ck_p : inout STD_LOGIC; + DDR_cke : inout STD_LOGIC; + DDR_cs_n : inout STD_LOGIC; + DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_odt : inout STD_LOGIC; + DDR_ras_n : inout STD_LOGIC; + DDR_reset_n : inout STD_LOGIC; + DDR_we_n : inout STD_LOGIC; + FIXED_IO_ddr_vrn : inout STD_LOGIC; + FIXED_IO_ddr_vrp : inout STD_LOGIC; + FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + FIXED_IO_ps_clk : inout STD_LOGIC; + FIXED_IO_ps_porb : inout STD_LOGIC; + FIXED_IO_ps_srstb : inout STD_LOGIC; + HDMI_CLK_N : out STD_LOGIC; + HDMI_CLK_P : out STD_LOGIC; + HDMI_DATA_N : out STD_LOGIC_VECTOR ( 2 downto 0 ); + HDMI_DATA_P : out STD_LOGIC_VECTOR ( 2 downto 0 ); + LED : out STD_LOGIC_VECTOR ( 3 downto 0 ); + RGB_LED : out STD_LOGIC_VECTOR ( 5 downto 0 ); + SWITCH : in STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of design_3 : entity is "design_3,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_3,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=27,numReposBlks=14,numNonXlnxBlks=1,numHierBlks=13,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of design_3 : entity is "design_3.hwdef"; +end design_3; + +architecture STRUCTURE of design_3 is + signal AXI_Intercon_M00_AXI2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal AXI_Intercon_M00_AXI2_ARVALID : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal AXI_Intercon_M00_AXI2_AWVALID : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_BREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_BVALID : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal AXI_Intercon_M00_AXI2_RLAST : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_RREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal AXI_Intercon_M00_AXI2_RVALID : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal AXI_Intercon_M00_AXI2_WLAST : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_WREADY : STD_LOGIC; + signal AXI_Intercon_M00_AXI2_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal AXI_Intercon_M00_AXI2_WVALID : STD_LOGIC; + signal BUTTON_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal SWITCH_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL1_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_ARREADY : STD_LOGIC; + signal S_AXIL1_1_ARVALID : STD_LOGIC; + signal S_AXIL1_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_AWREADY : STD_LOGIC; + signal S_AXIL1_1_AWVALID : STD_LOGIC; + signal S_AXIL1_1_BREADY : STD_LOGIC; + signal S_AXIL1_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL1_1_BVALID : STD_LOGIC; + signal S_AXIL1_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_RREADY : STD_LOGIC; + signal S_AXIL1_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL1_1_RVALID : STD_LOGIC; + signal S_AXIL1_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL1_1_WREADY : STD_LOGIC; + signal S_AXIL1_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL1_1_WVALID : STD_LOGIC; + signal S_AXIL_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_ARREADY : STD_LOGIC; + signal S_AXIL_1_ARVALID : STD_LOGIC; + signal S_AXIL_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_AWREADY : STD_LOGIC; + signal S_AXIL_1_AWVALID : STD_LOGIC; + signal S_AXIL_1_BREADY : STD_LOGIC; + signal S_AXIL_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL_1_BVALID : STD_LOGIC; + signal S_AXIL_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_RREADY : STD_LOGIC; + signal S_AXIL_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal S_AXIL_1_RVALID : STD_LOGIC; + signal S_AXIL_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXIL_1_WREADY : STD_LOGIC; + signal S_AXIL_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal S_AXIL_1_WVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal VideoSubsystem_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal VideoSubsystem_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal VideoSubsystem_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal VideoSubsystem_M_AXI_ARREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal VideoSubsystem_M_AXI_ARVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal VideoSubsystem_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal VideoSubsystem_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal VideoSubsystem_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal VideoSubsystem_M_AXI_AWREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal VideoSubsystem_M_AXI_AWVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal VideoSubsystem_M_AXI_BREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal VideoSubsystem_M_AXI_BVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal VideoSubsystem_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal VideoSubsystem_M_AXI_RLAST : STD_LOGIC; + signal VideoSubsystem_M_AXI_RREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal VideoSubsystem_M_AXI_RVALID : STD_LOGIC; + signal VideoSubsystem_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal VideoSubsystem_M_AXI_WLAST : STD_LOGIC; + signal VideoSubsystem_M_AXI_WREADY : STD_LOGIC; + signal VideoSubsystem_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal VideoSubsystem_M_AXI_WVALID : STD_LOGIC; + signal VideoSubsystem_VS2MM_INTERRUPT : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC; + signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_DDR_CAS_N : STD_LOGIC; + signal processing_system7_0_DDR_CKE : STD_LOGIC; + signal processing_system7_0_DDR_CK_N : STD_LOGIC; + signal processing_system7_0_DDR_CK_P : STD_LOGIC; + signal processing_system7_0_DDR_CS_N : STD_LOGIC; + signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_DDR_ODT : STD_LOGIC; + signal processing_system7_0_DDR_RAS_N : STD_LOGIC; + signal processing_system7_0_DDR_RESET_N : STD_LOGIC; + signal processing_system7_0_DDR_WE_N : STD_LOGIC; + signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; + signal processing_system7_0_FCLK_CLK3 : STD_LOGIC; + signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC; + signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC; + signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); + signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC; + signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC; + signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC; + signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC; + signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC; + signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); + signal zynq_base_hdmi_0_HDMI_CLK_N : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_CLK_P : STD_LOGIC; + signal zynq_base_hdmi_0_HDMI_DATA_N : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_HDMI_DATA_P : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_LED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_ARVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_AWVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_BVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_RVALID : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WLAST : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WREADY : STD_LOGIC; + signal zynq_base_hdmi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal zynq_base_hdmi_0_M_AXI_WVALID : STD_LOGIC; + signal zynq_base_hdmi_0_RGB_LED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal zynq_base_hdmi_0_VIDEO_INTERRUPT : STD_LOGIC; + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_INFO of DDR_cas_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; + attribute X_INTERFACE_INFO of DDR_ck_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; + attribute X_INTERFACE_INFO of DDR_ck_p : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; + attribute X_INTERFACE_INFO of DDR_cke : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; + attribute X_INTERFACE_INFO of DDR_cs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; + attribute X_INTERFACE_INFO of DDR_odt : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; + attribute X_INTERFACE_INFO of DDR_ras_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; + attribute X_INTERFACE_INFO of DDR_reset_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; + attribute X_INTERFACE_INFO of DDR_we_n : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; + attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrn : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; + attribute X_INTERFACE_PARAMETER : string; + attribute X_INTERFACE_PARAMETER of FIXED_IO_ddr_vrn : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; + attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrp : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; + attribute X_INTERFACE_INFO of FIXED_IO_ps_clk : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; + attribute X_INTERFACE_INFO of FIXED_IO_ps_porb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; + attribute X_INTERFACE_INFO of FIXED_IO_ps_srstb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; + attribute X_INTERFACE_INFO of DDR_addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; + attribute X_INTERFACE_PARAMETER of DDR_addr : signal is "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250"; + attribute X_INTERFACE_INFO of DDR_ba : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; + attribute X_INTERFACE_INFO of DDR_dm : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; + attribute X_INTERFACE_INFO of DDR_dq : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; + attribute X_INTERFACE_INFO of DDR_dqs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; + attribute X_INTERFACE_INFO of DDR_dqs_p : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; + attribute X_INTERFACE_INFO of FIXED_IO_mio : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; +begin + BUTTON_0_1(3 downto 0) <= BUTTON(3 downto 0); + HDMI_CLK_N <= zynq_base_hdmi_0_HDMI_CLK_N; + HDMI_CLK_P <= zynq_base_hdmi_0_HDMI_CLK_P; + HDMI_DATA_N(2 downto 0) <= zynq_base_hdmi_0_HDMI_DATA_N(2 downto 0); + HDMI_DATA_P(2 downto 0) <= zynq_base_hdmi_0_HDMI_DATA_P(2 downto 0); + LED(3 downto 0) <= zynq_base_hdmi_0_LED(3 downto 0); + RGB_LED(5 downto 0) <= zynq_base_hdmi_0_RGB_LED(5 downto 0); + SWITCH_0_1(3 downto 0) <= SWITCH(3 downto 0); +AXI_Intercon: entity work.AXI_Intercon_imp_1AN5YJY + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + M00_AXI1_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), + M00_AXI1_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), + M00_AXI1_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), + M00_AXI1_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), + M00_AXI1_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), + M00_AXI1_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), + M00_AXI1_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), + M00_AXI1_arready => axi_mem_intercon_M00_AXI_ARREADY, + M00_AXI1_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), + M00_AXI1_arvalid => axi_mem_intercon_M00_AXI_ARVALID, + M00_AXI1_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), + M00_AXI1_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), + M00_AXI1_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), + M00_AXI1_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), + M00_AXI1_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), + M00_AXI1_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), + M00_AXI1_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), + M00_AXI1_awready => axi_mem_intercon_M00_AXI_AWREADY, + M00_AXI1_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), + M00_AXI1_awvalid => axi_mem_intercon_M00_AXI_AWVALID, + M00_AXI1_bready => axi_mem_intercon_M00_AXI_BREADY, + M00_AXI1_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), + M00_AXI1_bvalid => axi_mem_intercon_M00_AXI_BVALID, + M00_AXI1_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), + M00_AXI1_rlast => axi_mem_intercon_M00_AXI_RLAST, + M00_AXI1_rready => axi_mem_intercon_M00_AXI_RREADY, + M00_AXI1_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), + M00_AXI1_rvalid => axi_mem_intercon_M00_AXI_RVALID, + M00_AXI1_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), + M00_AXI1_wlast => axi_mem_intercon_M00_AXI_WLAST, + M00_AXI1_wready => axi_mem_intercon_M00_AXI_WREADY, + M00_AXI1_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), + M00_AXI1_wvalid => axi_mem_intercon_M00_AXI_WVALID, + M00_AXI2_araddr(31 downto 0) => AXI_Intercon_M00_AXI2_ARADDR(31 downto 0), + M00_AXI2_arburst(1 downto 0) => AXI_Intercon_M00_AXI2_ARBURST(1 downto 0), + M00_AXI2_arcache(3 downto 0) => AXI_Intercon_M00_AXI2_ARCACHE(3 downto 0), + M00_AXI2_arlen(3 downto 0) => AXI_Intercon_M00_AXI2_ARLEN(3 downto 0), + M00_AXI2_arlock(1 downto 0) => AXI_Intercon_M00_AXI2_ARLOCK(1 downto 0), + M00_AXI2_arprot(2 downto 0) => AXI_Intercon_M00_AXI2_ARPROT(2 downto 0), + M00_AXI2_arqos(3 downto 0) => AXI_Intercon_M00_AXI2_ARQOS(3 downto 0), + M00_AXI2_arready => AXI_Intercon_M00_AXI2_ARREADY, + M00_AXI2_arsize(2 downto 0) => AXI_Intercon_M00_AXI2_ARSIZE(2 downto 0), + M00_AXI2_arvalid => AXI_Intercon_M00_AXI2_ARVALID, + M00_AXI2_awaddr(31 downto 0) => AXI_Intercon_M00_AXI2_AWADDR(31 downto 0), + M00_AXI2_awburst(1 downto 0) => AXI_Intercon_M00_AXI2_AWBURST(1 downto 0), + M00_AXI2_awcache(3 downto 0) => AXI_Intercon_M00_AXI2_AWCACHE(3 downto 0), + M00_AXI2_awlen(3 downto 0) => AXI_Intercon_M00_AXI2_AWLEN(3 downto 0), + M00_AXI2_awlock(1 downto 0) => AXI_Intercon_M00_AXI2_AWLOCK(1 downto 0), + M00_AXI2_awprot(2 downto 0) => AXI_Intercon_M00_AXI2_AWPROT(2 downto 0), + M00_AXI2_awqos(3 downto 0) => AXI_Intercon_M00_AXI2_AWQOS(3 downto 0), + M00_AXI2_awready => AXI_Intercon_M00_AXI2_AWREADY, + M00_AXI2_awsize(2 downto 0) => AXI_Intercon_M00_AXI2_AWSIZE(2 downto 0), + M00_AXI2_awvalid => AXI_Intercon_M00_AXI2_AWVALID, + M00_AXI2_bready => AXI_Intercon_M00_AXI2_BREADY, + M00_AXI2_bresp(1 downto 0) => AXI_Intercon_M00_AXI2_BRESP(1 downto 0), + M00_AXI2_bvalid => AXI_Intercon_M00_AXI2_BVALID, + M00_AXI2_rdata(63 downto 0) => AXI_Intercon_M00_AXI2_RDATA(63 downto 0), + M00_AXI2_rlast => AXI_Intercon_M00_AXI2_RLAST, + M00_AXI2_rready => AXI_Intercon_M00_AXI2_RREADY, + M00_AXI2_rresp(1 downto 0) => AXI_Intercon_M00_AXI2_RRESP(1 downto 0), + M00_AXI2_rvalid => AXI_Intercon_M00_AXI2_RVALID, + M00_AXI2_wdata(63 downto 0) => AXI_Intercon_M00_AXI2_WDATA(63 downto 0), + M00_AXI2_wlast => AXI_Intercon_M00_AXI2_WLAST, + M00_AXI2_wready => AXI_Intercon_M00_AXI2_WREADY, + M00_AXI2_wstrb(7 downto 0) => AXI_Intercon_M00_AXI2_WSTRB(7 downto 0), + M00_AXI2_wvalid => AXI_Intercon_M00_AXI2_WVALID, + M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0), + M00_AXI_arready => ps7_0_axi_periph_M00_AXI_ARREADY, + M00_AXI_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID, + M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0), + M00_AXI_awready => ps7_0_axi_periph_M00_AXI_AWREADY, + M00_AXI_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID, + M00_AXI_bready => ps7_0_axi_periph_M00_AXI_BREADY, + M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), + M00_AXI_bvalid => ps7_0_axi_periph_M00_AXI_BVALID, + M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), + M00_AXI_rready => ps7_0_axi_periph_M00_AXI_RREADY, + M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), + M00_AXI_rvalid => ps7_0_axi_periph_M00_AXI_RVALID, + M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), + M00_AXI_wready => ps7_0_axi_periph_M00_AXI_WREADY, + M00_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), + M00_AXI_wvalid => ps7_0_axi_periph_M00_AXI_WVALID, + M01_AXI_araddr(31 downto 0) => S_AXIL_1_ARADDR(31 downto 0), + M01_AXI_arready => S_AXIL_1_ARREADY, + M01_AXI_arvalid => S_AXIL_1_ARVALID, + M01_AXI_awaddr(31 downto 0) => S_AXIL_1_AWADDR(31 downto 0), + M01_AXI_awready => S_AXIL_1_AWREADY, + M01_AXI_awvalid => S_AXIL_1_AWVALID, + M01_AXI_bready => S_AXIL_1_BREADY, + M01_AXI_bresp(1 downto 0) => S_AXIL_1_BRESP(1 downto 0), + M01_AXI_bvalid => S_AXIL_1_BVALID, + M01_AXI_rdata(31 downto 0) => S_AXIL_1_RDATA(31 downto 0), + M01_AXI_rready => S_AXIL_1_RREADY, + M01_AXI_rresp(1 downto 0) => S_AXIL_1_RRESP(1 downto 0), + M01_AXI_rvalid => S_AXIL_1_RVALID, + M01_AXI_wdata(31 downto 0) => S_AXIL_1_WDATA(31 downto 0), + M01_AXI_wready => S_AXIL_1_WREADY, + M01_AXI_wstrb(3 downto 0) => S_AXIL_1_WSTRB(3 downto 0), + M01_AXI_wvalid => S_AXIL_1_WVALID, + M02_AXI_araddr(31 downto 0) => S_AXIL1_1_ARADDR(31 downto 0), + M02_AXI_arready => S_AXIL1_1_ARREADY, + M02_AXI_arvalid => S_AXIL1_1_ARVALID, + M02_AXI_awaddr(31 downto 0) => S_AXIL1_1_AWADDR(31 downto 0), + M02_AXI_awready => S_AXIL1_1_AWREADY, + M02_AXI_awvalid => S_AXIL1_1_AWVALID, + M02_AXI_bready => S_AXIL1_1_BREADY, + M02_AXI_bresp(1 downto 0) => S_AXIL1_1_BRESP(1 downto 0), + M02_AXI_bvalid => S_AXIL1_1_BVALID, + M02_AXI_rdata(31 downto 0) => S_AXIL1_1_RDATA(31 downto 0), + M02_AXI_rready => S_AXIL1_1_RREADY, + M02_AXI_rresp(1 downto 0) => S_AXIL1_1_RRESP(1 downto 0), + M02_AXI_rvalid => S_AXIL1_1_RVALID, + M02_AXI_wdata(31 downto 0) => S_AXIL1_1_WDATA(31 downto 0), + M02_AXI_wready => S_AXIL1_1_WREADY, + M02_AXI_wstrb(3 downto 0) => S_AXIL1_1_WSTRB(3 downto 0), + M02_AXI_wvalid => S_AXIL1_1_WVALID, + S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0), + S00_AXI1_araddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0), + S00_AXI1_arburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0), + S00_AXI1_arcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0), + S00_AXI1_arid(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARID(3 downto 0), + S00_AXI1_arlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0), + S00_AXI1_arprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0), + S00_AXI1_arready => zynq_base_hdmi_0_M_AXI_ARREADY, + S00_AXI1_arsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0), + S00_AXI1_arvalid => zynq_base_hdmi_0_M_AXI_ARVALID, + S00_AXI1_awaddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0), + S00_AXI1_awburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0), + S00_AXI1_awcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0), + S00_AXI1_awlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0), + S00_AXI1_awprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0), + S00_AXI1_awready => zynq_base_hdmi_0_M_AXI_AWREADY, + S00_AXI1_awsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0), + S00_AXI1_awvalid => zynq_base_hdmi_0_M_AXI_AWVALID, + S00_AXI1_bready => zynq_base_hdmi_0_M_AXI_BREADY, + S00_AXI1_bresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0), + S00_AXI1_bvalid => zynq_base_hdmi_0_M_AXI_BVALID, + S00_AXI1_rdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0), + S00_AXI1_rid(3 downto 0) => zynq_base_hdmi_0_M_AXI_RID(3 downto 0), + S00_AXI1_rlast => zynq_base_hdmi_0_M_AXI_RLAST, + S00_AXI1_rready => zynq_base_hdmi_0_M_AXI_RREADY, + S00_AXI1_rresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0), + S00_AXI1_rvalid => zynq_base_hdmi_0_M_AXI_RVALID, + S00_AXI1_wdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0), + S00_AXI1_wlast => zynq_base_hdmi_0_M_AXI_WLAST, + S00_AXI1_wready => zynq_base_hdmi_0_M_AXI_WREADY, + S00_AXI1_wstrb(3 downto 0) => zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0), + S00_AXI1_wvalid => zynq_base_hdmi_0_M_AXI_WVALID, + S00_AXI2_araddr(31 downto 0) => VideoSubsystem_M_AXI_ARADDR(31 downto 0), + S00_AXI2_arburst(1 downto 0) => VideoSubsystem_M_AXI_ARBURST(1 downto 0), + S00_AXI2_arcache(3 downto 0) => VideoSubsystem_M_AXI_ARCACHE(3 downto 0), + S00_AXI2_arid(0) => VideoSubsystem_M_AXI_ARID(0), + S00_AXI2_arlen(3 downto 0) => VideoSubsystem_M_AXI_ARLEN(3 downto 0), + S00_AXI2_arprot(2 downto 0) => VideoSubsystem_M_AXI_ARPROT(2 downto 0), + S00_AXI2_arready => VideoSubsystem_M_AXI_ARREADY, + S00_AXI2_arsize(2 downto 0) => VideoSubsystem_M_AXI_ARSIZE(2 downto 0), + S00_AXI2_arvalid => VideoSubsystem_M_AXI_ARVALID, + S00_AXI2_awaddr(31 downto 0) => VideoSubsystem_M_AXI_AWADDR(31 downto 0), + S00_AXI2_awburst(1 downto 0) => VideoSubsystem_M_AXI_AWBURST(1 downto 0), + S00_AXI2_awcache(3 downto 0) => VideoSubsystem_M_AXI_AWCACHE(3 downto 0), + S00_AXI2_awid(0) => VideoSubsystem_M_AXI_AWID(0), + S00_AXI2_awlen(3 downto 0) => VideoSubsystem_M_AXI_AWLEN(3 downto 0), + S00_AXI2_awprot(2 downto 0) => VideoSubsystem_M_AXI_AWPROT(2 downto 0), + S00_AXI2_awready => VideoSubsystem_M_AXI_AWREADY, + S00_AXI2_awsize(2 downto 0) => VideoSubsystem_M_AXI_AWSIZE(2 downto 0), + S00_AXI2_awvalid => VideoSubsystem_M_AXI_AWVALID, + S00_AXI2_bid(0) => VideoSubsystem_M_AXI_BID(0), + S00_AXI2_bready => VideoSubsystem_M_AXI_BREADY, + S00_AXI2_bresp(1 downto 0) => VideoSubsystem_M_AXI_BRESP(1 downto 0), + S00_AXI2_bvalid => VideoSubsystem_M_AXI_BVALID, + S00_AXI2_rdata(31 downto 0) => VideoSubsystem_M_AXI_RDATA(31 downto 0), + S00_AXI2_rid(0) => VideoSubsystem_M_AXI_RID(0), + S00_AXI2_rlast => VideoSubsystem_M_AXI_RLAST, + S00_AXI2_rready => VideoSubsystem_M_AXI_RREADY, + S00_AXI2_rresp(1 downto 0) => VideoSubsystem_M_AXI_RRESP(1 downto 0), + S00_AXI2_rvalid => VideoSubsystem_M_AXI_RVALID, + S00_AXI2_wdata(31 downto 0) => VideoSubsystem_M_AXI_WDATA(31 downto 0), + S00_AXI2_wlast => VideoSubsystem_M_AXI_WLAST, + S00_AXI2_wready => VideoSubsystem_M_AXI_WREADY, + S00_AXI2_wstrb(3 downto 0) => VideoSubsystem_M_AXI_WSTRB(3 downto 0), + S00_AXI2_wvalid => VideoSubsystem_M_AXI_WVALID, + S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), + S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), + S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), + S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), + S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), + S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), + S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), + S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), + S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY, + S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), + S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID, + S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), + S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), + S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), + S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), + S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), + S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), + S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), + S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), + S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY, + S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), + S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID, + S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), + S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY, + S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), + S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID, + S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), + S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), + S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST, + S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY, + S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), + S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID, + S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), + S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), + S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST, + S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY, + S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), + S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID + ); +PS: entity work.PS_imp_Z714CR + port map ( + DDR_addr(14 downto 0) => DDR_addr(14 downto 0), + DDR_ba(2 downto 0) => DDR_ba(2 downto 0), + DDR_cas_n => DDR_cas_n, + DDR_ck_n => DDR_ck_n, + DDR_ck_p => DDR_ck_p, + DDR_cke => DDR_cke, + DDR_cs_n => DDR_cs_n, + DDR_dm(3 downto 0) => DDR_dm(3 downto 0), + DDR_dq(31 downto 0) => DDR_dq(31 downto 0), + DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), + DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), + DDR_odt => DDR_odt, + DDR_ras_n => DDR_ras_n, + DDR_reset_n => DDR_reset_n, + DDR_we_n => DDR_we_n, + FCLK_CLK0 => processing_system7_0_FCLK_CLK0, + FCLK_CLK3 => processing_system7_0_FCLK_CLK3, + FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, + FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), + FIXED_IO_ps_clk => FIXED_IO_ps_clk, + FIXED_IO_ps_porb => FIXED_IO_ps_porb, + FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, + In0(0) => zynq_base_hdmi_0_VIDEO_INTERRUPT, + In1 => VideoSubsystem_VS2MM_INTERRUPT, + M_AXI_GP0_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), + M_AXI_GP0_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), + M_AXI_GP0_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), + M_AXI_GP0_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), + M_AXI_GP0_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), + M_AXI_GP0_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), + M_AXI_GP0_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), + M_AXI_GP0_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), + M_AXI_GP0_arready => processing_system7_0_M_AXI_GP0_ARREADY, + M_AXI_GP0_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), + M_AXI_GP0_arvalid => processing_system7_0_M_AXI_GP0_ARVALID, + M_AXI_GP0_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), + M_AXI_GP0_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), + M_AXI_GP0_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), + M_AXI_GP0_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), + M_AXI_GP0_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), + M_AXI_GP0_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), + M_AXI_GP0_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), + M_AXI_GP0_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), + M_AXI_GP0_awready => processing_system7_0_M_AXI_GP0_AWREADY, + M_AXI_GP0_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), + M_AXI_GP0_awvalid => processing_system7_0_M_AXI_GP0_AWVALID, + M_AXI_GP0_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), + M_AXI_GP0_bready => processing_system7_0_M_AXI_GP0_BREADY, + M_AXI_GP0_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), + M_AXI_GP0_bvalid => processing_system7_0_M_AXI_GP0_BVALID, + M_AXI_GP0_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), + M_AXI_GP0_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), + M_AXI_GP0_rlast => processing_system7_0_M_AXI_GP0_RLAST, + M_AXI_GP0_rready => processing_system7_0_M_AXI_GP0_RREADY, + M_AXI_GP0_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), + M_AXI_GP0_rvalid => processing_system7_0_M_AXI_GP0_RVALID, + M_AXI_GP0_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), + M_AXI_GP0_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), + M_AXI_GP0_wlast => processing_system7_0_M_AXI_GP0_WLAST, + M_AXI_GP0_wready => processing_system7_0_M_AXI_GP0_WREADY, + M_AXI_GP0_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), + M_AXI_GP0_wvalid => processing_system7_0_M_AXI_GP0_WVALID, + S_AXI_ACP_araddr(31 downto 0) => AXI_Intercon_M00_AXI2_ARADDR(31 downto 0), + S_AXI_ACP_arburst(1 downto 0) => AXI_Intercon_M00_AXI2_ARBURST(1 downto 0), + S_AXI_ACP_arcache(3 downto 0) => AXI_Intercon_M00_AXI2_ARCACHE(3 downto 0), + S_AXI_ACP_arlen(3 downto 0) => AXI_Intercon_M00_AXI2_ARLEN(3 downto 0), + S_AXI_ACP_arlock(1 downto 0) => AXI_Intercon_M00_AXI2_ARLOCK(1 downto 0), + S_AXI_ACP_arprot(2 downto 0) => AXI_Intercon_M00_AXI2_ARPROT(2 downto 0), + S_AXI_ACP_arqos(3 downto 0) => AXI_Intercon_M00_AXI2_ARQOS(3 downto 0), + S_AXI_ACP_arready => AXI_Intercon_M00_AXI2_ARREADY, + S_AXI_ACP_arsize(2 downto 0) => AXI_Intercon_M00_AXI2_ARSIZE(2 downto 0), + S_AXI_ACP_arvalid => AXI_Intercon_M00_AXI2_ARVALID, + S_AXI_ACP_awaddr(31 downto 0) => AXI_Intercon_M00_AXI2_AWADDR(31 downto 0), + S_AXI_ACP_awburst(1 downto 0) => AXI_Intercon_M00_AXI2_AWBURST(1 downto 0), + S_AXI_ACP_awcache(3 downto 0) => AXI_Intercon_M00_AXI2_AWCACHE(3 downto 0), + S_AXI_ACP_awlen(3 downto 0) => AXI_Intercon_M00_AXI2_AWLEN(3 downto 0), + S_AXI_ACP_awlock(1 downto 0) => AXI_Intercon_M00_AXI2_AWLOCK(1 downto 0), + S_AXI_ACP_awprot(2 downto 0) => AXI_Intercon_M00_AXI2_AWPROT(2 downto 0), + S_AXI_ACP_awqos(3 downto 0) => AXI_Intercon_M00_AXI2_AWQOS(3 downto 0), + S_AXI_ACP_awready => AXI_Intercon_M00_AXI2_AWREADY, + S_AXI_ACP_awsize(2 downto 0) => AXI_Intercon_M00_AXI2_AWSIZE(2 downto 0), + S_AXI_ACP_awvalid => AXI_Intercon_M00_AXI2_AWVALID, + S_AXI_ACP_bready => AXI_Intercon_M00_AXI2_BREADY, + S_AXI_ACP_bresp(1 downto 0) => AXI_Intercon_M00_AXI2_BRESP(1 downto 0), + S_AXI_ACP_bvalid => AXI_Intercon_M00_AXI2_BVALID, + S_AXI_ACP_rdata(63 downto 0) => AXI_Intercon_M00_AXI2_RDATA(63 downto 0), + S_AXI_ACP_rlast => AXI_Intercon_M00_AXI2_RLAST, + S_AXI_ACP_rready => AXI_Intercon_M00_AXI2_RREADY, + S_AXI_ACP_rresp(1 downto 0) => AXI_Intercon_M00_AXI2_RRESP(1 downto 0), + S_AXI_ACP_rvalid => AXI_Intercon_M00_AXI2_RVALID, + S_AXI_ACP_wdata(63 downto 0) => AXI_Intercon_M00_AXI2_WDATA(63 downto 0), + S_AXI_ACP_wlast => AXI_Intercon_M00_AXI2_WLAST, + S_AXI_ACP_wready => AXI_Intercon_M00_AXI2_WREADY, + S_AXI_ACP_wstrb(7 downto 0) => AXI_Intercon_M00_AXI2_WSTRB(7 downto 0), + S_AXI_ACP_wvalid => AXI_Intercon_M00_AXI2_WVALID, + S_AXI_HP0_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), + S_AXI_HP0_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), + S_AXI_HP0_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), + S_AXI_HP0_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), + S_AXI_HP0_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), + S_AXI_HP0_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), + S_AXI_HP0_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), + S_AXI_HP0_arready => axi_mem_intercon_M00_AXI_ARREADY, + S_AXI_HP0_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), + S_AXI_HP0_arvalid => axi_mem_intercon_M00_AXI_ARVALID, + S_AXI_HP0_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), + S_AXI_HP0_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), + S_AXI_HP0_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), + S_AXI_HP0_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), + S_AXI_HP0_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), + S_AXI_HP0_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), + S_AXI_HP0_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), + S_AXI_HP0_awready => axi_mem_intercon_M00_AXI_AWREADY, + S_AXI_HP0_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), + S_AXI_HP0_awvalid => axi_mem_intercon_M00_AXI_AWVALID, + S_AXI_HP0_bready => axi_mem_intercon_M00_AXI_BREADY, + S_AXI_HP0_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), + S_AXI_HP0_bvalid => axi_mem_intercon_M00_AXI_BVALID, + S_AXI_HP0_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), + S_AXI_HP0_rlast => axi_mem_intercon_M00_AXI_RLAST, + S_AXI_HP0_rready => axi_mem_intercon_M00_AXI_RREADY, + S_AXI_HP0_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), + S_AXI_HP0_rvalid => axi_mem_intercon_M00_AXI_RVALID, + S_AXI_HP0_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), + S_AXI_HP0_wlast => axi_mem_intercon_M00_AXI_WLAST, + S_AXI_HP0_wready => axi_mem_intercon_M00_AXI_WREADY, + S_AXI_HP0_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), + S_AXI_HP0_wvalid => axi_mem_intercon_M00_AXI_WVALID, + peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0) + ); +VideoSubsystem: entity work.VideoSubsystem_imp_RHI5N8 + port map ( + ACLK => processing_system7_0_FCLK_CLK0, + ARESETN => rst_ps7_0_100M_peripheral_aresetn(0), + M_AXI_araddr(31 downto 0) => VideoSubsystem_M_AXI_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => VideoSubsystem_M_AXI_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => VideoSubsystem_M_AXI_ARCACHE(3 downto 0), + M_AXI_arid(0) => VideoSubsystem_M_AXI_ARID(0), + M_AXI_arlen(3 downto 0) => VideoSubsystem_M_AXI_ARLEN(3 downto 0), + M_AXI_arprot(2 downto 0) => VideoSubsystem_M_AXI_ARPROT(2 downto 0), + M_AXI_arready => VideoSubsystem_M_AXI_ARREADY, + M_AXI_arsize(2 downto 0) => VideoSubsystem_M_AXI_ARSIZE(2 downto 0), + M_AXI_arvalid => VideoSubsystem_M_AXI_ARVALID, + M_AXI_awaddr(31 downto 0) => VideoSubsystem_M_AXI_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => VideoSubsystem_M_AXI_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => VideoSubsystem_M_AXI_AWCACHE(3 downto 0), + M_AXI_awid(0) => VideoSubsystem_M_AXI_AWID(0), + M_AXI_awlen(3 downto 0) => VideoSubsystem_M_AXI_AWLEN(3 downto 0), + M_AXI_awprot(2 downto 0) => VideoSubsystem_M_AXI_AWPROT(2 downto 0), + M_AXI_awready => VideoSubsystem_M_AXI_AWREADY, + M_AXI_awsize(2 downto 0) => VideoSubsystem_M_AXI_AWSIZE(2 downto 0), + M_AXI_awvalid => VideoSubsystem_M_AXI_AWVALID, + M_AXI_bid(0) => VideoSubsystem_M_AXI_BID(0), + M_AXI_bready => VideoSubsystem_M_AXI_BREADY, + M_AXI_bresp(1 downto 0) => VideoSubsystem_M_AXI_BRESP(1 downto 0), + M_AXI_bvalid => VideoSubsystem_M_AXI_BVALID, + M_AXI_rdata(31 downto 0) => VideoSubsystem_M_AXI_RDATA(31 downto 0), + M_AXI_rid(0) => VideoSubsystem_M_AXI_RID(0), + M_AXI_rlast => VideoSubsystem_M_AXI_RLAST, + M_AXI_rready => VideoSubsystem_M_AXI_RREADY, + M_AXI_rresp(1 downto 0) => VideoSubsystem_M_AXI_RRESP(1 downto 0), + M_AXI_rvalid => VideoSubsystem_M_AXI_RVALID, + M_AXI_wdata(31 downto 0) => VideoSubsystem_M_AXI_WDATA(31 downto 0), + M_AXI_wlast => VideoSubsystem_M_AXI_WLAST, + M_AXI_wready => VideoSubsystem_M_AXI_WREADY, + M_AXI_wstrb(3 downto 0) => VideoSubsystem_M_AXI_WSTRB(3 downto 0), + M_AXI_wvalid => VideoSubsystem_M_AXI_WVALID, + S_AXIL1_araddr(31 downto 0) => S_AXIL1_1_ARADDR(31 downto 0), + S_AXIL1_arready => S_AXIL1_1_ARREADY, + S_AXIL1_arvalid => S_AXIL1_1_ARVALID, + S_AXIL1_awaddr(31 downto 0) => S_AXIL1_1_AWADDR(31 downto 0), + S_AXIL1_awready => S_AXIL1_1_AWREADY, + S_AXIL1_awvalid => S_AXIL1_1_AWVALID, + S_AXIL1_bready => S_AXIL1_1_BREADY, + S_AXIL1_bresp(1 downto 0) => S_AXIL1_1_BRESP(1 downto 0), + S_AXIL1_bvalid => S_AXIL1_1_BVALID, + S_AXIL1_rdata(31 downto 0) => S_AXIL1_1_RDATA(31 downto 0), + S_AXIL1_rready => S_AXIL1_1_RREADY, + S_AXIL1_rresp(1 downto 0) => S_AXIL1_1_RRESP(1 downto 0), + S_AXIL1_rvalid => S_AXIL1_1_RVALID, + S_AXIL1_wdata(31 downto 0) => S_AXIL1_1_WDATA(31 downto 0), + S_AXIL1_wready => S_AXIL1_1_WREADY, + S_AXIL1_wstrb(3 downto 0) => S_AXIL1_1_WSTRB(3 downto 0), + S_AXIL1_wvalid => S_AXIL1_1_WVALID, + S_AXIL_araddr(31 downto 0) => S_AXIL_1_ARADDR(31 downto 0), + S_AXIL_arready => S_AXIL_1_ARREADY, + S_AXIL_arvalid => S_AXIL_1_ARVALID, + S_AXIL_awaddr(31 downto 0) => S_AXIL_1_AWADDR(31 downto 0), + S_AXIL_awready => S_AXIL_1_AWREADY, + S_AXIL_awvalid => S_AXIL_1_AWVALID, + S_AXIL_bready => S_AXIL_1_BREADY, + S_AXIL_bresp(1 downto 0) => S_AXIL_1_BRESP(1 downto 0), + S_AXIL_bvalid => S_AXIL_1_BVALID, + S_AXIL_rdata(31 downto 0) => S_AXIL_1_RDATA(31 downto 0), + S_AXIL_rready => S_AXIL_1_RREADY, + S_AXIL_rresp(1 downto 0) => S_AXIL_1_RRESP(1 downto 0), + S_AXIL_rvalid => S_AXIL_1_RVALID, + S_AXIL_wdata(31 downto 0) => S_AXIL_1_WDATA(31 downto 0), + S_AXIL_wready => S_AXIL_1_WREADY, + S_AXIL_wstrb(3 downto 0) => S_AXIL_1_WSTRB(3 downto 0), + S_AXIL_wvalid => S_AXIL_1_WVALID, + VS2MM_INTERRUPT => VideoSubsystem_VS2MM_INTERRUPT + ); +ZYNQ_BASE: entity work.ZYNQ_BASE_imp_1TRJPP2 + port map ( + BUTTON_0(3 downto 0) => BUTTON_0_1(3 downto 0), + HDMI_CLK_N_0 => zynq_base_hdmi_0_HDMI_CLK_N, + HDMI_CLK_P_0 => zynq_base_hdmi_0_HDMI_CLK_P, + HDMI_DATA_N_0(2 downto 0) => zynq_base_hdmi_0_HDMI_DATA_N(2 downto 0), + HDMI_DATA_P_0(2 downto 0) => zynq_base_hdmi_0_HDMI_DATA_P(2 downto 0), + LED_0(3 downto 0) => zynq_base_hdmi_0_LED(3 downto 0), + M_AXI_ACLK => processing_system7_0_FCLK_CLK0, + M_AXI_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0), + M_AXI_araddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARCACHE(3 downto 0), + M_AXI_arid(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARID(3 downto 0), + M_AXI_arlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_ARLEN(3 downto 0), + M_AXI_arprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARPROT(2 downto 0), + M_AXI_arready => zynq_base_hdmi_0_M_AXI_ARREADY, + M_AXI_arsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_ARSIZE(2 downto 0), + M_AXI_arvalid => zynq_base_hdmi_0_M_AXI_ARVALID, + M_AXI_awaddr(31 downto 0) => zynq_base_hdmi_0_M_AXI_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => zynq_base_hdmi_0_M_AXI_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWCACHE(3 downto 0), + M_AXI_awlen(3 downto 0) => zynq_base_hdmi_0_M_AXI_AWLEN(3 downto 0), + M_AXI_awprot(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWPROT(2 downto 0), + M_AXI_awready => zynq_base_hdmi_0_M_AXI_AWREADY, + M_AXI_awsize(2 downto 0) => zynq_base_hdmi_0_M_AXI_AWSIZE(2 downto 0), + M_AXI_awvalid => zynq_base_hdmi_0_M_AXI_AWVALID, + M_AXI_bready => zynq_base_hdmi_0_M_AXI_BREADY, + M_AXI_bresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_BRESP(1 downto 0), + M_AXI_bvalid => zynq_base_hdmi_0_M_AXI_BVALID, + M_AXI_rdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_RDATA(31 downto 0), + M_AXI_rid(3 downto 0) => zynq_base_hdmi_0_M_AXI_RID(3 downto 0), + M_AXI_rlast => zynq_base_hdmi_0_M_AXI_RLAST, + M_AXI_rready => zynq_base_hdmi_0_M_AXI_RREADY, + M_AXI_rresp(1 downto 0) => zynq_base_hdmi_0_M_AXI_RRESP(1 downto 0), + M_AXI_rvalid => zynq_base_hdmi_0_M_AXI_RVALID, + M_AXI_wdata(31 downto 0) => zynq_base_hdmi_0_M_AXI_WDATA(31 downto 0), + M_AXI_wlast => zynq_base_hdmi_0_M_AXI_WLAST, + M_AXI_wready => zynq_base_hdmi_0_M_AXI_WREADY, + M_AXI_wstrb(3 downto 0) => zynq_base_hdmi_0_M_AXI_WSTRB(3 downto 0), + M_AXI_wvalid => zynq_base_hdmi_0_M_AXI_WVALID, + RGB_LED_0(5 downto 0) => zynq_base_hdmi_0_RGB_LED(5 downto 0), + SWITCH_0(3 downto 0) => SWITCH_0_1(3 downto 0), + S_AXIL_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0), + S_AXIL_arready => ps7_0_axi_periph_M00_AXI_ARREADY, + S_AXIL_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID, + S_AXIL_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0), + S_AXIL_awready => ps7_0_axi_periph_M00_AXI_AWREADY, + S_AXIL_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID, + S_AXIL_bready => ps7_0_axi_periph_M00_AXI_BREADY, + S_AXIL_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), + S_AXIL_bvalid => ps7_0_axi_periph_M00_AXI_BVALID, + S_AXIL_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), + S_AXIL_rready => ps7_0_axi_periph_M00_AXI_RREADY, + S_AXIL_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), + S_AXIL_rvalid => ps7_0_axi_periph_M00_AXI_RVALID, + S_AXIL_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), + S_AXIL_wready => ps7_0_axi_periph_M00_AXI_WREADY, + S_AXIL_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), + S_AXIL_wvalid => ps7_0_axi_periph_M00_AXI_WVALID, + VIDEO_CLK => processing_system7_0_FCLK_CLK3, + VIDEO_INTERRUPT => zynq_base_hdmi_0_VIDEO_INTERRUPT + ); +end STRUCTURE; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml index 10455a9..96bdd4f 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml @@ -321,7 +321,7 @@ viewChecksum - 59fe4094 + 9bd3ce3c @@ -334,7 +334,7 @@ viewChecksum - 59fe4094 + 9bd3ce3c @@ -861,7 +861,7 @@ IPI 1 - 2024-12-10T17:13:02Z + 2024-12-10T17:19:39Z 2023.1 diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd index d6b499d..4e86c41 100644 --- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd @@ -7,8 +7,7 @@ "name": "design_1", "rev_ctrl_bd_flag": "RevCtrlBdOff", "synth_flow_mode": "Hierarchical", - "tool_version": "2023.1", - "validated": "true" + "tool_version": "2023.1" }, "design_tree": { "axis_downsizer_0": "", diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd index 7dea4df..880613b 100644 --- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd @@ -3544,6 +3544,16 @@ "address_spaces": { "M_AXI": { "segments": { + "SEG_axi_2d_mmvs_0_reg0": { + "address_block": "/axi_2d_mmvs_0/S_AXIL/reg0", + "offset": "0x44A00000", + "range": "64K" + }, + "SEG_axis_video_filter_0_reg0": { + "address_block": "/axis_video_filter_0/S_AXIL/reg0", + "offset": "0x40000000", + "range": "32K" + }, "SEG_processing_system7_0_HP0_DDR_LOWOCM": { "address_block": "/PS/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", "offset": "0x00000000", @@ -3552,6 +3562,34 @@ } } } + }, + "/axi_2d_mmvs_0": { + "address_spaces": { + "M_AXI": { + "segments": { + "SEG_processing_system7_0_ACP_DDR_LOWOCM": { + "address_block": "/PS/processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM", + "offset": "0x00000000", + "range": "1G" + }, + "SEG_processing_system7_0_ACP_IOP": { + "address_block": "/PS/processing_system7_0/S_AXI_ACP/ACP_IOP", + "offset": "0xE0000000", + "range": "4M" + }, + "SEG_processing_system7_0_ACP_M_AXI_GP0": { + "address_block": "/PS/processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0", + "offset": "0x40000000", + "range": "1G" + }, + "SEG_processing_system7_0_ACP_QSPI_LINEAR": { + "address_block": "/PS/processing_system7_0/S_AXI_ACP/ACP_QSPI_LINEAR", + "offset": "0xFC000000", + "range": "16M" + } + } + } + } } } } diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xci index b1eb993..47bc439 100644 --- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xci +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xci @@ -479,7 +479,7 @@ "PCW_ENET_RESET_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PCW_ENET_RESET_SELECT": [ { "value": "Share reset pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PCW_ENET0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "PCW_ENET0_RESET_IO": [ { "value": "", "resolve_type": "user", "usage": "all" } ], "PCW_ENET1_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PCW_ENET1_ENET1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_I2C0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "PCW_I2C0_RESET_IO": [ { "value": "", "resolve_type": "user", "usage": "all" } ], "PCW_I2C1_PERIPHERAL_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PCW_I2C1_I2C1_IO": [ { "value": "MIO 12 .. 13", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PCW_I2C1_GRP_INT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], @@ -1461,7 +1461,7 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "master", "parameters": { - "FREQ_HZ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "FREQ_HZ": [ { "value": "1e+08", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_2_processing_system7_0_0_FCLK_CLK0", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], @@ -1479,7 +1479,7 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "master", "parameters": { - "FREQ_HZ": [ { "value": "125000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "FREQ_HZ": [ { "value": "1.25e+08", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_2_processing_system7_0_0_FCLK_CLK1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], @@ -1497,7 +1497,7 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "master", "parameters": { - "FREQ_HZ": [ { "value": "200000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "FREQ_HZ": [ { "value": "2e+08", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_2_processing_system7_0_0_FCLK_CLK2", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], @@ -1515,7 +1515,7 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "master", "parameters": { - "FREQ_HZ": [ { "value": "66666672", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "FREQ_HZ": [ { "value": "6.66667e+07", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_2_processing_system7_0_0_FCLK_CLK3", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui index 75894d6..933abd5 100644 --- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui @@ -1,59 +1,59 @@ { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"1.22367", - "Default View_TopLeft":"16,-7", + "Default View_ScaleFactor":"1.1577", + "Default View_TopLeft":"-119,-76", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD -preplace port DDR -pg 1 -lvl 5 -x 1260 -y 110 -defaultsOSRD -preplace port FIXED_IO -pg 1 -lvl 5 -x 1260 -y 140 -defaultsOSRD -preplace port port-id_HDMI_CLK_N -pg 1 -lvl 5 -x 1260 -y 300 -defaultsOSRD -preplace port port-id_HDMI_CLK_P -pg 1 -lvl 5 -x 1260 -y 330 -defaultsOSRD +preplace port DDR -pg 1 -lvl 5 -x 1410 -y 110 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 5 -x 1410 -y 140 -defaultsOSRD +preplace port port-id_HDMI_CLK_N -pg 1 -lvl 5 -x 1410 -y 300 -defaultsOSRD +preplace port port-id_HDMI_CLK_P -pg 1 -lvl 5 -x 1410 -y 330 -defaultsOSRD preplace portBus BUTTON -pg 1 -lvl 0 -x 0 -y 350 -defaultsOSRD -preplace portBus HDMI_DATA_N -pg 1 -lvl 5 -x 1260 -y 360 -defaultsOSRD -preplace portBus HDMI_DATA_P -pg 1 -lvl 5 -x 1260 -y 390 -defaultsOSRD -preplace portBus LED -pg 1 -lvl 5 -x 1260 -y 420 -defaultsOSRD -preplace portBus RGB_LED -pg 1 -lvl 5 -x 1260 -y 450 -defaultsOSRD +preplace portBus HDMI_DATA_N -pg 1 -lvl 5 -x 1410 -y 360 -defaultsOSRD +preplace portBus HDMI_DATA_P -pg 1 -lvl 5 -x 1410 -y 390 -defaultsOSRD +preplace portBus LED -pg 1 -lvl 5 -x 1410 -y 420 -defaultsOSRD +preplace portBus RGB_LED -pg 1 -lvl 5 -x 1410 -y 450 -defaultsOSRD preplace portBus SWITCH -pg 1 -lvl 0 -x 0 -y 410 -defaultsOSRD -preplace inst AXI_Intercon -pg 1 -lvl 2 -x 470 -y 150 -defaultsOSRD -preplace inst PS -pg 1 -lvl 3 -x 830 -y 170 -defaultsOSRD -preplace inst ZYNQ_BASE -pg 1 -lvl 3 -x 830 -y 380 -defaultsOSRD +preplace inst AXI_Intercon -pg 1 -lvl 2 -x 570 -y 150 -defaultsOSRD +preplace inst PS -pg 1 -lvl 3 -x 979 -y 170 -defaultsOSRD +preplace inst ZYNQ_BASE -pg 1 -lvl 3 -x 979 -y 380 -defaultsOSRD preplace inst axis_downsizer_0 -pg 1 -lvl 1 -x 150 -y 730 -defaultsOSRD -preplace inst axi_2d_mmvs_0 -pg 1 -lvl 2 -x 470 -y 1010 -defaultsOSRD -preplace inst axis_upsizer_0 -pg 1 -lvl 3 -x 830 -y 740 -defaultsOSRD -preplace inst axis_linemem_single_0 -pg 1 -lvl 4 -x 1130 -y 810 -defaultsOSRD -preplace inst axis_video_filter_0 -pg 1 -lvl 2 -x 470 -y 740 -defaultsOSRD +preplace inst axi_2d_mmvs_0 -pg 1 -lvl 2 -x 570 -y 1010 -defaultsOSRD +preplace inst axis_upsizer_0 -pg 1 -lvl 3 -x 979 -y 740 -defaultsOSRD +preplace inst axis_linemem_single_0 -pg 1 -lvl 4 -x 1280 -y 810 -defaultsOSRD +preplace inst axis_video_filter_0 -pg 1 -lvl 2 -x 570 -y 740 -defaultsOSRD preplace netloc BUTTON_0_1 1 0 3 NJ 350 N 350 NJ -preplace netloc Net 1 0 4 30 810 290J 630 660 660 1000 -preplace netloc Net1 1 0 4 20 650 270J 610 680 610 1020 +preplace netloc Net 1 0 4 30 810 390J 630 809 660 1150 +preplace netloc Net1 1 0 4 20 650 370J 610 829 610 1170 preplace netloc SWITCH_0_1 1 0 3 NJ 410 N 410 NJ -preplace netloc processing_system7_0_FCLK_CLK0 1 1 3 310 40 650 40 1020 -preplace netloc processing_system7_0_FCLK_CLK3 1 2 2 670 10 1030 -preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 3 340 240 660 60 980 -preplace netloc zynq_base_hdmi_0_HDMI_CLK_N 1 3 2 NJ 330 1230 -preplace netloc zynq_base_hdmi_0_HDMI_CLK_P 1 3 2 NJ 350 1240 -preplace netloc zynq_base_hdmi_0_HDMI_DATA_N 1 3 2 NJ 370 1230 +preplace netloc processing_system7_0_FCLK_CLK0 1 1 3 410 40 799 40 1170 +preplace netloc processing_system7_0_FCLK_CLK3 1 2 2 819 10 1180 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 3 440 240 809 60 1130 +preplace netloc zynq_base_hdmi_0_HDMI_CLK_N 1 3 2 NJ 330 1380 +preplace netloc zynq_base_hdmi_0_HDMI_CLK_P 1 3 2 NJ 350 1390 +preplace netloc zynq_base_hdmi_0_HDMI_DATA_N 1 3 2 NJ 370 1380 preplace netloc zynq_base_hdmi_0_HDMI_DATA_P 1 3 2 NJ 390 N -preplace netloc zynq_base_hdmi_0_LED 1 3 2 NJ 410 1240 -preplace netloc zynq_base_hdmi_0_RGB_LED 1 3 2 NJ 430 1230 -preplace netloc zynq_base_hdmi_0_VIDEO_INTERRUPT 1 2 2 680 30 1010 -preplace netloc AXI_Intercon_M00_AXI2 1 1 2 310 260 620 -preplace netloc AXI_Intercon_M00_AXI3 1 1 2 300 250 610 -preplace netloc AXI_Intercon_M00_AXI_4 1 2 1 630 170n -preplace netloc S00_AXI_2_1 1 1 2 270 270 610 -preplace netloc axi_2d_mmvs_0_M_AXIS 1 0 3 30 600 NJ 600 600 -preplace netloc axi_mem_intercon_M00_AXI 1 2 1 630 130n -preplace netloc axis_downsizer_0_M_AXIS 1 1 3 280J 620 NJ 620 1030 -preplace netloc axis_linemem_single_0_m_axis 1 1 4 330 640 NJ 640 NJ 640 1230 -preplace netloc axis_upsizer_0_M_AXIS 1 1 3 340 650 NJ 650 990 -preplace netloc axis_video_filter_0_M_AXIS 1 2 1 630 720n -preplace netloc processing_system7_0_DDR 1 3 2 NJ 120 1230 +preplace netloc zynq_base_hdmi_0_LED 1 3 2 NJ 410 1390 +preplace netloc zynq_base_hdmi_0_RGB_LED 1 3 2 NJ 430 1380 +preplace netloc zynq_base_hdmi_0_VIDEO_INTERRUPT 1 2 2 829 30 1160 +preplace netloc AXI_Intercon_M00_AXI2 1 1 2 410 260 720 +preplace netloc AXI_Intercon_M00_AXI3 1 1 2 400 250 710 +preplace netloc AXI_Intercon_M00_AXI_4 1 2 1 730 170n +preplace netloc S00_AXI_2_1 1 1 2 370 270 710 +preplace netloc axi_2d_mmvs_0_M_AXIS 1 0 3 30 600 NJ 600 700 +preplace netloc axi_mem_intercon_M00_AXI 1 2 1 730 130n +preplace netloc axis_downsizer_0_M_AXIS 1 1 3 380J 620 NJ 620 1180 +preplace netloc axis_linemem_single_0_m_axis 1 1 4 430 640 NJ 640 NJ 640 1380 +preplace netloc axis_upsizer_0_M_AXIS 1 1 3 440 650 NJ 650 1140 +preplace netloc axis_video_filter_0_M_AXIS 1 2 1 730 720n +preplace netloc processing_system7_0_DDR 1 3 2 NJ 120 1380 preplace netloc processing_system7_0_FIXED_IO 1 3 2 NJ 140 N -preplace netloc processing_system7_0_M_AXI_GP0 1 1 3 340 20 NJ 20 990 -preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 640 110n -preplace netloc zynq_base_hdmi_0_M_AXI 1 1 3 320 50 NJ 50 1000 -levelinfo -pg 1 0 150 470 830 1130 1260 -pagesize -pg 1 -db -bbox -sgen -140 0 1440 1100 +preplace netloc processing_system7_0_M_AXI_GP0 1 1 3 440 20 NJ 20 1140 +preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 740 110n +preplace netloc zynq_base_hdmi_0_M_AXI 1 1 3 420 50 NJ 50 1150 +levelinfo -pg 1 0 150 570 979 1280 1410 +pagesize -pg 1 -db -bbox -sgen -140 0 1820 1730 " } 0 diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_3b5c004.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_3b5c004.ui index d280402..a09854f 100644 --- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_3b5c004.ui +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_3b5c004.ui @@ -1,7 +1,7 @@ { "ActiveEmotionalView":"Default View", "Default View_ScaleFactor":"1.61965", - "Default View_TopLeft":"-379,-7", + "Default View_TopLeft":"-244,219", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD @@ -20,16 +20,16 @@ preplace inst ps7_0_axi_periph -pg 1 -lvl 1 -x 450 -y 110 -defaultsOSRD preplace inst axi_interconnect_0 -pg 1 -lvl 1 -x 450 -y 670 -defaultsOSRD preplace netloc processing_system7_0_FCLK_CLK0 1 0 1 300 70n preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 1 310 90n +preplace netloc S00_AXI_1_1 1 0 1 N 610 +preplace netloc axi_interconnect_0_M00_AXI 1 1 1 N 670 preplace netloc axi_mem_intercon_M00_AXI 1 1 1 590J 330n +preplace netloc axi_mem_intercon_M01_AXI 1 1 1 590 360n +preplace netloc axi_mem_intercon_M02_AXI 1 1 1 N 390 preplace netloc processing_system7_0_M_AXI_GP0 1 0 1 NJ 50 preplace netloc ps7_0_axi_periph_M00_AXI 1 1 1 NJ 110 preplace netloc zynq_base_hdmi_0_M_AXI 1 0 1 10J 250n -preplace netloc axi_mem_intercon_M01_AXI 1 1 1 590 360n -preplace netloc axi_mem_intercon_M02_AXI 1 1 1 N 390 -preplace netloc S00_AXI_1_1 1 0 1 N 610 -preplace netloc axi_interconnect_0_M00_AXI 1 1 1 N 670 levelinfo -pg 1 -10 450 630 pagesize -pg 1 -db -bbox -sgen -150 -120 750 810 " } - +0 diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_9bff7ad4.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_9bff7ad4.ui index 4b36669..0c2f6ed 100644 --- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_9bff7ad4.ui +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_9bff7ad4.ui @@ -1,7 +1,7 @@ { "ActiveEmotionalView":"Default View", "Default View_ScaleFactor":"1.6443", - "Default View_TopLeft":"-117,-120", + "Default View_TopLeft":"-192,-38", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD @@ -26,12 +26,12 @@ preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 3 1 NJ 470 preplace netloc xlconcat_0_dout 1 1 1 210J 320n preplace netloc xlconstant_0_dout 1 2 1 660 50n preplace netloc S_AXI_ACP_1 1 0 2 NJ 260 NJ +preplace netloc S_AXI_ACP_2 1 0 2 NJ 230 220 preplace netloc processing_system7_0_DDR 1 2 2 670J 140 NJ preplace netloc processing_system7_0_FIXED_IO 1 2 2 NJ 170 NJ preplace netloc processing_system7_0_M_AXI_GP0 1 2 2 NJ 250 NJ -preplace netloc S_AXI_ACP_2 1 0 2 NJ 230 220 levelinfo -pg 1 0 120 440 840 1040 pagesize -pg 1 -db -bbox -sgen -120 -20 1260 550 " } - +0 diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/design_3.bd b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/design_3.bd new file mode 100644 index 0000000..7a2e6de --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/design_3.bd @@ -0,0 +1,3780 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x3A6704D3ADB2B84D", + "device": "xc7z020clg400-1", + "gen_directory": "../../../../milestone6.gen/sources_1/bd/design_3", + "name": "design_3", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2023.1", + "validated": "true" + }, + "design_tree": { + "AXI_Intercon": { + "axi_mem_intercon": { + "s00_couplers": { + "auto_us": "" + } + }, + "ps7_0_axi_periph": { + "xbar": "", + "s00_couplers": { + "auto_pc": "" + }, + "m00_couplers": {}, + "m01_couplers": {}, + "m02_couplers": {} + }, + "axi_interconnect_0": { + "s00_couplers": { + "auto_us": "" + } + } + }, + "PS": { + "processing_system7_0": "", + "rst_ps7_0_100M": "", + "xlconcat_0": "", + "xlconstant_0": "" + }, + "ZYNQ_BASE": { + "zynq_base_hdmi_0": "" + }, + "VideoSubsystem": { + "axis_downsizer_0": "", + "axis_upsizer_0": "", + "axis_linemem_single_0": "", + "axis_video_filter_0": "", + "axi_2d_mmvs_0": "" + } + }, + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", + "parameters": { + "AXI_ARBITRATION_SCHEME": { + "value": "TDM", + "value_src": "default" + }, + "BURST_LENGTH": { + "value": "8", + "value_src": "default" + }, + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "CAS_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CAS_WRITE_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CS_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_MASK_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "8", + "value_src": "default" + }, + "MEMORY_TYPE": { + "value": "COMPONENTS", + "value_src": "default" + }, + "MEM_ADDR_MAP": { + "value": "ROW_COLUMN_BANK", + "value_src": "default" + }, + "SLOT": { + "value": "Single", + "value_src": "default" + }, + "TIMEPERIOD_PS": { + "value": "1250", + "value_src": "default" + } + }, + "port_maps": { + "CAS_N": { + "physical_name": "DDR_cas_n", + "direction": "IO" + }, + "CKE": { + "physical_name": "DDR_cke", + "direction": "IO" + }, + "CK_N": { + "physical_name": "DDR_ck_n", + "direction": "IO" + }, + "CK_P": { + "physical_name": "DDR_ck_p", + "direction": "IO" + }, + "CS_N": { + "physical_name": "DDR_cs_n", + "direction": "IO" + }, + "RESET_N": { + "physical_name": "DDR_reset_n", + "direction": "IO" + }, + "ODT": { + "physical_name": "DDR_odt", + "direction": "IO" + }, + "RAS_N": { + "physical_name": "DDR_ras_n", + "direction": "IO" + }, + "WE_N": { + "physical_name": "DDR_we_n", + "direction": "IO" + }, + "BA": { + "physical_name": "DDR_ba", + "direction": "IO", + "left": "2", + "right": "0" + }, + "ADDR": { + "physical_name": "DDR_addr", + "direction": "IO", + "left": "14", + "right": "0" + }, + "DM": { + "physical_name": "DDR_dm", + "direction": "IO", + "left": "3", + "right": "0" + }, + "DQ": { + "physical_name": "DDR_dq", + "direction": "IO", + "left": "31", + "right": "0" + }, + "DQS_N": { + "physical_name": "DDR_dqs_n", + "direction": "IO", + "left": "3", + "right": "0" + }, + "DQS_P": { + "physical_name": "DDR_dqs_p", + "direction": "IO", + "left": "3", + "right": "0" + } + } + }, + "FIXED_IO": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + } + }, + "port_maps": { + "MIO": { + "physical_name": "FIXED_IO_mio", + "direction": "IO", + "left": "53", + "right": "0" + }, + "DDR_VRN": { + "physical_name": "FIXED_IO_ddr_vrn", + "direction": "IO" + }, + "DDR_VRP": { + "physical_name": "FIXED_IO_ddr_vrp", + "direction": "IO" + }, + "PS_SRSTB": { + "physical_name": "FIXED_IO_ps_srstb", + "direction": "IO" + }, + "PS_CLK": { + "physical_name": "FIXED_IO_ps_clk", + "direction": "IO" + }, + "PS_PORB": { + "physical_name": "FIXED_IO_ps_porb", + "direction": "IO" + } + } + } + }, + "ports": { + "BUTTON": { + "direction": "I", + "left": "3", + "right": "0" + }, + "HDMI_CLK_N": { + "direction": "O" + }, + "HDMI_CLK_P": { + "direction": "O" + }, + "HDMI_DATA_N": { + "direction": "O", + "left": "2", + "right": "0" + }, + "HDMI_DATA_P": { + "direction": "O", + "left": "2", + "right": "0" + }, + "LED": { + "direction": "O", + "left": "3", + "right": "0" + }, + "RGB_LED": { + "direction": "O", + "left": "5", + "right": "0" + }, + "SWITCH": { + "direction": "I", + "left": "3", + "right": "0" + } + }, + "components": { + "AXI_Intercon": { + "interface_ports": { + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI1": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S00_AXI1": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S00_AXI2": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI2": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M02_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I" + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "axi_mem_intercon": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip\\design_3_axi_mem_intercon_0\\design_3_axi_mem_intercon_0.xci", + "inst_hier_path": "AXI_Intercon/axi_mem_intercon", + "xci_name": "design_3_axi_mem_intercon_0", + "parameters": { + "NUM_MI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "design_3_auto_us_0", + "xci_path": "ip\\design_3_auto_us_0\\design_3_auto_us_0.xci", + "inst_hier_path": "AXI_Intercon/axi_mem_intercon/s00_couplers/auto_us", + "parameters": { + "MI_DATA_WIDTH": { + "value": "64" + }, + "SI_DATA_WIDTH": { + "value": "32" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_us_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_us/M_AXI" + ] + }, + "s00_couplers_to_auto_us": { + "interface_ports": [ + "S_AXI", + "auto_us/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn" + ] + } + } + } + }, + "interface_nets": { + "axi_mem_intercon_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_axi_mem_intercon": { + "interface_ports": [ + "s00_couplers/M_AXI", + "M00_AXI" + ] + } + }, + "nets": { + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "axi_mem_intercon_ACLK_net": { + "ports": [ + "M00_ACLK", + "s00_couplers/M_ACLK" + ] + }, + "axi_mem_intercon_ARESETN_net": { + "ports": [ + "M00_ARESETN", + "s00_couplers/M_ARESETN" + ] + } + } + }, + "ps7_0_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip\\design_3_ps7_0_axi_periph_0\\design_3_ps7_0_axi_periph_0.xci", + "inst_hier_path": "AXI_Intercon/ps7_0_axi_periph", + "xci_name": "design_3_ps7_0_axi_periph_0", + "parameters": { + "NUM_MI": { + "value": "3" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M02_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M02_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M02_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M02_ARESETN" + } + } + }, + "M02_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "design_3_xbar_0", + "xci_path": "ip\\design_3_xbar_0\\design_3_xbar_0.xci", + "inst_hier_path": "AXI_Intercon/ps7_0_axi_periph/xbar", + "parameters": { + "NUM_MI": { + "value": "3" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI", + "M02_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "xci_name": "design_3_auto_pc_0", + "xci_path": "ip\\design_3_auto_pc_0\\design_3_auto_pc_0.xci", + "inst_hier_path": "AXI_Intercon/ps7_0_axi_periph/s00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI4LITE" + }, + "SI_PROTOCOL": { + "value": "AXI3" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_pc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m02_couplers_to_m02_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "m00_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "m00_couplers/M_AXI", + "M00_AXI" + ] + }, + "m01_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "m01_couplers/M_AXI", + "M01_AXI" + ] + }, + "m02_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "m02_couplers/M_AXI", + "M02_AXI" + ] + }, + "ps7_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + }, + "xbar_to_m02_couplers": { + "interface_ports": [ + "xbar/M02_AXI", + "m02_couplers/S_AXI" + ] + } + }, + "nets": { + "ps7_0_axi_periph_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/S_ACLK", + "s00_couplers/M_ACLK", + "m00_couplers/M_ACLK", + "m01_couplers/M_ACLK", + "m02_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK", + "m02_couplers/S_ACLK" + ] + }, + "ps7_0_axi_periph_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/S_ARESETN", + "s00_couplers/M_ARESETN", + "m00_couplers/M_ARESETN", + "m01_couplers/M_ARESETN", + "m02_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN", + "m02_couplers/S_ARESETN" + ] + } + } + }, + "axi_interconnect_0": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip\\design_3_axi_interconnect_0_0\\design_3_axi_interconnect_0_0.xci", + "inst_hier_path": "AXI_Intercon/axi_interconnect_0", + "xci_name": "design_3_axi_interconnect_0_0", + "parameters": { + "NUM_MI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "design_3_auto_us_1", + "xci_path": "ip\\design_3_auto_us_1\\design_3_auto_us_1.xci", + "inst_hier_path": "AXI_Intercon/axi_interconnect_0/s00_couplers/auto_us", + "parameters": { + "MI_DATA_WIDTH": { + "value": "64" + }, + "SI_DATA_WIDTH": { + "value": "32" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_us_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_us/M_AXI" + ] + }, + "s00_couplers_to_auto_us": { + "interface_ports": [ + "S_AXI", + "auto_us/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn" + ] + } + } + } + }, + "interface_nets": { + "axi_interconnect_0_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_axi_interconnect_0": { + "interface_ports": [ + "s00_couplers/M_AXI", + "M00_AXI" + ] + } + }, + "nets": { + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "axi_interconnect_0_ACLK_net": { + "ports": [ + "M00_ACLK", + "s00_couplers/M_ACLK" + ] + }, + "axi_interconnect_0_ARESETN_net": { + "ports": [ + "M00_ARESETN", + "s00_couplers/M_ARESETN" + ] + } + } + } + }, + "interface_nets": { + "Conn1": { + "interface_ports": [ + "ps7_0_axi_periph/M01_AXI", + "M01_AXI" + ] + }, + "Conn2": { + "interface_ports": [ + "ps7_0_axi_periph/M02_AXI", + "M02_AXI" + ] + }, + "S00_AXI2_1": { + "interface_ports": [ + "S00_AXI2", + "axi_interconnect_0/S00_AXI" + ] + }, + "axi_interconnect_0_M00_AXI": { + "interface_ports": [ + "M00_AXI2", + "axi_interconnect_0/M00_AXI" + ] + }, + "axi_mem_intercon_M00_AXI": { + "interface_ports": [ + "M00_AXI1", + "axi_mem_intercon/M00_AXI" + ] + }, + "processing_system7_0_M_AXI_GP0": { + "interface_ports": [ + "S00_AXI", + "ps7_0_axi_periph/S00_AXI" + ] + }, + "ps7_0_axi_periph_M00_AXI": { + "interface_ports": [ + "M00_AXI", + "ps7_0_axi_periph/M00_AXI" + ] + }, + "zynq_base_hdmi_0_M_AXI": { + "interface_ports": [ + "S00_AXI1", + "axi_mem_intercon/S00_AXI" + ] + } + }, + "nets": { + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "ACLK", + "axi_mem_intercon/ACLK", + "axi_mem_intercon/M00_ACLK", + "axi_mem_intercon/S00_ACLK", + "ps7_0_axi_periph/ACLK", + "ps7_0_axi_periph/M00_ACLK", + "ps7_0_axi_periph/S00_ACLK", + "axi_interconnect_0/ACLK", + "axi_interconnect_0/S00_ACLK", + "axi_interconnect_0/M00_ACLK", + "ps7_0_axi_periph/M01_ACLK", + "ps7_0_axi_periph/M02_ACLK" + ] + }, + "rst_ps7_0_100M_peripheral_aresetn": { + "ports": [ + "S00_ARESETN", + "axi_mem_intercon/ARESETN", + "axi_mem_intercon/M00_ARESETN", + "axi_mem_intercon/S00_ARESETN", + "ps7_0_axi_periph/ARESETN", + "ps7_0_axi_periph/M00_ARESETN", + "ps7_0_axi_periph/S00_ARESETN", + "axi_interconnect_0/ARESETN", + "axi_interconnect_0/S00_ARESETN", + "axi_interconnect_0/M00_ARESETN", + "ps7_0_axi_periph/M01_ARESETN", + "ps7_0_axi_periph/M02_ARESETN" + ] + } + } + }, + "PS": { + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0" + }, + "FIXED_IO": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0" + }, + "M_AXI_GP0": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI_HP0": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI_ACP": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "FCLK_CLK0": { + "type": "clk", + "direction": "O" + }, + "FCLK_CLK3": { + "type": "clk", + "direction": "O" + }, + "In0": { + "direction": "I", + "left": "0", + "right": "0" + }, + "peripheral_aresetn": { + "type": "rst", + "direction": "O", + "left": "0", + "right": "0" + }, + "In1": { + "type": "intr", + "direction": "I" + } + }, + "components": { + "processing_system7_0": { + "vlnv": "xilinx.com:ip:processing_system7:5.5", + "xci_name": "design_3_processing_system7_0_0", + "xci_path": "ip\\design_3_processing_system7_0_0\\design_3_processing_system7_0_0.xci", + "inst_hier_path": "PS/processing_system7_0", + "parameters": { + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { + "value": "666.666687" + }, + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.158730" + }, + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "66.666672" + }, + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { + "value": "50.000000" + }, + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_APU_CLK_RATIO_ENABLE": { + "value": "6:2:1" + }, + "PCW_APU_PERIPHERAL_FREQMHZ": { + "value": "667" + }, + "PCW_CAN0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_CAN_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_CLK0_FREQ": { + "value": "100000000" + }, + "PCW_CLK1_FREQ": { + "value": "125000000" + }, + "PCW_CLK2_FREQ": { + "value": "200000000" + }, + "PCW_CLK3_FREQ": { + "value": "66666672" + }, + "PCW_CPU_CPU_6X4X_MAX_RANGE": { + "value": "667" + }, + "PCW_CPU_PERIPHERAL_CLKSRC": { + "value": "ARM PLL" + }, + "PCW_CRYSTAL_PERIPHERAL_FREQMHZ": { + "value": "33.333333" + }, + "PCW_DCI_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.159" + }, + "PCW_DDR_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DDR_RAM_HIGHADDR": { + "value": "0x3FFFFFFF" + }, + "PCW_ENET0_ENET0_IO": { + "value": "MIO 16 .. 27" + }, + "PCW_ENET0_GRP_MDIO_ENABLE": { + "value": "1" + }, + "PCW_ENET0_GRP_MDIO_IO": { + "value": "MIO 52 .. 53" + }, + "PCW_ENET0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_ENET0_PERIPHERAL_FREQMHZ": { + "value": "1000 Mbps" + }, + "PCW_ENET0_RESET_ENABLE": { + "value": "0" + }, + "PCW_ENET1_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_ENET_RESET_ENABLE": { + "value": "1" + }, + "PCW_ENET_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_ENET_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_EN_4K_TIMER": { + "value": "0" + }, + "PCW_EN_CAN0": { + "value": "0" + }, + "PCW_EN_CLK1_PORT": { + "value": "1" + }, + "PCW_EN_CLK2_PORT": { + "value": "1" + }, + "PCW_EN_CLK3_PORT": { + "value": "1" + }, + "PCW_EN_EMIO_CAN0": { + "value": "0" + }, + "PCW_EN_EMIO_I2C0": { + "value": "0" + }, + "PCW_EN_EMIO_I2C1": { + "value": "0" + }, + "PCW_EN_EMIO_SPI0": { + "value": "0" + }, + "PCW_EN_EMIO_SPI1": { + "value": "0" + }, + "PCW_EN_EMIO_TTC0": { + "value": "1" + }, + "PCW_EN_EMIO_UART0": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO0": { + "value": "1" + }, + "PCW_EN_ENET0": { + "value": "1" + }, + "PCW_EN_GPIO": { + "value": "1" + }, + "PCW_EN_I2C0": { + "value": "1" + }, + "PCW_EN_I2C1": { + "value": "1" + }, + "PCW_EN_QSPI": { + "value": "1" + }, + "PCW_EN_SDIO0": { + "value": "1" + }, + "PCW_EN_SPI0": { + "value": "0" + }, + "PCW_EN_SPI1": { + "value": "0" + }, + "PCW_EN_TTC0": { + "value": "1" + }, + "PCW_EN_UART0": { + "value": "1" + }, + "PCW_EN_UART1": { + "value": "1" + }, + "PCW_EN_USB0": { + "value": "1" + }, + "PCW_FCLK_CLK1_BUF": { + "value": "TRUE" + }, + "PCW_FCLK_CLK2_BUF": { + "value": "TRUE" + }, + "PCW_FCLK_CLK3_BUF": { + "value": "TRUE" + }, + "PCW_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "125" + }, + "PCW_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "65" + }, + "PCW_FPGA_FCLK0_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK1_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK2_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK3_ENABLE": { + "value": "1" + }, + "PCW_GPIO_MIO_GPIO_ENABLE": { + "value": "1" + }, + "PCW_GPIO_MIO_GPIO_IO": { + "value": "MIO" + }, + "PCW_GPIO_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C0_GRP_INT_ENABLE": { + "value": "0" + }, + "PCW_I2C0_I2C0_IO": { + "value": "MIO 14 .. 15" + }, + "PCW_I2C0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_I2C0_RESET_ENABLE": { + "value": "0" + }, + "PCW_I2C1_GRP_INT_ENABLE": { + "value": "0" + }, + "PCW_I2C1_I2C1_IO": { + "value": "MIO 12 .. 13" + }, + "PCW_I2C1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_I2C_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_I2C_RESET_ENABLE": { + "value": "1" + }, + "PCW_I2C_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_IRQ_F2P_INTR": { + "value": "1" + }, + "PCW_IRQ_F2P_MODE": { + "value": "DIRECT" + }, + "PCW_MIO_0_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_0_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_0_SLEW": { + "value": "slow" + }, + "PCW_MIO_10_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_10_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_10_SLEW": { + "value": "slow" + }, + "PCW_MIO_11_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_11_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_11_SLEW": { + "value": "slow" + }, + "PCW_MIO_12_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_12_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_12_SLEW": { + "value": "slow" + }, + "PCW_MIO_13_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_13_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_13_SLEW": { + "value": "slow" + }, + "PCW_MIO_14_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_14_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_14_SLEW": { + "value": "slow" + }, + "PCW_MIO_15_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_15_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_15_SLEW": { + "value": "slow" + }, + "PCW_MIO_16_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_16_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_16_SLEW": { + "value": "fast" + }, + "PCW_MIO_17_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_17_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_17_SLEW": { + "value": "fast" + }, + "PCW_MIO_18_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_18_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_18_SLEW": { + "value": "fast" + }, + "PCW_MIO_19_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_19_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_19_SLEW": { + "value": "fast" + }, + "PCW_MIO_1_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_1_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_1_SLEW": { + "value": "slow" + }, + "PCW_MIO_20_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_20_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_20_SLEW": { + "value": "fast" + }, + "PCW_MIO_21_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_21_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_21_SLEW": { + "value": "fast" + }, + "PCW_MIO_22_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_22_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_22_SLEW": { + "value": "fast" + }, + "PCW_MIO_23_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_23_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_23_SLEW": { + "value": "fast" + }, + "PCW_MIO_24_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_24_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_24_SLEW": { + "value": "fast" + }, + "PCW_MIO_25_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_25_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_25_SLEW": { + "value": "fast" + }, + "PCW_MIO_26_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_26_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_26_SLEW": { + "value": "fast" + }, + "PCW_MIO_27_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_27_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_27_SLEW": { + "value": "fast" + }, + "PCW_MIO_28_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_28_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_28_SLEW": { + "value": "fast" + }, + "PCW_MIO_29_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_29_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_29_SLEW": { + "value": "fast" + }, + "PCW_MIO_2_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_2_SLEW": { + "value": "slow" + }, + "PCW_MIO_30_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_30_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_30_SLEW": { + "value": "fast" + }, + "PCW_MIO_31_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_31_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_31_SLEW": { + "value": "fast" + }, + "PCW_MIO_32_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_32_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_32_SLEW": { + "value": "fast" + }, + "PCW_MIO_33_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_33_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_33_SLEW": { + "value": "fast" + }, + "PCW_MIO_34_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_34_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_34_SLEW": { + "value": "fast" + }, + "PCW_MIO_35_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_35_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_35_SLEW": { + "value": "fast" + }, + "PCW_MIO_36_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_36_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_36_SLEW": { + "value": "fast" + }, + "PCW_MIO_37_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_37_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_37_SLEW": { + "value": "fast" + }, + "PCW_MIO_38_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_38_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_38_SLEW": { + "value": "fast" + }, + "PCW_MIO_39_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_39_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_39_SLEW": { + "value": "fast" + }, + "PCW_MIO_3_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_3_SLEW": { + "value": "slow" + }, + "PCW_MIO_40_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_40_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_40_SLEW": { + "value": "slow" + }, + "PCW_MIO_41_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_41_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_41_SLEW": { + "value": "slow" + }, + "PCW_MIO_42_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_42_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_42_SLEW": { + "value": "slow" + }, + "PCW_MIO_43_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_43_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_43_SLEW": { + "value": "slow" + }, + "PCW_MIO_44_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_44_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_44_SLEW": { + "value": "slow" + }, + "PCW_MIO_45_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_45_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_45_SLEW": { + "value": "slow" + }, + "PCW_MIO_46_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_46_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_46_SLEW": { + "value": "slow" + }, + "PCW_MIO_47_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_47_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_47_SLEW": { + "value": "slow" + }, + "PCW_MIO_48_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_48_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_48_SLEW": { + "value": "slow" + }, + "PCW_MIO_49_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_49_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_49_SLEW": { + "value": "slow" + }, + "PCW_MIO_4_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_4_SLEW": { + "value": "slow" + }, + "PCW_MIO_50_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_50_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_50_SLEW": { + "value": "slow" + }, + "PCW_MIO_51_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_51_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_51_SLEW": { + "value": "slow" + }, + "PCW_MIO_52_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_52_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_52_SLEW": { + "value": "slow" + }, + "PCW_MIO_53_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_53_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_53_SLEW": { + "value": "slow" + }, + "PCW_MIO_5_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_5_SLEW": { + "value": "slow" + }, + "PCW_MIO_6_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_6_SLEW": { + "value": "slow" + }, + "PCW_MIO_7_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_7_SLEW": { + "value": "slow" + }, + "PCW_MIO_8_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_8_SLEW": { + "value": "slow" + }, + "PCW_MIO_9_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_9_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_9_SLEW": { + "value": "slow" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": [ + "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#UART 0#UART 0#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet", + "0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0" + ] + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#rx#tx#scl#sda#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio" + }, + "PCW_OVERRIDE_BASIC_CLOCK": { + "value": "0" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY0": { + "value": "0.221" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY1": { + "value": "0.222" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY2": { + "value": "0.217" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY3": { + "value": "0.244" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.050" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.044" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2": { + "value": "-0.035" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3": { + "value": "-0.100" + }, + "PCW_PCAP_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_PJTAG_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_PLL_BYPASSMODE_ENABLE": { + "value": "0" + }, + "PCW_PRESET_BANK0_VOLTAGE": { + "value": "LVCMOS 3.3V" + }, + "PCW_PRESET_BANK1_VOLTAGE": { + "value": "LVCMOS 1.8V" + }, + "PCW_QSPI_GRP_FBCLK_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_FBCLK_IO": { + "value": "MIO 8" + }, + "PCW_QSPI_GRP_IO1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_SINGLE_SS_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_SINGLE_SS_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_QSPI_GRP_SS1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_INTERNAL_HIGHADDRESS": { + "value": "0xFCFFFFFF" + }, + "PCW_QSPI_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_QSPI_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_QSPI_QSPI_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_SD0_GRP_CD_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_CD_IO": { + "value": "MIO 47" + }, + "PCW_SD0_GRP_POW_ENABLE": { + "value": "0" + }, + "PCW_SD0_GRP_WP_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_WP_IO": { + "value": "EMIO" + }, + "PCW_SD0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_SD0_SD0_IO": { + "value": "MIO 40 .. 45" + }, + "PCW_SDIO_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SDIO_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_SDIO_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_SINGLE_QSPI_DATA_MODE": { + "value": "x4" + }, + "PCW_SMC_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SPI0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_TPIU_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_TTC0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_TTC0_TTC0_IO": { + "value": "EMIO" + }, + "PCW_TTC_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_UART0_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART0_UART0_IO": { + "value": "MIO 10 .. 11" + }, + "PCW_UART1_BAUD_RATE": { + "value": "115200" + }, + "PCW_UART1_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART1_UART1_IO": { + "value": "MIO 48 .. 49" + }, + "PCW_UART_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_UART_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_UART_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { + "value": "533.333374" + }, + "PCW_UIPARAM_DDR_ADV_ENABLE": { + "value": "0" + }, + "PCW_UIPARAM_DDR_AL": { + "value": "0" + }, + "PCW_UIPARAM_DDR_BL": { + "value": "8" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY0": { + "value": "0.221" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY1": { + "value": "0.222" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY2": { + "value": "0.217" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY3": { + "value": "0.244" + }, + "PCW_UIPARAM_DDR_BUS_WIDTH": { + "value": "32 Bit" + }, + "PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM": { + "value": "18.8" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM": { + "value": "18.8" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM": { + "value": "18.8" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM": { + "value": "18.8" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_STOP_EN": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_0_LENGTH_MM": { + "value": "22.8" + }, + "PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH": { + "value": "105.056" + }, + "PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_1_LENGTH_MM": { + "value": "27.9" + }, + "PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH": { + "value": "66.904" + }, + "PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_2_LENGTH_MM": { + "value": "22.9" + }, + "PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH": { + "value": "89.1715" + }, + "PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_3_LENGTH_MM": { + "value": "29.4" + }, + "PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH": { + "value": "113.63" + }, + "PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.050" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.044" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2": { + "value": "-0.035" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3": { + "value": "-0.100" + }, + "PCW_UIPARAM_DDR_DQ_0_LENGTH_MM": { + "value": "22.8" + }, + "PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH": { + "value": "98.503" + }, + "PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_1_LENGTH_MM": { + "value": "27.9" + }, + "PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH": { + "value": "68.5855" + }, + "PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_2_LENGTH_MM": { + "value": "22.9" + }, + "PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH": { + "value": "90.295" + }, + "PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_3_LENGTH_MM": { + "value": "29.4" + }, + "PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH": { + "value": "103.977" + }, + "PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_ENABLE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_FREQ_MHZ": { + "value": "533.333333" + }, + "PCW_UIPARAM_DDR_HIGH_TEMP": { + "value": "Normal (0-85)" + }, + "PCW_UIPARAM_DDR_MEMORY_TYPE": { + "value": "DDR 3 (Low Voltage)" + }, + "PCW_UIPARAM_DDR_PARTNO": { + "value": "MT41K256M16 RE-125" + }, + "PCW_UIPARAM_DDR_TRAIN_DATA_EYE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_READ_GATE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL": { + "value": "1" + }, + "PCW_UIPARAM_DDR_USE_INTERNAL_VREF": { + "value": "0" + }, + "PCW_USB0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_USB0_RESET_ENABLE": { + "value": "1" + }, + "PCW_USB0_RESET_IO": { + "value": "MIO 46" + }, + "PCW_USB0_USB0_IO": { + "value": "MIO 28 .. 39" + }, + "PCW_USB_RESET_ENABLE": { + "value": "1" + }, + "PCW_USB_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_USB_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_USE_AXI_NONSECURE": { + "value": "0" + }, + "PCW_USE_CROSS_TRIGGER": { + "value": "0" + }, + "PCW_USE_DEFAULT_ACP_USER_VAL": { + "value": "1" + }, + "PCW_USE_FABRIC_INTERRUPT": { + "value": "1" + }, + "PCW_USE_M_AXI_GP0": { + "value": "1" + }, + "PCW_USE_S_AXI_ACP": { + "value": "1" + }, + "PCW_USE_S_AXI_GP0": { + "value": "0" + }, + "PCW_USE_S_AXI_HP0": { + "value": "1" + } + }, + "interface_ports": { + "M_AXI_GP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x40000000", + "maximum": "0x7FFFFFFF", + "width": "32" + } + }, + "S_AXI_ACP": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "memory_map_ref": "S_AXI_ACP" + }, + "S_AXI_HP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "memory_map_ref": "S_AXI_HP0" + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32", + "local_memory_map": { + "name": "Data", + "description": "Address Space Segments", + "address_blocks": { + "segment1": { + "name": "segment1", + "display_name": "segment1", + "base_address": "0x00000000", + "range": "256K", + "width": "18", + "usage": "register" + }, + "segment2": { + "name": "segment2", + "display_name": "segment2", + "base_address": "0x00040000", + "range": "256K", + "width": "19", + "usage": "register" + }, + "segment3": { + "name": "segment3", + "display_name": "segment3", + "base_address": "0x00080000", + "range": "512K", + "width": "20", + "usage": "register" + }, + "segment4": { + "name": "segment4", + "display_name": "segment4", + "base_address": "0x00100000", + "range": "1023M", + "width": "30", + "usage": "register" + }, + "M_AXI_GP0": { + "name": "M_AXI_GP0", + "display_name": "M_AXI_GP0", + "base_address": "0x40000000", + "range": "1G", + "width": "31", + "usage": "register" + }, + "M_AXI_GP1": { + "name": "M_AXI_GP1", + "display_name": "M_AXI_GP1", + "base_address": "0x80000000", + "range": "1G", + "width": "32", + "usage": "register" + }, + "IO_Peripheral_Registers": { + "name": "IO_Peripheral_Registers", + "display_name": "IO Peripheral Registers", + "base_address": "0xE0000000", + "range": "3M", + "width": "32", + "usage": "register" + }, + "SMC_Memories": { + "name": "SMC_Memories", + "display_name": "SMC Memories", + "base_address": "0xE1000000", + "range": "80M", + "width": "32", + "usage": "register" + }, + "SLCR_Registers": { + "name": "SLCR_Registers", + "display_name": "SLCR Registers", + "base_address": "0xF8000000", + "range": "3K", + "width": "32", + "usage": "register" + }, + "PS_System_Registers": { + "name": "PS_System_Registers", + "display_name": "PS System Registers", + "base_address": "0xF8001000", + "range": "8252K", + "width": "32", + "usage": "register" + }, + "CPU_Private_Registers": { + "name": "CPU_Private_Registers", + "display_name": "CPU Private Registers", + "base_address": "0xF8900000", + "range": "6156K", + "width": "32", + "usage": "register" + }, + "segment5": { + "name": "segment5", + "display_name": "segment5", + "base_address": "0xFC000000", + "range": "32M", + "width": "32", + "usage": "register" + }, + "segment6": { + "name": "segment6", + "display_name": "segment6", + "base_address": "0xFFFC0000", + "range": "256K", + "width": "32", + "usage": "register" + } + } + } + } + } + } + }, + "rst_ps7_0_100M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "design_3_rst_ps7_0_100M_0", + "xci_path": "ip\\design_3_rst_ps7_0_100M_0\\design_3_rst_ps7_0_100M_0.xci", + "inst_hier_path": "PS/rst_ps7_0_100M" + }, + "xlconcat_0": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "xci_name": "design_3_xlconcat_0_0", + "xci_path": "ip\\design_3_xlconcat_0_0\\design_3_xlconcat_0_0.xci", + "inst_hier_path": "PS/xlconcat_0", + "parameters": { + "IN0_WIDTH": { + "value": "1" + }, + "IN1_WIDTH": { + "value": "1" + }, + "NUM_PORTS": { + "value": "2" + } + } + }, + "xlconstant_0": { + "vlnv": "xilinx.com:ip:xlconstant:1.1", + "xci_name": "design_3_xlconstant_0_0", + "xci_path": "ip\\design_3_xlconstant_0_0\\design_3_xlconstant_0_0.xci", + "inst_hier_path": "PS/xlconstant_0" + } + }, + "interface_nets": { + "S_AXI_ACP_1": { + "interface_ports": [ + "S_AXI_HP0", + "processing_system7_0/S_AXI_HP0" + ] + }, + "S_AXI_ACP_2": { + "interface_ports": [ + "S_AXI_ACP", + "processing_system7_0/S_AXI_ACP" + ] + }, + "processing_system7_0_DDR": { + "interface_ports": [ + "DDR", + "processing_system7_0/DDR" + ] + }, + "processing_system7_0_FIXED_IO": { + "interface_ports": [ + "FIXED_IO", + "processing_system7_0/FIXED_IO" + ] + }, + "processing_system7_0_M_AXI_GP0": { + "interface_ports": [ + "M_AXI_GP0", + "processing_system7_0/M_AXI_GP0" + ] + } + }, + "nets": { + "In0_1": { + "ports": [ + "In0", + "xlconcat_0/In0" + ] + }, + "In1_1": { + "ports": [ + "In1", + "xlconcat_0/In1" + ] + }, + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "processing_system7_0/FCLK_CLK0", + "FCLK_CLK0", + "processing_system7_0/M_AXI_GP0_ACLK", + "processing_system7_0/S_AXI_HP0_ACLK", + "rst_ps7_0_100M/slowest_sync_clk", + "processing_system7_0/S_AXI_ACP_ACLK" + ] + }, + "processing_system7_0_FCLK_CLK3": { + "ports": [ + "processing_system7_0/FCLK_CLK3", + "FCLK_CLK3" + ] + }, + "processing_system7_0_FCLK_RESET0_N": { + "ports": [ + "processing_system7_0/FCLK_RESET0_N", + "rst_ps7_0_100M/ext_reset_in" + ] + }, + "rst_ps7_0_100M_peripheral_aresetn": { + "ports": [ + "rst_ps7_0_100M/peripheral_aresetn", + "peripheral_aresetn" + ] + }, + "xlconcat_0_dout": { + "ports": [ + "xlconcat_0/dout", + "processing_system7_0/IRQ_F2P" + ] + }, + "xlconstant_0_dout": { + "ports": [ + "xlconstant_0/dout", + "processing_system7_0/SDIO0_WP" + ] + } + } + }, + "ZYNQ_BASE": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXIL": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "BUTTON_0": { + "direction": "I", + "left": "3", + "right": "0" + }, + "HDMI_CLK_N_0": { + "direction": "O" + }, + "HDMI_CLK_P_0": { + "direction": "O" + }, + "HDMI_DATA_N_0": { + "direction": "O", + "left": "2", + "right": "0" + }, + "HDMI_DATA_P_0": { + "direction": "O", + "left": "2", + "right": "0" + }, + "LED_0": { + "direction": "O", + "left": "3", + "right": "0" + }, + "M_AXI_ACLK": { + "type": "clk", + "direction": "I" + }, + "M_AXI_ARESETN": { + "type": "rst", + "direction": "I" + }, + "RGB_LED_0": { + "direction": "O", + "left": "5", + "right": "0" + }, + "SWITCH_0": { + "direction": "I", + "left": "3", + "right": "0" + }, + "VIDEO_CLK": { + "direction": "I" + }, + "VIDEO_INTERRUPT": { + "direction": "O" + } + }, + "components": { + "zynq_base_hdmi_0": { + "vlnv": "xilinx.com:user:zynq_base_hdmi:1.0", + "xci_name": "design_3_zynq_base_hdmi_0_0", + "xci_path": "ip\\design_3_zynq_base_hdmi_0_0\\design_3_zynq_base_hdmi_0_0.xci", + "inst_hier_path": "ZYNQ_BASE/zynq_base_hdmi_0", + "parameters": { + "FIFO_AWIDTH": { + "value": "12" + }, + "HAS_HDMI": { + "value": "true" + }, + "HAS_VGA_OUTPUTS": { + "value": "false" + } + }, + "interface_ports": { + "M_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "M_AXI", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "M_AXI": { + "range": "4G", + "width": "32" + } + } + } + } + }, + "interface_nets": { + "ps7_0_axi_periph_M00_AXI": { + "interface_ports": [ + "S_AXIL", + "zynq_base_hdmi_0/S_AXIL" + ] + }, + "zynq_base_hdmi_0_M_AXI": { + "interface_ports": [ + "M_AXI", + "zynq_base_hdmi_0/M_AXI" + ] + } + }, + "nets": { + "BUTTON_0_1": { + "ports": [ + "BUTTON_0", + "zynq_base_hdmi_0/BUTTON" + ] + }, + "SWITCH_0_1": { + "ports": [ + "SWITCH_0", + "zynq_base_hdmi_0/SWITCH" + ] + }, + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "M_AXI_ACLK", + "zynq_base_hdmi_0/M_AXI_ACLK", + "zynq_base_hdmi_0/S_AXIL_ACLK" + ] + }, + "processing_system7_0_FCLK_CLK3": { + "ports": [ + "VIDEO_CLK", + "zynq_base_hdmi_0/VIDEO_CLK" + ] + }, + "rst_ps7_0_100M_peripheral_aresetn": { + "ports": [ + "M_AXI_ARESETN", + "zynq_base_hdmi_0/M_AXI_ARESETN", + "zynq_base_hdmi_0/S_AXIL_ARESETN", + "zynq_base_hdmi_0/VIDEO_RESETN" + ] + }, + "zynq_base_hdmi_0_HDMI_CLK_N": { + "ports": [ + "zynq_base_hdmi_0/HDMI_CLK_N", + "HDMI_CLK_N_0" + ] + }, + "zynq_base_hdmi_0_HDMI_CLK_P": { + "ports": [ + "zynq_base_hdmi_0/HDMI_CLK_P", + "HDMI_CLK_P_0" + ] + }, + "zynq_base_hdmi_0_HDMI_DATA_N": { + "ports": [ + "zynq_base_hdmi_0/HDMI_DATA_N", + "HDMI_DATA_N_0" + ] + }, + "zynq_base_hdmi_0_HDMI_DATA_P": { + "ports": [ + "zynq_base_hdmi_0/HDMI_DATA_P", + "HDMI_DATA_P_0" + ] + }, + "zynq_base_hdmi_0_LED": { + "ports": [ + "zynq_base_hdmi_0/LED", + "LED_0" + ] + }, + "zynq_base_hdmi_0_RGB_LED": { + "ports": [ + "zynq_base_hdmi_0/RGB_LED", + "RGB_LED_0" + ] + }, + "zynq_base_hdmi_0_VIDEO_INTERRUPT": { + "ports": [ + "zynq_base_hdmi_0/VIDEO_INTERRUPT", + "VIDEO_INTERRUPT" + ] + } + } + }, + "VideoSubsystem": { + "interface_ports": { + "S_AXIL": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXIL1": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "ACLK": { + "type": "clk", + "direction": "I" + }, + "VS2MM_INTERRUPT": { + "type": "intr", + "direction": "O" + } + }, + "components": { + "axis_downsizer_0": { + "vlnv": "xilinx.com:user:axis_downsizer:1.0", + "xci_name": "design_3_axis_downsizer_0_0", + "xci_path": "ip\\design_3_axis_downsizer_0_0\\design_3_axis_downsizer_0_0.xci", + "inst_hier_path": "VideoSubsystem/axis_downsizer_0", + "parameters": { + "SIZE_FACTOR": { + "value": "4" + } + } + }, + "axis_upsizer_0": { + "vlnv": "xilinx.com:user:axis_upsizer:1.0", + "xci_name": "design_3_axis_upsizer_0_0", + "xci_path": "ip\\design_3_axis_upsizer_0_0\\design_3_axis_upsizer_0_0.xci", + "inst_hier_path": "VideoSubsystem/axis_upsizer_0", + "parameters": { + "SIZE_FACTOR": { + "value": "4" + } + } + }, + "axis_linemem_single_0": { + "vlnv": "xilinx.com:user:axis_linemem_single_master:1.0", + "xci_name": "design_3_axis_linemem_single_0_0", + "xci_path": "ip\\design_3_axis_linemem_single_0_0\\design_3_axis_linemem_single_0_0.xci", + "inst_hier_path": "VideoSubsystem/axis_linemem_single_0", + "parameters": { + "DATA_WIDTH": { + "value": "8" + } + } + }, + "axis_video_filter_0": { + "vlnv": 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} ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "ACLK" } ] + } + } + }, + "memory_maps": { + "S_AXIL": { + "display_name": "S_AXIL", + "address_blocks": { + "reg0": { + "base_address": "0x0", + "range": "0x8000", + "display_name": "reg0", + "usage": "register" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/design_3_processing_system7_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/design_3_processing_system7_0_0.xci new file mode 100644 index 0000000..6702ba9 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ip/design_3_processing_system7_0_0/design_3_processing_system7_0_0.xci @@ -0,0 +1,1692 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_3_processing_system7_0_0", + "cell_name": "PS/processing_system7_0", + "component_reference": "xilinx.com:ip:processing_system7:5.5", + "ip_revision": "6", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_3/ip/design_3_processing_system7_0_0", + "parameters": { + "component_parameters": { + "PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_DDR_RAM_HIGHADDR": [ { "value": "0x3FFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", 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"resolve_type": "user", "usage": "all" } ], + "PCW_PJTAG_PJTAG_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C0_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C_RESET_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C_RESET_SELECT": [ { "value": "Share reset pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C1_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C1_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_APU_CLK_RATIO_ENABLE": [ { "value": "6:2:1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET0_PERIPHERAL_FREQMHZ": [ { "value": "1000 Mbps", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET1_PERIPHERAL_FREQMHZ": [ { "value": "1000 Mbps", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CPU_PERIPHERAL_CLKSRC": [ { "value": "ARM PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_DDR_PERIPHERAL_CLKSRC": [ { "value": "DDR PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_QSPI_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SDIO_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": 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"PCW_MIO_52_PULLUP": [ { "value": "enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_52_IOTYPE": [ { "value": "LVCMOS 1.8V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_52_DIRECTION": [ { "value": "out", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_52_SLEW": [ { "value": "slow", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_53_PULLUP": [ { "value": "enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_53_IOTYPE": [ { "value": "LVCMOS 1.8V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_53_DIRECTION": [ { "value": "inout", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_53_SLEW": [ { "value": "slow", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "preset": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_GENERATE_SUMMARY": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_TREE_PERIPHERALS": [ { "value": "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#UART 0#UART 0#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_TREE_SIGNALS": [ { "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#rx#tx#scl#sda#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_PS7_SI_REV": [ { "value": "PRODUCTION", "resolve_type": "user", "usage": "all" } ], + "PCW_FPGA_FCLK0_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_FPGA_FCLK1_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_FPGA_FCLK2_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_FPGA_FCLK3_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + 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], + "PCW_NAND_CYCLES_T_RC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_CYCLE_T0": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_CYCLE_T1": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_CYCLE_T2": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_CYCLE_T3": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_CYCLE_T4": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_CYCLE_T5": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_CYCLE_T6": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ], + "PCW_PACKAGE_NAME": [ { "value": "clg400", "resolve_type": "user", "usage": "all" } ], + "PCW_PLL_BYPASSMODE_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Component_Name": [ { "value": "design_3_processing_system7_0_0", "resolve_type": "user", "usage": "all" } ] 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"resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": 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"0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": 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"M04_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + 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"generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "S_AXIL_ACLK" } ] + } + } + }, + "address_spaces": { + "M_AXI": { + "range": "4294967296", + "width": "32" + } + }, + "memory_maps": { + "S_AXIL": { + "address_blocks": { + "reg0": { + "base_address": "0", + "range": "65536", + "usage": "register" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_205a0ed2.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_205a0ed2.ui new file mode 100644 index 0000000..6d7181a --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_205a0ed2.ui @@ -0,0 +1,118 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"5.0", + "Default View_TopLeft":"2145,807", + "ExpandedHierarchyInLayout":"/AXI_Intercon|/PS|/ZYNQ_BASE|/VideoSubsystem", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace port DDR -pg 1 -lvl 4 -x 3570 -y 730 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 4 -x 3570 -y 760 -defaultsOSRD +preplace port port-id_HDMI_CLK_N -pg 1 -lvl 4 -x 3570 -y 120 -defaultsOSRD +preplace port port-id_HDMI_CLK_P -pg 1 -lvl 4 -x 3570 -y 150 -defaultsOSRD +preplace portBus BUTTON -pg 1 -lvl 0 -x 0 -y 170 -defaultsOSRD +preplace portBus HDMI_DATA_N -pg 1 -lvl 4 -x 3570 -y 180 -defaultsOSRD +preplace portBus HDMI_DATA_P -pg 1 -lvl 4 -x 3570 -y 210 -defaultsOSRD +preplace portBus LED -pg 1 -lvl 4 -x 3570 -y 240 -defaultsOSRD +preplace portBus RGB_LED -pg 1 -lvl 4 -x 3570 -y 270 -defaultsOSRD +preplace portBus SWITCH -pg 1 -lvl 0 -x 0 -y 230 -defaultsOSRD +preplace inst AXI_Intercon -pg 1 -lvl 2 -x 1840 -y 460 -defaultsOSRD +preplace inst PS -pg 1 -lvl 3 -x 2490 -y 660 -defaultsOSRD +preplace inst ZYNQ_BASE -pg 1 -lvl 3 -x 2490 -y 130 -defaultsOSRD +preplace inst VideoSubsystem -pg 1 -lvl 1 -x 210 -y 1300 -defaultsOSRD -resize 144 160 +preplace inst AXI_Intercon|axi_mem_intercon -pg 1 -lvl 1 -x 1930 -y 810 -defaultsOSRD +preplace inst AXI_Intercon|ps7_0_axi_periph -pg 1 -lvl 1 -x 1930 -y 550 -defaultsOSRD +preplace inst AXI_Intercon|axi_interconnect_0 -pg 1 -lvl 1 -x 1930 -y 1030 -defaultsOSRD +preplace inst PS|processing_system7_0 -pg 1 -lvl 2 -x 2800 -y 870 -defaultsOSRD +preplace inst PS|rst_ps7_0_100M -pg 1 -lvl 3 -x 3200 -y 1020 -defaultsOSRD +preplace inst PS|xlconcat_0 -pg 1 -lvl 1 -x 2490 -y 930 -defaultsOSRD +preplace inst PS|xlconstant_0 -pg 1 -lvl 2 -x 2800 -y 640 -defaultsOSRD +preplace inst ZYNQ_BASE|zynq_base_hdmi_0 -pg 1 -lvl 1 -x 2580 -y 170 -defaultsOSRD +preplace inst VideoSubsystem|axis_downsizer_0 -pg 1 -lvl 1 -x 300 -y 1320 -defaultsOSRD +preplace inst VideoSubsystem|axis_upsizer_0 -pg 1 -lvl 4 -x 1030 -y 1550 -defaultsOSRD +preplace inst VideoSubsystem|axis_linemem_single_0 -pg 1 -lvl 2 -x 530 -y 1340 -defaultsOSRD +preplace inst VideoSubsystem|axis_video_filter_0 -pg 1 -lvl 3 -x 770 -y 1370 -defaultsOSRD +preplace inst VideoSubsystem|axi_2d_mmvs_0 -pg 1 -lvl 5 -x 1300 -y 1500 -defaultsOSRD +preplace netloc BUTTON_0_1 1 0 3 NJ 170 NJ 170 NJ +preplace netloc SWITCH_0_1 1 0 3 NJ 230 NJ 230 NJ +preplace netloc processing_system7_0_FCLK_CLK0 1 0 4 50 1200 1610 1200 2220 1150 3540 +preplace netloc processing_system7_0_FCLK_CLK3 1 2 2 2250 340 3530 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 4 30 1180 1620 1210 2240 1140 3520 +preplace netloc zynq_base_hdmi_0_HDMI_CLK_N 1 3 1 3550J 120n +preplace netloc zynq_base_hdmi_0_HDMI_CLK_P 1 3 1 3550J 150n +preplace netloc zynq_base_hdmi_0_HDMI_DATA_N 1 3 1 NJ 180 +preplace netloc zynq_base_hdmi_0_HDMI_DATA_P 1 3 1 3550J 200n +preplace netloc zynq_base_hdmi_0_LED 1 3 1 3550J 220n +preplace netloc zynq_base_hdmi_0_RGB_LED 1 3 1 3540J 240n +preplace netloc zynq_base_hdmi_0_VIDEO_INTERRUPT 1 2 2 2250 350 3520 +preplace netloc VideoSubsystem_VS2MM_INTERRUPT 1 1 2 N 1530 2250J +preplace netloc axi_mem_intercon_M00_AXI 1 2 1 N 810 +preplace netloc processing_system7_0_DDR 1 3 1 3550J 730n +preplace netloc processing_system7_0_FIXED_IO 1 3 1 NJ 760 +preplace netloc processing_system7_0_M_AXI_GP0 1 1 3 1640 1180 NJ 1180 3550 +preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 2200 90n +preplace netloc zynq_base_hdmi_0_M_AXI 1 1 3 1630 330 NJ 330 3530 +preplace netloc VideoSubsystem_M_AXI 1 1 1 1600 970n +preplace netloc AXI_Intercon_M00_AXI2 1 2 1 2230 830n +preplace netloc S_AXIL_1 1 0 3 40 1190 NJ 1190 2210 +preplace netloc S_AXIL1_1 1 0 3 20 1170 NJ 1170 2200 +preplace netloc AXI_Intercon|processing_system7_0_FCLK_CLK0 1 0 1 1780 470n +preplace netloc AXI_Intercon|rst_ps7_0_100M_peripheral_aresetn 1 0 1 1790 490n +preplace netloc AXI_Intercon|axi_mem_intercon_M00_AXI 1 1 1 N 810 +preplace netloc AXI_Intercon|processing_system7_0_M_AXI_GP0 1 0 1 N 450 +preplace netloc AXI_Intercon|ps7_0_axi_periph_M00_AXI 1 1 1 N 530 +preplace netloc AXI_Intercon|zynq_base_hdmi_0_M_AXI 1 0 1 N 750 +preplace netloc AXI_Intercon|S00_AXI2_1 1 0 1 N 970 +preplace netloc AXI_Intercon|axi_interconnect_0_M00_AXI 1 1 1 N 1030 +preplace netloc AXI_Intercon|Conn1 1 1 1 2080 550n +preplace netloc AXI_Intercon|Conn2 1 1 1 2070 570n +preplace netloc PS|In0_1 1 0 1 NJ 920 +preplace netloc PS|processing_system7_0_FCLK_CLK0 1 1 3 2580 1060 3030 890 NJ +preplace netloc PS|processing_system7_0_FCLK_CLK3 1 2 2 3020J 910 NJ +preplace netloc PS|processing_system7_0_FCLK_RESET0_N 1 2 1 N 1000 +preplace netloc PS|rst_ps7_0_100M_peripheral_aresetn 1 3 1 N 1060 +preplace netloc PS|xlconcat_0_dout 1 1 1 N 930 +preplace netloc PS|xlconstant_0_dout 1 2 1 3020 640n +preplace netloc PS|In1_1 1 0 1 N 940 +preplace netloc PS|S_AXI_ACP_1 1 0 2 NJ 810 2580 +preplace netloc PS|processing_system7_0_DDR 1 2 2 NJ 740 NJ +preplace netloc PS|processing_system7_0_FIXED_IO 1 2 2 NJ 760 NJ +preplace netloc PS|processing_system7_0_M_AXI_GP0 1 2 2 NJ 840 NJ +preplace netloc PS|S_AXI_ACP_2 1 0 2 NJ 830 NJ +preplace netloc ZYNQ_BASE|BUTTON_0_1 1 0 1 N 170 +preplace netloc ZYNQ_BASE|SWITCH_0_1 1 0 1 2410 150n +preplace netloc ZYNQ_BASE|processing_system7_0_FCLK_CLK0 1 0 1 2420 190n +preplace netloc ZYNQ_BASE|processing_system7_0_FCLK_CLK3 1 0 1 2400 110n +preplace netloc ZYNQ_BASE|rst_ps7_0_100M_peripheral_aresetn 1 0 1 2430 130n +preplace netloc ZYNQ_BASE|zynq_base_hdmi_0_HDMI_CLK_N 1 1 1 2740 140n +preplace netloc ZYNQ_BASE|zynq_base_hdmi_0_HDMI_CLK_P 1 1 1 N 160 +preplace netloc ZYNQ_BASE|zynq_base_hdmi_0_HDMI_DATA_N 1 1 1 2730 140n +preplace netloc ZYNQ_BASE|zynq_base_hdmi_0_HDMI_DATA_P 1 1 1 2750 120n +preplace netloc ZYNQ_BASE|zynq_base_hdmi_0_LED 1 1 1 N 220 +preplace netloc ZYNQ_BASE|zynq_base_hdmi_0_RGB_LED 1 1 1 N 240 +preplace netloc ZYNQ_BASE|zynq_base_hdmi_0_VIDEO_INTERRUPT 1 1 1 2730 200n +preplace netloc ZYNQ_BASE|ps7_0_axi_periph_M00_AXI 1 0 1 N 90 +preplace netloc ZYNQ_BASE|zynq_base_hdmi_0_M_AXI 1 1 1 N 100 +preplace netloc VideoSubsystem|Net 1 0 5 170 1400 420 1250 650 1280 900 1450 1170J +preplace netloc VideoSubsystem|Net1 1 0 5 180 1410 430 1260 630 1270 910 1460 1150J +preplace netloc VideoSubsystem|axi_2d_mmvs_0_VS2MM_INTERRUPT 1 5 1 N 1530 +preplace netloc VideoSubsystem|axis_downsizer_0_M_AXIS 1 1 1 N 1320 +preplace netloc VideoSubsystem|axi_2d_mmvs_0_M_AXIS 1 0 6 180 1240 NJ 1240 NJ 1240 NJ 1240 NJ 1240 1430 +preplace netloc VideoSubsystem|axis_upsizer_0_M_AXIS 1 4 1 1160 1490n +preplace netloc VideoSubsystem|axis_video_filter_0_M_AXIS 1 3 1 890 1370n +preplace netloc VideoSubsystem|axis_linemem_single_0_m_axis 1 2 1 N 1340 +preplace netloc VideoSubsystem|S_AXIL_1 1 0 3 NJ 1440 NJ 1440 640 +preplace netloc VideoSubsystem|S_AXIL1_1 1 0 5 NJ 1470 NJ 1470 NJ 1470 NJ 1470 N +preplace netloc VideoSubsystem|axi_2d_mmvs_0_M_AXI 1 5 1 N 1470 +levelinfo -pg 1 0 210 1840 2490 3570 +levelinfo -hier AXI_Intercon * 1930 * +levelinfo -hier PS * 2490 2800 3200 * +levelinfo -hier ZYNQ_BASE * 2580 * +levelinfo -hier VideoSubsystem * 300 530 770 1030 1300 * +pagesize -pg 1 -db -bbox -sgen -140 0 3750 1650 +pagesize -hier AXI_Intercon -db -bbox -sgen 1750 390 2110 1150 +pagesize -hier PS -db -bbox -sgen 2370 580 3400 1120 +pagesize -hier ZYNQ_BASE -db -bbox -sgen 2370 30 2780 310 +pagesize -hier VideoSubsystem -db -bbox -sgen 140 1230 1460 1630 +" +} + diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_547d6c85.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_547d6c85.ui new file mode 100644 index 0000000..3e8f584 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_547d6c85.ui @@ -0,0 +1,35 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.16629", + "Default View_TopLeft":"-683,-10", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace port M00_AXI -pg 1 -lvl 2 -x 620 -y 110 -defaultsOSRD +preplace port M00_AXI1 -pg 1 -lvl 2 -x 620 -y 330 -defaultsOSRD +preplace port S00_AXI -pg 1 -lvl 0 -x -10 -y 50 -defaultsOSRD +preplace port S00_AXI1 -pg 1 -lvl 0 -x -10 -y 250 -defaultsOSRD +preplace port S00_AXI2 -pg 1 -lvl 0 -x -10 -y 650 -defaultsOSRD +preplace port M00_AXI2 -pg 1 -lvl 2 -x 620 -y 710 -defaultsOSRD +preplace port M01_AXI -pg 1 -lvl 2 -x 620 -y 80 -defaultsOSRD +preplace port M02_AXI -pg 1 -lvl 2 -x 620 -y 140 -defaultsOSRD +preplace port port-id_ACLK -pg 1 -lvl 0 -x -10 -y 280 -defaultsOSRD +preplace port port-id_S00_ARESETN -pg 1 -lvl 0 -x -10 -y 310 -defaultsOSRD +preplace inst axi_mem_intercon -pg 1 -lvl 1 -x 450 -y 370 -defaultsOSRD +preplace inst ps7_0_axi_periph -pg 1 -lvl 1 -x 450 -y 110 -defaultsOSRD +preplace inst axi_interconnect_0 -pg 1 -lvl 1 -x 450 -y 710 -defaultsOSRD +preplace netloc processing_system7_0_FCLK_CLK0 1 0 1 310 30n +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 1 290 50n +preplace netloc axi_mem_intercon_M00_AXI 1 1 1 600J 330n +preplace netloc processing_system7_0_M_AXI_GP0 1 0 1 10J 10n +preplace netloc ps7_0_axi_periph_M00_AXI 1 1 1 600J 90n +preplace netloc zynq_base_hdmi_0_M_AXI 1 0 1 300J 250n +preplace netloc S00_AXI2_1 1 0 1 N 650 +preplace netloc axi_interconnect_0_M00_AXI 1 1 1 N 710 +preplace netloc Conn1 1 1 1 590 80n +preplace netloc Conn2 1 1 1 590 130n +levelinfo -pg 1 -10 450 620 +pagesize -pg 1 -db -bbox -sgen -150 -50 740 1070 +" +} + diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_dfebd9d5.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_dfebd9d5.ui new file mode 100644 index 0000000..581cb6e --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_dfebd9d5.ui @@ -0,0 +1,39 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.4614", + "Default View_TopLeft":"-235,-8", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace port DDR -pg 1 -lvl 4 -x 1040 -y 140 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 4 -x 1040 -y 170 -defaultsOSRD +preplace port M_AXI_GP0 -pg 1 -lvl 4 -x 1040 -y 250 -defaultsOSRD +preplace port S_AXI_HP0 -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD +preplace port S_AXI_ACP -pg 1 -lvl 0 -x 0 -y 230 -defaultsOSRD +preplace port port-id_FCLK_CLK0 -pg 1 -lvl 4 -x 1040 -y 330 -defaultsOSRD +preplace port port-id_FCLK_CLK3 -pg 1 -lvl 4 -x 1040 -y 530 -defaultsOSRD +preplace port port-id_In1 -pg 1 -lvl 0 -x 0 -y 290 -defaultsOSRD +preplace portBus In0 -pg 1 -lvl 0 -x 0 -y 320 -defaultsOSRD +preplace portBus peripheral_aresetn -pg 1 -lvl 4 -x 1040 -y 470 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 2 -x 440 -y 280 -defaultsOSRD +preplace inst rst_ps7_0_100M -pg 1 -lvl 3 -x 840 -y 430 -defaultsOSRD +preplace inst xlconcat_0 -pg 1 -lvl 1 -x 120 -y 320 -defaultsOSRD +preplace inst xlconstant_0 -pg 1 -lvl 2 -x 440 -y 50 -defaultsOSRD +preplace netloc In0_1 1 0 1 30J 310n +preplace netloc processing_system7_0_FCLK_CLK0 1 1 3 220 470 660 320 1020J +preplace netloc processing_system7_0_FCLK_CLK3 1 2 2 670J 330 1010J +preplace netloc processing_system7_0_FCLK_RESET0_N 1 2 1 N 410 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 3 1 NJ 470 +preplace netloc xlconcat_0_dout 1 1 1 210J 320n +preplace netloc xlconstant_0_dout 1 2 1 660 50n +preplace netloc In1_1 1 0 1 20 290n +preplace netloc S_AXI_ACP_1 1 0 2 20J 250 220J +preplace netloc processing_system7_0_DDR 1 2 2 670J 140 NJ +preplace netloc processing_system7_0_FIXED_IO 1 2 2 NJ 170 NJ +preplace netloc processing_system7_0_M_AXI_GP0 1 2 2 NJ 250 NJ +preplace netloc S_AXI_ACP_2 1 0 2 NJ 230 220J +levelinfo -pg 1 0 120 440 840 1040 +pagesize -pg 1 -db -bbox -sgen -120 -10 1240 550 +" +} + diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_f2bb8c86.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_f2bb8c86.ui new file mode 100644 index 0000000..9e62e3e --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_3/ui/bd_f2bb8c86.ui @@ -0,0 +1,34 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.66832", + "Default View_TopLeft":"36,25", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace port S_AXIL -pg 1 -lvl 0 -x -10 -y 170 -defaultsOSRD +preplace port S_AXIL1 -pg 1 -lvl 0 -x -10 -y 290 -defaultsOSRD +preplace port M_AXI -pg 1 -lvl 6 -x 1310 -y 310 -defaultsOSRD +preplace port port-id_ARESETN -pg 1 -lvl 0 -x -10 -y 90 -defaultsOSRD +preplace port port-id_ACLK -pg 1 -lvl 0 -x -10 -y 60 -defaultsOSRD +preplace port port-id_VS2MM_INTERRUPT -pg 1 -lvl 6 -x 1310 -y 350 -defaultsOSRD +preplace inst axis_downsizer_0 -pg 1 -lvl 1 -x 150 -y 70 -defaultsOSRD +preplace inst axis_upsizer_0 -pg 1 -lvl 4 -x 860 -y 200 -defaultsOSRD +preplace inst axis_linemem_single_0 -pg 1 -lvl 2 -x 380 -y 90 -defaultsOSRD +preplace inst axis_video_filter_0 -pg 1 -lvl 3 -x 620 -y 180 -defaultsOSRD +preplace inst axi_2d_mmvs_0 -pg 1 -lvl 5 -x 1140 -y 320 -defaultsOSRD +preplace netloc Net 1 0 5 10 150 270 10 500 80 740 120 1000J +preplace netloc Net1 1 0 5 20 160 280 190 480 270 740 280 980J +preplace netloc axi_2d_mmvs_0_VS2MM_INTERRUPT 1 5 1 N 350 +preplace netloc axis_downsizer_0_M_AXIS 1 1 1 N 70 +preplace netloc axi_2d_mmvs_0_M_AXIS 1 0 6 30 180 NJ 180 490J 90 NJ 90 NJ 90 1270 +preplace netloc axis_upsizer_0_M_AXIS 1 4 1 990 200n +preplace netloc axis_video_filter_0_M_AXIS 1 3 1 N 180 +preplace netloc axis_linemem_single_0_m_axis 1 2 1 480 90n +preplace netloc S_AXIL_1 1 0 3 NJ 170 NJ 170 NJ +preplace netloc S_AXIL1_1 1 0 5 NJ 290 NJ 290 NJ 290 NJ 290 NJ +preplace netloc axi_2d_mmvs_0_M_AXI 1 5 1 1280 290n +levelinfo -pg 1 -10 150 380 620 860 1140 1310 +pagesize -pg 1 -db -bbox -sgen -120 -10 1490 430 +" +} + diff --git a/Milestone6/milestone6/milestone6.xpr b/Milestone6/milestone6/milestone6.xpr index 3601134..ecc1419 100644 --- a/Milestone6/milestone6/milestone6.xpr +++ b/Milestone6/milestone6/milestone6.xpr @@ -92,24 +92,35 @@ - + - + + + + + + + + + + + + + - - + @@ -120,7 +131,7 @@ @@ -195,7 +206,9 @@ - + + Vivado Synthesis Defaults + @@ -204,7 +217,9 @@ - + + Default settings for Implementation. + @@ -213,7 +228,9 @@ - + + +