From 2f46699f59f3f9ec3d29bc1da365d7f972178fc4 Mon Sep 17 00:00:00 2001 From: Sebastian Meyer Date: Tue, 10 Dec 2024 00:49:39 +0100 Subject: [PATCH] Hardware beschrieben und Blockschaltbild aufgebaut. => Filter macht bislang nichts --- .../sources_1/bd/design_1/design_1.bxml | 8 +- Milestone6/Moewe-192x192.bmp | Bin 110646 -> 0 bytes Milestone6/axis_video_filter.vhd | 145 +- .../sources_1/bd/design_1/design_1.bxml | 57 + .../sources_1/bd/design_1/design_1_ooc.xdc | 10 + .../bd/design_1/hdl/design_1_wrapper.v | 93 ++ .../design_1_axil_master_with_rom_0_0.xml | 1102 ++++++++++++ .../sim/design_1_axil_master_with_rom_0_0.vhd | 177 ++ .../design_1_axis_downsizer_0_0.xml | 779 +++++++++ .../sim/design_1_axis_downsizer_0_0.vhd | 136 ++ .../design_1_axis_linemem_single_0_0.xml | 896 ++++++++++ .../sim/design_1_axis_linemem_single_0_0.vhd | 138 ++ .../design_1_axis_master_simmodel_0_0.xml | 738 +++++++++ .../sim/design_1_axis_master_simmodel_0_0.vhd | 152 ++ .../design_1_axis_slave_simmodel_0_0.xml | 642 +++++++ .../sim/design_1_axis_slave_simmodel_0_0.vhd | 136 ++ .../design_1_axis_upsizer_0_0.xml | 795 +++++++++ .../sim/design_1_axis_upsizer_0_0.vhd | 136 ++ .../design_1_axis_video_filter_0_0.xml | 1473 +++++++++++++++++ .../sim/design_1_axis_video_filter_0_0.v | 187 +++ .../design_1_clk_rst_generator_0_0.xml | 226 +++ .../sim/design_1_clk_rst_generator_0_0.vhd | 97 ++ .../sources_1/new/axil_master_with_rom.vhd | 285 ++++ .../ipshared/85f6/sources_1/new/axilm_rom.vhd | 65 + .../9185/sources_1/new/axis_downsizer.vhd | 94 ++ .../9a97/sources_1/new/clk_rst_generator.vhd | 114 ++ .../new/axis_linemem_single_master.vhd | 150 ++ .../ipshared/9ba2/sources_1/new/bmem_dp.vhd | 78 + .../ipshared/c453/axis_slave_simmodel.vhd | 317 ++++ .../bd/design_1/ipshared/c453/bmp_pkg.vhd | 207 +++ .../ipshared/d44d/axis_master_simmodel.vhd | 375 +++++ .../bd/design_1/ipshared/d44d/bmp_pkg.vhd | 208 +++ .../dfd1/sources_1/new/axis_upsizer.vhd | 103 ++ .../sources_1/bd/design_1/sim/design_1.v | 225 +++ .../sources_1/bd/design_1/synth/design_1.v | 225 +++ .../bd/mref/axis_video_filter/component.xml | 870 ++++++++++ .../xgui/axis_video_filter_v1_0.tcl | 25 + .../sources_1/bd/design_1/design_1.bd | 799 +++++++++ .../design_1_axil_master_with_rom_0_0.xci | 172 ++ .../design_1_axis_downsizer_0_0.xci | 148 ++ .../design_1_axis_linemem_single_0_0.xci | 150 ++ .../design_1_axis_master_simmodel_0_0.xci | 148 ++ .../design_1_axis_slave_simmodel_0_0.xci | 135 ++ .../design_1_axis_upsizer_0_0.xci | 148 ++ .../design_1_axis_video_filter_0_0.xci | 232 +++ .../design_1_clk_rst_generator_0_0.xci | 55 + .../sources_1/bd/design_1/ui/bd_1f5defd0.ui | 30 + Milestone6/milestone6/milestone6.xpr | 35 +- Milestone6/{ => milestone6}/stimuli.mem | 0 49 files changed, 13487 insertions(+), 29 deletions(-) delete mode 100644 Milestone6/Moewe-192x192.bmp create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1_ooc.xdc create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/sim/design_1_axil_master_with_rom_0_0.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/sim/design_1_axis_downsizer_0_0.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/sim/design_1_axis_linemem_single_0_0.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/sim/design_1_axis_master_simmodel_0_0.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/sim/design_1_axis_slave_simmodel_0_0.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/sim/design_1_axis_upsizer_0_0.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/sim/design_1_axis_video_filter_0_0.v create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/sim/design_1_clk_rst_generator_0_0.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/85f6/sources_1/new/axil_master_with_rom.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/85f6/sources_1/new/axilm_rom.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9185/sources_1/new/axis_downsizer.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9ba2/sources_1/new/axis_linemem_single_master.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9ba2/sources_1/new/bmem_dp.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/c453/axis_slave_simmodel.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/c453/bmp_pkg.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/d44d/axis_master_simmodel.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/d44d/bmp_pkg.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/dfd1/sources_1/new/axis_upsizer.vhd create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.v create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.v create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/xgui/axis_video_filter_v1_0.tcl create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui rename Milestone6/{ => milestone6}/stimuli.mem (100%) diff --git a/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/design_1.bxml b/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/design_1.bxml index 9577cd7..205f2f1 100644 --- a/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/design_1.bxml +++ b/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/design_1.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/Milestone6/Moewe-192x192.bmp b/Milestone6/Moewe-192x192.bmp deleted file mode 100644 index 9de09ed3fe77db999c1cc9bb68c1c6e570f29753..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 110646 zcmZ_0^;evEwm#b3X`AVpp0)@fKyY^{pl~TlDKE<1-Eb#?gy0a85C}wYcMb8RlTJFV zV@K~fYkk+cf5v^@^qe{0UoQQIMdMWMckjpcr-YTY{{DN!OBVjc;NPQv{CoesGk6Ox z`1n_!z4z|lZ|`{TJzaT%vLH-d9IY(E6)DaSEr|(W=H_TPm7NVOJNr+LAHIC}_`4S` ze|+`&=O2Ii+xKsOef#5IaQ*o6-(J1><=a<3K7aMolV@)Z9=w=eJsg{upPt=ZUfEmU zINaKOuz&dI;NbD`gXf!@JDmJvPEkT@jcsXe=E>t1&tH81{Q2u|U%q+v?A77nqpj`3 zwY9yarR|xywW-?+GqdZf>-%@_F5jM*Sy|lL-Fq-QyE-vG)6;jOtNYrO-kYPNcLxW? zaE)HOJv4fIVEES68`GD1u6J~f^z=_$85r*yp6u?w)qZKTrK7*D@sh{i=JK@E)O0j7 zbh$l^4p)P>rp@1Qp|-ixV)rX`R;#zp>aMqX>UFMat*>6`sngcBPz*M@(Ng89kvnQg zEN*#4iJ&M|m>nX>KF7}u=H-USi=%X9G5X>#V_AfyB3@q-B_oGOa?eS~L9)CcZE?7f z600o^QxybPWe0N7Pw_GX#5qCS%+svYZ`hfq`B`Vgq*HQofUfAgz9>Xq5F{c8iE_^3 zk`;z>GJ-$;;J0V=y)XXw$CF=vi6`yE2Oqrm-uv%fKKST&zxx3H`}rTv$i4TWV+-1n2njiun;F2#JT1r$;A97tCx=$%<>|PbI;(YO_ras5Z=SvQ;pKNfKX~-& z&D%eJ``yo|oVP#x_3e*;{qD^#uiyOo^1ELiKYM+6{Nmo?_QOXZU&14LZ)$Q0M;E`gd>MzIpr0^A~R(K6rL`@bF;o z;rhn@!otS+5^C=I7S#PR%XNuivV8Ow*F#$V^@3Im4> z{RMALtFOAn=Wj7td|bJftI%6&nq2kmMsK~R>7u*slG0Z%GC3=CR<_PkskbtX4yM{v z$>B-Lvn}*AA1lLKndV?6T4}L1dW@46YoSD|i^5d-K?-t^BrixxKBp)+uPzLiBNU8-v8kJ&&mplYwIN5dZDwr%qQ)X6d7+vTe4lh1Go6+gRc%I3v)KRx;O?ZNSj@4o-_F*_E-r7)&95)a zt*tEYOx<3*H90pjG(J8teRX7Ve0=u$*!1YwEJ~=UwYRlnu=C3Gt}A1`LlgZYQ+T_( zf8xUB(e|#vrq(O%7yCLo``X)kYirx<>N=e62EVV_?`!e+nhh3@L}L*c>~g!;=&P^k z=x)5&Yp8Bgx@%-s4_{{$s7*YrRbX@I1PKw&=X7;Jl_FL_-dg<(!d_ zPKq+V;%9tal@p*Ti8fJ_th6{uR`AE~|D*q)em*?$;m03-{OKpZd;fzICr*6y$;Y35 z`n%75`}ij@5qZ@$QhyWQQC(!TmpQ!3DvG%x-dG-|D~`~Wgd58ujiuqn(l8q}+DVVI zP~*^x(D4k#=PhN?#_||LIq}PDQ2d1<+M+OYRBd69xjX`Q1m4z{gxMHL9!|D}maHrY z6_+JSs`yoUo1?MAOiMCS6Acyd25PdtB3VaCU}c0?lF3%7#3~i{wqLye@a3!5zo1l( zAAL8wxQm&!eeiU7>%pDH-QgQ^hYwyo{r2s{r{8TIJQ=^c(lapLKX_~O=1l#Co}sa+ z2ajH0er@kOTwdC+vB^eCoPiRrE{RZ;#AwUoQMWSkd3AA&gGIVvmrh+D*xK27^!&~7 z!*7otJbV1~+pXQ>nfdjZ#f|B?wWZbFjjf~Y?Zd^zjfop~Mu#SPFAa5f4Gay84Gm4) z7@r-RTxh*8*xh#n&8MNYul3^a@aVk@U03nW`sUu|_Wrhx{+8D6%iSXvE)LYxv^6z% z)zq~&HgvYMbl23k+ue0Wn@?l)3XC?6-XgTQ6y9oUW4o@VMdxdfnq5+@O>OlV-SsS` zk*Cn>oV8L%4TUGBQA(9m5}tAVb$UEs^=CUXcE6u|p z*_o-9ia0!3+QJZd?ipd`SC#K7jh=q0DmTzv7Hy}-n#-e1rQ!Uv)Bkt>A&Tb1kBG^I zp@kCq@S{Kc=}%}rL~Huv?{Y0>LvyFt+gN0A7u#KYZXWuEzBEEk4&^+*DSu(S7G^Nq%(pY_245qL!H;|h8O?l#%l^G}H1)-Y4 z^JwY%ip0x)?Z(o*m#;9{etG@&=jSiqtZ&_)UEH3!yF4?uy0Eyhxpla{aj>wsd3$p9 z`pB&tqqpYfH*VdUpS-i!H+TyJbo9n_ci$LV(8!JHfsv`Ui$hLNb8TZ+N9SN;^QESi z%dKra)pcz(HSN{aEnS@hgM;IEr_0x5bk>;MwMwT?WO7K%PMS)e!4q<=E?eUTl#RmZ z^w)LNH+MPxEjo)|s#A1}=|Zl9NP93y|iAYD=Rr-SC*(C@}ywm`a+0 zU~OTruK2vZEYeI%u;D`$F@}-|3^;93sIDYRQ;aK8RTwJIJ15OOTa_Cm&I{qDpZ)AZ zpq>AHLD8J}keFX6AxyFlKKdBF2p|6V55JFOQZ@N5F0DvIPm|^bNOA&s z>0k5Gz7}Mjl4hS(<_1VJPvSk?j8mM9)2#F}l^JIxbE{j$ah2zP^O@zBcloQV_ zEKspoS}sS&;Vw)szj*!g-qG`o-N#Go$E!P!4n}h5?XURn-=4jAv%YySKfk`byt%#s ze7?7|vc0gle*5<9)a2~FdrM+=mP%3=(Z zC{1C+=N}X0@z0l!iI-1NJ|BJj$!{&_gAYH%M^6O@d>I>BA`~n9&1_#|snc6T$wXtR z$_M6i)$@opgq%(qyuLbE}N=T;_ zxC@FS@g-(@s)?G2QD~vY8_Qx1rBN1296*$r600i?R~4Q&QseEc3>!1kLQOGKQ;gIE zaelm@q*zL&I#mjnS~c9=w}1R%dHry0>lk=xefQDA+R^InQ&BmTlbNz*-^@Eq+{fMW2dutE%V__s~@t~DPD@%y7(NGdx zoE$$t53h+f$j)(c$j(Zl;H}IwS7o+OSk$CtU9`)dJv{!~zx>^0&5K z=X>m|Z#g_Vq8{e)ki=&%K4+YZHsJOS`wG zmTpZh4&9oww_F;(vvmCM`Td9A?(H4c$Y@q(x{01)ugr0>vx$kx&#$Q}_6v(#ynMf~ z(8bMmurhtZ0=yHi-P~NSu)r@UaB@iX3QAA4{@%^O-R-T1Prf~V{POVO^W!Hk?mu|C zxpTC-zPq-uyS}*(xnO7S!OGg+#N^!VyGxVzHioa=>*yG$ZMdk^JGC}nO=D+$Q&&@S zcWv#3y1EOsHEkE#`vwMXUg^2!@wZq#b)LF5PS27dATPybmw zCqDS_<4-;X>;ZrO@IxSLVCYXjIPt-IKtS)m_j%Cin5@kFg7TQ${A?~)%ptpIz)=Kj zMonT$>Wjlc;q4VM#-j58SN4inTScs;JjzlLWykMEOVk#ILUvFUg`-~yvjcgUcX`3; zq6lSvuqHo9R~V|w4c6oZtMbod4vI5RR%M?-@dHjPi%_U>s*)&GVT86MoRfZDPG|az zdaGQj74Y>!;nc0!$1i?(`1B2?*zWxoOPj~2mZL|n??3(i^$&jmHNyy7TtAw;w>EZb zaeM;&XnA?#sB36q^yci+>i*Q7watxPJ2%f*k>KQHyLn^}kL;+-ba6;NKH1Gh^GUZ? zW*8_5+OjwcGuYBRT zzQ%^8&eryxrl!jmI{N$jZ;X!KzSuR?*mT+EYm^(EN|W2}Z*tW(YaD*7yTRnDcl%mw z_8OT7DTpU1M4TJM%Q{O<4mkDA z$$!?*2k(FI+3!Ci`pwN0K$aVTxyH{5;FC}xP;4L|gn$47Akh-OD2@NBEb*JNrH;(SktOMa(xY!Ty1GUHM zsP*`o9L~CihR(~EM+OIP4i8UUx-^Wz^^r*OWTFs`sPdi>NcOJ zxw-jrL&HU{r%5PK7E>z)a-G5KRcjp*l|`(v=}m5ntFFGL-R)_T+kGsfgRazblqP}B zD!2L6HZNZ&QdE}ODoLhyG7;*>KuN^i;bLWAtUzYe6o=yturqUcw5BvlRg!Q%Ist9w zw-UnG0{Q{Rgv^H zBl$~C`q%u7)0HVGkFUvbUy$RzDo#Gj%nGW?Jul4(WGDQwBKp&c_&>2yPYOvvLee<_ zDVUKFL`^+il6bl>{#0q=$%?o?(BeMF#ZLK#n;AsU2&QL*Fw)Q2Dl;9GBs?Pu=vT$z z>f+F%=u@RxS*)TWUPXn7PFL}GPK{x6|MC3B@!ZNGD(B$gcZZK&z5M>qFJJ$Hi;#w% zzTVh-bo<`=^6J49%I4e}JP*74HX!P3h9)V=k)cNgR(aRSmA1vwCktB7>ED(4)8 z5drCJ6*)wPwpkbop6IM3VYH!&Ec7HRJ;_AFt(s!RZOh9cfH#L^p<@KZnrKM?NPu>B z7O7fN+Uk^z_IKW#ymRCB+|gz6Q)wayMve?YryrMExl3Zsu+p2y3)~5Q4EiG5<)vZ!@jo9emD2!D)o5JjY zh@^1%@xOeDqLNlh%L?OX2byS!Hb%0cJlaA{a59sf%mf!R(Z|k!pycOexGG5zDd{IZ z|K^`92qlD`^U=qkT?B>y@RLv8Bjo6JFMs?rAv?FMgc_ET9+Q)spBbeqiPn|Hs=@3^ zW922$@`5l)Zm@t9#32Q7Nx>3wmx?KrQd1lY$w*lcBFs5gnSGv- z9bQQaXJ?(4nr zW|x*Ri%M99C1M(@e_(um{o&f~la0M+kDveW1Imnt!Z!4~sFb)_*jW||GX2t~z6Grw#8_$4jOG&?)f!OAjFVkKay z`JqNedaGMKef#Fd*53LKhS%QA!rIi#;u=c-`S*KAPZn3Uhp$cb4&1oZ)n8xTA2Y6*m4Qr zx#Qv>KF#B95{R@(nFZ&flM+Z|DpQCV*I3`#+;rJn+r}{3m@1=CWtN%TDw|JgbfJ(a zB4xQmEigD)GHn@+CSw*@Sec;nPFAXqm*c8TF;zsHX|Wz|R-K3pTpE{={qfoG-wFg{ z3nT2KPhdd(kAran^Xq>A_NO1kXJ!=^Q{qTuQfV2VlGP~8^;D+VX)&J4)EYkCPIobr z@Y+U8)|N!8i^KKhF-}Hu4VUC*rnnf%p2`fsY%4X!#Ypn9v#NRc1xVV`I3YO{N*z>d zcV%WZH@k+LgYTd(iAMhv=7x&0PVzFKES-|&1ge0S3PN(izs!n_Tg+gp z*u0^hkiQxlwx#*>=0I!7mN<3$PZV+#Vb5-pu|+m z%dRxpZ(P56dv0lFdGpDOS8sp%`Qg*2s~bC0_ZDv6njRXt**|cts|)1oQupOSLV+9{ z8yTJK>ABX|cO7Hya`)BNw%+>s&bs=}wzex5x`sjg>l-fC*LO5DU94~D1g(S84p`;) zwVF&`vBJ!)g4Cg;Gx%zizN4ehS>497cq-IpuF5FUS|kRC#Z!-WR?2i_k+M{2C{yT5 zltziOTA(wE`3yZX8|d0aNB>FnqIiV)&9ahOVPR}m&hO(h|2e|m70wBCq2FFUfSmZx z{`1+Vf${N$g_J~6UPfV&fRgFwq&wlQ(BmDIDSm#Aiv#sCy@pS!<>z?VDB5HbB?iKd zofZdo!^=*u=4bi2nO-ibMv&ViEp3%kS|r8Qyc`G0o1Wz7X4Q-Gt9iLj7N{{kne6A~ zRPzh;rO|lgRr#U(^sg!Lzo(~uogVsSVrV#zLXmSgMyb>!6+6}H_L_#B`_Cae&nzE2 ze*X69OQL>o;nqgwJbLm5Z$PQOJ~lfzFmd=yb_51v7)ioEjDw|4f zEMRa7IRY}1T_M#lWIB$~sjzun{w7aTCqreT>1-7mGfAYNXiOYewWPX9=dG{gF=+X* z;4-#~Xj4TTo_CCr$n>le@o69Y;ZMJ{Ak3_H%?Evm7+)Y@zv+i~=f_`t9+8$#p)k{O z^HYn8Wz2jRGXeF`ATFw_%J=iLs|BQ5QLc}dg~{mWqSeH~)PO*3D2sx&?B!&jZ0dyM z1`)YlNUr8(`q=4yPMQ}*$Vf0lJS6B_w6QEoR~lhQgW};E=GBRc^rhhVG0>M(h2fYc zcwHQGIx#eYRZ^-E2v9$IvBaiP+mz}%(<`%UNAqjSgQs~d-RXEqjA4(8_9Z0tN)VFZ;FQj!@`Nsi>?oW~%B zW6R4r!%90-p7>R1{1+vO-xMXDrlke2(g|r4Z&ak7hP=;C{gRdTO(mhU2a57S)TPl@ zMygMc@8aYdDiXA%5vGb*D>E5Nm$E1f$_99)BJZ3$FHoKvV4}v>8!9iiSN8)ck53Mb z-5$DeYhdKYz{t&kk+GqX8&`UVyRQs(b`5l19Jq3M;O5QSqoY%RLp@inUg{dS)Y;e8 zdb#alpV?lmG&$U}h?c3LHwD8=xo% zw$l^5tYjxW5zzueS**U4PZQB_~}(8A`!h4uRf4tBx^zTCV2{O}PpneQGvel@?e zH#5Jru&}eXez>`He{J*d?)1jO>i*oqnv+-P=HxorWD6tHhM~_&L$(3@3mUjIKddST zzzhQ`Mq3(>-U782?2?^!l9z>M6~IY9gEutA(ST~EibQRBEG`&!hKeLbQ50ySrYPJ( zLl=ry5*9!R<{A_UEmW`42s0(xToGfbh_*44+zMJ#ovXWlu;WbNZX)7B^RI5Ngayvl~?e zN5kN)Z@tiav2&1+0y>8q8ZI@|b^5(6B9(=ux3P3qs?t!X(4tP#q0A&_f{tmtje1X` z)!V4^)T0X(sfabs!pGTBQzjB;SX7PUuBU0Il@pm?`rA& z4?p@8{Rfzc=t%Fq_t95h$B?oMOQ^-=^bDZZ;$%lf1bk09`gQ><(O^T#c|$P(L$IbG zP?8fMBn1E@OLGI|WYF*+X>O1lzDW+jXb>`i;fsgV2o1A1SYH@oC<#TGL3T!s)$#y= zvN7*!cqBh3(@0H5^S3dOL&$Kj(yffd5~6;RIOP-xi><4wvZ>WBy}>M3)VZtgE$yyu zKR$TyYVY{vlNUeWLj7#-Jvn-Wa{BT3(YKpB4_4QYK;D6TP(s^#52xogXBYQoXP1qP zEFFRYunyrfQewf@ot0TOR)(ewO*>MOA0{aX#~TEUFNuPMgaVKiLdyz+XDuy?QbSIs zU}nX@YLOR4ND4x$@Xmv%Bwjv1*nvs%VrzN7CptR^I@rvRwNl~bh zK#Y;d!w53JmJ~-gl=Rltx}K{yhR5&rU!Uk19v!-V^Xk|H0gZ-k3=EHVUP4K9wKaEM z?6?Aq)Yfvz?`_hX-3Dj1!s3Ev2$_hlFjVR7YDcw|;Aodx+xnVYue9K5xl*Nba12(V z+9J|e2%Ah}s??ZhG96W>WvNW%3IiDeF^kR68B5TJbe3YRg>JN$D|ER$ajD8!VX&2H ztrUemh0Z^fQ~YU0-g}>Y@mrnz|GoahsZ)u$1tk^C{8CD4VPQ#roQ)EN#-b`jD+>kB z(iQ|6i$XMr7-gMerk{ce1eHmFhqo|XT@ax_l7t+nDF`*fp#Z}zi-BQ5Jd71ktqGYC z;<*KSBeaEzSadBNH4e^~g^qhU2FjtXJX&9dD-ube{K(VUamk!As**1>$>k2M#;Mbr z6-t{*bN$9NDA>{C*RU;Ky!!bSDEymW;mhBD@GT(F-oX=auIbs0wYB|?&7;Moo&7_w zp8d5gl+zaaj{*J~D-(7Jgha%y&@Mp3LDH?v3^P3);vv#&^1?_nJ;lo<`vpZ_eu0CN z1QAXs zi$pCs*|{)iVE5yzw52in@@Q98eyiWq(|e`+`gqUSWY6f>@QsN(GxIxp_b2bnbq`!^ z?;HRY0^jfLzut3Yq^+eJ&R28W6$?BLi&v_#DXl(7O`D^p)#Yz~S3ocwMAj3(g>Ix$Z|N*ZSYXTh|dd>Wd~Gc5%~dCNkl>P znY^U5Dn_N6FEB}EW~I`m)}a3wq_UpQL4v=(_~F^BpMLuFUw{4UzyI{-e>r~o9UN6q z_@f6eR#x}#O|P#kZf|WLudM7J96g<1+*w&WT3g?B@ryBi>=?3abh%_BW>9GqDgml8 zgh43MCVDEA3XCTUBgqU^6RsR9-OkSNfIDyr^i3DT8>LgT`i#z&zEU`!(%sK^Ua=7(sItPmG; z*4u`!UG2U$abf7{!1Wu0*T=35jPwj%?;jrP8N4xc{npUvL~qYk47iJ({VmO1^^F%T zz9y}s&RgBq3d)Z(ny;m~1yFnxB7oXfOHmpm7LU#Q=nPiFDRoYg7>3#G>B?2_Mo zd75DF1R8qp|HjW}BO-&6GJ@ig6G`O6-29Tfcso7TMvH}A3-`pyNP=UoEsl^DM#+kz zRVC4qyz|V=(`Cu03KLJ4CZDAwqbZ#hz^WsI&myB3Qk4xA@iZ(9+>Gx!PpqLlK~)e5 zu|*D$Pa~iXEIb-=aj7RO62G7(eJRQggo#E?3eHPPsbaE-`jN>^GO1ZEMCb=r50ua^fBDzrC$F~mpB_Jbjhx0hVDtLX;nDNe)qSK`5ALIWw%0a} zx3&%}tQ>eHkX7G7+)&g%FY6R=4ze72N)(WrnE)_}@A63KBxz6%P1Fuc>F>AyBU zHg$Jm^4_%@lf$Do`vv=U*HlyA+1q=)uWt-x)7XS?NH=i! zrS1`c!|nu3Ce;hG+M%?Ot=!MYI~a#zd9r zbGYJEZdH*&M?>h*mS-}eoPyFD-|F$F4(wC>td=nLa zHX=4MHS=_QVqSJ4JTG+tO#dK#X(-^Iu^f*)kwr9?MFR<#DT&&WSg0ku-1CxxD0y*= zsx%%DR7g52E(iyfAhH>hBr78mk1ZiH7KT^lhw;hbRfTbiqIe8GZBe+cC`wTjEia4` zW+Rk)3Z*5?4JL)3%1=ob(dharu|=gc$rVPa%qWop2zgCb2s==oUwrq=FMs*BpV5N; z_8;J1Tl-I7ux@NWLc?;r#%t?um~JegbA-Z^-Jc(a0%%E~$eF$z!zL`+&7 zEzS?;B1oJah)a?m0@$M{juI1iJ_0ll#ehEq4HkC_)KPpU{ukt3SC&AGT1qV7lLsCv z7glVhnVtZz`8SCbrX=z+7|MpSXbpN1DS!>Ri4=%i2^mWj@?AwSl7a|zaReS=xHi(l zFlk<>EI&e85U$9FP!Ou1B)SZ|OPwvZ?%caOw|sAAdHmMh!K-841m*9&(ldx&G(38% zxAz**(e=^sd(*3<*X|Av-$FR8>(UU!L#5fHb=DYNNXcHTZ|OFgeKM6<_uKhDg#Xja;2o zXmX+Nu|)c?gq%-){|{>a@t?l@UBLOzzdm&;D*ls@@Tj<8an3n8^3UV|6{1Jw(4sN8 zBT+@*+KQqGJgT^J;hAcS&s)K>I3yPnx*`ESUGR)pX@D6J+^qBz7%S?$Ks;9Z@_1b- zl5f$EFw`(*umCB-2!dG^v zH4|gE3FY~Rzx?H2{`0SY|4&FjTYFEJH;>o0AHiL{I(m0w<7jXH@xsd9+WOJn!Q;7w zoz3ls$H!0nQaZw`ZcZL}cTH7My`&s*AU!ojR1nU|MN5e>Qxgbu#LfXQljebc5zo6U zKa9XO$XgQnVFv6lSYu8$GH)=&(t(srbZF7UT(dD#@W>$Yhbe{$j+Bv|ku1tT&mu<% z@-XO8lgMF4LRv9YASDP4A7iB_qqjpf!vBIhI4aZ3)Hvw*=);_hGq^F0?5t*oY;1IJ zc41|De(n1BU4M0p-RkeSG>Ex2e08Fy_v+>Df$l3qqt_@rH-yaufN4?tI-%-T8md}^JAzP95p&mt-$VM*jy4%4N__hovlc$rmKwPuge)qKi)hR$kaPV!c zRK$t|IcEWcaDU05NKj(o+FKYIU~|%TRdz}Ud>48laf zYhy($K@SbPbrb)G$+1p-yZ}R5K>h{k5SlegzbuiqMe*ND2hhdM9y zU%4{aeYwA@v$wvs)mz;Pr>y(RXvf8YMglB#Ds^@}46@n|tE=8*_iOAvt*1`vsijyQ zbgPr1Gc)xTy2eb`T1!>>Vug;OhVg2X7@b1BUFUAl`WpFGFW=z6g)|#WsAA*d%ei8W zTn-+lGo2Oou>`y4WkqA(J~Q$|?)5g-~0WG(W8)cHXWc~Blm z%exVnXQ$TkNj2Oo;B6Nx*@B!Z9)Wj$s5B=4miN1P0cnL$8m-hMeObJrBF)SMqselz zb8y$gxC9|GR>WZt_=RLjas(+pv5LvmibNKb%C1KLQM>g9r&bRNR&RGddHU*?zy15) z|MkEA`Y->95_<6T4J@Yh?Z?1HhxcEAzAP^9E-dcC3w!qb_43;O+UD_thtFE{0-`4n z%1@@Ang~9H=>zK)fCnrLbRPHz`5$D=0BEhO)EZHtj}L{AK+fMtb_Lp?=f`r^Q)YQ{O>2 zXf2oR9sub&owrV4af=+jcR@!LMP=fe+$^oRM4`oNl#0yi)w=4eHLY52LzTN$WcNz} zr*#f~m4?NUG1(G9l?J&r4&kzSs;pkR!kAV_`|?akP{0>R!aJ$4ZU#^#?#)=hX2R$J zZYhZ}m&e!ufk3xQ!XWPeBS9Lnltmay!VtJcfXz@Gt}Q^|HVn3xla=8iEZrk5_6YxC>pnKWz~6Tdo;-Z` zyiUb7Qj;(#jHqyoDrTyKxZhKBm@KU#9;AgN5kC%fBU!p{?~v1Z?O1-hu=br-aCG=d;i-=?57xGhX6820@DGk2xdernEHeChP|nLSS(4Fetc(nVd;n}bFy=TUD-$p#)ren) z5P6{Fq&Sd@M1O$(!$=1mL;Lao|8TMhQjc8*c1De;=v|00&o3-M@T^*dKqKrP2m*+L zkdSF4s;e?hPr<~8yP8NOlgpw22Jj$gaHCP8?6i0nBi_k?8Wx8k2+;sl2Xhu|MF#1W z66@pT)>akQh>AVP*`n9c5)HUjOT#Vn*jia(ceQ5n+Ti-e&byrd*5utq?4wvq3p7_mAyEk=39teGQC5f*)Cd?H z*m}zd`7%8+mQ!9X=WtDit!TS9VzrOkLZ|l2Hk)KDd9;6!|RJV2?uB;#K>^(+s3;rqe=VfGpHutUEJirp5bUZb93T(7^2nfi%0AQeiiTTAy z)0D>p%>vc}`At^Vv zv^BH1h5g5yle1$Jv&gXBncp0nT7)fvZP~%WG2o(}-WwgA{TDBf^rC()^j9}_D(qgK z$wf8T!MqBqlx0;)Kxl!{QK>P@Y(9gh0a_y0?5xr|AzF%+$PsC|A~j#6k||9JlUt0~ zq}8kO)*I^EbpA%IyB0e~8mnLLsMDD}A_k3<9S+h2y$dJ^I@@o~5tRHYu;5%E;YbyT zEiFSw%|xP)c&xBw0ow~<^@4CsNt6?YBRk896b&`mS`m-P2iB25YE-2WBJz15@)G1= zY-52YCkK6zosfiOT@_yd^Awe%5sFYea;`wZ6=-3H$<;fX2Zv8y&#fNao!`DYzXJ-7 z6e3m&pFV%Hyn+SN9e5f0M^9m4KtDtwZEPO+q*VN9Ekff&t~&-ll$mvwMGCCU36>VZ zeS=mECzOb>A)rVoJisudvqEwZvE74IIfRRfI8Awsq!3SWsJH;Jb3{F1_y*&-##mPr zhP;DD!OFs5BNAB^(NUXFp5q@^S& zO5@b!2>?;p+tmOGl%U4K(5Mli0Y*Yi5?5u01EOvzp#b2g!(6N8k!pEa-pZ6(A*oTv z?rpEVJv9Y%G`FyIZ+7M0?CR~ii+AoV-=-BUQQ4{`z((Xz{&cD@ds^3 zj8$>qWPAyBe)9>uholDo3r8Ji|WVPIPt><*MiVGRM;#>GfPRY3Fr zXU9G!Bvzziz+^EH8zmHUIV4L_EpB!?HWUCI!R`sL#Lq?5!Rt38l2jgTqbK@#Sq1isG4jl;^k%E@=HTVI*}2t?{l(S2>G@SeYSEN#-C4YKck%YjDtgrX($?ng z1LUU0#%GZ`GTR7e-(d609e$z13;nP{X(*~vmPi1ntz4^{Wp?omHi5>8mkJy z+AtT0rxlqQY9i6|xuooffVAisK9#2A^D(^8e^dg@FR8eaBVtyHS!}gX(p*!ww0^X< z_jGc08;NKHkB^^x|KRcKjjac>^IO~7$GiKFb`BoH5nEW?+1h!uvwPnyELD}jtwUfk z98L=4EMgOuOyqxn+@SK&Gfp!y0tBQ0711yejZV~3QnbWMEHQd8WOZfm)3J~e3*!b$ z;-VbHKk(()G)FWDv1)v0WX}TMwY4Atkwu5a6N1GPa8Ee_eIq1~xtMOqX@dy7)6$bcQXGs_1oj%075xpCdt<{J>sxS>-vy#JCTCWbHumphi{!zx z-GfIn3){D6*Rev|*)@!)UL#tvZX_X!TPol@gPeQKjVw)q1_Nt*xhLXyV$$ zQeAz!Nz5@}WBuJS7qOc0&g`%;5?z(4s4G7w74b#n72$Ki7r?wDmXvX85TY5(0`&GI z(6QR8LX?n!o?>AV{yW5$tnh&3h)4mQ0SQRP;VO6n8JDjTR-yB-iYuyET-3e8V8STh zK76sb@c<+2>W%qluYSQU#^mJE^^qxrf6#ok_8%hxJ-@KCvVknweyx;>5;dSIN@J9W z9hS#p;}Yp3M8c3(g~(8qi`Z=tGG++bB6$d6s6y+2d{GQ{o=BLeiji)G1RX0b3>V^) zNr6bistd!kM0<&N2hIUq!WBiah@2^~+K>yR7Yxva3u`I(^U-fX5FoKaX2g%fr(vHO z7|e=g78+795yoO1Re`hv7DdC%WntLEg7*rP^{)A(`*;9UIW>ap8eu*#KhQqxJj^vW z;(ScPo^ump5m8%clE@E4tFcjqGYS|GGm{#WrB^R_m+s!$*xa37*&CZ(zjkM__40_X z>C&}3OEVh}uix9cac6b-`aQ%QFLsa0J@sXJtH@o$vUtRxz)TXjJxuav?^)E`Go;Bbcy8s zSOXG+I1fswE(r(G03E}YF-|X0{I=?X{g;fdB-rOA2ZFW(3nA!^fd%k`pfYqJXbvby zs4K*|7KF_mg~bXa9Ef953IM~xOchBEW}1(iS;NopvJ!0-M7+UKmETcgnwUh)Zhv56 zVR&kBar<~~^LT1*XLM?D?CuiQz$fmkT%VY8cU;jobZF{3^i3CqR!^0yMrifZB|3&w zM^_k-Y-A$Ys5HV8K`#;+9CDl2T+?D{?69<5w!oZq*BbC1XRXcGRD}Sb*6DOLUFf_z ze0_Rx^>A=_3dzaN%OgDl6P=f?R=a$9ZkeJm9O@8QDp(k{ig33gLW8s?_WI#=;k*S0 zHO>QDpOJvp>aHZ=562A)PgYWhhcN{HyN;GXiaZk+62>Sg<4~vqI#WnzN!VNoSHPh% zd6jHt8CA}&GC@%^J6ARzp#RLR9>TnM`_tdSzh)PAa3IF+0ghog1o&BAJD8c@MnDMX zX?TUjM8uSa^eh2c!G(dDAsQen4ub6BkuB(ctW1mspCAwAgjs;68wNetG?5g-#l((S zEbeP0GzdYSmIA(}D2)Z~#WRJ?7pOxbGDZ@*Stu_j1Rx5>0!RwNfCC+j1Q(mYiWXWt zj-h~us4Y(f>Vs2{1$>y!s3Iagm34-n8Gyri=!t)%Cw`8FJ{nHaNIgYOJ6V~2N|b$C zMx?C>MMZ~_E60vQ_&d-A7Z|If*rW>)kbeQr=lr zUVyP8x>3szIt~FD2))J8-pUE%7&8;@!ogAY>?r+dHwyALJLtU$*rdehIw35)qOgco zT*@w|3Ye9=3OZ_rN~uUpOG-&fqL)$xj7pSVnXPa_}WB#8Yn{zG#^4A#SAJl3J4i0rM4^@0wg$j zet@>%tSTSb66|S$Ee2`w&*5|ne%47rHcr3@zzwUQ#5OppMy|BZ&n;|hA1$u#!f3la zy>#miPK1~TWrOL~Jur5;|7QD@Yp%9#Z^soA7OQQZ3cZD8v>}{U%9UUZA50%n5OqVV zx#NW0QkO-(%)JBM%IUBR+RFHYGS7{`ed z&1@VTKRZ1B_U`m%XXl_(k8_R+2_l?NbYmQ+U?4KC3D}57LIWF)irhd`NtlzF1h)}# zE4YKY_&gqeJaHMJClewfDFwxpykcrWQDr%mPh%-XQffs7PJIXs2@|mR;!2)^D;mEx z_2#F)!~eoY{P#cp4O$lvzLPB9Cwn}qQD$thA ztPE{MBKipo8dZ4$WJ7d&1RxDm#CW11Nx_JRQLZS4*O02m)(HiZE749kQ)H+*PK*zB zrXFT!DT10XMsWyI8ayl%8%7~856p{NQ9+%!z{3Ufg+xihbVkKuIHD$@frE%4ABCVD zJTh2d*!9+wCFp2arOB;^RaZ$!Ouz$ns793;=-76sALxqjcC|c}2mq6j0R~UOnM+t3 z$IeK3%E_{{v-B*m#b7xClT;91Vp9e&S{(#|LP$&@LToS*dzwW40p~~nx#4Is?4N4r zX>ESP^yJvy&cWXPqlM+|+xNiK=BK8Y?#wJhmb^AT-8(Ygc(D%$JIHIAgzj3l#lbRI zSxN(rClXnGN`IrdwbRydS<`l@(%&HV)ERtDc3-ov8mrb0z0p@weWByR5TYjCJvX{8 zjrR84yg5EMGy;)xdU|ea`{41>@r%Wk!@F}kcV@Q-M{c_v9zl67KbzRPQsyH#5h2J4 zWu~33O#cQL6DKv@C+Zmqfmko)A~S zT3N6t7om|ee9{?F_9?u9J^PRz`=vt`;Xu>ZSOr^S~(cKId@}X9%o_<4Be^rwn$iX zVPPV`04pmBP<3dRn@)FajzQHZGwUgZ)7&0fm7HKpA|*`B?@~Gz!j)EJQ|n+Ze%Ce;LB-XKK$~Nei!)2R>pKs|CYP@C z;V7_)YhyDI7KTRdG&OWP^p>h}vb+e{a>7@FO<;oI1*aaTuA#e@M&qHzUmE<)@4ord zR~bpE1tf9_xu_(kfKfsba|LN>>8PK8uTRN%Vxvlgn_E zk@ms-8oPOy_@j@W9zJ+Jd3zc7XL9l$zaWm2g8(7U14Ny~g4H6l4+4nwQe^=WVy8Ko zr>aP&a4Ll?pMd>nDcqbOW>z2=7NCNVgf4+obOO;dcv+`KgqIqM!3PimbsEQ4BKV4N zfK&z!KEjN~?Tn6U!fXO)r=}=NVo@!)(-DY53Bhiwm!OH25r=-zlYFdXZ)Fk$HDoY`3O z{}J}yUs0gxzVGho>FJ!?HlZjWA}T5(86@YNbA}>RqH+#YQAN&Kf&s*wQ)?SK+Ic$7 z^vsUutoz&f;ry=VopYPF$EHpX z4KI4UGeaYb(=%t>t_iL@t+ubBrnNFVr8*_7nU*7MKOAdo8YzoHcE#n+OWXg0*IxSL zOTl{sqQfKOk4MEEkIFomUY1{cA|i_ON$YoB0F+-PE0^?3{+GQmigaj$?B8Hymu8u`lTQD%ZecTl)E^PZ}Pi5l@vH} zAI0osm_n&oc>KeHh^MaOU790VQQ|5<}R7owRc0s>#<_TAUee-cQB7sv?bktBDgT;?V zj_L|Fest%1QOQ|lZE}gq>>Xb`b$ava&3o5wKRkcs?&-~&8<*}pc>LK{-~UXVzkT;H zV+))J{fu{D2DiS`J6WUD7Ia9JD(n7Tha!(9wKQ}qqq}KE~$DrZHCy4&r+}OOm zcxrQY;oS7X`KhJz3#YH)8Xg=uH8iwfHhbOf$&t}TyKNZPzd_fh(Kvh6cJJVf!(?qO zO63&_7E}|z6Qz)EAUe3`!#8j>2J8(8J8<~K;p6cqVl$F6in0r%BE|XHwcW3=s;;%J zxwXEfJg2a&wq^Ou^^I$fo__lMqsO1Gp1HDq@$Mxbb9(K@M`S%MF0Eg_`3O^0S<>Oc zh^^R*gt%Sg#|k|pdQ_C~$eeI;2~}A3(WVS!0EdP5A6Fn~ry#|G(U(@lqI?b@=ab8* z4f-z`x8u&T6NL3`g%QSANTn*`K{yHS{%F5^5@lgJP~=jtqP7)*R1;srJr%dTCT3f$ zn2G3icA-M-%oez!&@`ge2ap$WG4NtBggMaU_lPc9uobi}6c)i*05)R5%f!LK;1=47 z`zh;SZ{A@D5uR~45fwxL-={D_nSUHQ0Hz5aL~ni==Lb(QbqVPRR&>!0@g?F?JAjT$ zTND8zlI;|6X zz7yo9f6CK8F*>?HUIA0j(((lwo{fw5HZDJyU7=&Y?H!!AS_gF+hut>f^-K{Isn^(b zDyvFq#y6dLC>%d621l;svz7nX4{FWq|j_SIMZrcHXTpA?qHPH3e?C|=u z(2C^H>QsUI0c3F>H6{laM+%QBR~uCY6@3{TSv=!26e?YGP|mnZfG(gNp2su5@w!p=E`#F^{8yVwQ;vpnJbE z53u(jSDP~Tpt|tL@Bdc@Oq8|1D}%2J;vJ%&2xvXF^Su)XgRS;{@5tQz>ID*#FI>CN z*&q;-5_IL(qs?n~&tJK9>DEW*F5kR{^5M>7K6v*bDYid+_9b@U>-{71xR6M_R%@IL z?^es8+2pZUyaNMxNoK~z7v~o@POV-U8(-%95aM+G&eMsx^`+G-v-9U&t|?dFgu8Ft zV)p2DeF~XT(yrhk?a_^l&JPUD*_3j!vo0g{@@MH$ty3v92^iFygO*W z|Gwh~k7cD~9y%oY=k4!rttzUlEGVrluPn&OEzd9RYLj2N{p|kZ=bwE39Vwb9pKss( z808`J7hEceAnb%^*3RpyGNioB3-DPpY8`J)2j@hfbrgi3;fPZN1Vmp1fWycPuOx`_ zvN#odWdTAjl!1wA5D42iZPhP@4@>9WZIs|KOr1R23<6EOJ*p3^Oey%s$+MF zkvSfiT11SN#E9JN!iX(AN(fLA3UEK@*K%;|Xg^x4>X>bH@jJit;e1#X?+5t9EruKv89*&838zSW1Q>)Lz>lkwN(;r-o)#!7OfIfQ z5fCj9gUk@}Gdt4*Thju%GK1vV`*EX7GJvn~TZzAjT;GPcos`N*{|{mghSb#6>s-Tg ztDDOk*EcTTfpWcZ_wmK+4{v?+$>|HXTw_Z!YcR2ofBfZdkH7eCVdL5oovD^7e*B_m~{E>5Deth=K z*u?7K&;l6a$jH)wXWDKZd za!y`-?RCH1djj|D3*CSCVDMo|(18P?eB6KQuCn}+lDy)o;)>j~oYK7F^1L#V#~wcW z_Q9jiZ;0;hKF+~QSe>6e|K{7DzWw$m=yW?w$bE}oP&V~B?(*`@@aeu+-1^?ec;R@13Xc5j});c z>YfM;_iqw0M_Vew->HlKfbk8}86y=@x;%idt8s$Rh9&O-f@`O0CGG4^+uNNM(47v< z8_<@tyEc~2Z5tC`%KjZG$B(5ZpKQ~Z?PIeGs6H;-TEBez%I!zj?mWKr;Mqq{zr23$ z+4ANsx10Vsd40 zV7A{q)z>%X^-PY9FO5&G3=Pc_;|~sV?!x{4(UtL;v*hTyToYhKO!|{ks{`I?n{_~= zv?-(}S&!aqa%0(+%1yx00_-h7)^b9~gA0!DcwZ#Uy!^_`uf6&DmJheS_ul(k-rW`v z7P)WVem)-L7f_HP#OpPQOZfA#FkpYA?ne!qS8{0+>@0`|G{@u#1C z_2u*LzWD0TODpHw^C0?huOFm?txMR6x`qLSHj;rwP^CE5Q-ZjCYGeHX(@Nq4vm^a8 z2)R1pmwQ5FEYR%;yVgm69_^_DrIF?!z&MV;pgv)@kaooGf`wu9hU^2{BBo5lbfkwh zXC7(GJ>EeqCsx*?=-!feS#f-0<`Im~S>Zd9j_*1d?w1_ymlCln;h10Iv7Jc~yHmq= zWNh7E* zG4R8T=*YB~$X=t(=pC0^-QKCiiKR0OXD)G&F5P;>xuFVOz5n!+=Rf@X^Iw1Y>)-zI zpZ@LFzx?*q^KY*qoq71|=_g-3dh!|mg-4G*dGzroj~;z`@#2kzxwY}JMK=K>b_|cx zgM)LNB|ycM(^saKE{x8uFRxzqdguGy*pX%ihvsMI&v`vF4*RgpGHA07QM)|uNxOAe zuCOvWVi@ODELiD8|LV9MTilH*eoqmt4S)4SRfPrvvxD(ExkZ?2xby0Lll%=$Hy^Y|2a+8n<4loCn1QK7yMaxx;cA3 zVa6VT&!h$M0&h;j;C}$WHVh_>w=ZS{wGUN}Trcb!Cv*VO4D8iu=nYKOsfhEzpXuJ= z)WD+A-&M+YdfN%Cda=%7sgJ&z-+{@iNMd zM>p?1C7|QN=2cT&F6yk`CkvrW77!xlh)D2c?og;wG=T*95|t?{h(^(hmyobujDbu* zBDpR*97iNi2P7JrNp3fB!6gOKZ`2THDkR@v?0z+I+sh+AfHe2HpSIvUt&ZEt^#M5! z@C$$}$;Nm{tWAV8|0sNlvJeBvVFF1sC5XgM5J;jbKB0ymDUGFbHddds)FzoK(fmYP zsuRg{A{Gp(Pj4|=mm{*G%pM{1`}U!WvWeAz7(O4#wCR9kAudzJSDtqXl`{8uv(# zrN69ODK$C?J|ACPNAIz6{^r%YPp*^Pb@ijqzWC326lN?nN zVQb>$|w3e(x$OIL56KTlrwg_X5UWRUC=86KMDsu~;<8w5;7uiZXM zvu)5iOa`~7f08cRWbhdEE|cD6F%L5SkBu$&^-ZBsflQ=0L(LEf!vwVb-Piv8_z=?g zr$4>)@+)t=y=9mG{`WuJ&iQ%gjdx=s6QhpB#YCM9KN`DzXTa<4Yz^GKe{y;apD9wz z1?Iu^>l+ttGDV_-{`l#a)St6wFUm_3d-6rife%913?56<%Yos^0%s<66{`hwhO96W zOh!|hfE){&13!_b9LrcFQ(F^IdEs$uU8bof-B^{1_lNKnVb-QzMQ$sK_^_B8;pjUV zhu+4`ogTg&M>fs^nrCE+BA+B~XB%eTlNg``ht9}W9Jjjy(IcKyAu z=jWgQ^5p(Qes!wi<9hOc@(`IH)K|qjdMc)e9UB)ftZZIgI)7zl9ZG?mN!<mYTB4&3XVGXY8$ z;%M-3PkBcXw_vW>DONm*Kg2t{fK&e;{(VcqRdv}H$K5$}x zNce}_cm2Z)FTV1p*JKhE0pn-RUuR#*m1_@4j=F}5{=qYh7^41Myxx@`)q=tyaZeS2 znF)L9sOl&y(t@RVVW2AvFYr@n_NWOM#3&2e@_2Jynx!t&T$9c$Mytch7_bpuyqYr1 zJ`DK6s?(XrJ3{hJAA;VDaX$ORj&!;j(FSkJIr?tFvG?*$fDZX_#wudAGP9HNQASE0 zCft)j9G;4VfU*SKg}{aYJ46D4$zZ`a1fPQHtR)%4&Mt;B6w$zaP;Bs?SXt?IFg#Ko z5i6=nA~x|zjS4hY5^o3(G(w7mqt;|^p&JA zk-UAlhi5qt3FuK$=DM;$ISz1QbHa8}f8vgX9S;r8Dk*K&i@XJebEr*gYm*yYBlGBo zPo2AV>)~facwqqf`rDuW`CtC+`Pbjyzja?zkpOP#`|J35L@*sr9BEc?7ua}v>43Ly ze(l_;jZ2H?5FK5dUOF?gcn-lordoE>j112?9b;;hqqR}4kQ$USW3SvqA%Y9z?ZChs z_ZJ`}a5UWlQc|JX#TFsLc@Dn+=6_~Zb721c&kHaA;l)>Z|D_jS-t8B%b8FE4pkq6B z?0e~D@xd2g{9{3C?!x>Uf#D;QYwPPbSbeg7{su;{I}bj^pmFC8`muB&-x8u7ST-mm zp*$q9oN5n(2SbgBi&yLK0(E%-fF5{MGy&20K=E)15g;BwlG5|>tI`+;BdP(^)s<4g zNKlW4B4=vj7bPqVW zRosc3YWNF+zYr@Hp&TX>^MD}wK`FB_4l_G|UGI`)25U=C*lH4aXyIY=59x}-jpflM zt~TzSB7U|bl)j8ZwD;jTiSZnvtgOr~qqDeEK^zBEh1xoxcML6@zPxnq+WjYAJRrXm z*yQZu6lgdgaI?Sq*LB)xI<;cb3@qYo{?x;)*=**2!R3@6GHC}Ju z=W%OM>>|>Iz%tcI4|HtovSn{ zswz3WDg7u)QEq4Kb??3L?~!Q#`{?}szZ4>0EqdX_ci-Oi-dldVb{u%+6|vFm_dgMb z!c`Kf)9f0VIfsVi=B6iTYtoQLz>UJbQ9!toI1+^C`w$-F ze6a{5xHVv@Kw1zZ0sPYZ01#1{XcAC|ii0FPeL^6L+_W`S3|y5Abj;MLqA3*|CALK2 zYKKlbhKPt{At(|IhP1v=`5+YvyeEYumWL~f<5XoQy9=UPGY`ONifNk70<6Ws!AeS1 z^1dblaB_|qE8NGohpir9r|zUbhIG(=>>ByoPs7172ruFD7`WvV2?R+Cg5 z5t1AcUXqrQ5gU`AnyfL{iBimJ?QBr!HMT*u)jJ9LckcS_ha$oYweV+OeEZ8Uzde5Z z#jUG1>3;|W<{WlHRi}plEckXA@JgY?MfGxNW>XspY!8!Hp0sEr-qE4K#g(z;vy-Pz zlg~Cjw>&a2x468%yu7ivaBgg5o-@O>)#n@sIO=yz%DS{Vom(a|D0|KFuHNR#nufew zNnyr;J^t(_``_o{zxm&nUVQVV7vFmIm2EHl!=L`+KL_p(l+?8-S|z$()9A?D*)x|( zo(CI8MSt({b27bERcXemB%cqIS{g%P5q8(Y<7m3T>bvv!WePJpXP9QPfvBPkVQd72 zre_u^cQT@pGchldqM68@g3X6@49J*)ph?@n{sU_deL$r;f`}cm9$cLYMn6oCAwsLN zx#I$vl3Fr?sc&2;7*6?-Xq7o~d=f+PCkW12$l9g=mAfnTZ*1%} z6}Cw`G}dmd19$Vl#PZ^qt2gg|`pM_t-?;VhC!c@A6i@QNl?zv~_sX*NsSD`Jj>xjb z-mzM+spLRhfpkR30NT=n_>E~Na zV8eId_CoN(h0>UDu$An3+*@GRc$0w~eYJ@D!q>?h6Mt7(yl`)kz~Hle;X^T3C!0CU zC2S8l&QHY{j!K6lDCGK%@5(0j4S3n-6-wXNn}3)ainG)uqMQy<#7MS;vry)R_GAiCXj2l3 z{og??Aa0Hm`LThm*ke!nCGGnl<-`f@ubhMg65T6HOBLq+I+?bu*M#uCt_MH#@aX*6 zD|a71`s8cy9+rdr@aJC;@0~w;Q6f|Xw3i2AMyRgTYP8MhB*kAR*#7{8F+%Okc!+u- z9q60S32sU`&{Yy=l{fS`48;1)p52^YU7uTBpI=*_TRu0lur@j|KQuUFHn?btR64EJGC6l<^TK7JN6ki1aR>-e_@;%8UCc7PMIMGY znJJ9-F?BM@3SSKNqKcDH7*J6J7idf4kd`4*<){E6F_HO3A+d0Z7dRj`YQv74@K!8} z$OuswiZrT_IxtC*>><*~v2UOXqeCW<6?&a(5i$$a4J`*XiX+M|oa>cd9ignx^S&Q6 zmFtxnLVt)kk!OJyFSIEtXoReAxR9!J%S>23D9yM`A=-#0AQdnrkUI-e6EAR>FK!AM z-C98yG%NHO_anD0XGtUgpyh_jNoEzGzc`$}hKjsOUL8EMIbl0<6A}xOlk$?1iZjwH zaFZZytJ;2$Yq(fDC43#+FimZk+dHQ8`*>S;Y*|J%4YAd*E_p7 zu(URG_QK%O8PC|PduZC?7_iz13w5#a!R{LNj?6e+!yfMhfYQwL^6K*D-1O?y#M1c0 z0zo$;V{;y&lHFq(qpP7!k)By}^jO^X?R#H;?JeSD|Kk+B{l>e|5eYFz6LOPs>MH8$ zE6Mw-uPv)-t7|pLq_CL;#S4>Z+5y@C+I1lTB0!HUS@grn?5JYl6lBCfSsw0403xwP zi?f7UM*g^OMbZ4UWCe4h8Oz9QK^TCG@Gxna6m9-qkWw}}i3XBi4!=^6gxn*t(il^Fai39Y^Yqy! zW^AJ~edDvP(HVz#)ahoQnuoJ7Fhma0)ackeE%)@~^2JNHSb{t=vpP3-8Wrv=vHv4; z{q9jG(SQA;Mw82^cl0WZEzPpBvc~kZg3!=o@4vtGPcOg9ar)yQUi$F8?Z=Kq#wR8f zm6lgmHB=N=w^db=Fb}53J|G%7v{=AR3|!FGpqB`N_-%s$3JfZFuO!(Yi7B?7;^>_q zw45khNWZ@}>5!SA`D9UV(Ldy%s5vGy$)Ldn5kzN5vI+Uw*MP1GnKXuF&H!T9Dlq31 zU}sZRGRf+^&;3Q`qbrZ+Ffb@FGBfTmFY8L94OIz9%WQSYrm6%3HL#MSm8`Ew0I|XU zC9>R0j$5h|tlWT=3Hs7#x@cWRg1Q(PKer)yFN8MGQAbjge3ohea};hk)L=mHukGzh zgXH2W+})naZy=yPIj|-v2=Wo12s#9o9rIkvey@`m!EpiapFDoNBt1PnHZD0jnz)V1 zqGE%4RBapVR9S^FS#9l5Lxaz9hY>q~MUic5SJ{Ph>I~Lw=%Myh;+=68(D@)t;?6>D zw4WPITMSNx!%-lXOo+@ZH2;QDf_cRh0Dh$}74svxg35wp{EBn{4){`A@*Fy;hb^Ep ziz5rGBeToI_>Ydw3=K~aoHaAEOo-OSi?{CFd%Ah?*7W@8v9bB3Qv|l3pP5;i7+aW} zULG8tG3Xpdox^5vyZVMbu3?vBz@&F5W%{PZ&b*w8g!r_eeW4tu*WP^Voh=`RgoYhH z7*UjxCg?4qz2f(v;lajL&KjvC2Autr1s{=aUIQo&fO0etvaKQe@W)l@363F@k@AFp$!KIEO55Dhd5Fm4wR( zJ&&p|jG@U~5yROdjst+vH-pDAgCl9iDo!U)E#l{IP7g&94GWB}qb1P~ri_3BS@uC* z{!E&@hloiRqDtYwP21O#9wcP|;j-q{Dmo$||E4>VriV!An&4azK>^|F<*bu++P!9j(`g?V z8lD-SSR5UkzO;Gs+wXt5b^n>mHSYCH3=hum7#W`B?c4&Q*;Sj_V=}UN)@3pF5sa); znT;BY&Ddup97*42w+(7~O&zVW;{2+#%%Y(EhxY8=lXx&#l8L=Boc6`5Npw| zve+w}?t&j4Qkz1=i2}Mu8_6_;1x%1rDIx_Lf-EoEKQn4?VGQWsUUsjS#V+s7#xE)DjxA!WjQ@v2_cTa!{S1y$&$Z6AQqU z&3wlJ1E{3KsXMuwW>{Su!8A>^$H9Spqqii29o8~@?rD3aXmvy@6|Be)?ae>Pje|mi z8LBrQ5DAT0pbS+;Ce3yr&l)LkzS~XEE`sbx#ZnzeDWE08`_q`hOmqmdCv7ccD@Gw+ z2oTD($$=S%{IcT{(xRidzjBk3>oIcX=P6~%VTPd5C5wB~>77=aJ=USwsg+GuMO?b} zfL)(A?mQV7p4V3;DRM$&Sz>`Qdm?fob`&5};pHY?Wy0@9o`1&C4>H5IW?^t6$@a*W z?Bgg~wpH>t0sDrk(@!KrBHK$4#2h2A&zFQ=MObvv>$c|}aXALB_~MKm16r{PW3~Gb5u56d#Vw_{0+F|C7_FIA#`;ThnVa8Txc$T~VK_Z^+{wwHo_5 zS2mN|3F4%8Xp|t92BK>_zGMBMvu5W)sa?#&Ulls1bZ zc7X3J0NeCHpvI~@jM+(CIv*Y42 zVq!C*V~f&KE3$J7Q`76pD~86GMrKZ1+~aI_l^gn0WaZ7DSzW(@gywI5|JS<@J{=le z?5#+miDG1EI_XyyP3E&ue)4bU{z3?c=!LX)5>D7QUJ<*eI&M!{EHApinpl<(as^<5 z!`+7bo6Q#_28f3wZ65`S76KI$e4UgTN%CjC$O3XBYLwSI$=c9<*C@ljt8c{HFKQHTQ34Ej#yCrTu2HSpqEs3? zWd_cVN@>)n%Bsmv8A;mtM^RMiY5*n5;~Bwd zq(Suo`hcJ{pwPrd6~~}<6Bd5-LNwAM;(+Gou#7vpEEZcjC^1Yrg87cT$R3(!?k0kU zNc+JlkjeDNMK8jTX$;^Rs3Fu1bzzvkEE2R0NRz3Ms*dRre7h+HmGy2eN}<^%{S1nn zqC|_EvYUe;W?mxMeeQ3RZvfQHiPS541|qu|!#jnNFc^h7qzrHDA>FGtFGQUiQh3xaH99IgK0ZA|RHbw6J)V*}tE&o7jP%A{!crB$=Z?&6FmdM=|ne9pSpEO*sGy zFZ`+ql1YHXms&>l1q4SVbdnCT6)=af0z8m(h|(w%=@3GXD)2+(vOrI?yEM0=WMzuP z34Vu&MY}07v_P4MaPg47$Pa+A2u({hFEL(v42(FzeTh=Yz3MR_C;0J1*Ph&6lemkz z!PB7we5;Hnh!R{EpqsgjsYjL-!XZ)fWECD`{^FO9cuBMwAXk8&DRj{R4L*6lP~ely z7K0pUTX8Jrf&k8HbHdK_koS&<>`#d}krEYMnw6Oz8xwUntSBwLu%K{oYGq{l^uXlG z@YJfwGvS#(bMEqkM~^>)h5!DCU+>)dsI!Q`?OhFs*^&hE0NulQ%Xh}r4$HtV&{s)< zk!`Dpsn0(2ds>$O5PXytkqC(5gaRtzKt&=RPh?t*06}~qzg}Vlz#l+R&01TZt$%oE za&lsRbZBa3YH@U6ipd=ysK0+4Cxy#7%-!T9_0iyV*@rkhHfo7u*kK(c&);bs7#W(K zom(07P7I+$@=iIO!$z%*>8!I$RbJUd+%an-I$3|EcPz}GIeYfXhrIc#SAy3)ke z>9BhALX~Zjc4{OI-R-sQ^#!FZg?TMG$+F@UT~!)>=d#3r%xM4Y82^&^y~Xjt)$A-t zLm|ffgS z7hiw-<8QzH)1wDZWyB*3*i&3IXu{cP1CJ> zt;#Oz(&^PUZYYO!z}r9O@l5pD1}7%wC#M$X=T})fODrU}5-l`JHvW^lPjo?6vqz(` zsQI?NMs|rdad_nVy5`P~u3j$3rTMk#vH7XV#W4T@c4ylMEksK8nsrKp&D3vWMZ48Q z`BE#*-JROj21#c_yQHSBsW`tWKdnA9vNb!RyEsu%&T5R<-qL8YRhuEgs3D>j5tqui zB&-v#pBxgHR(@9vEU3yp1hU;Lst~>gR3d_22MD4Q0I^{h5jvS7^4Vx<;8w(-%GuMD zMZxv+RW(9k2)`E079{=_4j5oE?5DBxgt~~RpD+MML7nFV_28^#_}=?mVTmUqH9FhO@gaokY00UP?^4=yod2+LP z?Z6A5SI_nty1BXdoo659t=ltUw)PuMPP3)YX6f_vj}G*Y*)3iJo)Mjkt+E3HQ*P%V z7n92|;&F}H*h*vZ5aKsIxk|X-K>v83WsqaQ0pk?0WLBrLXXjTnw##dpx@+3xwe7vN zEj`t3J*~Y4ozZEx^!M3@?B@P{$ABn4rhco=u9a)GN_`*8Zk)q>(4aOORc4FMp_b}Y zJzA~GqLOJfGCeVEolTOK@~W2O^av3UP4HfYa zrl8_dT5Ews=AF3Hi^Pi z)Y#P|)z-Gli|X5B(sBq3?N#W_dZ*pwwiz5+gt zw8}2Ev|TRmR;!gJdACN}Yvex}H8!2r;dYJVU^3|(dX-Vp-qlfA)>D=vFHHt*M!LfQ z1uH=TQHuwScZ{+Ku?_VEPe+U>LHSe|B2_tK-ghKrNK5f$Y{++6fmfXOYmQ(>2U#tQB!4r*sQ z{pSJ3Y9$B~nvEhtyg@-}yq4=*-+FB2zN=b4BJK+p}ZKmOXyE_5}v+*y;D? zn{VKY@!Ps>&$b;|CzD5~R+i3QpIY3od8ge|E2vmM`}}Jp^q+qEH6m48O98DN_d5t7 z`UKDkKypZ4vZ1isU~HswtED0(5avMa%$}-*fV$-1I#xWS>|?WxFpn^+#=}ti65jCn z65PZtNM8y>T|xjpm#VnE{j*DbW3%?biN1jeyVL8m_m2!s4iApaPM=zwU!9p=nx0%( zUOu<7vaz~)9vjZw%&8&o|-gkx!aTV8!@Ra1vSZ=-w})E1-Kr07z~B)z>-O>d97tF=ceQ7EK3lg?(+Ifda! z>yUS9J6mKbj#IBi=ubFlYKzs>*Y9Hb8?ssYaUp>)IQzzMx~UbW=7!d~vWoh`oW}gr zrtIjhJkrRIQYBFO0VeAZo|Q%c1_G$UkV44z;Pop;t_F)i81+$zep2gsg<=Q=ffPAW zgwzQ>G?XR^kqPt%h%vMpCkk|k0Ut_~2Zsu7oxVuQ$q^OrAeUDU7O*U=USR?R$PJYW z5#S+lPO?S2P6tIp3stIONMPtJEnQ`DL7me9pv}nhg&}UFd!)C zt+(Gn(f7_#K70Pxzx@4kyo3*)sOz%? zT?+)7Ppvp8%?x3z<5&XH5>fNGY6G_~AFZBbHcqQyROvH7)JZ z`kKbF{KCe<97#c{tTaVinL<;fDi9E#l+uCAOhi{9Nc&x=9Kn=_+6OLP!{%amw7kRA zAKG%B1%^19A{Y}|9Y6!1U7%(FXCk9v@X?xrKXWkXZ8#V>+0h?rOTrChd>n=}1Qn3J zn9Y5pkR2jU3UFIfc#Ip9dL=Iq)_dw6`~rL#z!CmI4yQafR9h5Q9O1uf+qMt4Zr$O( z`V_|;e6KYI9y zzOjH3ilDTOlY>V)1B5Mzmjj>>#|ighR|e`ze}qz?7Bu-pN&LIuJcqy&;CHh6Mc9av zwkC=KjIaIg`z+ zGW6AU)52KEA}(+1Zt7Mti^-%qMlSH9z#g$NW+L>H`A3wZ;ze2rWi5?D zjzVfEQa6AmhD1f~0puL0oh4Zmu|udhxVAVjph;j#_`iBG0?~Dl2COX(2a2qU+T*u% z>-$^YfBmhu-rTa~Pp`c4!V53F_WEl_4j$tCoQ#ee8ed#FcZ1n$Zte2z2hW~;`qjVu z>;L@v>py?;^hHI=yV2T69dzyT)f6V^db|m}6kX(dTjZ^*hXVjZ!O<$YiWV~@d7T)h}m-V#Ey4$+zDjFMW+S{9@?QOEU%DU#VqU!XR z%9A3*4{(FVRZ$S8Eg){QKE*Nz=QJ9j5X#rCQVi)XG+ zEp4uB-XOpS@aLcY`Cr*>{OPmjw$|d#^ZMS7}eq=0|wI1 zN9c-#Dw{gVi$%$W?la~q^N$InntuX!I_bxtiz)1$qe7BmcZ|b^S({;jxPad3bYn+_ zT`O_e^mdm+ZL#;-TsrTFWq8UoG|5{leEs;Wd3e$^JZ12VnH?Udd(dk4*laF?!J$@} zl?uI-=crR&SJ~KHCsEL`cqR<4k#?n}S*jyGf&}$;saB&lYeYZH!Bc6JX0_bZBT*@P z01B+KPL;fihq_m$2URc|`nb`^tI=z1oDfB~wpXSzXsx_eD-1@hRjV+7K=wI?EG8E| zIGfeWxs{N3%xUb_RM)iT<(C&0mKWrgm*thW6W~_gUYu20TT*bo+4s$!`gJ-L{V4$@Z9Zn1|QN`k`!f&_61>cU^aoy8Oe3Bo79hM)rk z+7-gZ{4g0EbuN;X!=(`cdw2P5_uKW_n{U1N(!Z-cSy;&}w(Wy05r@J`OUlq6E}gl) zym9mDtw-N}|1;*VZ@&5d%P+ojN-8-#;0A&X0c0SniY>b0?+rnYNNdd*Ch-Yile)x7 z5YiFEGX$;E0_BFWokyL2lo1S&0VoyKE7O)d=Liw3pze^))NM65TPbOBKohu@#MUQp zGgI|RV{MwcE?d@AESJ>DWF4r$80Gb@5tVDS%ji<@lJ`!SIYs@Hqj9Tiz~LJ54o(bs zhFngMMrUc0^pf=H92~dUz4pFgv_?9!TdBAA$PEUa9j?}-v-e8HF^~gG%M6Mx4TF`u zOQ(_<$EQ{=T)5Ha8qw?foQ@GYW1wvi^DK47&MqzIkj32Rwh!@fqt?N(!LC(=V{v9tPGWX*bu&tpskyb&tLJS7 zyVdAm*t8kl+^RrftafX!sc$aGZOBTfPd`R3A}VNTUw}cT6^uVVs7)}lWL4ofgE0sC zgS6%M3~T1=nT6z!tB_wZCxlCi7rP=al$u5g2i*ws9YR@Lw34(yzN8*x#+L=ejtTT# zNOY)0f+oufDL&!9<=uB*ef`Z>-g^7x*WaLjMs3Ag&d(md-TSuhjz1nbJaLNb*46X3 zS?%}bSKt5i^KYD==U;v6=&Gb)=C*A=xxYD)W}dl#;XS0AOO{q2UNtR9lw8uQ*wK@Q z_{|^RE@}aQK{`E@w1`@n)OgV9;9r24YfReRA#zHIEfU`cIEdOy)*rK{(1DjkfyE)r zLr;#2jY+mUi;fW~+WuxXC6%Al%9>0Toqb@yJvlRg_GA9^(8}iM;#syB&n=%BpIez- zIz6+nytI5~?F=GD(Jw76tj^CYjtx%@4@_7s{q(>#qXT>Z*x8^l$+}e3ADC91+QMirI`|>lIhTj0CW!xObvJ@+>T-3DKK!36TmniBuM7$%reL%Dkg+U zs$Po%G*WBt?C9;3C~2!YTe)FXEhO9))nuQ{OOMSc$u6lE#M{sog88N8 zD8MPk_MZ?GBRIKQ(}RGfIXUVg;v=X_VaO5Dl__&WJ5rGb1#riKXM#bYJP`tEkZL4D zDFFz9sv`a0e(lviy!59RUwP$EufK+uQyiW@zVycHZ|&ahw`a>v|1I0)a{ZYL_s)@% zeE;be&%giqm%o3_`FZ}WM^=vpgXW4O!HzR-F0LwWE>4A<^bd-LKnz0J<-vggD(B4j za6+^z$6+++_H`wZoGuO*ufEIkS1? z^tlU{uiQ9$_QF|gAPYRdi&InclM^$eL*paE69%10h^~zequ#3LS+lszq6j!0mVpbK zH~!cE`oHhoy06t(%tp7xNMMlwlxWdMhh}D`mKWw$XQvitrcSy02CZh-@bJvy;_2y$ z#o?i8H+$IKqfm9D!!w@#vCa;8OMQnzrd7*zI+aDMG^%CVo{rwC;+nkl0)<@5)P_ia z%aN8$A=Sz{6?EW|4tXy?6JWT(-e(^e8=K}k_ek~i)os)zX=`^|WsRh~L{gmIQ=FhJ zOVEQ+mqiNA58kfQ6TC&&hue#12MP~PmL^8V6)t7AlM=UIsXW1rAh(;lJ>Lh8ekSn z3*t}MMgXPe1XBLsUfDw$2*JdEHGt(-CQ_Y19TDw-$7&dO^H}x--4-J3=R(91)Xo8G z%2TYEq&Rv*a+hEVy{PI~g^x16vN`+R|qmuWiIwbPWE~P{w zt#9n`_K$!0>GQ9?{QCK4pAWc(%p51zu*KrGnER~;m)AW!F*Y+ZxpZoNbp@x}B>uIb zq2am7xzjVV%cCPiA&pwhE}O;0JD@{mlarX5vcj6OvYM*Wx}J8qN~%@KwNA6Ut**VL zww-~lsjj1|UD4Iv)7sF{+0w1-QAs&J?egv}Rad)A$%0a&gP)cXB$FGYa($o8qfrOxMwnAN3*jt{;)GxYdh_C_{69=gZk60>WjO8a3`LK-#dkc>kN>3PI z`OD}KV(>L{z<6?DE{M42&f=O=;k+n0ZYmS1Kk+C8ojz6c9g6c;PR8{OQ;4zWej@FTWe?ZJ~1$h9i1opZJ-aMhc^F z?$Cqb+@S#$8j=vEa?S}4fCVgUd;-mw4<$Pcx5zL^@j->viK-JLTNW6R2w2v!F0E9= z4`L#wr0@;7g{zVR*L zbY;lWN`-uD7d<4&oRWg*-ufJUXO&eabvezG(-Ujw&#zp(wsi5v=-T=IndQEbX~-t2XDLk;7&ia5{;}8fCxsfOkTxvG#On=%pK*yNdEF^Rr9a>f74t+RPe@RcCXG zW9d?<%m9xXg^|JnlF-@Q1%Sz<*3~AHNtE5KQjQQrF!+)c2H8pajlEZCaM(StglI1T z>dnT!mWp~=ONY8ks%UM~w72%wmr08f*-pift}hb7P*fE#Lk2e>M15H_1ijFTl+Y9b zIPatX;UUis))t2K797U@%*UC(@GxqjISRw7qjtaf@_(A7#G&z>q8Gq{{_xTtU;N{? z54Ob|kCZBO8#g}w?91<;e){FN-~af-pNY-+aZn?nwg^aExCn8H?rX`wn}Ce}s8Clj zg$Z;E#@UB(=0J%OUJ9YS4+{w>1a}rUHJB$*IgLGcD-#6E-@DU;#JV(ka_o4bi0zl4 zh7wv$s6#T|#YP@sPvDs0$;vu_e3YVuzKhd>Qxziv9vLAc6bTiO_!t@ZWFj&SQp$(| zh9H1&K`_HkCE+k7VP0&AJJDSluWrgW${U?lm1}I+J-;}(e0KHHjkPN`C)YOmXO{<; z*GJYiXE&}-Y~JjfTh-VHl%_tF&Tg^*M?1iRZ1#b{p($jv4<3B-<1fG6xOsnQWLn6! zCzfzLZC<`JG%_PouIs2SMfMNS(Am>2^<8bGtk;HJnCSyFf|#4|#7ia;?f z2#J~`b+4GU(}hWd0AV-|MfSe(h@CI_4vaWCzCSO%_{ZO;_!s}cxq9K%mtPCq9Z*nM zx_aa8ZUPz(c@HDeMWI3=l-V$bIFg zFnRfAf!*kZ(36W$ri>7TA7~WOE;0*%l5yXGm=QaVbjn8%A4X9FOay!ZDhoG6`Nhpg zIt14fEkva&fI;pc=g`g z#?`rvD;I7(An|zh^!mi~!pQi-@aXKy$~lo#^86dpVNNZq4GvCB&#e&@{M`>fvt`@m z8g)7cZH~dE)lFiPN2eBzHjh$kY4=60^{Px#iIP!^3Z_wWamVwJj~REd~u-?=bxjB(lZq1udsvlJ%%LjV&$G_Kx1d%)Hd7g!1gX*2-$D z)-*G{0w7NVHZ`#bQ8?t8a9aA!8l$qUt-UO#H1Tjz3_@Ig{_U_N#qoQ};&IRiv?5U^ zR)_>M^1DPP5<++6k%A&`IO$h#Z2O=7Ag-FntE!rBHVy3e0{@&%e(joPX+ z^3!M&4^wsVset0gq<{%cNFkGno3Ezyf_k7HhxR;-X>Jt1N03j5?Zs#+~yVw>r5jZbQjJ?NLXNPUb7&;K#usG zQAbxs?fL&cKb)%<{_w}Wd-qxUyg&W=kKcaxGG>*fXytSIRy*1*k04R`rpjyQ2Lojk( zJhIHa_2f(@i>e~nVdhY3MS2i$G!0T~GUwU4qMi&BR80eJ&Qk%ur<5vvHn%|lSwhd47eakNr_boJCU_R+J& zi5i8fnQy|@0NOJ_e6wnSRJw{}X>Crgw8>=FIr>@MFgv<(jwb5V=Jm_B9uSFq|D(sZ z?mQr>oeiW{Z`^(G=;_sKw=t4H_-yMv^bY*1oI26k8%Me$>p&~_)x|9-J9v@JaxUY_EH|F>BgEU3lzZ{ja=&iUIcn~s4 z+%ft$>{_MK+e!AWh~CaQB$2X|T&xrC3$ugB1N1MB+D6zQ5jqHK`Nv|##koLb6PO0V zTCRSYe9UXq&usA)<{GRXttPRkyfiq6^x>kRqPOS#h~g%~aG)lA`OKU>G|7>)Ti{x3 z9>=w(u1YeumpW8!Zil|l%`q4lUR)by>+$-PvzKpOyng56>L6(q|bSOHSrA>A1`6ts-BNL)Rk0l+8sxPS=9GDs(U%-7ZKX)3f zIQ%im>XTE;)6*+sWAMv}IY;QdO$HkUun)(9cf#o$>T?cz`zHz8(a81kHc59~RYP8K zLppB9LxkI4h^vV7ds#q+|Nnmi_6E-{o+ilmZ~yo&KmGKVAAb0C!EFF@hN$AUVwwYh zV#LFn@4JccAJN{2LHBoN@nC@$7hEXq4O9iqPZv7v^k8aE4~lUS*~I72tAry@qWS4T z_KBMkW)NusiZUN^#Z*-iFN|!2txq058}a(4|&zG7LqwHIvwwqH`aaUWohrDNn3!C56=ot1xe3G6N1 z%k3|8acnhB5DQb_d42L5C}T335NV@UA_6)T`CqpPVnQ-XR10XouS3HDU76I`T&mK^ zEd%|I=~)-o$I982&Ffe1K4ORF{rit@-@NzHgGWyuKYjZ2lc!HUxq0*cX)e3f^&u+5 z-VRb(FU}z#Adys!JQP;*%2& zhescdNQ{Wfh)!rItFv1?TvZ_9T!JROok<^rff5AfIl@H-JmncPncRAVQ>_8vGzj3! z1TN~KSdEO}C`bA`iLcz@7*Wa$U2Q$xEp2TT#f1qcUjJ|M2mYJm^x=m)dS%K>7cbNN zeE}Jv)H7uv*dr+u%*I4}c0{USk;S%EHfuw`d=i4)Z%ndN?WYzcBdl)Zpu9 z87O8DVgUJ^wxob2p}A$D-aZuFU1|H<_+-isqB8O22Y8MUVR8u3uFy*pg#n;StIR$K zk;;_xXx*aG0 z;3hI>h|$2k3wYarFCdF$wfjqHBgLj9a_O-b`IG4+9_;Y)UAtu@gvaedFkFtuO}IsX z6a)f~QU(10I2E#9#!{|t`g|PaZ5Z^>(l_R+x*Nhh&G}2W)^FUqbnVXO z#p|1wuiqfT{rcUNwT-2fbAwZh1CyubNV&cD@xsbki*VzPc?ZV_2ggx^d;5l%*2jit zXQx+Imd|gTzlK1rBt0iGV1I1z!Mu~H4MpW$HT57u00`)j`s_%XtW5n3`&OfiyAL1> z)Sdqe?V{>6C=^<$TqEi3ZRwOXwRN_40&ZH|eM3`Ir+__&2d9S#ZgLJgZ9{_tP&P!y zxx2fyMJ4r-QOP^}0$zEQXx#t4oqp%-ck3%^T_*GSwY6uDKLJ0S@z`iE7|#K>pz*bmoaggkS}=sRxP^_f;eXbJgO^Le-3A4C4SNvo?)fZc?Ot-Fp$B z9NXyF)FU>FaXu-<5PAHKvhu{vmQtCtiNrqR@SuHSnk@XQY>s~N`B&fk@bz~;KKb;k zYquX=x%Ckn0hU%a-0mrtYsP9ARCas1TU`dV13McMBSx^9$;J7JIj_kgt*I`Ii!Dh! z*9)Hd%D*UTR{`ESwmnAe%8T;P zj@XqMzOy3>;sY?5MHq*mX=tZGBe^>S4(U^XpmKrQ_}$sfjL*==v7tT2Z^hIG-j1YP zNIjYQi&z1GBRGO)20ap;8)pf$9IXrAT%hP8@Q2>Um$o57gCh`S87suRCe);C81bpO zNTm>`u{=>(6iwm^NeF73Uj^{LB)|g*z-S9GJa#P-6@1~SfDdALlohdY0HbJ(sV2o# zlZ<8+M~_a(R-?7$G5VSmT|<_xr9j_NscEaS_jYNeGFg{Gt<>>uYpp(k)Rt&>Vwf&s zk8RhRp4gD)hLYmO!s4dfyoSv5=Io5x6JaZgIepF96G~*-8ty!(>9fhPJjy{Z9mVikXz8AV}(mW@*RMTr-uFk+BXp= zK18Q*b@4gki4(4kee9+|%gQ3-#^eL#@j=CL7%&;5*lZ5}wWlV2Pib60e#~B$Tfqh6 zAK_)oMTXu9I1$ac4@hJe%zlxolpN4T*OZSXDx{8Ukpv{soQS+8jt5#bP$MorFnr(s znwZwCL-i@dat3pw{pa3Zz$>tb9N&n_{K(g`l8L68l~}ww&|>kI<{V(n7XOzx7nI2y zB)};67f{fqls)wTN9iFXY0z)ehm*;n(7?6j6 zHH?$5BG59IEu|n=Z0`kGMMoE27I&~LK0GHf;=tY`FZ{!sIdR!mg{HSzl@x9d-!1Ph zFX<@CZOTmN*t8esw&iE{lod&e^GzMiZgsEQXuWge&eaQ7*H+G+U%xapzQD2hz4sm( z#3DyOGfDqL5yRq*p%Rf~XPd0GMOstQlABkZnOm8jR$PbHMWIJ|0><9&fVCXRSyKG+05{h(-d7!&XTU^puSXfhA)!bOq z+|eYFvZOnmXI$urcyb|0`Hf-QA*dOt2^bC{c`?ZFxOn#ky*GNA7zM8Z%W&+|pX5}8X}RopMUPdS2d z!%L+pPf!w%BYdEd*jswVK4JowNRK=rFBGN5*YqBd(AJW*;#&`gcLt0I{18r-r;JMt z#2aA@!g4?}@j?&=@O>Brd>t})R~Q8fQ!`gKR2|JT-&53HQQz2NNotwcdQVIurweeN zRfetEv}z&TfMnbOzJWjB>jWi(Iz$0Q-J|-6tQg-zkjMql#3Zpq8Oo!HuQb=3bkwIp z4R3wJKQZj+oLh5Yb#mA`SDZ3*{n`z-2VK2#^Y-=I_io+2f9uYzt2fqG&P2qdOYc3BL<-s)TMAPBRVuy8O91>2Gk07bByo_7Dj+|AaRGp zVG8iE%n1DUbpUYyzl)V~#~}nc>cp_n6>uj)kpoykGInHz1iim6B{WEq$v)OS4RNV# zlN;5wOgl8wgRZm7Y&p7k{rc@kA3gr~|6%MtpzOM@^U(Vx&nYW$o|YX;B1IA;I*8uO z3}()<=3b@Xh?4=`ngysBZDa)((dkhGiuDL&7K09k}4*0B}g()q%B(PbGUNCp-S43 ziKCLXYCPs@T9^G#{V+eM%bNwzEvw+okiE)@XgO(G=7K|k#(Fhu`oy;`Ondu=+4UjS z2zD_QDl;wTG$2UGjOS~o8rFo*BQ`|HaCKz>TI08s^zU3gysxrv=W>+ESPb0WG>@ii za+*pvPOQLBr#JEC~J&s}2lb&|YE%Skm3v0;uQ~A5ucI7jIyEhXoWjf~T_*03b zb<~lWmjZa3XM3Jkl(KIGp7-nnX8-PXke$7*gl+5N!nH$VBx|wW)QWcW|(8sJo-*%*h*+(s6K?^gx}v?VM79GdH((40rXO)ZcyRy86S{ z*DK3ZzAMqDYOb?mu(@ba(dpI>QFU#N&E3b4sG}%acX!wEGbb-7FX6KY-4vvOfg8>c z8_ZHD0ynNxCdFjlyY7Aj3BU35ZLJO6!^dyBc*_IeWFwxTq4TXx-ADExI<%u|_u8`B zW#)@cBqrC{Eyz920olk*A0_sviOg`MbxNjZrnhmG=hK=~S2jhb>S1-ct0y+ESJdiu zGlu~?9g&q#bfYJ(!kN`8;$7GU?*J+soH{ghziwM)mXgcbV*wH|%$zfA&j-MPnapByB zM;?3fhBG&v#GF$Wa-zFy$hZmF`=f^&8yY)g`8zv@6sUCd99L)9-E&g+it6s`u4~x8 z|FG(~md2hA+^O$W(HbmdyV<-88+)C;;nrJjz4zwxcPgc$YW8;w)$OlSU|@K~MV#u^ zd+)sKk$dld-0pt2-U3?ow$R&h${5}wyLMf_W$nQ=i>}KEMAh;t!RY_U^XP+Mphh>F z5a||~psikXX0h}^E5J}%mcmP$P@-IEj9N=+gwm0U?@wl@up+HZL@ zxfPt51`RHU+`4>f2S_ZCH+n`5D9ec$@jY~};vQ2aOHBOM~A<)tvIwGKTeXW0K0LSK$vQr`3g0WH|A^EZUWp=et|Aa}JywKF3Vma?1lZp1T`sI=t`jt}Rv7l`FQFPp@4v$!G;(m#k$?*%%Z1 zMe#M|g$yncHiKNCS^z#p3W%8;Jw3sspnZWQAzBB`ltNrhIDc^YHL8_VVA47YwyzZ2 zj@ugaW)rD|mM(y;gJGrM*_K6F%O)C^0g}eEplxHOUjDo9`RBhw+?L2&J$2&m{I>d> z6wFWtoSgV3W)bA7<>TOxPl7;i)m-(fO25=oNop&APcx2q8G&Clw&o^ zEiLVRo&6_UI{S|`cO7f$s3RG5AMfZMZf@>AwC`x$b&dK{y3I3b>DL0#+SpCTlnCCx z`w(35Sz4boX&yb$sDZQT7><70e}_kK_o@8t0L zjkXXjt1f4{NqK@PWP=w_>qx<)^WY?S1qw>ybBtDwq<1NPTNY(94>pUba!-0Zx0&XR zZ_lnOJ_-xBtfT zx8APH;J!!hx$luj9{J!0pM3W2dmcP@_U6HX6N5u1`i)KMBx?_LwRF}WZKylie5|Fr zt@n6+Ti@X$O$YWLX*k-_Z9Esr$nZCVDNgW)=M6JyI;Lc|x8X=z{o$5l*EL+f`^ff< zJC9yhe`0`YB=$cJS`A0rv{SV;_tziO0^CIj*Z!%N_%5R_FWhYup^&ggJ9+OZyT;qg z>FkY{hD1jN$_h?mR!{)Na3~NozHb366Wxns(>`jvavM06G(dJ)lD8s@-lyD}T z!~p+nfh67`$YcPiw1qeeTF61_r3Y%4_3d0bxMwwf3mB{i)ER<0Si4-j-)l!v<9FDl z^>Y-P6)_Qp6HcypTPzPY?3LTrkg=k~ak90RHTJ-5x_2xV7f60((9^0YtNM@Co>whlyue|Jbvclh5Men^!V#{Jn`10 z$KN=A|A#I-@Y3y%z5d{HZ{PdWTlYQn=G~9KcE_VHow?yc(}C)Gp+s53R~%kG>geh*$XoaR z%2UmIFAO$cxbfu48_r$0^^V)_e&E(icb`9h@xo0v-*U^P3m0y=^_Dwsxka>o`)xOy zzck#@ZX{q+W4(fZ`{NurdVT%D-Pc{e?~uaZu2wzdCkLhE`c9o1K6iTfJPXrssQKuD zdRC~reQ3DvjD*N=@0s?7ZVd&xKAY+~wc4>l#||~OH1+CUxp3}|v!^beK1l?)A=~WU zbeAz2mk{!s?mB-~bwTuj<3l%@kA$bw`VlJ@VeISb;p+{GRH?LZObTadV5>TtyppAG43005fwtdYzwJ@gk_~9 zdT?3V{3^d+g;0UU>VFm*4r|s~>;z z^^ZUK+Q*-I?GsPG{>dj^`@~}(dgtM1-|~3$**70~`i+O5c~iC8-S<4A>Y``=R>4TI zW5vS09j2|?YiSnn^wLyS3v2$(A2p{@gXcP(JDE8z#B1G5 z*Ola3Ik9uw+}`~ahAsEh)$}zV9PDU3X&0PZZoA`7#YGQ2{?xNiJoWtj4?c4K!lmKk zH}>@mHZ?Xk)-|=XbRp{JZ@T5|`J0CaPU?#4>F8^3>gd9w8roDbHR$Fv2+pw94yNZO zs`WtUKzl<+hd{5sv$?L-*puV^XL{O(nvQkas>ues2J)Eh)!x+G-rSEDox3rU!Oq`! z=|uk-!Z}8O9&RK`0&V@YsJ6T*JLeX8nbVxj!37!W|?%7 z5nftROboCn+A#tiEhlSv88!JcCFMymekE=qGqO2d+m~Wc*lY}u;yV3hx-13GTQjK% zP(}CtsjkfH0aB)OE5V%-x|@-PC8)BG;3GK7!oHcwTqfA>t}gRg^1m`E2(zq*N&r=n zDloxDD$OjZLxy{+u}oSmdn9G>Ma6{r+BE|=T)6p>7w>)cjVE4x=f$@_`RYeM{rbm0 z^ZLg=^V&y0`|3NNe(CK$c;T&2K4&BBS3mN?Yae;}&5ynO`a7m`Kl$t{Pd)qU6VJc? z@Z-<3=2|Q|R`nqVtu=_I|YErbGdf#3)1Qx9*Oi73EGU33YTv{u*WwNTfw z5o0tEOd+f0FO{N7YqWrk@zA<;Oip3@g3jG5x({wV(OrM*g>(1Z_t3*nK6}r@Ph7hD zfpZt{Jag{SEw|ry&wY>DrNZU{H{C2SKY!x5rpr?UJ<3Qr`nm>A4WBuC^6Z)6GbaX4 zo*^cI(9n%N?E|gH+SDC&>HemBYbxoGFE+yKq-i|89Ycrq*6rVU=+OQK+rFPZVG^B0 ziTPlsIJ-_0r`aXp=Eg2-DI&_F|;t>qvpPrm%sKmXQW zeCMyf|JUFBo3~zjz2$lZWOe7y-*(UAAG&z|Qv*XMy0N1c14NGWb+nizag#f|zxnPP z`|dh7(6CA86egy-IgRHnHoRCXeLz1kU6TefQIj%4MF1h82xQzfs*z=06z8B%kw=jB zwc`zRZIX^zHRf35gx2kgFZLb2kTw&y+k3Dzx#CbA;L8<4?-r3U7dth(<-Wnv_&fjM{TL$#vnJ?E;-)&4m{oyuJ zxlIZCs%>1dkSn+D$yQgDa4SQ*R}9EsZ;=F#1(41j+`Y{oWOYVra6*3fKUn$T}^Ho?iHeZG%+ z%&cu+G_-5^(B2By&|hoIp7I{~slBTQcH46h5=#2*DOp?ITWe>@Y2p2?4bGZIy_xQF&{X3V&tJdv3bH{!6Jn_PlFTM5BM?Ue^CqMnk&wc)n zReOHv%U}4@FaOzBzy9?<|BJu+>+k;XKmXlNfBIkl;pe~j*+2aJr$77IkAL!$Z++t% zuRr(9+5UkeJNMM>R%gGzwZ3Ioe*BI{Z++;6ho1fL^B?~7r#}Cc@BHxZfAQ=8HuB$R zKk|whcb%JN^=!>{PUIs$O=gHw6Vmz#6u zIo+u1Et@Thp#5pnw5;~ffwM0jnvr3W_Nf`#y^;m+iiPW|S!_YOsx9BL;k_$+cP;I! z4UI&kB~r>qEPi4eYW%#p3?z@@RVaCpVXbyYZNd-3z8d@oQ9N!Pj8z zGUtc1!QIPx4sJVj^QAi;ed?)~-gx^{fB3mC{K;3p@#o+Dn;-t?zyHw>{?p%n?*~8p zzW@FGj{xSEzxvg?ASnL#t6%-nPKv`_eM22Rr+NoY_V%ArMXl_0Sl9jOyKleC8h!4w zpZ$-2`IqqadU%I0d6N zpnz&5aw&+@+}^Eo?6uUg0YjVKvC#%SdYrS%K<~CWecR{tZ3Dkhg#?vq2~5wxI=0MC zNVkAL(NZ@&7bw2PeDy?5S!*R6NmeD2m8Rq!4^f9s_O?!W)( zi|6msN}vMWxVh8A7}Qx0eVzSXC#@!J-@KY)p_RCckx>`-Z(es_sF+p!pzF4E%k13# zJ7ud^@d$tvGqrPBB;rkT#Q0!l(HQ~jE587EY?oa)4bjES5iJrQl5>dsqA=d16p8+D z>5^7l$hK=K)R|9LAwjzg!!R3?5t{*f1G`srZeJ+xnKGWL1${eI1ksTu$pd2S3=6XZ zCv8k$GPX(YYWbw?FiM3{UD(ST9v{B+&|}ZM^y+8+`16d+-~Q;wOw2$0;+H@B`Okm$ zi(mZe*S|3wzk$wAfAW*>e*4>B{gXfW?593u8`tNbc=rC=@45ZLEq7eVMh*|(d;gOU zKl+?a7N2_N6YqTV3!ne|x4-=zZ~d=7`SA~a_=8V=@)Mu_qc5OOk393*ZQil_btz(XwHi_VpKxyBg&D>TF-nKyQZ~b5EY?A0F!H?rLu9X+^DD z&z-yY`djbZa_(YBeS2qP*FZO3b$+P#q+zE+J)WPt`P?O}h9xO>1TL}S_7-t#;~4x1 zGm?9JTNci`{3i3BY*ZGJDd1Cf7$GQqIn$tchQdZRJ%%sUE_2KG)Fc%(yn7`q*~Pf0 z+P_&w={5RBxxnVWVwAx;e8fMl8Ttrj1{OT>*cL#7(JUHm*PMDHOu>Vl%q*n z)nr;(o?`2qvckfw?B344g>}1Bc1#Q?s4RvY&Tc&wuet|M~C#{ulpW z3-cSu{I_5K`q#hw#V>#U^PhkB+u!+vkAL#5SKoT|g_mD>;pGoK^TI32@}GP0sSiH= z!G|Ax;t|OC;LFdxV8fD6ee4ro``XvP|GmHYyZ`i`UVHAD%`2DJY+V1|_xzi!tCnwD zQ*lFo&w;HQ`VQ^fQ!?JP!~X3W;pfG|Y~rvM4DMLiyG>wdR7+$f;bG6#_&eyzq_Xu> zXUNk}tgnG<3*gV6GyY`JRHlt_TY>$EM^N!azCu=qvsBF(+AWZ98 zxg^^GU)x)~aOhy=*|vQ*4>aF>;lv~N-1+E(sL_L$F5P?T)J7ldwQ^=CEN`os^A2BI|yJAK_f^%V5tRpvJ#o@}0 zKfI?RY{zES)r(uU&2OanBrIAu7(ZfT8jx7bg_(Wo#UkvIKT;P_0!7f3Flx&@4zYmK z(xE*okMFM>+_Or3Ab;0aQ$`%VUR~S<5S{B?4)ZHqEAgF)h1=&-R{)H`VVcD3n1h~2 zDO#dp^X54)!-Bbh6Z=*T?p&(J+*hqm%n6kZK$k>=DzaN|KKHRt{o$W}`K!FuKceM- zcmh1%`|fwY`OR;B>zm*F`q#ehzi)i~8(;e3mp=0cpZVyA-+ANZ*WS_|^v2t7zWVwL zPd@d^v(JC-4?p{juYdFJe)Qw-f9E@IKK=NCjg{B@-oL)$J^y_2<^R{bahENgblIxu zqt?y3dgCnVm}{l;IRM&opso zaKg?wOgAwlJgT_y^_aG4iZNVTR?T6U)VluK?#|T1po`a2hZaLX|*DV(xe&FG!o_O{dB>c(e6vf?r*8{iTao>p(H+FUP zcXtn@u2Okh_fTt7yIF;oE}ANTNj6ZlE+jW=ixg9k6N(TGd2Ub5;{IKj^YZp0)|U0| zwPR5dh|-s_9*jnRb=lyql_5w-^>&eX@ z4U$SE)gBMBX58BJKy`>Pk#E-{{b`q{Xc*8t6%--M?e0--~8Y& zzV#Ph`^ta#;=ljG7yjtq|GUq8*5eO9{z(w}!;gL9Bd@;p>a))QkLO?h{1^V+$KH7E z_LDc&Z>?KBSxG0g%7QkpzqV)V%)ae&yQ;Vnx{#9HX_=oO3A=fwpxy&)2C5gCiO10l zF$>j;*dh+7HC;9yQ)PAS(Tqr&z`&iQ>3E%yo<^Bzk{TyWi;A_*aKed>&qy=|s(7QR zcM5oNz^0i!IMv2%3}omTojipr=q|>dEi$LHt)J|PdBytlU8Ear_`upzcGT^xyKr*o z!MpE%{+Z|F=AQY`gZDq8Tl3QG_guL7(v3IVJlHeT-O@hPW4QboDMcx1>I(ZQE--@~ zqaf18Xeg7|#ru?Jiz`J|naN=Ic1oRbl5pcqf^IeNvl$typJPbVdef5NR@23FC}>P5 zt*o)|DZapY#75`o*}mAXdki5N09Q~jBy4A)~R(XQnbL4UEA5B?4Rx=wh3To z*u#QmFCE&AYw>PArNpJ8*-%O!CLwA@BOA)@-PCpHyWjoZFMj#U{~j&>^K{Mu_zKlSEw&wl2ew_kba(rxW~ z+PB(OJX4`;qM>@hJ#M{7J#KJr$io8hK9bSuL!vRNC&|Fo>3vlh$I+CHqNX4!JW=b$ zsm3O7Oc2$TH)5Wdwb;2eqZiq(?wr$@4u{P&nbSwK23o8!=asiWj$q9Y57YJts?OHE zWqPl})=jqaVBfZR&cL7YOlIqRyd{JSX;Pm3b-_c$O3)2i1>)pHhME&j?x?65N zd*j0oJoM@-Z@%>M8xKGF%lW*ClhE{=A+-JspYVm)Q0{kz0XEBkhaRt@a3>07xw2ufox)l2MJ*1yLA zD=_(3A@UTTTT8)SfRBMtO8UtH>!&?>Vel8f_+NkroPPPsU;g!XzyBA1`R%{@t8ahn zTi^Q1SHAj{Kl_Si@;~|f7ytOvpZkM%KK9bX_uSci@Lb)dGuKrP*OYJsIE*$IBR+v)NyzZ^DVllRuuQH=;gM*nhv?l?Yw{&lr>41=*jQAJ{%_eqi&}2FRIXBS5 zWKQs)CIMc7Go30XAHM$OFaF8rKK{<5=eh@K za$!gpA)V+Q^?0)-%T%b=Y-BK{(XG9ON0=4gQ8lj*dCOYIr2E@#(q#F%Scy%5F#{_4 zs z$(Yj;!@>X};ZE4TDbA6%qC5GmN7F_oNS&BrXp`c_Qc+&2q}=&l0NR zmawNgphl6BHjq?KPCB-BQl0PI6q<}V<&^js& zQ!~7?oUD<;PWd(RU>paWgp^vcUIO3_?f-b%6p{#|)NBfnH0~BH284RGNt0tkw(u-w zbItDFI&-*sAycMA&ANbx^KfUtKuFAFvu#+@9M1=LEWoK)Ct9MPZ4kJPUD8gajA}e7 zgQs&&KmsZ{By-faEpN^w1jLyuMD6_Bq1K@08x*8lr6lysDy8Z>$hQ0;SG^D zJCe_L!U2s2ZuzZ(zL`FVY3;4b2KUOJeA|d|-_CN;)~N$)PVBG1gcCQVOugK%s4loP zyV0|KA#oU->=Pk&#xyW(7D?pJjwuclXQ93buzUv!EvX^Ak`ve3&txclJr9u z3ki?e2dX*Q5=EQg1{}U%*U=RvBQUW!-X%BDrcV%DnmS+@t(6c9N8f0sZ>(o zYeMPlUNNH(XQpl^ zM{o;!-7(%Mk;>Cq5yEUd-PYM{1fT5-26rtUtSKpOYDxULtW5y3V;=ZHBZv;yEb6VA zV>Y#S!I%>!{NEZu09ts`f{bB7awRhu7U4O94Qvefb#jsVxz^b3YMk~rOoI|qJV>nY zImfBo2>js4pAbe@g`>J177SFE4%L1vN9Rktr3iM5aK3F8GAOiUrM{6dk4 zFO&3y1R|1khY-g=2rX!MZv~X{K}GCu?D;J5)TslN!~5jCR-D*Zar)p|pW9O%NN}}m zW8qtoYE-9$F&qiO2A!~W3E82$dg1B)D{s7h4Nwj5R-C_p>O0csJMIG?_~@H&{m&5k z>5u>JufF!Bk3N0x9c{baYv_vD*`3G-4OA~=x7Ui!fch&+<77f*u zaAB4sp;r6?z|6Ch{X6jRdHtcyp(xpTVbk=%nnfpemBA8@#D6(Y;b>-dCnWcwWJa|L z5+A(VT=+pOv(*$NgyGNT!s3IrWM9{~N^*WMs~k=%5L4l^brB-U?BLQC4q6b@0oro4 zVx9!}n5u-7L`LL9VRdyWkPPivaeQ9|b+NBDxo_gI?57ktRS-py2Zx`N`zwf7MzsSH zV-l^>2Z`Kwtz^M)Fy|>ku%&8=PaIe?xF@fh>rU8AevOo*lBAlu%zL|OO*l{0{MOA& zc9yKInqRS}ynI*rf;BUzzyEjs^*=U=dr~@k?hpUw2md{Ue)P9Lyu0rp$oW1)COPzN z^Fz@I0=1>bcP)XI;ayAYN5FveS1)8JhVy!v7tb81ICHR~zZQF6$YKl>gqb{Oq$-`N zdD9HGWvI5)ibDusurR^K4mYL_eI|(UnGZtN5fq1NtrR~fg0OJ&y>YPGqR+*mN3h}b z<2y@<%!qMBNE%@F;7;QM*zj2+?Ibu7)kt>rm}(F~G@H3?4!X|o7*W+2HQQrKM`3xq z*tkv^00XOtBH}|~KiN9O8`lyV1W4UUk`hB~^P$CW8nV=;KqaCRf){0pqAP_ecBA$X z2}4Wb)WkB`<=n+cQ6-}x6H&XQixg8utS+J3parX^=qc;Q59KJ9eESMwYM`_ zEC~R3;6*%+ha8#bmYzf@wc#Yr2}{TKuJj@whmWx^tk9{0Yfl|qe|-NM_=%)h8~ivw zsfS$>2z0qYA{mj&SN7Fb82CNl#N|MH*y*1z$; z3#U%v$o~kT@BPPb+<0gmGcr&ut)?ht4!Nm)+q@XJTH@qF=H=ub2B$pzs=P_HGzv?o zFLKV%o@HkatQy`G`~XAy=INn8ta04aoVLv~2Wl1#)=CU5B-$LQOnHwuDB(7{5$-*Q z2}%^UZO*_Bwr)Xx%>tMitbw{k2vS5IYEpb6DZo%oH@hyX409Ipr_#f`dYH$_L(9=x z9DW`$24GZ2?$T6Ymklc2+eGEY52l!tZ9(2xLf|AH!GQ2kg|G+Q0bn~RECAp<=-bt(T1LOZScmMGPpJ-zgC)^l0>A|6fI64oM0f_=syM@TQ-~Kp zV6mr68CIk2R6!}hP{EI{-RsG}Z}r4%@UljNQW}%Xy7J!i_KI#ei{lJJ?P4FHVT#f? zk~Q|vq&6s!RPiEYmZy+-jZwlFxtOXFY5k&o7*!K7%`GBs%OownfP-U026l5>MsQFG zmgi!k7_d<)c9xvlU%|qF)8L+ECl9Pqh9oCqePiDuEyi6s&j`F#5MeBXJIi^}PB(b< zyun?i$~LN&E%@#K^Pm0B@BIGG9ragTHvXUelPliy&&EIcz|-&pJRknxZG$yAi5L?C zefse|OHb@s1|C))a*B&whIKFw+}X)}%h@7S2j>**2!z|@qy(Wpy1Hbjrqt5M+TgCj zXP$0XDX8!`U@%xc|D@B_mJU=S6&8X!6UNSg8PS%QE9erEr@3+_V>nQg6~~Tnk}kwJ zgv8%Sg3EqD7>-3}M&j(4uUM@`y*rRzCzn?uWjHMuEb1!MfW95`IcSXCCpzswuCqiy zt;Q;(E4r#uYVD-(zjhq*0jQ=EseOqUxe+Z#?? zwtVCfc3SX|p(1$LA+M0P9{PP-1dm~ck&M90g2>@KPt)# z(<+$ZEt=z`Z)RmUgItE}qy!2YkeTz*0azOmIwyFP`l|2VbQHDITXd|?ysmPJ9TLr% zN$HOLfFdfEAYDQ^mC4F2n3N|phCn=c&s+M~2c>8j#( z7^dWJuUU+BQ=dq?GX5&e<<8VeqDJf(E@X?V1FObgU(8{kFD1_fNQJ;6sv6pjzAF6C zs5Skd$Za-BCJbC02SRZ!1r9~uVr?`AcMY7pk!4`|woCWKLNcKpPPM}< zIM*{12>oeYY>SVs5>q4Fura%p#mmP<>P-FK)&*i8N|C;&I`Y1>mrP}}yF5fvzR!`8 z2`kIg~)@T;L`w^GldkI2!dfy*rmuZ;tO@ zZ3%n{&70>-$NLDs5=o&_Di2$?mDqLEi%py7HpyYtjJ&u|VzgJ`B15#jsNYB;Y=Jo* zb+%317L`ERAt+wAdfdTPlr0AD^psWxcMG=#U@; zFz`&JDZ(^GGF*RI(Oaz=)3(&1I!q02U)+PjF4xak#kA&X3x>?gWXn#uB*B!5z8#C( zw=b^G-f*m$%gC4Gi^^(dBN()Hu3dGEcyhmE)G_k1S}A^Z&&m$WRQ`uQBQp*bJt5d! zo}12#u0*wJCsMsHDj(|W#cY|qqikr;YA=!sEi?-wdtQh+l{hdPlH>PQFj*d1yIsq} zh-$<;4j>(KdHyuFJlB(=5mkta(~u>GBKmV7UsJIAcQ5Y?Hnb>G^8(;JR1-y)mYzdn zNSgD!2qZ-B4z=6~390J=p7rgnDQ#n6EIOB3?Ymmkr(A!JbFLT>A9{8!aX=d<5;g^& z@`I(FI~FyY!a)W}85p%h5_2a09J6B;5EVWyW(p7YMacst2fK4EdfR3xA!)%W*K3PgH^o0wKfEPI z&jQtLn8t1}hKz=Da*N!Ma~2RP^+7Te@X%^Hikg$mXS43}U520T&|{%Ar4~yXR2bqD z<1)w*IBil7LQ#>$a$oYX4YT&I)(Ua0y5cxKY)8s0HSke*MBhc4DSm{vl8a~1Qk=6r zx=m!{BH5kiaV3n2#TBiqd|oN&)~r#)P-PubW^P+)R-Iy;cy+RD4r48YOxm?4hOSim zmP(rK6U2e484%y$PR8cw;{rQGl7%_sp*+J@HU6|X}-?D4T$piX;*7h)-zQ8?N zhgJ^lSx)nT9Jg~ICnT&cE6jKZmG9irm@{L2nL(D#a>Gw?Wd2xg!ZA!uH{YSKmX+9^ zW$Kj3s9s31CwP+7JfI!?I(ZqbUSKaA+c_d@C-CQhLX$WzoS7flMov*MJmVPMCZO_1 zX+NLZDk1CbVNE!pFHJEgKj{2|dSzp?o0L`4j?~^q+mX4Jip_WvGN#}9LyBwW?BcIs zKr9^7#N@`qS_0B>i9CA|g=HX5GMHQDA*krC=?4@cg%j#|#4Irp;kV&V!U0vI9GoQv z5`i;3Kqj*QhZd14Xf?ZQ${Xd;c9gR@*hnKwvICVZ_Z(DUrZX3&(5t9&CktTpg==FH z75r$KH&IG5)Y2=FjXxzE`RIHD^HDXgXC!R$yvw*w71~^+t`JoL60ceX727Lj^RA*j zM9$Y{9E-Yq3C3n71)O;=txBWAu_33lg+|I0Gp*{=U`7Yf4lge7Vz--UH(7hBHEk;b z5U#V}kaNLfXfNWY!q#QSq>J=V>|J`Ykc=3O<9m$mENc#<0GN4LjVNA#BTzyqxkXf@ zuO^5Jt#T58sa|wq@3ND7h-pq(@UBoSFhF~lh=oJDv0o%%HmG2Xc?;bpSPBDYYUGJH zL>96qA_K1!XG)0@LIQ9nFBxJVKFpYa6E@XZC0{9*Cq{@bb2biIv`*q9t&fZrVXjff zUJNiI&qCLX`Iy$lQi)B3(uHu2jdfnGT>XD=L zg^S(17%c6u=rIClxsG`0b*m2vpctoCys=m#YrT+_;2cLt5p%?F@m~~3xpnR@UJ3m0 zYBW2UHD<^4FJ*9ign@O?=sE7xY&HnCrqFT6;yM$Aq+=jW_z6Fd@9)iBprR}}5jTP> zXXV6eX$=TH&PtIuM00xZ0kyD%^LJ}oQn5&>n{@5ClR4L*_6=&j*{73}F0kjc+loTp762yv-hu9bmVR$#p zQ*`Gy#1aCbK8sl>6L`d2AXErs<{Ty{CixcTD8?iMCzD@T=F8VlVfrp30Bp_9pfJM@ zswRN#SlnPR9q}j0_l1puDSoPENxSL`7q)YGw|Km`(;=h_LYStVSdE)^8AGT46u)B4 zq{A3AaOG&guSI~SuZ(W_3q+9U#aYd`#L=ZiKDF` zhn1z=JV!EGoGboHC9323GJG{jb1}8d2s>XY>j5?(guV31(gL2djYQo1*PbPS!8lMR z1?<*~zElV`c7|%iXR!NF|*v(MReR%y`)F6nHEAxRr+u-c?0``ick*B zTs7ma<-n8jv)F`qy1~7xhWA&ZtlfFOP_Q32ut z+LaGM&K5WL!lT;l*Uf^@#;x<~l~r?IJRP!HsEfrF##?!4A?LmcWejpW6qCsHSVZE| zUbXt=;v?S%2o*RKdZQ?e@G`E7tzghP!b~E&xx0bEbH}uAGX{1Vm>~e-SyWc2*fdhj zj*TEl`nv^9TMQ83FH|LEoPv^gWEfhG?<|qzVjlpHB?-EA%ol}mh=aB6de$k6?qTiN z6Y{dxqe@X4b0w@3C^9TjmDwDrRalZtSJ*6+rY|vllqhFLcnZ044%9i1V~T8D3VSF~ zaPAC(J2fh)LmSC_ZI;qS@D&1Z(9@e5i8JqFdyMUGS7r ziy3vEvPHT=B3uJ=kj#s@DxU>}^lCv?^VT_NxxX~&xxh@lAnr0SQtJ$^}K}XbF?T&HzRXMYPJf(jUVqCv#XTf>Lpv zY={C6IdLUka-b>xDUuh-l*zM5fiaS@{BmBP!a5}{=7W;LD6*^RZ&fuk8^DH8rXBND zCsLW19b!14J7pfuV98iu4F5M{Z`~>PqiFItJybGBL-^&jj3MSFj@7fVh@uXnh1U7d!+DH1CB|LGWZ$sC$XjEQh!BbOWgg2Ir9>+`lHF+7Gz+vuKn&f82IWJ6AIr@n zN=Q^7u{;5=UO1y5Gg?9BAM#&(jl85AlZ29}BvNgxMC+zPvP&^1O*rj-Y9Ul}Sv%m7 zM@X?*?pZ)m$dT3?_pkJ*>Ilpk4^i>OAOKrGV^X9NdQq&T8|2M#jG~KKdQ{IvI!Wj0 zjL5ndiSmK%3RXRGk^({@Brb`#9S4-tVpj80X6EvuHyYJwkm-2a%_wYE;w5&ISXb0R zGD;O?(Us<>U-5KGfb@&0{FHYX(NEYEGa1aX6gtX$iKEpV(s<=c*h7v(l50d% z6cFvNP@{N!|0+s2!$lyXfbli-htyq&?E!?w5`QpXY+ATcp72&9BCSw)s1!BKTe1TC~h;c@&*w8DBIvGGlXA91%5 z?!4&Wf$I6kca@ypiyI4eVq~=ZSohv4H+cMx=isCW=Wylt>np}lg4C^7$k)z*s1P2h$~b%`A?SwCZ@76L*U69Y z6oPJ=cI*SGliMmpNa1`kw(h=UD5T?E8}Y%#r0mcuKHBGw@Ff)*Qtjjy>L}jgfOLeZ zH7a_Ggt|;qA)GEr(5>VnGJcYt!c{sR-$dI-Y48xygf9VvQVO05!zFP^NiccnYEi}z z1MYY%7YKVX4Pqewo9(&h36AnE94Rm6`-cj36r2|Z(uIK(W%j1Zoag=P@6;bgSJ=9x&8bu4;Q7gNb zY9C%nP70#fOiU@L-lCu}-O%ucdMW>4&|GkkOjAmJt-zJ%v8A(BYq&5U4cOocOYPG1 zYfK24;%1i##U~jJ)`q|c2F!brI&s%?9HmORq#@jWLT1rTXt1Cr=7qiyh1nZ(Z%Sfv zi^+Ny3812i%=zPbYLTL*sl6`$pUSOZ~l1R0*OaGDNIF;djydE6+YN4S%Yw4uUkMCMEa4lhi-yTWwE@|24y6yaG=ot(0jZ zvK2-tx{X(mCFcZ^-fG$!fi8J!%AP>UcbiB&(U5yKA|6{|rL2W-9t$0i#;Q#vJZvyQ zkPwH3@We{wpFQe=ctasJ@4!Ye2>F?%1filb86-l9`-3+H%ropS;O$l!T9^^NOZwc+ z4$?r;zF|sQ$u^HPl&Kq>u17uvW?s~esu)lM@rXT@a*XD4B8WHy%exp_)KGA{nu` zm7FAGDOM}J6{!IOl{n2XtBgSODK3f7O~GS!B-fw<=a0gy)hnMOWx$6nPN^G8!$NX` zToO`LjE;e1sB_xZLe+5wLKZb6w7FWyoWgq&3bP}g3NWIQiJDb^MMm@DNCrUwB9P&0 zRM+^z6>-IDpesccpH&da)~%V~%TIaFdi{f9^BE!|>tcq67C)Hr(~vPinJQ%~u4Sf8 z{2L@BQd2mptq(R#Vi|Ej37_NC^qgkh*%Pg!ftJ688wFRd#57G&4I7t~J`0r0%7Ss4 z!eGD~;m7L$23L;pMpcX6=|)+G4MH#j&nRS*&plDPa|kCC4|VKsETe zQ<$CUUUZ&f0MYdJ6t2jMCi)=tn1f-8Z?kO3CXdv&ki{4o2|Ix&WemNcf#>!QK_Z={ z;=+TI9VxfKWO$h*P}E4r%}GL~6gHJ`CYip6uWc- zgCb+Q&~%*?;mFjWF-5PjKoyp(vgNY`lJyo{xFPU#nCOpx^vyfWc@RbZh3{jO!W)Z# zUHvmCM$DA^P)tIBcd$?~Q%R+dtx-xPM@$WXNhJ^&1VP1T1)n~PaclJ!W+Z8Am*KKg zttZE=_l-x+D=ckOp|I8@oAw6N68^&gv)XC=z+i_ zVGE%Tmj2%)rmU6=BPf|}4>n@0V^~-W%P~cJyVcA} zZJEgeSZD_@0t^wx!nQb}`3X#lW1OmE^Yno#1&4DuEWwo0cP6EuVc7(PlL5)krga%W z&F}cQp73Xc2Qtl%Vu)P83=l%CVKR<#BNn6)erhKlm;TeVon7qAI(s79d(I4yk=x30%ut0Wl+&@UsI_?=_A5k9@40~? z%G<1|S`lu}t<6&TK8r4UK2)5`XzT0{22PS?v)1f}TU#rT#5YKw)-hA;)fNMR^_wW1 z!(f+KI7^A@7;qPJL0-Ul0#ryyo;TGC$@W6#T#7mXGYhT($jP~`0UEK9_*`gV;@D3{ z7*2=}i9^FZsJjKUL=Zua>_yzoH_dO|lzN`DpSxLnpD8Af1#rAbWMsJkCjO;p z&C7D@j0i(WsP3QIc5IYD-Zvhhbz>&c>6FpH?mqRaxSNqNKKT?z0PHRCbgKzS@hM1- zH?B9wz@FNsZjNo;I2j~5q}TIaZf-`OE|2vSTh>l6=O<3HV9T-@QZaJ5P_XkoWIpyhYvdY07in+=lH=f1VK|I)dW(w`cjH%n6+T>CiNAvJaY<~59!bv+ z>d(bU6Dj1fVN!`H?h$euZFWv8tGHQ>r7v82?DQk<5tg~Q-;Y#G0KX%vGqF5#D%AKD z(@uQJv=pz9U(g<=-dCO5(~~S#K$WmX?3`DMfhtvV^b#^DVX$f1!dRjKIs=@T$cY}K4!CAX@NXuyb zKCHm*mH`zb=Cp|oO>NbC_{ z(QO9_RGbTYWdkN_9p}g{ZMDY%@TB_JT8|hmSq3k1F3#MhQHY%pURBvWS>G8@#S{c! zF+oD(I4SNdhEW%=V6b2>u8`%)>qRUNZ!8QincAu(M=bH80h%GbC{ZV3OuOR;1*%CR zOCT~k$^u!luFV=bLvDkvEC-I7I3)&?y$zw|P2OEiqzEGgfHnayZ?b-hwZ?o3WjM2U zx(b(pK81czOA_(~B!2eFu)izWVH(g9;U%CV2?CX?iijNz&>NW%{-wv&A}t}bF*3#I zjG5NU^Mc}LdIl@ezTsN0089oR7WzQ1E7@#WIhu$Ag+)q+0ur3COPi`;CTk`^1@7&y zfCNx+cd)L-$)^|ul<;cfRG0@31lwEO+AV8Q?rV)k?^I9A1DZc)b@j8vFd;^I??u4!FFuHeeSiN#_MO?3-s*(h*|+vPgNZb=q|@iKArVIfsm zu{Jk44@~-16x8@2!i5wATNDb<>)$h8Y@&S1^;QhC$&o&VZ%(#KIrpBzOyUG`VAg zNE}CUhr%|@h`AEKvpgAErQdno1hyzs?*~Sl|xVgmyWyRDNi<>)F#1xxPZyXWlV{nE@tOOQTBKXlLF@@VTt{>9ae@}31 zM!-GGwJ{)|XfG$M+h=hlxDec;UT$+X2d`$hER)3ozk=un56Ffy^s2on{9|S^D3y_e zAnz1mb+9D-N4Ih?6M-qAYG{vyAOcUnO^-Rk!;lVpo0r9q zdLv(NHT#S4Pvo8j@+D+k;WQ?NuYrM>eeO>Lv~HpWbtB_E{%OUX765uQlNKDw@oY#B zH&=w)Eo;XY>{mpO&y4qW7A(;daH6jZzBB3ZJ4B7w^Cj!s9InoONe0w1FRFTN2`l4FiersF;O_wCDtwq1;pm zi^7r!-r+nK=FHC4%Jt{%@wP6^U6AN0!a`1BSz|)+_VorOVUKRxsAR>40&dAE^{Y)W zHJuV0N!aDvfG84f_+$nYFhQ|7j`vUBx%oLJ=a>oRJmE!|+?9K|m#r2Dx!H{)SUrxZ z@x+Q?uvrT`J>~5j$F*Un=JxOlmE-&q0Xw#GOmpSXvID0^!rbgZA$xnWYr z`iZS;#x+)q95b=i1TCkv#A_yYZRAZRI}AvgD#o;}o!HHdQlW+Rl{PjV+f+HWe${AC zoY^_S71&_4EeM&|E}Un(Vx1;}jYpGxD%VVOh1sE_a(q+8xMtIFE4(;Hu^S!&GkjA_obW%^KzPW`_Rz0FWka`M zDRerXjtY%Ai>=@%Ugq8DOt~H>)NU3w7#r&tZz+O;>~X^$7T-qne@=n-Z(1|C(N|PC zf%WEY;*?{(uXPW?iIpm7##9&(!20Ukq4|0X2znU3_fC=%XvIN#sJu zSUt9J)!3HGv5l+8vfhqoH>^eD>Isdj#y6}U-E7fC_Z8zH#KFf_T+_H}^s$v!A6M;$gu4w`Zdz3F9)wt@K7H5Es%JKCpM>VXxriCd3 zj5QP5HOQ|SpU+)6rhdifhE-z#qtggPn{lih)41}QhE-R$R*Y?1J+`G{TubrdvE|n| zveAsG)#JRYapmYH?^->+)gCdc$2QRu0EzFTAFdqTu)+n5$)pi-x6Fg)^0z7VDoGQ|wz>ll|xs z08f~>yh2t2*EKA^{&Dn`QSuzgpA-*kW7f41OyC&?3YR*^D}lYJO#tq>_D1$i3}}ZM ze`$qP6Kik;PHSbMBIZ5bc9m~_LMIMvy6j5p=$@T)Y{eK$+_+j$>;|0DW}Z@3b4=5! zv6iyM*+{a!3Y$mk$u;$H#pvQYA6sV^!W9;Ag0HvP)?F3jywR`fR$L7v`Fht(U>sn; zck6(L71zMPv1OwyME%NZnkvS&R*q|2b#;p`fB7|aORs8JKB|7%mG#T6YFcqkd*yhm z*|=hq=f{>^Rk!4ddK;-PyQXp3DCcQ${uNhy-2u%jM;&#*vQdZ2uQ*cnfqF1oKC0FA zFTbY2IhS44485xWZwxrqFTL{Uk`L6`EMw^?zdE+$%0r7UyRP)I!{r}nSb23bTrIuI zmDDe}^2p*39A13I;j$}^EVe$k&T)&TKUN*XM#b_{V0sG~no$%++X0Za;t&QkdlxazW# z&Nc*fZV^I?HFzazi9mqYcB*TQ#dcV{iM6I1#F+3DnB?@ha!7Wk{z*juc%*g#nH0&A1%N9sDGAQ$}7R+Q0e;)mAvm*`3LICFZc84k}Hla zxx8_yCBD+T4llm!XxZg{mA5-)@ny#rUshj!xkp{u<%dh(d!+Qe#};3HwDkSgFM98h zlJ^}cdH>;(%Z`*f)fFwvuJP%PIlSn7M@!##xa9Kd7UsG0G`cWAa`2+})`O^rw|JDf z;8A`aExr7Z-*oW!7Ikoz7oBX{zS^+ zL?$#|Y+|G6fGa^uh>Cv8$5l)KHb0s1qwLRezGE!=U%zrp%c?Q0tK&y_oYso*?Q#L| z!?~=unqg^VMwVXLynI@1Knf0t{F+KwA91V`Z0F(55Aq*Ok8aXvzEP;SDfKey@QIDZiq=>~c@)%P;f# z(M7+1qy%6ts{^^9<@cTNSZV%w6n+-|+oPaTl255Cb-?@Ui(mO|Ls{PLy*aY<{g6|D z=ik=l;177q(URXkS^|yEcE!=W%PUTGIc6A=kPI?eb#4zLL0n>yNZA$_8xfwXbCUxV zsHWgHX*&q%p&k?MWeP@a`B(-T0t1q5{wyMc(5atM#O+ralTGnmoeizpL}$gr8=H-6 z#a&~Rhy(d7)}#0*SYn>>N&%HEb>g$2CG5*J`ydC8*r>wtOs1kxm_ zquWGT5?6l zimTd|U)8kqipC|E`DfkY_XAAJiYwdm#%qAKgY{c}RpZhtT9=P%L!uav^2?f+UD4qa zS6r+9t&sP>iKJGvFO zUw)0Zv~Z)0=MtYXs%fb+T-mVXst6PmB%D?~QdZwwGW>8#hZjZq8)kLcxFPwn{IoRi zW7PnlD*;;cN#b4{O=5rBcFfOmtKXyZFd)TUAE8^2UQpr@n*eoaEzg3r76geC9MLmb ziQv%j@WZ^|IX#Mn2!_})jA=GWD$1b9JTl+1hzdcaKk>U1(mWQ)#Slx?%L%1Pe6CrL z>n`vUaz=i(v4I6q#4}+j_(=>kt4qwaZgS728T~XL_mrBe&9nQ2nKtIe$8c-~4{IlN zJBIJZKP$#}@VxK?9>BA1QqTHHz0}2Z6S~%n?_N8h$Mj}^^nBgK-t`kYE5^W2fU(ND zU){B4LZ?T?7|YkbYE1W<@m*`i^sbxG>pW|{9po6atJ=V9)z$gAa#Y9aYuZ-BSPt%9 zGuAO(YsPg~j&+h=7bXbudgWM$byke-6LS^NYFTkr>k1$l(^=`a6I?*s%2DmB$F^a} z%dhTWlR1%PSGF#P$y{D%#kj83}K|C zMt2Ts^OPmYr_AwN_ykDOw*!)qbWWoYl~~YQ6nluoEgxBCn+btsJ`{kxJ#~O;e)L&* z&?L9%M95`C#ic@1V2U9*u~acB#1oj0isE%Yja*46FvIO2G6gi^lqBkv*FslO;h`w z$9v%rsMb&D*^u}8ZLhblpVYOE^&8t>Ij+|<`*jl?=HYA(?j-e8T-~yIbQh0IZdyB` zbFC0Z1nq(WDq#lxLjv=yX*C<7jK{U<39MTkHhQOG!7H+Y7=rt%*utbTk4 z4-%P|xTpTjsjR7A$p>ZJXp#s8ewZMfr+{2BjI5lQh9esV58& zGn19bEbBr7A}P?ilX=OEYdDOB94HQpZpB4REBeC$&8!zT)ym%EJBAk;FqK zH~vNkC{FeqekjRBc1a`{anGsbm`KDVzM?=v9ge@(KO-GWNpx+Uq5Q_Lii0Bp%O*su z-aM^O5}`mtG-JGSg3UU;DP% zSPBF2i4nv7`BBJCYqVZYo5N&DawitDb`l~yOC*=1<7cJf#Yhm0B?+&0D}>YYDCy&$ zRxs=6Ta`;9;gWsytSyQ$k?K`cL;vxdo}a~yb}grna<8fdaH2x87}B1x1I|WU9#l)u zjHn<@9ar*hTDBt{M`GfGlDATol;5UeN19AIM?TBDR2gwm%L}@y#o@|v1x3tR99h? zlJEi;5DMNRO=sMx4 z6Ii07#E?nFhk_rgF0?61$kr3Uff=!MZ^mNNKcRF$Np>zN!0@LPS(QW_BiCQ#)bhNy zsE^99EQ?ay*ZH0c`y;<##g*^+4vX)c{+x7@1#)C8LxgCHnEqT#>{k{}ogVy*oJ6~j zGmxy2aN$@Ob?R`^P?>(}q8V16!l&DCVFUoyJ;eY?<~o1ci=;kblKLGnnFgLzTJ&dT zuutW7_6#j?0fohr5z7kt2!};2r*mpN3AEC6Tu+2zDAEEH*>os-6=g96cyNDV2i@7*d-1fR+AVV$n<88KF1W55`--zrYS~% zKJ2dVWw`R8(+1*vF@M>s;Gw`0IQb_SutFjTq;#Tn?<0DOZ$QaV}|{wphFg zDiY)*kGU}QFqFnf%@#{~J$oC;3qZxY7KVLbc4W!(MD1wS3*JVs7fd=&Ae|G^x2fE+ z{L)x?C8Nt-7(+BtKq#M*R!#pLd4>Mz751m_s!`7UHXo4`gS#^Abwx@v>8kiFm7>aT z{B^~yZJvXZW1xsV(Zx^{0{MD{sD5Ve$Rc*Ie1ZkvY7USsl`c3zfMH{wC! zM>ZAfvMEV(55HnGcpsSYgrD*RqPV%3l#wi05@A76$Ho{CPexAb_>mm0xA0TEp=i+w zxjzZABsG|zykfmV@K7~gsTXu*SPHl0U^XX)G{G#;;&`H`Bwv!$P+63}E7-$SsmBCZ zf2I_Fk%^NoDQZ8~%NP6V+}8l(5lW*cC8z+T!k%yhxtEhYbmxZN#88h!TTD$noh4Sx zli#Kkq$uh`o8?0-w_gDRs}f67v25R!s6l5-rB0s6Z$xA`;8M1B0XWK&edNk=!?)9P$HfSqMQc zEJ0V=EjfiaHMhJ+VJ<>Wye01~Tv%a7I1W|T2v0gDoGSQn+EfWLFKJ9GaOl%x?h5FJ z$1+fyk^HGwyep?Fh%{7yD@a>qNN`v{<+MK672@87j6i8joR~&GOf2e<-?BO0m2i*O zD0~eR!B`;YCQ6dsGNmdkSOR+=F`@$$e#*Vip2TrjDYs`9IuzY=I2j?#euYRl%&EdC zz%K-*pt407m?JH*BzP9uD^jb-vu%|ko@5adlo_LuEbSx)0SsEi@*^3~q|PZb zy7BY`hXor207Q0qB^a0xslf^5!Yao#uNl`?IgX4V{wj`?E*aAzr6Sv2FZoHkZOD^L?s4I z+?0?FCc|VH!%&?l&m?G0ll}}s#VcGVAEY?M9sU1wb)MZ-UCFxs7sm+Ui2b|IHoKZ^oU81 z+;yT@*zmX;J21#c&rVfwv`EkcF}?H)8%p)OdO@#uR7n?n%~?O_jdZ^CG_m$K8^$!$JKhMj%hDAr(2yqq`kn7>gH$9^Aw%ky=J!97O^Qqq#_*p#<4a~rd8l# zr^)L{t~OENbxqxVYDID2b-veZSMfL(PDlmL1|)o;=qJNmOuae7Jw8hg{X&6Ozse!J zWua2&-!0OsN*3>8=(i(%UcI!brHGzPaz6+a+(hU`0A_*~6e^K*t$69hjo-?oGHT01 z)M3vJK?uc0(UkuWhIRY0UtNdVw&fWd`|#fqKwN zuTqdvQMnOF;*C7Rs#1vv8u{3}_1|o>B`f}_LAptI9pN?jTsx^|MPAthJeEmsC$aD* z0J&uauWjUU&`mu{nw13)bi0D=L~SbYwvW3?ELW7KG%8O`)Zt2=DPd&tB5ry{#3Lr* zR8T#7p2tuniyjKKF6Xf)kA~Qx>)f^|*Rrg@Lr4i-JTl^e9cvJthj>Z=3VrQR_+WgQ_e7DOi4_!$O6d zCT?IW+;(}9$vv_Z{VIg+Xe!)O^V?YbN)E3QYct{{6})bqeSt13Kf{zS^&OFW5AsaDEOM1l3^JhP`=CNn%@?z`rW&Y1NYoV4EJfmiLKy-L)OEh_! z$Nj0E5mC$HX|whMc$5Ft3cqTqE}m=gG(fupS<5Ki;8ic-(CrNC96zJBQQJ=(_OiI; zd5he54f_>6R6*wso!N9=Jrl-W<&OjN^iP`+-2L$!W_>SDr#Uarz%?^tU+pF68vc6q z0Kb{Lz88HTLpbC_ud&xq;hvqxJG}45jndv%dVSc#ou(qbmYoR2ln`@>aS!&jEEJ1u zq_SAzN!o70x&}LY5LhZa8{tN~orq(9sfSp%bGWLsb0xv8;?MJ89u(VN1q_k!e2Li6 zvbna?kyWIY5qBc1;O?S};Gz(br9`%eHwhJDHY1jmS_$!z@=lD)ON5>siq^%&mW9RE zMJ2X2TAnMkJXch^sK8U@mPN%K3kutxEo^_Tu;aPn_UDQ_u+X)TeYE0^#rft1`EB$r zC^j!dq0McbpWB8k%xzl$FeNx)H-zEL*8E(at+eKa%)qWkUPH8((Y+PtkOetjHKE4I z!k)__mf5V?cw~*j77q(-o>v!m8JOQ;Ax+WCbMLlQ1vWT%{f~mh))@c9bLT2Qb(gMz z*jcvW53Ba)l^cf8TjCwCU8~4=jZ%-Km{F-BcRX;UV|O`n06C0M!fu1*V2)Oq%f z4+!Bg8k*sU*Q%PFS~DfT)S=lN9Lg4BiG!Jg4`+BVw89_6#L6OLvM z*;hg#UVLZS#$tzPL09v$om<$=oY%Q+KF-|;TUX5sh?-<8@@#(Vf-d%(P-H=w*SYoS z?k&%BZGNVE%RIu}wPjvc(=)j(&veUz{b@A?Q>(^8t|5etA}Pnl@uco&F^ui!50=I)H^ub8etx(SW8 z2&EGUMU(Q!>k4eqa{ad}YF+5fOLEN&WK?Xov6!a|hb8pJ9&SXF*BG>MyoGQukV;DB zea`!L0KcS*724+cYzMPL&4wNO$ZQaIY+cx~d0{s%PHb7&xp_esd*8erft{BkHq)go z>`wG1IWru^4huS(=65tb%dT`cXY@8Ao75NHex_sdJoXB4W)gO&+2HQn%1N1U9&I{o zdio-p+MBqr^VpkaPF?WL^E#X6N1%x{QFCaXQmnTUaf0~d#Z6CkZ2AuZ(Y^UuEM1$P zB;q)9Zc;$I2z`?yOMD%>j!jQ?;f$w;g`-CO9AMWg%yG*;);As=3!pF=(sl!``84#xa|eAL{Q`MJ$p7Jf{? zUcmLqDd%X9UWa^rNKM{>C3bwR*soVyba@wc=&cnl^@58{3Ll|YtR;)|dVnuDZcIh& zh>Lu9IgLQG@85*Zmv>3mmW9MCuW$EKg3fH@J!T;FVej6`y8(+8S1b z#z|qdLrpBVEn%gkqDjGRTZ&%h{Q)nQD77lVZ7a%p@gUwYU;(yLLE-fPt~OU*`|^Z? z=r7GFhbY5fK_?gSeMbQd;;uMSE_p4Vw_iv{ycIy{kwQ6O#ibQH>7B(G$*R!uJTJrG zfIYth1&5WTHr8M-U@5k~;OeFYKQBcTDS5K4cf*(Xn z6n-2Awz3FZiFnDu0v#Cg(c{&W!ABDVCmg&#-H8&+a9?yO&pS#*VU^&$B{07W8(ymSIPF z_AKwAOAgDcdzSU?dA@h=^J@33tnOKX(zh4o`6|YJEBp4nKyOuDEBp4o(6{f!-o2}; zdsp@DeL;(JTl)5`?%nrd-@cc6_r6%&_Yz{unoIlE_U>EFEdXsVf1hFhn%;eD=wi9Z zty~WaMb?vS(Cp@BfmP+pJ-gRnVIf*!MarRi*H-tu%)+uN3qE*qb1^H`y)XB&&%W=K zzWuNFvJAGHCw!&%!0UYn)?MOF4F1a-z5K~OR=+a7-pgwh>^bg#h4vC#V=}&0-T&$( z{$MORmV>WfI=Jo<{|J&5GJn;Cu7iJ)C;#CHyL8-M?LYWhzdT>><9}uy&{UVO9QqT| zcj&c#wo0YoNf+m0k~wndwM&R5c@<~(z9Rj=n!f!nUpnwIO7DTSeO$ML{B*1P_OG#V z?WF@KYx)kZR@VU^9$eFZaCJZWK_B9LU^PDdh`R9ip?p?fI{2awU&?w{4;)Ps;^j<~|OXMuiwU;GW)?P`vELRS{a^=vgmk+-jGI03SD~Dgk8GAo}{G7i9eRy5} z;q~bKN7nZrrsb_34wK~)f8ZLOw>YpL{!uv{~?I~>nh9ofj_Ss;Qy@s z<&Dd1Z6A4qKP1xs&c@4s**Jh4edF@cH|ZL9hr>4q@Hxu%H_jU`<8u^w!$x{hT&)rFv9iRbnRr*wUe8!op}4&$+xea*mV8mW?SCAezNKMyB0fG-+cX) zEvGi!IJNo4sV!>XMX|iM< zzUtcjRrlVnEmrn@o!kG{-2Sg~2WY=R^2ouz77l!qKk#kg(6{+R-xd!3t#C+EJdAu- zI{clKBj1&d{H^ro?|Y8_cDpcn@9GbIC%!Aa^L@`>zVA8uL(ehf`!dR3+#dU(a{TX- z6W{lo_@PJ250w+NnVkH4<>cS1Cx*|qAfvj5EyEwTjGk*9IoCF-Yt=e>e&^^pgv+&a z{QS;n$ItH?Ki@v_$*zg>yCyzqzk8v5;zIk~Pj=tEV7a*a-o@Q_-J;y<*zDu>Y*M3R&fv+S|xEf#P4}L8ODmSL5I}`9t3n4t-OkJ%aLW z;mBW$N4_Z@`L=lE`%9;P7&!B7>CfMmj(l5w=Wiv+_vLrKv*;pJbSZwQ9Q}Ls*!LA* zjp~ViAic=(AA67gqxa-L`cD3M>0QgoAN$|^vHukE^QBWi_rLek!23TVmp`EW*s#I z{_*cOKK|zo+H+DqJ@@;k=aGMY_6hRGjZYp(zaU+5!Gdz}!Oe@(Z+1Mm+40BCiw|xg z9e>>FcyPPp;jPXGA-6jp-tIyk-J$J%aHpI0A+03$@J{~WU_LtxW7qUoSN~_~{`8ku zAKcElxA5>zF;nm_Jh)S!eKbg0d~^pXJQyrKzy~`M-j;)WZWn*-J%Rkx_wG-(L;WsQckyZgQwwGK`X&9L`S- z=O>3~3&`Y1erlvJrB+I9q^QHuVnb@99F}UMCAZk6*T#yqG1^jntXQ`)HCk5JSh+S@ zrkz3=mtyG&Woo>X8Et7eBt^#hSdYd^IE;bOVyQ5E3gdXVrCx^A#wAnqGL^-X*r*9J z87;%l|9kxK|NJ;H$p?{36v-7S4EE<4wsD=(yxNt8i)9gaIW*$43?DELSc>VtFsveWF^w z8w0}u-97|&*11xfh+h0XmD;3Cb2@pJr^oP-15|jDN_~uPO;7!rGh%NI4uM)YJ(Q8(s-$kK2elK0xA(QMM}XEFv&74 ziz6tzA~;RRWI;G|(33)}p{qKrsL@u!lNL)lWb9qL-K`LMcQKE9<&Z`71VWsy-CMiiB6 z6Y!%X6S<`ZA=0_XWoXGHF1uSrq3l>k=p%^einYOTaMABpXYMLevWFyH0I16(xJxs0 z=nxZVjdjo)!|5^=4ACUUNib;gx(_*Z@)3K2RuoxDtx3i?W)6qc8X@>$$p8BK#{d52 zrtFC;V@7^M%n!Lpx>>Y#00v3M*~18lfkuY0uH2GJPf$V5A;W|&cr4T)@dG?Tlob`J zhOi*kCn?Mb7bRL_yCoi4+}5 zoIn_x)8a%HI0^i$jKn0+;x2KL!4q7`l2VPkQc7`#QK?GgG#0C|WHn2o$ZH#cWNb2o z0E5+w0L%DEX{SC>qDW1Xh*HAgPzVVd6kTmv9OAMoa1l_$6Ndqn8Gwp=G6o@dq7cEL zNHKK+Nx@Zo5eNF7h9ox+iRkNeF(hCUCy6d1E*}mZeH0BBIWcEd(BdNw@if>CeiFCA z5A7^MjpT!|24DdXH4AK%dBjqdf3zHuMOlc7Cc#Ha!XQO_77WUhvXIcKjTCC!sw6_Z zdND$&-lfHi9BRXI*19*r6F;D$!`T&1!RducRIH7-9*HFx@i8za z&HMmKB&FK8fXSB1TJ1=D^8!&STdG;EVlG~0DXU!LJu_M`L>AH)pF;-)y_~|0MZj>_ zU?!+jG&5=NLqHXAvYA3ptOY=jBcF(PtXpO#da>9I1{#WC2r4pu44A0)>Fg~3bPAno zPAaoqEJeMWlXij@IjeXnH7V6-awQ@y!oAWCiiD8vc7qnM8MTE&6xKh^B(tsSj)0LO zctk~H6)dsxnH}OfmFzHMf6tI|QDh|f2Q9i;_M9qVLL%{l;zL_7sta*>s>4ixL`qT3 z!XEW2Yn7KWuAFuRjOv$iQQT)4Arg*LkZ!e14n-<*k@63fi&i3d6!g#ukh+YG_%U6P z0kG2>Tm>7Btb?c(h$gYa-JZuN)HsD$7PV56PvXZEg%1{$QG#oq1apiH*s!PB1PKs6 z4vTeHOip1)!cClT=w-IC;Rh5y(tZ1;))mbwAM7y0`nk?+pcg_xk#%)VY6(RC2}p=w zC}|0u*_Bd=xXRP8q0%8fvuoL=@@8AZ75>0~@6y zs*)E%LI^gDkc@LA4oCI)C9`YI!=YRAqjiqO>1cY4n_?|~<|H3tB#Knsf*(b#0gSUv zf~Wl0dBdqmIDvr!XBe`iq|6X&p|ny`FV2ij^Cx~{cr1-PgQFaINka_S%y@NXJn9s% zd1ei_1P{^~E-K8A4wZ21lX6S)G`e2!1iiXP3x3o>ju$+j!l6o)vXCAW7#=7h5d}^z zYPzGRqD>BWN9Y}EFbGk)h!jNfN%=>F_$Es%Awmcr^MfLU(7h1S5RDQfk#hjXPyrz` zLy?M_DH0n&h>RgBXEH{eBJG4d4$&!U1#(e_O(+Gh2@42KJOAjm-TXifz2Ya}X(S>s z11)pX(cKb={~i6=#>ww8W=6!(pZ*2c!p?&EIsRrL-4>T-3dns2^(jgxorkXkX(-8eJkvECq689^Zl~|A-~8mrPxje~NW2iW=$2sR@3Rg#d|!gP_F9C#z+| zOUt3kV+FMAkU^AnwM4TtV_;-d+7WD;Cl2M~Di+vefXO*l=~(O&NgxWMa|m{Uq~VBB z(INRn5Q`Y(vBV{>RIBH9v(_JIpz>IKWx;T7BiL* zZQQ0s35&xl?ZjHzsZY$1j*x&#sR^zCW?H!@j9Cg2JmO6#W;bgYLQ&2DiR8oLSu8mh zX)R4Inu$ad`6m`dB19}X3pFa8$T2*D8G2+PDVe_`C8F$XP7+rM31g7v4*#}35tY`laH{Gj8#(Xo(jR5UHEXR;goSRE;30H)&QFMh^}vPamRQsm$+0p^vqBc2d4a)C_{V%YR$ z7p0J<6d`!TiSr(9c-m+}G;=~l(8@WGlc(IWv&6LI8K2!*R7pldva?uW*`u>a8vLNU zoQWS;(y~WmrB|GMXd~wYJid_^KPkS3q&rZ-7$UAjMWmE&ADSpRw*f*+JX%OIH?*Sk7U39w)Zip-B%rKY-; z)+%aqa*=N810;Y^E{gmEJa8opf-40#9qQtT&KjG1l?0>7$)d?uUPVpSFm zWQpE%iVPJUM$n@?l~m(Ag9wT9#)N9)lVp_YTpq4Z61|K~Q~*O5U6@o2m0My+!p0V7 z8zmf}q735|a)Qc-VyW(Jvf3z$SyJ1`KM>Mg2LMnZ`ff$hP`*y7GF>2qQWG29b&(?_ z0p=`3uh!v1-9Z$dN;R6w0%;tMXlZ23LJ3G@4`Awn)(Ck<7NwT}j6*|Gi;Uzd79bfg zZsL@+49qNYfspKDk(X4+yr}kbp>cE_(z=iZNC8i*pXYEwn4+{rtD7}FP?AwN1q=$M zLnc}x)&dMZy~+{{<7Ka@@HdJk(4(^X<)fSs1UlRaKc6evqu8aVRk3tQQ!(5hMw5_X z{CQ;2oW9k9899ihI1vxw!6RiMry3_8wQyw`zLoNAmp%n#95 zZXx0cn83y)1Tz^(fn0+t4fNYJPBP43x`3oH54nq(NoyFvhUiN?b0g0LQ5YpEVUde6 z=NMu;%mi{$?4|{h>mBx#j#SQk%NDgPC<>6o&kS$Eq!QN1KOh811jQCEz9XBJIj_3S z&tn0Q1zI7~@@Wn^aODE0E)%8g+UzW8PIaj_O%*qT9Llalq2w@|=)$?ta&|lgSUQnE zvo`f)32`qLi8Bv&C!7W<{49}zlyKNa&FT;oy=NtiJh4rNM z5m6+Bh6KPA7)Wwzhq@y97zXoWA9sOAS8cFMs0<1xKnlh4$e!pjc#R|`oQBi-C)Qfd zLgEJ{(*+d(IQckD0fP`yI+9(b(5=A0BBN4`v7vIo*mM|2P;}RZuzn7Bgp(guYvp4j zv?O3u+8p9+QKS&-I%f_rKs8ayLa~^Kj0CY^z4Vygh&bW4r|VIJflTq~M4&^jL?KJ` zDy$B@!PaL>t2I7D16t#RKc6c6X-P6!zDh=a7(KX%fx?5CnIuq2t?n{}ldg||NiED^ zF+y0R)PtFTXBd7;jyOn|pP|SbFd%FqhdAe?wBzM5fFIyvk04l(Uu1pUG zG=G{rSk;L%iHu&hX_QVRi{Zzf@ngocx^q$X5NHu#8l?;qZFyRFl+@Z7*=Aaq$3_%8 zh$7V~i*kwS=Cyn;)f)Od4rN49vkGvpWR^dm1huhO2%_QEHN+{1a)- zdCBXagpDAPsI-AWB%nLYqXFG=eg!oD+G;VM^hf8847nuu%S#WHM<)GfP&`q7Y|+PE+|r!C1gndd!K0 zhm4k(JS<9dOyW|jUaGL>lqE@wn$hP^T@44NFFU)no@QgLQV;?^aa%DxlHp`*5+s60 zs2Ce_64(p_Pr0VHs1{K+Al9jPStssd2?kt%LJ=OeCxtZPLS|qzJmb(Hi6TTPD0ARY zsAy&@ZheZVU%(^4go>tM)Q$*1dk4t zh`9a|>Es`xM!2!i>dQ!Iq+3ZDDdLjyQn2BHF(mv`3lGU5i?vf+%5tW{m!V)|9N~d6kt1L{dE}Xl z89>r-dhMV?!{ZiaER-rakWZ4uRZK()2{YqdWbgvBKr2dEIOL{Bhs7Vg)YOBoW)x zd8*jVNC6=W8It_8fN^$m90`OmP_II%a69Ni$bkJD2F?tDM6ltu!HLSHK}wT2^ybIJ zGG~Yx5VR7VS8Vtb+Bq>JV?$;};*b{qymFC-1l!@JhpX8NurW~npaMDcYFQ{k5Z!Tb zSyZ0nz#$0f3CXl?kZVKUodh0~A>Jx1D7X@M2qbi$Qe$(q6kYcMk@?N0VIvVaf=3QvF)&I# zQNmELpc73crId?UT8kNjp(ra685rS|L`K==)^OmOqetk;U3PXWNTi554P;1UHb+)Q zV&_bfIS5@W0f{m8@C*{;=UV{ID5E|}xFu%+U<}eJe5eT}Ivq&Rr5_&)Fw8Q8(RQ~u zm?G8>eyT=#;g(j_3QlC4Qo)Li3HBFwk{tX560|Bk88DGIgp+a{1QRH8^Q2&bf5F+XM_h%zTag>sgWlYIUSA(l+3esOVh zF+~m(&7kOd<{vwJy08v6m))UPIU}s<4FF7zj8>S$U{Gr^_Kc9=Nfsxu#E&N76rNl` z7XXdZ=>vo~+;}=KsmK~OeKzwWPMk9%dCI|4@gao-J2l~{pH8Ct1?Llf-q5o{G1Cwc zl~pJlw0b0ai=4dE4&>+%awO=35^l_EY(^M{REb0g0C)j&C*>AMs5ueIQwfI$J}7~l zQ&9A(3u#cN^d%|+r&Q(wErTR}Qst5xNrpo)0~KaThh`~~k8yHuVB>@nna2)Zc*k(H zGs;&=L0k&2d6a()j1)yAzKmJm2!!M7D<6aqdO;$bj0({Vw6G^jppx9e$UJ5&&1M)J zCWMGE^o(vFwzDlsa9U{}Cgq$q?j`&AThpywg z2=FuG4C4zWLW~UxU*`l52pJwg5xgQY_h{BVQQV1T)YCRIj!=HO4z?ttJy41(*_}co0IfFwcIfbRt(?`S7#IIS}$Fj}DT)qsr|iz>cy gj*_|PQnm?-Sb6f)H(>)X+)sg!$>GT!kDYV>AClgjnE(I) diff --git a/Milestone6/axis_video_filter.vhd b/Milestone6/axis_video_filter.vhd index ba88d43..b810fee 100644 --- a/Milestone6/axis_video_filter.vhd +++ b/Milestone6/axis_video_filter.vhd @@ -61,19 +61,92 @@ architecture rtl of axis_video_filter is constant wRowProd : integer := wPixelSigned + wCoeff + 2; constant wFilterRes : integer := wRowProd+1 + 2; + signal m_valid_sig1 : std_logic; + signal m_valid_sig2 : std_logic; + signal m_last_sig1 : std_logic; + signal m_user_sig1 : std_logic; + + signal row1Result : signed(wRowProd-1 downto 0); + signal row2Result : signed(wRowProd-1 downto 0); + signal row3Result : signed(wRowProd-1 downto 0); + + signal coeff_11 : signed(wCoeff-1 downto 0); + signal coeff_12 : signed(wCoeff-1 downto 0); + signal coeff_13 : signed(wCoeff-1 downto 0); + signal coeff_21 : signed(wCoeff-1 downto 0); + signal coeff_22 : signed(wCoeff-1 downto 0); + signal coeff_23 : signed(wCoeff-1 downto 0); + signal coeff_31 : signed(wCoeff-1 downto 0); + signal coeff_32 : signed(wCoeff-1 downto 0); + signal coeff_33 : signed(wCoeff-1 downto 0); + + signal shiftAmount : unsigned(wShift-1 downto 0); + + begin - S_AXIS_TREADY <= M_AXIS_TREADY; + S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig1) or (not m_valid_sig2); ------------------------ --- Filter Kernel ------------------------ -process - -begin - -end process; + ----------------------- + -- Filter Kernel + ----------------------- + process + variable data_11 : signed (wPixelSigned-1 downto 0); + variable data_12 : signed (wPixelSigned-1 downto 0); + variable data_13 : signed (wPixelSigned-1 downto 0); + variable data_21 : signed (wPixelSigned-1 downto 0); + variable data_22 : signed (wPixelSigned-1 downto 0); + variable data_23 : signed (wPixelSigned-1 downto 0); + variable data_31 : signed (wPixelSigned-1 downto 0); + variable data_32 : signed (wPixelSigned-1 downto 0); + variable data_33 : signed (wPixelSigned-1 downto 0); + variable filterResult : signed (wFilterRes-1 downto 0); + + begin + wait until rising_edge (ACLK); + if ARESETN = '0' then + m_valid_sig1 <= '0'; + m_valid_sig2 <= '0'; + else + if M_AXIS_TREADY = '1' or m_valid_sig1='0' then + data_11 := data_12; + data_12 := data_13; + data_13 := signed("0"&S_AXIS_TDATA(wPixel*3-1 downto wPixel*2)); + data_21 := data_22; + data_22 := data_23; + data_23 := signed("0"&S_AXIS_TDATA(wPixel*2-1 downto wPixel*1)); + data_31 := data_32; + data_32 := data_33; + data_33 := signed("0"&S_AXIS_TDATA(wPixel*1-1 downto wPixel*0)); + + row1Result <= resize(data_11*coeff_11,wRowProd) + resize(data_12*coeff_12,wRowProd) + resize(data_13*coeff_13,wRowProd); + row2Result <= resize(data_21*coeff_21,wRowProd) + resize(data_22*coeff_22,wRowProd) + resize(data_23*coeff_23,wRowProd); + row3Result <= resize(data_31*coeff_31,wRowProd) + resize(data_32*coeff_32,wRowProd) + resize(data_33*coeff_33,wRowProd); + + m_last_sig1 <= S_AXIS_TLAST; + m_user_sig1 <= S_AXIS_TUSER(1); + m_valid_sig1 <= S_AXIS_TVALID; + end if; + + if M_AXIS_TREADY = '1' or m_valid_sig2='0' then + filterResult := resize(row1Result,wFilterRes)+resize(row2Result,wFilterRes)+resize(row3Result,wFilterRes); + filterResult := shift_right(filterResult, to_integer(shiftAmount)); + + if (filterResult < 0) then + filterResult := to_signed(0,wFilterRes); + elsif (filterResult > 255) then + filterResult := to_signed(255,wFilterRes); + end if; + + M_AXIS_TDATA <= std_logic_vector(filterResult(7 downto 0)); + M_AXIS_TVALID <= m_valid_sig1; + M_AXIS_TLAST <= m_last_sig1; + M_AXIS_TUSER <= m_user_sig1; + m_valid_sig2 <= m_valid_sig1; + end if; + end if; + end process; @@ -90,28 +163,70 @@ S_AXIL_RRESP <= "00"; process begin wait until rising_edge (ACLK); - + if ARESETN = '0' then S_AXIL_BVALID <= '0'; S_AXIL_RVALID <= '0'; + coeff_11 <= (others=>'0'); + coeff_12 <= (others=>'0'); + coeff_13 <= (others=>'0'); + coeff_21 <= (others=>'0'); + coeff_22 <= (0=>'1',others=>'0'); + coeff_23 <= (others=>'0'); + coeff_31 <= (others=>'0'); + coeff_32 <= (others=>'0'); + coeff_33 <= (others=>'0'); + shiftAmount <= to_unsigned(0,wShift); else if S_AXIL_RREADY = '1' then S_AXIL_RVALID <= '0'; end if; - + --Leselogik if S_AXIL_ARVALID = '1' then S_AXIL_RDATA <= (others=>'0'); + case (to_integer(unsigned(S_AXIL_ARADDR(5 downto 0)))) is + when 0 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_11); + when 4 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_12); + when 8 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_13); + when 12 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_21); + when 16 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_22); + when 20 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_23); + when 24 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_31); + when 28 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_32); + when 32 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_33); + when 36 => S_AXIL_RDATA <= (31 downto 4 => '0') & std_logic_vector(shiftAmount); + when others => null; + end case; S_AXIL_RVALID <= '1'; end if; if S_AXIL_BREADY = '1' then - S_AXIL_BVALID <= '0'; - end if; - - if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then S_AXIL_BVALID <= '1'; end if; + --schreiblogik + if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then + S_AXIL_BVALID <= '0'; + S_AXIL_RDATA <= (others=>'0'); + + if S_AXIL_WSTRB(0) = '1' then + case (to_integer(unsigned(S_AXIL_AWADDR(5 downto 0)))) is + when 0 => if S_AXIL_WSTRB(0) = '1' then coeff_11(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; + when 4 => if S_AXIL_WSTRB(0) = '1' then coeff_12(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; + when 8 => if S_AXIL_WSTRB(0) = '1' then coeff_13(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; + when 12 => if S_AXIL_WSTRB(0) = '1' then coeff_21(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; + when 16 => if S_AXIL_WSTRB(0) = '1' then coeff_22(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; + when 20 => if S_AXIL_WSTRB(0) = '1' then coeff_23(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; + when 24 => if S_AXIL_WSTRB(0) = '1' then coeff_31(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; + when 28 => if S_AXIL_WSTRB(0) = '1' then coeff_32(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; + when 32 => if S_AXIL_WSTRB(0) = '1' then coeff_33(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; + when 36 => if S_AXIL_WSTRB(0) = '1' then shiftAmount(3 downto 0) <= unsigned(S_AXIL_WDATA(3 downto 0)); end if; + when others => null; + end case; + end if; + end if; end if; end process; + + end; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml new file mode 100644 index 0000000..e3cc8f2 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml @@ -0,0 +1,57 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1_ooc.xdc b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1_ooc.xdc new file mode 100644 index 0000000..7fac2b2 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1_ooc.xdc @@ -0,0 +1,10 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ + +################################################################################ \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v new file mode 100644 index 0000000..eb16751 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v @@ -0,0 +1,93 @@ +//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +//Date : Tue Dec 10 00:45:24 2024 +//Host : Bastistablet running 64-bit major release (build 9200) +//Command : generate_target design_1_wrapper.bd +//Design : design_1_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module design_1_wrapper + (m_axi_lite_araddr, + m_axi_lite_arprot, + m_axi_lite_arready, + m_axi_lite_arvalid, + m_axi_lite_awaddr, + m_axi_lite_awprot, + m_axi_lite_awready, + m_axi_lite_awvalid, + m_axi_lite_bready, + m_axi_lite_bresp, + m_axi_lite_bvalid, + m_axi_lite_rdata, + m_axi_lite_rready, + m_axi_lite_rresp, + m_axi_lite_rvalid, + m_axi_lite_wdata, + m_axi_lite_wready, + m_axi_lite_wstrb, + m_axi_lite_wvalid); + output [31:0]m_axi_lite_araddr; + output [2:0]m_axi_lite_arprot; + input m_axi_lite_arready; + output m_axi_lite_arvalid; + output [31:0]m_axi_lite_awaddr; + output [2:0]m_axi_lite_awprot; + input m_axi_lite_awready; + output m_axi_lite_awvalid; + output m_axi_lite_bready; + input [1:0]m_axi_lite_bresp; + input m_axi_lite_bvalid; + input [31:0]m_axi_lite_rdata; + output m_axi_lite_rready; + input [1:0]m_axi_lite_rresp; + input m_axi_lite_rvalid; + output [31:0]m_axi_lite_wdata; + input m_axi_lite_wready; + output [3:0]m_axi_lite_wstrb; + output m_axi_lite_wvalid; + + wire [31:0]m_axi_lite_araddr; + wire [2:0]m_axi_lite_arprot; + wire m_axi_lite_arready; + wire m_axi_lite_arvalid; + wire [31:0]m_axi_lite_awaddr; + wire [2:0]m_axi_lite_awprot; + wire m_axi_lite_awready; + wire m_axi_lite_awvalid; + wire m_axi_lite_bready; + wire [1:0]m_axi_lite_bresp; + wire m_axi_lite_bvalid; + wire [31:0]m_axi_lite_rdata; + wire m_axi_lite_rready; + wire [1:0]m_axi_lite_rresp; + wire m_axi_lite_rvalid; + wire [31:0]m_axi_lite_wdata; + wire m_axi_lite_wready; + wire [3:0]m_axi_lite_wstrb; + wire m_axi_lite_wvalid; + + design_1 design_1_i + (.m_axi_lite_araddr(m_axi_lite_araddr), + .m_axi_lite_arprot(m_axi_lite_arprot), + .m_axi_lite_arready(m_axi_lite_arready), + .m_axi_lite_arvalid(m_axi_lite_arvalid), + .m_axi_lite_awaddr(m_axi_lite_awaddr), + .m_axi_lite_awprot(m_axi_lite_awprot), + .m_axi_lite_awready(m_axi_lite_awready), + .m_axi_lite_awvalid(m_axi_lite_awvalid), + .m_axi_lite_bready(m_axi_lite_bready), + .m_axi_lite_bresp(m_axi_lite_bresp), + .m_axi_lite_bvalid(m_axi_lite_bvalid), + .m_axi_lite_rdata(m_axi_lite_rdata), + .m_axi_lite_rready(m_axi_lite_rready), + .m_axi_lite_rresp(m_axi_lite_rresp), + .m_axi_lite_rvalid(m_axi_lite_rvalid), + .m_axi_lite_wdata(m_axi_lite_wdata), + .m_axi_lite_wready(m_axi_lite_wready), + .m_axi_lite_wstrb(m_axi_lite_wstrb), + .m_axi_lite_wvalid(m_axi_lite_wvalid)); +endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml new file mode 100644 index 0000000..deffabc --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml @@ -0,0 +1,1102 @@ + + + wg + customized_ip + design_1_axil_master_with_rom_0_0 + 1.0 + + + M_AXIL + + + + + + + + + AWADDR + + + M_AXIL_AWADDR + + + + + AWPROT + + + M_AXIL_AWPROT + + + + + AWVALID + + + M_AXIL_AWVALID + + + + + AWREADY + + + M_AXIL_AWREADY + + + + + WDATA + + + M_AXIL_WDATA + + + + + WSTRB + + + M_AXIL_WSTRB + + + + + WVALID + + + M_AXIL_WVALID + + + + + WREADY + + + M_AXIL_WREADY + + + + + BRESP + + + M_AXIL_BRESP + + + + + BVALID + + + M_AXIL_BVALID + + + + + BREADY + + + M_AXIL_BREADY + + + + + ARADDR + + + M_AXIL_ARADDR + + + + + ARPROT + + + M_AXIL_ARPROT + + + + + ARVALID + + + M_AXIL_ARVALID + + + + + ARREADY + + + M_AXIL_ARREADY + + + + + RDATA + + + M_AXIL_RDATA + + + + + RRESP + + + M_AXIL_RRESP + + + + + RVALID + + + M_AXIL_RVALID + + + + + RREADY + + + M_AXIL_RREADY + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + M_AXIL_ARESETN + + + + + + + RST + + + M_AXIL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + M_AXIL_ACLK + + + + + + + CLK + + + M_AXIL_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIL + + + ASSOCIATED_RESET + M_AXIL_ARESETN + + + FREQ_HZ + 100000000 + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + M_AXIL + M_AXIL + 0x100000000 + 32 + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axil_master_with_rom + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:9a9349f5 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_axil_master_with_rom_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:9a9349f5 + + + + + + + interrupt_in + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + finished_o + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + M_AXIL_ACLK + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_ARESETN + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + M_AXIL_ARREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIL_ARVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_ARADDR + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_ARPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_RREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_RVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIL_RDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIL_RRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIL_AWREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIL_AWVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_AWADDR + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_AWPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_WREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIL_WVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_WDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_WSTRB + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_BREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIL_BVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIL_BRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + STIM_FILENAME + Stim Filename + ../../stimuli.mem + + + HAS_FINISHED_OUT + Has Finished Out + false + + + HAS_INTERRUPT_IN + Has Interrupt In + false + + + REVISION_NO + Revision No + 1 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/85f6/sources_1/new/axilm_rom.vhd + vhdlSource + + + ../../ipshared/85f6/sources_1/new/axil_master_with_rom.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_axil_master_with_rom_0_0.vhd + vhdlSource + xil_defaultlib + + + + axil_master_with_rom + + + STIM_FILENAME + Stim Filename + ../../stimuli.mem + + + Component_Name + design_1_axil_master_with_rom_0_0 + + + HAS_FINISHED_OUT + Has Finished Out + false + + + HAS_INTERRUPT_IN + Has Interrupt In + false + + + REVISION_NO + Revision No + 1 + + + + + axil_master_with_rom + package_project + 19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/sim/design_1_axil_master_with_rom_0_0.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/sim/design_1_axil_master_with_rom_0_0.vhd new file mode 100644 index 0000000..7caa3c3 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/sim/design_1_axil_master_with_rom_0_0.vhd @@ -0,0 +1,177 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: wg:user:axil_master_with_rom:1.0 +-- IP Revision: 19 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_axil_master_with_rom_0_0 IS + PORT ( + M_AXIL_ACLK : IN STD_LOGIC; + M_AXIL_ARESETN : IN STD_LOGIC; + M_AXIL_ARREADY : IN STD_LOGIC; + M_AXIL_ARVALID : OUT STD_LOGIC; + M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXIL_RREADY : OUT STD_LOGIC; + M_AXIL_RVALID : IN STD_LOGIC; + M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXIL_AWREADY : IN STD_LOGIC; + M_AXIL_AWVALID : OUT STD_LOGIC; + M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXIL_WREADY : IN STD_LOGIC; + M_AXIL_WVALID : OUT STD_LOGIC; + M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXIL_BREADY : OUT STD_LOGIC; + M_AXIL_BVALID : IN STD_LOGIC; + M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0) + ); +END design_1_axil_master_with_rom_0_0; + +ARCHITECTURE design_1_axil_master_with_rom_0_0_arch OF design_1_axil_master_with_rom_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axil_master_with_rom IS + GENERIC ( + STIM_FILENAME : STRING; + HAS_FINISHED_OUT : BOOLEAN; + HAS_INTERRUPT_IN : BOOLEAN; + REVISION_NO : INTEGER + ); + PORT ( + interrupt_in : IN STD_LOGIC; + finished_o : OUT STD_LOGIC; + M_AXIL_ACLK : IN STD_LOGIC; + M_AXIL_ARESETN : IN STD_LOGIC; + M_AXIL_ARREADY : IN STD_LOGIC; + M_AXIL_ARVALID : OUT STD_LOGIC; + M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXIL_RREADY : OUT STD_LOGIC; + M_AXIL_RVALID : IN STD_LOGIC; + M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + M_AXIL_AWREADY : IN STD_LOGIC; + M_AXIL_AWVALID : OUT STD_LOGIC; + M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + M_AXIL_WREADY : IN STD_LOGIC; + M_AXIL_WVALID : OUT STD_LOGIC; + M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + M_AXIL_BREADY : OUT STD_LOGIC; + M_AXIL_BVALID : IN STD_LOGIC; + M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT axil_master_with_rom; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" & +"SERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID"; +BEGIN + U0 : axil_master_with_rom + GENERIC MAP ( + STIM_FILENAME => "../../stimuli.mem", + HAS_FINISHED_OUT => false, + HAS_INTERRUPT_IN => false, + REVISION_NO => 1 + ) + PORT MAP ( + interrupt_in => '0', + M_AXIL_ACLK => M_AXIL_ACLK, + M_AXIL_ARESETN => M_AXIL_ARESETN, + M_AXIL_ARREADY => M_AXIL_ARREADY, + M_AXIL_ARVALID => M_AXIL_ARVALID, + M_AXIL_ARADDR => M_AXIL_ARADDR, + M_AXIL_ARPROT => M_AXIL_ARPROT, + M_AXIL_RREADY => M_AXIL_RREADY, + M_AXIL_RVALID => M_AXIL_RVALID, + M_AXIL_RDATA => M_AXIL_RDATA, + M_AXIL_RRESP => M_AXIL_RRESP, + M_AXIL_AWREADY => M_AXIL_AWREADY, + M_AXIL_AWVALID => M_AXIL_AWVALID, + M_AXIL_AWADDR => M_AXIL_AWADDR, + M_AXIL_AWPROT => M_AXIL_AWPROT, + M_AXIL_WREADY => M_AXIL_WREADY, + M_AXIL_WVALID => M_AXIL_WVALID, + M_AXIL_WDATA => M_AXIL_WDATA, + M_AXIL_WSTRB => M_AXIL_WSTRB, + M_AXIL_BREADY => M_AXIL_BREADY, + M_AXIL_BVALID => M_AXIL_BVALID, + M_AXIL_BRESP => M_AXIL_BRESP + ); +END design_1_axil_master_with_rom_0_0_arch; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xml new file mode 100644 index 0000000..3fdffbd --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xml @@ -0,0 +1,779 @@ + + + xilinx.com + customized_ip + design_1_axis_downsizer_0_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TUSER + + + M_AXIS_TUSER + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TUSER + + + S_AXIS_TUSER + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXIS_ARESETN + + + + + + + RST + + + AXIS_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXIS_ACLK + + + + + + + CLK + + + AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS + + + ASSOCIATED_RESET + AXIS_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_downsizer + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:b4dbaa33 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_axis_downsizer_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:b4dbaa33 + + + + + + + AXIS_ACLK + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + AXIS_ARESETN + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TUSER + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + M_AXIS_TUSER + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + + + WIDTH_OUT + Width Out + 8 + + + SIZE_FACTOR + Size Factor + 4 + + + BIG_ENDIAN + Big Endian + false + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/9185/sources_1/new/axis_downsizer.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_axis_downsizer_0_0.vhd + vhdlSource + xil_defaultlib + + + + axis_downsizer_v1_0 + + + WIDTH_OUT + Width Out + 8 + + + SIZE_FACTOR + Size Factor + 4 + + + BIG_ENDIAN + Big Endian + false + + + Component_Name + design_1_axis_downsizer_0_0 + + + + + axis_downsizer_v1_0 + package_project + 2 + + d:/projekte/edvs/vivado/vivado/ip_projects/axis_downsizer/axis_downsizer.srcs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/sim/design_1_axis_downsizer_0_0.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/sim/design_1_axis_downsizer_0_0.vhd new file mode 100644 index 0000000..580252c --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/sim/design_1_axis_downsizer_0_0.vhd @@ -0,0 +1,136 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:user:axis_downsizer:1.0 +-- IP Revision: 2 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_axis_downsizer_0_0 IS + PORT ( + AXIS_ACLK : IN STD_LOGIC; + AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC + ); +END design_1_axis_downsizer_0_0; + +ARCHITECTURE design_1_axis_downsizer_0_0_arch OF design_1_axis_downsizer_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_downsizer_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_downsizer IS + GENERIC ( + WIDTH_OUT : INTEGER; + SIZE_FACTOR : INTEGER; + BIG_ENDIAN : BOOLEAN + ); + PORT ( + AXIS_ACLK : IN STD_LOGIC; + AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC + ); + END COMPONENT axis_downsizer; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_downsizer + GENERIC MAP ( + WIDTH_OUT => 8, + SIZE_FACTOR => 4, + BIG_ENDIAN => false + ) + PORT MAP ( + AXIS_ACLK => AXIS_ACLK, + AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TUSER => S_AXIS_TUSER, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TUSER => M_AXIS_TUSER + ); +END design_1_axis_downsizer_0_0_arch; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xml new file mode 100644 index 0000000..0739695 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xml @@ -0,0 +1,896 @@ + + + xilinx.com + customized_ip + design_1_axis_linemem_single_0_0 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + TDATA_NUM_BYTES + 3 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 3 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TUSER + + + s_axis_tuser + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_linemem_single_master + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:c744c730 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_axis_linemem_single_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:c744c730 + + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + s_axis_tdata + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tlast + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tuser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tlast + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + m_axis_tuser + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + + + MAX_LINELEN + Max Linelen + 2048 + + + NUM_LINES + Num Lines + 3 + + + DATA_WIDTH + Data Width + 8 + + + TUSER_WIDTH + Tuser Width + 1 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/9ba2/sources_1/new/bmem_dp.vhd + vhdlSource + + + ../../ipshared/9ba2/sources_1/new/axis_linemem_single_master.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_axis_linemem_single_0_0.vhd + vhdlSource + xil_defaultlib + + + + axis_linemem_single_master_v1_0 + + + MAX_LINELEN + Max Linelen + 2048 + + + NUM_LINES + Num Lines + 3 + + + DATA_WIDTH + Data Width + 8 + + + TUSER_WIDTH + Tuser Width + 1 + + + Component_Name + design_1_axis_linemem_single_0_0 + + + + + axis_linemem_single_master_v1_0 + 17 + + D:/Projekte/edvs/vivado/vivado/ip_projects/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/sim/design_1_axis_linemem_single_0_0.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/sim/design_1_axis_linemem_single_0_0.vhd new file mode 100644 index 0000000..410d4d1 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/sim/design_1_axis_linemem_single_0_0.vhd @@ -0,0 +1,138 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:user:axis_linemem_single_master:1.0 +-- IP Revision: 17 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_axis_linemem_single_0_0 IS + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC; + s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s_axis_tlast : IN STD_LOGIC; + s_axis_tready : OUT STD_LOGIC; + s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_tvalid : OUT STD_LOGIC; + m_axis_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + m_axis_tlast : OUT STD_LOGIC; + m_axis_tready : IN STD_LOGIC; + m_axis_tuser : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END design_1_axis_linemem_single_0_0; + +ARCHITECTURE design_1_axis_linemem_single_0_0_arch OF design_1_axis_linemem_single_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_linemem_single_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_linemem_single_master IS + GENERIC ( + MAX_LINELEN : INTEGER; + NUM_LINES : INTEGER; + DATA_WIDTH : INTEGER; + TUSER_WIDTH : INTEGER + ); + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC; + s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s_axis_tlast : IN STD_LOGIC; + s_axis_tready : OUT STD_LOGIC; + s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_tvalid : OUT STD_LOGIC; + m_axis_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + m_axis_tlast : OUT STD_LOGIC; + m_axis_tready : IN STD_LOGIC; + m_axis_tuser : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); + END COMPONENT axis_linemem_single_master; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF m_axis:s_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_tvalid: SIGNAL IS "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 3, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_tvalid: SIGNAL IS "XIL_INTERFACENAME s_axis, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TVALID"; +BEGIN + U0 : axis_linemem_single_master + GENERIC MAP ( + MAX_LINELEN => 2048, + NUM_LINES => 3, + DATA_WIDTH => 8, + TUSER_WIDTH => 1 + ) + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + s_axis_tvalid => s_axis_tvalid, + s_axis_tdata => s_axis_tdata, + s_axis_tlast => s_axis_tlast, + s_axis_tready => s_axis_tready, + s_axis_tuser => s_axis_tuser, + m_axis_tvalid => m_axis_tvalid, + m_axis_tdata => m_axis_tdata, + m_axis_tlast => m_axis_tlast, + m_axis_tready => m_axis_tready, + m_axis_tuser => m_axis_tuser + ); +END design_1_axis_linemem_single_0_0_arch; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xml new file mode 100644 index 0000000..a22dd0d --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xml @@ -0,0 +1,738 @@ + + + Gehrke + customized_ip + design_1_axis_master_simmodel_0_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TUSER + + + M_AXIS_TUSER + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + signal_reset + + + + + + + RST + + + ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + signal_clock + + + + + + + CLK + + + ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS + + + ASSOCIATED_RESET + ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_master_simmodel + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:82169cab + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_axis_master_simmodel_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:82169cab + + + + + + + ACLK + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + ARESETN + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + FINISHED + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TUSER + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_NUM_FREE + + in + + 10 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + + + DATA_WIDTH + Data Width + 32 + + + HAS_FIFO_INTERFACE + Has Fifo Interface + false + + + FIFO_AWIDTH + Fifo Awidth + 11 + + + FIFO_REQUEST_TRESHOLD + Fifo Request Treshold + 32 + + + TUSERWIDTH + Tuserwidth + 1 + + + FILE_NAME + File Name + ../../../../Moewe-192x192 + + + FILE_EXTENSION + File Extension + bmp + + + FILE_AUTONUMBERING + File Autonumbering + false + + + NUM_PIX_PER_LINE + Num Pix Per Line + 192 + + + NUM_LINES + Num Lines + 192 + + + NUM_FRAMES_PER_FILE + Num Frames Per File + 1 + + + RANDOM_TVALID + Random Tvalid + true + + + PIXEL_FORMAT + Pixel Format + 13 + + + ALPHA_VALUE + Alpha Value + 255 + + + FRAMING_PIXELS + Framing Pixels + 0 + + + FRAMING_LINES + Framing Lines + 0 + + + FRAMING_VAL_R_V + Framing Val R V + 128 + + + FRAMING_VAL_G_Y + Framing Val G Y + 128 + + + FRAMING_VAL_B_U + Framing Val B U + 128 + + + + + + choice_list_91f15632 + bmp + yuv + bin + raw + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/d44d/bmp_pkg.vhd + vhdlSource + + + ../../ipshared/d44d/axis_master_simmodel.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_axis_master_simmodel_0_0.vhd + vhdlSource + xil_defaultlib + + + + axis_master_simmodel + + + FRAMING_VAL_B_U + Framing Val B U + 128 + + + FRAMING_VAL_G_Y + Framing Val G Y + 128 + + + FRAMING_VAL_R_V + Framing Val R V + 128 + + + FRAMING_LINES + Framing Lines + 0 + + + FRAMING_PIXELS + Framing Pixels + 0 + + + ALPHA_VALUE + Alpha Value + 255 + + + PIXEL_FORMAT + Pixel Format + 13 + + + RANDOM_TVALID + Random Tvalid + true + + + NUM_FRAMES_PER_FILE + Num Frames Per File + 1 + + + NUM_LINES + Num Lines + 192 + + + NUM_PIX_PER_LINE + Num Pix Per Line + 192 + + + FILE_AUTONUMBERING + File Autonumbering + false + + + FILE_EXTENSION + File Extension + bmp + + + FILE_NAME + File Name + ../../../../Moewe-192x192 + + + TUSERWIDTH + Tuserwidth + 1 + + + FIFO_REQUEST_TRESHOLD + Fifo Request Treshold + 32 + + + FIFO_AWIDTH + Fifo Awidth + 11 + + + HAS_FIFO_INTERFACE + Has Fifo Interface + false + + + Component_Name + Component Name + design_1_axis_master_simmodel_0_0 + + + + + axis_master_simmodel + 10 + + D:/Projekte/edvs/vivado/ip_projects/axis_master_simmodel/axis_master_simmodel.srcs/sources_1/new + D:/Projekte/edvs/vivado/ip_projects/axis_master_simmodel/axis_master_simmodel.srcs/sources_1/new + D:/Projekte/edvs/vivado/ip_projects/axis_master_simmodel/axis_master_simmodel.srcs/sources_1/new + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2015.2 + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/sim/design_1_axis_master_simmodel_0_0.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/sim/design_1_axis_master_simmodel_0_0.vhd new file mode 100644 index 0000000..960fa8f --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/sim/design_1_axis_master_simmodel_0_0.vhd @@ -0,0 +1,152 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: Gehrke:user:axis_master_simmodel:1.0 +-- IP Revision: 10 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_axis_master_simmodel_0_0 IS + PORT ( + ACLK : IN STD_LOGIC; + ARESETN : IN STD_LOGIC; + FINISHED : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END design_1_axis_master_simmodel_0_0; + +ARCHITECTURE design_1_axis_master_simmodel_0_0_arch OF design_1_axis_master_simmodel_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_master_simmodel_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_master_simmodel IS + GENERIC ( + DATA_WIDTH : INTEGER; + HAS_FIFO_INTERFACE : BOOLEAN; + FIFO_AWIDTH : INTEGER; + FIFO_REQUEST_TRESHOLD : INTEGER; + TUSERWIDTH : INTEGER; + FILE_NAME : STRING; + FILE_EXTENSION : STRING; + FILE_AUTONUMBERING : BOOLEAN; + NUM_PIX_PER_LINE : INTEGER; + NUM_LINES : INTEGER; + NUM_FRAMES_PER_FILE : INTEGER; + RANDOM_TVALID : BOOLEAN; + PIXEL_FORMAT : INTEGER; + ALPHA_VALUE : INTEGER; + FRAMING_PIXELS : INTEGER; + FRAMING_LINES : INTEGER; + FRAMING_VAL_R_V : INTEGER; + FRAMING_VAL_G_Y : INTEGER; + FRAMING_VAL_B_U : INTEGER + ); + PORT ( + ACLK : IN STD_LOGIC; + ARESETN : IN STD_LOGIC; + FINISHED : OUT STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + M_AXIS_NUM_FREE : IN STD_LOGIC_VECTOR(10 DOWNTO 0) + ); + END COMPONENT axis_master_simmodel; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; +BEGIN + U0 : axis_master_simmodel + GENERIC MAP ( + DATA_WIDTH => 32, + HAS_FIFO_INTERFACE => false, + FIFO_AWIDTH => 11, + FIFO_REQUEST_TRESHOLD => 32, + TUSERWIDTH => 1, + FILE_NAME => "../../../../Moewe-192x192", + FILE_EXTENSION => "bmp", + FILE_AUTONUMBERING => false, + NUM_PIX_PER_LINE => 192, + NUM_LINES => 192, + NUM_FRAMES_PER_FILE => 1, + RANDOM_TVALID => true, + PIXEL_FORMAT => 13, + ALPHA_VALUE => 255, + FRAMING_PIXELS => 0, + FRAMING_LINES => 0, + FRAMING_VAL_R_V => 128, + FRAMING_VAL_G_Y => 128, + FRAMING_VAL_B_U => 128 + ) + PORT MAP ( + ACLK => ACLK, + ARESETN => ARESETN, + FINISHED => FINISHED, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_NUM_FREE => STD_LOGIC_VECTOR(TO_UNSIGNED(1, 11)) + ); +END design_1_axis_master_simmodel_0_0_arch; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xml new file mode 100644 index 0000000..a671ca0 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xml @@ -0,0 +1,642 @@ + + + Gehrke + customized_ip + design_1_axis_slave_simmodel_0_0 + 1.0 + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TUSER + + + S_AXIS_TUSER + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS_signal_reset + + + + + + + RST + + + S_AXIS_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS_signal_clock + + + + + + + CLK + + + S_AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXIS + + + ASSOCIATED_RESET + S_AXIS_ARESETN + + + FREQ_HZ + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_slave_simmodel + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:ff3fc857 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_axis_slave_simmodel_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:ff3fc857 + + + + + + + FINISHED + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_ACLK + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_ARESETN + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TUSER + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + + + + + TUSERWIDTH + Tuserwidth + 1 + + + FILE_NAME + File Name + ../../../../tst_out + + + FILE_EXTENSION + File Extension + bmp + + + FILE_AUTONUMBERING + File Autonumbering + false + + + PIXEL_FORMAT + Pixel Format + 13 + + + NUM_PIX_PER_LINE + Num Pix Per Line + 192 + + + NUM_LINES + Num Lines + 192 + + + NUM_FRAMES_PER_FILE + Num Frames Per File + 1 + + + NUM_FILES + Num Files + 1 + + + FRAMING_PIXELS + Framing Pixels + 0 + + + FRAMING_LINES + Framing Lines + 0 + + + RANDOM_TREADY + Random Tready + true + + + + + + choice_list_91f15632 + bmp + yuv + bin + raw + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/c453/bmp_pkg.vhd + vhdlSource + + + ../../ipshared/c453/axis_slave_simmodel.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_axis_slave_simmodel_0_0.vhd + vhdlSource + xil_defaultlib + + + + axis_slave_simmodel_v1_0 + + + RANDOM_TREADY + Random Tready + true + + + FRAMING_LINES + Framing Lines + 0 + + + FRAMING_PIXELS + Framing Pixels + 0 + + + NUM_FILES + Num Files + 1 + + + NUM_FRAMES_PER_FILE + Num Frames Per File + 1 + + + NUM_LINES + Num Lines + 192 + + + NUM_PIX_PER_LINE + Num Pix Per Line + 192 + + + PIXEL_FORMAT + Pixel Format + 13 + + + FILE_AUTONUMBERING + File Autonumbering + false + + + FILE_EXTENSION + File Extension + bmp + + + FILE_NAME + File Name + ../../../../tst_out + + + TUSERWIDTH + Tuserwidth + 1 + + + Component_Name + Component Name + design_1_axis_slave_simmodel_0_0 + + + + + axis_slave_simmodel_v1_0 + 4 + + D:/Projekte/edvs/vivado/ip_projects/axis_slave_simmodel/axis_slave_simmodel.srcs/sources_1/new + D:/Projekte/edvs/vivado/ip_projects/axis_slave_simmodel/axis_slave_simmodel.srcs/sources_1/new + D:/Projekte/edvs/vivado/ip_projects/axis_slave_simmodel/axis_slave_simmodel.srcs/sources_1/new + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/sim/design_1_axis_slave_simmodel_0_0.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/sim/design_1_axis_slave_simmodel_0_0.vhd new file mode 100644 index 0000000..7d0ace0 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/sim/design_1_axis_slave_simmodel_0_0.vhd @@ -0,0 +1,136 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: Gehrke:user:axis_slave_simmodel:1.0 +-- IP Revision: 4 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_axis_slave_simmodel_0_0 IS + PORT ( + FINISHED : OUT STD_LOGIC; + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END design_1_axis_slave_simmodel_0_0; + +ARCHITECTURE design_1_axis_slave_simmodel_0_0_arch OF design_1_axis_slave_simmodel_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_slave_simmodel_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_slave_simmodel IS + GENERIC ( + TUSERWIDTH : INTEGER; + FILE_NAME : STRING; + FILE_EXTENSION : STRING; + FILE_AUTONUMBERING : BOOLEAN; + PIXEL_FORMAT : INTEGER; + NUM_PIX_PER_LINE : INTEGER; + NUM_LINES : INTEGER; + NUM_FRAMES_PER_FILE : INTEGER; + NUM_FILES : INTEGER; + FRAMING_PIXELS : INTEGER; + FRAMING_LINES : INTEGER; + RANDOM_TREADY : BOOLEAN + ); + PORT ( + FINISHED : OUT STD_LOGIC; + S_AXIS_ACLK : IN STD_LOGIC; + S_AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT axis_slave_simmodel; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_slave_simmodel + GENERIC MAP ( + TUSERWIDTH => 1, + FILE_NAME => "../../../../tst_out", + FILE_EXTENSION => "bmp", + FILE_AUTONUMBERING => false, + PIXEL_FORMAT => 13, + NUM_PIX_PER_LINE => 192, + NUM_LINES => 192, + NUM_FRAMES_PER_FILE => 1, + NUM_FILES => 1, + FRAMING_PIXELS => 0, + FRAMING_LINES => 0, + RANDOM_TREADY => true + ) + PORT MAP ( + FINISHED => FINISHED, + S_AXIS_ACLK => S_AXIS_ACLK, + S_AXIS_ARESETN => S_AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TUSER => S_AXIS_TUSER + ); +END design_1_axis_slave_simmodel_0_0_arch; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xml new file mode 100644 index 0000000..197e1d4 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xml @@ -0,0 +1,795 @@ + + + xilinx.com + customized_ip + design_1_axis_upsizer_0_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TUSER + + + M_AXIS_TUSER + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TUSER + + + S_AXIS_TUSER + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXIS_ARESETN + + + + + + + RST + + + AXIS_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXIS_ACLK + + + + + + + CLK + + + AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS + + + ASSOCIATED_RESET + AXIS_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_upsizer + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:8a86da2c + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_axis_upsizer_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:8a86da2c + + + + + + + AXIS_ACLK + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + AXIS_ARESETN + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TUSER + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + M_AXIS_TUSER + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + + + WIDTH_IN + Width In + 8 + + + SIZE_FACTOR + Size Factor + 4 + + + BIG_ENDIAN + Big Endian + false + + + + + + choice_list_552a89ba + 2 + 4 + 8 + 16 + + + choice_list_5f2cf65b + 1 + 8 + 16 + 32 + 64 + 128 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/dfd1/sources_1/new/axis_upsizer.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_axis_upsizer_0_0.vhd + vhdlSource + xil_defaultlib + + + + axis_upsizer_v1_0 + + + WIDTH_IN + Width In + 8 + + + SIZE_FACTOR + Size Factor + 4 + + + BIG_ENDIAN + Big Endian + false + + + Component_Name + design_1_axis_upsizer_0_0 + + + + + axis_upsizer_v1_0 + package_project + 3 + + d:/Projekte/edvs/vivado/vivado/ip_projects/axis_upsizer/axis_upsizer.srcs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/sim/design_1_axis_upsizer_0_0.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/sim/design_1_axis_upsizer_0_0.vhd new file mode 100644 index 0000000..2906e0b --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/sim/design_1_axis_upsizer_0_0.vhd @@ -0,0 +1,136 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:user:axis_upsizer:1.0 +-- IP Revision: 3 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_axis_upsizer_0_0 IS + PORT ( + AXIS_ACLK : IN STD_LOGIC; + AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC + ); +END design_1_axis_upsizer_0_0; + +ARCHITECTURE design_1_axis_upsizer_0_0_arch OF design_1_axis_upsizer_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_upsizer_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axis_upsizer IS + GENERIC ( + WIDTH_IN : INTEGER; + SIZE_FACTOR : INTEGER; + BIG_ENDIAN : BOOLEAN + ); + PORT ( + AXIS_ACLK : IN STD_LOGIC; + AXIS_ARESETN : IN STD_LOGIC; + S_AXIS_TVALID : IN STD_LOGIC; + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXIS_TLAST : IN STD_LOGIC; + S_AXIS_TREADY : OUT STD_LOGIC; + S_AXIS_TUSER : IN STD_LOGIC; + M_AXIS_TVALID : OUT STD_LOGIC; + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + M_AXIS_TLAST : OUT STD_LOGIC; + M_AXIS_TREADY : IN STD_LOGIC; + M_AXIS_TUSER : OUT STD_LOGIC + ); + END COMPONENT axis_upsizer; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK"; + ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER"; + ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; +BEGIN + U0 : axis_upsizer + GENERIC MAP ( + WIDTH_IN => 8, + SIZE_FACTOR => 4, + BIG_ENDIAN => false + ) + PORT MAP ( + AXIS_ACLK => AXIS_ACLK, + AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TUSER => S_AXIS_TUSER, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TUSER => M_AXIS_TUSER + ); +END design_1_axis_upsizer_0_0_arch; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xml new file mode 100644 index 0000000..75eff95 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xml @@ -0,0 +1,1473 @@ + + + xilinx.com + customized_ip + design_1_axis_video_filter_0_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TUSER + + + M_AXIS_TUSER + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 1 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TUSER + + + S_AXIS_TUSER + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + TDATA_NUM_BYTES + 3 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 3 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S_AXIL + + + + + + + + + AWADDR + + + S_AXIL_AWADDR + + + + + AWVALID + + + S_AXIL_AWVALID + + + + + AWREADY + + + S_AXIL_AWREADY + + + + + WDATA + + + S_AXIL_WDATA + + + + + WSTRB + + + S_AXIL_WSTRB + + + + + WVALID + + + S_AXIL_WVALID + + + + + WREADY + + + S_AXIL_WREADY + + + + + BRESP + + + S_AXIL_BRESP + + + + + BVALID + + + S_AXIL_BVALID + + + + + BREADY + + + S_AXIL_BREADY + + + + + ARADDR + + + S_AXIL_ARADDR + + + + + ARVALID + + + S_AXIL_ARVALID + + + + + ARREADY + + + S_AXIL_ARREADY + + + + + RDATA + + + S_AXIL_RDATA + + + + + RRESP + + + S_AXIL_RRESP + + + + + RVALID + + + S_AXIL_RVALID + + + + + RREADY + + + S_AXIL_RREADY + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 15 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + ARESETN + + + + + + + RST + + + ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + ACLK + + + + + + + CLK + + + ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS:S_AXIL + + + ASSOCIATED_RESET + ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + S_AXIL + S_AXIL + + reg0 + reg0 + 0x0 + 0x8000 + 32 + register + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + axis_video_filter + + + outputProductCRC + 9:c39d825f + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + design_1_axis_video_filter_0_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Dec 09 23:45:24 UTC 2024 + + + outputProductCRC + 9:c39d825f + + + + + + + ACLK + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + ARESETN + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIS_TDATA + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TUSER + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + M_AXIS_TUSER + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_AWADDR + + in + + 14 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_AWVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIL_AWREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_WVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIL_WREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_BVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_BREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + S_AXIL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_ARADDR + + in + + 14 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_ARVALID + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIL_ARREADY + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_RVALID + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_RREADY + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + S_AXIL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagebehavioralsimulation + + + + + + + + COEFF_WIDTH + Coeff Width + 8 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_axis_video_filter_0_0.v + verilogSource + xil_defaultlib + + + + xilinx.com:module_ref:axis_video_filter:1.0 + + + COEFF_WIDTH + Coeff Width + 8 + + + Component_Name + design_1_axis_video_filter_0_0 + + + + + axis_video_filter_v1_0 + module_ref + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/sim/design_1_axis_video_filter_0_0.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/sim/design_1_axis_video_filter_0_0.v new file mode 100644 index 0000000..9a12f5f --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/sim/design_1_axis_video_filter_0_0.v @@ -0,0 +1,187 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:module_ref:axis_video_filter:1.0 +// IP Revision: 1 + +`timescale 1ns/1ps + +(* IP_DEFINITION_SOURCE = "module_ref" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_axis_video_filter_0_0 ( + ACLK, + ARESETN, + S_AXIS_TVALID, + S_AXIS_TDATA, + S_AXIS_TLAST, + S_AXIS_TREADY, + S_AXIS_TUSER, + M_AXIS_TVALID, + M_AXIS_TDATA, + M_AXIS_TLAST, + M_AXIS_TREADY, + M_AXIS_TUSER, + S_AXIL_AWADDR, + S_AXIL_AWVALID, + S_AXIL_AWREADY, + S_AXIL_WDATA, + S_AXIL_WVALID, + S_AXIL_WREADY, + S_AXIL_WSTRB, + S_AXIL_BVALID, + S_AXIL_BREADY, + S_AXIL_BRESP, + S_AXIL_ARADDR, + S_AXIL_ARVALID, + S_AXIL_ARREADY, + S_AXIL_RDATA, + S_AXIL_RVALID, + S_AXIL_RREADY, + S_AXIL_RRESP +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:S_AXIL, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ACLK CLK" *) +input wire ACLK; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ARESETN RST" *) +input wire ARESETN; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) +input wire S_AXIS_TVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) +input wire [23 : 0] S_AXIS_TDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) +input wire S_AXIS_TLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) +output wire S_AXIS_TREADY; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 3, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) +input wire [2 : 0] S_AXIS_TUSER; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) +output wire M_AXIS_TVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) +output wire [7 : 0] M_AXIS_TDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) +output wire M_AXIS_TLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) +input wire M_AXIS_TREADY; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) +output wire M_AXIS_TUSER; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR" *) +input wire [14 : 0] S_AXIL_AWADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID" *) +input wire S_AXIL_AWVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY" *) +output wire S_AXIL_AWREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WDATA" *) +input wire [31 : 0] S_AXIL_WDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WVALID" *) +input wire S_AXIL_WVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WREADY" *) +output wire S_AXIL_WREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB" *) +input wire [3 : 0] S_AXIL_WSTRB; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL BVALID" *) +output wire S_AXIL_BVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL BREADY" *) +input wire S_AXIL_BREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL BRESP" *) +output wire [1 : 0] S_AXIL_BRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR" *) +input wire [14 : 0] S_AXIL_ARADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID" *) +input wire S_AXIL_ARVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY" *) +output wire S_AXIL_ARREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RDATA" *) +output wire [31 : 0] S_AXIL_RDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RVALID" *) +output wire S_AXIL_RVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RREADY" *) +input wire S_AXIL_RREADY; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\ +BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RRESP" *) +output wire [1 : 0] S_AXIL_RRESP; + + axis_video_filter #( + .COEFF_WIDTH(8) + ) inst ( + .ACLK(ACLK), + .ARESETN(ARESETN), + .S_AXIS_TVALID(S_AXIS_TVALID), + .S_AXIS_TDATA(S_AXIS_TDATA), + .S_AXIS_TLAST(S_AXIS_TLAST), + .S_AXIS_TREADY(S_AXIS_TREADY), + .S_AXIS_TUSER(S_AXIS_TUSER), + .M_AXIS_TVALID(M_AXIS_TVALID), + .M_AXIS_TDATA(M_AXIS_TDATA), + .M_AXIS_TLAST(M_AXIS_TLAST), + .M_AXIS_TREADY(M_AXIS_TREADY), + .M_AXIS_TUSER(M_AXIS_TUSER), + .S_AXIL_AWADDR(S_AXIL_AWADDR), + .S_AXIL_AWVALID(S_AXIL_AWVALID), + .S_AXIL_AWREADY(S_AXIL_AWREADY), + .S_AXIL_WDATA(S_AXIL_WDATA), + .S_AXIL_WVALID(S_AXIL_WVALID), + .S_AXIL_WREADY(S_AXIL_WREADY), + .S_AXIL_WSTRB(S_AXIL_WSTRB), + .S_AXIL_BVALID(S_AXIL_BVALID), + .S_AXIL_BREADY(S_AXIL_BREADY), + .S_AXIL_BRESP(S_AXIL_BRESP), + .S_AXIL_ARADDR(S_AXIL_ARADDR), + .S_AXIL_ARVALID(S_AXIL_ARVALID), + .S_AXIL_ARREADY(S_AXIL_ARREADY), + .S_AXIL_RDATA(S_AXIL_RDATA), + .S_AXIL_RVALID(S_AXIL_RVALID), + .S_AXIL_RREADY(S_AXIL_RREADY), + .S_AXIL_RRESP(S_AXIL_RRESP) + ); +endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml new file mode 100644 index 0000000..714a1bc --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml @@ -0,0 +1,226 @@ + + + wg + customized_ip + design_1_clk_rst_generator_0_0 + 1.0 + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + clk_rst_generator + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:deff16df + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_clk_rst_generator_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Dec 09 23:02:04 UTC 2024 + + + outputProductCRC + 9:deff16df + + + + + + + clk_in + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + rst_in + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + clk + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + rst_n + + out + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + + + stop_simulation + + in + + + std_logic + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + + + CLOCK_PERIOD + Clock Period + 10000 + + + HAS_CLK_INPUT + Has Clk Input + false + + + HAS_RESET_INPUT + Has Reset Input + false + + + HAS_STOP_INPUT + Has Stop Input + true + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_clk_rst_generator_0_0.vhd + vhdlSource + xil_defaultlib + + + + clk_rst_generator + + + CLOCK_PERIOD + Clock Period [ps] + 10000 + + + HAS_CLK_INPUT + Clock Input + false + + + HAS_RESET_INPUT + Reset Input + false + + + HAS_STOP_INPUT + Stop Input + true + + + Component_Name + design_1_clk_rst_generator_0_0 + + + + + clk_rst_generator + package_project + 7 + + + + + + + 2023.1 + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/sim/design_1_clk_rst_generator_0_0.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/sim/design_1_clk_rst_generator_0_0.vhd new file mode 100644 index 0000000..ff03053 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/sim/design_1_clk_rst_generator_0_0.vhd @@ -0,0 +1,97 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: wg:user:clk_rst_generator:1.0 +-- IP Revision: 7 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_clk_rst_generator_0_0 IS + PORT ( + clk : OUT STD_LOGIC; + rst_n : OUT STD_LOGIC; + stop_simulation : IN STD_LOGIC + ); +END design_1_clk_rst_generator_0_0; + +ARCHITECTURE design_1_clk_rst_generator_0_0_arch OF design_1_clk_rst_generator_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT clk_rst_generator IS + GENERIC ( + CLOCK_PERIOD : INTEGER; + HAS_CLK_INPUT : BOOLEAN; + HAS_RESET_INPUT : BOOLEAN; + HAS_STOP_INPUT : BOOLEAN + ); + PORT ( + clk_in : IN STD_LOGIC; + rst_in : IN STD_LOGIC; + clk : OUT STD_LOGIC; + rst_n : OUT STD_LOGIC; + stop_simulation : IN STD_LOGIC + ); + END COMPONENT clk_rst_generator; +BEGIN + U0 : clk_rst_generator + GENERIC MAP ( + CLOCK_PERIOD => 10000, + HAS_CLK_INPUT => false, + HAS_RESET_INPUT => false, + HAS_STOP_INPUT => true + ) + PORT MAP ( + clk_in => '1', + rst_in => '0', + clk => clk, + rst_n => rst_n, + stop_simulation => stop_simulation + ); +END design_1_clk_rst_generator_0_0_arch; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/85f6/sources_1/new/axil_master_with_rom.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/85f6/sources_1/new/axil_master_with_rom.vhd new file mode 100644 index 0000000..4e5d37f --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/85f6/sources_1/new/axil_master_with_rom.vhd @@ -0,0 +1,285 @@ +------------------------------------------------------------------------------ +-- axil_master_with_rom.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2024 +---------------------------------------------------------- + +-- AXIL-Master +-- +-- Transactions des Masters werden durch ein ladbares ROM definiert +-- Die Inhalte des ROMs werden aus einer Datei geladen und bei Synthese und Simulation verwendet +-- Das ROM besitzt eine Wortbreite von 40 bit +-- Für einen Befehl werden 1 bis 2 Worte verwendet +-- Nur 'wal' verwendet 2 40 - Bit - Worte +-- +-- Die Codierung ist nachfolgend dargestellt : +-- command wal : <39 : 8> Adresse <3 : 0> Befehl(wal = 1) +-- <39 : 8> Daten <3 : 0> Befehl WStrobe +-- command ral : <39 : 8> Adresse <3 : 0> Befehl(ral = 2) +-- command wfi : Befehl(wfi = 6) +-- command ral : <15 : 8> Wartezyklen <3 : 0> Befehl(slp = 7) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity axil_master_with_rom is + generic + ( + HAS_INTERRUPT_IN : boolean := true; + HAS_FINISHED_OUT : boolean := false; + REVISION_NO : integer := 1; + STIM_FILENAME : string := "../../stimuli.mem" + ); + port + ( + interrupt_in : in std_logic:='0'; + finished_o : out std_logic; + + M_AXIL_ACLK : in std_logic; + M_AXIL_ARESETN : in std_logic; + + M_AXIL_ARREADY : in std_logic; + M_AXIL_ARVALID : out std_logic; + M_AXIL_ARADDR : out std_logic_vector(31 downto 0); + M_AXIL_ARPROT : out std_logic_vector(2 downto 0); + M_AXIL_RREADY : out std_logic; + M_AXIL_RVALID : in std_logic; + M_AXIL_RDATA : in std_logic_vector(31 downto 0); + M_AXIL_RRESP : in std_logic_vector(1 downto 0); + M_AXIL_AWREADY : in std_logic; + M_AXIL_AWVALID : out std_logic; + M_AXIL_AWADDR : out std_logic_vector(31 downto 0); + M_AXIL_AWPROT : out std_logic_vector(2 downto 0); + M_AXIL_WREADY : in std_logic; + M_AXIL_WVALID : out std_logic; + M_AXIL_WDATA : out std_logic_vector(31 downto 0); + M_AXIL_WSTRB : out std_logic_vector(3 downto 0); + M_AXIL_BREADY : out std_logic; + M_AXIL_BVALID : in std_logic; + M_AXIL_BRESP : in std_logic_vector(1 downto 0) + ); + +end; + + +architecture rtl of axil_master_with_rom is + + + type TSTATE is (INIT,INIT_WAIT, + GET_COMMAND, + WR_ADDR,WR_ADDR_WAIT1,WR_ADDR_WAIT2,WR_DATA,WR_DATA_WAIT,WR_RESP, + RD_ADDR,RD_DATA, + WAIT_FOR_INT, + SLEEP,SLEEP_WAIT, + FINISHED + ); + + signal state : TSTATE := INIT; + + constant ADDR_WIDTH_CMD_ROM : integer := 12; + + signal mdata : std_logic_vector(39 downto 0); + signal maddr : std_logic_vector(ADDR_WIDTH_CMD_ROM-1 downto 0); + +begin + +cmdrom : entity work.axilm_rom + generic map ( + FILENAME => STIM_FILENAME, + DW => 40, + AW => ADDR_WIDTH_CMD_ROM + ) + port map ( + clk => M_AXIL_ACLK, + a => maddr, + q => mdata + ); + + +process + variable cnt8 : unsigned( 7 downto 0); + variable cnt32 : unsigned(31 downto 0); + variable addr_accepted : boolean; + variable data_accepted : boolean; + + begin + wait until rising_edge(M_AXIL_ACLK); + + if M_AXIL_ARESETN = '0' then + state <= INIT; + M_AXIL_ARVALID <= '0'; + M_AXIL_ARADDR <= (others=>'X'); + M_AXIL_ARPROT <= (others=>'0'); + M_AXIL_RREADY <= '0'; + M_AXIL_AWVALID <= '0'; + M_AXIL_AWADDR <= (others=>'X'); + M_AXIL_AWPROT <= (others=>'0'); + M_AXIL_WVALID <= '0'; + M_AXIL_WDATA <= (others=>'X'); + M_AXIL_WSTRB <= (others=>'X'); + M_AXIL_BREADY <= '0'; + finished_o <= '0'; + else + case state is + + ---- + -- Init + ---- + when INIT => + finished_o <= '0'; + cnt8 := x"10"; + maddr <= (others=>'0'); + M_AXIL_ARVALID <= '0'; + M_AXIL_ARADDR <= (others=>'X'); + M_AXIL_ARPROT <= (others=>'0'); + M_AXIL_RREADY <= '0'; + M_AXIL_AWVALID <= '0'; + M_AXIL_AWADDR <= (others=>'X'); + M_AXIL_AWPROT <= (others=>'0'); + M_AXIL_WVALID <= '0'; + M_AXIL_WDATA <= (others=>'X'); + M_AXIL_WSTRB <= (others=>'X'); + M_AXIL_BREADY <= '0'; + state <= INIT_WAIT; + + when INIT_WAIT => + cnt8 := cnt8 - 1; + if cnt8 = 0 then + state <= GET_COMMAND; + end if; + + when GET_COMMAND => + case (mdata(3 downto 0)) is + when x"0" => state <= FINISHED; + when x"1" => state <= WR_ADDR; + when x"2" => state <= RD_ADDR; + when x"6" => state <= WAIT_FOR_INT; + when x"7" => state <= SLEEP; + when others => maddr <= std_logic_vector(unsigned(maddr) + 1); + end case; + + + ---- + -- Write + ---- + when WR_ADDR => + M_AXIL_AWVALID <= '1'; + M_AXIL_AWADDR <= mdata(39 downto 8); + M_AXIL_ARVALID <= '0'; + M_AXIL_ARADDR <= (others => 'X'); + maddr <= std_logic_vector(unsigned(maddr) + 1); + addr_accepted := false; + data_accepted := false; + state <= WR_ADDR_WAIT1; + when WR_ADDR_WAIT1 => + if (M_AXIL_AWREADY = '1') then + M_AXIL_AWVALID <= '0'; + addr_accepted := true; + end if; + state <= WR_ADDR_WAIT2; + when WR_ADDR_WAIT2 => + if (M_AXIL_AWREADY = '1') then + M_AXIL_AWVALID <= '0'; + addr_accepted := true; + end if; + state <= WR_DATA; + when WR_DATA => + if (M_AXIL_AWREADY = '1') then + M_AXIL_AWVALID <= '0'; + addr_accepted := true; + end if; + M_AXIL_WSTRB <= mdata( 3 downto 0); + M_AXIL_WDATA <= mdata(39 downto 8); + M_AXIL_WVALID <= '1'; + state <= WR_DATA_WAIT; + when WR_DATA_WAIT => + if (M_AXIL_AWREADY = '1') then + M_AXIL_AWVALID <= '0'; + addr_accepted := true; + end if; + if (M_AXIL_WREADY = '1') then + M_AXIL_WVALID <= '0'; + data_accepted := true; + end if; + + if (addr_accepted and data_accepted) then + maddr <= std_logic_vector(unsigned(maddr) + 1); + M_AXIL_AWVALID <= '0'; + M_AXIL_WSTRB <= (others=>'X'); + M_AXIL_WDATA <= (others=>'X'); + M_AXIL_WVALID <= '0'; + M_AXIL_BREADY <= '1'; + state <= WR_RESP; + end if; + when WR_RESP => + if M_AXIL_BVALID = '1' then + M_AXIL_BREADY <= '0'; + state <= GET_COMMAND; + end if; + + + ---- + -- Read + ---- + when RD_ADDR => + M_AXIL_ARVALID <= '1'; + M_AXIL_ARADDR <= mdata(39 downto 8); + M_AXIL_AWVALID <= 'X'; + M_AXIL_AWADDR <= (others => 'X'); + M_AXIL_RREADY <= '1'; + addr_accepted := false; + state <= RD_DATA; + when RD_DATA => + if (M_AXIL_ARREADY = '1') then + M_AXIL_ARVALID <= '0'; + addr_accepted := true; + end if; + if (M_AXIL_RVALID = '1') then + M_AXIL_RREADY <= '0'; + data_accepted := true; + end if; + if (addr_accepted and data_accepted) then + maddr <= std_logic_vector(unsigned(maddr) + 1); + M_AXIL_ARVALID <= '0'; + M_AXIL_RREADY <= '0'; + M_AXIL_ARADDR <= (others => 'X'); + state <= GET_COMMAND; + end if; + + when WAIT_FOR_INT => + if (interrupt_in = '1') then + maddr <= std_logic_vector(unsigned(maddr) + 1); + state <= GET_COMMAND; + end if; + + when SLEEP => + cnt32 := unsigned(mdata(39 downto 8)); + -- synthesis translate_off + cnt32 := x"0000"&unsigned(mdata(39 downto 24)); -- fuer Simulation Wartezeit um 65536 verringern + -- synthesis translate_on + maddr <= std_logic_vector(unsigned(maddr) + 1); + state <= SLEEP_WAIT; + + when SLEEP_WAIT => + if (cnt32 /= 0) then + cnt32 := cnt32 - 1; + else + state <= GET_COMMAND; + end if; + + when FINISHED => + finished_o <= '1'; + + + end case; + + end if; + +end process; + + +end; \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/85f6/sources_1/new/axilm_rom.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/85f6/sources_1/new/axilm_rom.vhd new file mode 100644 index 0000000..da5b605 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/85f6/sources_1/new/axilm_rom.vhd @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------ +-- axilm_rom.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2024 +---------------------------------------------------------- + +-- ref. https://docs.amd.com/r/en-US/ug901-vivado-synthesis/VHDL-Code-Example + +use std.textio.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; + +entity axilm_rom is + + generic ( + FILENAME : string; + DW : integer; -- Data Width + AW : integer -- Address Width + ); + port ( + clk : in std_logic; -- Clock + a : in std_logic_vector(AW-1 downto 0); -- Address + q : out std_logic_vector(DW-1 downto 0) -- Data out port +); +end; + + +architecture rtl of axilm_rom is + type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0); + + impure function InitMemFromFile(MemFileName : in string) return tmem is + FILE MemFile : text is in MemFileName; + variable MemFileLine : line; + variable mem : tmem; + begin + for i in tmem'range loop + readline(MemFile, MemFileLine); + read(MemFileLine, mem(i)); + end loop; + return mem; + end function; + + constant mem : tmem := InitMemFromFile( + -- synthesis translate_off + "../../" & + -- synthesis translate_on + FILENAME); + +begin + process + begin + wait until rising_edge(clk); + q <= mem(to_integer(unsigned(a))); + end process; +end; + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9185/sources_1/new/axis_downsizer.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9185/sources_1/new/axis_downsizer.vhd new file mode 100644 index 0000000..ae3adc1 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9185/sources_1/new/axis_downsizer.vhd @@ -0,0 +1,94 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axis_downsizer is + generic + ( + WIDTH_OUT : integer := 8; + SIZE_FACTOR : integer := 2; + BIG_ENDIAN : boolean := false + ); + + port + ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + + -- AXIS SLAVE + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(WIDTH_OUT*SIZE_FACTOR-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TUSER : in std_logic; + + -- AXIS Master + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(WIDTH_OUT-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TUSER : out std_logic + ); +end; + + +architecture rtl of axis_downsizer is + type T_STATE is (BYTE0,BYTE1); + signal state : T_STATE := BYTE0; + signal last : std_logic; + signal data : std_logic_vector(WIDTH_OUT*SIZE_FACTOR-1 downto 0); + signal ui : unsigned(5 downto 0); +begin + S_AXIS_TREADY <= M_AXIS_TREADY when state = BYTE0 else '0'; + M_AXIS_TVALID <= S_AXIS_TVALID when state = BYTE0 else '1'; + M_AXIS_TLAST <= last when ui = to_unsigned(SIZE_FACTOR-1,6) else '0'; + M_AXIS_TUSER <= S_AXIS_TUSER when state = BYTE0 else '0'; + + + process (S_AXIS_TDATA, ui) + variable i: integer; + begin + i := to_integer(ui); + if BIG_ENDIAN then + if ui = 0 then + M_AXIS_TDATA <= S_AXIS_TDATA(WIDTH_OUT*SIZE_FACTOR-1 downto WIDTH_OUT*(SIZE_FACTOR-1)); + else + M_AXIS_TDATA <= data(WIDTH_OUT*(SIZE_FACTOR-i)-1 downto WIDTH_OUT*(SIZE_FACTOR-i-1)); + end if; + else + if ui = 0 then + M_AXIS_TDATA <= S_AXIS_TDATA(WIDTH_OUT-1 downto 0); + else + M_AXIS_TDATA <= data(WIDTH_OUT*(i+1)-1 downto WIDTH_OUT*i); + end if; + end if; + end process; + + process + begin + wait until rising_edge (AXIS_ACLK); + if AXIS_ARESETN = '0' then + state <= BYTE0; + else + case state is + when BYTE0 => + if S_AXIS_TVALID = '1' and M_AXIS_TREADY='1' then + last <= S_AXIS_TLAST; + data <= S_AXIS_TDATA; + ui <= to_unsigned(1,6); + state <= BYTE1; + end if; + when BYTE1 => + if M_AXIS_TREADY='1' then + if ui >= SIZE_FACTOR-1 then + state <= BYTE0; + ui <= to_unsigned(0,6); + else + ui <= ui+1; + end if; + end if; + end case; + end if; + end process; + +end; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd new file mode 100644 index 0000000..eb80819 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd @@ -0,0 +1,114 @@ +------------------------------------------------------------------------------ +-- clk_rst_generator.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2024 +---------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity clk_rst_generator is + generic + ( + CLOCK_PERIOD : integer := 10000; + HAS_CLK_INPUT : boolean := true; + HAS_RESET_INPUT : boolean := true; + HAS_STOP_INPUT : boolean := true + ); + port + ( + clk_in : in std_logic := '1'; + rst_in : in std_logic := '0'; + + clk : out std_logic; + rst_n : out std_logic; + + stop_simulation : in std_logic := '0' + ); + +end; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture rtl of clk_rst_generator is + + signal clk_sim : std_logic := '1'; + signal clk_in_sig : std_logic := '1'; + signal clk_sig : std_logic := '1'; + signal rst_sig : std_logic := '0'; + signal rst_in_sync : std_logic := '0'; + +begin + clk <= clk_sig; + rst_n <= not rst_sig; + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- CLOCK GENERATION + --------------------------------------------------------------- + --------------------------------------------------------------- + + clk_sig <= clk_in_sig and clk_sim; + -- Dies ist kein gated Clock! + -- Fuer die Synthese ist clk_sim konstant '1' + -- somit wird die UND-Verknuepfung 'wegoptimiert' + -- und was übrig bleibt, ist ein 'Draht' + + -- synthesis translate_off + clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2; + assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note; + assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note; + assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note; + -- synthesis translate_on + + process (clk_in) begin + clk_in_sig <= clk_in; + -- synthesis translate_off + clk_in_sig <= '1'; + -- synthesis translate_on + end process; + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- RESET GENERATION + --------------------------------------------------------------- + --------------------------------------------------------------- + + process + variable rescnt : unsigned (6 downto 0) := (others=>'1'); + begin + wait until rising_edge(clk_sig); + + rst_in_sync <= rst_in; + if rst_in_sync = '1' then + rescnt := (others=>'1'); + end if; + + if rescnt = 0 then + rst_sig <= '0'; + else + rescnt := rescnt - 1; + rst_sig <= '1'; + end if; + end process; + + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- STOP SIMULATION INPUT (simulation only) + --------------------------------------------------------------- + --------------------------------------------------------------- + + -- synthesis translate_off + process (stop_simulation) begin + if stop_simulation = '1' then + assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure; + end if; + end process; + -- synthesis translate_on + +end rtl; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9ba2/sources_1/new/axis_linemem_single_master.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9ba2/sources_1/new/axis_linemem_single_master.vhd new file mode 100644 index 0000000..1fbe22a --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9ba2/sources_1/new/axis_linemem_single_master.vhd @@ -0,0 +1,150 @@ +------------------------------------------------------------------------------ +-- axis_linemem_single_master.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2013/2014/2015/2016 +---------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; -- required for log2() + +entity axis_linemem_single_master is + generic + ( + MAX_LINELEN : integer := 2048; + NUM_LINES : integer := 3; + DATA_WIDTH : integer := 32; + TUSER_WIDTH : integer := 1 + ); + port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- AXI Streaming Target Port + s_axis_tvalid : in std_logic := '0'; + s_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + s_axis_tlast : in std_logic := '0'; + s_axis_tready : out std_logic; + s_axis_tuser : in std_logic_vector(TUSER_WIDTH-1 downto 0); + + -- AXI Streaming Initiator Port + + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(NUM_LINES*DATA_WIDTH-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tready : in std_logic := '1'; + m_axis_tuser : out std_logic_vector(NUM_LINES*TUSER_WIDTH-1 downto 0) + ); +end; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture rtl of axis_linemem_single_master is + + constant TUSER_OFFS : integer := (NUM_LINES-1)*DATA_WIDTH; + constant LOG2_MAX_LINELEN : integer := integer(ceil(log2(real(MAX_LINELEN)))); + + signal enable : std_logic; + signal zero : std_logic_vector((NUM_LINES-1)*(DATA_WIDTH+TUSER_WIDTH)-1 downto 0) := (others=>'0'); + signal rdaddr : std_logic_vector(LOG2_MAX_LINELEN-1 downto 0); + signal rdaddrReg : std_logic_vector(LOG2_MAX_LINELEN-1 downto 0); + signal rdaddrInc : std_logic_vector(LOG2_MAX_LINELEN-1 downto 0); + signal rddata : std_logic_vector((NUM_LINES-1)*(DATA_WIDTH+TUSER_WIDTH)-1 downto 0); + signal wraddr : std_logic_vector(LOG2_MAX_LINELEN-1 downto 0); + signal wren : std_logic; + signal wrdata : std_logic_vector((NUM_LINES-1)*(DATA_WIDTH+TUSER_WIDTH)-1 downto 0); + + signal tuser_reg : std_logic_vector(TUSER_WIDTH-1 downto 0); + signal tdata_reg : std_logic_vector(DATA_WIDTH-1 downto 0); + signal tlast_reg : std_logic; + signal tvalid_reg : std_logic; + signal m_valid_sig : std_logic := '0'; + +begin + + enable <= s_axis_tvalid and (m_axis_tready or (not m_valid_sig)); + + s_axis_tready <= enable; + + rdaddr <= (others=>'0') when s_axis_tlast = '1' and s_axis_tvalid = '1' + else rdaddrInc when enable='1' + else rdaddrReg; + + -- asynchronous feedback of data read from and written to memory + wrdata((NUM_LINES-1)*DATA_WIDTH-1 downto 0) <= rddata((NUM_LINES-2)*DATA_WIDTH-1 downto 0) & tdata_reg; + wrdata((NUM_LINES-1)*TUSER_WIDTH-1+TUSER_OFFS downto TUSER_OFFS) <= rddata((NUM_LINES-2)*TUSER_WIDTH-1+TUSER_OFFS downto TUSER_OFFS) & tuser_reg; + + + process begin + wait until rising_edge(aclk); + if aresetn = '0' then + m_valid_sig <= '0'; + m_axis_tvalid <= '0'; + m_axis_tlast <= '0'; + m_axis_tdata <= (others=>'0'); + m_axis_tuser <= (others=>'0'); + tlast_reg <= '0'; + tuser_reg <= (others=>'0'); + tdata_reg <= (others=>'0'); + tvalid_reg <= '0'; + rdaddrReg <= (others=>'1'); -- entspricht -1 + rdaddrInc <= (others=>'0'); + wraddr <= (others=>'0'); + wren <= '0'; + else + wren <= enable; + wraddr <= rdaddr; + rdaddrReg <= rdaddr; + rdaddrInc <= std_logic_vector(unsigned(rdaddr)+1); + + if m_axis_tready = '1' then -- falls Daten übernommen wurden, valid auf 0 setzen + m_valid_sig <= '0'; + m_axis_tvalid <= '0'; + end if; + + if enable = '1' then + tvalid_reg <= s_axis_tvalid; + tdata_reg <= s_axis_tdata; + tuser_reg <= s_axis_tuser; + tlast_reg <= s_axis_tlast; + + m_valid_sig <= tvalid_reg; + m_axis_tvalid <= tvalid_reg; + m_axis_tlast <= tlast_reg; + m_axis_tdata <= rddata((NUM_LINES-1)*DATA_WIDTH-1 downto 0) & tdata_reg; + m_axis_tuser <= rddata((NUM_LINES-1)*TUSER_WIDTH-1+TUSER_OFFS downto TUSER_OFFS) & tuser_reg; + end if; + + end if; + end process; + + + + dpmem : entity work.bmem_dp + generic map( + DW => (NUM_LINES-1)*(DATA_WIDTH+TUSER_WIDTH), -- Data Width + AW => LOG2_MAX_LINELEN -- Address Width + ) + port map( + -- Port 1 + clk1 => aclk, -- Clock + en1 => enable, -- Enable + a1 => rdaddr, -- Address + d1 => zero, -- Data in + we1 => '0', -- Write enable + q1 => rddata, -- Data out port + -- Port 2 + clk2 => aclk, -- Clock + en2 => '1', -- Enable + a2 => wraddr, -- Address + d2 => wrdata, -- Data in + we2 => wren, -- Write enable + q2 => open -- Data out port (not used) + ); + + end rtl; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9ba2/sources_1/new/bmem_dp.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9ba2/sources_1/new/bmem_dp.vhd new file mode 100644 index 0000000..035bb69 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/9ba2/sources_1/new/bmem_dp.vhd @@ -0,0 +1,78 @@ +-------------------------------------------------------------------------- +-- +-- Dual-ported Synchronous Memory (Block Memory) +-- +-- Prof. Dr.-Ing. W. Gehrke (c) 2011 +-- +-------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity bmem_dp is + + generic ( + DW : integer := 16; -- Data Width + AW : integer := 10 -- Address Width + ); + port ( + -- Port 1 + clk1 : in std_logic; -- Clock + en1 : in std_logic; -- Enable + a1 : in std_logic_vector(AW-1 downto 0); -- Address + d1 : in std_logic_vector(DW-1 downto 0); -- Data in + we1 : in std_logic; -- Write enable + q1 : out std_logic_vector(DW-1 downto 0); -- Data out port + + -- Port 2 + clk2 : in std_logic; -- Clock + en2 : in std_logic; -- Enable + a2 : in std_logic_vector(AW-1 downto 0); -- Address + d2 : in std_logic_vector(DW-1 downto 0); -- Data in + we2 : in std_logic; -- Write enable + q2 : out std_logic_vector(DW-1 downto 0) -- Data out port + + ); +end; + + +architecture rtl of bmem_dp is + + type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0); + shared variable mem : tmem := ((others=> (others=>'0'))); + + signal q1_sig : std_logic_vector(DW-1 downto 0) := (others=>'0'); + signal q2_sig : std_logic_vector(DW-1 downto 0) := (others=>'0'); + +begin + q1 <= q1_sig; + q2 <= q2_sig; + + -- Port 1 + process (clk1) + begin + if (clk1'event and clk1 = '1') then + if (en1 = '1') then + if (we1 = '1') then + mem(to_integer(unsigned(a1))) := d1; + end if; + q1_sig <= mem(to_integer(unsigned(a1))); + end if; + end if; + end process; + + -- Port 2 + process (clk2) + begin + if (clk2'event and clk2 = '1') then + if (en2 = '1') then + if (we2 = '1') then + mem(to_integer(unsigned(a2))) := d2; + end if; + q2_sig <= mem(to_integer(unsigned(a2))); + end if; + end if; + end process; + +end; \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/c453/axis_slave_simmodel.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/c453/axis_slave_simmodel.vhd new file mode 100644 index 0000000..b08fbf6 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/c453/axis_slave_simmodel.vhd @@ -0,0 +1,317 @@ +------------------------------------------------------------------------------ +-- axis_slave_simmodel.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2013 +---------------------------------------------------------- + +use std.textio.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.bmp_pkg.all; + + +entity axis_slave_simmodel is + generic + ( + TUSERWIDTH : integer := 1; + FILE_NAME : string := string'("tst_out"); + FILE_EXTENSION : string := string'("bmp"); + FILE_AUTONUMBERING : boolean := false; + PIXEL_FORMAT : integer := 1; + NUM_PIX_PER_LINE : integer := 128; + NUM_LINES : integer := 128; + NUM_FRAMES_PER_FILE : integer := 1; + NUM_FILES : integer := 1; + FRAMING_PIXELS : integer := 0; + FRAMING_LINES : integer := 0; + RANDOM_TREADY : boolean := true +); + port + ( + FINISHED : out std_logic; + S_AXIS_ACLK : in std_logic; + S_AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TUSER : in std_logic_vector(TUSERWIDTH-1 downto 0) + ); + +end entity axis_slave_simmodel; + + +architecture sim of axis_slave_simmodel is + + signal rnd : unsigned (31 downto 0) := x"DEADBEEF"; + signal local_clk : std_logic; + +begin + + local_clk <= S_AXIS_ACLK after 10 ps; + +-- synthesis translate_off +-- translate off + + -- uint32_t xorshift32() { + -- static uint32_t x = 314159265; + -- x ^= x << 13; + -- x ^= x >> 17; + -- x ^= x << 5; + -- return x; + -- } + process + variable r : unsigned (31 downto 0); + begin + wait until rising_edge(local_clk); + r := rnd; + r := r xor (r(18 downto 0)& x"000"&"0"); + r := r xor (x"0000"&"0"&r(31 downto 17)); + r := r xor (r(26 downto 0)& "00000"); + rnd <= r; + end process; + + process + + variable file_num : integer := 0; + variable is_bmp_file: boolean; + variable is_yuv_file: boolean; + + variable r : integer; + variable g : integer; + variable b : integer; + + variable y1 : integer; + variable u1 : integer; + variable v1 : integer; + variable y2 : integer; + variable u2 : integer; + variable v2 : integer; + + variable delay_cnt : integer; + variable tready_cnt : integer := 31415; + + file f : BMP_FILE_TYPE; + + variable file_status : file_open_status; + + variable x : integer; + variable pixels_per_beat : integer; + + + type rgbyuv is record + r : integer; + g : integer; + b : integer; + y : integer; + u : integer; + v : integer; + end record; + type tarr1 is array(0 to NUM_PIX_PER_LINE-1) of rgbyuv; + type tarr2 is array(0 to NUM_LINES-1) of tarr1; + variable pix : tarr2; + + type t_pixel_data is array(0 to 3) of rgbyuv; + variable p : t_pixel_data; + + type t_raw_data is array(0 to 3) of integer; + variable raw_data : t_raw_data; + + begin + wait until rising_edge(local_clk); + if (S_AXIS_ARESETN = '0') then + S_AXIS_TREADY <= '0'; + FINISHED <= '0'; + tready_cnt := to_integer(rnd and x"0000001F"); + else + S_AXIS_TREADY <= '1'; + + -- Check if output file is in BMP format + is_bmp_file := false; + is_yuv_file := false; + if (FILE_EXTENSION = "BMP") or (FILE_EXTENSION = "bmp") then + is_bmp_file := true; + elsif (FILE_EXTENSION = "YUV") or (FILE_EXTENSION = "yuv") then + is_yuv_file := true; + end if; + + case PIXEL_FORMAT is + when 0 => pixels_per_beat := 2; + when 1|5 => pixels_per_beat := 1; + when 2|6 => pixels_per_beat := 1; + when 12 => pixels_per_beat := 1; + when 13 => pixels_per_beat := 4; + when others => pixels_per_beat := 4; + end case; + + + for files in 0 to NUM_FILES-1 loop -- file loop + + -- Create filename and try to open the file + if FILE_AUTONUMBERING then + file_open ( file_status, f, FILE_NAME & "_" & integer'image(file_num) & "." & FILE_EXTENSION, write_mode); + else + file_open ( file_status, f, FILE_NAME & "." & FILE_EXTENSION, write_mode); + end if; + + file_num := file_num + 1; -- increase filenum idx + if is_bmp_file then + write_bmp_header(NUM_PIX_PER_LINE,NUM_LINES,f); + end if; + + for fr in 0 to NUM_FRAMES_PER_FILE-1 loop -- frame loop + + -- wait for start of frame + while S_AXIS_TVALID /= '1' or S_AXIS_TUSER(0) /= '1' loop + wait until rising_edge (local_clk); + end loop; + + for y in 0 to NUM_LINES+2*FRAMING_LINES-1 loop + x := 0; + while x < NUM_PIX_PER_LINE+2*FRAMING_PIXELS loop + + -- wait for valid data + while S_AXIS_TVALID /= '1' loop + wait until rising_edge (local_clk); + end loop; + + -- "active" pixel area ? + if (y >= FRAMING_LINES) and (y < FRAMING_LINES+NUM_LINES) and + (x >= FRAMING_PIXELS) and (x < FRAMING_PIXELS+NUM_PIX_PER_LINE) then + + if is_bmp_file or is_yuv_file then -- bmp format or yuv format ? + case PIXEL_FORMAT is + when 0 => + p(1).y := to_integer(unsigned(S_AXIS_TDATA(31 downto 24))); + p(1).v := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(0).v := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(0).y := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(1).u := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + p(0).u := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b); + yuv2rgb(p(1).y,p(1).u,p(1).v,p(1).r,p(1).g,p(1).b); + when 1|5 => + p(0).v := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(0).u := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b); + when 2|6 => + p(0).r := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(0).b := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(0).g := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + rgb2yuv(p(0).r,p(0).g,p(0).b,p(0).y,p(0).u,p(0).v); + when 12 => + p(0).v := 128; + p(0).u := 128; + p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b); + when 13 => + p(3).y := to_integer(unsigned(S_AXIS_TDATA(31 downto 24))); + p(3).v := 128; + p(3).u := 128; + p(2).y := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(2).v := 128; + p(2).u := 128; + p(1).y := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(1).v := 128; + p(1).u := 128; + p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + p(0).v := 128; + p(0).u := 128; + yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b); + yuv2rgb(p(1).y,p(1).u,p(1).v,p(1).r,p(1).g,p(1).b); + yuv2rgb(p(2).y,p(2).u,p(2).v,p(2).r,p(2).g,p(2).b); + yuv2rgb(p(3).y,p(3).u,p(3).v,p(3).r,p(3).g,p(3).b); + when others => + p(3).y := to_integer(unsigned(S_AXIS_TDATA(31 downto 24))); + p(3).v := 128; + p(3).u := 128; + p(2).y := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + p(2).v := 128; + p(2).u := 128; + p(1).y := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + p(1).v := 128; + p(1).u := 128; + p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + p(0).v := 128; + p(0).u := 128; + end case; + else -- raw format + raw_data(3) := to_integer(unsigned(S_AXIS_TDATA(31 downto 24))); + raw_data(2) := to_integer(unsigned(S_AXIS_TDATA(23 downto 16))); + raw_data(1) := to_integer(unsigned(S_AXIS_TDATA(15 downto 8))); + raw_data(0) := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))); + end if; + + if is_bmp_file or is_yuv_file then -- bmp format or yuv format ? + for xi in 0 to pixels_per_beat-1 loop + pix(y-FRAMING_LINES)(x+xi-FRAMING_PIXELS) := p(xi); + end loop; + x := x+pixels_per_beat; + else + bmpput8(raw_data(0),f); + bmpput8(raw_data(1),f); + bmpput8(raw_data(2),f); + bmpput8(raw_data(3),f); + end if; + end if; + + tready_cnt := tready_cnt - 1; + if RANDOM_TREADY and tready_cnt <= 0 then + -- random TREADY delay + delay_cnt := to_integer(rnd and x"00000007"); + while delay_cnt > 0 loop + S_AXIS_TREADY <= '0'; + delay_cnt := delay_cnt - 1; + wait until rising_edge (local_clk); + tready_cnt := to_integer(rnd and x"0000001F"); + end loop; + end if; + + S_AXIS_TREADY <= '1'; + wait until rising_edge (local_clk); + + end loop; -- hor loop (x) + end loop; -- ver loop (y) + if is_bmp_file then -- bmp format ? + for y in NUM_LINES-1 downto 0 loop + for x in 0 to NUM_PIX_PER_LINE-1 loop + write_bmp_pixel(pix(y)(x).r,pix(y)(x).g,pix(y)(x).b,f); + end loop; + end loop; + end if; + if is_bmp_file then -- yuv format ? + for y in NUM_LINES-1 downto 0 loop + for x in 0 to NUM_PIX_PER_LINE/2-1 loop + bmpput8(pix(y)(2*x).u,f); + bmpput8(pix(y)(2*x).y,f); + bmpput8(pix(y)(2*x).v,f); + bmpput8(pix(y)(2*x+1).y,f); + end loop; + end loop; + end if; + end loop; -- frame loop (fr) + file_close(f); + end loop; -- files loop (files) + + + FINISHED <= '1'; + S_AXIS_TREADY <= '0'; + + -- wait until reset is activated + while S_AXIS_ARESETN = '1' loop + wait until rising_edge (local_clk); + end loop; + + end if; + end process; + +-- synthesis translate_on +-- translate on + + +end sim; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/c453/bmp_pkg.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/c453/bmp_pkg.vhd new file mode 100644 index 0000000..874ba32 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/c453/bmp_pkg.vhd @@ -0,0 +1,207 @@ + +use std.textio.all; + +package bmp_pkg is + + type BMP_FILE_TYPE is file of character; + + procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ); + procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ); + procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ); + procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ); + procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ); + + function bmpget8 (file f : BMP_FILE_TYPE ) return integer; + function bmpget16 (file f : BMP_FILE_TYPE ) return integer; + function bmpget32 (file f : BMP_FILE_TYPE ) return integer; + procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ); + procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ); + procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ); + procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ); + procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ); + +end; + +package body bmp_pkg is + +procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + write(f, character'val(value)); +end bmpput8; + +procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8((value) mod 256,f); + bmpput8((value/256) mod 256,f); +end bmpput16; + +procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8((value) mod 256,f); + bmpput8((value/256) mod 256,f); + bmpput8((value/256/256) mod 256,f); + bmpput8((value/256/256/256) mod 256,f); +end bmpput32; + + +procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ) is +begin + write(f,'B'); + write(f,'M'); + bmpput32(54+sizex*sizey*3,f); -- bfSize : size of file (unsave) + bmpput32( 0, f); -- bfReserved : always 0 + bmpput32(54, f); -- bfOffBits : image data offset (=54) + bmpput32(40, f); -- biSize : header size (=40) + bmpput32(sizex,f); -- biWidth : num horizontal pixel + bmpput32(sizey,f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap) + bmpput16( 1, f); -- biPlanes : num bitplanes, always 1 + bmpput16(24, f); -- biBitCount : bpp + bmpput32( 0, f); -- biCompression : compression (0: uncompressed) + bmpput32(3*sizex*sizey,f); -- biSizeImage : if uncompressed: image size or 0 + bmpput32( 0, f); -- biXPelsPerMeter : hor resolution + bmpput32( 0, f); -- biYPelsPerMeter : ver resolution + bmpput32( 0, f); -- biClrUsed : for supported format always 0 + bmpput32( 0, f); -- biClrImportant : no color table => 0 + +end write_bmp_header; + +procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8(b,f); + bmpput8(g,f); + bmpput8(r,f); +end write_bmp_pixel; + + +function bmpget8 (file f : BMP_FILE_TYPE ) return integer is + variable chr : character; +begin + read (f,chr); + return character'pos(chr); +end bmpget8; + +function bmpget16 (file f : BMP_FILE_TYPE ) return integer is + variable value : integer; +begin + value := bmpget8(f); + value := value + bmpget8(f)*256; + return value; +end bmpget16; + +function bmpget32 (file f : BMP_FILE_TYPE ) return integer is + variable value : integer; +begin + value := bmpget8(f); + value := value + bmpget8(f)*256; + value := value + bmpget8(f)*256*256; + value := value + bmpget8(f)*256*256*256; + return value; +end bmpget32; + +procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ) is + variable chr : character; + variable val : integer; +begin + success := true; + read (f,chr); + if chr /= 'B' then success := false; end if; + read (f,chr); + if chr /= 'M' then success := false; end if; + val := bmpget32(f); -- bfSize : size of file (unsave) + val := bmpget32(f); -- bfReserved : always 0 + if val /= 0 then success := false; end if; + val := bmpget32(f); -- bfOffBits : image data offset + val := bmpget32(f); -- biSize : header size (=40) + if val /= 40 then success := false; end if; + sizex := bmpget32(f); -- biWidth : num horizontal pixel + sizey := bmpget32(f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap) + val := bmpget16(f); -- biPlanes : num bitplanes, always 1 + if val /= 1 then success := false; end if; + val := bmpget16(f); -- biBitCount : bpp + if val /= 24 then success := false; end if; + val := bmpget32(f); -- biCompression : compression (0: uncompressed) + if val /= 0 then success := false; end if; + val := bmpget32(f); -- biSizeImage : if uncompressed: image size or 0 + val := bmpget32(f); -- biXPelsPerMeter : hor resolution + val := bmpget32(f); -- biYPelsPerMeter : ver resolution + val := bmpget32(f); -- biClrUsed : for supported format always 0 + if val /= 0 then success := false; end if; + val := bmpget32(f); -- biClrImportant : no color table => 0 + if val /= 0 then success := false; end if; +end read_bmp_header; + + +procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ) is +begin + if endfile(f) then + success := false; + else + b := bmpget8(f); + g := bmpget8(f); + r := bmpget8(f); + success := true; + end if; +end read_bmp_pixel; + +procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ) is +begin + if endfile(f) then + success := false; + else + u := bmpget8(f); + y1 := bmpget8(f); + v := bmpget8(f); + y2 := bmpget8(f); + success := true; + end if; +end read_yuv422_pixels; + +procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ) is +begin + y := INTEGER( (0.299 * REAL(r)) + (0.587 * REAL(g)) + (0.114 * REAL(b)) + 0.0 ); + u := INTEGER(-(0.169 * REAL(r)) - (0.331 * REAL(g)) + (0.500 * REAL(b)) + 128.0 ); + v := INTEGER( (0.500 * REAL(r)) - (0.419 * REAL(g)) - (0.081 * REAL(b)) + 128.0 ); + if (y>255) then + y := 255; + elsif (y<0) then + y := 0; + end if; + if (u>255) then + u := 255; + elsif (u<0) then + u := 0; + end if; + if (v>255) then + v := 255; + elsif (v<0) then + v := 0; + end if; +end rgb2yuv; + +procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ) is +begin + r := INTEGER( (1.000 * REAL(y)) + (0.000 * REAL(u-128)) + (1.400 * REAL(v-128))); + g := INTEGER( (1.000 * REAL(y)) - (0.343 * REAL(u-128)) - (0.711 * REAL(v-128))); + b := INTEGER( (1.000 * REAL(y)) + (1.765 * REAL(u-128)) - (0.000 * REAL(v-128))); + if (r>255) then + r := 255; + elsif (r<0) then + r := 0; + end if; + if (g>255) then + g := 255; + elsif (g<0) then + g := 0; + end if; + if (b>255) then + b := 255; + elsif (b<0) then + b := 0; + end if; +end yuv2rgb; + + + + + +end package body; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/d44d/axis_master_simmodel.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/d44d/axis_master_simmodel.vhd new file mode 100644 index 0000000..ef32207 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/d44d/axis_master_simmodel.vhd @@ -0,0 +1,375 @@ +------------------------------------------------------------------------------ +-- axis_master_simmodel.vhd - entity/architecture pair +------------------------------------------------------------------------------ +---------------------------------------------------------- +-- Prof. Dr.-Ing. W. Gehrke (c) 2013/2015 +---------------------------------------------------------- + +use std.textio.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.bmp_pkg.all; + +entity axis_master_simmodel is + generic + ( + DATA_WIDTH : integer := 32; + HAS_FIFO_INTERFACE : boolean := false; + FIFO_AWIDTH : integer := 11; + FIFO_REQUEST_TRESHOLD : integer := 32; + TUSERWIDTH : integer := 1; + FILE_NAME : string := string'("tst"); + FILE_EXTENSION : string := string'("bmp"); + FILE_AUTONUMBERING : boolean := false; + NUM_PIX_PER_LINE : integer := 32; + NUM_LINES : integer := 32; + NUM_FRAMES_PER_FILE : integer := 1; + RANDOM_TVALID : boolean := true; + PIXEL_FORMAT : integer := 1; + ALPHA_VALUE : integer := 255; + FRAMING_PIXELS : integer := 0; + FRAMING_LINES : integer := 0; + FRAMING_VAL_R_V : integer := 128; + FRAMING_VAL_G_Y : integer := 128; + FRAMING_VAL_B_U : integer := 128 + ); + port + ( + ACLK : in std_logic; + ARESETN : in std_logic; + FINISHED : out std_logic; + + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(DATA_WIDTH-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TUSER : out std_logic_vector(TUSERWIDTH-1 downto 0); + M_AXIS_NUM_FREE : in std_logic_vector(FIFO_AWIDTH-1 downto 0) := (others=>'1') -- Number of free entries in target + ); + + +end entity axis_master_simmodel; + + +architecture sim of axis_master_simmodel is + + signal rnd : unsigned (31 downto 0) := x"ABBAABBA"; + signal local_clk : std_logic; + +begin + +-- synthesis translate_off +-- translate off + + local_clk <= ACLK; + + -- uint32_t xorshift32() { + -- static uint32_t x = 314159265; + -- x ^= x << 13; + -- x ^= x >> 17; + -- x ^= x << 5; + -- return x; + -- } + process + variable r : unsigned (31 downto 0); + begin + wait until rising_edge(local_clk); + r := rnd; + r := r xor (r(18 downto 0)& x"000"&"0"); + r := r xor (x"0000"&"0"&r(31 downto 17)); + r := r xor (r(26 downto 0)& "00000"); + rnd <= r; + end process; + + + process + + variable file_num : integer := 0; + variable is_bmp_file: boolean; + variable is_yuv_file: boolean; + + variable r : integer; + variable g : integer; + variable b : integer; + + variable y1 : integer; + variable u1 : integer; + variable v1 : integer; + variable y2 : integer; + variable u2 : integer; + variable v2 : integer; + + variable sizex : integer; + variable sizey : integer; + + variable delay_cnt : integer; + variable tvalid_cnt : integer := 31415; + + variable ok : boolean; + + file f : BMP_FILE_TYPE; + + variable file_status : file_open_status; + + + variable x : integer; + variable pixels_per_beat : integer; + + + type rgbyuv is record + r : integer; + g : integer; + b : integer; + y : integer; + u : integer; + v : integer; + end record; + type tarr1 is array(0 to NUM_PIX_PER_LINE-1) of rgbyuv; + type tarr2 is array(0 to NUM_LINES-1) of tarr1; + variable pix : tarr2; + + type t_pixel_data is array(0 to 3) of rgbyuv; + variable p : t_pixel_data; + + type t_raw_data is array(0 to 3) of integer; + variable raw_data : t_raw_data; + + begin + + wait until rising_edge (local_clk); + if (ARESETN = '0') then + M_AXIS_TVALID <= '0'; + M_AXIS_TDATA <= (others=>'0'); + M_AXIS_TLAST <= '0'; + M_AXIS_TUSER <= (others=>'0'); + FINISHED <= '0'; + file_num := 0; + tvalid_cnt := to_integer(rnd and x"0000001F"); + else + M_AXIS_TLAST <= '0'; + M_AXIS_TVALID <= '0'; + M_AXIS_TUSER <= (others=>'0'); + FINISHED <= '0'; + + -- Start-Up delay + for i in 0 to 100 loop + wait until rising_edge (local_clk); + end loop; + + -- Send dummy data in front of the frame to chen + M_AXIS_TVALID <= '1'; + M_AXIS_TDATA <= (others=>'0'); + M_AXIS_TLAST <= '0'; + M_AXIS_TUSER <= (others=>'0'); + + for i in 0 to 5000 loop + wait until rising_edge (local_clk); + end loop; + + M_AXIS_TVALID <= '0'; + + + -- Check if input file is in BMP format + is_bmp_file := false; + is_yuv_file := false; + if (FILE_EXTENSION = "BMP") or (FILE_EXTENSION = "bmp") then + is_bmp_file := true; + elsif (FILE_EXTENSION = "YUV") or (FILE_EXTENSION = "yuv") then + is_yuv_file := true; + end if; + + file_status := open_ok; + + while file_status = open_ok loop + -- Create filename and try to open the file + if FILE_AUTONUMBERING then + file_open ( file_status, f, FILE_NAME & "_" & integer'image(file_num) & "." & FILE_EXTENSION, read_mode); + else + file_open ( file_status, f, FILE_NAME & "." & FILE_EXTENSION, read_mode); + end if; + + -- File open succeeded ? + if file_status = open_ok then + file_num := file_num + 1; -- increase filenum idx + if is_bmp_file then + read_bmp_header(ok,sizex,sizey,f); + if sizey < 0 then + sizey := -sizey; + end if; + else + sizex := NUM_PIX_PER_LINE; + sizey := NUM_LINES; + ok := true; + end if; + + if ok then + for fr in 0 to NUM_FRAMES_PER_FILE-1 loop -- frame loop + M_AXIS_TUSER(0) <= '1'; -- start of frame + + if is_bmp_file then -- bmp format ? + for y in NUM_LINES-1 downto 0 loop + for x in 0 to NUM_PIX_PER_LINE-1 loop + read_bmp_pixel(ok,pix(y)(x).r,pix(y)(x).g,pix(y)(x).b,f); + rgb2yuv(pix(y)(x).r,pix(y)(x).g,pix(y)(x).b,pix(y)(x).y,pix(y)(x).u,pix(y)(x).v); + end loop; + end loop; + end if; + + if is_yuv_file then -- yuv format (YUV422) ? + for y in NUM_LINES-1 downto 0 loop + for x in 0 to NUM_PIX_PER_LINE/2-1 loop + read_yuv422_pixels(ok,pix(y)(x).y,pix(y)(x+1).y,pix(y)(x).u,pix(y)(x).v,f); + pix(y)(x+1).u := pix(y)(x).u; + pix(y)(x+1).v := pix(y)(x).v; + yuv2rgb(pix(y)(x).y,pix(y)(x).u,pix(y)(x).v,pix(y)(x).r,pix(y)(x).g,pix(y)(x).b); + yuv2rgb(pix(y)(x+1).y,pix(y)(x+1).u,pix(y)(x+1).v,pix(y)(x+1).r,pix(y)(x+1).g,pix(y)(x+1).b); + end loop; + end loop; + end if; + + if DATA_WIDTH = 32 then + case PIXEL_FORMAT is + when 0 => pixels_per_beat := 2; + when 1|5 => pixels_per_beat := 1; + when 2|6 => pixels_per_beat := 1; + when 12 => pixels_per_beat := 1; + when 13 => pixels_per_beat := 4; + when others => pixels_per_beat := 4; + end case; + else + pixels_per_beat := 1; + end if; + + for y in 0 to (sizey+2*FRAMING_LINES)-1 loop -- line loop + x := 0; + while x<(sizex+2*FRAMING_PIXELS) loop + if (y >= FRAMING_LINES) and (y < FRAMING_LINES+sizey) and + (x >= FRAMING_PIXELS) and (x < FRAMING_PIXELS+sizex) then + -- "active" pixel area + if is_bmp_file or is_yuv_file then -- bmp_format or yuv format ? + p(0) := pix(y-FRAMING_LINES)(x-FRAMING_PIXELS); + if pixels_per_beat > 1 then + p(1) := pix(y-FRAMING_LINES)(x+1-FRAMING_PIXELS); + end if; + if pixels_per_beat > 2 then + p(2) := pix(y-FRAMING_LINES)(x+2-FRAMING_PIXELS); + end if; + if pixels_per_beat > 3 then + p(3) := pix(y-FRAMING_LINES)(x+3-FRAMING_PIXELS); + end if; + else + raw_data(0) := bmpget8(f); + if DATA_WIDTH = 32 then + raw_data(1) := bmpget8(f); + raw_data(2) := bmpget8(f); + raw_data(3) := bmpget8(f); + end if; + end if; + else + -- "framing" area + p(0).r := FRAMING_VAL_R_V; + p(0).g := FRAMING_VAL_G_Y; + p(0).b := FRAMING_VAL_B_U; + p(0).v := FRAMING_VAL_R_V; + p(0).y := FRAMING_VAL_G_Y; + p(0).u := FRAMING_VAL_B_U; + p(1) := p(0); + p(2) := p(0); + p(3) := p(0); + end if; + + -- wait until receiving FIFO has sufficient space + -- if FIFO_REQUEST_TRESHOLD equals 0, this function is disabled + if HAS_FIFO_INTERFACE then + while FIFO_REQUEST_TRESHOLD /= 0 and to_integer(unsigned(M_AXIS_NUM_FREE)) < FIFO_REQUEST_TRESHOLD loop + wait until rising_edge (local_clk); + end loop; + end if; + + -- output data, valid and last + + if is_bmp_file or is_yuv_file then -- bmp format or yuv format ? + if DATA_WIDTH = 32 then + case PIXEL_FORMAT is + when 0 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(1).y,8)&to_unsigned((p(1).v+p(0).v)/2,8)&to_unsigned(p(0).y,8)&to_unsigned((p(1).u+p(0).u)/2,8)); + when 1|5 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(ALPHA_VALUE,8)&to_unsigned(p(0).v,8)&to_unsigned(p(0).u,8)&to_unsigned(p(0).y,8)); + when 2|6 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(ALPHA_VALUE,8)&to_unsigned(p(0).r,8)&to_unsigned(p(0).b,8)&to_unsigned(p(0).g,8)); + when 12 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(ALPHA_VALUE,8)&to_unsigned(128,8)&to_unsigned(128,8)&to_unsigned(p(0).y,8)); + when 13 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(3).y,8)&to_unsigned(p(2).y,8)&to_unsigned(p(1).y,8)&to_unsigned(p(0).y,8)); + when others => M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(3).y,8)&to_unsigned(p(2).y,8)&to_unsigned(p(1).y,8)&to_unsigned(p(0).y,8)); + end case; + else + M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(0).y,8)); + end if; + else -- raw format + if DATA_WIDTH = 32 then + M_AXIS_TDATA <= std_logic_vector(to_unsigned(raw_data(3),8)&to_unsigned(raw_data(2),8)&to_unsigned(raw_data(1),8)&to_unsigned(raw_data(0),8)); + else + M_AXIS_TDATA <= std_logic_vector(to_unsigned(raw_data(0),8)); + end if; + end if; + + M_AXIS_TVALID <= '1'; + if x = (sizex+2*FRAMING_PIXELS)-pixels_per_beat then + M_AXIS_TLAST <= '1'; + else + M_AXIS_TLAST <= '0'; + end if; + + -- wait until data has been acknowledged + wait until rising_edge (local_clk); + while M_AXIS_TREADY = '0' loop + wait until rising_edge (local_clk); + end loop; + + M_AXIS_TUSER(0) <= '0'; + + tvalid_cnt := tvalid_cnt - 1; + if RANDOM_TVALID and tvalid_cnt <= 0 then + -- random TVALID delay + delay_cnt := to_integer(rnd and x"00000007"); + while delay_cnt > 0 loop + M_AXIS_TVALID <= '0'; + delay_cnt := delay_cnt - 1; + wait until rising_edge (local_clk); + tvalid_cnt := to_integer(rnd and x"0000001F"); + end loop; + M_AXIS_TVALID <= '1'; + end if; + + x := x + pixels_per_beat; + + end loop; -- pixel loop + end loop; -- line loop + end loop; -- frame loop + file_close(f); + end if; -- if ok + end if; -- if open_status ok + end loop; + + FINISHED <= '1'; + M_AXIS_TLAST <= '0'; + M_AXIS_TVALID <= '1'; + M_AXIS_TUSER <= (others=>'0'); + if DATA_WIDTH = 32 then + M_AXIS_TDATA <= x"80808080"; + else + M_AXIS_TDATA <= x"80"; + end if; + + -- wait until reset is activated + while ARESETN = '1' loop + wait until rising_edge (local_clk); + end loop; + + end if; + end process; + +-- synthesis translate_on +-- translate on + + +end sim; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/d44d/bmp_pkg.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/d44d/bmp_pkg.vhd new file mode 100644 index 0000000..5826d4e --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/d44d/bmp_pkg.vhd @@ -0,0 +1,208 @@ + +use std.textio.all; + +package bmp_pkg is + + type BMP_FILE_TYPE is file of character; + + procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ); + procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ); + procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ); + procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ); + procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ); + + function bmpget8 (file f : BMP_FILE_TYPE ) return integer; + function bmpget16 (file f : BMP_FILE_TYPE ) return integer; + function bmpget32 (file f : BMP_FILE_TYPE ) return integer; + procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ); + procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ); + procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ); + procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ); + procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ); + +end; + +package body bmp_pkg is + +procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + write(f, character'val(value)); +end bmpput8; + +procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8((value) mod 256,f); + bmpput8((value/256) mod 256,f); +end bmpput16; + +procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8((value) mod 256,f); + bmpput8((value/256) mod 256,f); + bmpput8((value/256/256) mod 256,f); + bmpput8((value/256/256/256) mod 256,f); +end bmpput32; + + +procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ) is +begin + write(f,'B'); + write(f,'M'); + bmpput32(54+sizex*sizey*3,f); -- bfSize : size of file (unsave) + bmpput32( 0, f); -- bfReserved : always 0 + bmpput32(54, f); -- bfOffBits : image data offset (=54) + bmpput32(40, f); -- biSize : header size (=40) + bmpput32(sizex,f); -- biWidth : num horizontal pixel + bmpput32(sizey,f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap) + bmpput16( 1, f); -- biPlanes : num bitplanes, always 1 + bmpput16(24, f); -- biBitCount : bpp + bmpput32( 0, f); -- biCompression : compression (0: uncompressed) + bmpput32(3*sizex*sizey,f); -- biSizeImage : if uncompressed: image size or 0 + bmpput32( 0, f); -- biXPelsPerMeter : hor resolution + bmpput32( 0, f); -- biYPelsPerMeter : ver resolution + bmpput32( 0, f); -- biClrUsed : for supported format always 0 + bmpput32( 0, f); -- biClrImportant : no color table => 0 + +end write_bmp_header; + +procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ) is +begin + bmpput8(b,f); + bmpput8(g,f); + bmpput8(r,f); +end write_bmp_pixel; + + +function bmpget8 (file f : BMP_FILE_TYPE ) return integer is + variable chr : character; +begin + read (f,chr); + return character'pos(chr); +end bmpget8; + +function bmpget16 (file f : BMP_FILE_TYPE ) return integer is + variable value : integer; +begin + value := bmpget8(f); + value := value + bmpget8(f)*256; + return value; +end bmpget16; + +function bmpget32 (file f : BMP_FILE_TYPE ) return integer is + variable value : integer; +begin + value := bmpget8(f); + value := value + bmpget8(f)*256; + value := value + bmpget8(f)*256*256; + value := value + bmpget8(f)*256*256*256; + return value; +end bmpget32; + +procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ) is + variable chr : character; + variable val : integer; +begin + success := true; + read (f,chr); + if chr /= 'B' then success := false; end if; + read (f,chr); + if chr /= 'M' then success := false; end if; + val := bmpget32(f); -- bfSize : size of file (unsave) + val := bmpget32(f); -- bfReserved : always 0 + if val /= 0 then success := false; end if; + val := bmpget32(f); -- bfOffBits : image data offset + val := bmpget32(f); -- biSize : header size (=40) + if val /= 40 then success := false; end if; + sizex := bmpget32(f); -- biWidth : num horizontal pixel + sizey := bmpget32(f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap) + val := bmpget16(f); -- biPlanes : num bitplanes, always 1 + if val /= 1 then success := false; end if; + val := bmpget16(f); -- biBitCount : bpp + if val /= 24 then success := false; end if; + val := bmpget32(f); -- biCompression : compression (0: uncompressed) + if val /= 0 then success := false; end if; + val := bmpget32(f); -- biSizeImage : if uncompressed: image size or 0 + val := bmpget32(f); -- biXPelsPerMeter : hor resolution + val := bmpget32(f); -- biYPelsPerMeter : ver resolution + val := bmpget32(f); -- biClrUsed : for supported format always 0 + if val /= 0 then success := false; end if; + val := bmpget32(f); -- biClrImportant : no color table => 0 + if val /= 0 then success := false; end if; +end read_bmp_header; + + +procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ) is +begin + if endfile(f) then + success := false; + else + b := bmpget8(f); + g := bmpget8(f); + r := bmpget8(f); + success := true; + end if; +end read_bmp_pixel; + +procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ) is +begin + if endfile(f) then + success := false; + else + u := bmpget8(f); + y1 := bmpget8(f); + v := bmpget8(f); + y2 := bmpget8(f); + success := true; + end if; +end read_yuv422_pixels; + +procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ) is +begin + y := INTEGER( (0.299 * REAL(r)) + (0.587 * REAL(g)) + (0.114 * REAL(b)) + 0.0 ); + u := INTEGER(-(0.169 * REAL(r)) - (0.331 * REAL(g)) + (0.500 * REAL(b)) + 128.0 ); + v := INTEGER( (0.500 * REAL(r)) - (0.419 * REAL(g)) - (0.081 * REAL(b)) + 128.0 ); + if (y>255) then + y := 255; + elsif (y<0) then + y := 0; + end if; + if (u>255) then + u := 255; + elsif (u<0) then + u := 0; + end if; + if (v>255) then + v := 255; + elsif (v<0) then + v := 0; + end if; +end rgb2yuv; + +procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ) is +begin + r := INTEGER( (1.000 * REAL(y)) + (0.000 * REAL(u-128)) + (1.400 * REAL(v-128))); + g := INTEGER( (1.000 * REAL(y)) - (0.343 * REAL(u-128)) - (0.711 * REAL(v-128))); + b := INTEGER( (1.000 * REAL(y)) + (1.765 * REAL(u-128)) - (0.000 * REAL(v-128))); + if (r>255) then + r := 255; + elsif (r<0) then + r := 0; + end if; + if (g>255) then + g := 255; + elsif (g<0) then + g := 0; + end if; + if (b>255) then + b := 255; + elsif (b<0) then + b := 0; + end if; +end yuv2rgb; + + + + + +end package body; + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/dfd1/sources_1/new/axis_upsizer.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/dfd1/sources_1/new/axis_upsizer.vhd new file mode 100644 index 0000000..37c19a7 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ipshared/dfd1/sources_1/new/axis_upsizer.vhd @@ -0,0 +1,103 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axis_upsizer is + generic + ( + WIDTH_IN : integer := 8; + SIZE_FACTOR : integer := 2; + BIG_ENDIAN : boolean := false + ); + + port + ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + + -- AXIS SLAVE + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(WIDTH_IN-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TUSER : in std_logic; + + -- AXIS Master + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(WIDTH_IN*SIZE_FACTOR-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TUSER : out std_logic + ); +end; + + +architecture rtl of axis_upsizer is + type T_STATE is (BYTE0,BYTE1,BYTEF); + signal state : T_STATE := BYTE0; + signal user : std_logic; + signal data : std_logic_vector(WIDTH_IN*SIZE_FACTOR-1 downto 0); +begin + S_AXIS_TREADY <= M_AXIS_TREADY when state = BYTEF else '1'; + M_AXIS_TVALID <= S_AXIS_TVALID when state = BYTEF else '0'; + M_AXIS_TLAST <= S_AXIS_TLAST when state = BYTEF else '0'; + M_AXIS_TUSER <= user when state = BYTEF else '0'; + + process (S_AXIS_TDATA, data) + begin + if BIG_ENDIAN then + for i in 0 to SIZE_FACTOR-1 loop + M_AXIS_TDATA(WIDTH_IN*SIZE_FACTOR-1-WIDTH_IN*i downto (WIDTH_IN-1)*SIZE_FACTOR-WIDTH_IN*i) <= data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i); + end loop; + M_AXIS_TDATA(WIDTH_IN-1 downto 0) <= S_AXIS_TDATA; + + else + M_AXIS_TDATA <= S_AXIS_TDATA & data(WIDTH_IN*(SIZE_FACTOR-1)-1 downto 0); + end if; + end process; + + process + variable i : integer; + variable ui : unsigned(5 downto 0); + begin + wait until rising_edge (AXIS_ACLK); + if AXIS_ARESETN = '0' then + state <= BYTE0; + else + case state is + when BYTE0 => + if S_AXIS_TVALID = '1' then + ui := (others=>'0'); + i := to_integer(ui); + data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i) <= S_AXIS_TDATA; + user <= S_AXIS_TUSER; + if S_AXIS_TLAST = '1' then + state <= BYTE0; + else + if (i + if S_AXIS_TVALID = '1' then + ui := ui+1; + i := to_integer(ui); + data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i) <= S_AXIS_TDATA; + if S_AXIS_TLAST = '1' then + state <= BYTE0; + elsif (i>=SIZE_FACTOR-2) then + state <= BYTEF; + end if; + end if; + when BYTEF => + if S_AXIS_TVALID = '1' and M_AXIS_TREADY='1' then + state <= BYTE0; + end if; + end case; + end if; + end process; + +end; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.v new file mode 100644 index 0000000..cea85a6 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.v @@ -0,0 +1,225 @@ +//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +//Date : Tue Dec 10 00:45:24 2024 +//Host : Bastistablet running 64-bit major release (build 9200) +//Command : generate_target design_1.bd +//Design : design_1 +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *) +module design_1 + (m_axi_lite_araddr, + m_axi_lite_arprot, + m_axi_lite_arready, + m_axi_lite_arvalid, + m_axi_lite_awaddr, + m_axi_lite_awprot, + m_axi_lite_awready, + m_axi_lite_awvalid, + m_axi_lite_bready, + m_axi_lite_bresp, + m_axi_lite_bvalid, + m_axi_lite_rdata, + m_axi_lite_rready, + m_axi_lite_rresp, + m_axi_lite_rvalid, + m_axi_lite_wdata, + m_axi_lite_wready, + m_axi_lite_wstrb, + m_axi_lite_wvalid); + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axi_lite, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]m_axi_lite_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARPROT" *) output [2:0]m_axi_lite_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARREADY" *) input m_axi_lite_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARVALID" *) output m_axi_lite_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWADDR" *) output [31:0]m_axi_lite_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWPROT" *) output [2:0]m_axi_lite_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWREADY" *) input m_axi_lite_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWVALID" *) output m_axi_lite_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BREADY" *) output m_axi_lite_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BRESP" *) input [1:0]m_axi_lite_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BVALID" *) input m_axi_lite_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RDATA" *) input [31:0]m_axi_lite_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RREADY" *) output m_axi_lite_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RRESP" *) input [1:0]m_axi_lite_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RVALID" *) input m_axi_lite_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WDATA" *) output [31:0]m_axi_lite_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WREADY" *) input m_axi_lite_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WSTRB" *) output [3:0]m_axi_lite_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WVALID" *) output m_axi_lite_wvalid; + + wire Net; + wire Net1; + wire [31:0]axil_master_with_rom_0_M_AXIL_ARADDR; + wire [2:0]axil_master_with_rom_0_M_AXIL_ARPROT; + wire axil_master_with_rom_0_M_AXIL_ARREADY; + wire axil_master_with_rom_0_M_AXIL_ARVALID; + wire [31:0]axil_master_with_rom_0_M_AXIL_AWADDR; + wire [2:0]axil_master_with_rom_0_M_AXIL_AWPROT; + wire axil_master_with_rom_0_M_AXIL_AWREADY; + wire axil_master_with_rom_0_M_AXIL_AWVALID; + wire axil_master_with_rom_0_M_AXIL_BREADY; + wire [1:0]axil_master_with_rom_0_M_AXIL_BRESP; + wire axil_master_with_rom_0_M_AXIL_BVALID; + wire [31:0]axil_master_with_rom_0_M_AXIL_RDATA; + wire axil_master_with_rom_0_M_AXIL_RREADY; + wire [1:0]axil_master_with_rom_0_M_AXIL_RRESP; + wire axil_master_with_rom_0_M_AXIL_RVALID; + wire [31:0]axil_master_with_rom_0_M_AXIL_WDATA; + wire axil_master_with_rom_0_M_AXIL_WREADY; + wire [3:0]axil_master_with_rom_0_M_AXIL_WSTRB; + wire axil_master_with_rom_0_M_AXIL_WVALID; + wire [7:0]axis_downsizer_0_M_AXIS_TDATA; + wire axis_downsizer_0_M_AXIS_TLAST; + wire axis_downsizer_0_M_AXIS_TREADY; + wire axis_downsizer_0_M_AXIS_TUSER; + wire axis_downsizer_0_M_AXIS_TVALID; + wire [23:0]axis_linemem_single_0_m_axis_TDATA; + wire axis_linemem_single_0_m_axis_TLAST; + wire axis_linemem_single_0_m_axis_TREADY; + wire [2:0]axis_linemem_single_0_m_axis_TUSER; + wire axis_linemem_single_0_m_axis_TVALID; + wire [31:0]axis_master_simmodel_0_M_AXIS_TDATA; + wire axis_master_simmodel_0_M_AXIS_TLAST; + wire axis_master_simmodel_0_M_AXIS_TREADY; + wire [0:0]axis_master_simmodel_0_M_AXIS_TUSER; + wire axis_master_simmodel_0_M_AXIS_TVALID; + wire axis_slave_simmodel_0_FINISHED; + wire [31:0]axis_upsizer_0_M_AXIS_TDATA; + wire axis_upsizer_0_M_AXIS_TLAST; + wire axis_upsizer_0_M_AXIS_TREADY; + wire axis_upsizer_0_M_AXIS_TUSER; + wire axis_upsizer_0_M_AXIS_TVALID; + wire [7:0]axis_video_filter_0_M_AXIS_TDATA; + wire axis_video_filter_0_M_AXIS_TLAST; + wire axis_video_filter_0_M_AXIS_TREADY; + wire axis_video_filter_0_M_AXIS_TUSER; + wire axis_video_filter_0_M_AXIS_TVALID; + + assign axil_master_with_rom_0_M_AXIL_ARREADY = m_axi_lite_arready; + assign axil_master_with_rom_0_M_AXIL_AWREADY = m_axi_lite_awready; + assign axil_master_with_rom_0_M_AXIL_BRESP = m_axi_lite_bresp[1:0]; + assign axil_master_with_rom_0_M_AXIL_BVALID = m_axi_lite_bvalid; + assign axil_master_with_rom_0_M_AXIL_RDATA = m_axi_lite_rdata[31:0]; + assign axil_master_with_rom_0_M_AXIL_RRESP = m_axi_lite_rresp[1:0]; + assign axil_master_with_rom_0_M_AXIL_RVALID = m_axi_lite_rvalid; + assign axil_master_with_rom_0_M_AXIL_WREADY = m_axi_lite_wready; + assign m_axi_lite_araddr[31:0] = axil_master_with_rom_0_M_AXIL_ARADDR; + assign m_axi_lite_arprot[2:0] = axil_master_with_rom_0_M_AXIL_ARPROT; + assign m_axi_lite_arvalid = axil_master_with_rom_0_M_AXIL_ARVALID; + assign m_axi_lite_awaddr[31:0] = axil_master_with_rom_0_M_AXIL_AWADDR; + assign m_axi_lite_awprot[2:0] = axil_master_with_rom_0_M_AXIL_AWPROT; + assign m_axi_lite_awvalid = axil_master_with_rom_0_M_AXIL_AWVALID; + assign m_axi_lite_bready = axil_master_with_rom_0_M_AXIL_BREADY; + assign m_axi_lite_rready = axil_master_with_rom_0_M_AXIL_RREADY; + assign m_axi_lite_wdata[31:0] = axil_master_with_rom_0_M_AXIL_WDATA; + assign m_axi_lite_wstrb[3:0] = axil_master_with_rom_0_M_AXIL_WSTRB; + assign m_axi_lite_wvalid = axil_master_with_rom_0_M_AXIL_WVALID; + design_1_axil_master_with_rom_0_0 axil_master_with_rom_0 + (.M_AXIL_ACLK(Net), + .M_AXIL_ARADDR(axil_master_with_rom_0_M_AXIL_ARADDR), + .M_AXIL_ARESETN(Net1), + .M_AXIL_ARPROT(axil_master_with_rom_0_M_AXIL_ARPROT), + .M_AXIL_ARREADY(axil_master_with_rom_0_M_AXIL_ARREADY), + .M_AXIL_ARVALID(axil_master_with_rom_0_M_AXIL_ARVALID), + .M_AXIL_AWADDR(axil_master_with_rom_0_M_AXIL_AWADDR), + .M_AXIL_AWPROT(axil_master_with_rom_0_M_AXIL_AWPROT), + .M_AXIL_AWREADY(axil_master_with_rom_0_M_AXIL_AWREADY), + .M_AXIL_AWVALID(axil_master_with_rom_0_M_AXIL_AWVALID), + .M_AXIL_BREADY(axil_master_with_rom_0_M_AXIL_BREADY), + .M_AXIL_BRESP(axil_master_with_rom_0_M_AXIL_BRESP), + .M_AXIL_BVALID(axil_master_with_rom_0_M_AXIL_BVALID), + .M_AXIL_RDATA(axil_master_with_rom_0_M_AXIL_RDATA), + .M_AXIL_RREADY(axil_master_with_rom_0_M_AXIL_RREADY), + .M_AXIL_RRESP(axil_master_with_rom_0_M_AXIL_RRESP), + .M_AXIL_RVALID(axil_master_with_rom_0_M_AXIL_RVALID), + .M_AXIL_WDATA(axil_master_with_rom_0_M_AXIL_WDATA), + .M_AXIL_WREADY(axil_master_with_rom_0_M_AXIL_WREADY), + .M_AXIL_WSTRB(axil_master_with_rom_0_M_AXIL_WSTRB), + .M_AXIL_WVALID(axil_master_with_rom_0_M_AXIL_WVALID)); + design_1_axis_downsizer_0_0 axis_downsizer_0 + (.AXIS_ACLK(Net), + .AXIS_ARESETN(Net1), + .M_AXIS_TDATA(axis_downsizer_0_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_downsizer_0_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_downsizer_0_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_downsizer_0_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_downsizer_0_M_AXIS_TVALID), + .S_AXIS_TDATA(axis_master_simmodel_0_M_AXIS_TDATA), + .S_AXIS_TLAST(axis_master_simmodel_0_M_AXIS_TLAST), + .S_AXIS_TREADY(axis_master_simmodel_0_M_AXIS_TREADY), + .S_AXIS_TUSER(axis_master_simmodel_0_M_AXIS_TUSER), + .S_AXIS_TVALID(axis_master_simmodel_0_M_AXIS_TVALID)); + design_1_axis_linemem_single_0_0 axis_linemem_single_0 + (.aclk(Net), + .aresetn(Net1), + .m_axis_tdata(axis_linemem_single_0_m_axis_TDATA), + .m_axis_tlast(axis_linemem_single_0_m_axis_TLAST), + .m_axis_tready(axis_linemem_single_0_m_axis_TREADY), + .m_axis_tuser(axis_linemem_single_0_m_axis_TUSER), + .m_axis_tvalid(axis_linemem_single_0_m_axis_TVALID), + .s_axis_tdata(axis_downsizer_0_M_AXIS_TDATA), + .s_axis_tlast(axis_downsizer_0_M_AXIS_TLAST), + .s_axis_tready(axis_downsizer_0_M_AXIS_TREADY), + .s_axis_tuser(axis_downsizer_0_M_AXIS_TUSER), + .s_axis_tvalid(axis_downsizer_0_M_AXIS_TVALID)); + design_1_axis_master_simmodel_0_0 axis_master_simmodel_0 + (.ACLK(Net), + .ARESETN(Net1), + .M_AXIS_TDATA(axis_master_simmodel_0_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_master_simmodel_0_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_master_simmodel_0_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_master_simmodel_0_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_master_simmodel_0_M_AXIS_TVALID)); + design_1_axis_slave_simmodel_0_0 axis_slave_simmodel_0 + (.FINISHED(axis_slave_simmodel_0_FINISHED), + .S_AXIS_ACLK(Net), + .S_AXIS_ARESETN(Net1), + .S_AXIS_TDATA(axis_upsizer_0_M_AXIS_TDATA), + .S_AXIS_TLAST(axis_upsizer_0_M_AXIS_TLAST), + .S_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY), + .S_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER), + .S_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID)); + design_1_axis_upsizer_0_0 axis_upsizer_0 + (.AXIS_ACLK(Net), + .AXIS_ARESETN(Net1), + .M_AXIS_TDATA(axis_upsizer_0_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_upsizer_0_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID), + .S_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA), + .S_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST), + .S_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY), + .S_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER), + .S_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID)); + design_1_axis_video_filter_0_0 axis_video_filter_0 + (.ACLK(Net), + .ARESETN(Net1), + .M_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID), + .S_AXIL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXIL_ARVALID(1'b0), + .S_AXIL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXIL_AWVALID(1'b0), + .S_AXIL_BREADY(1'b0), + .S_AXIL_RREADY(1'b0), + .S_AXIL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXIL_WSTRB({1'b1,1'b1,1'b1,1'b1}), + .S_AXIL_WVALID(1'b0), + .S_AXIS_TDATA(axis_linemem_single_0_m_axis_TDATA), + .S_AXIS_TLAST(axis_linemem_single_0_m_axis_TLAST), + .S_AXIS_TREADY(axis_linemem_single_0_m_axis_TREADY), + .S_AXIS_TUSER(axis_linemem_single_0_m_axis_TUSER), + .S_AXIS_TVALID(axis_linemem_single_0_m_axis_TVALID)); + design_1_clk_rst_generator_0_0 clk_rst_generator_0 + (.clk(Net), + .rst_n(Net1), + .stop_simulation(axis_slave_simmodel_0_FINISHED)); +endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.v new file mode 100644 index 0000000..cea85a6 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.v @@ -0,0 +1,225 @@ +//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 +//Date : Tue Dec 10 00:45:24 2024 +//Host : Bastistablet running 64-bit major release (build 9200) +//Command : generate_target design_1.bd +//Design : design_1 +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *) +module design_1 + (m_axi_lite_araddr, + m_axi_lite_arprot, + m_axi_lite_arready, + m_axi_lite_arvalid, + m_axi_lite_awaddr, + m_axi_lite_awprot, + m_axi_lite_awready, + m_axi_lite_awvalid, + m_axi_lite_bready, + m_axi_lite_bresp, + m_axi_lite_bvalid, + m_axi_lite_rdata, + m_axi_lite_rready, + m_axi_lite_rresp, + m_axi_lite_rvalid, + m_axi_lite_wdata, + m_axi_lite_wready, + m_axi_lite_wstrb, + m_axi_lite_wvalid); + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axi_lite, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]m_axi_lite_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARPROT" *) output [2:0]m_axi_lite_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARREADY" *) input m_axi_lite_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARVALID" *) output m_axi_lite_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWADDR" *) output [31:0]m_axi_lite_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWPROT" *) output [2:0]m_axi_lite_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWREADY" *) input m_axi_lite_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWVALID" *) output m_axi_lite_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BREADY" *) output m_axi_lite_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BRESP" *) input [1:0]m_axi_lite_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BVALID" *) input m_axi_lite_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RDATA" *) input [31:0]m_axi_lite_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RREADY" *) output m_axi_lite_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RRESP" *) input [1:0]m_axi_lite_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RVALID" *) input m_axi_lite_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WDATA" *) output [31:0]m_axi_lite_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WREADY" *) input m_axi_lite_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WSTRB" *) output [3:0]m_axi_lite_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WVALID" *) output m_axi_lite_wvalid; + + wire Net; + wire Net1; + wire [31:0]axil_master_with_rom_0_M_AXIL_ARADDR; + wire [2:0]axil_master_with_rom_0_M_AXIL_ARPROT; + wire axil_master_with_rom_0_M_AXIL_ARREADY; + wire axil_master_with_rom_0_M_AXIL_ARVALID; + wire [31:0]axil_master_with_rom_0_M_AXIL_AWADDR; + wire [2:0]axil_master_with_rom_0_M_AXIL_AWPROT; + wire axil_master_with_rom_0_M_AXIL_AWREADY; + wire axil_master_with_rom_0_M_AXIL_AWVALID; + wire axil_master_with_rom_0_M_AXIL_BREADY; + wire [1:0]axil_master_with_rom_0_M_AXIL_BRESP; + wire axil_master_with_rom_0_M_AXIL_BVALID; + wire [31:0]axil_master_with_rom_0_M_AXIL_RDATA; + wire axil_master_with_rom_0_M_AXIL_RREADY; + wire [1:0]axil_master_with_rom_0_M_AXIL_RRESP; + wire axil_master_with_rom_0_M_AXIL_RVALID; + wire [31:0]axil_master_with_rom_0_M_AXIL_WDATA; + wire axil_master_with_rom_0_M_AXIL_WREADY; + wire [3:0]axil_master_with_rom_0_M_AXIL_WSTRB; + wire axil_master_with_rom_0_M_AXIL_WVALID; + wire [7:0]axis_downsizer_0_M_AXIS_TDATA; + wire axis_downsizer_0_M_AXIS_TLAST; + wire axis_downsizer_0_M_AXIS_TREADY; + wire axis_downsizer_0_M_AXIS_TUSER; + wire axis_downsizer_0_M_AXIS_TVALID; + wire [23:0]axis_linemem_single_0_m_axis_TDATA; + wire axis_linemem_single_0_m_axis_TLAST; + wire axis_linemem_single_0_m_axis_TREADY; + wire [2:0]axis_linemem_single_0_m_axis_TUSER; + wire axis_linemem_single_0_m_axis_TVALID; + wire [31:0]axis_master_simmodel_0_M_AXIS_TDATA; + wire axis_master_simmodel_0_M_AXIS_TLAST; + wire axis_master_simmodel_0_M_AXIS_TREADY; + wire [0:0]axis_master_simmodel_0_M_AXIS_TUSER; + wire axis_master_simmodel_0_M_AXIS_TVALID; + wire axis_slave_simmodel_0_FINISHED; + wire [31:0]axis_upsizer_0_M_AXIS_TDATA; + wire axis_upsizer_0_M_AXIS_TLAST; + wire axis_upsizer_0_M_AXIS_TREADY; + wire axis_upsizer_0_M_AXIS_TUSER; + wire axis_upsizer_0_M_AXIS_TVALID; + wire [7:0]axis_video_filter_0_M_AXIS_TDATA; + wire axis_video_filter_0_M_AXIS_TLAST; + wire axis_video_filter_0_M_AXIS_TREADY; + wire axis_video_filter_0_M_AXIS_TUSER; + wire axis_video_filter_0_M_AXIS_TVALID; + + assign axil_master_with_rom_0_M_AXIL_ARREADY = m_axi_lite_arready; + assign axil_master_with_rom_0_M_AXIL_AWREADY = m_axi_lite_awready; + assign axil_master_with_rom_0_M_AXIL_BRESP = m_axi_lite_bresp[1:0]; + assign axil_master_with_rom_0_M_AXIL_BVALID = m_axi_lite_bvalid; + assign axil_master_with_rom_0_M_AXIL_RDATA = m_axi_lite_rdata[31:0]; + assign axil_master_with_rom_0_M_AXIL_RRESP = m_axi_lite_rresp[1:0]; + assign axil_master_with_rom_0_M_AXIL_RVALID = m_axi_lite_rvalid; + assign axil_master_with_rom_0_M_AXIL_WREADY = m_axi_lite_wready; + assign m_axi_lite_araddr[31:0] = axil_master_with_rom_0_M_AXIL_ARADDR; + assign m_axi_lite_arprot[2:0] = axil_master_with_rom_0_M_AXIL_ARPROT; + assign m_axi_lite_arvalid = axil_master_with_rom_0_M_AXIL_ARVALID; + assign m_axi_lite_awaddr[31:0] = axil_master_with_rom_0_M_AXIL_AWADDR; + assign m_axi_lite_awprot[2:0] = axil_master_with_rom_0_M_AXIL_AWPROT; + assign m_axi_lite_awvalid = axil_master_with_rom_0_M_AXIL_AWVALID; + assign m_axi_lite_bready = axil_master_with_rom_0_M_AXIL_BREADY; + assign m_axi_lite_rready = axil_master_with_rom_0_M_AXIL_RREADY; + assign m_axi_lite_wdata[31:0] = axil_master_with_rom_0_M_AXIL_WDATA; + assign m_axi_lite_wstrb[3:0] = axil_master_with_rom_0_M_AXIL_WSTRB; + assign m_axi_lite_wvalid = axil_master_with_rom_0_M_AXIL_WVALID; + design_1_axil_master_with_rom_0_0 axil_master_with_rom_0 + (.M_AXIL_ACLK(Net), + .M_AXIL_ARADDR(axil_master_with_rom_0_M_AXIL_ARADDR), + .M_AXIL_ARESETN(Net1), + .M_AXIL_ARPROT(axil_master_with_rom_0_M_AXIL_ARPROT), + .M_AXIL_ARREADY(axil_master_with_rom_0_M_AXIL_ARREADY), + .M_AXIL_ARVALID(axil_master_with_rom_0_M_AXIL_ARVALID), + .M_AXIL_AWADDR(axil_master_with_rom_0_M_AXIL_AWADDR), + .M_AXIL_AWPROT(axil_master_with_rom_0_M_AXIL_AWPROT), + .M_AXIL_AWREADY(axil_master_with_rom_0_M_AXIL_AWREADY), + .M_AXIL_AWVALID(axil_master_with_rom_0_M_AXIL_AWVALID), + .M_AXIL_BREADY(axil_master_with_rom_0_M_AXIL_BREADY), + .M_AXIL_BRESP(axil_master_with_rom_0_M_AXIL_BRESP), + .M_AXIL_BVALID(axil_master_with_rom_0_M_AXIL_BVALID), + .M_AXIL_RDATA(axil_master_with_rom_0_M_AXIL_RDATA), + .M_AXIL_RREADY(axil_master_with_rom_0_M_AXIL_RREADY), + .M_AXIL_RRESP(axil_master_with_rom_0_M_AXIL_RRESP), + .M_AXIL_RVALID(axil_master_with_rom_0_M_AXIL_RVALID), + .M_AXIL_WDATA(axil_master_with_rom_0_M_AXIL_WDATA), + .M_AXIL_WREADY(axil_master_with_rom_0_M_AXIL_WREADY), + .M_AXIL_WSTRB(axil_master_with_rom_0_M_AXIL_WSTRB), + .M_AXIL_WVALID(axil_master_with_rom_0_M_AXIL_WVALID)); + design_1_axis_downsizer_0_0 axis_downsizer_0 + (.AXIS_ACLK(Net), + .AXIS_ARESETN(Net1), + .M_AXIS_TDATA(axis_downsizer_0_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_downsizer_0_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_downsizer_0_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_downsizer_0_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_downsizer_0_M_AXIS_TVALID), + .S_AXIS_TDATA(axis_master_simmodel_0_M_AXIS_TDATA), + .S_AXIS_TLAST(axis_master_simmodel_0_M_AXIS_TLAST), + .S_AXIS_TREADY(axis_master_simmodel_0_M_AXIS_TREADY), + .S_AXIS_TUSER(axis_master_simmodel_0_M_AXIS_TUSER), + .S_AXIS_TVALID(axis_master_simmodel_0_M_AXIS_TVALID)); + design_1_axis_linemem_single_0_0 axis_linemem_single_0 + (.aclk(Net), + .aresetn(Net1), + .m_axis_tdata(axis_linemem_single_0_m_axis_TDATA), + .m_axis_tlast(axis_linemem_single_0_m_axis_TLAST), + .m_axis_tready(axis_linemem_single_0_m_axis_TREADY), + .m_axis_tuser(axis_linemem_single_0_m_axis_TUSER), + .m_axis_tvalid(axis_linemem_single_0_m_axis_TVALID), + .s_axis_tdata(axis_downsizer_0_M_AXIS_TDATA), + .s_axis_tlast(axis_downsizer_0_M_AXIS_TLAST), + .s_axis_tready(axis_downsizer_0_M_AXIS_TREADY), + .s_axis_tuser(axis_downsizer_0_M_AXIS_TUSER), + .s_axis_tvalid(axis_downsizer_0_M_AXIS_TVALID)); + design_1_axis_master_simmodel_0_0 axis_master_simmodel_0 + (.ACLK(Net), + .ARESETN(Net1), + .M_AXIS_TDATA(axis_master_simmodel_0_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_master_simmodel_0_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_master_simmodel_0_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_master_simmodel_0_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_master_simmodel_0_M_AXIS_TVALID)); + design_1_axis_slave_simmodel_0_0 axis_slave_simmodel_0 + (.FINISHED(axis_slave_simmodel_0_FINISHED), + .S_AXIS_ACLK(Net), + .S_AXIS_ARESETN(Net1), + .S_AXIS_TDATA(axis_upsizer_0_M_AXIS_TDATA), + .S_AXIS_TLAST(axis_upsizer_0_M_AXIS_TLAST), + .S_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY), + .S_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER), + .S_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID)); + design_1_axis_upsizer_0_0 axis_upsizer_0 + (.AXIS_ACLK(Net), + .AXIS_ARESETN(Net1), + .M_AXIS_TDATA(axis_upsizer_0_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_upsizer_0_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID), + .S_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA), + .S_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST), + .S_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY), + .S_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER), + .S_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID)); + design_1_axis_video_filter_0_0 axis_video_filter_0 + (.ACLK(Net), + .ARESETN(Net1), + .M_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID), + .S_AXIL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXIL_ARVALID(1'b0), + .S_AXIL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXIL_AWVALID(1'b0), + .S_AXIL_BREADY(1'b0), + .S_AXIL_RREADY(1'b0), + .S_AXIL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXIL_WSTRB({1'b1,1'b1,1'b1,1'b1}), + .S_AXIL_WVALID(1'b0), + .S_AXIS_TDATA(axis_linemem_single_0_m_axis_TDATA), + .S_AXIS_TLAST(axis_linemem_single_0_m_axis_TLAST), + .S_AXIS_TREADY(axis_linemem_single_0_m_axis_TREADY), + .S_AXIS_TUSER(axis_linemem_single_0_m_axis_TUSER), + .S_AXIS_TVALID(axis_linemem_single_0_m_axis_TVALID)); + design_1_clk_rst_generator_0_0 clk_rst_generator_0 + (.clk(Net), + .rst_n(Net1), + .stop_simulation(axis_slave_simmodel_0_FINISHED)); +endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml new file mode 100644 index 0000000..b368867 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml @@ -0,0 +1,870 @@ + + + xilinx.com + module_ref + axis_video_filter + 1.0 + + + M_AXIS + + + + + + + TDATA + + + M_AXIS_TDATA + + + + + TLAST + + + M_AXIS_TLAST + + + + + TUSER + + + M_AXIS_TUSER + + + + + TVALID + + + M_AXIS_TVALID + + + + + TREADY + + + M_AXIS_TREADY + + + + + + S_AXIS + + + + + + + TDATA + + + S_AXIS_TDATA + + + + + TLAST + + + S_AXIS_TLAST + + + + + TUSER + + + S_AXIS_TUSER + + + + + TVALID + + + S_AXIS_TVALID + + + + + TREADY + + + S_AXIS_TREADY + + + + + + S_AXIL + + + + + + + + + AWADDR + + + S_AXIL_AWADDR + + + + + AWVALID + + + S_AXIL_AWVALID + + + + + AWREADY + + + S_AXIL_AWREADY + + + + + WDATA + + + S_AXIL_WDATA + + + + + WSTRB + + + S_AXIL_WSTRB + + + + + WVALID + + + S_AXIL_WVALID + + + + + WREADY + + + S_AXIL_WREADY + + + + + BRESP + + + S_AXIL_BRESP + + + + + BVALID + + + S_AXIL_BVALID + + + + + BREADY + + + S_AXIL_BREADY + + + + + ARADDR + + + S_AXIL_ARADDR + + + + + ARVALID + + + S_AXIL_ARVALID + + + + + ARREADY + + + S_AXIL_ARREADY + + + + + RDATA + + + S_AXIL_RDATA + + + + + RRESP + + + S_AXIL_RRESP + + + + + RVALID + + + S_AXIL_RVALID + + + + + RREADY + + + S_AXIL_RREADY + + + + + + ARESETN + + + + + + + RST + + + ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + ACLK + + + + + + + CLK + + + ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS:S_AXIL + + + ASSOCIATED_RESET + ARESETN + + + + + + + S_AXIL + S_AXIL + + reg0 + reg0 + 0x0 + 0x8000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_video_filter + + + viewChecksum + 9f5bf2d9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_video_filter + + + viewChecksum + 9f5bf2d9 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + + + ACLK + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ARESETN + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIS_TDATA + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIS_TUSER + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + M_AXIS_TUSER + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_AWADDR + + in + + 14 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIL_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIL_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + S_AXIL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_ARADDR + + in + + 14 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXIL_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + S_AXIL_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXIL_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + S_AXIL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + COEFF_WIDTH + Coeff Width + 8 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_xpgui_view_fileset + + xgui/axis_video_filter_v1_0.tcl + tclSource + CHECKSUM_7f403de5 + XGUI_VERSION_2 + + + + xilinx.com:module_ref:axis_video_filter:1.0 + + + COEFF_WIDTH + Coeff Width + 8 + + + Component_Name + axis_video_filter_v1_0 + + + + + + zynq + + + /UserIP + + axis_video_filter_v1_0 + level_1 + module_ref + + IPI + + 1 + 2024-12-09T23:45:17Z + + + 2023.1 + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/xgui/axis_video_filter_v1_0.tcl b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/xgui/axis_video_filter_v1_0.tcl new file mode 100644 index 0000000..97c74ab --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/xgui/axis_video_filter_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "COEFF_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.COEFF_WIDTH { PARAM_VALUE.COEFF_WIDTH } { + # Procedure called to update COEFF_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.COEFF_WIDTH { PARAM_VALUE.COEFF_WIDTH } { + # Procedure called to validate COEFF_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.COEFF_WIDTH { MODELPARAM_VALUE.COEFF_WIDTH PARAM_VALUE.COEFF_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.COEFF_WIDTH}] ${MODELPARAM_VALUE.COEFF_WIDTH} +} + diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd new file mode 100644 index 0000000..04a8d5c --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd @@ -0,0 +1,799 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x29EA2656194EC7BE", + "device": "xc7z020clg400-1", + "gen_directory": "../../../../milestone6.gen/sources_1/bd/design_1", + "name": "design_1", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2023.1", + "validated": "true" + }, + "design_tree": { + "axis_slave_simmodel_0": "", + "clk_rst_generator_0": "", + "axil_master_with_rom_0": "", + "axis_master_simmodel_0": "", + "axis_downsizer_0": "", + "axis_linemem_single_0": "", + "axis_upsizer_0": "", + "axis_video_filter_0": "" + }, + "interface_ports": { + "m_axi_lite": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "32" + }, + "ARUSER_WIDTH": { + "value": "0", + "value_src": "const_prop" + }, + "AWUSER_WIDTH": { + "value": "0", + "value_src": "const_prop" + }, + "BUSER_WIDTH": { + "value": "0", + "value_src": "const_prop" + }, + "DATA_WIDTH": { + "value": "32" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_BRESP": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_BURST": { + "value": "0" + }, + "HAS_CACHE": { + "value": "0" + }, + "HAS_LOCK": { + "value": "0" + }, + "HAS_PROT": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_QOS": { + "value": "0" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_WSTRB": { + "value": "1", + "value_src": "const_prop" + }, + "ID_WIDTH": { + "value": "0", + "value_src": "const_prop" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "1", + "value_src": "auto_prop" + }, + "NUM_READ_OUTSTANDING": { + "value": "1", + "value_src": "auto_prop" + }, + "NUM_READ_THREADS": { + "value": "1", + "value_src": "default" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1", + "value_src": "auto_prop" + }, + "NUM_WRITE_THREADS": { + "value": "1", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI4LITE" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE", + "value_src": "const_prop" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "default" + }, + "RUSER_WIDTH": { + "value": "0", + "value_src": "const_prop" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0", + "value_src": "auto_prop" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "default" + }, + "WUSER_WIDTH": { + "value": "0", + "value_src": "const_prop" + } + }, + "memory_map_ref": "m_axi_lite", + "port_maps": { + "AWADDR": { + "physical_name": "m_axi_lite_awaddr", + "direction": "O", + "left": "31", + "right": "0" + }, + "AWPROT": { + "physical_name": "m_axi_lite_awprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "AWVALID": { + "physical_name": "m_axi_lite_awvalid", + "direction": "O" + }, + "AWREADY": { + "physical_name": "m_axi_lite_awready", + "direction": "I" + }, + "WDATA": { + "physical_name": "m_axi_lite_wdata", + "direction": "O", + "left": "31", + "right": "0" + }, + "WSTRB": { + "physical_name": "m_axi_lite_wstrb", + "direction": "O", + "left": "3", + "right": "0" + }, + "WVALID": { + "physical_name": "m_axi_lite_wvalid", + "direction": "O" + }, + "WREADY": { + "physical_name": "m_axi_lite_wready", + "direction": "I" + }, + "BRESP": { + "physical_name": "m_axi_lite_bresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "m_axi_lite_bvalid", + "direction": "I" + }, + "BREADY": { + "physical_name": "m_axi_lite_bready", + "direction": "O" + }, + "ARADDR": { + "physical_name": "m_axi_lite_araddr", + "direction": "O", + "left": "31", + "right": "0" + }, + "ARPROT": { + "physical_name": "m_axi_lite_arprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "ARVALID": { + "physical_name": "m_axi_lite_arvalid", + "direction": "O" + }, + "ARREADY": { + "physical_name": "m_axi_lite_arready", + "direction": "I" + }, + "RDATA": { + "physical_name": "m_axi_lite_rdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "RRESP": { + "physical_name": "m_axi_lite_rresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "RVALID": { + "physical_name": "m_axi_lite_rvalid", + "direction": "I" + }, + "RREADY": { + "physical_name": "m_axi_lite_rready", + "direction": "O" + } + } + } + }, + "components": { + "axis_slave_simmodel_0": { + "vlnv": "Gehrke:user:axis_slave_simmodel:1.0", + "xci_name": "design_1_axis_slave_simmodel_0_0", + "xci_path": "ip\\design_1_axis_slave_simmodel_0_0\\design_1_axis_slave_simmodel_0_0.xci", + "inst_hier_path": "axis_slave_simmodel_0", + "parameters": { + "FILE_NAME": { + "value": "../../../../tst_out" + }, + "NUM_LINES": { + "value": "192" + }, + "NUM_PIX_PER_LINE": { + "value": "192" + }, + "PIXEL_FORMAT": { + "value": "13" + } + } + }, + "clk_rst_generator_0": { + "vlnv": "wg:user:clk_rst_generator:1.0", + "xci_name": "design_1_clk_rst_generator_0_0", + "xci_path": "ip\\design_1_clk_rst_generator_0_0\\design_1_clk_rst_generator_0_0.xci", + "inst_hier_path": "clk_rst_generator_0", + "parameters": { + "HAS_CLK_INPUT": { + "value": "false" + }, + "HAS_RESET_INPUT": { + "value": "false" + } + } + }, + "axil_master_with_rom_0": { + "vlnv": "wg:user:axil_master_with_rom:1.0", + "xci_name": "design_1_axil_master_with_rom_0_0", + "xci_path": "ip\\design_1_axil_master_with_rom_0_0\\design_1_axil_master_with_rom_0_0.xci", + "inst_hier_path": "axil_master_with_rom_0", + "parameters": { + "HAS_INTERRUPT_IN": { + "value": "false" + } + }, + "interface_ports": { + "M_AXIL": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "M_AXIL", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "M_AXIL": { + "range": "4G", + "width": "32" + } + } + } + }, + "axis_master_simmodel_0": { + "vlnv": "Gehrke:user:axis_master_simmodel:1.0", + "xci_name": "design_1_axis_master_simmodel_0_0", + "xci_path": "ip\\design_1_axis_master_simmodel_0_0\\design_1_axis_master_simmodel_0_0.xci", + "inst_hier_path": "axis_master_simmodel_0", + "parameters": { + "FILE_NAME": { + "value": "../../../../Moewe-192x192" + }, + "NUM_LINES": { + "value": "192" + }, + "NUM_PIX_PER_LINE": { + "value": "192" + }, + "PIXEL_FORMAT": { + "value": "13" + } + } + }, + "axis_downsizer_0": { + "vlnv": "xilinx.com:user:axis_downsizer:1.0", + "xci_name": "design_1_axis_downsizer_0_0", + "xci_path": "ip\\design_1_axis_downsizer_0_0\\design_1_axis_downsizer_0_0.xci", + "inst_hier_path": "axis_downsizer_0", + "parameters": { + "SIZE_FACTOR": { + "value": "4" + } + } + }, + "axis_linemem_single_0": { + "vlnv": "xilinx.com:user:axis_linemem_single_master:1.0", + "xci_name": "design_1_axis_linemem_single_0_0", + "xci_path": "ip\\design_1_axis_linemem_single_0_0\\design_1_axis_linemem_single_0_0.xci", + "inst_hier_path": "axis_linemem_single_0", + "parameters": { + "DATA_WIDTH": { + "value": "8" + } + } + }, + "axis_upsizer_0": { + "vlnv": "xilinx.com:user:axis_upsizer:1.0", + "xci_name": "design_1_axis_upsizer_0_0", + "xci_path": "ip\\design_1_axis_upsizer_0_0\\design_1_axis_upsizer_0_0.xci", + "inst_hier_path": "axis_upsizer_0", + "parameters": { + "SIZE_FACTOR": { + "value": "4" + } + } + }, + "axis_video_filter_0": { + "vlnv": "xilinx.com:module_ref:axis_video_filter:1.0", + "xci_name": "design_1_axis_video_filter_0_0", + "xci_path": "ip\\design_1_axis_video_filter_0_0\\design_1_axis_video_filter_0_0.xci", + "inst_hier_path": "axis_video_filter_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "axis_video_filter", + "boundary_crc": "0x0" + }, + "interface_ports": { + "M_AXIS": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "1", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "M_AXIS_TDATA", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "M_AXIS_TLAST", + "direction": "O" + }, + "TUSER": { + "physical_name": "M_AXIS_TUSER", + "direction": "O" + }, + "TVALID": { + "physical_name": "M_AXIS_TVALID", + "direction": "O" + }, + "TREADY": { + "physical_name": "M_AXIS_TREADY", + "direction": "I" + } + } + }, + "S_AXIS": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "3", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "3", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "S_AXIS_TDATA", + "direction": "I", + "left": "23", + "right": "0" + }, + "TLAST": { + "physical_name": "S_AXIS_TLAST", + "direction": "I" + }, + "TUSER": { + "physical_name": "S_AXIS_TUSER", + "direction": "I", + "left": "2", + "right": "0" + }, + "TVALID": { + "physical_name": "S_AXIS_TVALID", + "direction": "I" + }, + "TREADY": { + "physical_name": "S_AXIS_TREADY", + "direction": "O" + } + } + }, + "S_AXIL": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "DATA_WIDTH": { + "value": "32", + "value_src": "constant" + }, + "PROTOCOL": { + "value": "AXI4LITE", + "value_src": "constant" + }, + "ID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "ADDR_WIDTH": { + "value": "15", + "value_src": "constant" + }, + "AWUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "ARUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "WUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "RUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "BUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE", + "value_src": "constant" + }, + "HAS_BURST": { + "value": "0", + "value_src": "constant" + }, + "HAS_LOCK": { + "value": "0", + "value_src": "constant" + }, + "HAS_PROT": { + "value": "0", + "value_src": "constant" + }, + "HAS_CACHE": { + "value": "0", + "value_src": "constant" + }, + "HAS_QOS": { + "value": "0", + "value_src": "constant" + }, + "HAS_REGION": { + "value": "0", + "value_src": "constant" + }, + "HAS_WSTRB": { + "value": "1", + "value_src": "constant" + }, + "HAS_BRESP": { + "value": "1", + "value_src": "constant" + }, + "HAS_RRESP": { + "value": "1", + "value_src": "constant" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0", + "value_src": "auto" + }, + "NUM_READ_OUTSTANDING": { + "value": "1", + "value_src": "auto" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1", + "value_src": "auto" + }, + "MAX_BURST_LENGTH": { + "value": "1", + "value_src": "auto" + } + }, + "memory_map_ref": "S_AXIL", + "port_maps": { + "AWADDR": { + "physical_name": "S_AXIL_AWADDR", + "direction": "I", + "left": "14", + "right": "0" + }, + "AWVALID": { + "physical_name": "S_AXIL_AWVALID", + "direction": "I" + }, + "AWREADY": { + "physical_name": "S_AXIL_AWREADY", + "direction": "O" + }, + "WDATA": { + "physical_name": "S_AXIL_WDATA", + "direction": "I", + "left": "31", + "right": "0" + }, + "WSTRB": { + "physical_name": "S_AXIL_WSTRB", + "direction": "I", + "left": "3", + "right": "0" + }, + "WVALID": { + "physical_name": "S_AXIL_WVALID", + "direction": "I" + }, + "WREADY": { + "physical_name": "S_AXIL_WREADY", + "direction": "O" + }, + "BRESP": { + "physical_name": "S_AXIL_BRESP", + "direction": "O", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "S_AXIL_BVALID", + "direction": "O" + }, + "BREADY": { + "physical_name": "S_AXIL_BREADY", + "direction": "I" + }, + "ARADDR": { + "physical_name": "S_AXIL_ARADDR", + "direction": "I", + "left": "14", + "right": "0" + }, + "ARVALID": { + "physical_name": "S_AXIL_ARVALID", + "direction": "I" + }, + "ARREADY": { + "physical_name": "S_AXIL_ARREADY", + "direction": "O" + }, + "RDATA": { + "physical_name": "S_AXIL_RDATA", + "direction": "O", + "left": "31", + "right": "0" + }, + "RRESP": { + "physical_name": "S_AXIL_RRESP", + "direction": "O", + "left": "1", + "right": "0" + }, + "RVALID": { + "physical_name": "S_AXIL_RVALID", + "direction": "O" + }, + "RREADY": { + "physical_name": "S_AXIL_RREADY", + "direction": "I" + } + } + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXIS:S_AXIS:S_AXIL", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "ARESETN", + "value_src": "constant" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + } + }, + "interface_nets": { + "axil_master_with_rom_0_M_AXIL": { + "interface_ports": [ + "axil_master_with_rom_0/M_AXIL", + "m_axi_lite" + ] + }, + "axis_downsizer_0_M_AXIS": { + "interface_ports": [ + "axis_downsizer_0/M_AXIS", + "axis_linemem_single_0/s_axis" + ] + }, + "axis_linemem_single_0_m_axis": { + "interface_ports": [ + "axis_linemem_single_0/m_axis", + "axis_video_filter_0/S_AXIS" + ] + }, + "axis_master_simmodel_0_M_AXIS": { + "interface_ports": [ + "axis_master_simmodel_0/M_AXIS", + "axis_downsizer_0/S_AXIS" + ] + }, + "axis_upsizer_0_M_AXIS": { + "interface_ports": [ + "axis_upsizer_0/M_AXIS", + "axis_slave_simmodel_0/S_AXIS" + ] + }, + "axis_video_filter_0_M_AXIS": { + "interface_ports": [ + "axis_video_filter_0/M_AXIS", + "axis_upsizer_0/S_AXIS" + ] + } + }, + "nets": { + "Net": { + "ports": [ + "clk_rst_generator_0/clk", + "axil_master_with_rom_0/M_AXIL_ACLK", + "axis_slave_simmodel_0/S_AXIS_ACLK", + "axis_master_simmodel_0/ACLK", + "axis_downsizer_0/AXIS_ACLK", + "axis_linemem_single_0/aclk", + "axis_upsizer_0/AXIS_ACLK", + "axis_video_filter_0/ACLK" + ] + }, + "Net1": { + "ports": [ + "clk_rst_generator_0/rst_n", + "axis_upsizer_0/AXIS_ARESETN", + "axis_slave_simmodel_0/S_AXIS_ARESETN", + "axil_master_with_rom_0/M_AXIL_ARESETN", + "axis_master_simmodel_0/ARESETN", + "axis_linemem_single_0/aresetn", + "axis_downsizer_0/AXIS_ARESETN", + "axis_video_filter_0/ARESETN" + ] + }, + "axis_slave_simmodel_0_FINISHED": { + "ports": [ + "axis_slave_simmodel_0/FINISHED", + "clk_rst_generator_0/stop_simulation" + ] + } + }, + "addressing": { + "/": { + "memory_maps": { + "m_axi_lite": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "16", + "usage": "register" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci new file mode 100644 index 0000000..4f1e30a --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci @@ -0,0 +1,172 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_axil_master_with_rom_0_0", + "cell_name": "axil_master_with_rom_0", + "component_reference": "wg:user:axil_master_with_rom:1.0", + "ip_revision": "19", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0", + "parameters": { + "component_parameters": { + "STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "user", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ], + "HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "HAS_INTERRUPT_IN": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REVISION_NO": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ] + }, + "model_parameters": { + "STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "generated", "usage": "all" } ], + "HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "HAS_INTERRUPT_IN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "REVISION_NO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "19" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "M_AXIL_ACLK": [ { "direction": "in" } ], + "M_AXIL_ARESETN": [ { "direction": "in", "driver_value": "1" } ], + "M_AXIL_ARREADY": [ { "direction": "in", "driver_value": "0" } ], + "M_AXIL_ARVALID": [ { "direction": "out" } ], + "M_AXIL_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "M_AXIL_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "M_AXIL_RREADY": [ { "direction": "out" } ], + "M_AXIL_RVALID": [ { "direction": "in", "driver_value": "0" } ], + "M_AXIL_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "M_AXIL_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ], + "M_AXIL_AWREADY": [ { "direction": "in", "driver_value": "0" } ], + "M_AXIL_AWVALID": [ { "direction": "out" } ], + "M_AXIL_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "M_AXIL_AWPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "M_AXIL_WREADY": [ { "direction": "in", "driver_value": "0" } ], + "M_AXIL_WVALID": [ { "direction": "out" } ], + "M_AXIL_WDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "M_AXIL_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "M_AXIL_BREADY": [ { "direction": "out" } ], + "M_AXIL_BVALID": [ { "direction": "in", "driver_value": "0" } ], + "M_AXIL_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ] + }, + "interfaces": { + "M_AXIL": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "master", + "address_space_ref": "M_AXIL", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "M_AXIL_AWADDR" } ], + "AWPROT": [ { "physical_name": "M_AXIL_AWPROT" } ], + "AWVALID": [ { "physical_name": "M_AXIL_AWVALID" } ], + "AWREADY": [ { "physical_name": "M_AXIL_AWREADY" } ], + "WDATA": [ { "physical_name": "M_AXIL_WDATA" } ], + "WSTRB": [ { "physical_name": "M_AXIL_WSTRB" } ], + "WVALID": [ { "physical_name": "M_AXIL_WVALID" } ], + "WREADY": [ { "physical_name": "M_AXIL_WREADY" } ], + "BRESP": [ { "physical_name": "M_AXIL_BRESP" } ], + "BVALID": [ { "physical_name": "M_AXIL_BVALID" } ], + "BREADY": [ { "physical_name": "M_AXIL_BREADY" } ], + "ARADDR": [ { "physical_name": "M_AXIL_ARADDR" } ], + "ARPROT": [ { "physical_name": "M_AXIL_ARPROT" } ], + "ARVALID": [ { "physical_name": "M_AXIL_ARVALID" } ], + "ARREADY": [ { "physical_name": "M_AXIL_ARREADY" } ], + "RDATA": [ { "physical_name": "M_AXIL_RDATA" } ], + "RRESP": [ { "physical_name": "M_AXIL_RRESP" } ], + "RVALID": [ { "physical_name": "M_AXIL_RVALID" } ], + "RREADY": [ { "physical_name": "M_AXIL_RREADY" } ] + } + }, + "M_AXIL_ARESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "M_AXIL_ARESETN" } ] + } + }, + "M_AXIL_ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "M_AXIL_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "M_AXIL_ACLK" } ] + } + } + }, + "address_spaces": { + "M_AXIL": { + "range": "0x100000000", + "display_name": "M_AXIL", + "width": "32" + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xci new file mode 100644 index 0000000..c56ff51 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xci @@ -0,0 +1,148 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_axis_downsizer_0_0", + "cell_name": "axis_downsizer_0", + "component_reference": "xilinx.com:user:axis_downsizer:1.0", + "ip_revision": "2", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0", + "parameters": { + "component_parameters": { + "WIDTH_OUT": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SIZE_FACTOR": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BIG_ENDIAN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_axis_downsizer_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "WIDTH_OUT": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SIZE_FACTOR": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "BIG_ENDIAN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "2" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "AXIS_ACLK": [ { "direction": "in" } ], + "AXIS_ARESETN": [ { "direction": "in" } ], + "S_AXIS_TVALID": [ { "direction": "in" } ], + "S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0" } ], + "S_AXIS_TREADY": [ { "direction": "out" } ], + "S_AXIS_TUSER": [ { "direction": "in", "driver_value": "0" } ], + "M_AXIS_TVALID": [ { "direction": "out" } ], + "M_AXIS_TDATA": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], + "M_AXIS_TLAST": [ { "direction": "out" } ], + "M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ], + "M_AXIS_TUSER": [ { "direction": "out" } ] + }, + "interfaces": { + "M_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "M_AXIS_TDATA" } ], + "TLAST": [ { "physical_name": "M_AXIS_TLAST" } ], + "TUSER": [ { "physical_name": "M_AXIS_TUSER" } ], + "TVALID": [ { "physical_name": "M_AXIS_TVALID" } ], + "TREADY": [ { "physical_name": "M_AXIS_TREADY" } ] + } + }, + "S_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "S_AXIS_TDATA" } ], + "TLAST": [ { "physical_name": "S_AXIS_TLAST" } ], + "TUSER": [ { "physical_name": "S_AXIS_TUSER" } ], + "TVALID": [ { "physical_name": "S_AXIS_TVALID" } ], + "TREADY": [ { "physical_name": "S_AXIS_TREADY" } ] + } + }, + "AXIS_ARESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "AXIS_ARESETN" } ] + } + }, + "AXIS_ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "AXIS_ACLK" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xci new file mode 100644 index 0000000..fe94044 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xci @@ -0,0 +1,150 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_axis_linemem_single_0_0", + "cell_name": "axis_linemem_single_0", + "component_reference": "xilinx.com:user:axis_linemem_single_master:1.0", + "ip_revision": "17", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0", + "parameters": { + "component_parameters": { + "MAX_LINELEN": [ { "value": "2048", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_LINES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_axis_linemem_single_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "MAX_LINELEN": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_LINES": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "17" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in" } ], + "aresetn": [ { "direction": "in" } ], + "s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axis_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0" } ], + "s_axis_tlast": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axis_tready": [ { "direction": "out" } ], + "s_axis_tuser": [ { "direction": "in", "size_left": "0", "size_right": "0" } ], + "m_axis_tvalid": [ { "direction": "out" } ], + "m_axis_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0" } ], + "m_axis_tlast": [ { "direction": "out" } ], + "m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ], + "m_axis_tuser": [ { "direction": "out", "size_left": "2", "size_right": "0" } ] + }, + "interfaces": { + "m_axis": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "3", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_tdata" } ], + "TLAST": [ { "physical_name": "m_axis_tlast" } ], + "TUSER": [ { "physical_name": "m_axis_tuser" } ], + "TVALID": [ { "physical_name": "m_axis_tvalid" } ], + "TREADY": [ { "physical_name": "m_axis_tready" } ] + } + }, + "s_axis": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "s_axis_tdata" } ], + "TLAST": [ { "physical_name": "s_axis_tlast" } ], + "TUSER": [ { "physical_name": "s_axis_tuser" } ], + "TVALID": [ { "physical_name": "s_axis_tvalid" } ], + "TREADY": [ { "physical_name": "s_axis_tready" } ] + } + }, + "aresetn": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + }, + "aclk": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "m_axis:s_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xci new file mode 100644 index 0000000..2717d8d --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xci @@ -0,0 +1,148 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_axis_master_simmodel_0_0", + "cell_name": "axis_master_simmodel_0", + "component_reference": "Gehrke:user:axis_master_simmodel:1.0", + "ip_revision": "10", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0", + "parameters": { + "component_parameters": { + "FRAMING_VAL_B_U": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FRAMING_VAL_G_Y": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FRAMING_VAL_R_V": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FRAMING_LINES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FRAMING_PIXELS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ALPHA_VALUE": [ { "value": "255", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PIXEL_FORMAT": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RANDOM_TVALID": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_FRAMES_PER_FILE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_LINES": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_PIX_PER_LINE": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FILE_AUTONUMBERING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "FILE_EXTENSION": [ { "value": "bmp", "resolve_type": "user", "usage": "all" } ], + "FILE_NAME": [ { "value": "../../../../Moewe-192x192", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TUSERWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FIFO_REQUEST_TRESHOLD": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FIFO_AWIDTH": [ { "value": "11", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_FIFO_INTERFACE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_axis_master_simmodel_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "HAS_FIFO_INTERFACE": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "FIFO_AWIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FIFO_REQUEST_TRESHOLD": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "TUSERWIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FILE_NAME": [ { "value": "../../../../Moewe-192x192", "resolve_type": "generated", "usage": "all" } ], + "FILE_EXTENSION": [ { "value": "bmp", "resolve_type": "generated", "usage": "all" } ], + "FILE_AUTONUMBERING": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "NUM_PIX_PER_LINE": [ { "value": "192", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_LINES": [ { "value": "192", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_FRAMES_PER_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "RANDOM_TVALID": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "PIXEL_FORMAT": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "ALPHA_VALUE": [ { "value": "255", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FRAMING_PIXELS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FRAMING_LINES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FRAMING_VAL_R_V": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FRAMING_VAL_G_Y": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FRAMING_VAL_B_U": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "10" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "ACLK": [ { "direction": "in" } ], + "ARESETN": [ { "direction": "in" } ], + "FINISHED": [ { "direction": "out" } ], + "M_AXIS_TVALID": [ { "direction": "out" } ], + "M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "M_AXIS_TLAST": [ { "direction": "out" } ], + "M_AXIS_TREADY": [ { "direction": "in" } ], + "M_AXIS_TUSER": [ { "direction": "out", "size_left": "0", "size_right": "0" } ] + }, + "interfaces": { + "M_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "M_AXIS_TDATA" } ], + "TLAST": [ { "physical_name": "M_AXIS_TLAST" } ], + "TUSER": [ { "physical_name": "M_AXIS_TUSER" } ], + "TVALID": [ { "physical_name": "M_AXIS_TVALID" } ], + "TREADY": [ { "physical_name": "M_AXIS_TREADY" } ] + } + }, + "signal_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "ARESETN" } ] + } + }, + "signal_clock": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "ACLK" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xci new file mode 100644 index 0000000..a97e672 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xci @@ -0,0 +1,135 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_axis_slave_simmodel_0_0", + "cell_name": "axis_slave_simmodel_0", + "component_reference": "Gehrke:user:axis_slave_simmodel:1.0", + "ip_revision": "4", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0", + "parameters": { + "component_parameters": { + "RANDOM_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "FRAMING_LINES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FRAMING_PIXELS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_FILES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_FRAMES_PER_FILE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_LINES": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_PIX_PER_LINE": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PIXEL_FORMAT": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FILE_AUTONUMBERING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "FILE_EXTENSION": [ { "value": "bmp", "resolve_type": "user", "usage": "all" } ], + "FILE_NAME": [ { "value": "../../../../tst_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TUSERWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_axis_slave_simmodel_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "TUSERWIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FILE_NAME": [ { "value": "../../../../tst_out", "resolve_type": "generated", "usage": "all" } ], + "FILE_EXTENSION": [ { "value": "bmp", "resolve_type": "generated", "usage": "all" } ], + "FILE_AUTONUMBERING": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "PIXEL_FORMAT": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_PIX_PER_LINE": [ { "value": "192", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_LINES": [ { "value": "192", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_FRAMES_PER_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_FILES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FRAMING_PIXELS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FRAMING_LINES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "RANDOM_TREADY": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "4" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "FINISHED": [ { "direction": "out" } ], + "S_AXIS_ACLK": [ { "direction": "in" } ], + "S_AXIS_ARESETN": [ { "direction": "in" } ], + "S_AXIS_TVALID": [ { "direction": "in" } ], + "S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0" } ], + "S_AXIS_TLAST": [ { "direction": "in" } ], + "S_AXIS_TREADY": [ { "direction": "out" } ], + "S_AXIS_TUSER": [ { "direction": "in", "size_left": "0", "size_right": "0" } ] + }, + "interfaces": { + "S_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "S_AXIS_TDATA" } ], + "TLAST": [ { "physical_name": "S_AXIS_TLAST" } ], + "TUSER": [ { "physical_name": "S_AXIS_TUSER" } ], + "TVALID": [ { "physical_name": "S_AXIS_TVALID" } ], + "TREADY": [ { "physical_name": "S_AXIS_TREADY" } ] + } + }, + "S_AXIS_signal_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "S_AXIS_ARESETN" } ] + } + }, + "S_AXIS_signal_clock": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "S_AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "S_AXIS_ACLK" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xci new file mode 100644 index 0000000..b4e8a1b --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xci @@ -0,0 +1,148 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_axis_upsizer_0_0", + "cell_name": "axis_upsizer_0", + "component_reference": "xilinx.com:user:axis_upsizer:1.0", + "ip_revision": "3", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0", + "parameters": { + "component_parameters": { + "WIDTH_IN": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SIZE_FACTOR": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BIG_ENDIAN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_axis_upsizer_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "WIDTH_IN": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SIZE_FACTOR": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "BIG_ENDIAN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "3" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "AXIS_ACLK": [ { "direction": "in" } ], + "AXIS_ARESETN": [ { "direction": "in" } ], + "S_AXIS_TVALID": [ { "direction": "in" } ], + "S_AXIS_TDATA": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0" } ], + "S_AXIS_TREADY": [ { "direction": "out" } ], + "S_AXIS_TUSER": [ { "direction": "in", "driver_value": "0" } ], + "M_AXIS_TVALID": [ { "direction": "out" } ], + "M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "M_AXIS_TLAST": [ { "direction": "out" } ], + "M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ], + "M_AXIS_TUSER": [ { "direction": "out" } ] + }, + "interfaces": { + "M_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "M_AXIS_TDATA" } ], + "TLAST": [ { "physical_name": "M_AXIS_TLAST" } ], + "TUSER": [ { "physical_name": "M_AXIS_TUSER" } ], + "TVALID": [ { "physical_name": "M_AXIS_TVALID" } ], + "TREADY": [ { "physical_name": "M_AXIS_TREADY" } ] + } + }, + "S_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "S_AXIS_TDATA" } ], + "TLAST": [ { "physical_name": "S_AXIS_TLAST" } ], + "TUSER": [ { "physical_name": "S_AXIS_TUSER" } ], + "TVALID": [ { "physical_name": "S_AXIS_TVALID" } ], + "TREADY": [ { "physical_name": "S_AXIS_TREADY" } ] + } + }, + "AXIS_ARESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "AXIS_ARESETN" } ] + } + }, + "AXIS_ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "AXIS_ACLK" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xci new file mode 100644 index 0000000..2dade27 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xci @@ -0,0 +1,232 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_axis_video_filter_0_0", + "cell_name": "axis_video_filter_0", + "component_reference": "xilinx.com:module_ref:axis_video_filter:1.0", + "ip_revision": "1", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0", + "parameters": { + "component_parameters": { + "COEFF_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_axis_video_filter_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "COEFF_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "1" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ] + } + }, + "boundary": { + "ports": { + "ACLK": [ { "direction": "in" } ], + "ARESETN": [ { "direction": "in" } ], + "S_AXIS_TVALID": [ { "direction": "in", "driver_value": "0x0" } ], + "S_AXIS_TDATA": [ { "direction": "in", "size_left": "23", "size_right": "0", "driver_value": "0" } ], + "S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ], + "S_AXIS_TREADY": [ { "direction": "out" } ], + "S_AXIS_TUSER": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "M_AXIS_TVALID": [ { "direction": "out" } ], + "M_AXIS_TDATA": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], + "M_AXIS_TLAST": [ { "direction": "out" } ], + "M_AXIS_TREADY": [ { "direction": "in", "driver_value": "0x1" } ], + "M_AXIS_TUSER": [ { "direction": "out" } ], + "S_AXIL_AWADDR": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ], + "S_AXIL_AWVALID": [ { "direction": "in", "driver_value": "0x0" } ], + "S_AXIL_AWREADY": [ { "direction": "out" } ], + "S_AXIL_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "S_AXIL_WVALID": [ { "direction": "in", "driver_value": "0x0" } ], + "S_AXIL_WREADY": [ { "direction": "out" } ], + "S_AXIL_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "S_AXIL_BVALID": [ { "direction": "out" } ], + "S_AXIL_BREADY": [ { "direction": "in", "driver_value": "0x1" } ], + "S_AXIL_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "S_AXIL_ARADDR": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ], + "S_AXIL_ARVALID": [ { "direction": "in", "driver_value": "0x0" } ], + "S_AXIL_ARREADY": [ { "direction": "out" } ], + "S_AXIL_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "S_AXIL_RVALID": [ { "direction": "out" } ], + "S_AXIL_RREADY": [ { "direction": "in", "driver_value": "0x1" } ], + "S_AXIL_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ] + }, + "interfaces": { + "M_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "M_AXIS_TDATA" } ], + "TLAST": [ { "physical_name": "M_AXIS_TLAST" } ], + "TUSER": [ { "physical_name": "M_AXIS_TUSER" } ], + "TVALID": [ { "physical_name": "M_AXIS_TVALID" } ], + "TREADY": [ { "physical_name": "M_AXIS_TREADY" } ] + } + }, + "S_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "S_AXIS_TDATA" } ], + "TLAST": [ { "physical_name": "S_AXIS_TLAST" } ], + "TUSER": [ { "physical_name": "S_AXIS_TUSER" } ], + "TVALID": [ { "physical_name": "S_AXIS_TVALID" } ], + "TREADY": [ { "physical_name": "S_AXIS_TREADY" } ] + } + }, + "S_AXIL": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "memory_map_ref": "S_AXIL", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "15", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "S_AXIL_AWADDR" } ], + "AWVALID": [ { "physical_name": "S_AXIL_AWVALID" } ], + "AWREADY": [ { "physical_name": "S_AXIL_AWREADY" } ], + "WDATA": [ { "physical_name": "S_AXIL_WDATA" } ], + "WSTRB": [ { "physical_name": "S_AXIL_WSTRB" } ], + "WVALID": [ { "physical_name": "S_AXIL_WVALID" } ], + "WREADY": [ { "physical_name": "S_AXIL_WREADY" } ], + "BRESP": [ { "physical_name": "S_AXIL_BRESP" } ], + "BVALID": [ { "physical_name": "S_AXIL_BVALID" } ], + "BREADY": [ { "physical_name": "S_AXIL_BREADY" } ], + "ARADDR": [ { "physical_name": "S_AXIL_ARADDR" } ], + "ARVALID": [ { "physical_name": "S_AXIL_ARVALID" } ], + "ARREADY": [ { "physical_name": "S_AXIL_ARREADY" } ], + "RDATA": [ { "physical_name": "S_AXIL_RDATA" } ], + "RRESP": [ { "physical_name": "S_AXIL_RRESP" } ], + "RVALID": [ { "physical_name": "S_AXIL_RVALID" } ], + "RREADY": [ { "physical_name": "S_AXIL_RREADY" } ] + } + }, + "ARESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "ARESETN" } ] + } + }, + "ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS:S_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "ACLK" } ] + } + } + }, + "memory_maps": { + "S_AXIL": { + "display_name": "S_AXIL", + "address_blocks": { + "reg0": { + "base_address": "0x0", + "range": "0x8000", + "display_name": "reg0", + "usage": "register" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci new file mode 100644 index 0000000..14081e9 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci @@ -0,0 +1,55 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_clk_rst_generator_0_0", + "cell_name": "clk_rst_generator_0", + "component_reference": "wg:user:clk_rst_generator:1.0", + "ip_revision": "7", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0", + "parameters": { + "component_parameters": { + "CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_CLK_INPUT": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "HAS_RESET_INPUT": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "HAS_CLK_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "HAS_RESET_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "7" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "clk": [ { "direction": "out" } ], + "rst_n": [ { "direction": "out" } ], + "stop_simulation": [ { "direction": "in", "driver_value": "0x0" } ] + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui new file mode 100644 index 0000000..5e491ac --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui @@ -0,0 +1,30 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.705882", + "Default View_TopLeft":"20,-153", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace port m_axi_lite -pg 1 -lvl 7 -x 1640 -y 80 -defaultsOSRD +preplace inst axis_slave_simmodel_0 -pg 1 -lvl 4 -x 1000 -y 320 -defaultsOSRD +preplace inst clk_rst_generator_0 -pg 1 -lvl 5 -x 1240 -y 320 -defaultsOSRD +preplace inst axil_master_with_rom_0 -pg 1 -lvl 6 -x 1490 -y 80 -defaultsOSRD +preplace inst axis_master_simmodel_0 -pg 1 -lvl 6 -x 1490 -y 200 -defaultsOSRD +preplace inst axis_downsizer_0 -pg 1 -lvl 1 -x 170 -y 110 -defaultsOSRD +preplace inst axis_linemem_single_0 -pg 1 -lvl 2 -x 450 -y 130 -defaultsOSRD +preplace inst axis_upsizer_0 -pg 1 -lvl 3 -x 730 -y 300 -defaultsOSRD +preplace inst axis_video_filter_0 -pg 1 -lvl 2 -x 450 -y 280 -defaultsOSRD +preplace netloc Net 1 0 6 40 190 310 370 600 380 860 230 NJ 230 1350J +preplace netloc Net1 1 0 6 30 30 300 380 590 390 870 240 N 240 1360 +preplace netloc axis_slave_simmodel_0_FINISHED 1 4 1 N 320 +preplace netloc axil_master_with_rom_0_M_AXIL 1 6 1 N 80 +preplace netloc axis_downsizer_0_M_AXIS 1 1 1 N 110 +preplace netloc axis_linemem_single_0_m_axis 1 1 2 320 50 580 +preplace netloc axis_master_simmodel_0_M_AXIS 1 0 7 40 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 1620 +preplace netloc axis_upsizer_0_M_AXIS 1 3 1 N 300 +preplace netloc axis_video_filter_0_M_AXIS 1 2 1 N 280 +levelinfo -pg 1 0 170 450 730 1000 1240 1490 1640 +pagesize -pg 1 -db -bbox -sgen 0 0 1760 400 +" +} +0 diff --git a/Milestone6/milestone6/milestone6.xpr b/Milestone6/milestone6/milestone6.xpr index cc8efc8..07f7c3d 100644 --- a/Milestone6/milestone6/milestone6.xpr +++ b/Milestone6/milestone6/milestone6.xpr @@ -48,6 +48,7 @@ + + + + + + + + + + + + + + @@ -125,9 +139,10 @@ +