diff --git a/Milestone3/es-milestone3/es-milestone3.xpr b/Milestone3/es-milestone3/es-milestone3.xpr
index a7b66bc..c587f89 100644
--- a/Milestone3/es-milestone3/es-milestone3.xpr
+++ b/Milestone3/es-milestone3/es-milestone3.xpr
@@ -4,7 +4,7 @@
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
 <!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="63" Path="Z:/Praktika/Elektronische Systeme/es-praktikum/Milestone3/es-milestone3/es-milestone3.xpr">
+<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="ac364057cd1843739edfb55c505ac94b"/>
@@ -103,27 +103,27 @@
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
         </FileInfo>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xci">
+          <Proxy FileSetName="design_1_axis_audio_stereo2mo_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xci">
+          <Proxy FileSetName="design_1_axis_audio_mono2ster_0_0"/>
+        </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xci">
           <Proxy FileSetName="design_1_zybo_audio_0_0"/>
         </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci">
+          <Proxy FileSetName="design_1_axis_prog_audio_filt_0_1"/>
+        </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci">
           <Proxy FileSetName="design_1_clk_rst_generator_0_0"/>
         </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci">
           <Proxy FileSetName="design_1_axil_master_with_rom_0_0"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xci">
-          <Proxy FileSetName="design_1_axis_audio_mono2ster_0_0"/>
-        </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci">
           <Proxy FileSetName="design_1_system_ila_0_0"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xci">
-          <Proxy FileSetName="design_1_axis_audio_stereo2mo_0_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci">
-          <Proxy FileSetName="design_1_axis_prog_audio_filt_0_1"/>
-        </CompFileExtendedInfo>
       </File>
       <File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
         <FileInfo>
@@ -186,14 +186,6 @@
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
-      <File Path="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedInSteps" Val="synth_1"/>
-          <Attr Name="AutoDcp" Val="1"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -332,9 +324,7 @@
     </Run>
     <Run Id="design_1_axis_prog_audio_filt_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_axis_prog_audio_filt_0_1" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_prog_audio_filt_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axis_prog_audio_filt_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -464,9 +454,7 @@
     </Run>
     <Run Id="design_1_axis_prog_audio_filt_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_prog_audio_filt_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axis_prog_audio_filt_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
diff --git a/Milestone6/axis_video_filter.vhd b/Milestone6/axis_video_filter.vhd
index 69ff729..a0f3d48 100644
--- a/Milestone6/axis_video_filter.vhd
+++ b/Milestone6/axis_video_filter.vhd
@@ -13,14 +13,14 @@ entity axis_video_filter is
  port (
     ACLK                : in  std_logic;
     ARESETN             : in  std_logic;
-    
+
     -- AXI Streaming Target Port (from linemem)
     S_AXIS_TVALID       : in  std_logic := '0';
-    S_AXIS_TDATA        : in  std_logic_vector(23 downto 0); --drei Pixel 
+    S_AXIS_TDATA        : in  std_logic_vector(23 downto 0); --drei Pixel
     S_AXIS_TLAST        : in  std_logic := '0'; --letztes Pixel
-    S_AXIS_TREADY       : out std_logic; 
+    S_AXIS_TREADY       : out std_logic;
     S_AXIS_TUSER        : in  std_logic_vector(2 downto 0); --ertes Pixel
-    
+
     -- AXI Streaming Initiator Port
 
     M_AXIS_TVALID       : out std_logic;
@@ -28,17 +28,17 @@ entity axis_video_filter is
     M_AXIS_TLAST        : out std_logic;
     M_AXIS_TREADY       : in  std_logic := '1';
     M_AXIS_TUSER        : out std_logic;
-        
-        
+
+
         -- AXI-Lite Slave Interface (from/to CPU)
     S_AXIL_AWADDR       : in  std_logic_vector(14 downto 0) := (others=>'0');
     S_AXIL_AWVALID      : in  std_logic := '0';
     S_AXIL_AWREADY      : out std_logic;
     S_AXIL_WDATA        : in  std_logic_vector(31 downto 0) := (others=>'0');
     S_AXIL_WVALID       : in  std_logic := '0';
-    S_AXIL_WREADY       : out std_logic;    
-    S_AXIL_WSTRB        : in  std_logic_vector( 3 downto 0) := (others=>'0');    
-    S_AXIL_BVALID       : out std_logic;    
+    S_AXIL_WREADY       : out std_logic;
+    S_AXIL_WSTRB        : in  std_logic_vector( 3 downto 0) := (others=>'0');
+    S_AXIL_BVALID       : out std_logic;
     S_AXIL_BREADY       : in  std_logic := '1';
     S_AXIL_BRESP        : out std_logic_vector( 1 downto 0);
     S_AXIL_ARADDR       : in  std_logic_vector(14 downto 0) := (others=>'0');
@@ -48,7 +48,7 @@ entity axis_video_filter is
     S_AXIL_RVALID       : out std_logic;
     S_AXIL_RREADY       : in  std_logic := '1';
     S_AXIL_RRESP        : out std_logic_vector( 1 downto 0)
-    );  
+    );
 end;
 
 
@@ -60,16 +60,16 @@ architecture rtl of axis_video_filter is
     constant wPixelSigned : integer := wPixel+1;
     constant wRowProd     : integer := wPixelSigned + wCoeff + 2;
     constant wFilterRes   : integer := wRowProd+1 + 2;
-    
+
     signal   m_valid_sig1 : std_logic;
     signal   m_valid_sig2 : std_logic;
     signal   m_last_sig1  : std_logic;
     signal   m_user_sig1  : std_logic;
-    
+
     signal   row1Result   : signed(wRowProd-1 downto 0);
     signal   row2Result   : signed(wRowProd-1 downto 0);
     signal   row3Result   : signed(wRowProd-1 downto 0);
-    
+
     signal   coeff_11     : signed(wCoeff-1 downto 0);
     signal   coeff_12     : signed(wCoeff-1 downto 0);
     signal   coeff_13     : signed(wCoeff-1 downto 0);
@@ -79,7 +79,7 @@ architecture rtl of axis_video_filter is
     signal   coeff_31     : signed(wCoeff-1 downto 0);
     signal   coeff_32     : signed(wCoeff-1 downto 0);
     signal   coeff_33     : signed(wCoeff-1 downto 0);
-    
+
     signal   shiftAmount  : unsigned(wShift-1 downto 0);
 
 
@@ -91,7 +91,7 @@ begin
     -----------------------
     -- Filter Kernel
     -----------------------
-    process 
+    process
         variable data_11         : signed (wPixelSigned-1 downto 0);
         variable data_12         : signed (wPixelSigned-1 downto 0);
         variable data_13         : signed (wPixelSigned-1 downto 0);
@@ -102,7 +102,7 @@ begin
         variable data_32         : signed (wPixelSigned-1 downto 0);
         variable data_33         : signed (wPixelSigned-1 downto 0);
         variable filterResult    : signed (wFilterRes-1 downto 0);
-    
+
     begin
         wait until rising_edge (ACLK);
         if ARESETN = '0' then
@@ -119,26 +119,26 @@ begin
                 data_31 := data_32;
                 data_32 := data_33;
                 data_33 := signed("0"&S_AXIS_TDATA(wPixel*1-1 downto wPixel*0));
-            
+
                 row1Result <= resize(data_11*coeff_11,wRowProd) + resize(data_12*coeff_12,wRowProd) + resize(data_13*coeff_13,wRowProd);
                 row2Result <= resize(data_21*coeff_21,wRowProd) + resize(data_22*coeff_22,wRowProd) + resize(data_23*coeff_23,wRowProd);
                 row3Result <= resize(data_31*coeff_31,wRowProd) + resize(data_32*coeff_32,wRowProd) + resize(data_33*coeff_33,wRowProd);
-                                        
+
                 m_last_sig1  <= S_AXIS_TLAST;
                 m_user_sig1  <= S_AXIS_TUSER(1);
                 m_valid_sig1 <= S_AXIS_TVALID;
             end if;
-            
-            if M_AXIS_TREADY = '1' or m_valid_sig2='0' then 
-                filterResult := resize(row1Result,wFilterRes)+resize(row2Result,wFilterRes)+resize(row3Result,wFilterRes);         
+
+            if M_AXIS_TREADY = '1' or m_valid_sig2='0' then
+                filterResult := resize(row1Result,wFilterRes)+resize(row2Result,wFilterRes)+resize(row3Result,wFilterRes);
                 filterResult := shift_right(filterResult, to_integer(shiftAmount));
-                
+
                 if (filterResult < 0)   then
                     filterResult := to_signed(0,wFilterRes);
                 elsif (filterResult > 255) then
                     filterResult := to_signed(255,wFilterRes);
                 end if;
-                
+
                 M_AXIS_TDATA   <= std_logic_vector(filterResult(7 downto 0));
                 M_AXIS_TVALID  <= m_valid_sig1;
                 M_AXIS_TLAST   <= m_last_sig1;
@@ -151,93 +151,83 @@ begin
 
 
 
------------------------
--- AXI-Lite Interface
------------------------
+    -----------------------
+    -- AXI-Lite Interface
+    -----------------------
 
-S_AXIL_AWREADY  <= '1';
-S_AXIL_WREADY   <= '1';    
-S_AXIL_BRESP    <= "00";
-S_AXIL_ARREADY  <= '1';
-S_AXIL_RRESP    <= "00";
+    S_AXIL_BRESP   <= (others=>'0');    -- No write errors
+    S_AXIL_RRESP   <= (others=>'0');    -- No read errors
+    S_AXIL_ARREADY <= '1';              -- IP is always ready
+    S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
+    S_AXIL_WREADY  <= S_AXIL_AWVALID and S_AXIL_WVALID;
 
-process begin
-    wait until rising_edge (ACLK);
-         
-    if ARESETN = '0' then
-        S_AXIL_BVALID  <= '0';
-        S_AXIL_RVALID  <= '0';
-        coeff_11 <= (others=>'0');
-        coeff_12 <= (others=>'0');
-        coeff_13 <= (others=>'0');
-        coeff_21 <= (others=>'0');
-        coeff_22 <= (0=>'1',others=>'0');
-        coeff_23 <= (others=>'0');
-        coeff_31 <= (others=>'0');
-        coeff_32 <= (others=>'0');
-        coeff_33 <= (others=>'0');        
-                    coeff_11 <= to_signed(-1, wCoeff);
-                    coeff_12 <= to_signed(-1, wCoeff);
-                    coeff_13 <= to_signed(-1, wCoeff);
-                    coeff_21 <= to_signed(-1, wCoeff);
-                    coeff_22 <= to_signed(8, wCoeff);
-                    coeff_23 <= to_signed(-1, wCoeff);
-                    coeff_31 <= to_signed(-1, wCoeff);
-                    coeff_32 <= to_signed(-1, wCoeff);
-                    coeff_33 <= to_signed(-1, wCoeff);
+    process begin
+        wait until rising_edge (ACLK);
 
-        shiftAmount  <= to_unsigned(0,wShift);
-                    shiftAmount <= to_unsigned(3, wShift); -- Skalierung für die Summe der Koeffizienten
-    else
-        if S_AXIL_RREADY = '1' then
-            S_AXIL_RVALID  <= '0';
-        end if;
-        --Leselogik
-        if S_AXIL_ARVALID = '1' then
-            S_AXIL_RDATA   <= (others=>'0');
-            case (to_integer(unsigned(S_AXIL_ARADDR(5 downto 0)))) is 
-                when  0 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_11);
-                when  4 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_12);
-                when  8 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_13);
-                when 12 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_21);
-                when 16 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_22);
-                when 20 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_23);
-                when 24 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_31);
-                when 28 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_32);
-                when 32 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_33);
-                when 36 => S_AXIL_RDATA <= (31 downto 4 => '0') & std_logic_vector(shiftAmount);
-                when others => null;
-            end case;
-            S_AXIL_RVALID  <= '1';
-        end if;
-        
-        if S_AXIL_BREADY = '1' then
+        if ARESETN = '0' then
             S_AXIL_BVALID  <= '0';
-        end if;
-        --schreiblogik
-        if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then    
-            S_AXIL_BVALID  <= '1';
-            S_AXIL_RDATA   <= (others=>'0');
-            
-            --nur die unterseten sieben Bits werden benutzt 
-            if S_AXIL_WSTRB(0) = '1' then
-                case (to_integer(unsigned(S_AXIL_AWADDR(5 downto 0)))) is 
-                    when  0 => coeff_11(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));  
-                    when  4 => coeff_12(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));  
-                    when  8 => coeff_13(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));  
-                    when 12 => coeff_21(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));  
-                    when 16 => coeff_22(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));  
-                    when 20 => coeff_23(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));  
-                    when 24 => coeff_31(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));  
-                    when 28 => coeff_32(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));  
-                    when 32 => coeff_33(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));  
-                    when 36 => shiftAmount(3 downto 0) <= unsigned(S_AXIL_WDATA(3 downto 0));
+            S_AXIL_RVALID  <= '0';
+            coeff_11 <= (others=>'0');
+            coeff_12 <= (others=>'0');
+            coeff_13 <= (others=>'0');
+            coeff_21 <= (others=>'0');
+            coeff_22 <= (0=>'1',others=>'0');
+            coeff_23 <= (others=>'0');
+            coeff_31 <= (others=>'0');
+            coeff_32 <= (others=>'0');
+            coeff_33 <= (others=>'0');
+
+            shiftAmount  <= to_unsigned(0,wShift); -- Skalierung für die Summe der Koeffizienten
+        else
+            if S_AXIL_RREADY = '1' then
+                S_AXIL_RVALID  <= '0';
+            end if;
+            --Leselogik
+            if S_AXIL_ARVALID = '1' then
+                S_AXIL_RDATA   <= (others=>'0');
+                case (to_integer(unsigned(S_AXIL_ARADDR(5 downto 0)))) is
+                    when  0 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_11);
+                    when  4 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_12);
+                    when  8 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_13);
+                    when 12 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_21);
+                    when 16 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_22);
+                    when 20 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_23);
+                    when 24 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_31);
+                    when 28 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_32);
+                    when 32 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_33);
+                    when 36 => S_AXIL_RDATA <= (31 downto 4 => '0') & std_logic_vector(shiftAmount);
                     when others => null;
                 end case;
+                S_AXIL_RVALID  <= '1';
+            end if;
+
+            if S_AXIL_BREADY = '1' then
+                S_AXIL_BVALID  <= '0';
+            end if;
+            --schreiblogik
+            if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
+                S_AXIL_BVALID  <= '1';
+                S_AXIL_RDATA   <= (others=>'0');
+
+                --nur die unterseten sieben Bits werden benutzt
+                if S_AXIL_WSTRB(0) = '1' then
+                    case (to_integer(unsigned(S_AXIL_AWADDR(5 downto 0)))) is
+                        when  0 => coeff_11(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));
+                        when  4 => coeff_12(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));
+                        when  8 => coeff_13(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));
+                        when 12 => coeff_21(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));
+                        when 16 => coeff_22(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));
+                        when 20 => coeff_23(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));
+                        when 24 => coeff_31(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));
+                        when 28 => coeff_32(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));
+                        when 32 => coeff_33(7 downto 0)    <= signed(S_AXIL_WDATA(7 downto 0));
+                        when 36 => shiftAmount(3 downto 0) <= unsigned(S_AXIL_WDATA(3 downto 0));
+                        when others => null;
+                    end case;
+                end if;
             end if;
         end if;
-    end if;
-end process;
+    end process;
 
 
 
diff --git a/Milestone6/milestone6/.gitignore b/Milestone6/milestone6/.gitignore
index 424e122..6afe45b 100644
--- a/Milestone6/milestone6/.gitignore
+++ b/Milestone6/milestone6/.gitignore
@@ -83,4 +83,7 @@
 # ignore Vivado log files
 *.log
 *.jou
-vivado_pid*.str
\ No newline at end of file
+vivado_pid*.str
+
+# DO NOT ignore images as bitmap files
+!*.bmp
\ No newline at end of file
diff --git a/Milestone6/milestone6/Moewe-192x192.bmp b/Milestone6/milestone6/Moewe-192x192.bmp
new file mode 100644
index 0000000..9de09ed
Binary files /dev/null and b/Milestone6/milestone6/Moewe-192x192.bmp differ
diff --git a/Milestone6/milestone6/design_1_wrapper_behav.wcfg b/Milestone6/milestone6/design_1_wrapper_behav.wcfg
new file mode 100644
index 0000000..96f108d
--- /dev/null
+++ b/Milestone6/milestone6/design_1_wrapper_behav.wcfg
@@ -0,0 +1,37 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="design_1_wrapper_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="bmp_pkg" />
+            <top_module name="design_1_wrapper" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="1,417.118 ns"></ZoomStartTime>
+      <ZoomEndTime time="1,477.093 ns"></ZoomEndTime>
+      <Cursor1Time time="1,506.598 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="437"></NameColumnWidth>
+      <ValueColumnWidth column_width="116"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="1" />
+   <wvobject fp_name="/design_1_wrapper/design_1_i/SIM_Enviroment/axil_master_with_rom_0/M_AXIL" type="protoinst">
+      <obj_property name="children_use_element_short_name">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
+      <obj_property name="EnumTransactionColorTable">0=blank 1=#D399FF 2=pink</obj_property>
+      <obj_property name="EnumTransactionValueTable">0=blank;1=Read;2=Write;3=Read/Write</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">turquoise</obj_property>
+      <obj_property name="Render_Data">/design_1_wrapper/design_1_i/SIM_Enviroment/axil_master_with_rom_0/M_AXIL.readWriteSummary</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      <obj_property name="CellHeight">36</obj_property>
+      <obj_property name="ElementShortName">M_AXIL</obj_property>
+      <obj_property name="ObjectShortName">M_AXIL</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+   </wvobject>
+</wave_config>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml
index 5d07ea8..a86951e 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml
@@ -2,19 +2,18 @@
 <Root MajorVersion="0" MinorVersion="40">
   <CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
     <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1733831252"/>
-    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1733831253"/>
-    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1733831252"/>
-    <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1733831253"/>
+    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1733850802"/>
+    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1733850803"/>
+    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1733850802"/>
+    <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1733850803"/>
     <FileCollection Name="SOURCES" Type="SOURCES">
-      <File Name="synth\design_1.v" Type="Verilog">
+      <File Name="synth\design_1.vhd" Type="VHDL">
         <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
         <Library Name="xil_defaultlib"/>
         <UsedIn Val="SYNTHESIS"/>
-        <UsedIn Val="IMPLEMENTATION"/>
         <ProcessingOrder Val="NORMAL"/>
       </File>
-      <File Name="sim\design_1.v" Type="Verilog">
+      <File Name="sim\design_1.vhd" Type="VHDL">
         <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
         <Library Name="xil_defaultlib"/>
         <UsedIn Val="SIMULATION"/>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
deleted file mode 100644
index 4654857..0000000
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
+++ /dev/null
@@ -1,19 +0,0 @@
-//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-//--------------------------------------------------------------------------------
-//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
-//Date        : Tue Dec 10 12:47:32 2024
-//Host        : Bastistablet running 64-bit major release  (build 9200)
-//Command     : generate_target design_1_wrapper.bd
-//Design      : design_1_wrapper
-//Purpose     : IP block netlist
-//--------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-module design_1_wrapper
-   ();
-
-
-  design_1 design_1_i
-       ();
-endmodule
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
new file mode 100644
index 0000000..76fa85b
--- /dev/null
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
@@ -0,0 +1,24 @@
+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+--Date        : Tue Dec 10 18:13:22 2024
+--Host        : BiermannSurface running 64-bit major release  (build 9200)
+--Command     : generate_target design_1_wrapper.bd
+--Design      : design_1_wrapper
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity design_1_wrapper is
+end design_1_wrapper;
+
+architecture STRUCTURE of design_1_wrapper is
+  component design_1 is
+  end component design_1;
+begin
+design_1_i: component design_1
+ ;
+end STRUCTURE;
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml
index deffabc..078a2cc 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml
@@ -577,11 +577,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 09:02:19 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:9a9349f5</spirit:value>
+            <spirit:value>9:a028aa16</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -597,11 +597,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 16:53:35 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:9a9349f5</spirit:value>
+            <spirit:value>9:a028aa16</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xml
index 3fdffbd..9eed8b0 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xml
@@ -464,11 +464,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 09:02:19 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:b4dbaa33</spirit:value>
+            <spirit:value>9:f5576235</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -484,11 +484,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 16:53:35 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:b4dbaa33</spirit:value>
+            <spirit:value>9:f5576235</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xml
index 0739695..1ebbc00 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xml
@@ -464,11 +464,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 09:02:19 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:c744c730</spirit:value>
+            <spirit:value>9:7ddccb10</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -484,11 +484,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 16:53:35 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:c744c730</spirit:value>
+            <spirit:value>9:7ddccb10</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xml
index a22dd0d..f5bac01 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xml
@@ -298,11 +298,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 09:02:19 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:82169cab</spirit:value>
+            <spirit:value>9:216770ec</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -318,11 +318,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 16:53:35 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:82169cab</spirit:value>
+            <spirit:value>9:216770ec</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xml
index a671ca0..edbd375 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xml
@@ -293,11 +293,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 09:02:19 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:ff3fc857</spirit:value>
+            <spirit:value>9:3352134c</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -313,11 +313,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 16:53:34 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:ff3fc857</spirit:value>
+            <spirit:value>9:3352134c</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xml
index 197e1d4..1370813 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xml
@@ -464,11 +464,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 09:02:19 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:8a86da2c</spirit:value>
+            <spirit:value>9:42bb2862</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -484,11 +484,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 16:53:35 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:8a86da2c</spirit:value>
+            <spirit:value>9:42bb2862</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml
index cfea191..36a14fe 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml
@@ -902,27 +902,27 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:4ec30ce6</spirit:value>
+            <spirit:value>9:8c885d99</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
       <spirit:view>
-        <spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
-        <spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
-        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
-        <spirit:language>verilog</spirit:language>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
         <spirit:modelName>design_1_axis_video_filter_1_1</spirit:modelName>
         <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
         </spirit:fileSetRef>
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Dec 10 11:47:32 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 17:13:22 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:4ec30ce6</spirit:value>
+            <spirit:value>9:8c885d99</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1376,10 +1376,10 @@
   </spirit:choices>
   <spirit:fileSets>
     <spirit:fileSet>
-      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
       <spirit:file>
-        <spirit:name>sim/design_1_axis_video_filter_1_1.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:name>sim/design_1_axis_video_filter_1_1.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
     </spirit:fileSet>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.v
deleted file mode 100644
index a7fee97..0000000
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.v
+++ /dev/null
@@ -1,187 +0,0 @@
-// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of AMD and is protected under U.S. and international copyright
-// and other intellectual property laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// AMD, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) AMD shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or AMD had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// AMD products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of AMD products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:module_ref:axis_video_filter:1.0
-// IP Revision: 1
-
-`timescale 1ns/1ps
-
-(* IP_DEFINITION_SOURCE = "module_ref" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module design_1_axis_video_filter_1_1 (
-  ACLK,
-  ARESETN,
-  S_AXIS_TVALID,
-  S_AXIS_TDATA,
-  S_AXIS_TLAST,
-  S_AXIS_TREADY,
-  S_AXIS_TUSER,
-  M_AXIS_TVALID,
-  M_AXIS_TDATA,
-  M_AXIS_TLAST,
-  M_AXIS_TREADY,
-  M_AXIS_TUSER,
-  S_AXIL_AWADDR,
-  S_AXIL_AWVALID,
-  S_AXIL_AWREADY,
-  S_AXIL_WDATA,
-  S_AXIL_WVALID,
-  S_AXIL_WREADY,
-  S_AXIL_WSTRB,
-  S_AXIL_BVALID,
-  S_AXIL_BREADY,
-  S_AXIL_BRESP,
-  S_AXIL_ARADDR,
-  S_AXIL_ARVALID,
-  S_AXIL_ARREADY,
-  S_AXIL_RDATA,
-  S_AXIL_RVALID,
-  S_AXIL_RREADY,
-  S_AXIL_RRESP
-);
-
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:S_AXIL, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ACLK CLK" *)
-input wire ACLK;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ARESETN RST" *)
-input wire ARESETN;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
-input wire S_AXIS_TVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
-input wire [23 : 0] S_AXIS_TDATA;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
-input wire S_AXIS_TLAST;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
-output wire S_AXIS_TREADY;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 3, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *)
-input wire [2 : 0] S_AXIS_TUSER;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
-output wire M_AXIS_TVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
-output wire [7 : 0] M_AXIS_TDATA;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
-output wire M_AXIS_TLAST;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
-input wire M_AXIS_TREADY;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *)
-output wire M_AXIS_TUSER;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR" *)
-input wire [14 : 0] S_AXIL_AWADDR;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID" *)
-input wire S_AXIL_AWVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY" *)
-output wire S_AXIL_AWREADY;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WDATA" *)
-input wire [31 : 0] S_AXIL_WDATA;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WVALID" *)
-input wire S_AXIL_WVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WREADY" *)
-output wire S_AXIL_WREADY;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB" *)
-input wire [3 : 0] S_AXIL_WSTRB;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL BVALID" *)
-output wire S_AXIL_BVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL BREADY" *)
-input wire S_AXIL_BREADY;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL BRESP" *)
-output wire [1 : 0] S_AXIL_BRESP;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR" *)
-input wire [14 : 0] S_AXIL_ARADDR;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID" *)
-input wire S_AXIL_ARVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY" *)
-output wire S_AXIL_ARREADY;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RDATA" *)
-output wire [31 : 0] S_AXIL_RDATA;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RVALID" *)
-output wire S_AXIL_RVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RREADY" *)
-input wire S_AXIL_RREADY;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\
-BITS_PER_BYTE 0, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RRESP" *)
-output wire [1 : 0] S_AXIL_RRESP;
-
-  axis_video_filter #(
-    .COEFF_WIDTH(8)
-  ) inst (
-    .ACLK(ACLK),
-    .ARESETN(ARESETN),
-    .S_AXIS_TVALID(S_AXIS_TVALID),
-    .S_AXIS_TDATA(S_AXIS_TDATA),
-    .S_AXIS_TLAST(S_AXIS_TLAST),
-    .S_AXIS_TREADY(S_AXIS_TREADY),
-    .S_AXIS_TUSER(S_AXIS_TUSER),
-    .M_AXIS_TVALID(M_AXIS_TVALID),
-    .M_AXIS_TDATA(M_AXIS_TDATA),
-    .M_AXIS_TLAST(M_AXIS_TLAST),
-    .M_AXIS_TREADY(M_AXIS_TREADY),
-    .M_AXIS_TUSER(M_AXIS_TUSER),
-    .S_AXIL_AWADDR(S_AXIL_AWADDR),
-    .S_AXIL_AWVALID(S_AXIL_AWVALID),
-    .S_AXIL_AWREADY(S_AXIL_AWREADY),
-    .S_AXIL_WDATA(S_AXIL_WDATA),
-    .S_AXIL_WVALID(S_AXIL_WVALID),
-    .S_AXIL_WREADY(S_AXIL_WREADY),
-    .S_AXIL_WSTRB(S_AXIL_WSTRB),
-    .S_AXIL_BVALID(S_AXIL_BVALID),
-    .S_AXIL_BREADY(S_AXIL_BREADY),
-    .S_AXIL_BRESP(S_AXIL_BRESP),
-    .S_AXIL_ARADDR(S_AXIL_ARADDR),
-    .S_AXIL_ARVALID(S_AXIL_ARVALID),
-    .S_AXIL_ARREADY(S_AXIL_ARREADY),
-    .S_AXIL_RDATA(S_AXIL_RDATA),
-    .S_AXIL_RVALID(S_AXIL_RVALID),
-    .S_AXIL_RREADY(S_AXIL_RREADY),
-    .S_AXIL_RRESP(S_AXIL_RRESP)
-  );
-endmodule
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.vhd
new file mode 100644
index 0000000..b8f44e7
--- /dev/null
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.vhd
@@ -0,0 +1,202 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:axis_video_filter:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axis_video_filter_1_1 IS
+  PORT (
+    ACLK : IN STD_LOGIC;
+    ARESETN : IN STD_LOGIC;
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    S_AXIS_TLAST : IN STD_LOGIC;
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    S_AXIS_TUSER : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    M_AXIS_TLAST : OUT STD_LOGIC;
+    M_AXIS_TREADY : IN STD_LOGIC;
+    M_AXIS_TUSER : OUT STD_LOGIC;
+    S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    S_AXIL_AWVALID : IN STD_LOGIC;
+    S_AXIL_AWREADY : OUT STD_LOGIC;
+    S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_WVALID : IN STD_LOGIC;
+    S_AXIL_WREADY : OUT STD_LOGIC;
+    S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXIL_BVALID : OUT STD_LOGIC;
+    S_AXIL_BREADY : IN STD_LOGIC;
+    S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    S_AXIL_ARVALID : IN STD_LOGIC;
+    S_AXIL_ARREADY : OUT STD_LOGIC;
+    S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_RVALID : OUT STD_LOGIC;
+    S_AXIL_RREADY : IN STD_LOGIC;
+    S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+  );
+END design_1_axis_video_filter_1_1;
+
+ARCHITECTURE design_1_axis_video_filter_1_1_arch OF design_1_axis_video_filter_1_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_video_filter_1_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_video_filter IS
+    GENERIC (
+      COEFF_WIDTH : INTEGER
+    );
+    PORT (
+      ACLK : IN STD_LOGIC;
+      ARESETN : IN STD_LOGIC;
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      S_AXIS_TUSER : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC;
+      M_AXIS_TUSER : OUT STD_LOGIC;
+      S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+      S_AXIL_AWVALID : IN STD_LOGIC;
+      S_AXIL_AWREADY : OUT STD_LOGIC;
+      S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_WVALID : IN STD_LOGIC;
+      S_AXIL_WREADY : OUT STD_LOGIC;
+      S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXIL_BVALID : OUT STD_LOGIC;
+      S_AXIL_BREADY : IN STD_LOGIC;
+      S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+      S_AXIL_ARVALID : IN STD_LOGIC;
+      S_AXIL_ARREADY : OUT STD_LOGIC;
+      S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_RVALID : OUT STD_LOGIC;
+      S_AXIL_RREADY : IN STD_LOGIC;
+      S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+    );
+  END COMPONENT axis_video_filter;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:S_AXIL, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_" & 
+"BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 3, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_video_filter
+    GENERIC MAP (
+      COEFF_WIDTH => 8
+    )
+    PORT MAP (
+      ACLK => ACLK,
+      ARESETN => ARESETN,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => S_AXIS_TLAST,
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      S_AXIS_TUSER => S_AXIS_TUSER,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TLAST => M_AXIS_TLAST,
+      M_AXIS_TREADY => M_AXIS_TREADY,
+      M_AXIS_TUSER => M_AXIS_TUSER,
+      S_AXIL_AWADDR => S_AXIL_AWADDR,
+      S_AXIL_AWVALID => S_AXIL_AWVALID,
+      S_AXIL_AWREADY => S_AXIL_AWREADY,
+      S_AXIL_WDATA => S_AXIL_WDATA,
+      S_AXIL_WVALID => S_AXIL_WVALID,
+      S_AXIL_WREADY => S_AXIL_WREADY,
+      S_AXIL_WSTRB => S_AXIL_WSTRB,
+      S_AXIL_BVALID => S_AXIL_BVALID,
+      S_AXIL_BREADY => S_AXIL_BREADY,
+      S_AXIL_BRESP => S_AXIL_BRESP,
+      S_AXIL_ARADDR => S_AXIL_ARADDR,
+      S_AXIL_ARVALID => S_AXIL_ARVALID,
+      S_AXIL_ARREADY => S_AXIL_ARREADY,
+      S_AXIL_RDATA => S_AXIL_RDATA,
+      S_AXIL_RVALID => S_AXIL_RVALID,
+      S_AXIL_RREADY => S_AXIL_RREADY,
+      S_AXIL_RRESP => S_AXIL_RRESP
+    );
+END design_1_axis_video_filter_1_1_arch;
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml
index 714a1bc..6e6bf5e 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml
@@ -17,11 +17,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 09:02:19 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:deff16df</spirit:value>
+            <spirit:value>9:bd1771be</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -37,11 +37,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
+            <spirit:value>Tue Dec 10 16:53:34 UTC 2024</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:deff16df</spirit:value>
+            <spirit:value>9:bd1771be</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.vhd
new file mode 100644
index 0000000..98274f7
--- /dev/null
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.vhd
@@ -0,0 +1,469 @@
+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+--Date        : Tue Dec 10 18:13:22 2024
+--Host        : BiermannSurface running 64-bit major release  (build 9200)
+--Command     : generate_target design_1.bd
+--Design      : design_1
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity SIM_Enviroment_imp_14W2BPY is
+  port (
+    M_AXIL_ACLK : out STD_LOGIC;
+    M_AXIL_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_arready : in STD_LOGIC;
+    M_AXIL_arvalid : out STD_LOGIC;
+    M_AXIL_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_awready : in STD_LOGIC;
+    M_AXIL_awvalid : out STD_LOGIC;
+    M_AXIL_bready : out STD_LOGIC;
+    M_AXIL_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXIL_bvalid : in STD_LOGIC;
+    M_AXIL_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_rready : out STD_LOGIC;
+    M_AXIL_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXIL_rvalid : in STD_LOGIC;
+    M_AXIL_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_wready : in STD_LOGIC;
+    M_AXIL_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXIL_wvalid : out STD_LOGIC;
+    M_AXIS_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIS_tlast : out STD_LOGIC;
+    M_AXIS_tready : in STD_LOGIC;
+    M_AXIS_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXIS_tvalid : out STD_LOGIC;
+    S_AXIS_ARESETN : out STD_LOGIC;
+    S_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIS_tlast : in STD_LOGIC;
+    S_AXIS_tready : out STD_LOGIC;
+    S_AXIS_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXIS_tvalid : in STD_LOGIC
+  );
+end SIM_Enviroment_imp_14W2BPY;
+
+architecture STRUCTURE of SIM_Enviroment_imp_14W2BPY is
+  component design_1_clk_rst_generator_0_0 is
+  port (
+    clk : out STD_LOGIC;
+    rst_n : out STD_LOGIC;
+    stop_simulation : in STD_LOGIC
+  );
+  end component design_1_clk_rst_generator_0_0;
+  component design_1_axis_master_simmodel_0_0 is
+  port (
+    ACLK : in STD_LOGIC;
+    ARESETN : in STD_LOGIC;
+    FINISHED : out STD_LOGIC;
+    M_AXIS_TVALID : out STD_LOGIC;
+    M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIS_TLAST : out STD_LOGIC;
+    M_AXIS_TREADY : in STD_LOGIC;
+    M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_axis_master_simmodel_0_0;
+  component design_1_axis_slave_simmodel_0_0 is
+  port (
+    FINISHED : out STD_LOGIC;
+    S_AXIS_ACLK : in STD_LOGIC;
+    S_AXIS_ARESETN : in STD_LOGIC;
+    S_AXIS_TVALID : in STD_LOGIC;
+    S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIS_TLAST : in STD_LOGIC;
+    S_AXIS_TREADY : out STD_LOGIC;
+    S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_axis_slave_simmodel_0_0;
+  component design_1_axil_master_with_rom_0_0 is
+  port (
+    M_AXIL_ACLK : in STD_LOGIC;
+    M_AXIL_ARESETN : in STD_LOGIC;
+    M_AXIL_ARREADY : in STD_LOGIC;
+    M_AXIL_ARVALID : out STD_LOGIC;
+    M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXIL_RREADY : out STD_LOGIC;
+    M_AXIL_RVALID : in STD_LOGIC;
+    M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXIL_AWREADY : in STD_LOGIC;
+    M_AXIL_AWVALID : out STD_LOGIC;
+    M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXIL_WREADY : in STD_LOGIC;
+    M_AXIL_WVALID : out STD_LOGIC;
+    M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXIL_BREADY : out STD_LOGIC;
+    M_AXIL_BVALID : in STD_LOGIC;
+    M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_axil_master_with_rom_0_0;
+  signal Net : STD_LOGIC;
+  signal Net1 : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
+  signal axis_slave_simmodel_0_FINISHED : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC;
+  signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal NLW_axis_master_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC;
+begin
+  M_AXIL_ACLK <= Net;
+  M_AXIL_araddr(31 downto 0) <= axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0);
+  M_AXIL_arvalid <= axil_master_with_rom_0_M_AXIL_ARVALID;
+  M_AXIL_awaddr(31 downto 0) <= axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0);
+  M_AXIL_awvalid <= axil_master_with_rom_0_M_AXIL_AWVALID;
+  M_AXIL_bready <= axil_master_with_rom_0_M_AXIL_BREADY;
+  M_AXIL_rready <= axil_master_with_rom_0_M_AXIL_RREADY;
+  M_AXIL_wdata(31 downto 0) <= axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0);
+  M_AXIL_wstrb(3 downto 0) <= axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0);
+  M_AXIL_wvalid <= axil_master_with_rom_0_M_AXIL_WVALID;
+  M_AXIS_tdata(31 downto 0) <= axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0);
+  M_AXIS_tlast <= axis_master_simmodel_0_M_AXIS_TLAST;
+  M_AXIS_tuser(0) <= axis_master_simmodel_0_M_AXIS_TUSER(0);
+  M_AXIS_tvalid <= axis_master_simmodel_0_M_AXIS_TVALID;
+  S_AXIS_ARESETN <= Net1;
+  S_AXIS_tready <= axis_upsizer_0_M_AXIS_TREADY;
+  axil_master_with_rom_0_M_AXIL_ARREADY <= M_AXIL_arready;
+  axil_master_with_rom_0_M_AXIL_AWREADY <= M_AXIL_awready;
+  axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0) <= M_AXIL_bresp(1 downto 0);
+  axil_master_with_rom_0_M_AXIL_BVALID <= M_AXIL_bvalid;
+  axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0) <= M_AXIL_rdata(31 downto 0);
+  axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0) <= M_AXIL_rresp(1 downto 0);
+  axil_master_with_rom_0_M_AXIL_RVALID <= M_AXIL_rvalid;
+  axil_master_with_rom_0_M_AXIL_WREADY <= M_AXIL_wready;
+  axis_master_simmodel_0_M_AXIS_TREADY <= M_AXIS_tready;
+  axis_upsizer_0_M_AXIS_TDATA(31 downto 0) <= S_AXIS_tdata(31 downto 0);
+  axis_upsizer_0_M_AXIS_TLAST <= S_AXIS_tlast;
+  axis_upsizer_0_M_AXIS_TUSER(0) <= S_AXIS_tuser(0);
+  axis_upsizer_0_M_AXIS_TVALID <= S_AXIS_tvalid;
+axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
+     port map (
+      M_AXIL_ACLK => Net,
+      M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
+      M_AXIL_ARESETN => Net1,
+      M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0),
+      M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
+      M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
+      M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
+      M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0),
+      M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
+      M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
+      M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
+      M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
+      M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
+      M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
+      M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
+      M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
+      M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
+      M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
+      M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
+      M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
+      M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID
+    );
+axis_master_simmodel_0: component design_1_axis_master_simmodel_0_0
+     port map (
+      ACLK => Net,
+      ARESETN => Net1,
+      FINISHED => NLW_axis_master_simmodel_0_FINISHED_UNCONNECTED,
+      M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
+      M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
+      M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
+      M_AXIS_TUSER(0) => axis_master_simmodel_0_M_AXIS_TUSER(0),
+      M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
+    );
+axis_slave_simmodel_0: component design_1_axis_slave_simmodel_0_0
+     port map (
+      FINISHED => axis_slave_simmodel_0_FINISHED,
+      S_AXIS_ACLK => Net,
+      S_AXIS_ARESETN => Net1,
+      S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
+      S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
+      S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
+      S_AXIS_TUSER(0) => axis_upsizer_0_M_AXIS_TUSER(0),
+      S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID
+    );
+clk_rst_generator_0: component design_1_clk_rst_generator_0_0
+     port map (
+      clk => Net,
+      rst_n => Net1,
+      stop_simulation => axis_slave_simmodel_0_FINISHED
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity design_1 is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
+end design_1;
+
+architecture STRUCTURE of design_1 is
+  component design_1_axis_downsizer_0_0 is
+  port (
+    AXIS_ACLK : in STD_LOGIC;
+    AXIS_ARESETN : in STD_LOGIC;
+    S_AXIS_TVALID : in STD_LOGIC;
+    S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIS_TLAST : in STD_LOGIC;
+    S_AXIS_TREADY : out STD_LOGIC;
+    S_AXIS_TUSER : in STD_LOGIC;
+    M_AXIS_TVALID : out STD_LOGIC;
+    M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    M_AXIS_TLAST : out STD_LOGIC;
+    M_AXIS_TREADY : in STD_LOGIC;
+    M_AXIS_TUSER : out STD_LOGIC
+  );
+  end component design_1_axis_downsizer_0_0;
+  component design_1_axis_linemem_single_0_0 is
+  port (
+    aclk : in STD_LOGIC;
+    aresetn : in STD_LOGIC;
+    s_axis_tvalid : in STD_LOGIC;
+    s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    s_axis_tlast : in STD_LOGIC;
+    s_axis_tready : out STD_LOGIC;
+    s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
+    m_axis_tvalid : out STD_LOGIC;
+    m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    m_axis_tlast : out STD_LOGIC;
+    m_axis_tready : in STD_LOGIC;
+    m_axis_tuser : out STD_LOGIC_VECTOR ( 2 downto 0 )
+  );
+  end component design_1_axis_linemem_single_0_0;
+  component design_1_axis_upsizer_0_0 is
+  port (
+    AXIS_ACLK : in STD_LOGIC;
+    AXIS_ARESETN : in STD_LOGIC;
+    S_AXIS_TVALID : in STD_LOGIC;
+    S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    S_AXIS_TLAST : in STD_LOGIC;
+    S_AXIS_TREADY : out STD_LOGIC;
+    S_AXIS_TUSER : in STD_LOGIC;
+    M_AXIS_TVALID : out STD_LOGIC;
+    M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIS_TLAST : out STD_LOGIC;
+    M_AXIS_TREADY : in STD_LOGIC;
+    M_AXIS_TUSER : out STD_LOGIC
+  );
+  end component design_1_axis_upsizer_0_0;
+  component design_1_axis_video_filter_1_1 is
+  port (
+    ACLK : in STD_LOGIC;
+    ARESETN : in STD_LOGIC;
+    S_AXIS_TVALID : in STD_LOGIC;
+    S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    S_AXIS_TLAST : in STD_LOGIC;
+    S_AXIS_TREADY : out STD_LOGIC;
+    S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXIS_TVALID : out STD_LOGIC;
+    M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    M_AXIS_TLAST : out STD_LOGIC;
+    M_AXIS_TREADY : in STD_LOGIC;
+    M_AXIS_TUSER : out STD_LOGIC;
+    S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 14 downto 0 );
+    S_AXIL_AWVALID : in STD_LOGIC;
+    S_AXIL_AWREADY : out STD_LOGIC;
+    S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIL_WVALID : in STD_LOGIC;
+    S_AXIL_WREADY : out STD_LOGIC;
+    S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXIL_BVALID : out STD_LOGIC;
+    S_AXIL_BREADY : in STD_LOGIC;
+    S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 14 downto 0 );
+    S_AXIL_ARVALID : in STD_LOGIC;
+    S_AXIL_ARREADY : out STD_LOGIC;
+    S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIL_RVALID : out STD_LOGIC;
+    S_AXIL_RREADY : in STD_LOGIC;
+    S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_axis_video_filter_1_1;
+  signal Net : STD_LOGIC;
+  signal Net1 : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
+  signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_downsizer_0_M_AXIS_TUSER : STD_LOGIC;
+  signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC;
+  signal axis_linemem_single_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal axis_linemem_single_0_m_axis_TLAST : STD_LOGIC;
+  signal axis_linemem_single_0_m_axis_TREADY : STD_LOGIC;
+  signal axis_linemem_single_0_m_axis_TUSER : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal axis_linemem_single_0_m_axis_TVALID : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC;
+  signal axis_video_filter_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal axis_video_filter_1_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_video_filter_1_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_video_filter_1_M_AXIS_TUSER : STD_LOGIC;
+  signal axis_video_filter_1_M_AXIS_TVALID : STD_LOGIC;
+begin
+SIM_Enviroment: entity work.SIM_Enviroment_imp_14W2BPY
+     port map (
+      M_AXIL_ACLK => Net,
+      M_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
+      M_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
+      M_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
+      M_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
+      M_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
+      M_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
+      M_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY,
+      M_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
+      M_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
+      M_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
+      M_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY,
+      M_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
+      M_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
+      M_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
+      M_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY,
+      M_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
+      M_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID,
+      M_AXIS_tdata(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
+      M_AXIS_tlast => axis_master_simmodel_0_M_AXIS_TLAST,
+      M_AXIS_tready => axis_master_simmodel_0_M_AXIS_TREADY,
+      M_AXIS_tuser(0) => axis_master_simmodel_0_M_AXIS_TUSER(0),
+      M_AXIS_tvalid => axis_master_simmodel_0_M_AXIS_TVALID,
+      S_AXIS_ARESETN => Net1,
+      S_AXIS_tdata(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
+      S_AXIS_tlast => axis_upsizer_0_M_AXIS_TLAST,
+      S_AXIS_tready => axis_upsizer_0_M_AXIS_TREADY,
+      S_AXIS_tuser(0) => axis_upsizer_0_M_AXIS_TUSER,
+      S_AXIS_tvalid => axis_upsizer_0_M_AXIS_TVALID
+    );
+axis_downsizer_0: component design_1_axis_downsizer_0_0
+     port map (
+      AXIS_ACLK => Net,
+      AXIS_ARESETN => Net1,
+      M_AXIS_TDATA(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0),
+      M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST,
+      M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY,
+      M_AXIS_TUSER => axis_downsizer_0_M_AXIS_TUSER,
+      M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID,
+      S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
+      S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
+      S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
+      S_AXIS_TUSER => axis_master_simmodel_0_M_AXIS_TUSER(0),
+      S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
+    );
+axis_linemem_single_0: component design_1_axis_linemem_single_0_0
+     port map (
+      aclk => Net,
+      aresetn => Net1,
+      m_axis_tdata(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0),
+      m_axis_tlast => axis_linemem_single_0_m_axis_TLAST,
+      m_axis_tready => axis_linemem_single_0_m_axis_TREADY,
+      m_axis_tuser(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0),
+      m_axis_tvalid => axis_linemem_single_0_m_axis_TVALID,
+      s_axis_tdata(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0),
+      s_axis_tlast => axis_downsizer_0_M_AXIS_TLAST,
+      s_axis_tready => axis_downsizer_0_M_AXIS_TREADY,
+      s_axis_tuser(0) => axis_downsizer_0_M_AXIS_TUSER,
+      s_axis_tvalid => axis_downsizer_0_M_AXIS_TVALID
+    );
+axis_upsizer_0: component design_1_axis_upsizer_0_0
+     port map (
+      AXIS_ACLK => Net,
+      AXIS_ARESETN => Net1,
+      M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
+      M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
+      M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
+      M_AXIS_TUSER => axis_upsizer_0_M_AXIS_TUSER,
+      M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
+      S_AXIS_TDATA(7 downto 0) => axis_video_filter_1_M_AXIS_TDATA(7 downto 0),
+      S_AXIS_TLAST => axis_video_filter_1_M_AXIS_TLAST,
+      S_AXIS_TREADY => axis_video_filter_1_M_AXIS_TREADY,
+      S_AXIS_TUSER => axis_video_filter_1_M_AXIS_TUSER,
+      S_AXIS_TVALID => axis_video_filter_1_M_AXIS_TVALID
+    );
+axis_video_filter_1: component design_1_axis_video_filter_1_1
+     port map (
+      ACLK => Net,
+      ARESETN => Net1,
+      M_AXIS_TDATA(7 downto 0) => axis_video_filter_1_M_AXIS_TDATA(7 downto 0),
+      M_AXIS_TLAST => axis_video_filter_1_M_AXIS_TLAST,
+      M_AXIS_TREADY => axis_video_filter_1_M_AXIS_TREADY,
+      M_AXIS_TUSER => axis_video_filter_1_M_AXIS_TUSER,
+      M_AXIS_TVALID => axis_video_filter_1_M_AXIS_TVALID,
+      S_AXIL_ARADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(14 downto 0),
+      S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
+      S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
+      S_AXIL_AWADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(14 downto 0),
+      S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
+      S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
+      S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
+      S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
+      S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
+      S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
+      S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
+      S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
+      S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
+      S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
+      S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
+      S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
+      S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
+      S_AXIS_TDATA(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0),
+      S_AXIS_TLAST => axis_linemem_single_0_m_axis_TLAST,
+      S_AXIS_TREADY => axis_linemem_single_0_m_axis_TREADY,
+      S_AXIS_TUSER(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0),
+      S_AXIS_TVALID => axis_linemem_single_0_m_axis_TVALID
+    );
+end STRUCTURE;
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.vhd b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.vhd
new file mode 100644
index 0000000..98274f7
--- /dev/null
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.vhd
@@ -0,0 +1,469 @@
+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+--Date        : Tue Dec 10 18:13:22 2024
+--Host        : BiermannSurface running 64-bit major release  (build 9200)
+--Command     : generate_target design_1.bd
+--Design      : design_1
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity SIM_Enviroment_imp_14W2BPY is
+  port (
+    M_AXIL_ACLK : out STD_LOGIC;
+    M_AXIL_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_arready : in STD_LOGIC;
+    M_AXIL_arvalid : out STD_LOGIC;
+    M_AXIL_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_awready : in STD_LOGIC;
+    M_AXIL_awvalid : out STD_LOGIC;
+    M_AXIL_bready : out STD_LOGIC;
+    M_AXIL_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXIL_bvalid : in STD_LOGIC;
+    M_AXIL_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_rready : out STD_LOGIC;
+    M_AXIL_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXIL_rvalid : in STD_LOGIC;
+    M_AXIL_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_wready : in STD_LOGIC;
+    M_AXIL_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXIL_wvalid : out STD_LOGIC;
+    M_AXIS_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIS_tlast : out STD_LOGIC;
+    M_AXIS_tready : in STD_LOGIC;
+    M_AXIS_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXIS_tvalid : out STD_LOGIC;
+    S_AXIS_ARESETN : out STD_LOGIC;
+    S_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIS_tlast : in STD_LOGIC;
+    S_AXIS_tready : out STD_LOGIC;
+    S_AXIS_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXIS_tvalid : in STD_LOGIC
+  );
+end SIM_Enviroment_imp_14W2BPY;
+
+architecture STRUCTURE of SIM_Enviroment_imp_14W2BPY is
+  component design_1_clk_rst_generator_0_0 is
+  port (
+    clk : out STD_LOGIC;
+    rst_n : out STD_LOGIC;
+    stop_simulation : in STD_LOGIC
+  );
+  end component design_1_clk_rst_generator_0_0;
+  component design_1_axis_master_simmodel_0_0 is
+  port (
+    ACLK : in STD_LOGIC;
+    ARESETN : in STD_LOGIC;
+    FINISHED : out STD_LOGIC;
+    M_AXIS_TVALID : out STD_LOGIC;
+    M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIS_TLAST : out STD_LOGIC;
+    M_AXIS_TREADY : in STD_LOGIC;
+    M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_axis_master_simmodel_0_0;
+  component design_1_axis_slave_simmodel_0_0 is
+  port (
+    FINISHED : out STD_LOGIC;
+    S_AXIS_ACLK : in STD_LOGIC;
+    S_AXIS_ARESETN : in STD_LOGIC;
+    S_AXIS_TVALID : in STD_LOGIC;
+    S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIS_TLAST : in STD_LOGIC;
+    S_AXIS_TREADY : out STD_LOGIC;
+    S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_axis_slave_simmodel_0_0;
+  component design_1_axil_master_with_rom_0_0 is
+  port (
+    M_AXIL_ACLK : in STD_LOGIC;
+    M_AXIL_ARESETN : in STD_LOGIC;
+    M_AXIL_ARREADY : in STD_LOGIC;
+    M_AXIL_ARVALID : out STD_LOGIC;
+    M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXIL_RREADY : out STD_LOGIC;
+    M_AXIL_RVALID : in STD_LOGIC;
+    M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXIL_AWREADY : in STD_LOGIC;
+    M_AXIL_AWVALID : out STD_LOGIC;
+    M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXIL_WREADY : in STD_LOGIC;
+    M_AXIL_WVALID : out STD_LOGIC;
+    M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXIL_BREADY : out STD_LOGIC;
+    M_AXIL_BVALID : in STD_LOGIC;
+    M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_axil_master_with_rom_0_0;
+  signal Net : STD_LOGIC;
+  signal Net1 : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
+  signal axis_slave_simmodel_0_FINISHED : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC;
+  signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal NLW_axis_master_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC;
+begin
+  M_AXIL_ACLK <= Net;
+  M_AXIL_araddr(31 downto 0) <= axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0);
+  M_AXIL_arvalid <= axil_master_with_rom_0_M_AXIL_ARVALID;
+  M_AXIL_awaddr(31 downto 0) <= axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0);
+  M_AXIL_awvalid <= axil_master_with_rom_0_M_AXIL_AWVALID;
+  M_AXIL_bready <= axil_master_with_rom_0_M_AXIL_BREADY;
+  M_AXIL_rready <= axil_master_with_rom_0_M_AXIL_RREADY;
+  M_AXIL_wdata(31 downto 0) <= axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0);
+  M_AXIL_wstrb(3 downto 0) <= axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0);
+  M_AXIL_wvalid <= axil_master_with_rom_0_M_AXIL_WVALID;
+  M_AXIS_tdata(31 downto 0) <= axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0);
+  M_AXIS_tlast <= axis_master_simmodel_0_M_AXIS_TLAST;
+  M_AXIS_tuser(0) <= axis_master_simmodel_0_M_AXIS_TUSER(0);
+  M_AXIS_tvalid <= axis_master_simmodel_0_M_AXIS_TVALID;
+  S_AXIS_ARESETN <= Net1;
+  S_AXIS_tready <= axis_upsizer_0_M_AXIS_TREADY;
+  axil_master_with_rom_0_M_AXIL_ARREADY <= M_AXIL_arready;
+  axil_master_with_rom_0_M_AXIL_AWREADY <= M_AXIL_awready;
+  axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0) <= M_AXIL_bresp(1 downto 0);
+  axil_master_with_rom_0_M_AXIL_BVALID <= M_AXIL_bvalid;
+  axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0) <= M_AXIL_rdata(31 downto 0);
+  axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0) <= M_AXIL_rresp(1 downto 0);
+  axil_master_with_rom_0_M_AXIL_RVALID <= M_AXIL_rvalid;
+  axil_master_with_rom_0_M_AXIL_WREADY <= M_AXIL_wready;
+  axis_master_simmodel_0_M_AXIS_TREADY <= M_AXIS_tready;
+  axis_upsizer_0_M_AXIS_TDATA(31 downto 0) <= S_AXIS_tdata(31 downto 0);
+  axis_upsizer_0_M_AXIS_TLAST <= S_AXIS_tlast;
+  axis_upsizer_0_M_AXIS_TUSER(0) <= S_AXIS_tuser(0);
+  axis_upsizer_0_M_AXIS_TVALID <= S_AXIS_tvalid;
+axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
+     port map (
+      M_AXIL_ACLK => Net,
+      M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
+      M_AXIL_ARESETN => Net1,
+      M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0),
+      M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
+      M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
+      M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
+      M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0),
+      M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
+      M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
+      M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
+      M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
+      M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
+      M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
+      M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
+      M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
+      M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
+      M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
+      M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
+      M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
+      M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID
+    );
+axis_master_simmodel_0: component design_1_axis_master_simmodel_0_0
+     port map (
+      ACLK => Net,
+      ARESETN => Net1,
+      FINISHED => NLW_axis_master_simmodel_0_FINISHED_UNCONNECTED,
+      M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
+      M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
+      M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
+      M_AXIS_TUSER(0) => axis_master_simmodel_0_M_AXIS_TUSER(0),
+      M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
+    );
+axis_slave_simmodel_0: component design_1_axis_slave_simmodel_0_0
+     port map (
+      FINISHED => axis_slave_simmodel_0_FINISHED,
+      S_AXIS_ACLK => Net,
+      S_AXIS_ARESETN => Net1,
+      S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
+      S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
+      S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
+      S_AXIS_TUSER(0) => axis_upsizer_0_M_AXIS_TUSER(0),
+      S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID
+    );
+clk_rst_generator_0: component design_1_clk_rst_generator_0_0
+     port map (
+      clk => Net,
+      rst_n => Net1,
+      stop_simulation => axis_slave_simmodel_0_FINISHED
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity design_1 is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
+end design_1;
+
+architecture STRUCTURE of design_1 is
+  component design_1_axis_downsizer_0_0 is
+  port (
+    AXIS_ACLK : in STD_LOGIC;
+    AXIS_ARESETN : in STD_LOGIC;
+    S_AXIS_TVALID : in STD_LOGIC;
+    S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIS_TLAST : in STD_LOGIC;
+    S_AXIS_TREADY : out STD_LOGIC;
+    S_AXIS_TUSER : in STD_LOGIC;
+    M_AXIS_TVALID : out STD_LOGIC;
+    M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    M_AXIS_TLAST : out STD_LOGIC;
+    M_AXIS_TREADY : in STD_LOGIC;
+    M_AXIS_TUSER : out STD_LOGIC
+  );
+  end component design_1_axis_downsizer_0_0;
+  component design_1_axis_linemem_single_0_0 is
+  port (
+    aclk : in STD_LOGIC;
+    aresetn : in STD_LOGIC;
+    s_axis_tvalid : in STD_LOGIC;
+    s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    s_axis_tlast : in STD_LOGIC;
+    s_axis_tready : out STD_LOGIC;
+    s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
+    m_axis_tvalid : out STD_LOGIC;
+    m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    m_axis_tlast : out STD_LOGIC;
+    m_axis_tready : in STD_LOGIC;
+    m_axis_tuser : out STD_LOGIC_VECTOR ( 2 downto 0 )
+  );
+  end component design_1_axis_linemem_single_0_0;
+  component design_1_axis_upsizer_0_0 is
+  port (
+    AXIS_ACLK : in STD_LOGIC;
+    AXIS_ARESETN : in STD_LOGIC;
+    S_AXIS_TVALID : in STD_LOGIC;
+    S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    S_AXIS_TLAST : in STD_LOGIC;
+    S_AXIS_TREADY : out STD_LOGIC;
+    S_AXIS_TUSER : in STD_LOGIC;
+    M_AXIS_TVALID : out STD_LOGIC;
+    M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXIS_TLAST : out STD_LOGIC;
+    M_AXIS_TREADY : in STD_LOGIC;
+    M_AXIS_TUSER : out STD_LOGIC
+  );
+  end component design_1_axis_upsizer_0_0;
+  component design_1_axis_video_filter_1_1 is
+  port (
+    ACLK : in STD_LOGIC;
+    ARESETN : in STD_LOGIC;
+    S_AXIS_TVALID : in STD_LOGIC;
+    S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    S_AXIS_TLAST : in STD_LOGIC;
+    S_AXIS_TREADY : out STD_LOGIC;
+    S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXIS_TVALID : out STD_LOGIC;
+    M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    M_AXIS_TLAST : out STD_LOGIC;
+    M_AXIS_TREADY : in STD_LOGIC;
+    M_AXIS_TUSER : out STD_LOGIC;
+    S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 14 downto 0 );
+    S_AXIL_AWVALID : in STD_LOGIC;
+    S_AXIL_AWREADY : out STD_LOGIC;
+    S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIL_WVALID : in STD_LOGIC;
+    S_AXIL_WREADY : out STD_LOGIC;
+    S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXIL_BVALID : out STD_LOGIC;
+    S_AXIL_BREADY : in STD_LOGIC;
+    S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 14 downto 0 );
+    S_AXIL_ARVALID : in STD_LOGIC;
+    S_AXIL_ARREADY : out STD_LOGIC;
+    S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXIL_RVALID : out STD_LOGIC;
+    S_AXIL_RREADY : in STD_LOGIC;
+    S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_axis_video_filter_1_1;
+  signal Net : STD_LOGIC;
+  signal Net1 : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
+  signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
+  signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_downsizer_0_M_AXIS_TUSER : STD_LOGIC;
+  signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC;
+  signal axis_linemem_single_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal axis_linemem_single_0_m_axis_TLAST : STD_LOGIC;
+  signal axis_linemem_single_0_m_axis_TREADY : STD_LOGIC;
+  signal axis_linemem_single_0_m_axis_TUSER : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal axis_linemem_single_0_m_axis_TVALID : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TUSER : STD_LOGIC;
+  signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC;
+  signal axis_video_filter_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal axis_video_filter_1_M_AXIS_TLAST : STD_LOGIC;
+  signal axis_video_filter_1_M_AXIS_TREADY : STD_LOGIC;
+  signal axis_video_filter_1_M_AXIS_TUSER : STD_LOGIC;
+  signal axis_video_filter_1_M_AXIS_TVALID : STD_LOGIC;
+begin
+SIM_Enviroment: entity work.SIM_Enviroment_imp_14W2BPY
+     port map (
+      M_AXIL_ACLK => Net,
+      M_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
+      M_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
+      M_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
+      M_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
+      M_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
+      M_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
+      M_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY,
+      M_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
+      M_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
+      M_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
+      M_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY,
+      M_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
+      M_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
+      M_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
+      M_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY,
+      M_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
+      M_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID,
+      M_AXIS_tdata(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
+      M_AXIS_tlast => axis_master_simmodel_0_M_AXIS_TLAST,
+      M_AXIS_tready => axis_master_simmodel_0_M_AXIS_TREADY,
+      M_AXIS_tuser(0) => axis_master_simmodel_0_M_AXIS_TUSER(0),
+      M_AXIS_tvalid => axis_master_simmodel_0_M_AXIS_TVALID,
+      S_AXIS_ARESETN => Net1,
+      S_AXIS_tdata(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
+      S_AXIS_tlast => axis_upsizer_0_M_AXIS_TLAST,
+      S_AXIS_tready => axis_upsizer_0_M_AXIS_TREADY,
+      S_AXIS_tuser(0) => axis_upsizer_0_M_AXIS_TUSER,
+      S_AXIS_tvalid => axis_upsizer_0_M_AXIS_TVALID
+    );
+axis_downsizer_0: component design_1_axis_downsizer_0_0
+     port map (
+      AXIS_ACLK => Net,
+      AXIS_ARESETN => Net1,
+      M_AXIS_TDATA(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0),
+      M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST,
+      M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY,
+      M_AXIS_TUSER => axis_downsizer_0_M_AXIS_TUSER,
+      M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID,
+      S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
+      S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
+      S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
+      S_AXIS_TUSER => axis_master_simmodel_0_M_AXIS_TUSER(0),
+      S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
+    );
+axis_linemem_single_0: component design_1_axis_linemem_single_0_0
+     port map (
+      aclk => Net,
+      aresetn => Net1,
+      m_axis_tdata(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0),
+      m_axis_tlast => axis_linemem_single_0_m_axis_TLAST,
+      m_axis_tready => axis_linemem_single_0_m_axis_TREADY,
+      m_axis_tuser(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0),
+      m_axis_tvalid => axis_linemem_single_0_m_axis_TVALID,
+      s_axis_tdata(7 downto 0) => axis_downsizer_0_M_AXIS_TDATA(7 downto 0),
+      s_axis_tlast => axis_downsizer_0_M_AXIS_TLAST,
+      s_axis_tready => axis_downsizer_0_M_AXIS_TREADY,
+      s_axis_tuser(0) => axis_downsizer_0_M_AXIS_TUSER,
+      s_axis_tvalid => axis_downsizer_0_M_AXIS_TVALID
+    );
+axis_upsizer_0: component design_1_axis_upsizer_0_0
+     port map (
+      AXIS_ACLK => Net,
+      AXIS_ARESETN => Net1,
+      M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
+      M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
+      M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
+      M_AXIS_TUSER => axis_upsizer_0_M_AXIS_TUSER,
+      M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
+      S_AXIS_TDATA(7 downto 0) => axis_video_filter_1_M_AXIS_TDATA(7 downto 0),
+      S_AXIS_TLAST => axis_video_filter_1_M_AXIS_TLAST,
+      S_AXIS_TREADY => axis_video_filter_1_M_AXIS_TREADY,
+      S_AXIS_TUSER => axis_video_filter_1_M_AXIS_TUSER,
+      S_AXIS_TVALID => axis_video_filter_1_M_AXIS_TVALID
+    );
+axis_video_filter_1: component design_1_axis_video_filter_1_1
+     port map (
+      ACLK => Net,
+      ARESETN => Net1,
+      M_AXIS_TDATA(7 downto 0) => axis_video_filter_1_M_AXIS_TDATA(7 downto 0),
+      M_AXIS_TLAST => axis_video_filter_1_M_AXIS_TLAST,
+      M_AXIS_TREADY => axis_video_filter_1_M_AXIS_TREADY,
+      M_AXIS_TUSER => axis_video_filter_1_M_AXIS_TUSER,
+      M_AXIS_TVALID => axis_video_filter_1_M_AXIS_TVALID,
+      S_AXIL_ARADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(14 downto 0),
+      S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
+      S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
+      S_AXIL_AWADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(14 downto 0),
+      S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
+      S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
+      S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
+      S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
+      S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
+      S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
+      S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
+      S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
+      S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
+      S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
+      S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
+      S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
+      S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
+      S_AXIS_TDATA(23 downto 0) => axis_linemem_single_0_m_axis_TDATA(23 downto 0),
+      S_AXIS_TLAST => axis_linemem_single_0_m_axis_TLAST,
+      S_AXIS_TREADY => axis_linemem_single_0_m_axis_TREADY,
+      S_AXIS_TUSER(2 downto 0) => axis_linemem_single_0_m_axis_TUSER(2 downto 0),
+      S_AXIS_TVALID => axis_linemem_single_0_m_axis_TVALID
+    );
+end STRUCTURE;
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml
index 72a4257..e900603 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml
@@ -2,10 +2,10 @@
 <Root MajorVersion="0" MinorVersion="40">
   <CompositeFile CompositeFileTopName="design_2" CanBeSetAsTop="false" CanDisplayChildGraph="true">
     <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1733832971"/>
-    <Generation Name="SIMULATION" State="STALE" Timestamp="1733832971"/>
-    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1733832971"/>
-    <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1733832971"/>
+    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1733850794"/>
+    <Generation Name="SIMULATION" State="RESET" Timestamp="1733850785"/>
+    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1733850794"/>
+    <Generation Name="HW_HANDOFF" State="RESET" Timestamp="1733850785"/>
     <FileCollection Name="SOURCES" Type="SOURCES"/>
   </CompositeFile>
 </Root>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xml
index 5b96f9e..448b446 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xml
@@ -3930,67 +3930,68 @@
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xml
index 2594732..1cbcee9 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xml
@@ -3832,7 +3832,7 @@
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
@@ -3843,7 +3843,7 @@
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xml
index 4a4ef76..0f289f1 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xml
@@ -46030,6 +46030,7 @@
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RSTIF.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RSTIF.TYPE" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xml
index fe895fb..1a63ae3 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xml
@@ -3045,36 +3045,36 @@
         <xilinx:tag xilinx:name="ui.data.coregen.dd@340c86f3_ARCHIVE_LOCATION">d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs</xilinx:tag>
       </xilinx:tags>
       <xilinx:configElementInfos>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml
index 21f5aa8..10455a9 100644
--- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml
+++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml
@@ -321,7 +321,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>1ada2a66</spirit:value>
+            <spirit:value>59fe4094</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -334,7 +334,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>1ada2a66</spirit:value>
+            <spirit:value>59fe4094</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -861,7 +861,7 @@
         <xilinx:designToolContext>IPI</xilinx:designToolContext>
       </xilinx:designToolContexts>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-12-10T11:47:25Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-12-10T17:13:02Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
       <xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd
index 3561c2b..d6b499d 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd
@@ -11,101 +11,18 @@
       "validated": "true"
     },
     "design_tree": {
-      "axis_slave_simmodel_0": "",
-      "clk_rst_generator_0": "",
-      "axil_master_with_rom_0": "",
-      "axis_master_simmodel_0": "",
       "axis_downsizer_0": "",
       "axis_linemem_single_0": "",
       "axis_upsizer_0": "",
+      "SIM_Enviroment": {
+        "clk_rst_generator_0": "",
+        "axis_master_simmodel_0": "",
+        "axis_slave_simmodel_0": "",
+        "axil_master_with_rom_0": ""
+      },
       "axis_video_filter_1": ""
     },
     "components": {
-      "axis_slave_simmodel_0": {
-        "vlnv": "Gehrke:user:axis_slave_simmodel:1.0",
-        "xci_name": "design_1_axis_slave_simmodel_0_0",
-        "xci_path": "ip\\design_1_axis_slave_simmodel_0_0\\design_1_axis_slave_simmodel_0_0.xci",
-        "inst_hier_path": "axis_slave_simmodel_0",
-        "parameters": {
-          "FILE_NAME": {
-            "value": "../../../../tst_out"
-          },
-          "NUM_LINES": {
-            "value": "192"
-          },
-          "NUM_PIX_PER_LINE": {
-            "value": "192"
-          },
-          "PIXEL_FORMAT": {
-            "value": "13"
-          }
-        }
-      },
-      "clk_rst_generator_0": {
-        "vlnv": "wg:user:clk_rst_generator:1.0",
-        "xci_name": "design_1_clk_rst_generator_0_0",
-        "xci_path": "ip\\design_1_clk_rst_generator_0_0\\design_1_clk_rst_generator_0_0.xci",
-        "inst_hier_path": "clk_rst_generator_0",
-        "parameters": {
-          "HAS_CLK_INPUT": {
-            "value": "false"
-          },
-          "HAS_RESET_INPUT": {
-            "value": "false"
-          }
-        }
-      },
-      "axil_master_with_rom_0": {
-        "vlnv": "wg:user:axil_master_with_rom:1.0",
-        "xci_name": "design_1_axil_master_with_rom_0_0",
-        "xci_path": "ip\\design_1_axil_master_with_rom_0_0\\design_1_axil_master_with_rom_0_0.xci",
-        "inst_hier_path": "axil_master_with_rom_0",
-        "parameters": {
-          "HAS_INTERRUPT_IN": {
-            "value": "false"
-          }
-        },
-        "interface_ports": {
-          "M_AXIL": {
-            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
-            "mode": "Master",
-            "address_space_ref": "M_AXIL",
-            "base_address": {
-              "minimum": "0x00000000",
-              "maximum": "0xFFFFFFFF",
-              "width": "32"
-            }
-          }
-        },
-        "addressing": {
-          "address_spaces": {
-            "M_AXIL": {
-              "range": "4G",
-              "width": "32"
-            }
-          }
-        }
-      },
-      "axis_master_simmodel_0": {
-        "vlnv": "Gehrke:user:axis_master_simmodel:1.0",
-        "xci_name": "design_1_axis_master_simmodel_0_0",
-        "xci_path": "ip\\design_1_axis_master_simmodel_0_0\\design_1_axis_master_simmodel_0_0.xci",
-        "inst_hier_path": "axis_master_simmodel_0",
-        "parameters": {
-          "FILE_NAME": {
-            "value": "../../../../Moewe-192x192"
-          },
-          "NUM_LINES": {
-            "value": "192"
-          },
-          "NUM_PIX_PER_LINE": {
-            "value": "192"
-          },
-          "PIXEL_FORMAT": {
-            "value": "13"
-          }
-        }
-      },
       "axis_downsizer_0": {
         "vlnv": "xilinx.com:user:axis_downsizer:1.0",
         "xci_name": "design_1_axis_downsizer_0_0",
@@ -139,6 +56,168 @@
           }
         }
       },
+      "SIM_Enviroment": {
+        "interface_ports": {
+          "M_AXIS": {
+            "mode": "Master",
+            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
+          },
+          "S_AXIS": {
+            "mode": "Slave",
+            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
+          },
+          "M_AXIL": {
+            "mode": "Master",
+            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
+            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
+          }
+        },
+        "ports": {
+          "M_AXIL_ACLK": {
+            "type": "clk",
+            "direction": "O"
+          },
+          "S_AXIS_ARESETN": {
+            "type": "rst",
+            "direction": "O"
+          }
+        },
+        "components": {
+          "clk_rst_generator_0": {
+            "vlnv": "wg:user:clk_rst_generator:1.0",
+            "xci_name": "design_1_clk_rst_generator_0_0",
+            "xci_path": "ip\\design_1_clk_rst_generator_0_0\\design_1_clk_rst_generator_0_0.xci",
+            "inst_hier_path": "SIM_Enviroment/clk_rst_generator_0",
+            "parameters": {
+              "HAS_CLK_INPUT": {
+                "value": "false"
+              },
+              "HAS_RESET_INPUT": {
+                "value": "false"
+              }
+            }
+          },
+          "axis_master_simmodel_0": {
+            "vlnv": "Gehrke:user:axis_master_simmodel:1.0",
+            "xci_name": "design_1_axis_master_simmodel_0_0",
+            "xci_path": "ip\\design_1_axis_master_simmodel_0_0\\design_1_axis_master_simmodel_0_0.xci",
+            "inst_hier_path": "SIM_Enviroment/axis_master_simmodel_0",
+            "parameters": {
+              "FILE_NAME": {
+                "value": "../../../../Moewe-192x192"
+              },
+              "NUM_LINES": {
+                "value": "192"
+              },
+              "NUM_PIX_PER_LINE": {
+                "value": "192"
+              },
+              "PIXEL_FORMAT": {
+                "value": "13"
+              }
+            }
+          },
+          "axis_slave_simmodel_0": {
+            "vlnv": "Gehrke:user:axis_slave_simmodel:1.0",
+            "xci_name": "design_1_axis_slave_simmodel_0_0",
+            "xci_path": "ip\\design_1_axis_slave_simmodel_0_0\\design_1_axis_slave_simmodel_0_0.xci",
+            "inst_hier_path": "SIM_Enviroment/axis_slave_simmodel_0",
+            "parameters": {
+              "FILE_NAME": {
+                "value": "../../../../tst_out"
+              },
+              "NUM_LINES": {
+                "value": "192"
+              },
+              "NUM_PIX_PER_LINE": {
+                "value": "192"
+              },
+              "PIXEL_FORMAT": {
+                "value": "13"
+              }
+            }
+          },
+          "axil_master_with_rom_0": {
+            "vlnv": "wg:user:axil_master_with_rom:1.0",
+            "xci_name": "design_1_axil_master_with_rom_0_0",
+            "xci_path": "ip\\design_1_axil_master_with_rom_0_0\\design_1_axil_master_with_rom_0_0.xci",
+            "inst_hier_path": "SIM_Enviroment/axil_master_with_rom_0",
+            "parameters": {
+              "HAS_INTERRUPT_IN": {
+                "value": "false"
+              }
+            },
+            "interface_ports": {
+              "M_AXIL": {
+                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
+                "mode": "Master",
+                "address_space_ref": "M_AXIL",
+                "base_address": {
+                  "minimum": "0x00000000",
+                  "maximum": "0xFFFFFFFF",
+                  "width": "32"
+                }
+              }
+            },
+            "addressing": {
+              "address_spaces": {
+                "M_AXIL": {
+                  "range": "4G",
+                  "width": "32"
+                }
+              }
+            }
+          }
+        },
+        "interface_nets": {
+          "axil_master_with_rom_0_M_AXIL": {
+            "interface_ports": [
+              "M_AXIL",
+              "axil_master_with_rom_0/M_AXIL"
+            ]
+          },
+          "axis_master_simmodel_0_M_AXIS": {
+            "interface_ports": [
+              "M_AXIS",
+              "axis_master_simmodel_0/M_AXIS"
+            ]
+          },
+          "axis_upsizer_0_M_AXIS": {
+            "interface_ports": [
+              "S_AXIS",
+              "axis_slave_simmodel_0/S_AXIS"
+            ]
+          }
+        },
+        "nets": {
+          "Net": {
+            "ports": [
+              "clk_rst_generator_0/clk",
+              "M_AXIL_ACLK",
+              "axil_master_with_rom_0/M_AXIL_ACLK",
+              "axis_slave_simmodel_0/S_AXIS_ACLK",
+              "axis_master_simmodel_0/ACLK"
+            ]
+          },
+          "Net1": {
+            "ports": [
+              "clk_rst_generator_0/rst_n",
+              "S_AXIS_ARESETN",
+              "axis_slave_simmodel_0/S_AXIS_ARESETN",
+              "axil_master_with_rom_0/M_AXIL_ARESETN",
+              "axis_master_simmodel_0/ARESETN"
+            ]
+          },
+          "axis_slave_simmodel_0_FINISHED": {
+            "ports": [
+              "axis_slave_simmodel_0/FINISHED",
+              "clk_rst_generator_0/stop_simulation"
+            ]
+          }
+        }
+      },
       "axis_video_filter_1": {
         "vlnv": "xilinx.com:module_ref:axis_video_filter:1.0",
         "xci_name": "design_1_axis_video_filter_1_1",
@@ -495,7 +574,7 @@
       "axil_master_with_rom_0_M_AXIL": {
         "interface_ports": [
           "axis_video_filter_1/S_AXIL",
-          "axil_master_with_rom_0/M_AXIL"
+          "SIM_Enviroment/M_AXIL"
         ]
       },
       "axis_downsizer_0_M_AXIS": {
@@ -512,14 +591,14 @@
       },
       "axis_master_simmodel_0_M_AXIS": {
         "interface_ports": [
-          "axis_master_simmodel_0/M_AXIS",
+          "SIM_Enviroment/M_AXIS",
           "axis_downsizer_0/S_AXIS"
         ]
       },
       "axis_upsizer_0_M_AXIS": {
         "interface_ports": [
           "axis_upsizer_0/M_AXIS",
-          "axis_slave_simmodel_0/S_AXIS"
+          "SIM_Enviroment/S_AXIS"
         ]
       },
       "axis_video_filter_1_M_AXIS": {
@@ -532,10 +611,7 @@
     "nets": {
       "Net": {
         "ports": [
-          "clk_rst_generator_0/clk",
-          "axil_master_with_rom_0/M_AXIL_ACLK",
-          "axis_slave_simmodel_0/S_AXIS_ACLK",
-          "axis_master_simmodel_0/ACLK",
+          "SIM_Enviroment/M_AXIL_ACLK",
           "axis_downsizer_0/AXIS_ACLK",
           "axis_linemem_single_0/aclk",
           "axis_upsizer_0/AXIS_ACLK",
@@ -544,21 +620,27 @@
       },
       "Net1": {
         "ports": [
-          "clk_rst_generator_0/rst_n",
-          "axis_slave_simmodel_0/S_AXIS_ARESETN",
-          "axil_master_with_rom_0/M_AXIL_ARESETN",
-          "axis_master_simmodel_0/ARESETN",
+          "SIM_Enviroment/S_AXIS_ARESETN",
           "axis_linemem_single_0/aresetn",
           "axis_downsizer_0/AXIS_ARESETN",
           "axis_upsizer_0/AXIS_ARESETN",
           "axis_video_filter_1/ARESETN"
         ]
-      },
-      "axis_slave_simmodel_0_FINISHED": {
-        "ports": [
-          "axis_slave_simmodel_0/FINISHED",
-          "clk_rst_generator_0/stop_simulation"
-        ]
+      }
+    },
+    "addressing": {
+      "/SIM_Enviroment/axil_master_with_rom_0": {
+        "address_spaces": {
+          "M_AXIL": {
+            "segments": {
+              "SEG_axis_video_filter_1_reg0": {
+                "address_block": "/axis_video_filter_1/S_AXIL/reg0",
+                "offset": "0x43C00000",
+                "range": "32K"
+              }
+            }
+          }
+        }
       }
     }
   }
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci
index 4f1e30a..5c09b9d 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci
@@ -2,7 +2,7 @@
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
     "xci_name": "design_1_axil_master_with_rom_0_0",
-    "cell_name": "axil_master_with_rom_0",
+    "cell_name": "SIM_Enviroment/axil_master_with_rom_0",
     "component_reference": "wg:user:axil_master_with_rom:1.0",
     "ip_revision": "19",
     "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0",
@@ -22,11 +22,11 @@
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "zynq" } ],
-        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7z020" } ],
         "PACKAGE": [ { "value": "clg400" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xci
index c56ff51..1dc8bea 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0/design_1_axis_downsizer_0_0.xci
@@ -20,11 +20,11 @@
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "zynq" } ],
-        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7z020" } ],
         "PACKAGE": [ { "value": "clg400" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xci
index fe94044..21a193d 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0/design_1_axis_linemem_single_0_0.xci
@@ -22,11 +22,11 @@
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "zynq" } ],
-        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7z020" } ],
         "PACKAGE": [ { "value": "clg400" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xci
index 2717d8d..b48ac21 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0/design_1_axis_master_simmodel_0_0.xci
@@ -2,7 +2,7 @@
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
     "xci_name": "design_1_axis_master_simmodel_0_0",
-    "cell_name": "axis_master_simmodel_0",
+    "cell_name": "SIM_Enviroment/axis_master_simmodel_0",
     "component_reference": "Gehrke:user:axis_master_simmodel:1.0",
     "ip_revision": "10",
     "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0",
@@ -51,11 +51,11 @@
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "zynq" } ],
-        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7z020" } ],
         "PACKAGE": [ { "value": "clg400" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xci
index a97e672..72c7b06 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0/design_1_axis_slave_simmodel_0_0.xci
@@ -2,7 +2,7 @@
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
     "xci_name": "design_1_axis_slave_simmodel_0_0",
-    "cell_name": "axis_slave_simmodel_0",
+    "cell_name": "SIM_Enviroment/axis_slave_simmodel_0",
     "component_reference": "Gehrke:user:axis_slave_simmodel:1.0",
     "ip_revision": "4",
     "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_slave_simmodel_0_0",
@@ -38,11 +38,11 @@
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "zynq" } ],
-        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7z020" } ],
         "PACKAGE": [ { "value": "clg400" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xci
index b4e8a1b..16b0693 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0/design_1_axis_upsizer_0_0.xci
@@ -20,11 +20,11 @@
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "zynq" } ],
-        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7z020" } ],
         "PACKAGE": [ { "value": "clg400" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xci
index e7166fa..66695bc 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xci
@@ -16,11 +16,11 @@
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "zynq" } ],
-        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7z020" } ],
         "PACKAGE": [ { "value": "clg400" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci
index 14081e9..45bef9c 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci
@@ -2,7 +2,7 @@
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
     "xci_name": "design_1_clk_rst_generator_0_0",
-    "cell_name": "clk_rst_generator_0",
+    "cell_name": "SIM_Enviroment/clk_rst_generator_0",
     "component_reference": "wg:user:clk_rst_generator:1.0",
     "ip_revision": "7",
     "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0",
@@ -22,11 +22,11 @@
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "zynq" } ],
-        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7z020" } ],
         "PACKAGE": [ { "value": "clg400" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
index d902781..133a8eb 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
@@ -1,29 +1,25 @@
 {
    "ActiveEmotionalView":"Default View",
-   "Default View_ScaleFactor":"0.920395",
-   "Default View_TopLeft":"12,-175",
+   "Default View_ScaleFactor":"1.21496",
+   "Default View_TopLeft":"44,-100",
    "ExpandedHierarchyInLayout":"",
    "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
 #  -string -flagsOSRD
-preplace inst axis_slave_simmodel_0 -pg 1 -lvl 4 -x 920 -y 310 -defaultsOSRD
-preplace inst clk_rst_generator_0 -pg 1 -lvl 5 -x 1150 -y 310 -defaultsOSRD
-preplace inst axil_master_with_rom_0 -pg 1 -lvl 6 -x 1390 -y 100 -defaultsOSRD
-preplace inst axis_master_simmodel_0 -pg 1 -lvl 6 -x 1390 -y 220 -defaultsOSRD
-preplace inst axis_downsizer_0 -pg 1 -lvl 1 -x 150 -y 100 -defaultsOSRD
-preplace inst axis_linemem_single_0 -pg 1 -lvl 2 -x 420 -y 120 -defaultsOSRD
-preplace inst axis_upsizer_0 -pg 1 -lvl 3 -x 670 -y 290 -defaultsOSRD
-preplace inst axis_video_filter_1 -pg 1 -lvl 2 -x 420 -y 270 -defaultsOSRD
-preplace netloc Net 1 0 6 30 180 270 360 550 370 790 220 NJ 220 1260J
-preplace netloc Net1 1 0 6 20 190 280 370 540 380 800 230 N 230 1270
-preplace netloc axis_slave_simmodel_0_FINISHED 1 4 1 N 310
-preplace netloc axis_downsizer_0_M_AXIS 1 1 1 N 100
-preplace netloc axis_master_simmodel_0_M_AXIS 1 0 7 30 20 NJ 20 NJ 20 N 20 NJ 20 NJ 20 1520
-preplace netloc axis_upsizer_0_M_AXIS 1 3 1 N 290
-preplace netloc axis_linemem_single_0_m_axis 1 1 2 300 40 540
-preplace netloc axis_video_filter_1_M_AXIS 1 2 1 N 270
-preplace netloc axil_master_with_rom_0_M_AXIL 1 1 6 290 30 NJ 30 NJ 30 NJ 30 NJ 30 1510
-levelinfo -pg 1 0 150 420 670 920 1150 1390 1540
-pagesize -pg 1 -db -bbox -sgen 0 0 1540 390
+preplace inst axis_downsizer_0 -pg 1 -lvl 1 -x 160 -y 80 -defaultsOSRD
+preplace inst axis_linemem_single_0 -pg 1 -lvl 2 -x 400 -y 100 -defaultsOSRD
+preplace inst axis_upsizer_0 -pg 1 -lvl 4 -x 900 -y 300 -defaultsOSRD
+preplace inst SIM_Enviroment -pg 1 -lvl 5 -x 1140 -y 300 -defaultsOSRD
+preplace inst axis_video_filter_1 -pg 1 -lvl 3 -x 650 -y 280 -defaultsOSRD
+preplace netloc Net 1 0 6 30 170 290 190 500 380 780 380 NJ 380 1260
+preplace netloc Net1 1 0 6 20 180 300 180 510 370 770 210 NJ 210 1270
+preplace netloc axil_master_with_rom_0_M_AXIL 1 2 4 530 190 NJ 190 NJ 190 1280
+preplace netloc axis_downsizer_0_M_AXIS 1 1 1 N 80
+preplace netloc axis_linemem_single_0_m_axis 1 2 1 520 100n
+preplace netloc axis_master_simmodel_0_M_AXIS 1 0 6 40 160 280J 20 NJ 20 NJ 20 NJ 20 1260
+preplace netloc axis_upsizer_0_M_AXIS 1 4 1 N 300
+preplace netloc axis_video_filter_1_M_AXIS 1 3 1 N 280
+levelinfo -pg 1 0 160 400 650 900 1140 1300
+pagesize -pg 1 -db -bbox -sgen 0 0 1300 390
 "
 }
 0
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_a4880b6f.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_a4880b6f.ui
new file mode 100644
index 0000000..63abb27
--- /dev/null
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_a4880b6f.ui
@@ -0,0 +1,27 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.54454",
+   "Default View_TopLeft":"-92,-106",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
+#  -string -flagsOSRD
+preplace port M_AXIS -pg 1 -lvl 4 -x 750 -y 210 -defaultsOSRD
+preplace port S_AXIS -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD
+preplace port M_AXIL -pg 1 -lvl 4 -x 750 -y 60 -defaultsOSRD
+preplace port port-id_M_AXIL_ACLK -pg 1 -lvl 4 -x 750 -y 120 -defaultsOSRD
+preplace port port-id_S_AXIS_ARESETN -pg 1 -lvl 4 -x 750 -y 150 -defaultsOSRD
+preplace inst clk_rst_generator_0 -pg 1 -lvl 2 -x 370 -y 130 -defaultsOSRD
+preplace inst axis_master_simmodel_0 -pg 1 -lvl 3 -x 610 -y 220 -defaultsOSRD
+preplace inst axis_slave_simmodel_0 -pg 1 -lvl 1 -x 140 -y 130 -defaultsOSRD
+preplace inst axil_master_with_rom_0 -pg 1 -lvl 3 -x 610 -y 60 -defaultsOSRD
+preplace netloc axis_slave_simmodel_0_FINISHED 1 1 1 N 130
+preplace netloc Net 1 0 4 20 50 NJ 50 490 130 730J
+preplace netloc Net1 1 0 4 20 210 NJ 210 480 150 NJ
+preplace netloc axis_master_simmodel_0_M_AXIS 1 3 1 NJ 210
+preplace netloc axis_upsizer_0_M_AXIS 1 0 1 N 110
+preplace netloc axil_master_with_rom_0_M_AXIL 1 3 1 NJ 60
+levelinfo -pg 1 0 140 370 610 750
+pagesize -pg 1 -db -bbox -sgen -100 -10 910 290
+"
+}
+
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd
index 1cd7d47..7dea4df 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd
@@ -3443,18 +3443,18 @@
         "ports": [
           "axis_downsizer_0/AXIS_ACLK",
           "axi_2d_mmvs_0/ACLK",
-          "axis_video_filter_0/ACLK",
           "axis_upsizer_0/AXIS_ACLK",
-          "axis_linemem_single_0/aclk"
+          "axis_linemem_single_0/aclk",
+          "axis_video_filter_0/ACLK"
         ]
       },
       "Net1": {
         "ports": [
           "axis_downsizer_0/AXIS_ARESETN",
           "axi_2d_mmvs_0/ARESETN",
-          "axis_video_filter_0/ARESETN",
           "axis_upsizer_0/AXIS_ARESETN",
-          "axis_linemem_single_0/aresetn"
+          "axis_linemem_single_0/aresetn",
+          "axis_video_filter_0/ARESETN"
         ]
       },
       "SWITCH_0_1": {
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xci
index f3983f7..926f06a 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xci
@@ -132,26 +132,26 @@
           "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI3", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "12", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -210,26 +210,26 @@
           "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
           "mode": "master",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -289,7 +289,7 @@
           "parameters": {
             "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
-            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+            "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
             "RST": [ { "physical_name": "aresetn" } ]
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xci
index 4d78eb6..d5fb897 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xci
@@ -175,10 +175,10 @@
           "mode": "master",
           "address_space_ref": "M_AXI",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0/design_2_axis_video_filter_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0/design_2_axis_video_filter_0_0.xci
index 55140a1..437a3ee 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0/design_2_axis_video_filter_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0/design_2_axis_video_filter_0_0.xci
@@ -16,11 +16,11 @@
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "zynq" } ],
-        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7z020" } ],
         "PACKAGE": [ { "value": "clg400" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xci
index e5b8247..eea7b00 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xci
@@ -1345,7 +1345,7 @@
           "parameters": {
             "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
-            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+            "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
             "RST": [ { "physical_name": "aresetn" } ]
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xci
index 9620e0c..8f034eb 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xci
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xci
@@ -183,26 +183,26 @@
           "mode": "master",
           "address_space_ref": "M_AXI",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui
index fd4a673..75894d6 100644
--- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui
+++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui
@@ -1,7 +1,7 @@
 {
    "ActiveEmotionalView":"Default View",
    "Default View_ScaleFactor":"1.22367",
-   "Default View_TopLeft":"-326,-2",
+   "Default View_TopLeft":"16,-7",
    "ExpandedHierarchyInLayout":"",
    "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
 #  -string -flagsOSRD
@@ -24,6 +24,8 @@ preplace inst axis_upsizer_0 -pg 1 -lvl 3 -x 830 -y 740 -defaultsOSRD
 preplace inst axis_linemem_single_0 -pg 1 -lvl 4 -x 1130 -y 810 -defaultsOSRD
 preplace inst axis_video_filter_0 -pg 1 -lvl 2 -x 470 -y 740 -defaultsOSRD
 preplace netloc BUTTON_0_1 1 0 3 NJ 350 N 350 NJ
+preplace netloc Net 1 0 4 30 810 290J 630 660 660 1000
+preplace netloc Net1 1 0 4 20 650 270J 610 680 610 1020
 preplace netloc SWITCH_0_1 1 0 3 NJ 410 N 410 NJ
 preplace netloc processing_system7_0_FCLK_CLK0 1 1 3 310 40 650 40 1020
 preplace netloc processing_system7_0_FCLK_CLK3 1 2 2 670 10 1030
@@ -35,25 +37,23 @@ preplace netloc zynq_base_hdmi_0_HDMI_DATA_P 1 3 2 NJ 390 N
 preplace netloc zynq_base_hdmi_0_LED 1 3 2 NJ 410 1240
 preplace netloc zynq_base_hdmi_0_RGB_LED 1 3 2 NJ 430 1230
 preplace netloc zynq_base_hdmi_0_VIDEO_INTERRUPT 1 2 2 680 30 1010
-preplace netloc Net 1 0 4 30 810 290J 630 660 660 1000
-preplace netloc Net1 1 0 4 20 650 270J 610 680 610 1020
+preplace netloc AXI_Intercon_M00_AXI2 1 1 2 310 260 620
+preplace netloc AXI_Intercon_M00_AXI3 1 1 2 300 250 610
+preplace netloc AXI_Intercon_M00_AXI_4 1 2 1 630 170n
+preplace netloc S00_AXI_2_1 1 1 2 270 270 610
+preplace netloc axi_2d_mmvs_0_M_AXIS 1 0 3 30 600 NJ 600 600
 preplace netloc axi_mem_intercon_M00_AXI 1 2 1 630 130n
+preplace netloc axis_downsizer_0_M_AXIS 1 1 3 280J 620 NJ 620 1030
+preplace netloc axis_linemem_single_0_m_axis 1 1 4 330 640 NJ 640 NJ 640 1230
+preplace netloc axis_upsizer_0_M_AXIS 1 1 3 340 650 NJ 650 990
+preplace netloc axis_video_filter_0_M_AXIS 1 2 1 630 720n
 preplace netloc processing_system7_0_DDR 1 3 2 NJ 120 1230
 preplace netloc processing_system7_0_FIXED_IO 1 3 2 NJ 140 N
 preplace netloc processing_system7_0_M_AXI_GP0 1 1 3 340 20 NJ 20 990
 preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 640 110n
 preplace netloc zynq_base_hdmi_0_M_AXI 1 1 3 320 50 NJ 50 1000
-preplace netloc axis_upsizer_0_M_AXIS 1 1 3 340 650 NJ 650 990
-preplace netloc axis_video_filter_0_M_AXIS 1 2 1 630 720n
-preplace netloc axis_downsizer_0_M_AXIS 1 1 3 280J 620 NJ 620 1030
-preplace netloc axis_linemem_single_0_m_axis 1 1 4 330 640 NJ 640 NJ 640 1230
-preplace netloc axi_2d_mmvs_0_M_AXIS 1 0 3 30 600 NJ 600 600
-preplace netloc AXI_Intercon_M00_AXI2 1 1 2 310 260 620
-preplace netloc AXI_Intercon_M00_AXI3 1 1 2 300 250 610
-preplace netloc S00_AXI_2_1 1 1 2 270 270 610
-preplace netloc AXI_Intercon_M00_AXI_4 1 2 1 630 170n
 levelinfo -pg 1 0 150 470 830 1130 1260
 pagesize -pg 1 -db -bbox -sgen -140 0 1440 1100
 "
 }
-
+0
diff --git a/Milestone6/milestone6/milestone6.xpr b/Milestone6/milestone6/milestone6.xpr
index f66b857..3601134 100644
--- a/Milestone6/milestone6/milestone6.xpr
+++ b/Milestone6/milestone6/milestone6.xpr
@@ -4,7 +4,7 @@
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
 <!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="63" Path="C:/es-praktikum/Milestone6/milestone6/milestone6.xpr">
+<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-praktikum/Milestone6/milestone6/milestone6.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="8685839343394c1fb7ae4540054d577c"/>
@@ -43,8 +43,8 @@
     <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
-    <Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.1"/>
-    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/basti/AppData/Roaming/Xilinx/Vivado/2023.1/xhub/board_store/xilinx_board_store"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val=""/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
@@ -61,20 +61,20 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="zybo-z7-20"/>
-    <Option Name="WTXSimLaunchSim" Val="24"/>
+    <Option Name="WTXSimLaunchSim" Val="29"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="18"/>
-    <Option Name="WTModelSimExportSim" Val="18"/>
-    <Option Name="WTQuestaExportSim" Val="18"/>
+    <Option Name="WTXSimExportSim" Val="21"/>
+    <Option Name="WTModelSimExportSim" Val="21"/>
+    <Option Name="WTQuestaExportSim" Val="21"/>
     <Option Name="WTIesExportSim" Val="0"/>
-    <Option Name="WTVcsExportSim" Val="18"/>
-    <Option Name="WTRivieraExportSim" Val="18"/>
-    <Option Name="WTActivehdlExportSim" Val="18"/>
+    <Option Name="WTVcsExportSim" Val="21"/>
+    <Option Name="WTRivieraExportSim" Val="21"/>
+    <Option Name="WTActivehdlExportSim" Val="21"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -92,31 +92,29 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
+      <File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../axis_video_filter.vhd">
         <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.v">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PSRCDIR/sources_1/bd/design_2/design_2.bd">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
@@ -148,6 +146,11 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/design_1_wrapper_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="design_1_wrapper"/>
@@ -161,6 +164,7 @@
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/design_1_wrapper_behav.wcfg"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
@@ -216,9 +220,7 @@
       <RQSFiles/>
     </Run>
   </Runs>
-  <Board>
-    <Jumpers/>
-  </Board>
+  <Board/>
   <DashboardSummary Version="1" Minor="0">
     <Dashboards>
       <Dashboard Name="default_dashboard">
diff --git a/Milestone6/milestone6/tst_out.bmp b/Milestone6/milestone6/tst_out.bmp
new file mode 100644
index 0000000..c19089c
Binary files /dev/null and b/Milestone6/milestone6/tst_out.bmp differ