update gitignore files

Milestone1/es-milestone1/.gitignore

@@ -1,41 +1,86 @@
-# Ignore everything
+# Created by https://www.toptal.com/developers/gitignore/api/vivado
+# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
+
+### Vivado ###
+#########################################################################################################
+##	This is an example .gitignore file for Vivado, please treat it as an example as
+##	it might not be complete. In addition, XAPP 1165 should be followed.
+#########
+#Exclude all
 *
-# Allow whitelisting subdirectories
 !*/
-# Don\'t ignore the block design and block design hdl wrapper files
+!.gitignore
-!/bd/*/*.bd
+###########################################################################
-!/bd/*/hdl/*.sv
+##	VIVADO
-!/bd/*/hdl/*.v
+#Source files:
-!/bd/*/hdl/*.vhd
+#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
-!/bd/*/hdl/*.vhdl
+!*.vhd
-# Don\'t ignore the constraint files
+!*.v
-!/constraints/**/*.xdc
+!*.sv
-# Don\'t ignore the synthesis files
+!*.bd
-!/hdl/**/*.sv
+!*.edif
-!/hdl/**/*.v
+#IP files
-!/hdl/**/*.vh
+#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
-!/hdl/**/*.vhd
+#.xci + .dcp: implementation possible but not re-synthesis
-!/hdl/**/*.vhdl
+#*.xci(www.spiritconsortium.org)
-# Don\'t ignore the HLS source and testbench files
+!*.xci
-!/hsl/*/sources/*.cpp
+#.xcix: Core container file
-!/hsl/*/sources/*.hpp
+#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
-!/hsl/*/testbench/*.cpp
+!*.xcix
-# Don\'t ignore the IP defintion files
+#*.dcp(checkpoint files)
-!/ip/*/*.xci
+!*.dcp
-# Don\'t ignore the HLS IP defintion files
+!*.vds
-!/ip/hls_ip/**
+!*.pb
-# Don\'t ignore the output files
+#All bd comments and layout coordinates are stored within .ui
-!/output/**/*.bit
+!*.ui
-!/output/**/*.xsa
+!*.ooc
-!/output/**/*.dcp
+#System Generator
-# Don\'t ignore the project files
+!*.mdl
-!/project/*.xpr
+!*.slx
-# Don\'t ignore the simulation files
+!*.bxml
-!/sim/**/*.sv
+#Simulation logic analyzer
-!/sim/**/*.v
+!*.wcfg
-!/sim/**/*.vh
+!*.coe
-!/sim/**/*.vhd
+#MIG
-!/sim/**/*.vhdl
+!*.prj
-!/sim/**/*.wav
+!*.mem
-# Don\'t ignore this file
+#Project files
-!.gitignore
+#XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
+#Do NOT ignore *.xpr files
+!*.xpr
+#Include *.xml files for 2013.4 or earlier version
+!*.xml
+#Constraint files
+#Do NOT ignore *.xdc files
+!*.xdc
+#TCL - files
+!*.tcl
+#Journal - files
+!*.jou
+#Reports
+!*.rpt
+!*.txt
+!*.vdi
+#C-files
+!*.c
+!*.h
+!*.elf
+!*.bmm
+!*.xmp
+
+# End of https://www.toptal.com/developers/gitignore/api/vivado
+
+# Vidado project directories which are not needed
+.Xil/
+*.cache/
+*.hw/
+*.ip_user_files/
+*.runs/
+*.sim/
+# design checkpoint file
+*.dcp
+
+# ignore Vivado log files
+*.log
+*.jou
+vivado_pid*.str

Milestone2/VivadoProjekt/axis_audio_bitcrusher/.gitignore

@@ -1,41 +1,86 @@
-# Ignore everything
+# Created by https://www.toptal.com/developers/gitignore/api/vivado
+# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
+
+### Vivado ###
+#########################################################################################################
+##	This is an example .gitignore file for Vivado, please treat it as an example as
+##	it might not be complete. In addition, XAPP 1165 should be followed.
+#########
+#Exclude all
 *
-# Allow whitelisting subdirectories
 !*/
-# Don\'t ignore the block design and block design hdl wrapper files
+!.gitignore
-!/bd/*/*.bd
+###########################################################################
-!/bd/*/hdl/*.sv
+##	VIVADO
-!/bd/*/hdl/*.v
+#Source files:
-!/bd/*/hdl/*.vhd
+#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
-!/bd/*/hdl/*.vhdl
+!*.vhd
-# Don\'t ignore the constraint files
+!*.v
-!/constraints/**/*.xdc
+!*.sv
-# Don\'t ignore the synthesis files
+!*.bd
-!/hdl/**/*.sv
+!*.edif
-!/hdl/**/*.v
+#IP files
-!/hdl/**/*.vh
+#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
-!/hdl/**/*.vhd
+#.xci + .dcp: implementation possible but not re-synthesis
-!/hdl/**/*.vhdl
+#*.xci(www.spiritconsortium.org)
-# Don\'t ignore the HLS source and testbench files
+!*.xci
-!/hsl/*/sources/*.cpp
+#.xcix: Core container file
-!/hsl/*/sources/*.hpp
+#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
-!/hsl/*/testbench/*.cpp
+!*.xcix
-# Don\'t ignore the IP defintion files
+#*.dcp(checkpoint files)
-!/ip/*/*.xci
+!*.dcp
-# Don\'t ignore the HLS IP defintion files
+!*.vds
-!/ip/hls_ip/**
+!*.pb
-# Don\'t ignore the output files
+#All bd comments and layout coordinates are stored within .ui
-!/output/**/*.bit
+!*.ui
-!/output/**/*.xsa
+!*.ooc
-!/output/**/*.dcp
+#System Generator
-# Don\'t ignore the project files
+!*.mdl
-!/project/*.xpr
+!*.slx
-# Don\'t ignore the simulation files
+!*.bxml
-!/sim/**/*.sv
+#Simulation logic analyzer
-!/sim/**/*.v
+!*.wcfg
-!/sim/**/*.vh
+!*.coe
-!/sim/**/*.vhd
+#MIG
-!/sim/**/*.vhdl
+!*.prj
-!/sim/**/*.wav
+!*.mem
-# Don\'t ignore this file
+#Project files
-!.gitignore
+#XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
+#Do NOT ignore *.xpr files
+!*.xpr
+#Include *.xml files for 2013.4 or earlier version
+!*.xml
+#Constraint files
+#Do NOT ignore *.xdc files
+!*.xdc
+#TCL - files
+!*.tcl
+#Journal - files
+!*.jou
+#Reports
+!*.rpt
+!*.txt
+!*.vdi
+#C-files
+!*.c
+!*.h
+!*.elf
+!*.bmm
+!*.xmp
+
+# End of https://www.toptal.com/developers/gitignore/api/vivado
+
+# Vidado project directories which are not needed
+.Xil/
+*.cache/
+*.hw/
+*.ip_user_files/
+*.runs/
+*.sim/
+# design checkpoint file
+*.dcp
+
+# ignore Vivado log files
+*.log
+*.jou
+vivado_pid*.str

Milestone3/es-milestone3/.gitignore

@@ -1,41 +1,86 @@
-# Ignore everything
+# Created by https://www.toptal.com/developers/gitignore/api/vivado
+# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
+
+### Vivado ###
+#########################################################################################################
+##	This is an example .gitignore file for Vivado, please treat it as an example as
+##	it might not be complete. In addition, XAPP 1165 should be followed.
+#########
+#Exclude all
 *
-# Allow whitelisting subdirectories
 !*/
-# Don\'t ignore the block design and block design hdl wrapper files
+!.gitignore
-!/bd/*/*.bd
+###########################################################################
-!/bd/*/hdl/*.sv
+##	VIVADO
-!/bd/*/hdl/*.v
+#Source files:
-!/bd/*/hdl/*.vhd
+#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
-!/bd/*/hdl/*.vhdl
+!*.vhd
-# Don\'t ignore the constraint files
+!*.v
-!/constraints/**/*.xdc
+!*.sv
-# Don\'t ignore the synthesis files
+!*.bd
-!/hdl/**/*.sv
+!*.edif
-!/hdl/**/*.v
+#IP files
-!/hdl/**/*.vh
+#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
-!/hdl/**/*.vhd
+#.xci + .dcp: implementation possible but not re-synthesis
-!/hdl/**/*.vhdl
+#*.xci(www.spiritconsortium.org)
-# Don\'t ignore the HLS source and testbench files
+!*.xci
-!/hsl/*/sources/*.cpp
+#.xcix: Core container file
-!/hsl/*/sources/*.hpp
+#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
-!/hsl/*/testbench/*.cpp
+!*.xcix
-# Don\'t ignore the IP defintion files
+#*.dcp(checkpoint files)
-!/ip/*/*.xci
+!*.dcp
-# Don\'t ignore the HLS IP defintion files
+!*.vds
-!/ip/hls_ip/**
+!*.pb
-# Don\'t ignore the output files
+#All bd comments and layout coordinates are stored within .ui
-!/output/**/*.bit
+!*.ui
-!/output/**/*.xsa
+!*.ooc
-!/output/**/*.dcp
+#System Generator
-# Don\'t ignore the project files
+!*.mdl
-!/project/*.xpr
+!*.slx
-# Don\'t ignore the simulation files
+!*.bxml
-!/sim/**/*.sv
+#Simulation logic analyzer
-!/sim/**/*.v
+!*.wcfg
-!/sim/**/*.vh
+!*.coe
-!/sim/**/*.vhd
+#MIG
-!/sim/**/*.vhdl
+!*.prj
-!/sim/**/*.wav
+!*.mem
-# Don\'t ignore this file
+#Project files
-!.gitignore
+#XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
+#Do NOT ignore *.xpr files
+!*.xpr
+#Include *.xml files for 2013.4 or earlier version
+!*.xml
+#Constraint files
+#Do NOT ignore *.xdc files
+!*.xdc
+#TCL - files
+!*.tcl
+#Journal - files
+!*.jou
+#Reports
+!*.rpt
+!*.txt
+!*.vdi
+#C-files
+!*.c
+!*.h
+!*.elf
+!*.bmm
+!*.xmp
+
+# End of https://www.toptal.com/developers/gitignore/api/vivado
+
+# Vidado project directories which are not needed
+.Xil/
+*.cache/
+*.hw/
+*.ip_user_files/
+*.runs/
+*.sim/
+# design checkpoint file
+*.dcp
+
+# ignore Vivado log files
+*.log
+*.jou
+vivado_pid*.str

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_master_si_0_0/sim/af_sim_axis_audio_master_si_0_0.vhd

@@ -0,0 +1,108 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axis_audio_master_simmodel:1.0
+-- IP Revision: 2
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY af_sim_axis_audio_master_si_0_0 IS
+  PORT (
+    ACLK : IN STD_LOGIC;
+    ARESETN : IN STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIS_TREADY : IN STD_LOGIC;
+    WAV_HEADER : OUT STD_LOGIC_VECTOR(351 DOWNTO 0)
+  );
+END af_sim_axis_audio_master_si_0_0;
+
+ARCHITECTURE af_sim_axis_audio_master_si_0_0_arch OF af_sim_axis_audio_master_si_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_master_si_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_audio_master_simmodel IS
+    GENERIC (
+      CLOCK_CYCLES_PER_SAMPLE : INTEGER;
+      FILE_NAME : STRING
+    );
+    PORT (
+      ACLK : IN STD_LOGIC;
+      ARESETN : IN STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIS_TREADY : IN STD_LOGIC;
+      WAV_HEADER : OUT STD_LOGIC_VECTOR(351 DOWNTO 0)
+    );
+  END COMPONENT axis_audio_master_simmodel;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+BEGIN
+  U0 : axis_audio_master_simmodel
+    GENERIC MAP (
+      CLOCK_CYCLES_PER_SAMPLE => 5,
+      FILE_NAME => "../../../../HaveANiceDay"
+    )
+    PORT MAP (
+      ACLK => ACLK,
+      ARESETN => ARESETN,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TREADY => M_AXIS_TREADY,
+      WAV_HEADER => WAV_HEADER
+    );
+END af_sim_axis_audio_master_si_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_mono2ster_0_0/sim/af_sim_axis_audio_mono2ster_0_0.vhd

@@ -0,0 +1,114 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
+-- IP Revision: 3
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY af_sim_axis_audio_mono2ster_0_0 IS
+  PORT (
+    AXIS_ACLK : IN STD_LOGIC;
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIS_TREADY : IN STD_LOGIC
+  );
+END af_sim_axis_audio_mono2ster_0_0;
+
+ARCHITECTURE af_sim_axis_audio_mono2ster_0_0_arch OF af_sim_axis_audio_mono2ster_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_audio_mono2stereo IS
+    GENERIC (
+      HAS_LAST : BOOLEAN
+    );
+    PORT (
+      AXIS_ACLK : IN STD_LOGIC;
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC
+    );
+  END COMPONENT axis_audio_mono2stereo;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_audio_mono2stereo
+    GENERIC MAP (
+      HAS_LAST => false
+    )
+    PORT MAP (
+      AXIS_ACLK => AXIS_ACLK,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => '0',
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TREADY => M_AXIS_TREADY
+    );
+END af_sim_axis_audio_mono2ster_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_slave_sim_0_0/sim/af_sim_axis_audio_slave_sim_0_0.vhd

@@ -0,0 +1,111 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axis_audio_slave_simmodel:1.0
+-- IP Revision: 18
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY af_sim_axis_audio_slave_sim_0_0 IS
+  PORT (
+    ACLK : IN STD_LOGIC;
+    ARESETN : IN STD_LOGIC;
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    FINISHED : OUT STD_LOGIC;
+    WAV_HEADER : IN STD_LOGIC_VECTOR(351 DOWNTO 0)
+  );
+END af_sim_axis_audio_slave_sim_0_0;
+
+ARCHITECTURE af_sim_axis_audio_slave_sim_0_0_arch OF af_sim_axis_audio_slave_sim_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_slave_sim_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_audio_slave_simmodel IS
+    GENERIC (
+      FILE_NAME : STRING;
+      RANDOM_TREADY : BOOLEAN
+    );
+    PORT (
+      ACLK : IN STD_LOGIC;
+      ARESETN : IN STD_LOGIC;
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      FINISHED : OUT STD_LOGIC;
+      WAV_HEADER : IN STD_LOGIC_VECTOR(351 DOWNTO 0)
+    );
+  END COMPONENT axis_audio_slave_simmodel;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_audio_slave_simmodel
+    GENERIC MAP (
+      FILE_NAME => "../../../../sim_out",
+      RANDOM_TREADY => true
+    )
+    PORT MAP (
+      ACLK => ACLK,
+      ARESETN => ARESETN,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      FINISHED => FINISHED,
+      WAV_HEADER => WAV_HEADER
+    );
+END af_sim_axis_audio_slave_sim_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_stereo2mo_0_0/sim/af_sim_axis_audio_stereo2mo_0_0.vhd

@@ -0,0 +1,114 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
+-- IP Revision: 4
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY af_sim_axis_audio_stereo2mo_0_0 IS
+  PORT (
+    AXIS_ACLK : IN STD_LOGIC;
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    M_AXIS_TREADY : IN STD_LOGIC
+  );
+END af_sim_axis_audio_stereo2mo_0_0;
+
+ARCHITECTURE af_sim_axis_audio_stereo2mo_0_0_arch OF af_sim_axis_audio_stereo2mo_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_audio_stereo2mono IS
+    GENERIC (
+      HAS_LAST : BOOLEAN
+    );
+    PORT (
+      AXIS_ACLK : IN STD_LOGIC;
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC
+    );
+  END COMPONENT axis_audio_stereo2mono;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_audio_stereo2mono
+    GENERIC MAP (
+      HAS_LAST => false
+    )
+    PORT MAP (
+      AXIS_ACLK => AXIS_ACLK,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => '0',
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TREADY => M_AXIS_TREADY
+    );
+END af_sim_axis_audio_stereo2mo_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/sim/af_sim_axis_prog_audio_filt_0_0.vhd

@@ -0,0 +1,204 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:axis_prog_audio_filter3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY af_sim_axis_prog_audio_filt_0_0 IS
+  PORT (
+    AXI_ACLK : IN STD_LOGIC;
+    AXI_ARESETN : IN STD_LOGIC;
+    S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXIL_AWVALID : IN STD_LOGIC;
+    S_AXIL_AWREADY : OUT STD_LOGIC;
+    S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_WVALID : IN STD_LOGIC;
+    S_AXIL_WREADY : OUT STD_LOGIC;
+    S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXIL_BVALID : OUT STD_LOGIC;
+    S_AXIL_BREADY : IN STD_LOGIC;
+    S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXIL_ARVALID : IN STD_LOGIC;
+    S_AXIL_ARREADY : OUT STD_LOGIC;
+    S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_RVALID : OUT STD_LOGIC;
+    S_AXIL_RREADY : IN STD_LOGIC;
+    S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    S_AXIS_TLAST : IN STD_LOGIC;
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    M_AXIS_TLAST : OUT STD_LOGIC;
+    M_AXIS_TREADY : IN STD_LOGIC
+  );
+END af_sim_axis_prog_audio_filt_0_0;
+
+ARCHITECTURE af_sim_axis_prog_audio_filt_0_0_arch OF af_sim_axis_prog_audio_filt_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_prog_audio_filt_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_prog_audio_filter3 IS
+    GENERIC (
+      COEFF_0 : INTEGER;
+      COEFF_1 : INTEGER;
+      COEFF_2 : INTEGER;
+      SHIFT : INTEGER;
+      RUN_AFTER_RESET : BOOLEAN;
+      HAS_LAST : BOOLEAN
+    );
+    PORT (
+      AXI_ACLK : IN STD_LOGIC;
+      AXI_ARESETN : IN STD_LOGIC;
+      S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      S_AXIL_AWVALID : IN STD_LOGIC;
+      S_AXIL_AWREADY : OUT STD_LOGIC;
+      S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_WVALID : IN STD_LOGIC;
+      S_AXIL_WREADY : OUT STD_LOGIC;
+      S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXIL_BVALID : OUT STD_LOGIC;
+      S_AXIL_BREADY : IN STD_LOGIC;
+      S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      S_AXIL_ARVALID : IN STD_LOGIC;
+      S_AXIL_ARREADY : OUT STD_LOGIC;
+      S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_RVALID : OUT STD_LOGIC;
+      S_AXIL_RREADY : IN STD_LOGIC;
+      S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC
+    );
+  END COMPONENT axis_prog_audio_filter3;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI_ACLK, ASSOCIATED_RESET AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" & 
+"ITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_prog_audio_filter3
+    GENERIC MAP (
+      COEFF_0 => 16,
+      COEFF_1 => 32,
+      COEFF_2 => 16,
+      SHIFT => 6,
+      RUN_AFTER_RESET => true,
+      HAS_LAST => false
+    )
+    PORT MAP (
+      AXI_ACLK => AXI_ACLK,
+      AXI_ARESETN => AXI_ARESETN,
+      S_AXIL_AWADDR => S_AXIL_AWADDR,
+      S_AXIL_AWVALID => S_AXIL_AWVALID,
+      S_AXIL_AWREADY => S_AXIL_AWREADY,
+      S_AXIL_WDATA => S_AXIL_WDATA,
+      S_AXIL_WVALID => S_AXIL_WVALID,
+      S_AXIL_WREADY => S_AXIL_WREADY,
+      S_AXIL_WSTRB => S_AXIL_WSTRB,
+      S_AXIL_BVALID => S_AXIL_BVALID,
+      S_AXIL_BREADY => S_AXIL_BREADY,
+      S_AXIL_BRESP => S_AXIL_BRESP,
+      S_AXIL_ARADDR => S_AXIL_ARADDR,
+      S_AXIL_ARVALID => S_AXIL_ARVALID,
+      S_AXIL_ARREADY => S_AXIL_ARREADY,
+      S_AXIL_RDATA => S_AXIL_RDATA,
+      S_AXIL_RVALID => S_AXIL_RVALID,
+      S_AXIL_RREADY => S_AXIL_RREADY,
+      S_AXIL_RRESP => S_AXIL_RRESP,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => S_AXIS_TLAST,
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TLAST => M_AXIS_TLAST,
+      M_AXIS_TREADY => M_AXIS_TREADY
+    );
+END af_sim_axis_prog_audio_filt_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_clk_rst_generator_0_0/sim/af_sim_clk_rst_generator_0_0.vhd

@@ -0,0 +1,97 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: wg:user:clk_rst_generator:1.0
+-- IP Revision: 7
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY af_sim_clk_rst_generator_0_0 IS
+  PORT (
+    clk : OUT STD_LOGIC;
+    rst_n : OUT STD_LOGIC;
+    stop_simulation : IN STD_LOGIC
+  );
+END af_sim_clk_rst_generator_0_0;
+
+ARCHITECTURE af_sim_clk_rst_generator_0_0_arch OF af_sim_clk_rst_generator_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT clk_rst_generator IS
+    GENERIC (
+      CLOCK_PERIOD : INTEGER;
+      HAS_CLK_INPUT : BOOLEAN;
+      HAS_RESET_INPUT : BOOLEAN;
+      HAS_STOP_INPUT : BOOLEAN
+    );
+    PORT (
+      clk_in : IN STD_LOGIC;
+      rst_in : IN STD_LOGIC;
+      clk : OUT STD_LOGIC;
+      rst_n : OUT STD_LOGIC;
+      stop_simulation : IN STD_LOGIC
+    );
+  END COMPONENT clk_rst_generator;
+BEGIN
+  U0 : clk_rst_generator
+    GENERIC MAP (
+      CLOCK_PERIOD => 8000,
+      HAS_CLK_INPUT => false,
+      HAS_RESET_INPUT => false,
+      HAS_STOP_INPUT => true
+    )
+    PORT MAP (
+      clk_in => '1',
+      rst_in => '0',
+      clk => clk,
+      rst_n => rst_n,
+      stop_simulation => stop_simulation
+    );
+END af_sim_clk_rst_generator_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/45f9/axis_audio_master_simmodel.vhd

@@ -0,0 +1,152 @@
+------------------------------------------------------------------------------
+-- axis_audio_master_simmodel.vhd - entity/architecture pair
+------------------------------------------------------------------------------
+----------------------------------------------------------
+-- Prof. Dr.-Ing. W. Gehrke (c) 2020
+----------------------------------------------------------
+
+use std.textio.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wav_pkg.all;
+
+entity axis_audio_master_simmodel is
+  generic
+  (
+    CLOCK_CYCLES_PER_SAMPLE        : integer := 2083;
+    FILE_NAME	     	           : string  := string'("tst")
+  );
+  port
+  (
+    ACLK		                   : in  std_logic;
+    ARESETN	                       : in  std_logic;
+
+    M_AXIS_TVALID                  : out std_logic;
+    M_AXIS_TDATA                   : out std_logic_vector(31 downto 0);
+    M_AXIS_TREADY                  : in  std_logic;
+    
+    WAV_HEADER                     : out std_logic_vector(44*8-1 downto 0)
+   );
+
+end entity axis_audio_master_simmodel;
+
+
+architecture sim of axis_audio_master_simmodel is
+
+    signal rnd : unsigned (31 downto 0) := x"ABBAABBA";  
+    signal local_clk : std_logic;
+
+begin
+    
+-- synthesis translate_off
+-- translate off
+
+    local_clk <= ACLK;
+            
+    --  uint32_t xorshift32() {
+    --    static uint32_t x = 314159265;
+    --    x ^= x << 13;
+    --    x ^= x >> 17;
+    --    x ^= x << 5;
+    --    return x;
+    --  }
+    process     
+        variable r : unsigned (31 downto 0);
+    begin
+        wait until rising_edge(local_clk);
+        r := rnd;
+        r := r xor (r(18 downto 0)& x"000"&"0");
+        r := r xor (x"0000"&"0"&r(31 downto 17));
+        r := r xor (r(26 downto 0)& "00000");
+        rnd <= r;
+    end process;
+
+
+    process
+        variable file_num 	 : integer := 0;        
+        variable num_samples : integer;
+        variable sample      : std_logic_vector(31 downto 0);
+
+        variable delay_cnt   : integer;
+        variable tvalid_cnt  : integer := 31415;
+        
+        file     f    		 : WAV_FILE_TYPE;
+        variable header      : WAV_HEADER_TYPE;
+        variable file_status : file_open_status;
+        variable ok	   		 : boolean;  
+        variable cyccnt      : integer;                      
+                
+    begin
+
+        wait until rising_edge (local_clk);
+        if (ARESETN = '0') then
+            M_AXIS_TVALID	<= '0';
+            M_AXIS_TDATA 	<= (others=>'0');
+            file_num 		:= 0;
+            tvalid_cnt      := to_integer(rnd and x"0000001F");
+        else
+            M_AXIS_TVALID <= '0';
+            
+            -- Start-Up delay
+            for i in 0 to 100 loop
+                wait until rising_edge (local_clk);
+            end loop;
+                        
+            M_AXIS_TVALID <= '0';
+            
+            -- Create filename and try to open the file
+            file_open ( file_status, f, FILE_NAME & ".wav", read_mode);
+            
+            -- File open succeeded ?
+            if file_status /= open_ok then
+			    assert false report "AXIS_AUDIO_MASTER_SIMMODEL: Cannot open input file." & FILE_NAME & ".wav" severity failure;
+		    else
+                read_wav_header(ok,num_samples,header,f);
+                
+                assert ok report "AXIS_AUDIO_MASTER_SIMMODEL: Input is not in WAV format." severity failure;
+                
+                for i in 0 to 43 loop
+                    WAV_HEADER(8*(i+1)-1 downto 8*i) <= std_logic_vector(to_unsigned(header(i),8));
+                end loop;
+                if ok then
+                    for s in 0 to num_samples-1 loop	-- sample loop
+                        M_AXIS_TDATA ( 7 downto  0) <= std_logic_vector(to_unsigned(wavget8(f),8));
+                        M_AXIS_TDATA (15 downto  8) <= std_logic_vector(to_unsigned(wavget8(f),8));
+                        M_AXIS_TDATA (23 downto 16) <= std_logic_vector(to_unsigned(wavget8(f),8));
+                        M_AXIS_TDATA (31 downto 24) <= std_logic_vector(to_unsigned(wavget8(f),8));
+                        M_AXIS_TVALID <= '1';
+                         -- wait until data has been acknowledged
+                        wait until rising_edge (local_clk);
+                        cyccnt := CLOCK_CYCLES_PER_SAMPLE;
+                        while M_AXIS_TREADY = '0' loop
+                            wait until rising_edge (local_clk);
+                            cyccnt := cyccnt - 1;
+                        end loop;
+                        M_AXIS_TVALID <= '0';
+                        while cyccnt > 0 loop
+                            wait until rising_edge (local_clk);
+                            cyccnt := cyccnt - 1;
+                        end loop;
+                    end loop;			-- sample loop
+                    file_close(f);
+                end if;	-- if ok
+            end if;	-- if open_status ok
+            
+            M_AXIS_TVALID <= '0';
+                        
+            -- wait until reset is activated
+            while ARESETN = '1' loop
+                wait until rising_edge (local_clk);
+            end loop;
+
+        end if;
+    end process;
+
+-- synthesis translate_on
+-- translate on
+
+ 
+end sim;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/45f9/wav_pkg.vhd

@@ -0,0 +1,64 @@
+
+use std.textio.all;
+
+package wav_pkg is
+  
+    type      WAV_FILE_TYPE is file of character;
+    type      WAV_HEADER_TYPE is array (0 to 43) of integer;
+    
+	procedure wavput8  (value : in  integer; file f : WAV_FILE_TYPE );
+	procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
+	
+	impure function  wavget8  (file f : WAV_FILE_TYPE ) return integer;
+	procedure read_wav_header (success : inout boolean; numsamples : inout  integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
+
+end;
+  
+package body wav_pkg is
+
+procedure wavput8 (value : in  integer; file f : WAV_FILE_TYPE ) is
+begin
+	write(f, character'val(value));
+end wavput8;
+
+procedure  write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
+begin
+	for i in 0 to 43 loop
+	   wavput8(header(i),f);
+	end loop;	        
+end write_wav_header;
+
+
+
+impure function wavget8 (file f : WAV_FILE_TYPE ) return integer is
+    variable chr           : character;
+begin
+    read (f,chr);
+    return character'pos(chr);
+end wavget8;
+
+procedure read_wav_header (success : inout boolean; numsamples : inout  integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
+    variable chr : character;
+    variable val : integer;
+begin
+	success := true;
+	for i in 0 to 43 loop
+	   header(i) := wavget8(f);
+	end loop;
+	numsamples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
+	
+	if header(0) /= 16#52# or header(1) /= 16#49# or header(2) /= 16#46# or header(3) /= 16#46# then   -- check for 'RIFF'
+        numsamples := 0;
+        success    := false; 
+	end if;
+	
+	if header(8) /= 16#57# or header(9) /= 16#41# or header(10) /= 16#56# or header(11) /= 16#45# then   -- check for 'WAVE'
+        numsamples := 0;
+ 	    success := false; 
+	end if;
+	
+end read_wav_header;
+
+
+end package body;
+

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/4738/sources_1/new/axis_audio_mono2stereo.vhd

@@ -0,0 +1,51 @@
+--------------------------------------------------------------------------
+--
+-- AXI Stream Audio Mono to Stereo
+--
+-- Prof. Dr.-Ing. W. Gehrke (c) 2020
+--
+--------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity axis_audio_mono2stereo is
+    generic
+    (
+        HAS_LAST         : boolean     := false
+    );
+    port
+    (
+        AXIS_ACLK               : in  std_logic;
+
+        -- AXI Streaming Target Port
+        S_AXIS_TVALID           : in  std_logic;
+        S_AXIS_TDATA            : in  std_logic_vector(15 downto 0);
+        S_AXIS_TLAST            : in  std_logic := '0';
+        S_AXIS_TREADY           : out std_logic;
+
+        -- AXI Streaming Initiator Port
+        M_AXIS_TVALID           : out std_logic;
+        M_AXIS_TDATA            : out std_logic_vector(31 downto 0);
+        M_AXIS_TLAST            : out std_logic;
+        M_AXIS_TREADY           : in  std_logic
+    );  
+end;
+
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+
+architecture rtl of axis_audio_mono2stereo is
+     
+begin
+
+    S_AXIS_TREADY <= M_AXIS_TREADY;
+    M_AXIS_TVALID <= S_AXIS_TVALID;
+    M_AXIS_TLAST  <= S_AXIS_TLAST;
+    
+    M_AXIS_TDATA (31 downto 16) <= S_AXIS_TDATA;
+    M_AXIS_TDATA (15 downto  0) <= S_AXIS_TDATA;
+        
+end;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/9a97/sources_1/new/clk_rst_generator.vhd

@@ -0,0 +1,114 @@
+------------------------------------------------------------------------------
+-- clk_rst_generator.vhd - entity/architecture pair
+------------------------------------------------------------------------------
+----------------------------------------------------------
+-- Prof. Dr.-Ing. W. Gehrke (c) 2024
+----------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity clk_rst_generator is
+  generic
+  (
+    CLOCK_PERIOD        : integer  := 10000;
+    HAS_CLK_INPUT       : boolean  := true;
+    HAS_RESET_INPUT     : boolean  := true;
+    HAS_STOP_INPUT      : boolean  := true
+  );
+  port
+  (
+    clk_in                  : in   std_logic := '1';
+    rst_in                  : in   std_logic := '0';
+    
+    clk                     : out  std_logic;
+    rst_n                   : out  std_logic;
+
+    stop_simulation         : in   std_logic := '0'
+  );
+
+end;
+
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+
+architecture rtl of clk_rst_generator is
+
+    signal clk_sim      : std_logic := '1';
+    signal clk_in_sig   : std_logic := '1';
+    signal clk_sig      : std_logic := '1';
+    signal rst_sig      : std_logic := '0';
+    signal rst_in_sync  : std_logic := '0';
+    
+begin
+    clk    	    <= clk_sig;
+	rst_n       <= not rst_sig;
+
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+    -- CLOCK GENERATION
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+    
+    clk_sig  <= clk_in_sig and clk_sim; 
+                                    -- Dies ist kein gated Clock!
+                                    -- Fuer die Synthese ist clk_sim konstant '1'
+                                    -- somit wird die UND-Verknuepfung 'wegoptimiert'
+                                    -- und was übrig bleibt, ist ein 'Draht' 
+	
+    -- synthesis translate_off
+	clk_sim      <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
+	assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
+	assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
+	assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
+    -- synthesis translate_on
+
+    process (clk_in) begin
+        clk_in_sig 	<= clk_in;
+        -- synthesis translate_off
+        clk_in_sig 	<= '1';
+        -- synthesis translate_on
+    end process;
+
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+    -- RESET GENERATION
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+
+    process
+        variable rescnt : unsigned (6 downto 0) := (others=>'1'); 
+    begin
+        wait until rising_edge(clk_sig);
+
+        rst_in_sync <= rst_in;
+        if rst_in_sync = '1' then
+            rescnt := (others=>'1');
+        end if;
+
+        if rescnt = 0 then
+            rst_sig <= '0';
+        else
+            rescnt := rescnt - 1;
+            rst_sig <= '1';
+        end if;
+    end process;
+    
+    
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+    -- STOP SIMULATION INPUT (simulation only)
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+
+    -- synthesis translate_off
+ 	process (stop_simulation) begin
+        if stop_simulation = '1' then
+			assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
+		end if;
+	end process;
+    -- synthesis translate_on
+
+end rtl;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/9e1d/sources_1/new/axis_audio_stereo2mono.vhd

@@ -0,0 +1,58 @@
+--------------------------------------------------------------------------
+--
+-- AXI Stream Audio Stereo to Mono
+--
+-- Prof. Dr.-Ing. W. Gehrke (c) 2020/2021
+--
+--------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity axis_audio_stereo2mono is
+    generic
+    (
+        HAS_LAST         : boolean     := false
+    );
+    port
+    (
+        AXIS_ACLK               : in  std_logic;
+
+        -- AXI Streaming Target Port
+        S_AXIS_TVALID           : in  std_logic;
+        S_AXIS_TDATA            : in  std_logic_vector(31 downto 0);
+        S_AXIS_TLAST            : in  std_logic := '0';
+        S_AXIS_TREADY           : out std_logic;
+
+        -- AXI Streaming Initiator Port
+        M_AXIS_TVALID           : out std_logic;
+        M_AXIS_TDATA            : out std_logic_vector(15 downto 0);
+        M_AXIS_TLAST            : out std_logic;
+        M_AXIS_TREADY           : in  std_logic
+    );  
+end;
+
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+
+architecture rtl of axis_audio_stereo2mono is
+     signal m_valid_sig : std_logic := '0';
+begin
+
+    S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
+    
+    process begin
+        wait until rising_edge(AXIS_ACLK);
+        if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
+            M_AXIS_TDATA  <= std_logic_vector(signed(S_AXIS_TDATA(31)&S_AXIS_TDATA(31 downto 17))+signed(S_AXIS_TDATA(15)&S_AXIS_TDATA(15 downto 1)));
+            M_AXIS_TVALID <= S_AXIS_TVALID;
+            m_valid_sig   <= S_AXIS_TVALID;
+            M_AXIS_TLAST  <= S_AXIS_TLAST;
+        end if;
+    end process;
+    
+        
+end;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/efba/axis_audio_slave_simmodel.vhd

@@ -0,0 +1,147 @@
+------------------------------------------------------------------------------
+-- axis_audio_slave_simmodel.vhd - entity/architecture pair
+------------------------------------------------------------------------------
+----------------------------------------------------------
+-- Prof. Dr.-Ing. W. Gehrke (c) 2020
+----------------------------------------------------------
+
+use std.textio.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wav_pkg.all;
+
+entity axis_audio_slave_simmodel is
+  generic
+  (
+    FILE_NAME	     	           : string  := string'("tst_out");
+    RANDOM_TREADY                  : boolean := true   
+  );
+  port
+  (
+    ACLK		                   : in  std_logic;
+    ARESETN	                       : in  std_logic;
+
+    S_AXIS_TVALID                  : in  std_logic;
+    S_AXIS_TDATA                   : in  std_logic_vector(31 downto 0);
+    S_AXIS_TREADY                  : out std_logic;
+    
+    FINISHED                       : out std_logic;
+    WAV_HEADER                     : in  std_logic_vector(11*32-1 downto 0)
+   );
+
+end entity;
+
+
+architecture sim of axis_audio_slave_simmodel is
+
+    signal rnd : unsigned (31 downto 0) := x"ABBAABBA";  
+    signal local_clk : std_logic;
+
+begin
+    
+-- synthesis translate_off
+-- translate off
+
+    local_clk <= ACLK;
+            
+    --  uint32_t xorshift32() {
+    --    static uint32_t x = 314159265;
+    --    x ^= x << 13;
+    --    x ^= x >> 17;
+    --    x ^= x << 5;
+    --    return x;
+    --  }
+    process     
+        variable r : unsigned (31 downto 0);
+    begin
+        wait until rising_edge(local_clk);
+        r := rnd;
+        r := r xor (r(18 downto 0)& x"000"&"0");
+        r := r xor (x"0000"&"0"&r(31 downto 17));
+        r := r xor (r(26 downto 0)& "00000");
+        rnd <= r;
+    end process;
+
+
+    process
+        variable num_samples : integer;
+
+        variable delay_cnt   : integer;
+        variable tready_cnt  : integer := 31415;
+        
+        file     f    		 : WAV_FILE_TYPE;
+        variable header      : WAV_HEADER_TYPE;
+        variable file_status : file_open_status;
+                
+    begin
+
+        wait until rising_edge (local_clk);
+        if (ARESETN = '0') then
+            tready_cnt      := to_integer(rnd and x"0000001F");
+            FINISHED <= '0';
+        else
+            S_AXIS_TREADY <= '1';
+            FINISHED <= '0';
+            -- Create filename and try to open the file
+            file_open ( file_status, f, FILE_NAME & ".wav", write_mode);
+            
+            -- File open succeeded ?
+            if file_status /= open_ok then
+			    assert false report "AXIS_AUDIO_SLAVE_SIMMODEL: Cannot open input file." & FILE_NAME & ".wav" severity failure;
+		    else
+            
+                wait until S_AXIS_TVALID = '1';
+                for i in 0 to 43 loop
+                    header(i) := to_integer(unsigned(WAV_HEADER(8*(i+1)-1 downto 8*i)));
+                end loop;
+                write_wav_header(header,f);
+                
+                num_samples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
+                                
+                for s in 0 to num_samples-1 loop	-- sample loop
+                
+                    S_AXIS_TREADY <= '1';
+                    wait until rising_edge(local_clk);
+                    while S_AXIS_TVALID /= '1' loop
+                        wait until rising_edge(local_clk);
+                    end loop;
+                    
+                    wavput8 (to_integer(unsigned(S_AXIS_TDATA( 7 downto  0))),f);
+                    wavput8 (to_integer(unsigned(S_AXIS_TDATA(15 downto  8))),f);
+                    wavput8 (to_integer(unsigned(S_AXIS_TDATA(23 downto 16))),f);
+                    wavput8 (to_integer(unsigned(S_AXIS_TDATA(31 downto 24))),f);
+                                            
+			        tready_cnt := tready_cnt - 1;
+                    if RANDOM_TREADY and tready_cnt <= 0 then
+                        -- random TREADY delay 
+                        delay_cnt := to_integer(rnd and x"00000007");
+                        while delay_cnt > 0 loop
+                            S_AXIS_TREADY <= '0';
+                            delay_cnt := delay_cnt - 1;
+                            wait until rising_edge (local_clk);
+                            tready_cnt := to_integer(rnd and x"0000001F");
+                        end loop;
+                    end if; 
+                end loop;			-- sample loop
+                
+                file_close(f);
+                FINISHED <= '1';
+                
+            end if;	-- if open_status ok
+            
+            -- wait until reset is activated
+            while ARESETN = '1' loop
+                wait until rising_edge (local_clk);
+            end loop;
+
+        end if;
+    end process;
+
+-- synthesis translate_on
+-- translate on
+
+ 
+end sim;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/efba/wav_pkg.vhd

@@ -0,0 +1,64 @@
+
+use std.textio.all;
+
+package wav_pkg is
+  
+    type      WAV_FILE_TYPE is file of character;
+    type      WAV_HEADER_TYPE is array (0 to 43) of integer;
+    
+	procedure wavput8  (value : in  integer; file f : WAV_FILE_TYPE );
+	procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
+	
+	impure function  wavget8  (file f : WAV_FILE_TYPE ) return integer;
+	procedure read_wav_header (success : inout boolean; numsamples : inout  integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
+
+end;
+  
+package body wav_pkg is
+
+procedure wavput8 (value : in  integer; file f : WAV_FILE_TYPE ) is
+begin
+	write(f, character'val(value));
+end wavput8;
+
+procedure  write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
+begin
+	for i in 0 to 43 loop
+	   wavput8(header(i),f);
+	end loop;	        
+end write_wav_header;
+
+
+
+impure function wavget8 (file f : WAV_FILE_TYPE ) return integer is
+    variable chr           : character;
+begin
+    read (f,chr);
+    return character'pos(chr);
+end wavget8;
+
+procedure read_wav_header (success : inout boolean; numsamples : inout  integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
+    variable chr : character;
+    variable val : integer;
+begin
+	success := true;
+	for i in 0 to 43 loop
+	   header(i) := wavget8(f);
+	end loop;
+	numsamples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
+	
+	if header(0) /= 16#52# or header(1) /= 16#49# or header(2) /= 16#46# or header(3) /= 16#46# then   -- check for 'RIFF'
+        numsamples := 0;
+        success    := false; 
+	end if;
+	
+	if header(8) /= 16#57# or header(9) /= 16#41# or header(10) /= 16#56# or header(11) /= 16#45# then   -- check for 'WAVE'
+        numsamples := 0;
+ 	    success := false; 
+	end if;
+	
+end read_wav_header;
+
+
+end package body;
+

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/constrs_1/new/axil_master_with_rom_ooc.xdc

@@ -0,0 +1 @@
+create_clock -period 10.000 -name M_AXIL_ACLK -waveform {0.000 5.000} [get_ports M_AXIL_ACLK]

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_stub.v

@@ -0,0 +1,47 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:25:48 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_stub.v
+// Design      : design_1_axil_master_with_rom_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axil_master_with_rom,Vivado 2023.1" *)
+module design_1_axil_master_with_rom_0_0(interrupt_in, M_AXIL_ACLK, M_AXIL_ARESETN, 
+  M_AXIL_ARREADY, M_AXIL_ARVALID, M_AXIL_ARADDR, M_AXIL_ARPROT, M_AXIL_RREADY, M_AXIL_RVALID, 
+  M_AXIL_RDATA, M_AXIL_RRESP, M_AXIL_AWREADY, M_AXIL_AWVALID, M_AXIL_AWADDR, M_AXIL_AWPROT, 
+  M_AXIL_WREADY, M_AXIL_WVALID, M_AXIL_WDATA, M_AXIL_WSTRB, M_AXIL_BREADY, M_AXIL_BVALID, 
+  M_AXIL_BRESP)
+/* synthesis syn_black_box black_box_pad_pin="interrupt_in,M_AXIL_ARESETN,M_AXIL_ARREADY,M_AXIL_ARVALID,M_AXIL_ARADDR[31:0],M_AXIL_ARPROT[2:0],M_AXIL_RREADY,M_AXIL_RVALID,M_AXIL_RDATA[31:0],M_AXIL_RRESP[1:0],M_AXIL_AWREADY,M_AXIL_AWVALID,M_AXIL_AWADDR[31:0],M_AXIL_AWPROT[2:0],M_AXIL_WREADY,M_AXIL_WVALID,M_AXIL_WDATA[31:0],M_AXIL_WSTRB[3:0],M_AXIL_BREADY,M_AXIL_BVALID,M_AXIL_BRESP[1:0]" */
+/* synthesis syn_force_seq_prim="M_AXIL_ACLK" */;
+  input interrupt_in;
+  input M_AXIL_ACLK /* synthesis syn_isclock = 1 */;
+  input M_AXIL_ARESETN;
+  input M_AXIL_ARREADY;
+  output M_AXIL_ARVALID;
+  output [31:0]M_AXIL_ARADDR;
+  output [2:0]M_AXIL_ARPROT;
+  output M_AXIL_RREADY;
+  input M_AXIL_RVALID;
+  input [31:0]M_AXIL_RDATA;
+  input [1:0]M_AXIL_RRESP;
+  input M_AXIL_AWREADY;
+  output M_AXIL_AWVALID;
+  output [31:0]M_AXIL_AWADDR;
+  output [2:0]M_AXIL_AWPROT;
+  input M_AXIL_WREADY;
+  output M_AXIL_WVALID;
+  output [31:0]M_AXIL_WDATA;
+  output [3:0]M_AXIL_WSTRB;
+  output M_AXIL_BREADY;
+  input M_AXIL_BVALID;
+  input [1:0]M_AXIL_BRESP;
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/sim/design_1_axil_master_with_rom_0_0.vhd

@@ -0,0 +1,176 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: wg:user:axil_master_with_rom:1.0
+-- IP Revision: 17
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axil_master_with_rom_0_0 IS
+  PORT (
+    interrupt_in : IN STD_LOGIC;
+    M_AXIL_ACLK : IN STD_LOGIC;
+    M_AXIL_ARESETN : IN STD_LOGIC;
+    M_AXIL_ARREADY : IN STD_LOGIC;
+    M_AXIL_ARVALID : OUT STD_LOGIC;
+    M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    M_AXIL_RREADY : OUT STD_LOGIC;
+    M_AXIL_RVALID : IN STD_LOGIC;
+    M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    M_AXIL_AWREADY : IN STD_LOGIC;
+    M_AXIL_AWVALID : OUT STD_LOGIC;
+    M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    M_AXIL_WREADY : IN STD_LOGIC;
+    M_AXIL_WVALID : OUT STD_LOGIC;
+    M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    M_AXIL_BREADY : OUT STD_LOGIC;
+    M_AXIL_BVALID : IN STD_LOGIC;
+    M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
+  );
+END design_1_axil_master_with_rom_0_0;
+
+ARCHITECTURE design_1_axil_master_with_rom_0_0_arch OF design_1_axil_master_with_rom_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axil_master_with_rom IS
+    GENERIC (
+      STIM_FILENAME : STRING;
+      HAS_FINISHED_OUT : BOOLEAN;
+      HAS_INTERRUPT_IN : BOOLEAN
+    );
+    PORT (
+      interrupt_in : IN STD_LOGIC;
+      finished_o : OUT STD_LOGIC;
+      M_AXIL_ACLK : IN STD_LOGIC;
+      M_AXIL_ARESETN : IN STD_LOGIC;
+      M_AXIL_ARREADY : IN STD_LOGIC;
+      M_AXIL_ARVALID : OUT STD_LOGIC;
+      M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      M_AXIL_RREADY : OUT STD_LOGIC;
+      M_AXIL_RVALID : IN STD_LOGIC;
+      M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      M_AXIL_AWREADY : IN STD_LOGIC;
+      M_AXIL_AWVALID : OUT STD_LOGIC;
+      M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      M_AXIL_WREADY : IN STD_LOGIC;
+      M_AXIL_WVALID : OUT STD_LOGIC;
+      M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      M_AXIL_BREADY : OUT STD_LOGIC;
+      M_AXIL_BVALID : IN STD_LOGIC;
+      M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
+    );
+  END COMPONENT axil_master_with_rom;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" & 
+"SERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID";
+BEGIN
+  U0 : axil_master_with_rom
+    GENERIC MAP (
+      STIM_FILENAME => "../../stimuli.mem",
+      HAS_FINISHED_OUT => false,
+      HAS_INTERRUPT_IN => true
+    )
+    PORT MAP (
+      interrupt_in => interrupt_in,
+      M_AXIL_ACLK => M_AXIL_ACLK,
+      M_AXIL_ARESETN => M_AXIL_ARESETN,
+      M_AXIL_ARREADY => M_AXIL_ARREADY,
+      M_AXIL_ARVALID => M_AXIL_ARVALID,
+      M_AXIL_ARADDR => M_AXIL_ARADDR,
+      M_AXIL_ARPROT => M_AXIL_ARPROT,
+      M_AXIL_RREADY => M_AXIL_RREADY,
+      M_AXIL_RVALID => M_AXIL_RVALID,
+      M_AXIL_RDATA => M_AXIL_RDATA,
+      M_AXIL_RRESP => M_AXIL_RRESP,
+      M_AXIL_AWREADY => M_AXIL_AWREADY,
+      M_AXIL_AWVALID => M_AXIL_AWVALID,
+      M_AXIL_AWADDR => M_AXIL_AWADDR,
+      M_AXIL_AWPROT => M_AXIL_AWPROT,
+      M_AXIL_WREADY => M_AXIL_WREADY,
+      M_AXIL_WVALID => M_AXIL_WVALID,
+      M_AXIL_WDATA => M_AXIL_WDATA,
+      M_AXIL_WSTRB => M_AXIL_WSTRB,
+      M_AXIL_BREADY => M_AXIL_BREADY,
+      M_AXIL_BVALID => M_AXIL_BVALID,
+      M_AXIL_BRESP => M_AXIL_BRESP
+    );
+END design_1_axil_master_with_rom_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/synth/design_1_axil_master_with_rom_0_0.vhd

@@ -0,0 +1,182 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: wg:user:axil_master_with_rom:1.0
+-- IP Revision: 17
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axil_master_with_rom_0_0 IS
+  PORT (
+    interrupt_in : IN STD_LOGIC;
+    M_AXIL_ACLK : IN STD_LOGIC;
+    M_AXIL_ARESETN : IN STD_LOGIC;
+    M_AXIL_ARREADY : IN STD_LOGIC;
+    M_AXIL_ARVALID : OUT STD_LOGIC;
+    M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    M_AXIL_RREADY : OUT STD_LOGIC;
+    M_AXIL_RVALID : IN STD_LOGIC;
+    M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    M_AXIL_AWREADY : IN STD_LOGIC;
+    M_AXIL_AWVALID : OUT STD_LOGIC;
+    M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    M_AXIL_WREADY : IN STD_LOGIC;
+    M_AXIL_WVALID : OUT STD_LOGIC;
+    M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    M_AXIL_BREADY : OUT STD_LOGIC;
+    M_AXIL_BVALID : IN STD_LOGIC;
+    M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
+  );
+END design_1_axil_master_with_rom_0_0;
+
+ARCHITECTURE design_1_axil_master_with_rom_0_0_arch OF design_1_axil_master_with_rom_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axil_master_with_rom IS
+    GENERIC (
+      STIM_FILENAME : STRING;
+      HAS_FINISHED_OUT : BOOLEAN;
+      HAS_INTERRUPT_IN : BOOLEAN
+    );
+    PORT (
+      interrupt_in : IN STD_LOGIC;
+      finished_o : OUT STD_LOGIC;
+      M_AXIL_ACLK : IN STD_LOGIC;
+      M_AXIL_ARESETN : IN STD_LOGIC;
+      M_AXIL_ARREADY : IN STD_LOGIC;
+      M_AXIL_ARVALID : OUT STD_LOGIC;
+      M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      M_AXIL_RREADY : OUT STD_LOGIC;
+      M_AXIL_RVALID : IN STD_LOGIC;
+      M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      M_AXIL_AWREADY : IN STD_LOGIC;
+      M_AXIL_AWVALID : OUT STD_LOGIC;
+      M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      M_AXIL_WREADY : IN STD_LOGIC;
+      M_AXIL_WVALID : OUT STD_LOGIC;
+      M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      M_AXIL_BREADY : OUT STD_LOGIC;
+      M_AXIL_BVALID : IN STD_LOGIC;
+      M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
+    );
+  END COMPONENT axil_master_with_rom;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "axil_master_with_rom,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axil_master_with_rom_0_0_arch : ARCHITECTURE IS "design_1_axil_master_with_rom_0_0,axil_master_with_rom,{}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "package_project";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" & 
+"SERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID";
+BEGIN
+  U0 : axil_master_with_rom
+    GENERIC MAP (
+      STIM_FILENAME => "../../stimuli.mem",
+      HAS_FINISHED_OUT => false,
+      HAS_INTERRUPT_IN => true
+    )
+    PORT MAP (
+      interrupt_in => interrupt_in,
+      M_AXIL_ACLK => M_AXIL_ACLK,
+      M_AXIL_ARESETN => M_AXIL_ARESETN,
+      M_AXIL_ARREADY => M_AXIL_ARREADY,
+      M_AXIL_ARVALID => M_AXIL_ARVALID,
+      M_AXIL_ARADDR => M_AXIL_ARADDR,
+      M_AXIL_ARPROT => M_AXIL_ARPROT,
+      M_AXIL_RREADY => M_AXIL_RREADY,
+      M_AXIL_RVALID => M_AXIL_RVALID,
+      M_AXIL_RDATA => M_AXIL_RDATA,
+      M_AXIL_RRESP => M_AXIL_RRESP,
+      M_AXIL_AWREADY => M_AXIL_AWREADY,
+      M_AXIL_AWVALID => M_AXIL_AWVALID,
+      M_AXIL_AWADDR => M_AXIL_AWADDR,
+      M_AXIL_AWPROT => M_AXIL_AWPROT,
+      M_AXIL_WREADY => M_AXIL_WREADY,
+      M_AXIL_WVALID => M_AXIL_WVALID,
+      M_AXIL_WDATA => M_AXIL_WDATA,
+      M_AXIL_WSTRB => M_AXIL_WSTRB,
+      M_AXIL_BREADY => M_AXIL_BREADY,
+      M_AXIL_BVALID => M_AXIL_BVALID,
+      M_AXIL_BRESP => M_AXIL_BRESP
+    );
+END design_1_axil_master_with_rom_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/constrs_1/new/axis_audio_mono2stereo_ooc.xdc

@@ -0,0 +1 @@
+create_clock -period 10.000 [get_ports AXIS_ACLK]

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_sim_netlist.v

@@ -0,0 +1,172 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:25:44 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_sim_netlist.v
+// Design      : design_1_axis_audio_mono2ster_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) 
+(* x_core_info = "axis_audio_mono2stereo,Vivado 2023.1" *) 
+(* NotValidForBitStream *)
+module design_1_axis_audio_mono2ster_0_0
+   (AXIS_ACLK,
+    S_AXIS_TVALID,
+    S_AXIS_TDATA,
+    S_AXIS_TREADY,
+    M_AXIS_TVALID,
+    M_AXIS_TDATA,
+    M_AXIS_TREADY);
+  (* x_interface_info = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input AXIS_ACLK;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [15:0]S_AXIS_TDATA;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [31:0]M_AXIS_TDATA;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
+
+  wire [31:0]M_AXIS_TDATA;
+  wire M_AXIS_TREADY;
+  wire M_AXIS_TVALID;
+  wire [15:0]S_AXIS_TDATA;
+  wire S_AXIS_TREADY;
+  wire S_AXIS_TVALID;
+  wire NLW_U0_M_AXIS_TLAST_UNCONNECTED;
+
+  (* HAS_LAST = "FALSE" *) 
+  design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo U0
+       (.AXIS_ACLK(1'b0),
+        .M_AXIS_TDATA(M_AXIS_TDATA),
+        .M_AXIS_TLAST(NLW_U0_M_AXIS_TLAST_UNCONNECTED),
+        .M_AXIS_TREADY(M_AXIS_TREADY),
+        .M_AXIS_TVALID(M_AXIS_TVALID),
+        .S_AXIS_TDATA(S_AXIS_TDATA),
+        .S_AXIS_TLAST(1'b0),
+        .S_AXIS_TREADY(S_AXIS_TREADY),
+        .S_AXIS_TVALID(S_AXIS_TVALID));
+endmodule
+
+(* HAS_LAST = "FALSE" *) (* ORIG_REF_NAME = "axis_audio_mono2stereo" *) 
+module design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo
+   (AXIS_ACLK,
+    S_AXIS_TVALID,
+    S_AXIS_TDATA,
+    S_AXIS_TLAST,
+    S_AXIS_TREADY,
+    M_AXIS_TVALID,
+    M_AXIS_TDATA,
+    M_AXIS_TLAST,
+    M_AXIS_TREADY);
+  input AXIS_ACLK;
+  input S_AXIS_TVALID;
+  input [15:0]S_AXIS_TDATA;
+  input S_AXIS_TLAST;
+  output S_AXIS_TREADY;
+  output M_AXIS_TVALID;
+  output [31:0]M_AXIS_TDATA;
+  output M_AXIS_TLAST;
+  input M_AXIS_TREADY;
+
+  wire \<const0> ;
+  wire M_AXIS_TREADY;
+  wire [15:0]S_AXIS_TDATA;
+  wire S_AXIS_TVALID;
+
+  assign M_AXIS_TDATA[31:16] = S_AXIS_TDATA;
+  assign M_AXIS_TDATA[15:0] = S_AXIS_TDATA;
+  assign M_AXIS_TLAST = \<const0> ;
+  assign M_AXIS_TVALID = S_AXIS_TVALID;
+  assign S_AXIS_TREADY = M_AXIS_TREADY;
+  GND GND
+       (.G(\<const0> ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_stub.v

@@ -0,0 +1,28 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:25:44 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_stub.v
+// Design      : design_1_axis_audio_mono2ster_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axis_audio_mono2stereo,Vivado 2023.1" *)
+module design_1_axis_audio_mono2ster_0_0(AXIS_ACLK, S_AXIS_TVALID, S_AXIS_TDATA, 
+  S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TREADY)
+/* synthesis syn_black_box black_box_pad_pin="AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TREADY" */;
+  input AXIS_ACLK;
+  input S_AXIS_TVALID;
+  input [15:0]S_AXIS_TDATA;
+  output S_AXIS_TREADY;
+  output M_AXIS_TVALID;
+  output [31:0]M_AXIS_TDATA;
+  input M_AXIS_TREADY;
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/sim/design_1_axis_audio_mono2ster_0_0.vhd

@@ -0,0 +1,114 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
+-- IP Revision: 3
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axis_audio_mono2ster_0_0 IS
+  PORT (
+    AXIS_ACLK : IN STD_LOGIC;
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIS_TREADY : IN STD_LOGIC
+  );
+END design_1_axis_audio_mono2ster_0_0;
+
+ARCHITECTURE design_1_axis_audio_mono2ster_0_0_arch OF design_1_axis_audio_mono2ster_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_audio_mono2stereo IS
+    GENERIC (
+      HAS_LAST : BOOLEAN
+    );
+    PORT (
+      AXIS_ACLK : IN STD_LOGIC;
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC
+    );
+  END COMPONENT axis_audio_mono2stereo;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_audio_mono2stereo
+    GENERIC MAP (
+      HAS_LAST => false
+    )
+    PORT MAP (
+      AXIS_ACLK => AXIS_ACLK,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => '0',
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TREADY => M_AXIS_TREADY
+    );
+END design_1_axis_audio_mono2ster_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/synth/design_1_axis_audio_mono2ster_0_0.vhd

@@ -0,0 +1,122 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
+-- IP Revision: 3
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axis_audio_mono2ster_0_0 IS
+  PORT (
+    AXIS_ACLK : IN STD_LOGIC;
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    M_AXIS_TREADY : IN STD_LOGIC
+  );
+END design_1_axis_audio_mono2ster_0_0;
+
+ARCHITECTURE design_1_axis_audio_mono2ster_0_0_arch OF design_1_axis_audio_mono2ster_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_audio_mono2stereo IS
+    GENERIC (
+      HAS_LAST : BOOLEAN
+    );
+    PORT (
+      AXIS_ACLK : IN STD_LOGIC;
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC
+    );
+  END COMPONENT axis_audio_mono2stereo;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "axis_audio_mono2stereo,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axis_audio_mono2ster_0_0_arch : ARCHITECTURE IS "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_audio_mono2stereo,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,HAS_LAST=false}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "package_project";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_audio_mono2stereo
+    GENERIC MAP (
+      HAS_LAST => false
+    )
+    PORT MAP (
+      AXIS_ACLK => AXIS_ACLK,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => '0',
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TREADY => M_AXIS_TREADY
+    );
+END design_1_axis_audio_mono2ster_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/constrs_1/new/axis_audio_stereo2mono_ooc.xdc

@@ -0,0 +1 @@
+create_clock -period 10.000 [get_ports AXIS_ACLK]

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_sim_netlist.v

@@ -0,0 +1,439 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:25:44 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_sim_netlist.v
+// Design      : design_1_axis_audio_stereo2mo_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) 
+(* x_core_info = "axis_audio_stereo2mono,Vivado 2023.1" *) 
+(* NotValidForBitStream *)
+module design_1_axis_audio_stereo2mo_0_0
+   (AXIS_ACLK,
+    S_AXIS_TVALID,
+    S_AXIS_TDATA,
+    S_AXIS_TREADY,
+    M_AXIS_TVALID,
+    M_AXIS_TDATA,
+    M_AXIS_TREADY);
+  (* x_interface_info = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input AXIS_ACLK;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [31:0]S_AXIS_TDATA;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [15:0]M_AXIS_TDATA;
+  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
+
+  wire AXIS_ACLK;
+  wire [15:0]M_AXIS_TDATA;
+  wire M_AXIS_TREADY;
+  wire M_AXIS_TVALID;
+  wire [31:0]S_AXIS_TDATA;
+  wire S_AXIS_TREADY;
+  wire S_AXIS_TVALID;
+  wire NLW_U0_M_AXIS_TLAST_UNCONNECTED;
+
+  (* HAS_LAST = "FALSE" *) 
+  design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono U0
+       (.AXIS_ACLK(AXIS_ACLK),
+        .M_AXIS_TDATA(M_AXIS_TDATA),
+        .M_AXIS_TLAST(NLW_U0_M_AXIS_TLAST_UNCONNECTED),
+        .M_AXIS_TREADY(M_AXIS_TREADY),
+        .M_AXIS_TVALID(M_AXIS_TVALID),
+        .S_AXIS_TDATA({S_AXIS_TDATA[31:17],1'b0,S_AXIS_TDATA[15:1],1'b0}),
+        .S_AXIS_TLAST(1'b0),
+        .S_AXIS_TREADY(S_AXIS_TREADY),
+        .S_AXIS_TVALID(S_AXIS_TVALID));
+endmodule
+
+(* HAS_LAST = "FALSE" *) (* ORIG_REF_NAME = "axis_audio_stereo2mono" *) 
+module design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono
+   (AXIS_ACLK,
+    S_AXIS_TVALID,
+    S_AXIS_TDATA,
+    S_AXIS_TLAST,
+    S_AXIS_TREADY,
+    M_AXIS_TVALID,
+    M_AXIS_TDATA,
+    M_AXIS_TLAST,
+    M_AXIS_TREADY);
+  input AXIS_ACLK;
+  input S_AXIS_TVALID;
+  input [31:0]S_AXIS_TDATA;
+  input S_AXIS_TLAST;
+  output S_AXIS_TREADY;
+  output M_AXIS_TVALID;
+  output [15:0]M_AXIS_TDATA;
+  output M_AXIS_TLAST;
+  input M_AXIS_TREADY;
+
+  wire \<const0> ;
+  wire AXIS_ACLK;
+  wire [15:0]M_AXIS_TDATA;
+  wire \M_AXIS_TDATA[11]_i_2_n_0 ;
+  wire \M_AXIS_TDATA[11]_i_3_n_0 ;
+  wire \M_AXIS_TDATA[11]_i_4_n_0 ;
+  wire \M_AXIS_TDATA[11]_i_5_n_0 ;
+  wire \M_AXIS_TDATA[15]_i_2_n_0 ;
+  wire \M_AXIS_TDATA[15]_i_3_n_0 ;
+  wire \M_AXIS_TDATA[15]_i_4_n_0 ;
+  wire \M_AXIS_TDATA[15]_i_5_n_0 ;
+  wire \M_AXIS_TDATA[3]_i_2_n_0 ;
+  wire \M_AXIS_TDATA[3]_i_3_n_0 ;
+  wire \M_AXIS_TDATA[3]_i_4_n_0 ;
+  wire \M_AXIS_TDATA[3]_i_5_n_0 ;
+  wire \M_AXIS_TDATA[7]_i_2_n_0 ;
+  wire \M_AXIS_TDATA[7]_i_3_n_0 ;
+  wire \M_AXIS_TDATA[7]_i_4_n_0 ;
+  wire \M_AXIS_TDATA[7]_i_5_n_0 ;
+  wire \M_AXIS_TDATA_reg[11]_i_1_n_0 ;
+  wire \M_AXIS_TDATA_reg[11]_i_1_n_1 ;
+  wire \M_AXIS_TDATA_reg[11]_i_1_n_2 ;
+  wire \M_AXIS_TDATA_reg[11]_i_1_n_3 ;
+  wire \M_AXIS_TDATA_reg[15]_i_1_n_1 ;
+  wire \M_AXIS_TDATA_reg[15]_i_1_n_2 ;
+  wire \M_AXIS_TDATA_reg[15]_i_1_n_3 ;
+  wire \M_AXIS_TDATA_reg[3]_i_1_n_0 ;
+  wire \M_AXIS_TDATA_reg[3]_i_1_n_1 ;
+  wire \M_AXIS_TDATA_reg[3]_i_1_n_2 ;
+  wire \M_AXIS_TDATA_reg[3]_i_1_n_3 ;
+  wire \M_AXIS_TDATA_reg[7]_i_1_n_0 ;
+  wire \M_AXIS_TDATA_reg[7]_i_1_n_1 ;
+  wire \M_AXIS_TDATA_reg[7]_i_1_n_2 ;
+  wire \M_AXIS_TDATA_reg[7]_i_1_n_3 ;
+  wire M_AXIS_TREADY;
+  wire M_AXIS_TVALID;
+  wire [31:0]S_AXIS_TDATA;
+  wire S_AXIS_TREADY;
+  wire S_AXIS_TVALID;
+  wire [15:0]p_0_in;
+  wire [3:3]\NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED ;
+
+  assign M_AXIS_TLAST = \<const0> ;
+  GND GND
+       (.G(\<const0> ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[11]_i_2 
+       (.I0(S_AXIS_TDATA[28]),
+        .I1(S_AXIS_TDATA[12]),
+        .O(\M_AXIS_TDATA[11]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[11]_i_3 
+       (.I0(S_AXIS_TDATA[27]),
+        .I1(S_AXIS_TDATA[11]),
+        .O(\M_AXIS_TDATA[11]_i_3_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[11]_i_4 
+       (.I0(S_AXIS_TDATA[26]),
+        .I1(S_AXIS_TDATA[10]),
+        .O(\M_AXIS_TDATA[11]_i_4_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[11]_i_5 
+       (.I0(S_AXIS_TDATA[25]),
+        .I1(S_AXIS_TDATA[9]),
+        .O(\M_AXIS_TDATA[11]_i_5_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \M_AXIS_TDATA[15]_i_2 
+       (.I0(S_AXIS_TDATA[31]),
+        .O(\M_AXIS_TDATA[15]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[15]_i_3 
+       (.I0(S_AXIS_TDATA[31]),
+        .I1(S_AXIS_TDATA[15]),
+        .O(\M_AXIS_TDATA[15]_i_3_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[15]_i_4 
+       (.I0(S_AXIS_TDATA[30]),
+        .I1(S_AXIS_TDATA[14]),
+        .O(\M_AXIS_TDATA[15]_i_4_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[15]_i_5 
+       (.I0(S_AXIS_TDATA[29]),
+        .I1(S_AXIS_TDATA[13]),
+        .O(\M_AXIS_TDATA[15]_i_5_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[3]_i_2 
+       (.I0(S_AXIS_TDATA[20]),
+        .I1(S_AXIS_TDATA[4]),
+        .O(\M_AXIS_TDATA[3]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[3]_i_3 
+       (.I0(S_AXIS_TDATA[19]),
+        .I1(S_AXIS_TDATA[3]),
+        .O(\M_AXIS_TDATA[3]_i_3_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[3]_i_4 
+       (.I0(S_AXIS_TDATA[18]),
+        .I1(S_AXIS_TDATA[2]),
+        .O(\M_AXIS_TDATA[3]_i_4_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[3]_i_5 
+       (.I0(S_AXIS_TDATA[17]),
+        .I1(S_AXIS_TDATA[1]),
+        .O(\M_AXIS_TDATA[3]_i_5_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[7]_i_2 
+       (.I0(S_AXIS_TDATA[24]),
+        .I1(S_AXIS_TDATA[8]),
+        .O(\M_AXIS_TDATA[7]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[7]_i_3 
+       (.I0(S_AXIS_TDATA[23]),
+        .I1(S_AXIS_TDATA[7]),
+        .O(\M_AXIS_TDATA[7]_i_3_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[7]_i_4 
+       (.I0(S_AXIS_TDATA[22]),
+        .I1(S_AXIS_TDATA[6]),
+        .O(\M_AXIS_TDATA[7]_i_4_n_0 ));
+  LUT2 #(
+    .INIT(4'h6)) 
+    \M_AXIS_TDATA[7]_i_5 
+       (.I0(S_AXIS_TDATA[21]),
+        .I1(S_AXIS_TDATA[5]),
+        .O(\M_AXIS_TDATA[7]_i_5_n_0 ));
+  FDRE \M_AXIS_TDATA_reg[0] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[0]),
+        .Q(M_AXIS_TDATA[0]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[10] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[10]),
+        .Q(M_AXIS_TDATA[10]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[11] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[11]),
+        .Q(M_AXIS_TDATA[11]),
+        .R(1'b0));
+  CARRY4 \M_AXIS_TDATA_reg[11]_i_1 
+       (.CI(\M_AXIS_TDATA_reg[7]_i_1_n_0 ),
+        .CO({\M_AXIS_TDATA_reg[11]_i_1_n_0 ,\M_AXIS_TDATA_reg[11]_i_1_n_1 ,\M_AXIS_TDATA_reg[11]_i_1_n_2 ,\M_AXIS_TDATA_reg[11]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI(S_AXIS_TDATA[28:25]),
+        .O(p_0_in[11:8]),
+        .S({\M_AXIS_TDATA[11]_i_2_n_0 ,\M_AXIS_TDATA[11]_i_3_n_0 ,\M_AXIS_TDATA[11]_i_4_n_0 ,\M_AXIS_TDATA[11]_i_5_n_0 }));
+  FDRE \M_AXIS_TDATA_reg[12] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[12]),
+        .Q(M_AXIS_TDATA[12]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[13] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[13]),
+        .Q(M_AXIS_TDATA[13]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[14] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[14]),
+        .Q(M_AXIS_TDATA[14]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[15] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[15]),
+        .Q(M_AXIS_TDATA[15]),
+        .R(1'b0));
+  CARRY4 \M_AXIS_TDATA_reg[15]_i_1 
+       (.CI(\M_AXIS_TDATA_reg[11]_i_1_n_0 ),
+        .CO({\NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED [3],\M_AXIS_TDATA_reg[15]_i_1_n_1 ,\M_AXIS_TDATA_reg[15]_i_1_n_2 ,\M_AXIS_TDATA_reg[15]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,\M_AXIS_TDATA[15]_i_2_n_0 ,S_AXIS_TDATA[30:29]}),
+        .O(p_0_in[15:12]),
+        .S({1'b1,\M_AXIS_TDATA[15]_i_3_n_0 ,\M_AXIS_TDATA[15]_i_4_n_0 ,\M_AXIS_TDATA[15]_i_5_n_0 }));
+  FDRE \M_AXIS_TDATA_reg[1] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[1]),
+        .Q(M_AXIS_TDATA[1]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[2] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[2]),
+        .Q(M_AXIS_TDATA[2]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[3] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[3]),
+        .Q(M_AXIS_TDATA[3]),
+        .R(1'b0));
+  CARRY4 \M_AXIS_TDATA_reg[3]_i_1 
+       (.CI(1'b0),
+        .CO({\M_AXIS_TDATA_reg[3]_i_1_n_0 ,\M_AXIS_TDATA_reg[3]_i_1_n_1 ,\M_AXIS_TDATA_reg[3]_i_1_n_2 ,\M_AXIS_TDATA_reg[3]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI(S_AXIS_TDATA[20:17]),
+        .O(p_0_in[3:0]),
+        .S({\M_AXIS_TDATA[3]_i_2_n_0 ,\M_AXIS_TDATA[3]_i_3_n_0 ,\M_AXIS_TDATA[3]_i_4_n_0 ,\M_AXIS_TDATA[3]_i_5_n_0 }));
+  FDRE \M_AXIS_TDATA_reg[4] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[4]),
+        .Q(M_AXIS_TDATA[4]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[5] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[5]),
+        .Q(M_AXIS_TDATA[5]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[6] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[6]),
+        .Q(M_AXIS_TDATA[6]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[7] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[7]),
+        .Q(M_AXIS_TDATA[7]),
+        .R(1'b0));
+  CARRY4 \M_AXIS_TDATA_reg[7]_i_1 
+       (.CI(\M_AXIS_TDATA_reg[3]_i_1_n_0 ),
+        .CO({\M_AXIS_TDATA_reg[7]_i_1_n_0 ,\M_AXIS_TDATA_reg[7]_i_1_n_1 ,\M_AXIS_TDATA_reg[7]_i_1_n_2 ,\M_AXIS_TDATA_reg[7]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI(S_AXIS_TDATA[24:21]),
+        .O(p_0_in[7:4]),
+        .S({\M_AXIS_TDATA[7]_i_2_n_0 ,\M_AXIS_TDATA[7]_i_3_n_0 ,\M_AXIS_TDATA[7]_i_4_n_0 ,\M_AXIS_TDATA[7]_i_5_n_0 }));
+  FDRE \M_AXIS_TDATA_reg[8] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[8]),
+        .Q(M_AXIS_TDATA[8]),
+        .R(1'b0));
+  FDRE \M_AXIS_TDATA_reg[9] 
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(p_0_in[9]),
+        .Q(M_AXIS_TDATA[9]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    M_AXIS_TVALID_reg
+       (.C(AXIS_ACLK),
+        .CE(S_AXIS_TREADY),
+        .D(S_AXIS_TVALID),
+        .Q(M_AXIS_TVALID),
+        .R(1'b0));
+  LUT2 #(
+    .INIT(4'hB)) 
+    S_AXIS_TREADY_INST_0
+       (.I0(M_AXIS_TREADY),
+        .I1(M_AXIS_TVALID),
+        .O(S_AXIS_TREADY));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_stub.v

@@ -0,0 +1,29 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:25:44 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_stub.v
+// Design      : design_1_axis_audio_stereo2mo_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axis_audio_stereo2mono,Vivado 2023.1" *)
+module design_1_axis_audio_stereo2mo_0_0(AXIS_ACLK, S_AXIS_TVALID, S_AXIS_TDATA, 
+  S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TREADY)
+/* synthesis syn_black_box black_box_pad_pin="S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TREADY" */
+/* synthesis syn_force_seq_prim="AXIS_ACLK" */;
+  input AXIS_ACLK /* synthesis syn_isclock = 1 */;
+  input S_AXIS_TVALID;
+  input [31:0]S_AXIS_TDATA;
+  output S_AXIS_TREADY;
+  output M_AXIS_TVALID;
+  output [15:0]M_AXIS_TDATA;
+  input M_AXIS_TREADY;
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/sim/design_1_axis_audio_stereo2mo_0_0.vhd

@@ -0,0 +1,114 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
+-- IP Revision: 4
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axis_audio_stereo2mo_0_0 IS
+  PORT (
+    AXIS_ACLK : IN STD_LOGIC;
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    M_AXIS_TREADY : IN STD_LOGIC
+  );
+END design_1_axis_audio_stereo2mo_0_0;
+
+ARCHITECTURE design_1_axis_audio_stereo2mo_0_0_arch OF design_1_axis_audio_stereo2mo_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_audio_stereo2mono IS
+    GENERIC (
+      HAS_LAST : BOOLEAN
+    );
+    PORT (
+      AXIS_ACLK : IN STD_LOGIC;
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC
+    );
+  END COMPONENT axis_audio_stereo2mono;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_audio_stereo2mono
+    GENERIC MAP (
+      HAS_LAST => false
+    )
+    PORT MAP (
+      AXIS_ACLK => AXIS_ACLK,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => '0',
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TREADY => M_AXIS_TREADY
+    );
+END design_1_axis_audio_stereo2mo_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/synth/design_1_axis_audio_stereo2mo_0_0.vhd

@@ -0,0 +1,122 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
+-- IP Revision: 4
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axis_audio_stereo2mo_0_0 IS
+  PORT (
+    AXIS_ACLK : IN STD_LOGIC;
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    M_AXIS_TREADY : IN STD_LOGIC
+  );
+END design_1_axis_audio_stereo2mo_0_0;
+
+ARCHITECTURE design_1_axis_audio_stereo2mo_0_0_arch OF design_1_axis_audio_stereo2mo_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_audio_stereo2mono IS
+    GENERIC (
+      HAS_LAST : BOOLEAN
+    );
+    PORT (
+      AXIS_ACLK : IN STD_LOGIC;
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC
+    );
+  END COMPONENT axis_audio_stereo2mono;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "axis_audio_stereo2mono,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axis_audio_stereo2mo_0_0_arch : ARCHITECTURE IS "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_audio_stereo2mono,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,HAS_LAST=false}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "package_project";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_audio_stereo2mono
+    GENERIC MAP (
+      HAS_LAST => false
+    )
+    PORT MAP (
+      AXIS_ACLK => AXIS_ACLK,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => '0',
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TREADY => M_AXIS_TREADY
+    );
+END design_1_axis_audio_stereo2mo_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.v

@@ -0,0 +1,52 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:25:50 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.v
+// Design      : design_1_axis_prog_audio_filt_0_1
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axis_prog_audio_filter3,Vivado 2023.1" *)
+module design_1_axis_prog_audio_filt_0_1(AXI_ACLK, AXI_ARESETN, S_AXIL_AWADDR, 
+  S_AXIL_AWVALID, S_AXIL_AWREADY, S_AXIL_WDATA, S_AXIL_WVALID, S_AXIL_WREADY, S_AXIL_WSTRB, 
+  S_AXIL_BVALID, S_AXIL_BREADY, S_AXIL_BRESP, S_AXIL_ARADDR, S_AXIL_ARVALID, S_AXIL_ARREADY, 
+  S_AXIL_RDATA, S_AXIL_RVALID, S_AXIL_RREADY, S_AXIL_RRESP, S_AXIS_TVALID, S_AXIS_TDATA, 
+  S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY)
+/* synthesis syn_black_box black_box_pad_pin="AXI_ARESETN,S_AXIL_AWADDR[7:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[7:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TLAST,M_AXIS_TREADY" */
+/* synthesis syn_force_seq_prim="AXI_ACLK" */;
+  input AXI_ACLK /* synthesis syn_isclock = 1 */;
+  input AXI_ARESETN;
+  input [7:0]S_AXIL_AWADDR;
+  input S_AXIL_AWVALID;
+  output S_AXIL_AWREADY;
+  input [31:0]S_AXIL_WDATA;
+  input S_AXIL_WVALID;
+  output S_AXIL_WREADY;
+  input [3:0]S_AXIL_WSTRB;
+  output S_AXIL_BVALID;
+  input S_AXIL_BREADY;
+  output [1:0]S_AXIL_BRESP;
+  input [7:0]S_AXIL_ARADDR;
+  input S_AXIL_ARVALID;
+  output S_AXIL_ARREADY;
+  output [31:0]S_AXIL_RDATA;
+  output S_AXIL_RVALID;
+  input S_AXIL_RREADY;
+  output [1:0]S_AXIL_RRESP;
+  input S_AXIS_TVALID;
+  input [15:0]S_AXIS_TDATA;
+  input S_AXIS_TLAST;
+  output S_AXIS_TREADY;
+  output M_AXIS_TVALID;
+  output [15:0]M_AXIS_TDATA;
+  output M_AXIS_TLAST;
+  input M_AXIS_TREADY;
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/sim/design_1_axis_prog_audio_filt_0_1.vhd

@@ -0,0 +1,204 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:axis_prog_audio_filter3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axis_prog_audio_filt_0_1 IS
+  PORT (
+    AXI_ACLK : IN STD_LOGIC;
+    AXI_ARESETN : IN STD_LOGIC;
+    S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXIL_AWVALID : IN STD_LOGIC;
+    S_AXIL_AWREADY : OUT STD_LOGIC;
+    S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_WVALID : IN STD_LOGIC;
+    S_AXIL_WREADY : OUT STD_LOGIC;
+    S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXIL_BVALID : OUT STD_LOGIC;
+    S_AXIL_BREADY : IN STD_LOGIC;
+    S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXIL_ARVALID : IN STD_LOGIC;
+    S_AXIL_ARREADY : OUT STD_LOGIC;
+    S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_RVALID : OUT STD_LOGIC;
+    S_AXIL_RREADY : IN STD_LOGIC;
+    S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    S_AXIS_TLAST : IN STD_LOGIC;
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    M_AXIS_TLAST : OUT STD_LOGIC;
+    M_AXIS_TREADY : IN STD_LOGIC
+  );
+END design_1_axis_prog_audio_filt_0_1;
+
+ARCHITECTURE design_1_axis_prog_audio_filt_0_1_arch OF design_1_axis_prog_audio_filt_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_prog_audio_filter3 IS
+    GENERIC (
+      COEFF_0 : INTEGER;
+      COEFF_1 : INTEGER;
+      COEFF_2 : INTEGER;
+      SHIFT : INTEGER;
+      RUN_AFTER_RESET : BOOLEAN;
+      HAS_LAST : BOOLEAN
+    );
+    PORT (
+      AXI_ACLK : IN STD_LOGIC;
+      AXI_ARESETN : IN STD_LOGIC;
+      S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      S_AXIL_AWVALID : IN STD_LOGIC;
+      S_AXIL_AWREADY : OUT STD_LOGIC;
+      S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_WVALID : IN STD_LOGIC;
+      S_AXIL_WREADY : OUT STD_LOGIC;
+      S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXIL_BVALID : OUT STD_LOGIC;
+      S_AXIL_BREADY : IN STD_LOGIC;
+      S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      S_AXIL_ARVALID : IN STD_LOGIC;
+      S_AXIL_ARREADY : OUT STD_LOGIC;
+      S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_RVALID : OUT STD_LOGIC;
+      S_AXIL_RREADY : IN STD_LOGIC;
+      S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC
+    );
+  END COMPONENT axis_prog_audio_filter3;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI_ACLK, ASSOCIATED_RESET AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" & 
+"ITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_prog_audio_filter3
+    GENERIC MAP (
+      COEFF_0 => 42,
+      COEFF_1 => 42,
+      COEFF_2 => 42,
+      SHIFT => 7,
+      RUN_AFTER_RESET => true,
+      HAS_LAST => false
+    )
+    PORT MAP (
+      AXI_ACLK => AXI_ACLK,
+      AXI_ARESETN => AXI_ARESETN,
+      S_AXIL_AWADDR => S_AXIL_AWADDR,
+      S_AXIL_AWVALID => S_AXIL_AWVALID,
+      S_AXIL_AWREADY => S_AXIL_AWREADY,
+      S_AXIL_WDATA => S_AXIL_WDATA,
+      S_AXIL_WVALID => S_AXIL_WVALID,
+      S_AXIL_WREADY => S_AXIL_WREADY,
+      S_AXIL_WSTRB => S_AXIL_WSTRB,
+      S_AXIL_BVALID => S_AXIL_BVALID,
+      S_AXIL_BREADY => S_AXIL_BREADY,
+      S_AXIL_BRESP => S_AXIL_BRESP,
+      S_AXIL_ARADDR => S_AXIL_ARADDR,
+      S_AXIL_ARVALID => S_AXIL_ARVALID,
+      S_AXIL_ARREADY => S_AXIL_ARREADY,
+      S_AXIL_RDATA => S_AXIL_RDATA,
+      S_AXIL_RVALID => S_AXIL_RVALID,
+      S_AXIL_RREADY => S_AXIL_RREADY,
+      S_AXIL_RRESP => S_AXIL_RRESP,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => S_AXIS_TLAST,
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TLAST => M_AXIS_TLAST,
+      M_AXIS_TREADY => M_AXIS_TREADY
+    );
+END design_1_axis_prog_audio_filt_0_1_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/synth/design_1_axis_prog_audio_filt_0_1.vhd

@@ -0,0 +1,212 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:axis_prog_audio_filter3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axis_prog_audio_filt_0_1 IS
+  PORT (
+    AXI_ACLK : IN STD_LOGIC;
+    AXI_ARESETN : IN STD_LOGIC;
+    S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXIL_AWVALID : IN STD_LOGIC;
+    S_AXIL_AWREADY : OUT STD_LOGIC;
+    S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_WVALID : IN STD_LOGIC;
+    S_AXIL_WREADY : OUT STD_LOGIC;
+    S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXIL_BVALID : OUT STD_LOGIC;
+    S_AXIL_BREADY : IN STD_LOGIC;
+    S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXIL_ARVALID : IN STD_LOGIC;
+    S_AXIL_ARREADY : OUT STD_LOGIC;
+    S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_RVALID : OUT STD_LOGIC;
+    S_AXIL_RREADY : IN STD_LOGIC;
+    S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXIS_TVALID : IN STD_LOGIC;
+    S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    S_AXIS_TLAST : IN STD_LOGIC;
+    S_AXIS_TREADY : OUT STD_LOGIC;
+    M_AXIS_TVALID : OUT STD_LOGIC;
+    M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    M_AXIS_TLAST : OUT STD_LOGIC;
+    M_AXIS_TREADY : IN STD_LOGIC
+  );
+END design_1_axis_prog_audio_filt_0_1;
+
+ARCHITECTURE design_1_axis_prog_audio_filt_0_1_arch OF design_1_axis_prog_audio_filt_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_prog_audio_filter3 IS
+    GENERIC (
+      COEFF_0 : INTEGER;
+      COEFF_1 : INTEGER;
+      COEFF_2 : INTEGER;
+      SHIFT : INTEGER;
+      RUN_AFTER_RESET : BOOLEAN;
+      HAS_LAST : BOOLEAN
+    );
+    PORT (
+      AXI_ACLK : IN STD_LOGIC;
+      AXI_ARESETN : IN STD_LOGIC;
+      S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      S_AXIL_AWVALID : IN STD_LOGIC;
+      S_AXIL_AWREADY : OUT STD_LOGIC;
+      S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_WVALID : IN STD_LOGIC;
+      S_AXIL_WREADY : OUT STD_LOGIC;
+      S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXIL_BVALID : OUT STD_LOGIC;
+      S_AXIL_BREADY : IN STD_LOGIC;
+      S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      S_AXIL_ARVALID : IN STD_LOGIC;
+      S_AXIL_ARREADY : OUT STD_LOGIC;
+      S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_RVALID : OUT STD_LOGIC;
+      S_AXIL_RREADY : IN STD_LOGIC;
+      S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXIS_TVALID : IN STD_LOGIC;
+      S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      S_AXIS_TLAST : IN STD_LOGIC;
+      S_AXIS_TREADY : OUT STD_LOGIC;
+      M_AXIS_TVALID : OUT STD_LOGIC;
+      M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+      M_AXIS_TLAST : OUT STD_LOGIC;
+      M_AXIS_TREADY : IN STD_LOGIC
+    );
+  END COMPONENT axis_prog_audio_filter3;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "axis_prog_audio_filter3,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axis_prog_audio_filt_0_1_arch : ARCHITECTURE IS "design_1_axis_prog_audio_filt_0_1,axis_prog_audio_filter3,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "design_1_axis_prog_audio_filt_0_1,axis_prog_audio_filter3,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_prog_audio_filter3,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,COEFF_0=42,COEFF_1=42,COEFF_2=42,SHIFT=7,RUN_AFTER_RESET=true,HAS_LAST=false}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI_ACLK, ASSOCIATED_RESET AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" & 
+"ITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
+BEGIN
+  U0 : axis_prog_audio_filter3
+    GENERIC MAP (
+      COEFF_0 => 42,
+      COEFF_1 => 42,
+      COEFF_2 => 42,
+      SHIFT => 7,
+      RUN_AFTER_RESET => true,
+      HAS_LAST => false
+    )
+    PORT MAP (
+      AXI_ACLK => AXI_ACLK,
+      AXI_ARESETN => AXI_ARESETN,
+      S_AXIL_AWADDR => S_AXIL_AWADDR,
+      S_AXIL_AWVALID => S_AXIL_AWVALID,
+      S_AXIL_AWREADY => S_AXIL_AWREADY,
+      S_AXIL_WDATA => S_AXIL_WDATA,
+      S_AXIL_WVALID => S_AXIL_WVALID,
+      S_AXIL_WREADY => S_AXIL_WREADY,
+      S_AXIL_WSTRB => S_AXIL_WSTRB,
+      S_AXIL_BVALID => S_AXIL_BVALID,
+      S_AXIL_BREADY => S_AXIL_BREADY,
+      S_AXIL_BRESP => S_AXIL_BRESP,
+      S_AXIL_ARADDR => S_AXIL_ARADDR,
+      S_AXIL_ARVALID => S_AXIL_ARVALID,
+      S_AXIL_ARREADY => S_AXIL_ARREADY,
+      S_AXIL_RDATA => S_AXIL_RDATA,
+      S_AXIL_RVALID => S_AXIL_RVALID,
+      S_AXIL_RREADY => S_AXIL_RREADY,
+      S_AXIL_RRESP => S_AXIL_RRESP,
+      S_AXIS_TVALID => S_AXIS_TVALID,
+      S_AXIS_TDATA => S_AXIS_TDATA,
+      S_AXIS_TLAST => S_AXIS_TLAST,
+      S_AXIS_TREADY => S_AXIS_TREADY,
+      M_AXIS_TVALID => M_AXIS_TVALID,
+      M_AXIS_TDATA => M_AXIS_TDATA,
+      M_AXIS_TLAST => M_AXIS_TLAST,
+      M_AXIS_TREADY => M_AXIS_TREADY
+    );
+END design_1_axis_prog_audio_filt_0_1_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_ooc.xdc

@@ -0,0 +1 @@
+create_clock -period 10.000 -name clk_in -waveform {0.000 5.000} [get_ports clk_in]

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_sim_netlist.v

@@ -0,0 +1,375 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:25:44 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_sim_netlist.v
+// Design      : design_1_clk_rst_generator_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_clk_rst_generator_0_0,clk_rst_generator,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) 
+(* x_core_info = "clk_rst_generator,Vivado 2023.1" *) 
+(* NotValidForBitStream *)
+module design_1_clk_rst_generator_0_0
+   (clk_in,
+    rst_in,
+    clk,
+    rst_n,
+    stop_simulation);
+  input clk_in;
+  input rst_in;
+  output clk;
+  output rst_n;
+  input stop_simulation;
+
+  wire clk;
+  wire clk_in;
+  wire rst_in;
+  wire rst_n;
+
+  (* CLOCK_PERIOD = "10000" *) 
+  (* HAS_CLK_INPUT = "TRUE" *) 
+  (* HAS_RESET_INPUT = "TRUE" *) 
+  (* HAS_STOP_INPUT = "TRUE" *) 
+  design_1_clk_rst_generator_0_0_clk_rst_generator U0
+       (.clk(clk),
+        .clk_in(clk_in),
+        .rst_in(rst_in),
+        .rst_n(rst_n),
+        .stop_simulation(1'b0));
+endmodule
+
+(* CLOCK_PERIOD = "10000" *) (* HAS_CLK_INPUT = "TRUE" *) (* HAS_RESET_INPUT = "TRUE" *) 
+(* HAS_STOP_INPUT = "TRUE" *) (* ORIG_REF_NAME = "clk_rst_generator" *) 
+module design_1_clk_rst_generator_0_0_clk_rst_generator
+   (clk_in,
+    rst_in,
+    clk,
+    rst_n,
+    stop_simulation);
+  input clk_in;
+  input rst_in;
+  output clk;
+  output rst_n;
+  input stop_simulation;
+
+  wire [4:0]L;
+  wire clk_in;
+  wire [6:0]rescnt;
+  wire \rescnt[3]_i_5_n_0 ;
+  wire \rescnt[3]_i_6_n_0 ;
+  wire \rescnt[3]_i_7_n_0 ;
+  wire \rescnt[3]_i_8_n_0 ;
+  wire \rescnt[6]_i_4_n_0 ;
+  wire \rescnt[6]_i_5_n_0 ;
+  wire \rescnt[6]_i_6_n_0 ;
+  wire [6:0]rescnt_reg;
+  wire \rescnt_reg[3]_i_1_n_0 ;
+  wire \rescnt_reg[3]_i_1_n_1 ;
+  wire \rescnt_reg[3]_i_1_n_2 ;
+  wire \rescnt_reg[3]_i_1_n_3 ;
+  wire \rescnt_reg[6]_i_1_n_2 ;
+  wire \rescnt_reg[6]_i_1_n_3 ;
+  wire rst_in;
+  wire rst_in_sync;
+  wire rst_n;
+  wire rst_sig;
+  wire rst_sig_i_1_n_0;
+  wire rst_sig_i_2_n_0;
+  wire rst_sig_reg_n_0;
+  wire [3:2]\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED ;
+  wire [3:3]\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED ;
+
+  assign clk = clk_in;
+  LUT2 #(
+    .INIT(4'hE)) 
+    \rescnt[3]_i_2 
+       (.I0(rst_in_sync),
+        .I1(rescnt_reg[2]),
+        .O(L[2]));
+  LUT5 #(
+    .INIT(32'h00000001)) 
+    \rescnt[3]_i_3 
+       (.I0(rescnt_reg[6]),
+        .I1(rescnt_reg[4]),
+        .I2(rst_in_sync),
+        .I3(rescnt_reg[5]),
+        .I4(rst_sig_i_2_n_0),
+        .O(rst_sig));
+  LUT2 #(
+    .INIT(4'hE)) 
+    \rescnt[3]_i_4 
+       (.I0(rst_in_sync),
+        .I1(rescnt_reg[0]),
+        .O(L[0]));
+  LUT3 #(
+    .INIT(8'hF9)) 
+    \rescnt[3]_i_5 
+       (.I0(rescnt_reg[2]),
+        .I1(rescnt_reg[3]),
+        .I2(rst_in_sync),
+        .O(\rescnt[3]_i_5_n_0 ));
+  LUT6 #(
+    .INIT(64'h000000000001FFFE)) 
+    \rescnt[3]_i_6 
+       (.I0(rst_sig_i_2_n_0),
+        .I1(rescnt_reg[5]),
+        .I2(rescnt_reg[4]),
+        .I3(rescnt_reg[6]),
+        .I4(rescnt_reg[2]),
+        .I5(rst_in_sync),
+        .O(\rescnt[3]_i_6_n_0 ));
+  LUT6 #(
+    .INIT(64'h000000000001FFFE)) 
+    \rescnt[3]_i_7 
+       (.I0(rst_sig_i_2_n_0),
+        .I1(rescnt_reg[5]),
+        .I2(rescnt_reg[4]),
+        .I3(rescnt_reg[6]),
+        .I4(rescnt_reg[1]),
+        .I5(rst_in_sync),
+        .O(\rescnt[3]_i_7_n_0 ));
+  LUT6 #(
+    .INIT(64'h0055005500550056)) 
+    \rescnt[3]_i_8 
+       (.I0(rescnt_reg[0]),
+        .I1(rst_sig_i_2_n_0),
+        .I2(rescnt_reg[5]),
+        .I3(rst_in_sync),
+        .I4(rescnt_reg[4]),
+        .I5(rescnt_reg[6]),
+        .O(\rescnt[3]_i_8_n_0 ));
+  LUT2 #(
+    .INIT(4'hE)) 
+    \rescnt[6]_i_2 
+       (.I0(rst_in_sync),
+        .I1(rescnt_reg[4]),
+        .O(L[4]));
+  LUT2 #(
+    .INIT(4'hE)) 
+    \rescnt[6]_i_3 
+       (.I0(rst_in_sync),
+        .I1(rescnt_reg[3]),
+        .O(L[3]));
+  LUT3 #(
+    .INIT(8'hF9)) 
+    \rescnt[6]_i_4 
+       (.I0(rescnt_reg[5]),
+        .I1(rescnt_reg[6]),
+        .I2(rst_in_sync),
+        .O(\rescnt[6]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8'hF9)) 
+    \rescnt[6]_i_5 
+       (.I0(rescnt_reg[4]),
+        .I1(rescnt_reg[5]),
+        .I2(rst_in_sync),
+        .O(\rescnt[6]_i_5_n_0 ));
+  LUT3 #(
+    .INIT(8'hF9)) 
+    \rescnt[6]_i_6 
+       (.I0(rescnt_reg[3]),
+        .I1(rescnt_reg[4]),
+        .I2(rst_in_sync),
+        .O(\rescnt[6]_i_6_n_0 ));
+  FDRE #(
+    .INIT(1'b1)) 
+    \rescnt_reg[0] 
+       (.C(clk_in),
+        .CE(1'b1),
+        .D(rescnt[0]),
+        .Q(rescnt_reg[0]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b1)) 
+    \rescnt_reg[1] 
+       (.C(clk_in),
+        .CE(1'b1),
+        .D(rescnt[1]),
+        .Q(rescnt_reg[1]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b1)) 
+    \rescnt_reg[2] 
+       (.C(clk_in),
+        .CE(1'b1),
+        .D(rescnt[2]),
+        .Q(rescnt_reg[2]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b1)) 
+    \rescnt_reg[3] 
+       (.C(clk_in),
+        .CE(1'b1),
+        .D(rescnt[3]),
+        .Q(rescnt_reg[3]),
+        .R(1'b0));
+  (* ADDER_THRESHOLD = "35" *) 
+  CARRY4 \rescnt_reg[3]_i_1 
+       (.CI(1'b0),
+        .CO({\rescnt_reg[3]_i_1_n_0 ,\rescnt_reg[3]_i_1_n_1 ,\rescnt_reg[3]_i_1_n_2 ,\rescnt_reg[3]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({L[2],rst_sig,rst_sig_i_1_n_0,L[0]}),
+        .O(rescnt[3:0]),
+        .S({\rescnt[3]_i_5_n_0 ,\rescnt[3]_i_6_n_0 ,\rescnt[3]_i_7_n_0 ,\rescnt[3]_i_8_n_0 }));
+  FDRE #(
+    .INIT(1'b1)) 
+    \rescnt_reg[4] 
+       (.C(clk_in),
+        .CE(1'b1),
+        .D(rescnt[4]),
+        .Q(rescnt_reg[4]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b1)) 
+    \rescnt_reg[5] 
+       (.C(clk_in),
+        .CE(1'b1),
+        .D(rescnt[5]),
+        .Q(rescnt_reg[5]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b1)) 
+    \rescnt_reg[6] 
+       (.C(clk_in),
+        .CE(1'b1),
+        .D(rescnt[6]),
+        .Q(rescnt_reg[6]),
+        .R(1'b0));
+  (* ADDER_THRESHOLD = "35" *) 
+  CARRY4 \rescnt_reg[6]_i_1 
+       (.CI(\rescnt_reg[3]_i_1_n_0 ),
+        .CO({\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED [3:2],\rescnt_reg[6]_i_1_n_2 ,\rescnt_reg[6]_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,L[4:3]}),
+        .O({\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED [3],rescnt[6:4]}),
+        .S({1'b0,\rescnt[6]_i_4_n_0 ,\rescnt[6]_i_5_n_0 ,\rescnt[6]_i_6_n_0 }));
+  FDRE #(
+    .INIT(1'b0)) 
+    rst_in_sync_reg
+       (.C(clk_in),
+        .CE(1'b1),
+        .D(rst_in),
+        .Q(rst_in_sync),
+        .R(1'b0));
+  LUT1 #(
+    .INIT(2'h1)) 
+    rst_n_INST_0
+       (.I0(rst_sig_reg_n_0),
+        .O(rst_n));
+  LUT5 #(
+    .INIT(32'hFFFFFFFE)) 
+    rst_sig_i_1
+       (.I0(rst_sig_i_2_n_0),
+        .I1(rescnt_reg[5]),
+        .I2(rst_in_sync),
+        .I3(rescnt_reg[4]),
+        .I4(rescnt_reg[6]),
+        .O(rst_sig_i_1_n_0));
+  LUT5 #(
+    .INIT(32'hFFFFFFFE)) 
+    rst_sig_i_2
+       (.I0(rescnt_reg[2]),
+        .I1(rescnt_reg[3]),
+        .I2(rst_in_sync),
+        .I3(rescnt_reg[0]),
+        .I4(rescnt_reg[1]),
+        .O(rst_sig_i_2_n_0));
+  FDRE #(
+    .INIT(1'b0)) 
+    rst_sig_reg
+       (.C(clk_in),
+        .CE(1'b1),
+        .D(rst_sig_i_1_n_0),
+        .Q(rst_sig_reg_n_0),
+        .R(1'b0));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_stub.v

@@ -0,0 +1,27 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:25:44 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_stub.v
+// Design      : design_1_clk_rst_generator_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "clk_rst_generator,Vivado 2023.1" *)
+module design_1_clk_rst_generator_0_0(clk_in, rst_in, clk, rst_n, stop_simulation)
+/* synthesis syn_black_box black_box_pad_pin="rst_in,rst_n,stop_simulation" */
+/* synthesis syn_force_seq_prim="clk_in" */
+/* synthesis syn_force_seq_prim="clk" */;
+  input clk_in /* synthesis syn_isclock = 1 */;
+  input rst_in;
+  output clk /* synthesis syn_isclock = 1 */;
+  output rst_n;
+  input stop_simulation;
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/sim/design_1_clk_rst_generator_0_0.vhd

@@ -0,0 +1,99 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: wg:user:clk_rst_generator:1.0
+-- IP Revision: 7
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_clk_rst_generator_0_0 IS
+  PORT (
+    clk_in : IN STD_LOGIC;
+    rst_in : IN STD_LOGIC;
+    clk : OUT STD_LOGIC;
+    rst_n : OUT STD_LOGIC;
+    stop_simulation : IN STD_LOGIC
+  );
+END design_1_clk_rst_generator_0_0;
+
+ARCHITECTURE design_1_clk_rst_generator_0_0_arch OF design_1_clk_rst_generator_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT clk_rst_generator IS
+    GENERIC (
+      CLOCK_PERIOD : INTEGER;
+      HAS_CLK_INPUT : BOOLEAN;
+      HAS_RESET_INPUT : BOOLEAN;
+      HAS_STOP_INPUT : BOOLEAN
+    );
+    PORT (
+      clk_in : IN STD_LOGIC;
+      rst_in : IN STD_LOGIC;
+      clk : OUT STD_LOGIC;
+      rst_n : OUT STD_LOGIC;
+      stop_simulation : IN STD_LOGIC
+    );
+  END COMPONENT clk_rst_generator;
+BEGIN
+  U0 : clk_rst_generator
+    GENERIC MAP (
+      CLOCK_PERIOD => 10000,
+      HAS_CLK_INPUT => true,
+      HAS_RESET_INPUT => true,
+      HAS_STOP_INPUT => true
+    )
+    PORT MAP (
+      clk_in => clk_in,
+      rst_in => rst_in,
+      clk => clk,
+      rst_n => rst_n,
+      stop_simulation => stop_simulation
+    );
+END design_1_clk_rst_generator_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/synth/design_1_clk_rst_generator_0_0.vhd

@@ -0,0 +1,105 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: wg:user:clk_rst_generator:1.0
+-- IP Revision: 7
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_clk_rst_generator_0_0 IS
+  PORT (
+    clk_in : IN STD_LOGIC;
+    rst_in : IN STD_LOGIC;
+    clk : OUT STD_LOGIC;
+    rst_n : OUT STD_LOGIC;
+    stop_simulation : IN STD_LOGIC
+  );
+END design_1_clk_rst_generator_0_0;
+
+ARCHITECTURE design_1_clk_rst_generator_0_0_arch OF design_1_clk_rst_generator_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT clk_rst_generator IS
+    GENERIC (
+      CLOCK_PERIOD : INTEGER;
+      HAS_CLK_INPUT : BOOLEAN;
+      HAS_RESET_INPUT : BOOLEAN;
+      HAS_STOP_INPUT : BOOLEAN
+    );
+    PORT (
+      clk_in : IN STD_LOGIC;
+      rst_in : IN STD_LOGIC;
+      clk : OUT STD_LOGIC;
+      rst_n : OUT STD_LOGIC;
+      stop_simulation : IN STD_LOGIC
+    );
+  END COMPONENT clk_rst_generator;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "clk_rst_generator,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_clk_rst_generator_0_0_arch : ARCHITECTURE IS "design_1_clk_rst_generator_0_0,clk_rst_generator,{}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "package_project";
+BEGIN
+  U0 : clk_rst_generator
+    GENERIC MAP (
+      CLOCK_PERIOD => 10000,
+      HAS_CLK_INPUT => true,
+      HAS_RESET_INPUT => true,
+      HAS_STOP_INPUT => true
+    )
+    PORT MAP (
+      clk_in => clk_in,
+      rst_in => rst_in,
+      clk => clk,
+      rst_n => rst_n,
+      stop_simulation => stop_simulation
+    );
+END design_1_clk_rst_generator_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c_ooc.xdc

@@ -0,0 +1,11 @@
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# This constraints file contains default clock frequencies to be used during
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
+# This constraints file is not used in normal top-down synthesis (default flow
+# of Vivado)
+################################################################################
+create_clock -name clk -period 10 [get_ports clk]
+
+################################################################################

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hdl/bd_f60c_wrapper.vhd

@@ -0,0 +1,113 @@
+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Command: generate_target bd_f60c_wrapper.bd
+--Design : bd_f60c_wrapper
+--Purpose: IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity bd_f60c_wrapper is
+  port (
+    SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    SLOT_0_AXI_arready : in STD_LOGIC;
+    SLOT_0_AXI_arvalid : in STD_LOGIC;
+    SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    SLOT_0_AXI_awready : in STD_LOGIC;
+    SLOT_0_AXI_awvalid : in STD_LOGIC;
+    SLOT_0_AXI_bready : in STD_LOGIC;
+    SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    SLOT_0_AXI_bvalid : in STD_LOGIC;
+    SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_rready : in STD_LOGIC;
+    SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    SLOT_0_AXI_rvalid : in STD_LOGIC;
+    SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_wready : in STD_LOGIC;
+    SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    SLOT_0_AXI_wvalid : in STD_LOGIC;
+    SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    SLOT_1_AXIS_tlast : in STD_LOGIC;
+    SLOT_1_AXIS_tready : in STD_LOGIC;
+    SLOT_1_AXIS_tvalid : in STD_LOGIC;
+    SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    SLOT_2_AXIS_tlast : in STD_LOGIC;
+    SLOT_2_AXIS_tready : in STD_LOGIC;
+    SLOT_2_AXIS_tvalid : in STD_LOGIC;
+    clk : in STD_LOGIC;
+    resetn : in STD_LOGIC
+  );
+end bd_f60c_wrapper;
+
+architecture STRUCTURE of bd_f60c_wrapper is
+  component bd_f60c is
+  port (
+    clk : in STD_LOGIC;
+    resetn : in STD_LOGIC;
+    SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    SLOT_0_AXI_awvalid : in STD_LOGIC;
+    SLOT_0_AXI_awready : in STD_LOGIC;
+    SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    SLOT_0_AXI_wvalid : in STD_LOGIC;
+    SLOT_0_AXI_wready : in STD_LOGIC;
+    SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    SLOT_0_AXI_bvalid : in STD_LOGIC;
+    SLOT_0_AXI_bready : in STD_LOGIC;
+    SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    SLOT_0_AXI_arvalid : in STD_LOGIC;
+    SLOT_0_AXI_arready : in STD_LOGIC;
+    SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    SLOT_0_AXI_rvalid : in STD_LOGIC;
+    SLOT_0_AXI_rready : in STD_LOGIC;
+    SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    SLOT_1_AXIS_tlast : in STD_LOGIC;
+    SLOT_1_AXIS_tvalid : in STD_LOGIC;
+    SLOT_1_AXIS_tready : in STD_LOGIC;
+    SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    SLOT_2_AXIS_tlast : in STD_LOGIC;
+    SLOT_2_AXIS_tvalid : in STD_LOGIC;
+    SLOT_2_AXIS_tready : in STD_LOGIC
+  );
+  end component bd_f60c;
+begin
+bd_f60c_i: component bd_f60c
+     port map (
+      SLOT_0_AXI_araddr(31 downto 0) => SLOT_0_AXI_araddr(31 downto 0),
+      SLOT_0_AXI_arprot(2 downto 0) => SLOT_0_AXI_arprot(2 downto 0),
+      SLOT_0_AXI_arready => SLOT_0_AXI_arready,
+      SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
+      SLOT_0_AXI_awaddr(31 downto 0) => SLOT_0_AXI_awaddr(31 downto 0),
+      SLOT_0_AXI_awprot(2 downto 0) => SLOT_0_AXI_awprot(2 downto 0),
+      SLOT_0_AXI_awready => SLOT_0_AXI_awready,
+      SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
+      SLOT_0_AXI_bready => SLOT_0_AXI_bready,
+      SLOT_0_AXI_bresp(1 downto 0) => SLOT_0_AXI_bresp(1 downto 0),
+      SLOT_0_AXI_bvalid => SLOT_0_AXI_bvalid,
+      SLOT_0_AXI_rdata(31 downto 0) => SLOT_0_AXI_rdata(31 downto 0),
+      SLOT_0_AXI_rready => SLOT_0_AXI_rready,
+      SLOT_0_AXI_rresp(1 downto 0) => SLOT_0_AXI_rresp(1 downto 0),
+      SLOT_0_AXI_rvalid => SLOT_0_AXI_rvalid,
+      SLOT_0_AXI_wdata(31 downto 0) => SLOT_0_AXI_wdata(31 downto 0),
+      SLOT_0_AXI_wready => SLOT_0_AXI_wready,
+      SLOT_0_AXI_wstrb(3 downto 0) => SLOT_0_AXI_wstrb(3 downto 0),
+      SLOT_0_AXI_wvalid => SLOT_0_AXI_wvalid,
+      SLOT_1_AXIS_tdata(15 downto 0) => SLOT_1_AXIS_tdata(15 downto 0),
+      SLOT_1_AXIS_tlast => SLOT_1_AXIS_tlast,
+      SLOT_1_AXIS_tready => SLOT_1_AXIS_tready,
+      SLOT_1_AXIS_tvalid => SLOT_1_AXIS_tvalid,
+      SLOT_2_AXIS_tdata(15 downto 0) => SLOT_2_AXIS_tdata(15 downto 0),
+      SLOT_2_AXIS_tlast => SLOT_2_AXIS_tlast,
+      SLOT_2_AXIS_tready => SLOT_2_AXIS_tready,
+      SLOT_2_AXIS_tvalid => SLOT_2_AXIS_tvalid,
+      clk => clk,
+      resetn => resetn
+    );
+end STRUCTURE;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0_ooc.xdc

@@ -0,0 +1,69 @@
+
+
+################################################################################
+# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# User should update the correct clock period before proceeding further
+# This constraints file contains default clock frequencies to be used during 
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs. 
+# For best results the frequencies should be modified# to match the target 
+# frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+################################################################################
+#create_clock -name clock_name -period 10 [get_ports clock_name] 
+################################################################################
+
+#list of all the clock needed for ILA core
+
+
+        
+	create_clock -name ILA_CLK -period 10 [get_ports clk]
+
+################################################################################

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc

@@ -0,0 +1,103 @@
+##
+## ARM and HALT transfer false paths
+##
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/din_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/dout_reg0_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
+
+##
+## ILA Register False Paths
+##
+#set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_*/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/itrigger_out_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/use_probe_debug_circuit_2_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/capture_qual_ctrl_2_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/debug_data_in_sync1_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*.cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/cfg_data_vec_sync1_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
+#set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_ila_reg*" && IS_SEQUENTIAL} ]
+#set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL} ]
+#set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL} ]
+#set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_reg*" && IS_SEQUENTIAL} ]
+#set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_xsdb_reg*" && IS_SEQUENTIAL} ]
+#set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL} ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
+
+##
+## Match Unit Configuration to Match Output false path
+##
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*" && IS_SEQUENTIAL}]]
+#set_false_path -from [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK}] -to [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D}]
+
+##
+## ILA Capture Block False Paths
+##
+
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*icap_addr_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/captured_samples*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/CAP_DONE_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/CAP_TRIGGER_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
+
+##
+## ILA Capture State to XSDB register False Paths
+##
+set_false_path -from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/U_NS*/I_YESLUT6.I_YES_OREG.O_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_*/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]*" && IS_SEQUENTIAL } ]
+
+##
+## ILA Sample Counter Match Condition out False Paths
+##
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
+#set_false_path -from [get_pins -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
+
+##
+## ILA Window Counter Match Condition out False Paths
+##
+#set_false_path -from [get_pins -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
+#set_false_path -from [get_pins -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL }]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }] 
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL }]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
+
+
+
+
+##
+## Waivers 
+##
+#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]]
+#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_xsdb_reg*"} ]]
+#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_reg*"} ]]
+#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_ila_reg*"} ]]
+#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]]
+#create_waiver -internal -scope -type CDC -id CDC-15 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]]  -to [get_pins -filter {REF_PIN_NAME=~R} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*"} ]]
+

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc

@@ -0,0 +1,30 @@
+##
+## Match Unit Configuration to Match Output false path
+##
+
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]]
+
+##
+## ILA Sample Counter Match Condition out False Paths
+##
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
+
+##
+## ILA Window Counter Match Condition out False Paths
+##
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
+set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
+
+
+create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*"}]]  -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]]  -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process} 
+create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*"}]]  -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]]  -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process} 
+create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*"}]]  -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]]  -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process} 
+create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*"}]]  -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process} 
+create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]]  -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process} 
+create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]]  -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*"}]]  -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
+create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]]  -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*"}]]  -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
+create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]]  -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*"}]]  -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
+create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]]  -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]]  -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
+#create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srlD/S1*"}]]  -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]]  -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
+create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]]  -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*"}]]  -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
+

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/sim/bd_f60c_ila_lib_0.vhd

@@ -0,0 +1,89 @@
+-- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
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+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY bd_f60c_ila_lib_0 IS
+PORT (
+clk : IN STD_LOGIC;
+
+
+probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    probe3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe5 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    probe6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe12 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    probe13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
+);
+END bd_f60c_ila_lib_0;
+
+ARCHITECTURE bd_f60c_ila_lib_0_arch OF bd_f60c_ila_lib_0 IS
+BEGIN
+END bd_f60c_ila_lib_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/sim/bd_f60c_slot_0_aw_0.v

@@ -0,0 +1,328 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_aw_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/synth/bd_f60c_slot_0_aw_0.v

@@ -0,0 +1,332 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
+(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_aw_0,xlconcat_v2_1_4_xlconcat,{}" *)
+(* CORE_GENERATION_INFO = "bd_f60c_slot_0_aw_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDT\
+H=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN\
+62_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WI\
+DTH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_aw_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/sim/bd_f60c_slot_0_w_0.v

@@ -0,0 +1,328 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_w_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/synth/bd_f60c_slot_0_w_0.v

@@ -0,0 +1,332 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
+(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_w_0,xlconcat_v2_1_4_xlconcat,{}" *)
+(* CORE_GENERATION_INFO = "bd_f60c_slot_0_w_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH\
+=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN6\
+2_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WID\
+TH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_w_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/sim/bd_f60c_slot_0_b_0.v

@@ -0,0 +1,328 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_b_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/synth/bd_f60c_slot_0_b_0.v

@@ -0,0 +1,332 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
+(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_b_0,xlconcat_v2_1_4_xlconcat,{}" *)
+(* CORE_GENERATION_INFO = "bd_f60c_slot_0_b_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH\
+=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN6\
+2_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WID\
+TH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_b_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/sim/bd_f60c_slot_0_ar_0.v

@@ -0,0 +1,328 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_ar_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/synth/bd_f60c_slot_0_ar_0.v

@@ -0,0 +1,332 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
+(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_ar_0,xlconcat_v2_1_4_xlconcat,{}" *)
+(* CORE_GENERATION_INFO = "bd_f60c_slot_0_ar_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDT\
+H=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN\
+62_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WI\
+DTH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_ar_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/sim/bd_f60c_slot_0_r_0.v

@@ -0,0 +1,328 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_r_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/synth/bd_f60c_slot_0_r_0.v

@@ -0,0 +1,332 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
+(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_r_0,xlconcat_v2_1_4_xlconcat,{}" *)
+(* CORE_GENERATION_INFO = "bd_f60c_slot_0_r_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH\
+=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN6\
+2_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WID\
+TH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module bd_f60c_slot_0_r_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/sim/bd_f60c.vhd

@@ -0,0 +1,435 @@
+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Command: generate_target bd_f60c.bd
+--Design : bd_f60c
+--Purpose: IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity bd_f60c is
+  port (
+    SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    SLOT_0_AXI_arready : in STD_LOGIC;
+    SLOT_0_AXI_arvalid : in STD_LOGIC;
+    SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    SLOT_0_AXI_awready : in STD_LOGIC;
+    SLOT_0_AXI_awvalid : in STD_LOGIC;
+    SLOT_0_AXI_bready : in STD_LOGIC;
+    SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    SLOT_0_AXI_bvalid : in STD_LOGIC;
+    SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_rready : in STD_LOGIC;
+    SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    SLOT_0_AXI_rvalid : in STD_LOGIC;
+    SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_wready : in STD_LOGIC;
+    SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    SLOT_0_AXI_wvalid : in STD_LOGIC;
+    SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    SLOT_1_AXIS_tlast : in STD_LOGIC;
+    SLOT_1_AXIS_tready : in STD_LOGIC;
+    SLOT_1_AXIS_tvalid : in STD_LOGIC;
+    SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    SLOT_2_AXIS_tlast : in STD_LOGIC;
+    SLOT_2_AXIS_tready : in STD_LOGIC;
+    SLOT_2_AXIS_tvalid : in STD_LOGIC;
+    clk : in STD_LOGIC;
+    resetn : in STD_LOGIC
+  );
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of bd_f60c : entity is "design_1_system_ila_0_0.hwdef";
+end bd_f60c;
+
+architecture STRUCTURE of bd_f60c is
+  component bd_f60c_ila_lib_0 is
+  port (
+    clk : in STD_LOGIC;
+    probe0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe2 : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    probe3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe5 : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe12 : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    probe13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe18 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe22 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe25 : in STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component bd_f60c_ila_lib_0;
+  component bd_f60c_g_inst_0 is
+  port (
+    aclk : in STD_LOGIC;
+    aresetn : in STD_LOGIC;
+    m_slot_0_axi_b_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_r_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_aw_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_ar_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    slot_0_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    slot_0_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    slot_0_axi_awvalid : in STD_LOGIC;
+    slot_0_axi_awready : in STD_LOGIC;
+    slot_0_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    slot_0_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    slot_0_axi_wvalid : in STD_LOGIC;
+    slot_0_axi_wready : in STD_LOGIC;
+    slot_0_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    slot_0_axi_bvalid : in STD_LOGIC;
+    slot_0_axi_bready : in STD_LOGIC;
+    slot_0_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    slot_0_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    slot_0_axi_arvalid : in STD_LOGIC;
+    slot_0_axi_arready : in STD_LOGIC;
+    slot_0_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    slot_0_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    slot_0_axi_rvalid : in STD_LOGIC;
+    slot_0_axi_rready : in STD_LOGIC;
+    slot_1_axis_tvalid : in STD_LOGIC;
+    slot_1_axis_tready : in STD_LOGIC;
+    slot_1_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    slot_1_axis_tlast : in STD_LOGIC;
+    slot_2_axis_tvalid : in STD_LOGIC;
+    slot_2_axis_tready : in STD_LOGIC;
+    slot_2_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    slot_2_axis_tlast : in STD_LOGIC;
+    m_slot_0_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_slot_0_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    m_slot_0_axi_awvalid : out STD_LOGIC;
+    m_slot_0_axi_awready : out STD_LOGIC;
+    m_slot_0_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_slot_0_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    m_slot_0_axi_wvalid : out STD_LOGIC;
+    m_slot_0_axi_wready : out STD_LOGIC;
+    m_slot_0_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_bvalid : out STD_LOGIC;
+    m_slot_0_axi_bready : out STD_LOGIC;
+    m_slot_0_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_slot_0_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    m_slot_0_axi_arvalid : out STD_LOGIC;
+    m_slot_0_axi_arready : out STD_LOGIC;
+    m_slot_0_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_slot_0_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_rvalid : out STD_LOGIC;
+    m_slot_0_axi_rready : out STD_LOGIC;
+    m_slot_1_axis_tvalid : out STD_LOGIC;
+    m_slot_1_axis_tready : out STD_LOGIC;
+    m_slot_1_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
+    m_slot_1_axis_tlast : out STD_LOGIC;
+    m_slot_2_axis_tvalid : out STD_LOGIC;
+    m_slot_2_axis_tready : out STD_LOGIC;
+    m_slot_2_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
+    m_slot_2_axis_tlast : out STD_LOGIC
+  );
+  end component bd_f60c_g_inst_0;
+  component bd_f60c_slot_0_aw_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_aw_0;
+  component bd_f60c_slot_0_w_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_w_0;
+  component bd_f60c_slot_0_b_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_b_0;
+  component bd_f60c_slot_0_ar_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_ar_0;
+  component bd_f60c_slot_0_r_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_r_0;
+  signal Conn1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
+  signal Conn1_TLAST : STD_LOGIC;
+  signal Conn1_TREADY : STD_LOGIC;
+  signal Conn1_TVALID : STD_LOGIC;
+  signal Conn2_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
+  signal Conn2_TLAST : STD_LOGIC;
+  signal Conn2_TREADY : STD_LOGIC;
+  signal Conn2_TVALID : STD_LOGIC;
+  signal Conn_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal Conn_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal Conn_ARREADY : STD_LOGIC;
+  signal Conn_ARVALID : STD_LOGIC;
+  signal Conn_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal Conn_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal Conn_AWREADY : STD_LOGIC;
+  signal Conn_AWVALID : STD_LOGIC;
+  signal Conn_BREADY : STD_LOGIC;
+  signal Conn_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal Conn_BVALID : STD_LOGIC;
+  signal Conn_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal Conn_RREADY : STD_LOGIC;
+  signal Conn_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal Conn_RVALID : STD_LOGIC;
+  signal Conn_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal Conn_WREADY : STD_LOGIC;
+  signal Conn_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal Conn_WVALID : STD_LOGIC;
+  signal clk_1 : STD_LOGIC;
+  signal net_slot_0_axi_ar_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_ar_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal net_slot_0_axi_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal net_slot_0_axi_arready : STD_LOGIC;
+  signal net_slot_0_axi_arvalid : STD_LOGIC;
+  signal net_slot_0_axi_aw_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_aw_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal net_slot_0_axi_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal net_slot_0_axi_awready : STD_LOGIC;
+  signal net_slot_0_axi_awvalid : STD_LOGIC;
+  signal net_slot_0_axi_b_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_b_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_bready : STD_LOGIC;
+  signal net_slot_0_axi_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_bvalid : STD_LOGIC;
+  signal net_slot_0_axi_r_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_r_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal net_slot_0_axi_rready : STD_LOGIC;
+  signal net_slot_0_axi_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_rvalid : STD_LOGIC;
+  signal net_slot_0_axi_w_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal net_slot_0_axi_wready : STD_LOGIC;
+  signal net_slot_0_axi_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal net_slot_0_axi_wvalid : STD_LOGIC;
+  signal net_slot_1_axis_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
+  signal net_slot_1_axis_tlast : STD_LOGIC;
+  signal net_slot_1_axis_tready : STD_LOGIC;
+  signal net_slot_1_axis_tvalid : STD_LOGIC;
+  signal net_slot_2_axis_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
+  signal net_slot_2_axis_tlast : STD_LOGIC;
+  signal net_slot_2_axis_tready : STD_LOGIC;
+  signal net_slot_2_axis_tvalid : STD_LOGIC;
+  signal resetn_1 : STD_LOGIC;
+  attribute X_INTERFACE_INFO : string;
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID";
+  attribute X_INTERFACE_INFO of SLOT_1_AXIS_tlast : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST";
+  attribute X_INTERFACE_INFO of SLOT_1_AXIS_tready : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY";
+  attribute X_INTERFACE_INFO of SLOT_1_AXIS_tvalid : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID";
+  attribute X_INTERFACE_INFO of SLOT_2_AXIS_tlast : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TLAST";
+  attribute X_INTERFACE_INFO of SLOT_2_AXIS_tready : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TREADY";
+  attribute X_INTERFACE_INFO of SLOT_2_AXIS_tvalid : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TVALID";
+  attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
+  attribute X_INTERFACE_PARAMETER : string;
+  attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
+  attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST";
+  attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
+  attribute X_INTERFACE_PARAMETER of SLOT_0_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_0_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN bd_f60c_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
+  attribute X_INTERFACE_INFO of SLOT_1_AXIS_tdata : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA";
+  attribute X_INTERFACE_PARAMETER of SLOT_1_AXIS_tdata : signal is "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
+  attribute X_INTERFACE_INFO of SLOT_2_AXIS_tdata : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TDATA";
+  attribute X_INTERFACE_PARAMETER of SLOT_2_AXIS_tdata : signal is "XIL_INTERFACENAME SLOT_2_AXIS, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
+begin
+  Conn1_TDATA(15 downto 0) <= SLOT_1_AXIS_tdata(15 downto 0);
+  Conn1_TLAST <= SLOT_1_AXIS_tlast;
+  Conn1_TREADY <= SLOT_1_AXIS_tready;
+  Conn1_TVALID <= SLOT_1_AXIS_tvalid;
+  Conn2_TDATA(15 downto 0) <= SLOT_2_AXIS_tdata(15 downto 0);
+  Conn2_TLAST <= SLOT_2_AXIS_tlast;
+  Conn2_TREADY <= SLOT_2_AXIS_tready;
+  Conn2_TVALID <= SLOT_2_AXIS_tvalid;
+  Conn_ARADDR(31 downto 0) <= SLOT_0_AXI_araddr(31 downto 0);
+  Conn_ARPROT(2 downto 0) <= SLOT_0_AXI_arprot(2 downto 0);
+  Conn_ARREADY <= SLOT_0_AXI_arready;
+  Conn_ARVALID <= SLOT_0_AXI_arvalid;
+  Conn_AWADDR(31 downto 0) <= SLOT_0_AXI_awaddr(31 downto 0);
+  Conn_AWPROT(2 downto 0) <= SLOT_0_AXI_awprot(2 downto 0);
+  Conn_AWREADY <= SLOT_0_AXI_awready;
+  Conn_AWVALID <= SLOT_0_AXI_awvalid;
+  Conn_BREADY <= SLOT_0_AXI_bready;
+  Conn_BRESP(1 downto 0) <= SLOT_0_AXI_bresp(1 downto 0);
+  Conn_BVALID <= SLOT_0_AXI_bvalid;
+  Conn_RDATA(31 downto 0) <= SLOT_0_AXI_rdata(31 downto 0);
+  Conn_RREADY <= SLOT_0_AXI_rready;
+  Conn_RRESP(1 downto 0) <= SLOT_0_AXI_rresp(1 downto 0);
+  Conn_RVALID <= SLOT_0_AXI_rvalid;
+  Conn_WDATA(31 downto 0) <= SLOT_0_AXI_wdata(31 downto 0);
+  Conn_WREADY <= SLOT_0_AXI_wready;
+  Conn_WSTRB(3 downto 0) <= SLOT_0_AXI_wstrb(3 downto 0);
+  Conn_WVALID <= SLOT_0_AXI_wvalid;
+  clk_1 <= clk;
+  resetn_1 <= resetn;
+g_inst: component bd_f60c_g_inst_0
+     port map (
+      aclk => clk_1,
+      aresetn => resetn_1,
+      m_slot_0_axi_ar_cnt(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
+      m_slot_0_axi_araddr(31 downto 0) => net_slot_0_axi_araddr(31 downto 0),
+      m_slot_0_axi_arprot(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
+      m_slot_0_axi_arready => net_slot_0_axi_arready,
+      m_slot_0_axi_arvalid => net_slot_0_axi_arvalid,
+      m_slot_0_axi_aw_cnt(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
+      m_slot_0_axi_awaddr(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
+      m_slot_0_axi_awprot(2 downto 0) => net_slot_0_axi_awprot(2 downto 0),
+      m_slot_0_axi_awready => net_slot_0_axi_awready,
+      m_slot_0_axi_awvalid => net_slot_0_axi_awvalid,
+      m_slot_0_axi_b_cnt(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
+      m_slot_0_axi_bready => net_slot_0_axi_bready,
+      m_slot_0_axi_bresp(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
+      m_slot_0_axi_bvalid => net_slot_0_axi_bvalid,
+      m_slot_0_axi_r_cnt(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
+      m_slot_0_axi_rdata(31 downto 0) => net_slot_0_axi_rdata(31 downto 0),
+      m_slot_0_axi_rready => net_slot_0_axi_rready,
+      m_slot_0_axi_rresp(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
+      m_slot_0_axi_rvalid => net_slot_0_axi_rvalid,
+      m_slot_0_axi_wdata(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
+      m_slot_0_axi_wready => net_slot_0_axi_wready,
+      m_slot_0_axi_wstrb(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
+      m_slot_0_axi_wvalid => net_slot_0_axi_wvalid,
+      m_slot_1_axis_tdata(15 downto 0) => net_slot_1_axis_tdata(15 downto 0),
+      m_slot_1_axis_tlast => net_slot_1_axis_tlast,
+      m_slot_1_axis_tready => net_slot_1_axis_tready,
+      m_slot_1_axis_tvalid => net_slot_1_axis_tvalid,
+      m_slot_2_axis_tdata(15 downto 0) => net_slot_2_axis_tdata(15 downto 0),
+      m_slot_2_axis_tlast => net_slot_2_axis_tlast,
+      m_slot_2_axis_tready => net_slot_2_axis_tready,
+      m_slot_2_axis_tvalid => net_slot_2_axis_tvalid,
+      slot_0_axi_araddr(31 downto 0) => Conn_ARADDR(31 downto 0),
+      slot_0_axi_arprot(2 downto 0) => Conn_ARPROT(2 downto 0),
+      slot_0_axi_arready => Conn_ARREADY,
+      slot_0_axi_arvalid => Conn_ARVALID,
+      slot_0_axi_awaddr(31 downto 0) => Conn_AWADDR(31 downto 0),
+      slot_0_axi_awprot(2 downto 0) => Conn_AWPROT(2 downto 0),
+      slot_0_axi_awready => Conn_AWREADY,
+      slot_0_axi_awvalid => Conn_AWVALID,
+      slot_0_axi_bready => Conn_BREADY,
+      slot_0_axi_bresp(1 downto 0) => Conn_BRESP(1 downto 0),
+      slot_0_axi_bvalid => Conn_BVALID,
+      slot_0_axi_rdata(31 downto 0) => Conn_RDATA(31 downto 0),
+      slot_0_axi_rready => Conn_RREADY,
+      slot_0_axi_rresp(1 downto 0) => Conn_RRESP(1 downto 0),
+      slot_0_axi_rvalid => Conn_RVALID,
+      slot_0_axi_wdata(31 downto 0) => Conn_WDATA(31 downto 0),
+      slot_0_axi_wready => Conn_WREADY,
+      slot_0_axi_wstrb(3 downto 0) => Conn_WSTRB(3 downto 0),
+      slot_0_axi_wvalid => Conn_WVALID,
+      slot_1_axis_tdata(15 downto 0) => Conn1_TDATA(15 downto 0),
+      slot_1_axis_tlast => Conn1_TLAST,
+      slot_1_axis_tready => Conn1_TREADY,
+      slot_1_axis_tvalid => Conn1_TVALID,
+      slot_2_axis_tdata(15 downto 0) => Conn2_TDATA(15 downto 0),
+      slot_2_axis_tlast => Conn2_TLAST,
+      slot_2_axis_tready => Conn2_TREADY,
+      slot_2_axis_tvalid => Conn2_TVALID
+    );
+ila_lib: component bd_f60c_ila_lib_0
+     port map (
+      clk => clk_1,
+      probe0(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
+      probe1(31 downto 0) => net_slot_0_axi_araddr(31 downto 0),
+      probe10(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
+      probe11(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
+      probe12(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
+      probe13(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0),
+      probe14(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0),
+      probe15(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0),
+      probe16(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
+      probe17(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0),
+      probe18(15 downto 0) => net_slot_1_axis_tdata(15 downto 0),
+      probe19(0) => net_slot_1_axis_tvalid,
+      probe2(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
+      probe20(0) => net_slot_1_axis_tready,
+      probe21(0) => net_slot_1_axis_tlast,
+      probe22(15 downto 0) => net_slot_2_axis_tdata(15 downto 0),
+      probe23(0) => net_slot_2_axis_tvalid,
+      probe24(0) => net_slot_2_axis_tready,
+      probe25(0) => net_slot_2_axis_tlast,
+      probe3(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
+      probe4(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
+      probe5(2 downto 0) => net_slot_0_axi_awprot(2 downto 0),
+      probe6(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
+      probe7(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
+      probe8(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
+      probe9(31 downto 0) => net_slot_0_axi_rdata(31 downto 0)
+    );
+slot_0_ar: component bd_f60c_slot_0_ar_0
+     port map (
+      In0(0) => net_slot_0_axi_arvalid,
+      In1(0) => net_slot_0_axi_arready,
+      dout(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0)
+    );
+slot_0_aw: component bd_f60c_slot_0_aw_0
+     port map (
+      In0(0) => net_slot_0_axi_awvalid,
+      In1(0) => net_slot_0_axi_awready,
+      dout(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0)
+    );
+slot_0_b: component bd_f60c_slot_0_b_0
+     port map (
+      In0(0) => net_slot_0_axi_bvalid,
+      In1(0) => net_slot_0_axi_bready,
+      dout(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0)
+    );
+slot_0_r: component bd_f60c_slot_0_r_0
+     port map (
+      In0(0) => net_slot_0_axi_rvalid,
+      In1(0) => net_slot_0_axi_rready,
+      dout(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0)
+    );
+slot_0_w: component bd_f60c_slot_0_w_0
+     port map (
+      In0(0) => net_slot_0_axi_wvalid,
+      In1(0) => net_slot_0_axi_wready,
+      dout(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0)
+    );
+end STRUCTURE;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/bd_f60c.vhd

@@ -0,0 +1,435 @@
+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Command: generate_target bd_f60c.bd
+--Design : bd_f60c
+--Purpose: IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity bd_f60c is
+  port (
+    SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    SLOT_0_AXI_arready : in STD_LOGIC;
+    SLOT_0_AXI_arvalid : in STD_LOGIC;
+    SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    SLOT_0_AXI_awready : in STD_LOGIC;
+    SLOT_0_AXI_awvalid : in STD_LOGIC;
+    SLOT_0_AXI_bready : in STD_LOGIC;
+    SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    SLOT_0_AXI_bvalid : in STD_LOGIC;
+    SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_rready : in STD_LOGIC;
+    SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    SLOT_0_AXI_rvalid : in STD_LOGIC;
+    SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    SLOT_0_AXI_wready : in STD_LOGIC;
+    SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    SLOT_0_AXI_wvalid : in STD_LOGIC;
+    SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    SLOT_1_AXIS_tlast : in STD_LOGIC;
+    SLOT_1_AXIS_tready : in STD_LOGIC;
+    SLOT_1_AXIS_tvalid : in STD_LOGIC;
+    SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    SLOT_2_AXIS_tlast : in STD_LOGIC;
+    SLOT_2_AXIS_tready : in STD_LOGIC;
+    SLOT_2_AXIS_tvalid : in STD_LOGIC;
+    clk : in STD_LOGIC;
+    resetn : in STD_LOGIC
+  );
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of bd_f60c : entity is "design_1_system_ila_0_0.hwdef";
+end bd_f60c;
+
+architecture STRUCTURE of bd_f60c is
+  component bd_f60c_ila_lib_0 is
+  port (
+    clk : in STD_LOGIC;
+    probe0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe2 : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    probe3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe5 : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe12 : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    probe13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe18 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe22 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe25 : in STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component bd_f60c_ila_lib_0;
+  component bd_f60c_g_inst_0 is
+  port (
+    aclk : in STD_LOGIC;
+    aresetn : in STD_LOGIC;
+    m_slot_0_axi_b_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_r_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_aw_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_ar_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    slot_0_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    slot_0_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    slot_0_axi_awvalid : in STD_LOGIC;
+    slot_0_axi_awready : in STD_LOGIC;
+    slot_0_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    slot_0_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    slot_0_axi_wvalid : in STD_LOGIC;
+    slot_0_axi_wready : in STD_LOGIC;
+    slot_0_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    slot_0_axi_bvalid : in STD_LOGIC;
+    slot_0_axi_bready : in STD_LOGIC;
+    slot_0_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    slot_0_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    slot_0_axi_arvalid : in STD_LOGIC;
+    slot_0_axi_arready : in STD_LOGIC;
+    slot_0_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    slot_0_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    slot_0_axi_rvalid : in STD_LOGIC;
+    slot_0_axi_rready : in STD_LOGIC;
+    slot_1_axis_tvalid : in STD_LOGIC;
+    slot_1_axis_tready : in STD_LOGIC;
+    slot_1_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    slot_1_axis_tlast : in STD_LOGIC;
+    slot_2_axis_tvalid : in STD_LOGIC;
+    slot_2_axis_tready : in STD_LOGIC;
+    slot_2_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    slot_2_axis_tlast : in STD_LOGIC;
+    m_slot_0_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_slot_0_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    m_slot_0_axi_awvalid : out STD_LOGIC;
+    m_slot_0_axi_awready : out STD_LOGIC;
+    m_slot_0_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_slot_0_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    m_slot_0_axi_wvalid : out STD_LOGIC;
+    m_slot_0_axi_wready : out STD_LOGIC;
+    m_slot_0_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_bvalid : out STD_LOGIC;
+    m_slot_0_axi_bready : out STD_LOGIC;
+    m_slot_0_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_slot_0_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    m_slot_0_axi_arvalid : out STD_LOGIC;
+    m_slot_0_axi_arready : out STD_LOGIC;
+    m_slot_0_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_slot_0_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    m_slot_0_axi_rvalid : out STD_LOGIC;
+    m_slot_0_axi_rready : out STD_LOGIC;
+    m_slot_1_axis_tvalid : out STD_LOGIC;
+    m_slot_1_axis_tready : out STD_LOGIC;
+    m_slot_1_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
+    m_slot_1_axis_tlast : out STD_LOGIC;
+    m_slot_2_axis_tvalid : out STD_LOGIC;
+    m_slot_2_axis_tready : out STD_LOGIC;
+    m_slot_2_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
+    m_slot_2_axis_tlast : out STD_LOGIC
+  );
+  end component bd_f60c_g_inst_0;
+  component bd_f60c_slot_0_aw_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_aw_0;
+  component bd_f60c_slot_0_w_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_w_0;
+  component bd_f60c_slot_0_b_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_b_0;
+  component bd_f60c_slot_0_ar_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_ar_0;
+  component bd_f60c_slot_0_r_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component bd_f60c_slot_0_r_0;
+  signal Conn1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
+  signal Conn1_TLAST : STD_LOGIC;
+  signal Conn1_TREADY : STD_LOGIC;
+  signal Conn1_TVALID : STD_LOGIC;
+  signal Conn2_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
+  signal Conn2_TLAST : STD_LOGIC;
+  signal Conn2_TREADY : STD_LOGIC;
+  signal Conn2_TVALID : STD_LOGIC;
+  signal Conn_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal Conn_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal Conn_ARREADY : STD_LOGIC;
+  signal Conn_ARVALID : STD_LOGIC;
+  signal Conn_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal Conn_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal Conn_AWREADY : STD_LOGIC;
+  signal Conn_AWVALID : STD_LOGIC;
+  signal Conn_BREADY : STD_LOGIC;
+  signal Conn_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal Conn_BVALID : STD_LOGIC;
+  signal Conn_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal Conn_RREADY : STD_LOGIC;
+  signal Conn_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal Conn_RVALID : STD_LOGIC;
+  signal Conn_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal Conn_WREADY : STD_LOGIC;
+  signal Conn_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal Conn_WVALID : STD_LOGIC;
+  signal clk_1 : STD_LOGIC;
+  signal net_slot_0_axi_ar_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_ar_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal net_slot_0_axi_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal net_slot_0_axi_arready : STD_LOGIC;
+  signal net_slot_0_axi_arvalid : STD_LOGIC;
+  signal net_slot_0_axi_aw_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_aw_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal net_slot_0_axi_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal net_slot_0_axi_awready : STD_LOGIC;
+  signal net_slot_0_axi_awvalid : STD_LOGIC;
+  signal net_slot_0_axi_b_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_b_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_bready : STD_LOGIC;
+  signal net_slot_0_axi_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_bvalid : STD_LOGIC;
+  signal net_slot_0_axi_r_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_r_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal net_slot_0_axi_rready : STD_LOGIC;
+  signal net_slot_0_axi_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_rvalid : STD_LOGIC;
+  signal net_slot_0_axi_w_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal net_slot_0_axi_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal net_slot_0_axi_wready : STD_LOGIC;
+  signal net_slot_0_axi_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal net_slot_0_axi_wvalid : STD_LOGIC;
+  signal net_slot_1_axis_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
+  signal net_slot_1_axis_tlast : STD_LOGIC;
+  signal net_slot_1_axis_tready : STD_LOGIC;
+  signal net_slot_1_axis_tvalid : STD_LOGIC;
+  signal net_slot_2_axis_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
+  signal net_slot_2_axis_tlast : STD_LOGIC;
+  signal net_slot_2_axis_tready : STD_LOGIC;
+  signal net_slot_2_axis_tvalid : STD_LOGIC;
+  signal resetn_1 : STD_LOGIC;
+  attribute X_INTERFACE_INFO : string;
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID";
+  attribute X_INTERFACE_INFO of SLOT_1_AXIS_tlast : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST";
+  attribute X_INTERFACE_INFO of SLOT_1_AXIS_tready : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY";
+  attribute X_INTERFACE_INFO of SLOT_1_AXIS_tvalid : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID";
+  attribute X_INTERFACE_INFO of SLOT_2_AXIS_tlast : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TLAST";
+  attribute X_INTERFACE_INFO of SLOT_2_AXIS_tready : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TREADY";
+  attribute X_INTERFACE_INFO of SLOT_2_AXIS_tvalid : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TVALID";
+  attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
+  attribute X_INTERFACE_PARAMETER : string;
+  attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
+  attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST";
+  attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
+  attribute X_INTERFACE_PARAMETER of SLOT_0_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_0_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN bd_f60c_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
+  attribute X_INTERFACE_INFO of SLOT_0_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
+  attribute X_INTERFACE_INFO of SLOT_1_AXIS_tdata : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA";
+  attribute X_INTERFACE_PARAMETER of SLOT_1_AXIS_tdata : signal is "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
+  attribute X_INTERFACE_INFO of SLOT_2_AXIS_tdata : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TDATA";
+  attribute X_INTERFACE_PARAMETER of SLOT_2_AXIS_tdata : signal is "XIL_INTERFACENAME SLOT_2_AXIS, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
+begin
+  Conn1_TDATA(15 downto 0) <= SLOT_1_AXIS_tdata(15 downto 0);
+  Conn1_TLAST <= SLOT_1_AXIS_tlast;
+  Conn1_TREADY <= SLOT_1_AXIS_tready;
+  Conn1_TVALID <= SLOT_1_AXIS_tvalid;
+  Conn2_TDATA(15 downto 0) <= SLOT_2_AXIS_tdata(15 downto 0);
+  Conn2_TLAST <= SLOT_2_AXIS_tlast;
+  Conn2_TREADY <= SLOT_2_AXIS_tready;
+  Conn2_TVALID <= SLOT_2_AXIS_tvalid;
+  Conn_ARADDR(31 downto 0) <= SLOT_0_AXI_araddr(31 downto 0);
+  Conn_ARPROT(2 downto 0) <= SLOT_0_AXI_arprot(2 downto 0);
+  Conn_ARREADY <= SLOT_0_AXI_arready;
+  Conn_ARVALID <= SLOT_0_AXI_arvalid;
+  Conn_AWADDR(31 downto 0) <= SLOT_0_AXI_awaddr(31 downto 0);
+  Conn_AWPROT(2 downto 0) <= SLOT_0_AXI_awprot(2 downto 0);
+  Conn_AWREADY <= SLOT_0_AXI_awready;
+  Conn_AWVALID <= SLOT_0_AXI_awvalid;
+  Conn_BREADY <= SLOT_0_AXI_bready;
+  Conn_BRESP(1 downto 0) <= SLOT_0_AXI_bresp(1 downto 0);
+  Conn_BVALID <= SLOT_0_AXI_bvalid;
+  Conn_RDATA(31 downto 0) <= SLOT_0_AXI_rdata(31 downto 0);
+  Conn_RREADY <= SLOT_0_AXI_rready;
+  Conn_RRESP(1 downto 0) <= SLOT_0_AXI_rresp(1 downto 0);
+  Conn_RVALID <= SLOT_0_AXI_rvalid;
+  Conn_WDATA(31 downto 0) <= SLOT_0_AXI_wdata(31 downto 0);
+  Conn_WREADY <= SLOT_0_AXI_wready;
+  Conn_WSTRB(3 downto 0) <= SLOT_0_AXI_wstrb(3 downto 0);
+  Conn_WVALID <= SLOT_0_AXI_wvalid;
+  clk_1 <= clk;
+  resetn_1 <= resetn;
+g_inst: component bd_f60c_g_inst_0
+     port map (
+      aclk => clk_1,
+      aresetn => resetn_1,
+      m_slot_0_axi_ar_cnt(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
+      m_slot_0_axi_araddr(31 downto 0) => net_slot_0_axi_araddr(31 downto 0),
+      m_slot_0_axi_arprot(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
+      m_slot_0_axi_arready => net_slot_0_axi_arready,
+      m_slot_0_axi_arvalid => net_slot_0_axi_arvalid,
+      m_slot_0_axi_aw_cnt(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
+      m_slot_0_axi_awaddr(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
+      m_slot_0_axi_awprot(2 downto 0) => net_slot_0_axi_awprot(2 downto 0),
+      m_slot_0_axi_awready => net_slot_0_axi_awready,
+      m_slot_0_axi_awvalid => net_slot_0_axi_awvalid,
+      m_slot_0_axi_b_cnt(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
+      m_slot_0_axi_bready => net_slot_0_axi_bready,
+      m_slot_0_axi_bresp(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
+      m_slot_0_axi_bvalid => net_slot_0_axi_bvalid,
+      m_slot_0_axi_r_cnt(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
+      m_slot_0_axi_rdata(31 downto 0) => net_slot_0_axi_rdata(31 downto 0),
+      m_slot_0_axi_rready => net_slot_0_axi_rready,
+      m_slot_0_axi_rresp(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
+      m_slot_0_axi_rvalid => net_slot_0_axi_rvalid,
+      m_slot_0_axi_wdata(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
+      m_slot_0_axi_wready => net_slot_0_axi_wready,
+      m_slot_0_axi_wstrb(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
+      m_slot_0_axi_wvalid => net_slot_0_axi_wvalid,
+      m_slot_1_axis_tdata(15 downto 0) => net_slot_1_axis_tdata(15 downto 0),
+      m_slot_1_axis_tlast => net_slot_1_axis_tlast,
+      m_slot_1_axis_tready => net_slot_1_axis_tready,
+      m_slot_1_axis_tvalid => net_slot_1_axis_tvalid,
+      m_slot_2_axis_tdata(15 downto 0) => net_slot_2_axis_tdata(15 downto 0),
+      m_slot_2_axis_tlast => net_slot_2_axis_tlast,
+      m_slot_2_axis_tready => net_slot_2_axis_tready,
+      m_slot_2_axis_tvalid => net_slot_2_axis_tvalid,
+      slot_0_axi_araddr(31 downto 0) => Conn_ARADDR(31 downto 0),
+      slot_0_axi_arprot(2 downto 0) => Conn_ARPROT(2 downto 0),
+      slot_0_axi_arready => Conn_ARREADY,
+      slot_0_axi_arvalid => Conn_ARVALID,
+      slot_0_axi_awaddr(31 downto 0) => Conn_AWADDR(31 downto 0),
+      slot_0_axi_awprot(2 downto 0) => Conn_AWPROT(2 downto 0),
+      slot_0_axi_awready => Conn_AWREADY,
+      slot_0_axi_awvalid => Conn_AWVALID,
+      slot_0_axi_bready => Conn_BREADY,
+      slot_0_axi_bresp(1 downto 0) => Conn_BRESP(1 downto 0),
+      slot_0_axi_bvalid => Conn_BVALID,
+      slot_0_axi_rdata(31 downto 0) => Conn_RDATA(31 downto 0),
+      slot_0_axi_rready => Conn_RREADY,
+      slot_0_axi_rresp(1 downto 0) => Conn_RRESP(1 downto 0),
+      slot_0_axi_rvalid => Conn_RVALID,
+      slot_0_axi_wdata(31 downto 0) => Conn_WDATA(31 downto 0),
+      slot_0_axi_wready => Conn_WREADY,
+      slot_0_axi_wstrb(3 downto 0) => Conn_WSTRB(3 downto 0),
+      slot_0_axi_wvalid => Conn_WVALID,
+      slot_1_axis_tdata(15 downto 0) => Conn1_TDATA(15 downto 0),
+      slot_1_axis_tlast => Conn1_TLAST,
+      slot_1_axis_tready => Conn1_TREADY,
+      slot_1_axis_tvalid => Conn1_TVALID,
+      slot_2_axis_tdata(15 downto 0) => Conn2_TDATA(15 downto 0),
+      slot_2_axis_tlast => Conn2_TLAST,
+      slot_2_axis_tready => Conn2_TREADY,
+      slot_2_axis_tvalid => Conn2_TVALID
+    );
+ila_lib: component bd_f60c_ila_lib_0
+     port map (
+      clk => clk_1,
+      probe0(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
+      probe1(31 downto 0) => net_slot_0_axi_araddr(31 downto 0),
+      probe10(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
+      probe11(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
+      probe12(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
+      probe13(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0),
+      probe14(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0),
+      probe15(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0),
+      probe16(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
+      probe17(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0),
+      probe18(15 downto 0) => net_slot_1_axis_tdata(15 downto 0),
+      probe19(0) => net_slot_1_axis_tvalid,
+      probe2(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
+      probe20(0) => net_slot_1_axis_tready,
+      probe21(0) => net_slot_1_axis_tlast,
+      probe22(15 downto 0) => net_slot_2_axis_tdata(15 downto 0),
+      probe23(0) => net_slot_2_axis_tvalid,
+      probe24(0) => net_slot_2_axis_tready,
+      probe25(0) => net_slot_2_axis_tlast,
+      probe3(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
+      probe4(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
+      probe5(2 downto 0) => net_slot_0_axi_awprot(2 downto 0),
+      probe6(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
+      probe7(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
+      probe8(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
+      probe9(31 downto 0) => net_slot_0_axi_rdata(31 downto 0)
+    );
+slot_0_ar: component bd_f60c_slot_0_ar_0
+     port map (
+      In0(0) => net_slot_0_axi_arvalid,
+      In1(0) => net_slot_0_axi_arready,
+      dout(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0)
+    );
+slot_0_aw: component bd_f60c_slot_0_aw_0
+     port map (
+      In0(0) => net_slot_0_axi_awvalid,
+      In1(0) => net_slot_0_axi_awready,
+      dout(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0)
+    );
+slot_0_b: component bd_f60c_slot_0_b_0
+     port map (
+      In0(0) => net_slot_0_axi_bvalid,
+      In1(0) => net_slot_0_axi_bready,
+      dout(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0)
+    );
+slot_0_r: component bd_f60c_slot_0_r_0
+     port map (
+      In0(0) => net_slot_0_axi_rvalid,
+      In1(0) => net_slot_0_axi_rready,
+      dout(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0)
+    );
+slot_0_w: component bd_f60c_slot_0_w_0
+     port map (
+      In0(0) => net_slot_0_axi_wvalid,
+      In1(0) => net_slot_0_axi_wready,
+      dout(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0)
+    );
+end STRUCTURE;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc

@@ -0,0 +1,57 @@
+# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of AMD and is protected under U.S. and international copyright
+# and other intellectual property laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# AMD, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) AMD shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or AMD had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# AMD products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of AMD products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 10 -name clk [get_ports clk]
+
+

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v

@@ -0,0 +1,57 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:18:42 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
+// Design      : design_1_system_ila_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "bd_f60c,Vivado 2023.1" *)
+module design_1_system_ila_0_0(clk, SLOT_0_AXI_awaddr, SLOT_0_AXI_awprot, 
+  SLOT_0_AXI_awvalid, SLOT_0_AXI_awready, SLOT_0_AXI_wdata, SLOT_0_AXI_wstrb, 
+  SLOT_0_AXI_wvalid, SLOT_0_AXI_wready, SLOT_0_AXI_bresp, SLOT_0_AXI_bvalid, 
+  SLOT_0_AXI_bready, SLOT_0_AXI_araddr, SLOT_0_AXI_arprot, SLOT_0_AXI_arvalid, 
+  SLOT_0_AXI_arready, SLOT_0_AXI_rdata, SLOT_0_AXI_rresp, SLOT_0_AXI_rvalid, 
+  SLOT_0_AXI_rready, SLOT_1_AXIS_tdata, SLOT_1_AXIS_tlast, SLOT_1_AXIS_tvalid, 
+  SLOT_1_AXIS_tready, SLOT_2_AXIS_tdata, SLOT_2_AXIS_tlast, SLOT_2_AXIS_tvalid, 
+  SLOT_2_AXIS_tready, resetn)
+/* synthesis syn_black_box black_box_pad_pin="SLOT_0_AXI_awaddr[31:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[31:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,SLOT_1_AXIS_tdata[15:0],SLOT_1_AXIS_tlast,SLOT_1_AXIS_tvalid,SLOT_1_AXIS_tready,SLOT_2_AXIS_tdata[15:0],SLOT_2_AXIS_tlast,SLOT_2_AXIS_tvalid,SLOT_2_AXIS_tready,resetn" */
+/* synthesis syn_force_seq_prim="clk" */;
+  input clk /* synthesis syn_isclock = 1 */;
+  input [31:0]SLOT_0_AXI_awaddr;
+  input [2:0]SLOT_0_AXI_awprot;
+  input SLOT_0_AXI_awvalid;
+  input SLOT_0_AXI_awready;
+  input [31:0]SLOT_0_AXI_wdata;
+  input [3:0]SLOT_0_AXI_wstrb;
+  input SLOT_0_AXI_wvalid;
+  input SLOT_0_AXI_wready;
+  input [1:0]SLOT_0_AXI_bresp;
+  input SLOT_0_AXI_bvalid;
+  input SLOT_0_AXI_bready;
+  input [31:0]SLOT_0_AXI_araddr;
+  input [2:0]SLOT_0_AXI_arprot;
+  input SLOT_0_AXI_arvalid;
+  input SLOT_0_AXI_arready;
+  input [31:0]SLOT_0_AXI_rdata;
+  input [1:0]SLOT_0_AXI_rresp;
+  input SLOT_0_AXI_rvalid;
+  input SLOT_0_AXI_rready;
+  input [15:0]SLOT_1_AXIS_tdata;
+  input SLOT_1_AXIS_tlast;
+  input SLOT_1_AXIS_tvalid;
+  input SLOT_1_AXIS_tready;
+  input [15:0]SLOT_2_AXIS_tdata;
+  input SLOT_2_AXIS_tlast;
+  input SLOT_2_AXIS_tvalid;
+  input SLOT_2_AXIS_tready;
+  input resetn;
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/sim/design_1_system_ila_0_0.vhd

@@ -0,0 +1,196 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:system_ila:1.1
+-- IP Revision: 14
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_system_ila_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    SLOT_0_AXI_awvalid : IN STD_LOGIC;
+    SLOT_0_AXI_awready : IN STD_LOGIC;
+    SLOT_0_AXI_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SLOT_0_AXI_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    SLOT_0_AXI_wvalid : IN STD_LOGIC;
+    SLOT_0_AXI_wready : IN STD_LOGIC;
+    SLOT_0_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    SLOT_0_AXI_bvalid : IN STD_LOGIC;
+    SLOT_0_AXI_bready : IN STD_LOGIC;
+    SLOT_0_AXI_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    SLOT_0_AXI_arvalid : IN STD_LOGIC;
+    SLOT_0_AXI_arready : IN STD_LOGIC;
+    SLOT_0_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SLOT_0_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    SLOT_0_AXI_rvalid : IN STD_LOGIC;
+    SLOT_0_AXI_rready : IN STD_LOGIC;
+    SLOT_1_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    SLOT_1_AXIS_tlast : IN STD_LOGIC;
+    SLOT_1_AXIS_tvalid : IN STD_LOGIC;
+    SLOT_1_AXIS_tready : IN STD_LOGIC;
+    SLOT_2_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    SLOT_2_AXIS_tlast : IN STD_LOGIC;
+    SLOT_2_AXIS_tvalid : IN STD_LOGIC;
+    SLOT_2_AXIS_tready : IN STD_LOGIC;
+    resetn : IN STD_LOGIC
+  );
+END design_1_system_ila_0_0;
+
+ARCHITECTURE design_1_system_ila_0_0_arch OF design_1_system_ila_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_system_ila_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT bd_f60c IS
+    PORT (
+      clk : IN STD_LOGIC;
+      SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      SLOT_0_AXI_awvalid : IN STD_LOGIC;
+      SLOT_0_AXI_awready : IN STD_LOGIC;
+      SLOT_0_AXI_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      SLOT_0_AXI_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      SLOT_0_AXI_wvalid : IN STD_LOGIC;
+      SLOT_0_AXI_wready : IN STD_LOGIC;
+      SLOT_0_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      SLOT_0_AXI_bvalid : IN STD_LOGIC;
+      SLOT_0_AXI_bready : IN STD_LOGIC;
+      SLOT_0_AXI_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      SLOT_0_AXI_arvalid : IN STD_LOGIC;
+      SLOT_0_AXI_arready : IN STD_LOGIC;
+      SLOT_0_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      SLOT_0_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      SLOT_0_AXI_rvalid : IN STD_LOGIC;
+      SLOT_0_AXI_rready : IN STD_LOGIC;
+      SLOT_1_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      SLOT_1_AXIS_tlast : IN STD_LOGIC;
+      SLOT_1_AXIS_tvalid : IN STD_LOGIC;
+      SLOT_1_AXIS_tready : IN STD_LOGIC;
+      SLOT_2_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      SLOT_2_AXIS_tlast : IN STD_LOGIC;
+      SLOT_2_AXIS_tvalid : IN STD_LOGIC;
+      SLOT_2_AXIS_tready : IN STD_LOGIC;
+      resetn : IN STD_LOGIC
+    );
+  END COMPONENT bd_f60c;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_0_AXI_awaddr: SIGNAL IS "XIL_INTERFACENAME SLOT_0_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, R" & 
+"USER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_1_AXIS_tdata: SIGNAL IS "XIL_INTERFACENAME SLOT_1_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_2_AXIS_tdata: SIGNAL IS "XIL_INTERFACENAME SLOT_2_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS, ASSOCIATED_RESET resetn, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.clk CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME RST.resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.resetn RST";
+BEGIN
+  U0 : bd_f60c
+    PORT MAP (
+      clk => clk,
+      SLOT_0_AXI_awaddr => SLOT_0_AXI_awaddr,
+      SLOT_0_AXI_awprot => SLOT_0_AXI_awprot,
+      SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
+      SLOT_0_AXI_awready => SLOT_0_AXI_awready,
+      SLOT_0_AXI_wdata => SLOT_0_AXI_wdata,
+      SLOT_0_AXI_wstrb => SLOT_0_AXI_wstrb,
+      SLOT_0_AXI_wvalid => SLOT_0_AXI_wvalid,
+      SLOT_0_AXI_wready => SLOT_0_AXI_wready,
+      SLOT_0_AXI_bresp => SLOT_0_AXI_bresp,
+      SLOT_0_AXI_bvalid => SLOT_0_AXI_bvalid,
+      SLOT_0_AXI_bready => SLOT_0_AXI_bready,
+      SLOT_0_AXI_araddr => SLOT_0_AXI_araddr,
+      SLOT_0_AXI_arprot => SLOT_0_AXI_arprot,
+      SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
+      SLOT_0_AXI_arready => SLOT_0_AXI_arready,
+      SLOT_0_AXI_rdata => SLOT_0_AXI_rdata,
+      SLOT_0_AXI_rresp => SLOT_0_AXI_rresp,
+      SLOT_0_AXI_rvalid => SLOT_0_AXI_rvalid,
+      SLOT_0_AXI_rready => SLOT_0_AXI_rready,
+      SLOT_1_AXIS_tdata => SLOT_1_AXIS_tdata,
+      SLOT_1_AXIS_tlast => SLOT_1_AXIS_tlast,
+      SLOT_1_AXIS_tvalid => SLOT_1_AXIS_tvalid,
+      SLOT_1_AXIS_tready => SLOT_1_AXIS_tready,
+      SLOT_2_AXIS_tdata => SLOT_2_AXIS_tdata,
+      SLOT_2_AXIS_tlast => SLOT_2_AXIS_tlast,
+      SLOT_2_AXIS_tvalid => SLOT_2_AXIS_tvalid,
+      SLOT_2_AXIS_tready => SLOT_2_AXIS_tready,
+      resetn => resetn
+    );
+END design_1_system_ila_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/synth/design_1_system_ila_0_0.vhd

@@ -0,0 +1,361 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:system_ila:1.1
+-- IP Revision: 14
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_system_ila_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    SLOT_0_AXI_awvalid : IN STD_LOGIC;
+    SLOT_0_AXI_awready : IN STD_LOGIC;
+    SLOT_0_AXI_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SLOT_0_AXI_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    SLOT_0_AXI_wvalid : IN STD_LOGIC;
+    SLOT_0_AXI_wready : IN STD_LOGIC;
+    SLOT_0_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    SLOT_0_AXI_bvalid : IN STD_LOGIC;
+    SLOT_0_AXI_bready : IN STD_LOGIC;
+    SLOT_0_AXI_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    SLOT_0_AXI_arvalid : IN STD_LOGIC;
+    SLOT_0_AXI_arready : IN STD_LOGIC;
+    SLOT_0_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SLOT_0_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    SLOT_0_AXI_rvalid : IN STD_LOGIC;
+    SLOT_0_AXI_rready : IN STD_LOGIC;
+    SLOT_1_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    SLOT_1_AXIS_tlast : IN STD_LOGIC;
+    SLOT_1_AXIS_tvalid : IN STD_LOGIC;
+    SLOT_1_AXIS_tready : IN STD_LOGIC;
+    SLOT_2_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    SLOT_2_AXIS_tlast : IN STD_LOGIC;
+    SLOT_2_AXIS_tvalid : IN STD_LOGIC;
+    SLOT_2_AXIS_tready : IN STD_LOGIC;
+    resetn : IN STD_LOGIC
+  );
+END design_1_system_ila_0_0;
+
+ARCHITECTURE design_1_system_ila_0_0_arch OF design_1_system_ila_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_system_ila_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT bd_f60c IS
+    PORT (
+      clk : IN STD_LOGIC;
+      SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      SLOT_0_AXI_awvalid : IN STD_LOGIC;
+      SLOT_0_AXI_awready : IN STD_LOGIC;
+      SLOT_0_AXI_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      SLOT_0_AXI_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      SLOT_0_AXI_wvalid : IN STD_LOGIC;
+      SLOT_0_AXI_wready : IN STD_LOGIC;
+      SLOT_0_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      SLOT_0_AXI_bvalid : IN STD_LOGIC;
+      SLOT_0_AXI_bready : IN STD_LOGIC;
+      SLOT_0_AXI_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      SLOT_0_AXI_arvalid : IN STD_LOGIC;
+      SLOT_0_AXI_arready : IN STD_LOGIC;
+      SLOT_0_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      SLOT_0_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      SLOT_0_AXI_rvalid : IN STD_LOGIC;
+      SLOT_0_AXI_rready : IN STD_LOGIC;
+      SLOT_1_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      SLOT_1_AXIS_tlast : IN STD_LOGIC;
+      SLOT_1_AXIS_tvalid : IN STD_LOGIC;
+      SLOT_1_AXIS_tready : IN STD_LOGIC;
+      SLOT_2_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      SLOT_2_AXIS_tlast : IN STD_LOGIC;
+      SLOT_2_AXIS_tvalid : IN STD_LOGIC;
+      SLOT_2_AXIS_tready : IN STD_LOGIC;
+      resetn : IN STD_LOGIC
+    );
+  END COMPONENT bd_f60c;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_system_ila_0_0_arch: ARCHITECTURE IS "bd_f60c,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_system_ila_0_0_arch : ARCHITECTURE IS "design_1_system_ila_0_0,bd_f60c,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_system_ila_0_0_arch: ARCHITECTURE IS "design_1_system_ila_0_0,bd_f60c,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=system_ila,x_ipVersion=1.1,x_ipCoreRevision=14,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_SLOT=2,C_SLOT_15_TYPE=0,C_SLOT_14_TYPE=0,C_SLOT_13_TYPE=0,C_SLOT_12_TYPE=0,C_SLOT_11_TYPE=0,C_SLOT_10_TYPE=0,C_SLOT_9_TYPE=0,C_SLOT_8_TYPE=0,C_SLOT_7_TYPE=0,C_SLOT_6_TYPE=0,C_SLOT_5_TYPE=0,C_SLOT_4_TYPE=0,C_SLOT_3_TYPE=0,C_SLOT_2_TYPE=0,C_SLOT_1_TYPE=0,C_SLOT_0_TYPE=0,C" & 
+"_SLOT_0_MAX_RD_BURSTS=2,C_SLOT_0_MAX_WR_BURSTS=2,C_SLOT_1_MAX_RD_BURSTS=2,C_SLOT_1_MAX_WR_BURSTS=2,C_SLOT_2_MAX_RD_BURSTS=2,C_SLOT_2_MAX_WR_BURSTS=2,C_SLOT_3_MAX_RD_BURSTS=2,C_SLOT_3_MAX_WR_BURSTS=2,C_SLOT_4_MAX_RD_BURSTS=2,C_SLOT_4_MAX_WR_BURSTS=2,C_SLOT_5_MAX_RD_BURSTS=2,C_SLOT_5_MAX_WR_BURSTS=2,C_SLOT_6_MAX_RD_BURSTS=2,C_SLOT_6_MAX_WR_BURSTS=2,C_SLOT_7_MAX_RD_BURSTS=2,C_SLOT_7_MAX_WR_BURSTS=2,C_SLOT_8_MAX_RD_BURSTS=2,C_SLOT_8_MAX_WR_BURSTS=2,C_SLOT_9_MAX_RD_BURSTS=2,C_SLOT_9_MAX_WR_BURSTS=2,C" & 
+"_SLOT_10_MAX_RD_BURSTS=2,C_SLOT_10_MAX_WR_BURSTS=2,C_SLOT_11_MAX_RD_BURSTS=2,C_SLOT_11_MAX_WR_BURSTS=2,C_SLOT_12_MAX_RD_BURSTS=2,C_SLOT_12_MAX_WR_BURSTS=2,C_SLOT_13_MAX_RD_BURSTS=2,C_SLOT_13_MAX_WR_BURSTS=2,C_SLOT_14_MAX_RD_BURSTS=2,C_SLOT_14_MAX_WR_BURSTS=2,C_SLOT_15_MAX_RD_BURSTS=2,C_SLOT_15_MAX_WR_BURSTS=2,C_SLOT_0_TXN_CNTR_EN=1,C_SLOT_1_TXN_CNTR_EN=1,C_SLOT_2_TXN_CNTR_EN=1,C_SLOT_3_TXN_CNTR_EN=1,C_SLOT_4_TXN_CNTR_EN=1,C_SLOT_5_TXN_CNTR_EN=1,C_SLOT_6_TXN_CNTR_EN=1,C_SLOT_7_TXN_CNTR_EN=1,C_SLO" & 
+"T_8_TXN_CNTR_EN=1,C_SLOT_9_TXN_CNTR_EN=1,C_SLOT_10_TXN_CNTR_EN=1,C_SLOT_11_TXN_CNTR_EN=1,C_SLOT_12_TXN_CNTR_EN=1,C_SLOT_13_TXN_CNTR_EN=1,C_SLOT_14_TXN_CNTR_EN=1,C_SLOT_15_TXN_CNTR_EN=1,C_SLOT_0_APC_STS_EN=0,C_SLOT_1_APC_STS_EN=0,C_SLOT_2_APC_STS_EN=0,C_SLOT_3_APC_STS_EN=0,C_SLOT_4_APC_STS_EN=0,C_SLOT_5_APC_STS_EN=0,C_SLOT_6_APC_STS_EN=0,C_SLOT_7_APC_STS_EN=0,C_SLOT_8_APC_STS_EN=0,C_SLOT_9_APC_STS_EN=0,C_SLOT_10_APC_STS_EN=0,C_SLOT_11_APC_STS_EN=0,C_SLOT_12_APC_STS_EN=0,C_SLOT_13_APC_STS_EN=0,C_S" & 
+"LOT_14_APC_STS_EN=0,C_SLOT_15_APC_STS_EN=0,C_SLOT_0_APC_EN=0,C_SLOT_1_APC_EN=0,C_SLOT_2_APC_EN=0,C_SLOT_3_APC_EN=0,C_SLOT_4_APC_EN=0,C_SLOT_5_APC_EN=0,C_SLOT_6_APC_EN=0,C_SLOT_7_APC_EN=0,C_SLOT_8_APC_EN=0,C_SLOT_9_APC_EN=0,C_SLOT_10_APC_EN=0,C_SLOT_11_APC_EN=0,C_SLOT_12_APC_EN=0,C_SLOT_13_APC_EN=0,C_SLOT_14_APC_EN=0,C_SLOT_15_APC_EN=0,C_SLOT_0_APC_MAX_AW_WAITS=0,C_SLOT_0_APC_MAX_AR_WAITS=0,C_SLOT_0_APC_MAX_W_WAITS=0,C_SLOT_0_APC_MAX_B_WAITS=0,C_SLOT_0_APC_MAX_R_WAITS=0,C_SLOT_0_APC_MAX_CONTINUOU" & 
+"S_WTRANSFERS_WAITS=0,C_SLOT_0_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_0_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_0_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_AW_WAITS=0,C_SLOT_1_APC_MAX_AR_WAITS=0,C_SLOT_1_APC_MAX_W_WAITS=0,C_SLOT_1_APC_MAX_B_WAITS=0,C_SLOT_1_APC_MAX_R_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_1_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_AW_WAITS=0,C_SLOT_" & 
+"2_APC_MAX_AR_WAITS=0,C_SLOT_2_APC_MAX_W_WAITS=0,C_SLOT_2_APC_MAX_B_WAITS=0,C_SLOT_2_APC_MAX_R_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_2_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_AW_WAITS=0,C_SLOT_3_APC_MAX_AR_WAITS=0,C_SLOT_3_APC_MAX_W_WAITS=0,C_SLOT_3_APC_MAX_B_WAITS=0,C_SLOT_3_APC_MAX_R_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_WLAST_TO_AWVALID_WAI" & 
+"TS=0,C_SLOT_3_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_AW_WAITS=0,C_SLOT_4_APC_MAX_AR_WAITS=0,C_SLOT_4_APC_MAX_W_WAITS=0,C_SLOT_4_APC_MAX_B_WAITS=0,C_SLOT_4_APC_MAX_R_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_4_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_5_APC_MAX_AW_WAITS=0,C_SLOT_5_APC_MAX_AR_WAITS=0,C_SLOT_5_APC_MAX_W_WAITS=0,C_SLOT_5_A" & 
+"PC_MAX_B_WAITS=0,C_SLOT_5_APC_MAX_R_WAITS=0,C_SLOT_5_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_5_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_5_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_5_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_6_APC_MAX_AW_WAITS=0,C_SLOT_6_APC_MAX_AR_WAITS=0,C_SLOT_6_APC_MAX_W_WAITS=0,C_SLOT_6_APC_MAX_B_WAITS=0,C_SLOT_6_APC_MAX_R_WAITS=0,C_SLOT_6_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_6_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_6_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_6_APC" & 
+"_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_7_APC_MAX_AW_WAITS=0,C_SLOT_7_APC_MAX_AR_WAITS=0,C_SLOT_7_APC_MAX_W_WAITS=0,C_SLOT_7_APC_MAX_B_WAITS=0,C_SLOT_7_APC_MAX_R_WAITS=0,C_SLOT_7_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_7_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_7_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_7_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_8_APC_MAX_AW_WAITS=0,C_SLOT_8_APC_MAX_AR_WAITS=0,C_SLOT_8_APC_MAX_W_WAITS=0,C_SLOT_8_APC_MAX_B_WAITS=0,C_SLOT_8_APC_MAX_R_WAITS=0,C_SLOT_8_APC_M" & 
+"AX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_8_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_8_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_8_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_9_APC_MAX_AW_WAITS=0,C_SLOT_9_APC_MAX_AR_WAITS=0,C_SLOT_9_APC_MAX_W_WAITS=0,C_SLOT_9_APC_MAX_B_WAITS=0,C_SLOT_9_APC_MAX_R_WAITS=0,C_SLOT_9_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_9_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_9_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_9_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_10_APC_MAX_AW_WA" & 
+"ITS=0,C_SLOT_10_APC_MAX_AR_WAITS=0,C_SLOT_10_APC_MAX_W_WAITS=0,C_SLOT_10_APC_MAX_B_WAITS=0,C_SLOT_10_APC_MAX_R_WAITS=0,C_SLOT_10_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_10_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_10_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_10_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_11_APC_MAX_AW_WAITS=0,C_SLOT_11_APC_MAX_AR_WAITS=0,C_SLOT_11_APC_MAX_W_WAITS=0,C_SLOT_11_APC_MAX_B_WAITS=0,C_SLOT_11_APC_MAX_R_WAITS=0,C_SLOT_11_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_11_" & 
+"APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_11_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_11_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_12_APC_MAX_AW_WAITS=0,C_SLOT_12_APC_MAX_AR_WAITS=0,C_SLOT_12_APC_MAX_W_WAITS=0,C_SLOT_12_APC_MAX_B_WAITS=0,C_SLOT_12_APC_MAX_R_WAITS=0,C_SLOT_12_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_12_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_12_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_12_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_13_APC_MAX_AW_WAITS=0,C_SLOT_13_APC_MAX_AR_WAIT" & 
+"S=0,C_SLOT_13_APC_MAX_W_WAITS=0,C_SLOT_13_APC_MAX_B_WAITS=0,C_SLOT_13_APC_MAX_R_WAITS=0,C_SLOT_13_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_13_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_13_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_13_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_14_APC_MAX_AW_WAITS=0,C_SLOT_14_APC_MAX_AR_WAITS=0,C_SLOT_14_APC_MAX_W_WAITS=0,C_SLOT_14_APC_MAX_B_WAITS=0,C_SLOT_14_APC_MAX_R_WAITS=0,C_SLOT_14_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_14_APC_MAX_WLAST_TO_AWVALID_WAITS=" & 
+"0,C_SLOT_14_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_14_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_15_APC_MAX_AW_WAITS=0,C_SLOT_15_APC_MAX_AR_WAITS=0,C_SLOT_15_APC_MAX_W_WAITS=0,C_SLOT_15_APC_MAX_B_WAITS=0,C_SLOT_15_APC_MAX_R_WAITS=0,C_SLOT_15_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_15_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_15_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_15_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_BRAM_CNT=0.0,C_SLOT_0_AXI_AW_SEL_DATA=1,C_SLOT_0_AXI_W_SEL_DATA=1,C_SLOT_0_AXI_B_SE" & 
+"L_DATA=1,C_SLOT_0_AXI_AR_SEL_DATA=1,C_SLOT_0_AXI_R_SEL_DATA=1,C_SLOT_1_AXI_AW_SEL_DATA=1,C_SLOT_1_AXI_W_SEL_DATA=1,C_SLOT_1_AXI_B_SEL_DATA=1,C_SLOT_1_AXI_AR_SEL_DATA=1,C_SLOT_1_AXI_R_SEL_DATA=1,C_SLOT_2_AXI_AW_SEL_DATA=1,C_SLOT_2_AXI_W_SEL_DATA=1,C_SLOT_2_AXI_B_SEL_DATA=1,C_SLOT_2_AXI_AR_SEL_DATA=1,C_SLOT_2_AXI_R_SEL_DATA=1,C_SLOT_3_AXI_AW_SEL_DATA=1,C_SLOT_3_AXI_W_SEL_DATA=1,C_SLOT_3_AXI_B_SEL_DATA=1,C_SLOT_3_AXI_AR_SEL_DATA=1,C_SLOT_3_AXI_R_SEL_DATA=1,C_SLOT_4_AXI_AW_SEL_DATA=1,C_SLOT_4_AXI_W_" & 
+"SEL_DATA=1,C_SLOT_4_AXI_B_SEL_DATA=1,C_SLOT_4_AXI_AR_SEL_DATA=1,C_SLOT_4_AXI_R_SEL_DATA=1,C_SLOT_5_AXI_AW_SEL_DATA=1,C_SLOT_5_AXI_W_SEL_DATA=1,C_SLOT_5_AXI_B_SEL_DATA=1,C_SLOT_5_AXI_AR_SEL_DATA=1,C_SLOT_5_AXI_R_SEL_DATA=1,C_SLOT_6_AXI_AW_SEL_DATA=1,C_SLOT_6_AXI_W_SEL_DATA=1,C_SLOT_6_AXI_B_SEL_DATA=1,C_SLOT_6_AXI_AR_SEL_DATA=1,C_SLOT_6_AXI_R_SEL_DATA=1,C_SLOT_7_AXI_AW_SEL_DATA=1,C_SLOT_7_AXI_W_SEL_DATA=1,C_SLOT_7_AXI_B_SEL_DATA=1,C_SLOT_7_AXI_AR_SEL_DATA=1,C_SLOT_7_AXI_R_SEL_DATA=1,C_SLOT_8_AXI_A" & 
+"W_SEL_DATA=1,C_SLOT_8_AXI_W_SEL_DATA=1,C_SLOT_8_AXI_B_SEL_DATA=1,C_SLOT_8_AXI_AR_SEL_DATA=1,C_SLOT_8_AXI_R_SEL_DATA=1,C_SLOT_9_AXI_AW_SEL_DATA=1,C_SLOT_9_AXI_W_SEL_DATA=1,C_SLOT_9_AXI_B_SEL_DATA=1,C_SLOT_9_AXI_AR_SEL_DATA=1,C_SLOT_9_AXI_R_SEL_DATA=1,C_SLOT_10_AXI_AW_SEL_DATA=1,C_SLOT_10_AXI_W_SEL_DATA=1,C_SLOT_10_AXI_B_SEL_DATA=1,C_SLOT_10_AXI_AR_SEL_DATA=1,C_SLOT_10_AXI_R_SEL_DATA=1,C_SLOT_11_AXI_AW_SEL_DATA=1,C_SLOT_11_AXI_W_SEL_DATA=1,C_SLOT_11_AXI_B_SEL_DATA=1,C_SLOT_11_AXI_AR_SEL_DATA=1,C_S" & 
+"LOT_11_AXI_R_SEL_DATA=1,C_SLOT_12_AXI_AW_SEL_DATA=1,C_SLOT_12_AXI_W_SEL_DATA=1,C_SLOT_12_AXI_B_SEL_DATA=1,C_SLOT_12_AXI_AR_SEL_DATA=1,C_SLOT_12_AXI_R_SEL_DATA=1,C_SLOT_13_AXI_AW_SEL_DATA=1,C_SLOT_13_AXI_W_SEL_DATA=1,C_SLOT_13_AXI_B_SEL_DATA=1,C_SLOT_13_AXI_AR_SEL_DATA=1,C_SLOT_13_AXI_R_SEL_DATA=1,C_SLOT_14_AXI_AW_SEL_DATA=1,C_SLOT_14_AXI_W_SEL_DATA=1,C_SLOT_14_AXI_B_SEL_DATA=1,C_SLOT_14_AXI_AR_SEL_DATA=1,C_SLOT_14_AXI_R_SEL_DATA=1,C_SLOT_15_AXI_AW_SEL_DATA=1,C_SLOT_15_AXI_W_SEL_DATA=1,C_SLOT_15_" & 
+"AXI_B_SEL_DATA=1,C_SLOT_15_AXI_AR_SEL_DATA=1,C_SLOT_15_AXI_R_SEL_DATA=1,C_SLOT_0_AXI_AW_SEL_TRIG=1,C_SLOT_0_AXI_W_SEL_TRIG=1,C_SLOT_0_AXI_B_SEL_TRIG=1,C_SLOT_0_AXI_AR_SEL_TRIG=1,C_SLOT_0_AXI_R_SEL_TRIG=1,C_SLOT_1_AXI_AW_SEL_TRIG=1,C_SLOT_1_AXI_W_SEL_TRIG=1,C_SLOT_1_AXI_B_SEL_TRIG=1,C_SLOT_1_AXI_AR_SEL_TRIG=1,C_SLOT_1_AXI_R_SEL_TRIG=1,C_SLOT_2_AXI_AW_SEL_TRIG=1,C_SLOT_2_AXI_W_SEL_TRIG=1,C_SLOT_2_AXI_B_SEL_TRIG=1,C_SLOT_2_AXI_AR_SEL_TRIG=1,C_SLOT_2_AXI_R_SEL_TRIG=1,C_SLOT_3_AXI_AW_SEL_TRIG=1,C_SLO" & 
+"T_3_AXI_W_SEL_TRIG=1,C_SLOT_3_AXI_B_SEL_TRIG=1,C_SLOT_3_AXI_AR_SEL_TRIG=1,C_SLOT_3_AXI_R_SEL_TRIG=1,C_SLOT_4_AXI_AW_SEL_TRIG=1,C_SLOT_4_AXI_W_SEL_TRIG=1,C_SLOT_4_AXI_B_SEL_TRIG=1,C_SLOT_4_AXI_AR_SEL_TRIG=1,C_SLOT_4_AXI_R_SEL_TRIG=1,C_SLOT_5_AXI_AW_SEL_TRIG=1,C_SLOT_5_AXI_W_SEL_TRIG=1,C_SLOT_5_AXI_B_SEL_TRIG=1,C_SLOT_5_AXI_AR_SEL_TRIG=1,C_SLOT_5_AXI_R_SEL_TRIG=1,C_SLOT_6_AXI_AW_SEL_TRIG=1,C_SLOT_6_AXI_W_SEL_TRIG=1,C_SLOT_6_AXI_B_SEL_TRIG=1,C_SLOT_6_AXI_AR_SEL_TRIG=1,C_SLOT_6_AXI_R_SEL_TRIG=1,C_SL" & 
+"OT_7_AXI_AW_SEL_TRIG=1,C_SLOT_7_AXI_W_SEL_TRIG=1,C_SLOT_7_AXI_B_SEL_TRIG=1,C_SLOT_7_AXI_AR_SEL_TRIG=1,C_SLOT_7_AXI_R_SEL_TRIG=1,C_SLOT_8_AXI_AW_SEL_TRIG=1,C_SLOT_8_AXI_W_SEL_TRIG=1,C_SLOT_8_AXI_B_SEL_TRIG=1,C_SLOT_8_AXI_AR_SEL_TRIG=1,C_SLOT_8_AXI_R_SEL_TRIG=1,C_SLOT_9_AXI_AW_SEL_TRIG=1,C_SLOT_9_AXI_W_SEL_TRIG=1,C_SLOT_9_AXI_B_SEL_TRIG=1,C_SLOT_9_AXI_AR_SEL_TRIG=1,C_SLOT_9_AXI_R_SEL_TRIG=1,C_SLOT_10_AXI_AW_SEL_TRIG=1,C_SLOT_10_AXI_W_SEL_TRIG=1,C_SLOT_10_AXI_B_SEL_TRIG=1,C_SLOT_10_AXI_AR_SEL_TRIG=" & 
+"1,C_SLOT_10_AXI_R_SEL_TRIG=1,C_SLOT_11_AXI_AW_SEL_TRIG=1,C_SLOT_11_AXI_W_SEL_TRIG=1,C_SLOT_11_AXI_B_SEL_TRIG=1,C_SLOT_11_AXI_AR_SEL_TRIG=1,C_SLOT_11_AXI_R_SEL_TRIG=1,C_SLOT_12_AXI_AW_SEL_TRIG=1,C_SLOT_12_AXI_W_SEL_TRIG=1,C_SLOT_12_AXI_B_SEL_TRIG=1,C_SLOT_12_AXI_AR_SEL_TRIG=1,C_SLOT_12_AXI_R_SEL_TRIG=1,C_SLOT_13_AXI_AW_SEL_TRIG=1,C_SLOT_13_AXI_W_SEL_TRIG=1,C_SLOT_13_AXI_B_SEL_TRIG=1,C_SLOT_13_AXI_AR_SEL_TRIG=1,C_SLOT_13_AXI_R_SEL_TRIG=1,C_SLOT_14_AXI_AW_SEL_TRIG=1,C_SLOT_14_AXI_W_SEL_TRIG=1,C_SLO" & 
+"T_14_AXI_B_SEL_TRIG=1,C_SLOT_14_AXI_AR_SEL_TRIG=1,C_SLOT_14_AXI_R_SEL_TRIG=1,C_SLOT_15_AXI_AW_SEL_TRIG=1,C_SLOT_15_AXI_W_SEL_TRIG=1,C_SLOT_15_AXI_B_SEL_TRIG=1,C_SLOT_15_AXI_AR_SEL_TRIG=1,C_SLOT_15_AXI_R_SEL_TRIG=1,C_SLOT_0_AXI_AW_SEL=1,C_SLOT_0_AXI_W_SEL=1,C_SLOT_0_AXI_B_SEL=1,C_SLOT_0_AXI_AR_SEL=1,C_SLOT_0_AXI_R_SEL=1,C_SLOT_1_AXI_AW_SEL=1,C_SLOT_1_AXI_W_SEL=1,C_SLOT_1_AXI_B_SEL=1,C_SLOT_1_AXI_AR_SEL=1,C_SLOT_1_AXI_R_SEL=1,C_SLOT_2_AXI_AW_SEL=1,C_SLOT_2_AXI_W_SEL=1,C_SLOT_2_AXI_B_SEL=1,C_SLOT_2" & 
+"_AXI_AR_SEL=1,C_SLOT_2_AXI_R_SEL=1,C_SLOT_3_AXI_AW_SEL=1,C_SLOT_3_AXI_W_SEL=1,C_SLOT_3_AXI_B_SEL=1,C_SLOT_3_AXI_AR_SEL=1,C_SLOT_3_AXI_R_SEL=1,C_SLOT_4_AXI_AW_SEL=1,C_SLOT_4_AXI_W_SEL=1,C_SLOT_4_AXI_B_SEL=1,C_SLOT_4_AXI_AR_SEL=1,C_SLOT_4_AXI_R_SEL=1,C_SLOT_5_AXI_AW_SEL=1,C_SLOT_5_AXI_W_SEL=1,C_SLOT_5_AXI_B_SEL=1,C_SLOT_5_AXI_AR_SEL=1,C_SLOT_5_AXI_R_SEL=1,C_SLOT_6_AXI_AW_SEL=1,C_SLOT_6_AXI_W_SEL=1,C_SLOT_6_AXI_B_SEL=1,C_SLOT_6_AXI_AR_SEL=1,C_SLOT_6_AXI_R_SEL=1,C_SLOT_7_AXI_AW_SEL=1,C_SLOT_7_AXI_W_" & 
+"SEL=1,C_SLOT_7_AXI_B_SEL=1,C_SLOT_7_AXI_AR_SEL=1,C_SLOT_7_AXI_R_SEL=1,C_SLOT_8_AXI_AW_SEL=1,C_SLOT_8_AXI_W_SEL=1,C_SLOT_8_AXI_B_SEL=1,C_SLOT_8_AXI_AR_SEL=1,C_SLOT_8_AXI_R_SEL=1,C_SLOT_9_AXI_AW_SEL=1,C_SLOT_9_AXI_W_SEL=1,C_SLOT_9_AXI_B_SEL=1,C_SLOT_9_AXI_AR_SEL=1,C_SLOT_9_AXI_R_SEL=1,C_SLOT_10_AXI_AW_SEL=1,C_SLOT_10_AXI_W_SEL=1,C_SLOT_10_AXI_B_SEL=1,C_SLOT_10_AXI_AR_SEL=1,C_SLOT_10_AXI_R_SEL=1,C_SLOT_11_AXI_AW_SEL=1,C_SLOT_11_AXI_W_SEL=1,C_SLOT_11_AXI_B_SEL=1,C_SLOT_11_AXI_AR_SEL=1,C_SLOT_11_AXI_" & 
+"R_SEL=1,C_SLOT_12_AXI_AW_SEL=1,C_SLOT_12_AXI_W_SEL=1,C_SLOT_12_AXI_B_SEL=1,C_SLOT_12_AXI_AR_SEL=1,C_SLOT_12_AXI_R_SEL=1,C_SLOT_13_AXI_AW_SEL=1,C_SLOT_13_AXI_W_SEL=1,C_SLOT_13_AXI_B_SEL=1,C_SLOT_13_AXI_AR_SEL=1,C_SLOT_13_AXI_R_SEL=1,C_SLOT_14_AXI_AW_SEL=1,C_SLOT_14_AXI_W_SEL=1,C_SLOT_14_AXI_B_SEL=1,C_SLOT_14_AXI_AR_SEL=1,C_SLOT_14_AXI_R_SEL=1,C_SLOT_15_AXI_AW_SEL=1,C_SLOT_15_AXI_W_SEL=1,C_SLOT_15_AXI_B_SEL=1,C_SLOT_15_AXI_AR_SEL=1,C_SLOT_15_AXI_R_SEL=1,C_SLOT_0_AXI_DATA_SEL=1,C_SLOT_1_AXI_DATA_SE" & 
+"L=1,C_SLOT_2_AXI_DATA_SEL=1,C_SLOT_3_AXI_DATA_SEL=1,C_SLOT_4_AXI_DATA_SEL=1,C_SLOT_5_AXI_DATA_SEL=1,C_SLOT_6_AXI_DATA_SEL=1,C_SLOT_7_AXI_DATA_SEL=1,C_SLOT_8_AXI_DATA_SEL=1,C_SLOT_9_AXI_DATA_SEL=1,C_SLOT_10_AXI_DATA_SEL=1,C_SLOT_11_AXI_DATA_SEL=1,C_SLOT_12_AXI_DATA_SEL=1,C_SLOT_13_AXI_DATA_SEL=1,C_SLOT_14_AXI_DATA_SEL=1,C_SLOT_15_AXI_DATA_SEL=1,C_SLOT_0_AXI_TRIG_SEL=1,C_SLOT_1_AXI_TRIG_SEL=1,C_SLOT_2_AXI_TRIG_SEL=1,C_SLOT_3_AXI_TRIG_SEL=1,C_SLOT_4_AXI_TRIG_SEL=1,C_SLOT_5_AXI_TRIG_SEL=1,C_SLOT_6_A" & 
+"XI_TRIG_SEL=1,C_SLOT_7_AXI_TRIG_SEL=1,C_SLOT_8_AXI_TRIG_SEL=1,C_SLOT_9_AXI_TRIG_SEL=1,C_SLOT_10_AXI_TRIG_SEL=1,C_SLOT_11_AXI_TRIG_SEL=1,C_SLOT_12_AXI_TRIG_SEL=1,C_SLOT_13_AXI_TRIG_SEL=1,C_SLOT_14_AXI_TRIG_SEL=1,C_SLOT_15_AXI_TRIG_SEL=1,C_PROBE1023_TYPE=0,C_PROBE1022_TYPE=0,C_PROBE1021_TYPE=0,C_PROBE1020_TYPE=0,C_PROBE1019_TYPE=0,C_PROBE1018_TYPE=0,C_PROBE1017_TYPE=0,C_PROBE1016_TYPE=0,C_PROBE1015_TYPE=0,C_PROBE1014_TYPE=0,C_PROBE1013_TYPE=0,C_PROBE1012_TYPE=0,C_PROBE1011_TYPE=0,C_PROBE1010_TYPE=" & 
+"0,C_PROBE1009_TYPE=0,C_PROBE1008_TYPE=0,C_PROBE1007_TYPE=0,C_PROBE1006_TYPE=0,C_PROBE1005_TYPE=0,C_PROBE1004_TYPE=0,C_PROBE1003_TYPE=0,C_PROBE1002_TYPE=0,C_PROBE1001_TYPE=0,C_PROBE1000_TYPE=0,C_PROBE999_TYPE=0,C_PROBE998_TYPE=0,C_PROBE997_TYPE=0,C_PROBE996_TYPE=0,C_PROBE995_TYPE=0,C_PROBE994_TYPE=0,C_PROBE993_TYPE=0,C_PROBE992_TYPE=0,C_PROBE991_TYPE=0,C_PROBE990_TYPE=0,C_PROBE989_TYPE=0,C_PROBE988_TYPE=0,C_PROBE987_TYPE=0,C_PROBE986_TYPE=0,C_PROBE985_TYPE=0,C_PROBE984_TYPE=0,C_PROBE983_TYPE=0,C_" & 
+"PROBE982_TYPE=0,C_PROBE981_TYPE=0,C_PROBE980_TYPE=0,C_PROBE979_TYPE=0,C_PROBE978_TYPE=0,C_PROBE977_TYPE=0,C_PROBE976_TYPE=0,C_PROBE975_TYPE=0,C_PROBE974_TYPE=0,C_PROBE973_TYPE=0,C_PROBE972_TYPE=0,C_PROBE971_TYPE=0,C_PROBE970_TYPE=0,C_PROBE969_TYPE=0,C_PROBE968_TYPE=0,C_PROBE967_TYPE=0,C_PROBE966_TYPE=0,C_PROBE965_TYPE=0,C_PROBE964_TYPE=0,C_PROBE963_TYPE=0,C_PROBE962_TYPE=0,C_PROBE961_TYPE=0,C_PROBE960_TYPE=0,C_PROBE959_TYPE=0,C_PROBE958_TYPE=0,C_PROBE957_TYPE=0,C_PROBE956_TYPE=0,C_PROBE955_TYPE=" & 
+"0,C_PROBE954_TYPE=0,C_PROBE953_TYPE=0,C_PROBE952_TYPE=0,C_PROBE951_TYPE=0,C_PROBE950_TYPE=0,C_PROBE949_TYPE=0,C_PROBE948_TYPE=0,C_PROBE947_TYPE=0,C_PROBE946_TYPE=0,C_PROBE945_TYPE=0,C_PROBE944_TYPE=0,C_PROBE943_TYPE=0,C_PROBE942_TYPE=0,C_PROBE941_TYPE=0,C_PROBE940_TYPE=0,C_PROBE939_TYPE=0,C_PROBE938_TYPE=0,C_PROBE937_TYPE=0,C_PROBE936_TYPE=0,C_PROBE935_TYPE=0,C_PROBE934_TYPE=0,C_PROBE933_TYPE=0,C_PROBE932_TYPE=0,C_PROBE931_TYPE=0,C_PROBE930_TYPE=0,C_PROBE929_TYPE=0,C_PROBE928_TYPE=0,C_PROBE927_T" & 
+"YPE=0,C_PROBE926_TYPE=0,C_PROBE925_TYPE=0,C_PROBE924_TYPE=0,C_PROBE923_TYPE=0,C_PROBE922_TYPE=0,C_PROBE921_TYPE=0,C_PROBE920_TYPE=0,C_PROBE919_TYPE=0,C_PROBE918_TYPE=0,C_PROBE917_TYPE=0,C_PROBE916_TYPE=0,C_PROBE915_TYPE=0,C_PROBE914_TYPE=0,C_PROBE913_TYPE=0,C_PROBE912_TYPE=0,C_PROBE911_TYPE=0,C_PROBE910_TYPE=0,C_PROBE909_TYPE=0,C_PROBE908_TYPE=0,C_PROBE907_TYPE=0,C_PROBE906_TYPE=0,C_PROBE905_TYPE=0,C_PROBE904_TYPE=0,C_PROBE903_TYPE=0,C_PROBE902_TYPE=0,C_PROBE901_TYPE=0,C_PROBE900_TYPE=0,C_PROBE8" & 
+"99_TYPE=0,C_PROBE898_TYPE=0,C_PROBE897_TYPE=0,C_PROBE896_TYPE=0,C_PROBE895_TYPE=0,C_PROBE894_TYPE=0,C_PROBE893_TYPE=0,C_PROBE892_TYPE=0,C_PROBE891_TYPE=0,C_PROBE890_TYPE=0,C_PROBE889_TYPE=0,C_PROBE888_TYPE=0,C_PROBE887_TYPE=0,C_PROBE886_TYPE=0,C_PROBE885_TYPE=0,C_PROBE884_TYPE=0,C_PROBE883_TYPE=0,C_PROBE882_TYPE=0,C_PROBE881_TYPE=0,C_PROBE880_TYPE=0,C_PROBE879_TYPE=0,C_PROBE878_TYPE=0,C_PROBE877_TYPE=0,C_PROBE876_TYPE=0,C_PROBE875_TYPE=0,C_PROBE874_TYPE=0,C_PROBE873_TYPE=0,C_PROBE872_TYPE=0,C_PR" & 
+"OBE871_TYPE=0,C_PROBE870_TYPE=0,C_PROBE869_TYPE=0,C_PROBE868_TYPE=0,C_PROBE867_TYPE=0,C_PROBE866_TYPE=0,C_PROBE865_TYPE=0,C_PROBE864_TYPE=0,C_PROBE863_TYPE=0,C_PROBE862_TYPE=0,C_PROBE861_TYPE=0,C_PROBE860_TYPE=0,C_PROBE859_TYPE=0,C_PROBE858_TYPE=0,C_PROBE857_TYPE=0,C_PROBE856_TYPE=0,C_PROBE855_TYPE=0,C_PROBE854_TYPE=0,C_PROBE853_TYPE=0,C_PROBE852_TYPE=0,C_PROBE851_TYPE=0,C_PROBE850_TYPE=0,C_PROBE849_TYPE=0,C_PROBE848_TYPE=0,C_PROBE847_TYPE=0,C_PROBE846_TYPE=0,C_PROBE845_TYPE=0,C_PROBE844_TYPE=0," & 
+"C_PROBE843_TYPE=0,C_PROBE842_TYPE=0,C_PROBE841_TYPE=0,C_PROBE840_TYPE=0,C_PROBE839_TYPE=0,C_PROBE838_TYPE=0,C_PROBE837_TYPE=0,C_PROBE836_TYPE=0,C_PROBE835_TYPE=0,C_PROBE834_TYPE=0,C_PROBE833_TYPE=0,C_PROBE832_TYPE=0,C_PROBE831_TYPE=0,C_PROBE830_TYPE=0,C_PROBE829_TYPE=0,C_PROBE828_TYPE=0,C_PROBE827_TYPE=0,C_PROBE826_TYPE=0,C_PROBE825_TYPE=0,C_PROBE824_TYPE=0,C_PROBE823_TYPE=0,C_PROBE822_TYPE=0,C_PROBE821_TYPE=0,C_PROBE820_TYPE=0,C_PROBE819_TYPE=0,C_PROBE818_TYPE=0,C_PROBE817_TYPE=0,C_PROBE816_TYP" & 
+"E=0,C_PROBE815_TYPE=0,C_PROBE814_TYPE=0,C_PROBE813_TYPE=0,C_PROBE812_TYPE=0,C_PROBE811_TYPE=0,C_PROBE810_TYPE=0,C_PROBE809_TYPE=0,C_PROBE808_TYPE=0,C_PROBE807_TYPE=0,C_PROBE806_TYPE=0,C_PROBE805_TYPE=0,C_PROBE804_TYPE=0,C_PROBE803_TYPE=0,C_PROBE802_TYPE=0,C_PROBE801_TYPE=0,C_PROBE800_TYPE=0,C_PROBE799_TYPE=0,C_PROBE798_TYPE=0,C_PROBE797_TYPE=0,C_PROBE796_TYPE=0,C_PROBE795_TYPE=0,C_PROBE794_TYPE=0,C_PROBE793_TYPE=0,C_PROBE792_TYPE=0,C_PROBE791_TYPE=0,C_PROBE790_TYPE=0,C_PROBE789_TYPE=0,C_PROBE788" & 
+"_TYPE=0,C_PROBE787_TYPE=0,C_PROBE786_TYPE=0,C_PROBE785_TYPE=0,C_PROBE784_TYPE=0,C_PROBE783_TYPE=0,C_PROBE782_TYPE=0,C_PROBE781_TYPE=0,C_PROBE780_TYPE=0,C_PROBE779_TYPE=0,C_PROBE778_TYPE=0,C_PROBE777_TYPE=0,C_PROBE776_TYPE=0,C_PROBE775_TYPE=0,C_PROBE774_TYPE=0,C_PROBE773_TYPE=0,C_PROBE772_TYPE=0,C_PROBE771_TYPE=0,C_PROBE770_TYPE=0,C_PROBE769_TYPE=0,C_PROBE768_TYPE=0,C_PROBE767_TYPE=0,C_PROBE766_TYPE=0,C_PROBE765_TYPE=0,C_PROBE764_TYPE=0,C_PROBE763_TYPE=0,C_PROBE762_TYPE=0,C_PROBE761_TYPE=0,C_PROB" & 
+"E760_TYPE=0,C_PROBE759_TYPE=0,C_PROBE758_TYPE=0,C_PROBE757_TYPE=0,C_PROBE756_TYPE=0,C_PROBE755_TYPE=0,C_PROBE754_TYPE=0,C_PROBE753_TYPE=0,C_PROBE752_TYPE=0,C_PROBE751_TYPE=0,C_PROBE750_TYPE=0,C_PROBE749_TYPE=0,C_PROBE748_TYPE=0,C_PROBE747_TYPE=0,C_PROBE746_TYPE=0,C_PROBE745_TYPE=0,C_PROBE744_TYPE=0,C_PROBE743_TYPE=0,C_PROBE742_TYPE=0,C_PROBE741_TYPE=0,C_PROBE740_TYPE=0,C_PROBE739_TYPE=0,C_PROBE738_TYPE=0,C_PROBE737_TYPE=0,C_PROBE736_TYPE=0,C_PROBE735_TYPE=0,C_PROBE734_TYPE=0,C_PROBE733_TYPE=0,C_" & 
+"PROBE732_TYPE=0,C_PROBE731_TYPE=0,C_PROBE730_TYPE=0,C_PROBE729_TYPE=0,C_PROBE728_TYPE=0,C_PROBE727_TYPE=0,C_PROBE726_TYPE=0,C_PROBE725_TYPE=0,C_PROBE724_TYPE=0,C_PROBE723_TYPE=0,C_PROBE722_TYPE=0,C_PROBE721_TYPE=0,C_PROBE720_TYPE=0,C_PROBE719_TYPE=0,C_PROBE718_TYPE=0,C_PROBE717_TYPE=0,C_PROBE716_TYPE=0,C_PROBE715_TYPE=0,C_PROBE714_TYPE=0,C_PROBE713_TYPE=0,C_PROBE712_TYPE=0,C_PROBE711_TYPE=0,C_PROBE710_TYPE=0,C_PROBE709_TYPE=0,C_PROBE708_TYPE=0,C_PROBE707_TYPE=0,C_PROBE706_TYPE=0,C_PROBE705_TYPE=" & 
+"0,C_PROBE704_TYPE=0,C_PROBE703_TYPE=0,C_PROBE702_TYPE=0,C_PROBE701_TYPE=0,C_PROBE700_TYPE=0,C_PROBE699_TYPE=0,C_PROBE698_TYPE=0,C_PROBE697_TYPE=0,C_PROBE696_TYPE=0,C_PROBE695_TYPE=0,C_PROBE694_TYPE=0,C_PROBE693_TYPE=0,C_PROBE692_TYPE=0,C_PROBE691_TYPE=0,C_PROBE690_TYPE=0,C_PROBE689_TYPE=0,C_PROBE688_TYPE=0,C_PROBE687_TYPE=0,C_PROBE686_TYPE=0,C_PROBE685_TYPE=0,C_PROBE684_TYPE=0,C_PROBE683_TYPE=0,C_PROBE682_TYPE=0,C_PROBE681_TYPE=0,C_PROBE680_TYPE=0,C_PROBE679_TYPE=0,C_PROBE678_TYPE=0,C_PROBE677_T" & 
+"YPE=0,C_PROBE676_TYPE=0,C_PROBE675_TYPE=0,C_PROBE674_TYPE=0,C_PROBE673_TYPE=0,C_PROBE672_TYPE=0,C_PROBE671_TYPE=0,C_PROBE670_TYPE=0,C_PROBE669_TYPE=0,C_PROBE668_TYPE=0,C_PROBE667_TYPE=0,C_PROBE666_TYPE=0,C_PROBE665_TYPE=0,C_PROBE664_TYPE=0,C_PROBE663_TYPE=0,C_PROBE662_TYPE=0,C_PROBE661_TYPE=0,C_PROBE660_TYPE=0,C_PROBE659_TYPE=0,C_PROBE658_TYPE=0,C_PROBE657_TYPE=0,C_PROBE656_TYPE=0,C_PROBE655_TYPE=0,C_PROBE654_TYPE=0,C_PROBE653_TYPE=0,C_PROBE652_TYPE=0,C_PROBE651_TYPE=0,C_PROBE650_TYPE=0,C_PROBE6" & 
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+"OBE213_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE187" & 
+"_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE161_WIDTH" & 
+"=1,C_PROBE160_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE154_WIDTH=1,C_PROBE153_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE135_WIDTH=1,C_P" & 
+"ROBE134_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE10" & 
+"8_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE81_WIDT" & 
+"H=1,C_PROBE80_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE53_WIDTH=1,C_PROBE52_" & 
+"WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE25_WIDTH=1,C_PROB" & 
+"E24_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE0_WIDTH=1,C_DATA_DEPTH=16384,C_NUM_OF_PROBES=1,C_XLNX_HW_PROBE_INFO=DEFAULT," & 
+"Component_Name=design_1_system_ila_0_0,C_PROBE70_WIDTH=1,C_TRIGOUT_EN=false,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,C_DDR_CLK_GEN=FALSE,C_EN_DDR_ILA=FALSE,C_ADV_TRIGGER=FALSE,C_PROBE1023_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1008" & 
+"_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE984_MU_CNT=1,C_" & 
+"PROBE983_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE959_MU_CNT=1,C_" & 
+"PROBE958_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE934_MU_CNT=1,C_" & 
+"PROBE933_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE909_MU_CNT=1,C_" & 
+"PROBE908_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE884_MU_CNT=1,C_" & 
+"PROBE883_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE859_MU_CNT=1,C_" & 
+"PROBE858_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE834_MU_CNT=1,C_" & 
+"PROBE833_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE809_MU_CNT=1,C_" & 
+"PROBE808_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE784_MU_CNT=1,C_" & 
+"PROBE783_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE759_MU_CNT=1,C_" & 
+"PROBE758_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE734_MU_CNT=1,C_" & 
+"PROBE733_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE709_MU_CNT=1,C_" & 
+"PROBE708_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE684_MU_CNT=1,C_" & 
+"PROBE683_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE659_MU_CNT=1,C_" & 
+"PROBE658_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE634_MU_CNT=1,C_" & 
+"PROBE633_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE609_MU_CNT=1,C_" & 
+"PROBE608_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE584_MU_CNT=1,C_" & 
+"PROBE583_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE559_MU_CNT=1,C_" & 
+"PROBE558_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE534_MU_CNT=1,C_" & 
+"PROBE533_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE509_MU_CNT=1,C_" & 
+"PROBE508_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE484_MU_CNT=1,C_" & 
+"PROBE483_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE459_MU_CNT=1,C_" & 
+"PROBE458_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE434_MU_CNT=1,C_" & 
+"PROBE433_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE409_MU_CNT=1,C_" & 
+"PROBE408_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE384_MU_CNT=1,C_" & 
+"PROBE383_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE359_MU_CNT=1,C_" & 
+"PROBE358_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE334_MU_CNT=1,C_" & 
+"PROBE333_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE309_MU_CNT=1,C_" & 
+"PROBE308_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE284_MU_CNT=1,C_" & 
+"PROBE283_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE259_MU_CNT=1,C_" & 
+"PROBE258_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE234_MU_CNT=1,C_" & 
+"PROBE233_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE209_MU_CNT=1,C_" & 
+"PROBE208_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE184_MU_CNT=1,C_" & 
+"PROBE183_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE159_MU_CNT=1,C_" & 
+"PROBE158_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE134_MU_CNT=1,C_" & 
+"PROBE133_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE109_MU_CNT=1,C_" & 
+"PROBE108_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE83_MU_CNT=1" & 
+",C_PROBE82_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PRO" & 
+"BE56_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE30_M" & 
+"U_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PR" & 
+"OBE3_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE0_MU_CNT=1,C_TRIGIN_EN=false,EN_BRAM_DRC=TRUE,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_NUM_MONITOR_SLOTS=3,C_SLOT_0_AXI_ARUSER_WIDTH=1,C_SLOT_0_AXI_RUSER_WIDTH=1,C_SLOT_0_AXI_AWUSER_WIDTH=1,C_SLOT_0_AXI_WUSER_WIDTH=1,C_SLOT_0_AXI_BUSER_WIDTH=1,C_SLOT_0_AXI_ID_WIDTH=AUTO,C_SLOT_0_AXI_DATA_WIDTH=AUTO,C_SLOT_0_AXI_ADDR_WIDTH=AUTO,C_SLOT_0_AXI_PROTOCOL=AXI4,C_SLOT_0_AXIS_TDATA_WIDTH=AUTO,C_SLOT_0_AXIS_TID_WIDTH=AUTO,C_SLOT_0_AXIS_TUSER" & 
+"_WIDTH=AUTO,C_SLOT_0_AXIS_TDEST_WIDTH=AUTO,C_SLOT_1_AXI_ARUSER_WIDTH=1,C_SLOT_1_AXI_RUSER_WIDTH=1,C_SLOT_1_AXI_AWUSER_WIDTH=1,C_SLOT_1_AXI_WUSER_WIDTH=1,C_SLOT_1_AXI_BUSER_WIDTH=1,C_SLOT_1_AXI_ID_WIDTH=AUTO,C_SLOT_1_AXI_DATA_WIDTH=AUTO,C_SLOT_1_AXI_ADDR_WIDTH=AUTO,C_SLOT_1_AXI_PROTOCOL=AXI4,C_SLOT_1_AXIS_TDATA_WIDTH=AUTO,C_SLOT_1_AXIS_TID_WIDTH=AUTO,C_SLOT_1_AXIS_TUSER_WIDTH=AUTO,C_SLOT_1_AXIS_TDEST_WIDTH=AUTO,C_SLOT_0_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_1_INTF_TYPE=xilinx.com_in" & 
+"terface_axis_rtl_1.0,C_SLOT_2_INTF_TYPE=xilinx.com_interface_axis_rtl_1.0,C_SLOT_3_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_4_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_5_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_6_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_7_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_8_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_9_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_10_INTF_TYPE=xilinx.com_interface_aximm_r" & 
+"tl_1.0,C_SLOT_11_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_12_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_13_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_14_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_15_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_MON_TYPE=INTERFACE,C_SLOT_2_AXI_ARUSER_WIDTH=1,C_SLOT_2_AXI_RUSER_WIDTH=1,C_SLOT_2_AXI_AWUSER_WIDTH=1,C_SLOT_2_AXI_WUSER_WIDTH=1,C_SLOT_2_AXI_BUSER_WIDTH=1,C_SLOT_2_AXI_ID_WIDTH=AUTO,C_SLOT_2_AXI_DATA_WIDTH=AUTO,C_SL" & 
+"OT_2_AXI_ADDR_WIDTH=AUTO,C_SLOT_2_AXI_PROTOCOL=AXI4,C_SLOT_2_AXIS_TDATA_WIDTH=AUTO,C_SLOT_2_AXIS_TID_WIDTH=AUTO,C_SLOT_2_AXIS_TUSER_WIDTH=AUTO,C_SLOT_2_AXIS_TDEST_WIDTH=AUTO,C_SLOT_3_AXI_ARUSER_WIDTH=1,C_SLOT_3_AXI_RUSER_WIDTH=1,C_SLOT_3_AXI_AWUSER_WIDTH=1,C_SLOT_3_AXI_WUSER_WIDTH=1,C_SLOT_3_AXI_BUSER_WIDTH=1,C_SLOT_3_AXI_ID_WIDTH=AUTO,C_SLOT_3_AXI_DATA_WIDTH=AUTO,C_SLOT_3_AXI_ADDR_WIDTH=AUTO,C_SLOT_3_AXI_PROTOCOL=AXI4,C_SLOT_3_AXIS_TDATA_WIDTH=AUTO,C_SLOT_3_AXIS_TID_WIDTH=AUTO,C_SLOT_3_AXIS_TUS" & 
+"ER_WIDTH=AUTO,C_SLOT_3_AXIS_TDEST_WIDTH=AUTO,C_SLOT_4_AXI_ARUSER_WIDTH=1,C_SLOT_4_AXI_RUSER_WIDTH=1,C_SLOT_4_AXI_AWUSER_WIDTH=1,C_SLOT_4_AXI_WUSER_WIDTH=1,C_SLOT_4_AXI_BUSER_WIDTH=1,C_SLOT_4_AXI_ID_WIDTH=AUTO,C_SLOT_4_AXI_DATA_WIDTH=AUTO,C_SLOT_4_AXI_ADDR_WIDTH=AUTO,C_SLOT_4_AXI_PROTOCOL=AXI4,C_SLOT_4_AXIS_TDATA_WIDTH=AUTO,C_SLOT_4_AXIS_TID_WIDTH=AUTO,C_SLOT_4_AXIS_TUSER_WIDTH=AUTO,C_SLOT_4_AXIS_TDEST_WIDTH=AUTO,C_SLOT_5_AXI_ARUSER_WIDTH=1,C_SLOT_5_AXI_RUSER_WIDTH=1,C_SLOT_5_AXI_AWUSER_WIDTH=1,C" & 
+"_SLOT_5_AXI_WUSER_WIDTH=1,C_SLOT_5_AXI_BUSER_WIDTH=1,C_SLOT_5_AXI_ID_WIDTH=AUTO,C_SLOT_5_AXI_DATA_WIDTH=AUTO,C_SLOT_5_AXI_ADDR_WIDTH=AUTO,C_SLOT_5_AXI_PROTOCOL=AXI4,C_SLOT_5_AXIS_TDATA_WIDTH=AUTO,C_SLOT_5_AXIS_TID_WIDTH=AUTO,C_SLOT_5_AXIS_TUSER_WIDTH=AUTO,C_SLOT_5_AXIS_TDEST_WIDTH=AUTO,C_SLOT_6_AXI_ARUSER_WIDTH=1,C_SLOT_6_AXI_RUSER_WIDTH=1,C_SLOT_6_AXI_AWUSER_WIDTH=1,C_SLOT_6_AXI_WUSER_WIDTH=1,C_SLOT_6_AXI_BUSER_WIDTH=1,C_SLOT_6_AXI_ID_WIDTH=AUTO,C_SLOT_6_AXI_DATA_WIDTH=AUTO,C_SLOT_6_AXI_ADDR_WI" & 
+"DTH=AUTO,C_SLOT_6_AXI_PROTOCOL=AXI4,C_SLOT_6_AXIS_TDATA_WIDTH=AUTO,C_SLOT_6_AXIS_TID_WIDTH=AUTO,C_SLOT_6_AXIS_TUSER_WIDTH=AUTO,C_SLOT_6_AXIS_TDEST_WIDTH=AUTO,C_SLOT_7_AXI_ARUSER_WIDTH=1,C_SLOT_7_AXI_RUSER_WIDTH=1,C_SLOT_7_AXI_AWUSER_WIDTH=1,C_SLOT_7_AXI_WUSER_WIDTH=1,C_SLOT_7_AXI_BUSER_WIDTH=1,C_SLOT_7_AXI_ID_WIDTH=AUTO,C_SLOT_7_AXI_DATA_WIDTH=AUTO,C_SLOT_7_AXI_ADDR_WIDTH=AUTO,C_SLOT_7_AXI_PROTOCOL=AXI4,C_SLOT_7_AXIS_TDATA_WIDTH=AUTO,C_SLOT_7_AXIS_TID_WIDTH=AUTO,C_SLOT_7_AXIS_TUSER_WIDTH=AUTO,C_" & 
+"SLOT_7_AXIS_TDEST_WIDTH=AUTO,C_SLOT_8_AXI_ARUSER_WIDTH=1,C_SLOT_8_AXI_RUSER_WIDTH=1,C_SLOT_8_AXI_AWUSER_WIDTH=1,C_SLOT_8_AXI_WUSER_WIDTH=1,C_SLOT_8_AXI_BUSER_WIDTH=1,C_SLOT_8_AXI_ID_WIDTH=AUTO,C_SLOT_8_AXI_DATA_WIDTH=AUTO,C_SLOT_8_AXI_ADDR_WIDTH=AUTO,C_SLOT_8_AXI_PROTOCOL=AXI4,C_SLOT_8_AXIS_TDATA_WIDTH=AUTO,C_SLOT_8_AXIS_TID_WIDTH=AUTO,C_SLOT_8_AXIS_TUSER_WIDTH=AUTO,C_SLOT_8_AXIS_TDEST_WIDTH=AUTO,C_SLOT_9_AXI_ARUSER_WIDTH=1,C_SLOT_9_AXI_RUSER_WIDTH=1,C_SLOT_9_AXI_AWUSER_WIDTH=1,C_SLOT_9_AXI_WUSE" & 
+"R_WIDTH=1,C_SLOT_9_AXI_BUSER_WIDTH=1,C_SLOT_9_AXI_ID_WIDTH=AUTO,C_SLOT_9_AXI_DATA_WIDTH=AUTO,C_SLOT_9_AXI_ADDR_WIDTH=AUTO,C_SLOT_9_AXI_PROTOCOL=AXI4,C_SLOT_9_AXIS_TDATA_WIDTH=AUTO,C_SLOT_9_AXIS_TID_WIDTH=AUTO,C_SLOT_9_AXIS_TUSER_WIDTH=AUTO,C_SLOT_9_AXIS_TDEST_WIDTH=AUTO,C_SLOT_10_AXI_ARUSER_WIDTH=1,C_SLOT_10_AXI_RUSER_WIDTH=1,C_SLOT_10_AXI_AWUSER_WIDTH=1,C_SLOT_10_AXI_WUSER_WIDTH=1,C_SLOT_10_AXI_BUSER_WIDTH=1,C_SLOT_10_AXI_ID_WIDTH=AUTO,C_SLOT_10_AXI_DATA_WIDTH=AUTO,C_SLOT_10_AXI_ADDR_WIDTH=AUTO" & 
+",C_SLOT_10_AXI_PROTOCOL=AXI4,C_SLOT_10_AXIS_TDATA_WIDTH=AUTO,C_SLOT_10_AXIS_TID_WIDTH=AUTO,C_SLOT_10_AXIS_TUSER_WIDTH=AUTO,C_SLOT_10_AXIS_TDEST_WIDTH=AUTO,C_SLOT_11_AXI_ARUSER_WIDTH=1,C_SLOT_11_AXI_RUSER_WIDTH=1,C_SLOT_11_AXI_AWUSER_WIDTH=1,C_SLOT_11_AXI_WUSER_WIDTH=1,C_SLOT_11_AXI_BUSER_WIDTH=1,C_SLOT_11_AXI_ID_WIDTH=AUTO,C_SLOT_11_AXI_DATA_WIDTH=AUTO,C_SLOT_11_AXI_ADDR_WIDTH=AUTO,C_SLOT_11_AXI_PROTOCOL=AXI4,C_SLOT_11_AXIS_TDATA_WIDTH=AUTO,C_SLOT_11_AXIS_TID_WIDTH=AUTO,C_SLOT_11_AXIS_TUSER_WIDT" & 
+"H=AUTO,C_SLOT_11_AXIS_TDEST_WIDTH=AUTO,C_SLOT_12_AXI_ARUSER_WIDTH=1,C_SLOT_12_AXI_RUSER_WIDTH=1,C_SLOT_12_AXI_AWUSER_WIDTH=1,C_SLOT_12_AXI_WUSER_WIDTH=1,C_SLOT_12_AXI_BUSER_WIDTH=1,C_SLOT_12_AXI_ID_WIDTH=AUTO,C_SLOT_12_AXI_DATA_WIDTH=AUTO,C_SLOT_12_AXI_ADDR_WIDTH=AUTO,C_SLOT_12_AXI_PROTOCOL=AXI4,C_SLOT_12_AXIS_TDATA_WIDTH=AUTO,C_SLOT_12_AXIS_TID_WIDTH=AUTO,C_SLOT_12_AXIS_TUSER_WIDTH=AUTO,C_SLOT_12_AXIS_TDEST_WIDTH=AUTO,C_SLOT_13_AXI_ARUSER_WIDTH=1,C_SLOT_13_AXI_RUSER_WIDTH=1,C_SLOT_13_AXI_AWUSER" & 
+"_WIDTH=1,C_SLOT_13_AXI_WUSER_WIDTH=1,C_SLOT_13_AXI_BUSER_WIDTH=1,C_SLOT_13_AXI_ID_WIDTH=AUTO,C_SLOT_13_AXI_DATA_WIDTH=AUTO,C_SLOT_13_AXI_ADDR_WIDTH=AUTO,C_SLOT_13_AXI_PROTOCOL=AXI4,C_SLOT_13_AXIS_TDATA_WIDTH=AUTO,C_SLOT_13_AXIS_TID_WIDTH=AUTO,C_SLOT_13_AXIS_TUSER_WIDTH=AUTO,C_SLOT_13_AXIS_TDEST_WIDTH=AUTO,C_SLOT_14_AXI_ARUSER_WIDTH=1,C_SLOT_14_AXI_RUSER_WIDTH=1,C_SLOT_14_AXI_AWUSER_WIDTH=1,C_SLOT_14_AXI_WUSER_WIDTH=1,C_SLOT_14_AXI_BUSER_WIDTH=1,C_SLOT_14_AXI_ID_WIDTH=AUTO,C_SLOT_14_AXI_DATA_WIDT" & 
+"H=AUTO,C_SLOT_14_AXI_ADDR_WIDTH=AUTO,C_SLOT_14_AXI_PROTOCOL=AXI4,C_SLOT_14_AXIS_TDATA_WIDTH=AUTO,C_SLOT_14_AXIS_TID_WIDTH=AUTO,C_SLOT_14_AXIS_TUSER_WIDTH=AUTO,C_SLOT_14_AXIS_TDEST_WIDTH=AUTO,C_SLOT_15_AXI_ARUSER_WIDTH=1,C_SLOT_15_AXI_RUSER_WIDTH=1,C_SLOT_15_AXI_AWUSER_WIDTH=1,C_SLOT_15_AXI_WUSER_WIDTH=1,C_SLOT_15_AXI_BUSER_WIDTH=1,C_SLOT_15_AXI_ID_WIDTH=AUTO,C_SLOT_15_AXI_DATA_WIDTH=AUTO,C_SLOT_15_AXI_ADDR_WIDTH=AUTO,C_SLOT_15_AXI_PROTOCOL=AXI4,C_SLOT_15_AXIS_TDATA_WIDTH=AUTO,C_SLOT_15_AXIS_TID_" & 
+"WIDTH=AUTO,C_SLOT_15_AXIS_TUSER_WIDTH=AUTO,C_SLOT_15_AXIS_TDEST_WIDTH=AUTO,C_PROBE_WIDTH_PROPAGATION=AUTO}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_0_AXI_awaddr: SIGNAL IS "XIL_INTERFACENAME SLOT_0_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, R" & 
+"USER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_1_AXIS_tdata: SIGNAL IS "XIL_INTERFACENAME SLOT_1_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_2_AXIS_tdata: SIGNAL IS "XIL_INTERFACENAME SLOT_2_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS, ASSOCIATED_RESET resetn, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.clk CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME RST.resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.resetn RST";
+BEGIN
+  U0 : bd_f60c
+    PORT MAP (
+      clk => clk,
+      SLOT_0_AXI_awaddr => SLOT_0_AXI_awaddr,
+      SLOT_0_AXI_awprot => SLOT_0_AXI_awprot,
+      SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
+      SLOT_0_AXI_awready => SLOT_0_AXI_awready,
+      SLOT_0_AXI_wdata => SLOT_0_AXI_wdata,
+      SLOT_0_AXI_wstrb => SLOT_0_AXI_wstrb,
+      SLOT_0_AXI_wvalid => SLOT_0_AXI_wvalid,
+      SLOT_0_AXI_wready => SLOT_0_AXI_wready,
+      SLOT_0_AXI_bresp => SLOT_0_AXI_bresp,
+      SLOT_0_AXI_bvalid => SLOT_0_AXI_bvalid,
+      SLOT_0_AXI_bready => SLOT_0_AXI_bready,
+      SLOT_0_AXI_araddr => SLOT_0_AXI_araddr,
+      SLOT_0_AXI_arprot => SLOT_0_AXI_arprot,
+      SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
+      SLOT_0_AXI_arready => SLOT_0_AXI_arready,
+      SLOT_0_AXI_rdata => SLOT_0_AXI_rdata,
+      SLOT_0_AXI_rresp => SLOT_0_AXI_rresp,
+      SLOT_0_AXI_rvalid => SLOT_0_AXI_rvalid,
+      SLOT_0_AXI_rready => SLOT_0_AXI_rready,
+      SLOT_1_AXIS_tdata => SLOT_1_AXIS_tdata,
+      SLOT_1_AXIS_tlast => SLOT_1_AXIS_tlast,
+      SLOT_1_AXIS_tvalid => SLOT_1_AXIS_tvalid,
+      SLOT_1_AXIS_tready => SLOT_1_AXIS_tready,
+      SLOT_2_AXIS_tdata => SLOT_2_AXIS_tdata,
+      SLOT_2_AXIS_tlast => SLOT_2_AXIS_tlast,
+      SLOT_2_AXIS_tvalid => SLOT_2_AXIS_tvalid,
+      SLOT_2_AXIS_tready => SLOT_2_AXIS_tready,
+      resetn => resetn
+    );
+END design_1_system_ila_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/constrs_1/new/zybo_audio.xdc

@@ -0,0 +1 @@
+create_clock -period 8.00 [get_ports clk ];

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.v

@@ -0,0 +1,43 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Tue Nov 26 15:16:46 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.v
+// Design      : design_1_zybo_audio_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "zybo_audio,Vivado 2023.1" *)
+module design_1_zybo_audio_0_0(clk, axis_pb_data, axis_pb_valid, 
+  axis_pb_ready, axis_rec_data, axis_rec_valid, axis_rec_ready, mute, mclk, bclk, pb_dat, pb_lrc, 
+  rec_dat, rec_lrc, scl_i, scl_o, scl_t, sda_i, sda_o, sda_t)
+/* synthesis syn_black_box black_box_pad_pin="axis_pb_data[31:0],axis_pb_valid,axis_pb_ready,axis_rec_data[31:0],axis_rec_valid,axis_rec_ready,mute,mclk,bclk,pb_dat,pb_lrc,rec_dat,rec_lrc,scl_i,scl_o,scl_t,sda_i,sda_o,sda_t" */
+/* synthesis syn_force_seq_prim="clk" */;
+  input clk /* synthesis syn_isclock = 1 */;
+  input [31:0]axis_pb_data;
+  input axis_pb_valid;
+  output axis_pb_ready;
+  output [31:0]axis_rec_data;
+  output axis_rec_valid;
+  input axis_rec_ready;
+  output mute;
+  output mclk;
+  output bclk;
+  output pb_dat;
+  output pb_lrc;
+  input rec_dat;
+  output rec_lrc;
+  input scl_i;
+  output scl_o;
+  output scl_t;
+  input sda_i;
+  output sda_o;
+  output sda_t;
+endmodule

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/sim/design_1_zybo_audio_0_0.vhd

@@ -0,0 +1,166 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:zybo_audio:1.0
+-- IP Revision: 22
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_zybo_audio_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    axis_pb_valid : IN STD_LOGIC;
+    axis_pb_ready : OUT STD_LOGIC;
+    axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    axis_rec_valid : OUT STD_LOGIC;
+    axis_rec_ready : IN STD_LOGIC;
+    mute : OUT STD_LOGIC;
+    mclk : OUT STD_LOGIC;
+    bclk : OUT STD_LOGIC;
+    pb_dat : OUT STD_LOGIC;
+    pb_lrc : OUT STD_LOGIC;
+    rec_dat : IN STD_LOGIC;
+    rec_lrc : OUT STD_LOGIC;
+    scl_i : IN STD_LOGIC;
+    scl_o : OUT STD_LOGIC;
+    scl_t : OUT STD_LOGIC;
+    sda_i : IN STD_LOGIC;
+    sda_o : OUT STD_LOGIC;
+    sda_t : OUT STD_LOGIC
+  );
+END design_1_zybo_audio_0_0;
+
+ARCHITECTURE design_1_zybo_audio_0_0_arch OF design_1_zybo_audio_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT zybo_audio IS
+    GENERIC (
+      MIC_IN : INTEGER;
+      I2C_CLKDIV : INTEGER;
+      I2S_CLKDIV : INTEGER;
+      HAS_RESET_PIN : BOOLEAN;
+      SRR_70 : STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      resetn : IN STD_LOGIC;
+      axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      axis_pb_valid : IN STD_LOGIC;
+      axis_pb_ready : OUT STD_LOGIC;
+      axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      axis_rec_valid : OUT STD_LOGIC;
+      axis_rec_ready : IN STD_LOGIC;
+      mute : OUT STD_LOGIC;
+      mclk : OUT STD_LOGIC;
+      bclk : OUT STD_LOGIC;
+      pb_dat : OUT STD_LOGIC;
+      pb_lrc : OUT STD_LOGIC;
+      rec_dat : IN STD_LOGIC;
+      rec_lrc : OUT STD_LOGIC;
+      scl_i : IN STD_LOGIC;
+      scl_o : OUT STD_LOGIC;
+      scl_t : OUT STD_LOGIC;
+      sda_i : IN STD_LOGIC;
+      sda_o : OUT STD_LOGIC;
+      sda_t : OUT STD_LOGIC
+    );
+  END COMPONENT zybo_audio;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF axis_pb_data: SIGNAL IS "XIL_INTERFACENAME axis_pb, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_pb_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_pb_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_pb_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF axis_rec_data: SIGNAL IS "XIL_INTERFACENAME axis_rec, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_rec_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_rec_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_rec_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, ASSOCIATED_BUSIF axis_rec:axis_pb, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_I";
+  ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_O";
+  ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_T";
+  ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_I";
+  ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_O";
+  ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_T";
+BEGIN
+  U0 : zybo_audio
+    GENERIC MAP (
+      MIC_IN => 0,
+      I2C_CLKDIV => 9999,
+      I2S_CLKDIV => 4,
+      HAS_RESET_PIN => false,
+      SRR_70 => B"00000000"
+    )
+    PORT MAP (
+      clk => clk,
+      resetn => '1',
+      axis_pb_data => axis_pb_data,
+      axis_pb_valid => axis_pb_valid,
+      axis_pb_ready => axis_pb_ready,
+      axis_rec_data => axis_rec_data,
+      axis_rec_valid => axis_rec_valid,
+      axis_rec_ready => axis_rec_ready,
+      mute => mute,
+      mclk => mclk,
+      bclk => bclk,
+      pb_dat => pb_dat,
+      pb_lrc => pb_lrc,
+      rec_dat => rec_dat,
+      rec_lrc => rec_lrc,
+      scl_i => scl_i,
+      scl_o => scl_o,
+      scl_t => scl_t,
+      sda_i => sda_i,
+      sda_o => sda_o,
+      sda_t => sda_t
+    );
+END design_1_zybo_audio_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/synth/design_1_zybo_audio_0_0.vhd

@@ -0,0 +1,174 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:zybo_audio:1.0
+-- IP Revision: 22
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_zybo_audio_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    axis_pb_valid : IN STD_LOGIC;
+    axis_pb_ready : OUT STD_LOGIC;
+    axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    axis_rec_valid : OUT STD_LOGIC;
+    axis_rec_ready : IN STD_LOGIC;
+    mute : OUT STD_LOGIC;
+    mclk : OUT STD_LOGIC;
+    bclk : OUT STD_LOGIC;
+    pb_dat : OUT STD_LOGIC;
+    pb_lrc : OUT STD_LOGIC;
+    rec_dat : IN STD_LOGIC;
+    rec_lrc : OUT STD_LOGIC;
+    scl_i : IN STD_LOGIC;
+    scl_o : OUT STD_LOGIC;
+    scl_t : OUT STD_LOGIC;
+    sda_i : IN STD_LOGIC;
+    sda_o : OUT STD_LOGIC;
+    sda_t : OUT STD_LOGIC
+  );
+END design_1_zybo_audio_0_0;
+
+ARCHITECTURE design_1_zybo_audio_0_0_arch OF design_1_zybo_audio_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT zybo_audio IS
+    GENERIC (
+      MIC_IN : INTEGER;
+      I2C_CLKDIV : INTEGER;
+      I2S_CLKDIV : INTEGER;
+      HAS_RESET_PIN : BOOLEAN;
+      SRR_70 : STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      resetn : IN STD_LOGIC;
+      axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      axis_pb_valid : IN STD_LOGIC;
+      axis_pb_ready : OUT STD_LOGIC;
+      axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      axis_rec_valid : OUT STD_LOGIC;
+      axis_rec_ready : IN STD_LOGIC;
+      mute : OUT STD_LOGIC;
+      mclk : OUT STD_LOGIC;
+      bclk : OUT STD_LOGIC;
+      pb_dat : OUT STD_LOGIC;
+      pb_lrc : OUT STD_LOGIC;
+      rec_dat : IN STD_LOGIC;
+      rec_lrc : OUT STD_LOGIC;
+      scl_i : IN STD_LOGIC;
+      scl_o : OUT STD_LOGIC;
+      scl_t : OUT STD_LOGIC;
+      sda_i : IN STD_LOGIC;
+      sda_o : OUT STD_LOGIC;
+      sda_t : OUT STD_LOGIC
+    );
+  END COMPONENT zybo_audio;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "zybo_audio,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_zybo_audio_0_0_arch : ARCHITECTURE IS "design_1_zybo_audio_0_0,zybo_audio,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "design_1_zybo_audio_0_0,zybo_audio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zybo_audio,x_ipVersion=1.0,x_ipCoreRevision=22,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,MIC_IN=0,I2C_CLKDIV=9999,I2S_CLKDIV=4,HAS_RESET_PIN=false,SRR_70=00000000}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "package_project";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF axis_pb_data: SIGNAL IS "XIL_INTERFACENAME axis_pb, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_pb_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_pb_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_pb_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF axis_rec_data: SIGNAL IS "XIL_INTERFACENAME axis_rec, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_rec_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_rec_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF axis_rec_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, ASSOCIATED_BUSIF axis_rec:axis_pb, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_I";
+  ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_O";
+  ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_T";
+  ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_I";
+  ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_O";
+  ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_T";
+BEGIN
+  U0 : zybo_audio
+    GENERIC MAP (
+      MIC_IN => 0,
+      I2C_CLKDIV => 9999,
+      I2S_CLKDIV => 4,
+      HAS_RESET_PIN => false,
+      SRR_70 => B"00000000"
+    )
+    PORT MAP (
+      clk => clk,
+      resetn => '1',
+      axis_pb_data => axis_pb_data,
+      axis_pb_valid => axis_pb_valid,
+      axis_pb_ready => axis_pb_ready,
+      axis_rec_data => axis_rec_data,
+      axis_rec_valid => axis_rec_valid,
+      axis_rec_ready => axis_rec_ready,
+      mute => mute,
+      mclk => mclk,
+      bclk => bclk,
+      pb_dat => pb_dat,
+      pb_lrc => pb_lrc,
+      rec_dat => rec_dat,
+      rec_lrc => rec_lrc,
+      scl_i => scl_i,
+      scl_o => scl_o,
+      scl_t => scl_t,
+      sda_i => sda_i,
+      sda_o => sda_o,
+      sda_t => sda_t
+    );
+END design_1_zybo_audio_0_0_arch;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/122e/hdl/xsdbs_v1_0_vl_rfs.v

@@ -0,0 +1,552 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+IYB6YMUpLRG67Sjv6mvLa0lJDa9M83l3pszRl7mNKDbm3JQq1xub6O3MDaxf4WUUoRlbj6UmK+ls
+5TT1rZBI42slY2M8d8G/12u9ZwNU0B9Ysw0A9f7H2/gZw+bCFVT2XOufXRtM8469/cgTzPdX6455
+eehGCOlFNzztUpCCBuo=
+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+a/7EQ8W4oMyysM5YxqT496V07EUaiHtsiTeMr+xwggjSXDgZBxdH9zS0ZwSbWGNiHwg8nXSCMzIT
+bUcHpdhYenBbvS6lFHc+OYja/GxpeotPfuhlGtbxN3fXZjw43NjXQI/ojWzEeo5ATyxr94HJ8sHD
+JA1CsMdglOQT6QZiD9TVY3RkvJVUxzXGEK/4umSz/Fc5dPh6gxxp7cVofeuJ+snpie5VVQQJoj4j
+tjyBNmGrIhr0Y0IV+3TgWooJ+r24u/VBLLE6lnzKxh0zYnJ5zUjs4eHuQTqInalvOAdYvbUSVqio
+Lzp5Bj6tb7kmD+A/qe86yLb4GbJzLTehOjcfdg==
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+Bm8/8qhHbJitBA3cG0BWpho8+cHGNcXoWDJOit3rZ1HeeUrKdPeoNkL9hkzhf9ZUHxLpbdTUCjkz
+uhVRU8UTRMdIPDzL/7HSIQXCDLdOz1nxeYLnDxwllTKxlZ4aRFdGbB0RXQ/iZNRQW2EmaDTFRcRV
+v0IjKU+PjNN3ZYIXCkA=
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+bOGsLKO2Wjd3RNfQsUHtM5NcPLVbC6ZCRWCjSRRmyvuNhRjavSsIHbXkxLZHDjZnlnBuHdEZ8oea
+UHHfvapGkuZI0S7deY4irowm1O51aMUIiyYUNQJCaEgTDbqwyEsnkylKzYrQzRU/JO8aErpyMDc+
+dxDZeGYfZaF3iUzWGpDyEDaQh7d/AMIR890b/cRJ0JPD6S/d68REfiAIau8ZUsXiSCgHP9ot5Why
+yUKZOeml+FbZ2/zqywrRRADVaEpoSqu6cZux0zJFUOfKwG3rO6e2WYwBKucJSM1O+MXqHqUBqEfl
+IHl8aYzdxpc89jXiMIYfoqN06f8LwbIAKe3Z+w==
+
+`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+xyJ+44oGcnu3f/PRr5Q/pt05L20B492JqgiTtcs5oGrsK7nBtr3Jek5JEMvW6gatRMUMnyBEipiF
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+
+`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Synplicity", key_keyname = "SYNP15_1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-PREC-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25472)
+`pragma protect data_block
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+`pragma protect end_protected

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/4738/sources_1/new/axis_audio_mono2stereo.vhd

@@ -0,0 +1,51 @@
+--------------------------------------------------------------------------
+--
+-- AXI Stream Audio Mono to Stereo
+--
+-- Prof. Dr.-Ing. W. Gehrke (c) 2020
+--
+--------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity axis_audio_mono2stereo is
+    generic
+    (
+        HAS_LAST         : boolean     := false
+    );
+    port
+    (
+        AXIS_ACLK               : in  std_logic;
+
+        -- AXI Streaming Target Port
+        S_AXIS_TVALID           : in  std_logic;
+        S_AXIS_TDATA            : in  std_logic_vector(15 downto 0);
+        S_AXIS_TLAST            : in  std_logic := '0';
+        S_AXIS_TREADY           : out std_logic;
+
+        -- AXI Streaming Initiator Port
+        M_AXIS_TVALID           : out std_logic;
+        M_AXIS_TDATA            : out std_logic_vector(31 downto 0);
+        M_AXIS_TLAST            : out std_logic;
+        M_AXIS_TREADY           : in  std_logic
+    );  
+end;
+
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+
+architecture rtl of axis_audio_mono2stereo is
+     
+begin
+
+    S_AXIS_TREADY <= M_AXIS_TREADY;
+    M_AXIS_TVALID <= S_AXIS_TVALID;
+    M_AXIS_TLAST  <= S_AXIS_TLAST;
+    
+    M_AXIS_TDATA (31 downto 16) <= S_AXIS_TDATA;
+    M_AXIS_TDATA (15 downto  0) <= S_AXIS_TDATA;
+        
+end;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/6d0b/sources_1/new/i2c_transmitter.vhd

@@ -0,0 +1,147 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity i2c_transmitter is
+    generic(
+        AW          : positive := 8;
+        I2C_CLKDIV  : positive := 9999
+    );	                    
+    
+    port ( 
+        clk          : in  std_logic;
+        resetn       : in  std_logic;
+        data         : in  std_logic_vector (  11 downto 0);
+        addr         : out std_logic_vector (AW-1 downto 0);
+        done         : out std_logic:='0';
+        scl_i        : in  std_logic;
+        scl_o        : out std_logic:='1';
+        scl_t        : out std_logic:='1';
+        sda_i        : in  std_logic;
+        sda_o        : out std_logic:='1';
+        sda_t        : out std_logic:='1'
+       );
+end;
+
+
+architecture rtl of i2c_transmitter is
+
+signal nextstep  : std_logic;
+
+begin
+
+-----------------------------------------------------------------
+-- clock divider
+-----------------------------------------------------------------
+    process
+        variable cnt : unsigned(31 downto 0) := (others=>'0'); 
+    begin
+        wait until rising_edge(clk);
+        if resetn='0' then
+            nextstep <= '0';
+            cnt := (others=>'0');
+        else
+            nextstep <= '0';
+            if cnt = to_unsigned(I2C_CLKDIV,32) then
+                nextstep <= '1';
+                cnt := (others=>'0'); 
+            else
+                cnt := cnt + 1;
+            end if;
+        end if;
+    end process;
+
+
+-----------------------------------------------------------------
+-- transmitter core
+-----------------------------------------------------------------
+    process
+        type state_type is (IDLE, TRANSMIT, DEADEND);
+        variable state     : state_type;
+        
+        constant NSTEPS    : integer := 42;
+        --                                                         St D7  D6  D5  D4  D3  D2  D1  D0  ACK  Sp
+        variable sclbuffer : std_logic_vector (0 to NSTEPS-1) := "110011001100110011001100110011001100110011";
+        variable sdabuffer : std_logic_vector (0 to NSTEPS-1) := "100111100001111000011110000111100001111001";
+        
+        variable stepcnt   : unsigned(   5 downto 0) := (others=>'0');
+        variable addrcnt   : unsigned(AW-1 downto 0) := (others=>'0');
+        
+        variable startcond : std_logic;
+        variable stopcond  : std_logic;
+        variable finished  : std_logic;
+        variable restart   : std_logic;
+    begin
+        wait until rising_edge(clk);
+        
+        if resetn='0' then
+            done    <= '0';
+            state   := IDLE;
+            addrcnt := (others=>'0');
+        else
+            addr  <= std_logic_vector(addrcnt);
+            sda_o <= '0';
+            sda_t <= '1';
+            scl_o <= '0';
+            scl_t <= '1';
+            case state is
+                when IDLE =>
+                    done <= '0';
+                    if nextstep = '1' then
+                        stepcnt   := (others=>'0'); 
+
+                        startcond := data(11);     -- 1 = send start condition
+                        stopcond  := data(10);     -- 1 = send stop condition
+                        finished  := data( 9);     -- 1 = stop fsm after sending current byte
+                        restart   := data( 8);     -- 1 = restart transfer sequence from address 0  ELSE stop FSM
+                        for i in 0 to 7 loop
+                            sdabuffer(3+4*i to 6+4*i) := (others=>data(7-i));
+                        end loop;
+                        sdabuffer( 1 to  2) := (others=>not startcond);
+                        sdabuffer(NSTEPS-3 to NSTEPS-2) := (others=>not stopcond);
+                        sclbuffer(NSTEPS-4 to NSTEPS-3) := (others=>not stopcond);
+                    
+                        state     := TRANSMIT;
+                    end if;
+                    
+                    
+                when TRANSMIT =>
+                    done <= '0'; -- default assignment
+                    if sclbuffer(to_integer(stepcnt)) = '0' then
+                        scl_t <= '0';
+                    else
+                        scl_t <= '1';
+                    end if;  
+                    if sdabuffer(to_integer(stepcnt)) = '0' then
+                        sda_t <= '0';
+                    else
+                        sda_t <= '1';
+                    end if;  
+                    
+                    if nextstep = '1' then
+                        if stepcnt = NSTEPS-1 then   -- byte finished ?
+                            stepcnt := (others=>'0'); 
+                            if finished = '0' then   -- sequence of I2C commands finished?
+                                addrcnt:= addrcnt + 1;
+                                state  := IDLE;                            
+                            elsif restart = '1' then -- restart (send again) ?
+                                addrcnt:= (others=>'0');
+                                state  := IDLE;
+                            else
+                                state  := DEADEND;
+                            end if;
+                        else
+                            stepcnt := stepcnt + 1;
+                        end if;
+                    end if;   
+                                 
+                when DEADEND => -- this is the point of no return
+                    done  <= '1';
+                    sda_t <= '1';
+                    scl_t <= '1';
+
+            end case;
+        end if;
+    end process;
+  
+end rtl;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/6d0b/sources_1/new/i2s_transceiver.vhd

@@ -0,0 +1,135 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity i2s_transceiver is
+    generic(
+        I2S_CLKDIV  : natural := 4     -- fs = sysclk / 512 / (clkdiv+1)
+    );	                    
+    
+    port ( 
+        clk             : in  std_logic;
+        resetn          : in  std_logic;
+        i2c_done        : in  std_logic;
+        
+        axis_pb_data    : in  std_logic_vector (31 downto 0);
+        axis_pb_valid   : in  std_logic;
+        axis_pb_ready   : out std_logic;
+
+        axis_rec_data   : out std_logic_vector (31 downto 0);
+        axis_rec_valid  : out std_logic;
+        axis_rec_ready  : in  std_logic;
+        
+        mclk            : out std_logic;
+        mute            : out std_logic;
+        
+        bclk            : out std_logic;
+        pb_dat          : out std_logic;
+        pb_lrc          : out std_logic;
+        rec_dat         : in  std_logic;
+        rec_lrc         : out std_logic
+       );
+end;
+
+
+architecture rtl of i2s_transceiver is
+
+signal mclk_s            : std_logic := '0';
+signal bclk_s            : std_logic := '0';
+signal bclk_period_s     : unsigned(5 downto 0) := (others=>'0');
+
+begin
+
+    mute    <= i2c_done;
+ 
+-----------------------------------------------------------------
+-- mclk / bclk generation 
+-- mclk = sysclk / 2 / (clkdiv+1) = 256*fs
+-- bclk = mclk / 4 = 64 * fs
+-----------------------------------------------------------------
+    process
+        variable mcnt    : unsigned(7 downto 0) := (others=>'0');
+        variable bcnt    : unsigned(1 downto 0) := (others=>'0');
+    begin
+        wait until rising_edge(clk);
+        if resetn='0' or i2c_done = '0' then
+            mcnt     := (others=>'0');
+            mclk_s  <= '0';
+            bclk_s  <= '0';
+            bclk_period_s <= (others=>'0');
+        else
+            if mcnt = to_unsigned(I2S_CLKDIV,8) then
+                mclk_s <= not mclk_s;
+                if bcnt = "11" then
+                    if (bclk_s = '1') then
+                        bclk_period_s <= bclk_period_s + 1;
+                    end if;    
+                    bclk_s <= not bclk_s;
+                end if;
+                mcnt := (others=>'0');
+                bcnt := bcnt + 1;                   
+           else
+                mcnt := mcnt + 1;
+            end if;
+        end if;
+    end process;
+
+
+-----------------------------------------------------------------
+-- data transmission
+-----------------------------------------------------------------
+    process
+        variable pb_buffer     : std_logic_vector(31 downto 0) := (others=>'0');
+        variable rec_buffer    : std_logic_vector(31 downto 0) := (others=>'0');
+        variable bclk_period_i : integer;
+        variable pb_buff_loaded         : boolean := false;
+        variable rec_buff_transmitted   : boolean := false;
+    begin
+        wait until rising_edge(clk);
+
+        bclk_period_i  := to_integer(bclk_period_s);
+
+        if resetn='0' or i2c_done = '0' then
+            axis_rec_data  <=(others =>'0');
+            axis_rec_valid <= '0';
+            axis_pb_ready  <= '0';
+            pb_dat         <= '0';
+            pb_lrc         <= '0';
+            rec_lrc        <= '0';
+        else
+            axis_pb_ready  <= '0';
+            if axis_rec_ready = '1' then  -- keep valid until data has been consumed (if ready is not asserted in time, data will be lost)
+                axis_rec_valid <= '0';
+            end if; 
+            pb_dat         <= '0';
+            if bclk_period_i = 0  and not pb_buff_loaded then
+                pb_buff_loaded       := true;
+                rec_buff_transmitted := false;
+                pb_buffer      := axis_pb_data;
+                axis_pb_ready  <= '1';
+            elsif bclk_period_i >=  1 and bclk_period_i <= 16 then
+                pb_buff_loaded := false;
+                pb_dat <= pb_buffer(32-bclk_period_i);
+                if bclk_s = '1' then
+                    rec_buffer(32-bclk_period_i) := rec_dat;
+                end if ;
+            elsif bclk_period_i >= 33 and bclk_period_i <= 48 then
+                pb_dat <= pb_buffer(48-bclk_period_i);
+                if bclk_s = '1' then 
+                    rec_buffer(48-bclk_period_i) := rec_dat;
+                end if ;
+            elsif bclk_period_i = 63 and not rec_buff_transmitted then
+                rec_buff_transmitted := true;
+                axis_rec_data  <= rec_buffer;
+                axis_rec_valid <= '1';
+            end if;
+                        
+            pb_lrc  <= not bclk_period_s(5);
+            rec_lrc <= not bclk_period_s(5);
+        end if;
+        
+        mclk    <= mclk_s;
+        bclk    <= bclk_s;
+   end process;
+    
+end rtl;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/6d0b/sources_1/new/zybo_audio.vhd

@@ -0,0 +1,149 @@
+------------------------------------------------------------------------------
+-- This IP supports standalone audio without CPU intervention on ZyBO-Boards
+------------------------------------------------------------------------------
+-- Output/input data is delivered as AXI-Stream
+-- Initially (or after reset) the ZyBo Audio Codec is programmed via I2C
+-- The I2C sequence is defined by the "ROM" contents
+-- After programming is finished Audio Data is delivered via AXIS interfaces
+-- Audio Stream Data is 32 bits wide => [31:16] right channel [15:0] left channel
+
+-- Master Clock and Bit Clock for the Audio Codec are derived from internal clock dividers
+-- Clock division is controlled by Generics (see comments below)
+
+-- OOC synthesis is setup for a clk frequency of 125 MHz -> see contraints file
+
+-- Prof. Dr.-Ing W. Gehrke, 06/2020 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+------------------------
+-- entity section
+------------------------
+
+entity zybo_audio is
+    generic (
+        HAS_RESET_PIN   : boolean  := false;  -- use reset pin?
+        MIC_IN          : natural  := 0;      -- 0 => Line In Input, 1=> Mic input
+        SRR_70          : std_logic_vector(7 downto 0) := "00000000";  -- sample rate register [7:0]
+        I2C_CLKDIV      : positive := 9999;   -- SCL  = clk / 4 / (I2C_CLKDIV+1)
+        I2S_CLKDIV      : natural  := 4       -- mclk = clk / 2 / (I2S_CLKDIV+1)
+        );
+    port (
+        clk             : in  std_logic;
+        resetn          : in  std_logic := '1'; -- reset can be left unconnected
+        
+        -- AXIS playback data
+        axis_pb_data    : in  std_logic_vector (31 downto 0);
+        axis_pb_valid   : in  std_logic;    -- ignored! (added for compatibility), we assume that sender can deliver data when needed
+        axis_pb_ready   : out std_logic;
+
+        -- AXIS record data
+        axis_rec_data   : out std_logic_vector (31 downto 0);
+        axis_rec_valid  : out std_logic;
+        axis_rec_ready  : in  std_logic;    -- ignored! (added for compatibility), we assume data sink can receive data when needed
+        
+        -- Audio Codec Connections
+        mute            : out std_logic;    -- active low mute
+        mclk            : out std_logic;    -- master clock, 256*fs
+        bclk            : out std_logic;    -- I2S bit clock, 64 * fs
+        pb_dat          : out std_logic;    -- I2S playback data (out)
+        pb_lrc          : out std_logic;    -- I2S playback channel select
+        rec_dat         : in  std_logic;    -- I2S record data (in)
+        rec_lrc         : out std_logic;    -- I2S record channel select
+        
+        -- I2C Control for Audio Codec on ZyBo Board (SSM2603) -- insertion of Tristate-IO-Buffer is handled by Vivado
+        scl_i           : in  std_logic;    
+        scl_o           : out std_logic:='1';
+        scl_t           : out std_logic:='1';
+        sda_i           : in  std_logic;
+        sda_o           : out std_logic:='1';
+        sda_t           : out std_logic:='1'
+    );
+end;
+
+
+------------------------
+-- architecture section
+------------------------
+
+architecture rtl of zybo_audio is
+    constant I2C_ROM_ADDR_WIDTH : positive := 8; -- 8 is a bit overdone ;-) -- but let's stick to the save side in case of future extensions     
+        
+    signal   resetn_internal : std_logic;
+    signal   i2c_addr        : std_logic_vector(I2C_ROM_ADDR_WIDTH-1 downto 0);
+    signal   i2c_data        : std_logic_vector(11 downto 0);
+    signal   i2c_done        : std_logic;
+
+begin
+  resetn_internal <= resetn when HAS_RESET_PIN else '1';    -- if reset used, reset feed through, else always 1
+  
+  -- "ROM" containing I2C sequence for audio codec setup
+  i2c_rom : entity work.zybo_audio_i2c_rom
+    generic map(
+        MIC_IN   => MIC_IN,
+        SRR_70   => SRR_70,
+        AW       => I2C_ROM_ADDR_WIDTH  
+        )	                    
+    port map (
+        clk     => clk,
+        addr    => i2c_addr,    -- "ROM" addr
+        dout    => i2c_data     -- 8 bit output data
+        );
+
+   -- I2C Transmitter FSM
+   i2c : entity work.i2c_transmitter
+    generic map(
+        AW          => I2C_ROM_ADDR_WIDTH,
+        I2C_CLKDIV  => I2C_CLKDIV
+        )	                    
+    port map (
+        clk     => clk,
+        resetn  => resetn_internal,
+        
+        -- Internal I2C data from "ROM"
+        data    => i2c_data,    -- 8 bit output data
+        addr    => i2c_addr,    -- "ROM" addr
+        done    => i2c_done,    -- 1 if I2C sequence finished
+        
+        -- I2C IO
+        sda_i   => sda_i,       -- Input (not used)
+        sda_o   => sda_o,       -- Output
+        sda_t   => sda_t,       -- Tristate Enable (1=Tristate)
+        scl_i   => scl_i,       -- Input (not used)
+        scl_o   => scl_o,       -- Output
+        scl_t   => scl_t        -- Tristate Enable (1=Tristate)
+    );
+    
+   -- I2S <-> AXIS Transceiver
+   i2s : entity work.i2s_transceiver
+    generic map(
+        I2S_CLKDIV  => I2S_CLKDIV     -- fs = sysclk / 512 / (clkdiv+1)
+        )	                      
+    port map( 
+        clk             => clk,
+        resetn          => resetn_internal,
+        i2c_done        => i2c_done,    -- 1= I2C Transmitter has finished transmission
+        
+        -- Playback (Output) data 
+        axis_pb_data    => axis_pb_data,
+        axis_pb_valid   => axis_pb_valid,
+        axis_pb_ready   => axis_pb_ready,
+        
+        -- Record (Input) data 
+        axis_rec_data   => axis_rec_data,
+        axis_rec_valid  => axis_rec_valid,
+        axis_rec_ready  => axis_rec_ready,
+        
+        -- Connections to audio codec on Zybo Board (SSM2603)
+        mclk            => mclk,
+        mute            => mute,
+        bclk            => bclk,
+        pb_dat          => pb_dat,
+        pb_lrc          => pb_lrc,
+        rec_dat         => rec_dat,
+        rec_lrc         => rec_lrc
+       );
+
+end;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/6d0b/sources_1/new/zybo_audio_i2c_rom.vhd

@@ -0,0 +1,81 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity zybo_audio_i2c_rom is
+  generic(
+    MIC_IN          : natural   := 0;
+    SRR_70          : std_logic_vector(7 downto 0) := "00000000";  -- sample rate register [7:0]
+    AW              : positive  := 8
+    );
+  port (
+    clk        : in  std_logic;
+    addr       : in  std_logic_vector(AW-1 downto 0);   -- Address
+    dout       : out std_logic_vector(11 downto 0)      -- Data out
+    );
+end;
+
+
+architecture rtl of zybo_audio_i2c_rom is
+
+    constant R0_LEFT_ADC_VOL	 : std_logic_vector (6 downto 0) := "0000000";
+	constant R1_RIGHT_ADC_VOL	 : std_logic_vector (6 downto 0) := "0000001";
+	constant R2_LEFT_DAC_VOL	 : std_logic_vector (6 downto 0) := "0000010";
+	constant R3_RIGHT_DAC_VOL	 : std_logic_vector (6 downto 0) := "0000011";
+	constant R4_ANALOG_PATH		 : std_logic_vector (6 downto 0) := "0000100";
+	constant R5_DIGITAL_PATH	 : std_logic_vector (6 downto 0) := "0000101";
+	constant R6_POWER_MGMT		 : std_logic_vector (6 downto 0) := "0000110";
+	constant R7_DIGITAL_IF		 : std_logic_vector (6 downto 0) := "0000111";
+	constant R8_SAMPLE_RATE		 : std_logic_vector (6 downto 0) := "0001000";
+	constant R9_ACTIVE			 : std_logic_vector (6 downto 0) := "0001001";
+	constant R15_SOFTWARE_RESET	 : std_logic_vector (6 downto 0) := "0001111";
+	constant R16_ALC_CONTROL_1	 : std_logic_vector (6 downto 0) := "0010000";
+	constant R17_ALC_CONTROL_2	 : std_logic_vector (6 downto 0) := "0010001";
+	constant R18_ALC_CONTROL_2	 : std_logic_vector (6 downto 0) := "0010010";
+	
+	constant USE_MIC_INPUT : std_logic_vector (0 downto 0) := std_logic_vector(to_unsigned(MIC_IN,1));
+	constant MIC_MUTE      : std_logic_vector (0 downto 0) := (others=>not USE_MIC_INPUT(0));
+	
+
+    constant i2c_addr : std_logic_vector(6 downto 0) := "0011010"; -- SSM2603 I2C address
+ 
+    type tmem is array(0 to 2**AW-1) of std_logic_vector(11 downto 0);
+    signal mem : tmem := (
+        "1000"&i2c_addr&"0" , "0000"&R9_ACTIVE       &"0", "0100"&"00000001",   -- Diese beiden I2C-Zugriffe von R.H. (06/20) 
+        "1000"&i2c_addr&"0" , "0000"&R6_POWER_MGMT   &"0", "0100"&"00100000",   -- In SW-Ansteuerung des Codecs läuft dieser nicht, wenn diese Zeilen fehlen (Erklärung unklar)
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF",                                 -- Praktische Tests zeigen, dass dies mit dieser Implementierung nicht der Fall ist
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF",                                 -- dennoch wird die beiden Zugriffe hier mit aufgenommen - schaden werden sie nicht
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF",                                 -- anschließend ein paar dummy Zugriffe als Delay
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF", 
+        
+        "1000"&i2c_addr&"0" , "0000"&R15_SOFTWARE_RESET&"0","0100"&"00000000", 
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF", 
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF", 
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF", 
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF",         -- dummy => approx. 1 ms delay @ 100 kHz SCL freq
+        "1000"&i2c_addr&"0" , "0000"&R6_POWER_MGMT   &"0", "0100"&"00110000", 
+        "1000"&i2c_addr&"0" , "0000"&R0_LEFT_ADC_VOL &"0", "0100"&"00010111", 
+        "1000"&i2c_addr&"0" , "0000"&R1_RIGHT_ADC_VOL&"0", "0100"&"00010111", 
+        "1000"&i2c_addr&"0" , "0000"&R2_LEFT_DAC_VOL &"1", "0100"&"01111001", 
+        "1000"&i2c_addr&"0" , "0000"&R3_RIGHT_DAC_VOL&"1", "0100"&"01111001",
+        "1000"&i2c_addr&"0" , "0000"&R4_ANALOG_PATH  &"0", "0100"&"00000000",  
+        "1000"&i2c_addr&"0" , "0000"&R5_DIGITAL_PATH &"0", "0100"&"00000000", 
+        "1000"&i2c_addr&"0" , "0000"&R7_DIGITAL_IF   &"0", "0100"&"00001010", 
+        "1000"&i2c_addr&"0" , "0000"&R8_SAMPLE_RATE  &"0", "0100"&SRR_70, 
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF", 
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF", 
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF", 
+        "0000"&x"FF","0000"&x"FF","0000"&x"FF",         -- dummy => approx. 1 ms delay @ 100 kHz SCL freq
+        "1000"&i2c_addr&"0" , "0000"&R9_ACTIVE       &"0", "0100"&"00000001", 
+        "1000"&i2c_addr&"0" , "0000"&R6_POWER_MGMT   &"0", "0100"&"00000000", 
+        "1000"&i2c_addr&"0" , "0000"&R4_ANALOG_PATH  &"0", "0100"&"00010"&USE_MIC_INPUT&MIC_MUTE&"0",
+         
+        others=>"0010"&x"FF");
+
+begin
+    process begin
+        wait until rising_edge(clk);
+        dout <= mem(to_integer(unsigned(addr)));
+    end process;
+end;
+

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd

@@ -0,0 +1,114 @@
+------------------------------------------------------------------------------
+-- clk_rst_generator.vhd - entity/architecture pair
+------------------------------------------------------------------------------
+----------------------------------------------------------
+-- Prof. Dr.-Ing. W. Gehrke (c) 2024
+----------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity clk_rst_generator is
+  generic
+  (
+    CLOCK_PERIOD        : integer  := 10000;
+    HAS_CLK_INPUT       : boolean  := true;
+    HAS_RESET_INPUT     : boolean  := true;
+    HAS_STOP_INPUT      : boolean  := true
+  );
+  port
+  (
+    clk_in                  : in   std_logic := '1';
+    rst_in                  : in   std_logic := '0';
+    
+    clk                     : out  std_logic;
+    rst_n                   : out  std_logic;
+
+    stop_simulation         : in   std_logic := '0'
+  );
+
+end;
+
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+
+architecture rtl of clk_rst_generator is
+
+    signal clk_sim      : std_logic := '1';
+    signal clk_in_sig   : std_logic := '1';
+    signal clk_sig      : std_logic := '1';
+    signal rst_sig      : std_logic := '0';
+    signal rst_in_sync  : std_logic := '0';
+    
+begin
+    clk    	    <= clk_sig;
+	rst_n       <= not rst_sig;
+
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+    -- CLOCK GENERATION
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+    
+    clk_sig  <= clk_in_sig and clk_sim; 
+                                    -- Dies ist kein gated Clock!
+                                    -- Fuer die Synthese ist clk_sim konstant '1'
+                                    -- somit wird die UND-Verknuepfung 'wegoptimiert'
+                                    -- und was übrig bleibt, ist ein 'Draht' 
+	
+    -- synthesis translate_off
+	clk_sim      <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
+	assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
+	assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
+	assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
+    -- synthesis translate_on
+
+    process (clk_in) begin
+        clk_in_sig 	<= clk_in;
+        -- synthesis translate_off
+        clk_in_sig 	<= '1';
+        -- synthesis translate_on
+    end process;
+
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+    -- RESET GENERATION
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+
+    process
+        variable rescnt : unsigned (6 downto 0) := (others=>'1'); 
+    begin
+        wait until rising_edge(clk_sig);
+
+        rst_in_sync <= rst_in;
+        if rst_in_sync = '1' then
+            rescnt := (others=>'1');
+        end if;
+
+        if rescnt = 0 then
+            rst_sig <= '0';
+        else
+            rescnt := rescnt - 1;
+            rst_sig <= '1';
+        end if;
+    end process;
+    
+    
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+    -- STOP SIMULATION INPUT (simulation only)
+    ---------------------------------------------------------------
+    ---------------------------------------------------------------
+
+    -- synthesis translate_off
+ 	process (stop_simulation) begin
+        if stop_simulation = '1' then
+			assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
+		end if;
+	end process;
+    -- synthesis translate_on
+
+end rtl;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/9e1d/sources_1/new/axis_audio_stereo2mono.vhd

@@ -0,0 +1,58 @@
+--------------------------------------------------------------------------
+--
+-- AXI Stream Audio Stereo to Mono
+--
+-- Prof. Dr.-Ing. W. Gehrke (c) 2020/2021
+--
+--------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity axis_audio_stereo2mono is
+    generic
+    (
+        HAS_LAST         : boolean     := false
+    );
+    port
+    (
+        AXIS_ACLK               : in  std_logic;
+
+        -- AXI Streaming Target Port
+        S_AXIS_TVALID           : in  std_logic;
+        S_AXIS_TDATA            : in  std_logic_vector(31 downto 0);
+        S_AXIS_TLAST            : in  std_logic := '0';
+        S_AXIS_TREADY           : out std_logic;
+
+        -- AXI Streaming Initiator Port
+        M_AXIS_TVALID           : out std_logic;
+        M_AXIS_TDATA            : out std_logic_vector(15 downto 0);
+        M_AXIS_TLAST            : out std_logic;
+        M_AXIS_TREADY           : in  std_logic
+    );  
+end;
+
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+
+architecture rtl of axis_audio_stereo2mono is
+     signal m_valid_sig : std_logic := '0';
+begin
+
+    S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
+    
+    process begin
+        wait until rising_edge(AXIS_ACLK);
+        if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
+            M_AXIS_TDATA  <= std_logic_vector(signed(S_AXIS_TDATA(31)&S_AXIS_TDATA(31 downto 17))+signed(S_AXIS_TDATA(15)&S_AXIS_TDATA(15 downto 1)));
+            M_AXIS_TVALID <= S_AXIS_TVALID;
+            m_valid_sig   <= S_AXIS_TVALID;
+            M_AXIS_TLAST  <= S_AXIS_TLAST;
+        end if;
+    end process;
+    
+        
+end;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/d271/sources_1/new/axil_master_with_rom.vhd

@@ -0,0 +1,284 @@
+------------------------------------------------------------------------------
+-- axil_master_with_rom.vhd - entity/architecture pair
+------------------------------------------------------------------------------
+----------------------------------------------------------
+-- Prof. Dr.-Ing. W. Gehrke (c) 2024
+----------------------------------------------------------
+
+-- AXIL-Master
+-- 
+-- Transactions des Masters werden durch ein ladbares ROM definiert
+-- Die Inhalte des ROMs werden aus einer Datei geladen und bei Synthese und Simulation verwendet
+-- Das ROM besitzt eine Wortbreite von 40 bit
+-- Für einen Befehl werden 1 bis 2 Worte verwendet
+-- Nur 'wal' verwendet 2 40 - Bit - Worte
+--
+-- Die Codierung ist nachfolgend dargestellt :
+--     command wal : <39 : 8>   Adresse <3 : 0>        Befehl(wal = 1)
+--                   <39 : 8>   Daten   <3 : 0>        Befehl WStrobe
+--     command ral : <39 : 8>   Adresse <3 : 0>        Befehl(ral = 2)
+--     command wfi : Befehl(wfi = 6)
+--     command ral : <15 : 8>   Wartezyklen <3 : 0>    Befehl(slp = 7)
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity axil_master_with_rom is
+  generic
+  (
+    HAS_INTERRUPT_IN           : boolean   := true;
+    HAS_FINISHED_OUT           : boolean   := false;
+    STIM_FILENAME              : string    := "../../stimuli.mem"
+  );
+  port
+  (
+    interrupt_in               : in  std_logic:='0';
+    finished_o                 : out std_logic;
+    
+    M_AXIL_ACLK                : in  std_logic;
+    M_AXIL_ARESETN             : in  std_logic;
+    
+    M_AXIL_ARREADY             : in  std_logic;
+    M_AXIL_ARVALID             : out std_logic;
+    M_AXIL_ARADDR              : out std_logic_vector(31 downto 0);
+    M_AXIL_ARPROT              : out std_logic_vector(2 downto 0);
+    M_AXIL_RREADY              : out std_logic;
+    M_AXIL_RVALID              : in  std_logic;
+    M_AXIL_RDATA               : in  std_logic_vector(31 downto 0);
+    M_AXIL_RRESP               : in  std_logic_vector(1 downto 0);
+    M_AXIL_AWREADY             : in  std_logic;
+    M_AXIL_AWVALID             : out std_logic;
+    M_AXIL_AWADDR              : out std_logic_vector(31 downto 0);
+    M_AXIL_AWPROT              : out std_logic_vector(2 downto 0);
+    M_AXIL_WREADY              : in  std_logic;
+    M_AXIL_WVALID              : out std_logic;
+    M_AXIL_WDATA               : out std_logic_vector(31 downto 0);
+    M_AXIL_WSTRB               : out std_logic_vector(3 downto 0);
+    M_AXIL_BREADY              : out std_logic;
+    M_AXIL_BVALID              : in  std_logic;
+    M_AXIL_BRESP               : in  std_logic_vector(1 downto 0)
+  );
+
+end;
+
+
+architecture rtl of axil_master_with_rom is
+
+   
+    type TSTATE is (INIT,INIT_WAIT,
+                    GET_COMMAND,
+                    WR_ADDR,WR_ADDR_WAIT1,WR_ADDR_WAIT2,WR_DATA,WR_DATA_WAIT,WR_RESP,
+                    RD_ADDR,RD_DATA,
+                    WAIT_FOR_INT,
+                    SLEEP,SLEEP_WAIT,
+                    FINISHED
+                    );
+                    
+    signal state : TSTATE := INIT;
+    
+    constant ADDR_WIDTH_CMD_ROM : integer := 12;
+
+    signal mdata  : std_logic_vector(39 downto 0);
+    signal maddr  : std_logic_vector(ADDR_WIDTH_CMD_ROM-1 downto 0);   
+
+begin
+
+cmdrom : entity work.axilm_rom
+    generic map (
+        FILENAME    => STIM_FILENAME,
+        DW          => 40,
+        AW          => ADDR_WIDTH_CMD_ROM
+    )
+    port map (
+        clk         => M_AXIL_ACLK,
+        a           => maddr,
+        q           => mdata
+    );
+    
+
+process 
+    variable cnt8   : unsigned( 7 downto 0);
+    variable cnt32  : unsigned(31 downto 0);
+    variable addr_accepted : boolean;
+    variable data_accepted : boolean;
+         
+  begin
+    wait until rising_edge(M_AXIL_ACLK);
+    
+    if M_AXIL_ARESETN = '0' then
+        state          <= INIT;
+        M_AXIL_ARVALID <= '0';
+        M_AXIL_ARADDR  <= (others=>'X');
+        M_AXIL_ARPROT  <= (others=>'0');
+        M_AXIL_RREADY  <= '0';
+        M_AXIL_AWVALID <= '0';
+        M_AXIL_AWADDR  <= (others=>'X');
+        M_AXIL_AWPROT  <= (others=>'0');
+        M_AXIL_WVALID  <= '0';
+        M_AXIL_WDATA   <= (others=>'X');
+        M_AXIL_WSTRB   <= (others=>'X');
+        M_AXIL_BREADY  <= '0';
+        finished_o     <= '0';
+    else
+        case state is
+        
+            ----
+            -- Init
+            ----
+            when INIT =>
+                finished_o     <= '0';
+                cnt8 := x"10";
+                maddr <= (others=>'0');
+                M_AXIL_ARVALID <= '0';
+                M_AXIL_ARADDR  <= (others=>'X');
+                M_AXIL_ARPROT  <= (others=>'0');
+                M_AXIL_RREADY  <= '0';
+                M_AXIL_AWVALID <= '0';
+                M_AXIL_AWADDR  <= (others=>'X');
+                M_AXIL_AWPROT  <= (others=>'0');
+                M_AXIL_WVALID  <= '0';
+                M_AXIL_WDATA   <= (others=>'X');
+                M_AXIL_WSTRB   <= (others=>'X');
+                M_AXIL_BREADY  <= '0';
+                state <= INIT_WAIT;
+                
+            when INIT_WAIT =>
+                cnt8 := cnt8 - 1;
+                if cnt8 = 0 then
+                    state <= GET_COMMAND;
+                end if; 
+                
+            when GET_COMMAND =>
+                case (mdata(3 downto 0)) is
+                    when x"0" => state <= FINISHED;
+                    when x"1" => state <= WR_ADDR;
+                    when x"2" => state <= RD_ADDR;
+                    when x"6" => state <= WAIT_FOR_INT;
+                    when x"7" => state <= SLEEP;
+                    when others => maddr <= std_logic_vector(unsigned(maddr) + 1);
+                end case;
+                       
+                       
+            ----
+            -- Write
+            ----                       
+            when WR_ADDR =>
+                M_AXIL_AWVALID <= '1';   
+                M_AXIL_AWADDR <= mdata(39 downto 8);
+                M_AXIL_ARVALID <= '0';   
+                M_AXIL_ARADDR <= (others => 'X');
+                maddr <= std_logic_vector(unsigned(maddr) + 1);
+                addr_accepted := false;
+                data_accepted := false;
+                state <= WR_ADDR_WAIT1;
+            when WR_ADDR_WAIT1 =>
+                if (M_AXIL_AWREADY = '1') then
+                    M_AXIL_AWVALID <= '0';
+                    addr_accepted := true;
+                end if;
+                state <= WR_ADDR_WAIT2;
+            when WR_ADDR_WAIT2 =>
+                if (M_AXIL_AWREADY = '1') then
+                    M_AXIL_AWVALID <= '0';
+                    addr_accepted := true;
+                end if;
+                state <= WR_DATA;
+            when WR_DATA =>
+                if (M_AXIL_AWREADY = '1') then
+                    M_AXIL_AWVALID <= '0';
+                    addr_accepted := true;
+                end if;
+                M_AXIL_WSTRB  <= mdata( 3 downto 0);
+                M_AXIL_WDATA  <= mdata(39 downto 8);
+                M_AXIL_WVALID <= '1';   
+                state <= WR_DATA_WAIT;
+            when WR_DATA_WAIT =>
+                if (M_AXIL_AWREADY = '1') then
+                    M_AXIL_AWVALID <= '0';
+                    addr_accepted := true;
+                end if;
+                if (M_AXIL_WREADY = '1') then
+                    M_AXIL_WVALID <= '0';
+                    data_accepted := true;
+                end if;
+                
+                if (addr_accepted and data_accepted) then
+                    maddr <= std_logic_vector(unsigned(maddr) + 1);
+                    M_AXIL_AWVALID <= '0';
+                    M_AXIL_WSTRB   <= (others=>'X');
+                    M_AXIL_WDATA   <= (others=>'X');
+                    M_AXIL_WVALID  <= '0';
+                    M_AXIL_BREADY  <= '1';
+                    state <= WR_RESP;
+                end if;
+            when WR_RESP => 
+                if M_AXIL_BVALID = '1' then
+                    M_AXIL_BREADY  <= '0';
+                    state <= GET_COMMAND;
+                end if;
+                
+                
+            ----
+            -- Read
+            ----                       
+            when RD_ADDR =>
+                M_AXIL_ARVALID <= '1';   
+                M_AXIL_ARADDR <= mdata(39 downto 8);
+                M_AXIL_AWVALID <= 'X';   
+                M_AXIL_AWADDR <= (others => 'X');
+                M_AXIL_RREADY <= '1'; 
+                addr_accepted := false;
+                state <= RD_DATA;             
+            when RD_DATA =>
+                if (M_AXIL_ARREADY = '1') then
+                    M_AXIL_ARVALID <= '0';
+                    addr_accepted := true;
+                end if;
+                if (M_AXIL_RVALID = '1') then
+                    M_AXIL_RREADY <= '0';
+                    data_accepted := true;
+                end if;
+                if (addr_accepted and data_accepted) then
+                    maddr <= std_logic_vector(unsigned(maddr) + 1);
+                    M_AXIL_ARVALID <= '0';
+                    M_AXIL_RREADY  <= '0';
+                    M_AXIL_ARADDR <= (others => 'X');
+                    state <= GET_COMMAND;
+                end if;
+                
+            when WAIT_FOR_INT =>
+               if (interrupt_in = '1') then
+                    maddr <= std_logic_vector(unsigned(maddr) + 1);
+                    state <= GET_COMMAND;
+                end if;
+                
+            when SLEEP =>
+                cnt32 := unsigned(mdata(39 downto 8));
+                -- synthesis translate_off
+                cnt32 := x"0000"&unsigned(mdata(39 downto 24)); -- fuer Simulation Wartezeit um 65536 verringern
+                -- synthesis translate_on
+				maddr <= std_logic_vector(unsigned(maddr) + 1);
+                state <= SLEEP_WAIT;
+                
+            when SLEEP_WAIT =>
+                if (cnt32 /= 0) then
+                    cnt32 := cnt32 - 1;
+                else
+                    state <= GET_COMMAND;                    
+                end if;
+            
+            when FINISHED =>
+                finished_o     <= '1';
+
+            
+        end case;
+    
+    end if;   
+     
+end process;
+
+
+end;

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/d271/sources_1/new/axilm_rom.vhd

@@ -0,0 +1,65 @@
+------------------------------------------------------------------------------
+-- axilm_rom.vhd - entity/architecture pair
+------------------------------------------------------------------------------
+----------------------------------------------------------
+-- Prof. Dr.-Ing. W. Gehrke (c) 2024
+----------------------------------------------------------
+
+-- ref. https://docs.amd.com/r/en-US/ug901-vivado-synthesis/VHDL-Code-Example
+
+use std.textio.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+
+entity axilm_rom is
+
+  generic (
+    FILENAME    : string;
+    DW          : integer;                                  -- Data Width
+    AW          : integer                                   -- Address Width
+    );
+  port (
+    clk         : in  std_logic;                                            -- Clock
+    a           : in  std_logic_vector(AW-1 downto 0);                      -- Address
+    q           : out std_logic_vector(DW-1 downto 0)                       -- Data out port
+);
+end;
+
+
+architecture rtl of axilm_rom is
+    type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
+    
+    impure function InitMemFromFile(MemFileName : in string) return tmem is
+        FILE MemFile : text is in MemFileName;
+        variable MemFileLine : line;
+        variable mem : tmem;
+    begin
+        for i in tmem'range loop
+            readline(MemFile, MemFileLine);
+            read(MemFileLine, mem(i));
+        end loop;
+        return mem;
+    end function;
+    
+    constant mem : tmem := InitMemFromFile(
+    -- synthesis translate_off
+    "../../" &
+    -- synthesis translate_on
+    FILENAME);
+    
+begin
+    process
+    begin
+        wait until rising_edge(clk);
+         q <= mem(to_integer(unsigned(a)));
+    end process;
+end;
+
+
+
+
+
+

Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ipshared/e87a/hdl/gigantic_mux_v1_0_cntr.v

@@ -0,0 +1,287 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
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+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
+`pragma protect key_block
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+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11376)
+`pragma protect data_block
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+`pragma protect end_protected