diff --git a/Milestone3/M3-Audio-Filter-mit-AXIL.pdf b/Milestone3/M3-Audio-Filter-mit-AXIL.pdf new file mode 100644 index 0000000..326bf13 Binary files /dev/null and b/Milestone3/M3-Audio-Filter-mit-AXIL.pdf differ diff --git a/Milestone3/Single-Cycle-Loesung-mit-Timing-Failure/Stop! --Erstmal-selbst-probieren/axis_prog_audio_filter3-snippet-single-cycle.vhd b/Milestone3/Single-Cycle-Loesung-mit-Timing-Failure/Stop! --Erstmal-selbst-probieren/axis_prog_audio_filter3-snippet-single-cycle.vhd new file mode 100644 index 0000000..69ce63b --- /dev/null +++ b/Milestone3/Single-Cycle-Loesung-mit-Timing-Failure/Stop! --Erstmal-selbst-probieren/axis_prog_audio_filter3-snippet-single-cycle.vhd @@ -0,0 +1,66 @@ + +architecture rtl of axis_prog_audio_filter3 is + signal m_valid_sig : std_logic := '0'; + signal run : std_logic := '0'; +begin + + process + variable c0 : signed( 7 downto 0) := to_signed(COEFF_0,8); + variable c1 : signed( 7 downto 0) := to_signed(COEFF_1,8); + variable c2 : signed( 7 downto 0) := to_signed(COEFF_2,8); + variable s0 : signed(15 downto 0) := (others=>'0'); + variable s1 : signed(15 downto 0) := (others=>'0'); + variable s2 : signed(15 downto 0) := (others=>'0'); + variable p0 : signed(23 downto 0); + variable p1 : signed(23 downto 0); + variable p2 : signed(23 downto 0); + variable res : signed(25 downto 0); + variable lshift : unsigned(2 downto 0) := to_unsigned(SHIFT, 3); + begin + wait until rising_edge(AXI_ACLK); + + -- AXIL Slave Lesezugriff + -- das koennen Sie selbst !! + + -- AXI Slave Schreibzugriff + -- das koennen Sie selbst !! + + + if M_AXIS_TREADY = '1' or m_valid_sig = '0' then + + if HAS_LAST then + M_AXIS_TLAST <= S_AXIS_TLAST; + end if; + + m_valid_sig <= S_AXIS_TVALID; + + if S_AXIS_TVALID = '1' then + s2 := s1; + s1 := s0; + s0 := signed(S_AXIS_TDATA); + + p0 := s0*c0; + p1 := s1*c1; + p2 := s2*c2; + + res := (p0(23)&p0(23)&p0); + res := res + (p1(23)&p1(23)&p1); + res := res + (p2(23)&p2(23)&p2); + + M_AXIS_TDATA <= std_logic_vector(res(SHIFT+15 downto SHIFT)); + end if; + end if; + + -- Reset + if AXI_ARESETN = '0' then + S_AXIL_RVALID <= '0'; + S_AXIL_BVALID <= '0'; + + if RUN_AFTER_RESET = true then + run <= '1'; + else + run <= '0'; + end if; + end if; + end process; +end; \ No newline at end of file diff --git a/Milestone3/axis_audio_filter3.vhd b/Milestone3/axis_audio_filter3.vhd new file mode 100644 index 0000000..089e8c0 --- /dev/null +++ b/Milestone3/axis_audio_filter3.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity axis_prog_audio_filter3 is + generic + ( + COEFF_0 : integer := 42; + COEFF_1 : integer := 42; + COEFF_2 : integer := 42; + SHIFT : integer := 7; + RUN_AFTER_RESET : boolean := true; + HAS_LAST : boolean := false + ); + port + ( + AXI_ACLK : in std_logic; + AXI_ARESETN : in std_logic; + + --- Write address channel + S_AXIL_AWADDR : in std_logic_vector(7 downto 0); + S_AXIL_AWVALID : in std_logic; + S_AXIL_AWREADY : out std_logic; + --- Write data channel + S_AXIL_WDATA : in std_logic_vector(31 downto 0); + S_AXIL_WVALID : in std_logic; + S_AXIL_WREADY : out std_logic; + S_AXIL_WSTRB : in std_logic_vector((32/8)-1 downto 0); + --- Write response channel + S_AXIL_BVALID : out std_logic; + S_AXIL_BREADY : in std_logic; + S_AXIL_BRESP : out std_logic_vector(1 downto 0); + --- Read address channel + S_AXIL_ARADDR : in std_logic_vector(7 downto 0); + S_AXIL_ARVALID : in std_logic; + S_AXIL_ARREADY : out std_logic; + --- Read data channel + S_AXIL_RDATA : out std_logic_vector(31 downto 0); + S_AXIL_RVALID : out std_logic; + S_AXIL_RREADY : in std_logic; + S_AXIL_RRESP : out std_logic_vector(1 downto 0); + + -- AXI Streaming Target Port + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(15 downto 0); + S_AXIS_TLAST : in std_logic := '0'; + S_AXIS_TREADY : out std_logic; + -- AXI Streaming Initiator Port + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(15 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic + ); +end; + + + + +architecture rtl of axis_prog_audio_filter3 is + +begin + +end; \ No newline at end of file diff --git a/Milestone3/convertAll.bat b/Milestone3/convertAll.bat new file mode 100644 index 0000000..0ec5b04 --- /dev/null +++ b/Milestone3/convertAll.bat @@ -0,0 +1,3 @@ +@echo off +echo: +for %%i in (*.stm) do stm2mem %%i & echo: & echo: & echo: \ No newline at end of file diff --git a/Milestone3/milestone3.xdc b/Milestone3/milestone3.xdc new file mode 100644 index 0000000..76e3578 --- /dev/null +++ b/Milestone3/milestone3.xdc @@ -0,0 +1,14 @@ +create_clock -add -name clk_pin -period 8.00 [get_ports clk ]; +set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports clk]; # Board Clock (125 MHZ) + +set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports reset]; + +set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 PULLUP true} [get_ports i2c_scl_io]; +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 PULLUP true} [get_ports i2c_sda_io]; +set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports bclk]; +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports pb_dat]; +set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports pb_lrc]; +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports rec_dat]; +set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports rec_lrc]; +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports mute]; +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports mclk]; diff --git a/Milestone3/stimuli.mem b/Milestone3/stimuli.mem new file mode 100644 index 0000000..d1a6e47 --- /dev/null +++ b/Milestone3/stimuli.mem @@ -0,0 +1,18 @@ +0000000000000000000000000000000000000001 +0000000000000000000000000000000100001111 +0000000000000000000000000000010000000001 +0000011000010000001000000001000000001111 +0001011001011010000010111100000000000111 +0000000000000000000000000000010000000001 +0000011011110000001000001111000000001111 +0001011001011010000010111100000000000111 +0000000000000000000000000000010000000001 +0000011000010000000010001110000000001111 +0001011001011010000010111100000000000111 +0000000000000000000000000000010000000001 +0000011000100000000010000010000000001111 +0001011001011010000010111100000000000111 +0000000000000000000000000000010000000001 +0000011000000000010000000000000000001111 +0001011001011010000010111100000000000111 +0000000000000000000000000000000000000000 diff --git a/Milestone3/stimuli.stm b/Milestone3/stimuli.stm new file mode 100644 index 0000000..d29b483 --- /dev/null +++ b/Milestone3/stimuli.stm @@ -0,0 +1,11 @@ +wal 0 1 # RUN auf 1 +wal 4 0x06102010 # LOW PASS +slp 375000000 # sleep 3 sec +wal 4 0x06F020F0 # HIGH PASS +slp 375000000 # sleep 3 sec +wal 4 0x061008E0 # BAND PASS +slp 375000000 # sleep 3 sec +wal 4 0x06200820 # BAND STOP +slp 375000000 # sleep 3 sec +wal 4 0x06004000 # PASS THRU +slp 375000000 # sleep 3 sec diff --git a/Milestone3/stm2mem.exe b/Milestone3/stm2mem.exe new file mode 100644 index 0000000..7a20529 Binary files /dev/null and b/Milestone3/stm2mem.exe differ