Milestone 6 Vivado-Projekt angelegt
This commit is contained in:
Sebastian Meyer
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version:1
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6d6f64655f636f756e7465727c4755494d6f6465:2
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eof:
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@@ -0,0 +1,7 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2023.1 (64-bit) -->
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<!-- -->
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||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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||||
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||||
<labtools version="1" minor="0"/>
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BIN
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+5
-51
@@ -2,56 +2,10 @@
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<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1730144234"/>
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-452
@@ -1,452 +0,0 @@
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<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon Oct 28 20:37:14 2024" VIVADOVERSION="2023.1">
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<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.1" DEVICE="7z020" NAME="design_1_sim" PACKAGE="clg400" SPEEDGRADE="-1"/>
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<EXTERNALPORTS/>
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<EXTERNALINTERFACES/>
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<MODULES>
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<MODULE COREREVISION="1" FULLNAME="/axis_audio_bitcrusher_0" HWVERSION="1.0" INSTANCE="axis_audio_bitcrusher_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_bitcrusher" VLNV="xilinx.com:module_ref:axis_audio_bitcrusher:1.0">
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<PORTS>
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<CONNECTIONS>
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<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="I" NAME="AXIS_ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
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<CONNECTIONS>
|
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<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TVALID">
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<CONNECTIONS>
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<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TVALID"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="I" LEFT="15" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TDATA">
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<CONNECTIONS>
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<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TDATA"/>
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<PORT DIR="I" NAME="S_AXIS_TLAST" SIGIS="undef"/>
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<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TREADY">
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<CONNECTIONS>
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<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TREADY"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TVALID">
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<CONNECTIONS>
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<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TVALID"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" LEFT="15" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TDATA">
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<CONNECTIONS>
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<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TDATA"/>
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<PORT DIR="O" NAME="M_AXIS_TLAST" SIGIS="undef"/>
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<CONNECTIONS>
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<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TREADY"/>
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</PORT>
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</PORTS>
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<BUSINTERFACES>
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<PORTMAPS>
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="2" FULLNAME="/axis_audio_master_si_0" HWVERSION="1.0" INSTANCE="axis_audio_master_si_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_master_simmodel" VLNV="xilinx.com:user:axis_audio_master_simmodel:1.0">
|
||||
<DOCUMENTS/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<PORTS>
|
||||
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|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
|
||||
</CONNECTIONS>
|
||||
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|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="31" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="351" NAME="WAV_HEADER" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_WAV_HEADER">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="WAV_HEADER"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_master_si_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
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|
||||
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|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="3" FULLNAME="/axis_audio_mono2ster_0" HWVERSION="1.0" INSTANCE="axis_audio_mono2ster_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_mono2stereo" VLNV="xilinx.com:user:axis_audio_mono2stereo:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_axis_audio_mono2ster_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXIS_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="15" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="31" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_mono2ster_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
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|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
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|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_bitcrusher_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="18" FULLNAME="/axis_audio_slave_sim_0" HWVERSION="1.0" INSTANCE="axis_audio_slave_sim_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_slave_simmodel" VLNV="xilinx.com:user:axis_audio_slave_simmodel:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="FILE_NAME" VALUE="../../../../tst_out"/>
|
||||
<PARAMETER NAME="RANDOM_TREADY" VALUE="true"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_axis_audio_slave_sim_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="FINISHED" SIGIS="undef" SIGNAME="axis_audio_slave_sim_0_FINISHED">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="stop_simulation"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="351" NAME="WAV_HEADER" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_WAV_HEADER">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="WAV_HEADER"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_mono2ster_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="4" FULLNAME="/axis_audio_stereo2mo_0" HWVERSION="1.0" INSTANCE="axis_audio_stereo2mo_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_stereo2mono" VLNV="xilinx.com:user:axis_audio_stereo2mono:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_axis_audio_stereo2mo_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXIS_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="15" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_stereo2mo_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_master_si_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="7" FULLNAME="/clk_rst_generator_0" HWVERSION="1.0" INSTANCE="clk_rst_generator_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="clk_rst_generator" VLNV="wg:user:clk_rst_generator:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="CLOCK_PERIOD" VALUE="8000"/>
|
||||
<PARAMETER NAME="HAS_CLK_INPUT" VALUE="true"/>
|
||||
<PARAMETER NAME="HAS_RESET_INPUT" VALUE="true"/>
|
||||
<PARAMETER NAME="HAS_STOP_INPUT" VALUE="true"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_clk_rst_generator_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT DIR="I" NAME="clk_in" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="rst_in" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="clk" SIGIS="undef" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="ACLK"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="rst_n" SIGIS="undef" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="ARESETN"/>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="AXIS_ARESETN"/>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="ARESETN"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="stop_simulation" SIGIS="undef" SIGNAME="axis_audio_slave_sim_0_FINISHED">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="FINISHED"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES/>
|
||||
</MODULE>
|
||||
</MODULES>
|
||||
|
||||
</EDKSYSTEM>
|
||||
+10
-54
@@ -436,40 +436,6 @@
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_bitcrusher</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5912d307</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>design_1_sim_axis_audio_bitcrusher_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 19:06:27 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5912d307</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
@@ -478,7 +444,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -490,7 +456,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -502,7 +468,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -521,7 +487,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -536,7 +502,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -551,7 +517,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -563,7 +529,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -579,7 +545,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -591,7 +557,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -603,7 +569,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -632,16 +598,6 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_sim_axis_audio_bitcrusher_0_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_audio_bitcrusher:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
|
||||
-87
@@ -1,87 +0,0 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"design_1_sim": {
|
||||
"proto_instances": {
|
||||
"/axis_audio_bitcrusher_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"ARESETN": { "actual": "AXIS_ARESETN"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TLAST": { "actual": "M_AXIS_TLAST"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_bitcrusher_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"ARESETN": { "actual": "AXIS_ARESETN"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TLAST": { "actual": "S_AXIS_TLAST"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_master_si_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "ACLK"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_mono2ster_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_mono2ster_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_slave_sim_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "ACLK"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_stereo2mo_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_stereo2mo_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-81
@@ -1,81 +0,0 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Oct 28 20:37:14 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_sim.bd
|
||||
//Design : design_1_sim
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "design_1_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1_sim,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1_sim.hwdef" *)
|
||||
module design_1_sim
|
||||
();
|
||||
|
||||
wire [15:0]axis_audio_bitcrusher_0_M_AXIS_TDATA;
|
||||
wire axis_audio_bitcrusher_0_M_AXIS_TREADY;
|
||||
wire axis_audio_bitcrusher_0_M_AXIS_TVALID;
|
||||
wire [31:0]axis_audio_master_si_0_M_AXIS_TDATA;
|
||||
wire axis_audio_master_si_0_M_AXIS_TREADY;
|
||||
wire axis_audio_master_si_0_M_AXIS_TVALID;
|
||||
wire [351:0]axis_audio_master_si_0_WAV_HEADER;
|
||||
wire [31:0]axis_audio_mono2ster_0_M_AXIS_TDATA;
|
||||
wire axis_audio_mono2ster_0_M_AXIS_TREADY;
|
||||
wire axis_audio_mono2ster_0_M_AXIS_TVALID;
|
||||
wire axis_audio_slave_sim_0_FINISHED;
|
||||
wire [15:0]axis_audio_stereo2mo_0_M_AXIS_TDATA;
|
||||
wire axis_audio_stereo2mo_0_M_AXIS_TREADY;
|
||||
wire axis_audio_stereo2mo_0_M_AXIS_TVALID;
|
||||
wire clk_rst_generator_0_clk;
|
||||
wire clk_rst_generator_0_rst_n;
|
||||
|
||||
design_1_sim_axis_audio_bitcrusher_0_0 axis_audio_bitcrusher_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.AXIS_ARESETN(clk_rst_generator_0_rst_n),
|
||||
.M_AXIS_TDATA(axis_audio_bitcrusher_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_bitcrusher_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_bitcrusher_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_stereo2mo_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(1'b0),
|
||||
.S_AXIS_TREADY(axis_audio_stereo2mo_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_stereo2mo_0_M_AXIS_TVALID));
|
||||
design_1_sim_axis_audio_master_si_0_0 axis_audio_master_si_0
|
||||
(.ACLK(clk_rst_generator_0_clk),
|
||||
.ARESETN(clk_rst_generator_0_rst_n),
|
||||
.M_AXIS_TDATA(axis_audio_master_si_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_master_si_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_master_si_0_M_AXIS_TVALID),
|
||||
.WAV_HEADER(axis_audio_master_si_0_WAV_HEADER));
|
||||
design_1_sim_axis_audio_mono2ster_0_0 axis_audio_mono2ster_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.M_AXIS_TDATA(axis_audio_mono2ster_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_mono2ster_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_mono2ster_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_bitcrusher_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_bitcrusher_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_bitcrusher_0_M_AXIS_TVALID));
|
||||
design_1_sim_axis_audio_slave_sim_0_0 axis_audio_slave_sim_0
|
||||
(.ACLK(clk_rst_generator_0_clk),
|
||||
.ARESETN(clk_rst_generator_0_rst_n),
|
||||
.FINISHED(axis_audio_slave_sim_0_FINISHED),
|
||||
.S_AXIS_TDATA(axis_audio_mono2ster_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_mono2ster_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_mono2ster_0_M_AXIS_TVALID),
|
||||
.WAV_HEADER(axis_audio_master_si_0_WAV_HEADER));
|
||||
design_1_sim_axis_audio_stereo2mo_0_0 axis_audio_stereo2mo_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.M_AXIS_TDATA(axis_audio_stereo2mo_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_stereo2mo_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_stereo2mo_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_master_si_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_master_si_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_master_si_0_M_AXIS_TVALID));
|
||||
design_1_sim_clk_rst_generator_0_0 clk_rst_generator_0
|
||||
(.clk(clk_rst_generator_0_clk),
|
||||
.clk_in(1'b1),
|
||||
.rst_in(1'b0),
|
||||
.rst_n(clk_rst_generator_0_rst_n),
|
||||
.stop_simulation(axis_audio_slave_sim_0_FINISHED));
|
||||
endmodule
|
||||
BIN
Binary file not shown.
-81
@@ -1,81 +0,0 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Oct 28 20:37:14 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_sim.bd
|
||||
//Design : design_1_sim
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "design_1_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1_sim,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1_sim.hwdef" *)
|
||||
module design_1_sim
|
||||
();
|
||||
|
||||
wire [15:0]axis_audio_bitcrusher_0_M_AXIS_TDATA;
|
||||
wire axis_audio_bitcrusher_0_M_AXIS_TREADY;
|
||||
wire axis_audio_bitcrusher_0_M_AXIS_TVALID;
|
||||
wire [31:0]axis_audio_master_si_0_M_AXIS_TDATA;
|
||||
wire axis_audio_master_si_0_M_AXIS_TREADY;
|
||||
wire axis_audio_master_si_0_M_AXIS_TVALID;
|
||||
wire [351:0]axis_audio_master_si_0_WAV_HEADER;
|
||||
wire [31:0]axis_audio_mono2ster_0_M_AXIS_TDATA;
|
||||
wire axis_audio_mono2ster_0_M_AXIS_TREADY;
|
||||
wire axis_audio_mono2ster_0_M_AXIS_TVALID;
|
||||
wire axis_audio_slave_sim_0_FINISHED;
|
||||
wire [15:0]axis_audio_stereo2mo_0_M_AXIS_TDATA;
|
||||
wire axis_audio_stereo2mo_0_M_AXIS_TREADY;
|
||||
wire axis_audio_stereo2mo_0_M_AXIS_TVALID;
|
||||
wire clk_rst_generator_0_clk;
|
||||
wire clk_rst_generator_0_rst_n;
|
||||
|
||||
design_1_sim_axis_audio_bitcrusher_0_0 axis_audio_bitcrusher_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.AXIS_ARESETN(clk_rst_generator_0_rst_n),
|
||||
.M_AXIS_TDATA(axis_audio_bitcrusher_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_bitcrusher_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_bitcrusher_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_stereo2mo_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(1'b0),
|
||||
.S_AXIS_TREADY(axis_audio_stereo2mo_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_stereo2mo_0_M_AXIS_TVALID));
|
||||
design_1_sim_axis_audio_master_si_0_0 axis_audio_master_si_0
|
||||
(.ACLK(clk_rst_generator_0_clk),
|
||||
.ARESETN(clk_rst_generator_0_rst_n),
|
||||
.M_AXIS_TDATA(axis_audio_master_si_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_master_si_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_master_si_0_M_AXIS_TVALID),
|
||||
.WAV_HEADER(axis_audio_master_si_0_WAV_HEADER));
|
||||
design_1_sim_axis_audio_mono2ster_0_0 axis_audio_mono2ster_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.M_AXIS_TDATA(axis_audio_mono2ster_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_mono2ster_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_mono2ster_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_bitcrusher_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_bitcrusher_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_bitcrusher_0_M_AXIS_TVALID));
|
||||
design_1_sim_axis_audio_slave_sim_0_0 axis_audio_slave_sim_0
|
||||
(.ACLK(clk_rst_generator_0_clk),
|
||||
.ARESETN(clk_rst_generator_0_rst_n),
|
||||
.FINISHED(axis_audio_slave_sim_0_FINISHED),
|
||||
.S_AXIS_TDATA(axis_audio_mono2ster_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_mono2ster_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_mono2ster_0_M_AXIS_TVALID),
|
||||
.WAV_HEADER(axis_audio_master_si_0_WAV_HEADER));
|
||||
design_1_sim_axis_audio_stereo2mo_0_0 axis_audio_stereo2mo_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.M_AXIS_TDATA(axis_audio_stereo2mo_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_stereo2mo_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_stereo2mo_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_master_si_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_master_si_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_master_si_0_M_AXIS_TVALID));
|
||||
design_1_sim_clk_rst_generator_0_0 clk_rst_generator_0
|
||||
(.clk(clk_rst_generator_0_clk),
|
||||
.clk_in(1'b1),
|
||||
.rst_in(1'b0),
|
||||
.rst_n(clk_rst_generator_0_rst_n),
|
||||
.stop_simulation(axis_audio_slave_sim_0_FINISHED));
|
||||
endmodule
|
||||
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="design_1_syn" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1730149477"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1730149477"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1730149477"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1730149477"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732117019"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732117019"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732117019"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732117019"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_1_syn.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Oct 28 22:04:25 2024
|
||||
//Date : Wed Nov 20 16:36:50 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_syn_wrapper.bd
|
||||
//Design : design_1_syn_wrapper
|
||||
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon Oct 28 22:04:37 2024" VIVADOVERSION="2023.1">
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Nov 20 16:36:59 2024" VIVADOVERSION="2023.1">
|
||||
|
||||
<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.1" DEVICE="7z020" NAME="design_1_syn" PACKAGE="clg400" SPEEDGRADE="-1"/>
|
||||
|
||||
@@ -390,16 +390,16 @@
|
||||
<PORT DIR="O" NAME="clk" SIGIS="undef" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="zybo_audio_0" PORT="clk"/>
|
||||
<CONNECTION INSTANCE="system_ila_0" PORT="clk"/>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="AXIS_ACLK"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="rst_n" SIGIS="undef" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="AXIS_ARESETN"/>
|
||||
<CONNECTION INSTANCE="system_ila_0" PORT="resetn"/>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="AXIS_ARESETN"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="stop_simulation" SIGIS="undef"/>
|
||||
|
||||
+3
-3
@@ -471,7 +471,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:08:32 UTC 2024</spirit:value>
|
||||
<spirit:value>Wed Nov 20 15:39:18 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -502,7 +502,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
<spirit:value>Wed Nov 20 15:36:51 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -522,7 +522,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
<spirit:value>Wed Nov 20 15:36:51 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:08:32 2024
|
||||
// Date : Wed Nov 20 16:39:18 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0_sim_netlist.v
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:08:32 2024
|
||||
-- Date : Wed Nov 20 16:39:18 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0_sim_netlist.vhdl
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:08:32 2024
|
||||
// Date : Wed Nov 20 16:39:18 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0_stub.v
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:08:32 2024
|
||||
-- Date : Wed Nov 20 16:39:18 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0_stub.vhdl
|
||||
|
||||
+390
-6
@@ -1,26 +1,138 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"boundary_crc": "0x14BE19C5147B5D81",
|
||||
"design_src": "SBD",
|
||||
"device": "xc7z020clg400-1",
|
||||
"name": "bd_3e86_0",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"scoped": "true",
|
||||
"synth_flow_mode": "None",
|
||||
"tool_version": "2023.1"
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"ila_lib": "",
|
||||
"g_inst": ""
|
||||
},
|
||||
"design_tree": {},
|
||||
"interface_ports": {
|
||||
"SLOT_0_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_3e86_clk",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"LAYERED_METADATA": {
|
||||
"value": "undef",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_3e86_clk",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"LAYERED_METADATA": {
|
||||
"value": "undef",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
@@ -33,12 +145,284 @@
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "resetn"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_3e86_clk",
|
||||
"value_src": "default_prop"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_TOLERANCE_HZ": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"resetn": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"ila_lib": {
|
||||
"vlnv": "xilinx.com:ip:ila:6.2",
|
||||
"xci_name": "bd_3e86_0_ila_lib_0",
|
||||
"xci_path": "ip\\ip_0\\bd_3e86_0_ila_lib_0.xci",
|
||||
"inst_hier_path": "ila_lib",
|
||||
"parameters": {
|
||||
"ALL_PROBE_SAME_MU": {
|
||||
"value": "TRUE"
|
||||
},
|
||||
"ALL_PROBE_SAME_MU_CNT": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_ADV_TRIGGER": {
|
||||
"value": "FALSE"
|
||||
},
|
||||
"C_DATA_DEPTH": {
|
||||
"value": "1024"
|
||||
},
|
||||
"C_EN_STRG_QUAL": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_ILA_CLK_FREQ": {
|
||||
"value": "100000000"
|
||||
},
|
||||
"C_INPUT_PIPE_STAGES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_MONITOR_TYPE": {
|
||||
"value": "Native"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "8"
|
||||
},
|
||||
"C_PROBE0_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE0_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE1_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE1_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE2_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE2_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE3_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE3_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE4_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE4_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE5_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE5_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE6_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE6_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE7_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE7_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_TRIGIN_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_TRIGOUT_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_XLNX_HW_PROBE_INFO": {
|
||||
"value": "DEFAULT"
|
||||
}
|
||||
}
|
||||
},
|
||||
"g_inst": {
|
||||
"vlnv": "xilinx.com:ip:gigantic_mux:1.0",
|
||||
"xci_name": "bd_3e86_0_g_inst_0",
|
||||
"xci_path": "ip\\ip_1\\bd_3e86_0_g_inst_0.xci",
|
||||
"inst_hier_path": "g_inst",
|
||||
"parameters": {
|
||||
"C_EN_GIGAMUX": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_NUM_MONITOR_SLOTS": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_0_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_MON_MODE": {
|
||||
"value": "FT"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_1_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_MON_MODE": {
|
||||
"value": "FT"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"Conn": {
|
||||
"interface_ports": [
|
||||
"SLOT_0_AXIS",
|
||||
"g_inst/slot_0_axis"
|
||||
]
|
||||
},
|
||||
"Conn1": {
|
||||
"interface_ports": [
|
||||
"SLOT_1_AXIS",
|
||||
"g_inst/slot_1_axis"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_1": {
|
||||
"ports": [
|
||||
"clk",
|
||||
"ila_lib/clk",
|
||||
"g_inst/aclk"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tdata",
|
||||
"ila_lib/probe0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tlast",
|
||||
"ila_lib/probe3"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tready",
|
||||
"ila_lib/probe2"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tvalid",
|
||||
"ila_lib/probe1"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tdata",
|
||||
"ila_lib/probe4"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tlast",
|
||||
"ila_lib/probe7"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tready",
|
||||
"ila_lib/probe6"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tvalid",
|
||||
"ila_lib/probe5"
|
||||
]
|
||||
},
|
||||
"resetn_1": {
|
||||
"ports": [
|
||||
"resetn",
|
||||
"g_inst/aresetn"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
+39
-5
@@ -2,10 +2,44 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_3e86_0" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1730194747"/>
|
||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1730194747"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1730194747"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1730194747"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732117018"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732117018"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732117018"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732117018"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_3e86_0.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_3e86_0.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="bd_3e86_0_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1_syn_system_ila_0_2.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1_syn_system_ila_0_2.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
+1
@@ -6,5 +6,6 @@
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
+54
@@ -0,0 +1,54 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3e86_0_wrapper.bd
|
||||
//Design : bd_3e86_0_wrapper
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module bd_3e86_0_wrapper
|
||||
(SLOT_0_AXIS_tdata,
|
||||
SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tready,
|
||||
SLOT_0_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid,
|
||||
clk,
|
||||
resetn);
|
||||
input [15:0]SLOT_0_AXIS_tdata;
|
||||
input SLOT_0_AXIS_tlast;
|
||||
input SLOT_0_AXIS_tready;
|
||||
input SLOT_0_AXIS_tvalid;
|
||||
input [15:0]SLOT_1_AXIS_tdata;
|
||||
input SLOT_1_AXIS_tlast;
|
||||
input SLOT_1_AXIS_tready;
|
||||
input SLOT_1_AXIS_tvalid;
|
||||
input clk;
|
||||
input resetn;
|
||||
|
||||
wire [15:0]SLOT_0_AXIS_tdata;
|
||||
wire SLOT_0_AXIS_tlast;
|
||||
wire SLOT_0_AXIS_tready;
|
||||
wire SLOT_0_AXIS_tvalid;
|
||||
wire [15:0]SLOT_1_AXIS_tdata;
|
||||
wire SLOT_1_AXIS_tlast;
|
||||
wire SLOT_1_AXIS_tready;
|
||||
wire SLOT_1_AXIS_tvalid;
|
||||
wire clk;
|
||||
wire resetn;
|
||||
|
||||
bd_3e86_0 bd_3e86_0_i
|
||||
(.SLOT_0_AXIS_tdata(SLOT_0_AXIS_tdata),
|
||||
.SLOT_0_AXIS_tlast(SLOT_0_AXIS_tlast),
|
||||
.SLOT_0_AXIS_tready(SLOT_0_AXIS_tready),
|
||||
.SLOT_0_AXIS_tvalid(SLOT_0_AXIS_tvalid),
|
||||
.SLOT_1_AXIS_tdata(SLOT_1_AXIS_tdata),
|
||||
.SLOT_1_AXIS_tlast(SLOT_1_AXIS_tlast),
|
||||
.SLOT_1_AXIS_tready(SLOT_1_AXIS_tready),
|
||||
.SLOT_1_AXIS_tvalid(SLOT_1_AXIS_tvalid),
|
||||
.clk(clk),
|
||||
.resetn(resetn));
|
||||
endmodule
|
||||
+6306
File diff suppressed because it is too large
Load Diff
+74950
File diff suppressed because it is too large
Load Diff
+69
@@ -0,0 +1,69 @@
|
||||
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
|
||||
################################################################################
|
||||
#create_clock -name clock_name -period 10 [get_ports clock_name]
|
||||
################################################################################
|
||||
|
||||
#list of all the clock needed for ILA core
|
||||
|
||||
|
||||
|
||||
create_clock -name ILA_CLK -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
+103
@@ -0,0 +1,103 @@
|
||||
##
|
||||
## ARM and HALT transfer false paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/din_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/dout_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Register False Paths
|
||||
##
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/itrigger_out_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/use_probe_debug_circuit_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/capture_qual_ctrl_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/debug_data_in_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*.cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/cfg_data_vec_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_ila_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_xsdb_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL} ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*" && IS_SEQUENTIAL}]]
|
||||
#set_false_path -from [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK}] -to [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D}]
|
||||
|
||||
##
|
||||
## ILA Capture Block False Paths
|
||||
##
|
||||
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*icap_addr_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/captured_samples*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_DONE_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_TRIGGER_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Capture State to XSDB register False Paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS*/I_YESLUT6.I_YES_OREG.O_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
|
||||
|
||||
|
||||
##
|
||||
## Waivers
|
||||
##
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_xsdb_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_ila_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-15 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~R} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*"} ]]
|
||||
|
||||
+30
@@ -0,0 +1,30 @@
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
#create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srlD/S1*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
|
||||
+76
@@ -0,0 +1,76 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module bd_3e86_0_ila_lib_0 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [15 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [15 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [0 : 0] probe6;
|
||||
input [0 : 0] probe7;
|
||||
|
||||
|
||||
endmodule
|
||||
+4254
File diff suppressed because it is too large
Load Diff
+2882
File diff suppressed because it is too large
Load Diff
+113892
File diff suppressed because it is too large
Load Diff
+4882
File diff suppressed because it is too large
Load Diff
+4118
File diff suppressed because it is too large
Load Diff
+4178
File diff suppressed because it is too large
Load Diff
+91
@@ -0,0 +1,91 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3e86_0.bd
|
||||
//Design : bd_3e86_0
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "bd_3e86_0,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_3e86_0,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}" *) (* HW_HANDOFF = "design_1_syn_system_ila_0_2.hwdef" *)
|
||||
module bd_3e86_0
|
||||
(SLOT_0_AXIS_tdata,
|
||||
SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tready,
|
||||
SLOT_0_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid,
|
||||
clk,
|
||||
resetn);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_0_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_0_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TLAST" *) input SLOT_0_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TREADY" *) input SLOT_0_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TVALID" *) input SLOT_0_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_1_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST" *) input SLOT_1_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY" *) input SLOT_1_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID" *) input SLOT_1_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXIS:SLOT_1_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input resetn;
|
||||
|
||||
wire [15:0]Conn1_TDATA;
|
||||
wire Conn1_TLAST;
|
||||
wire Conn1_TREADY;
|
||||
wire Conn1_TVALID;
|
||||
wire [15:0]Conn_TDATA;
|
||||
wire Conn_TLAST;
|
||||
wire Conn_TREADY;
|
||||
wire Conn_TVALID;
|
||||
wire clk_1;
|
||||
wire [15:0]net_slot_0_axis_tdata;
|
||||
wire net_slot_0_axis_tlast;
|
||||
wire net_slot_0_axis_tready;
|
||||
wire net_slot_0_axis_tvalid;
|
||||
wire [15:0]net_slot_1_axis_tdata;
|
||||
wire net_slot_1_axis_tlast;
|
||||
wire net_slot_1_axis_tready;
|
||||
wire net_slot_1_axis_tvalid;
|
||||
wire resetn_1;
|
||||
|
||||
assign Conn1_TDATA = SLOT_1_AXIS_tdata[15:0];
|
||||
assign Conn1_TLAST = SLOT_1_AXIS_tlast;
|
||||
assign Conn1_TREADY = SLOT_1_AXIS_tready;
|
||||
assign Conn1_TVALID = SLOT_1_AXIS_tvalid;
|
||||
assign Conn_TDATA = SLOT_0_AXIS_tdata[15:0];
|
||||
assign Conn_TLAST = SLOT_0_AXIS_tlast;
|
||||
assign Conn_TREADY = SLOT_0_AXIS_tready;
|
||||
assign Conn_TVALID = SLOT_0_AXIS_tvalid;
|
||||
assign clk_1 = clk;
|
||||
assign resetn_1 = resetn;
|
||||
bd_3e86_0_g_inst_0 g_inst
|
||||
(.aclk(clk_1),
|
||||
.aresetn(resetn_1),
|
||||
.m_slot_0_axis_tdata(net_slot_0_axis_tdata),
|
||||
.m_slot_0_axis_tlast(net_slot_0_axis_tlast),
|
||||
.m_slot_0_axis_tready(net_slot_0_axis_tready),
|
||||
.m_slot_0_axis_tvalid(net_slot_0_axis_tvalid),
|
||||
.m_slot_1_axis_tdata(net_slot_1_axis_tdata),
|
||||
.m_slot_1_axis_tlast(net_slot_1_axis_tlast),
|
||||
.m_slot_1_axis_tready(net_slot_1_axis_tready),
|
||||
.m_slot_1_axis_tvalid(net_slot_1_axis_tvalid),
|
||||
.slot_0_axis_tdata(Conn_TDATA),
|
||||
.slot_0_axis_tlast(Conn_TLAST),
|
||||
.slot_0_axis_tready(Conn_TREADY),
|
||||
.slot_0_axis_tvalid(Conn_TVALID),
|
||||
.slot_1_axis_tdata(Conn1_TDATA),
|
||||
.slot_1_axis_tlast(Conn1_TLAST),
|
||||
.slot_1_axis_tready(Conn1_TREADY),
|
||||
.slot_1_axis_tvalid(Conn1_TVALID));
|
||||
bd_3e86_0_ila_lib_0 ila_lib
|
||||
(.clk(clk_1),
|
||||
.probe0(net_slot_0_axis_tdata),
|
||||
.probe1(net_slot_0_axis_tvalid),
|
||||
.probe2(net_slot_0_axis_tready),
|
||||
.probe3(net_slot_0_axis_tlast),
|
||||
.probe4(net_slot_1_axis_tdata),
|
||||
.probe5(net_slot_1_axis_tvalid),
|
||||
.probe6(net_slot_1_axis_tready),
|
||||
.probe7(net_slot_1_axis_tlast));
|
||||
endmodule
|
||||
+91
@@ -0,0 +1,91 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3e86_0.bd
|
||||
//Design : bd_3e86_0
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "bd_3e86_0,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_3e86_0,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}" *) (* HW_HANDOFF = "design_1_syn_system_ila_0_2.hwdef" *)
|
||||
module bd_3e86_0
|
||||
(SLOT_0_AXIS_tdata,
|
||||
SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tready,
|
||||
SLOT_0_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid,
|
||||
clk,
|
||||
resetn);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_0_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_0_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TLAST" *) input SLOT_0_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TREADY" *) input SLOT_0_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TVALID" *) input SLOT_0_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_1_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST" *) input SLOT_1_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY" *) input SLOT_1_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID" *) input SLOT_1_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXIS:SLOT_1_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input resetn;
|
||||
|
||||
wire [15:0]Conn1_TDATA;
|
||||
wire Conn1_TLAST;
|
||||
wire Conn1_TREADY;
|
||||
wire Conn1_TVALID;
|
||||
wire [15:0]Conn_TDATA;
|
||||
wire Conn_TLAST;
|
||||
wire Conn_TREADY;
|
||||
wire Conn_TVALID;
|
||||
wire clk_1;
|
||||
wire [15:0]net_slot_0_axis_tdata;
|
||||
wire net_slot_0_axis_tlast;
|
||||
wire net_slot_0_axis_tready;
|
||||
wire net_slot_0_axis_tvalid;
|
||||
wire [15:0]net_slot_1_axis_tdata;
|
||||
wire net_slot_1_axis_tlast;
|
||||
wire net_slot_1_axis_tready;
|
||||
wire net_slot_1_axis_tvalid;
|
||||
wire resetn_1;
|
||||
|
||||
assign Conn1_TDATA = SLOT_1_AXIS_tdata[15:0];
|
||||
assign Conn1_TLAST = SLOT_1_AXIS_tlast;
|
||||
assign Conn1_TREADY = SLOT_1_AXIS_tready;
|
||||
assign Conn1_TVALID = SLOT_1_AXIS_tvalid;
|
||||
assign Conn_TDATA = SLOT_0_AXIS_tdata[15:0];
|
||||
assign Conn_TLAST = SLOT_0_AXIS_tlast;
|
||||
assign Conn_TREADY = SLOT_0_AXIS_tready;
|
||||
assign Conn_TVALID = SLOT_0_AXIS_tvalid;
|
||||
assign clk_1 = clk;
|
||||
assign resetn_1 = resetn;
|
||||
bd_3e86_0_g_inst_0 g_inst
|
||||
(.aclk(clk_1),
|
||||
.aresetn(resetn_1),
|
||||
.m_slot_0_axis_tdata(net_slot_0_axis_tdata),
|
||||
.m_slot_0_axis_tlast(net_slot_0_axis_tlast),
|
||||
.m_slot_0_axis_tready(net_slot_0_axis_tready),
|
||||
.m_slot_0_axis_tvalid(net_slot_0_axis_tvalid),
|
||||
.m_slot_1_axis_tdata(net_slot_1_axis_tdata),
|
||||
.m_slot_1_axis_tlast(net_slot_1_axis_tlast),
|
||||
.m_slot_1_axis_tready(net_slot_1_axis_tready),
|
||||
.m_slot_1_axis_tvalid(net_slot_1_axis_tvalid),
|
||||
.slot_0_axis_tdata(Conn_TDATA),
|
||||
.slot_0_axis_tlast(Conn_TLAST),
|
||||
.slot_0_axis_tready(Conn_TREADY),
|
||||
.slot_0_axis_tvalid(Conn_TVALID),
|
||||
.slot_1_axis_tdata(Conn1_TDATA),
|
||||
.slot_1_axis_tlast(Conn1_TLAST),
|
||||
.slot_1_axis_tready(Conn1_TREADY),
|
||||
.slot_1_axis_tvalid(Conn1_TVALID));
|
||||
bd_3e86_0_ila_lib_0 ila_lib
|
||||
(.clk(clk_1),
|
||||
.probe0(net_slot_0_axis_tdata),
|
||||
.probe1(net_slot_0_axis_tvalid),
|
||||
.probe2(net_slot_0_axis_tready),
|
||||
.probe3(net_slot_0_axis_tlast),
|
||||
.probe4(net_slot_1_axis_tdata),
|
||||
.probe5(net_slot_1_axis_tvalid),
|
||||
.probe6(net_slot_1_axis_tready),
|
||||
.probe7(net_slot_1_axis_tlast));
|
||||
endmodule
|
||||
+74
-274
@@ -137,22 +137,6 @@
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:monitor spirit:interfaceMode="slave"/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDEST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tdest</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
@@ -161,22 +145,6 @@
|
||||
<spirit:name>SLOT_0_AXIS_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tstrb</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TKEEP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tkeep</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
@@ -185,14 +153,6 @@
|
||||
<spirit:name>SLOT_0_AXIS_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tuser</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
@@ -336,22 +296,6 @@
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:monitor spirit:interfaceMode="slave"/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDEST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tdest</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
@@ -360,22 +304,6 @@
|
||||
<spirit:name>SLOT_1_AXIS_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tstrb</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TKEEP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tkeep</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
@@ -384,14 +312,6 @@
|
||||
<spirit:name>SLOT_1_AXIS_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tuser</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
@@ -536,14 +456,14 @@
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>bd_3e86</spirit:modelName>
|
||||
<spirit:modelName>bd_3e86_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:27 UTC 2024</spirit:value>
|
||||
<spirit:value>Wed Nov 20 15:36:51 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -551,6 +471,24 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_elaboratebd</spirit:name>
|
||||
<spirit:displayName>Elaborate BD</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:elaborate.bd</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_elaboratebd_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Oct 29 09:39:07 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:9825d521</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_elaborateports</spirit:name>
|
||||
<spirit:displayName>Elaborate Ports</spirit:displayName>
|
||||
@@ -579,7 +517,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:12:08 UTC 2024</spirit:value>
|
||||
<spirit:value>Wed Nov 20 15:42:15 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -591,14 +529,14 @@
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:modelName>bd_3e86</spirit:modelName>
|
||||
<spirit:modelName>bd_3e86_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_synthesisconstraints_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:27 UTC 2024</spirit:value>
|
||||
<spirit:value>Wed Nov 20 15:36:51 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -651,7 +589,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:27 UTC 2024</spirit:value>
|
||||
<spirit:value>Wed Nov 20 15:36:51 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -674,92 +612,12 @@
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tdest</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tstrb</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tkeep</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -775,7 +633,7 @@
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tuser</spirit:name>
|
||||
<spirit:name>SLOT_0_AXIS_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -794,30 +652,25 @@
|
||||
<spirit:name>SLOT_0_AXIS_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
@@ -827,92 +680,12 @@
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tdest</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tstrb</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tkeep</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -928,7 +701,7 @@
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tuser</spirit:name>
|
||||
<spirit:name>SLOT_1_AXIS_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -947,30 +720,25 @@
|
||||
<spirit:name>SLOT_1_AXIS_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
@@ -991,6 +759,9 @@
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
@@ -2142,6 +1913,13 @@
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_elaboratebd_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>bd_1/bd_3e86_0.bd</spirit:name>
|
||||
<spirit:userFileType>block_diagram</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_elaborateports_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -36454,16 +36232,38 @@
|
||||
<xilinx:tag xilinx:name="driver_mode">mixed</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESETN.POLARITY" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESETN.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TKEEP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TLAST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TREADY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TSTRB" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TDEST_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TID_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TKEEP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TLAST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TREADY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TSTRB" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TDEST_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TID_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MON_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_MONITOR_SLOTS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_APC_EN" xilinx:valueSource="user"/>
|
||||
|
||||
+21625
-21625
File diff suppressed because it is too large
Load Diff
+45173
-45173
File diff suppressed because it is too large
Load Diff
+2
-2
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:12:03 2024
|
||||
// Date : Wed Nov 20 16:42:10 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_system_ila_0_2/design_1_syn_system_ila_0_2_stub.v
|
||||
@@ -14,7 +14,7 @@
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "bd_3e86,Vivado 2023.1" *)
|
||||
(* X_CORE_INFO = "bd_3e86_0,Vivado 2023.1" *)
|
||||
module design_1_syn_system_ila_0_2(clk, SLOT_0_AXIS_tdata, SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tvalid, SLOT_0_AXIS_tready, SLOT_1_AXIS_tdata, SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tvalid, SLOT_1_AXIS_tready, resetn)
|
||||
|
||||
+2
-2
@@ -2,7 +2,7 @@
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:12:03 2024
|
||||
-- Date : Wed Nov 20 16:42:10 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_system_ila_0_2/design_1_syn_system_ila_0_2_stub.vhdl
|
||||
@@ -35,6 +35,6 @@ attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,SLOT_0_AXIS_tdata[15:0],SLOT_0_AXIS_tlast,SLOT_0_AXIS_tvalid,SLOT_0_AXIS_tready,SLOT_1_AXIS_tdata[15:0],SLOT_1_AXIS_tlast,SLOT_1_AXIS_tvalid,SLOT_1_AXIS_tready,resetn";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "bd_3e86,Vivado 2023.1";
|
||||
attribute X_CORE_INFO of stub : architecture is "bd_3e86_0,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
|
||||
+163
-163
@@ -50,168 +50,168 @@
|
||||
// IP VLNV: xilinx.com:ip:system_ila:1.1
|
||||
// IP Revision: 14
|
||||
|
||||
(* X_CORE_INFO = "bd_3e86,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "design_1_syn_system_ila_0_2,bd_3e86,{}" *)
|
||||
(* CORE_GENERATION_INFO = "design_1_syn_system_ila_0_2,bd_3e86,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=system_ila,x_ipVersion=1.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_SLOT=0,C_SLOT_15_TYPE=0,C_SLOT_14_TYPE=0,C_SLOT_13_TYPE=0,C_SLOT_12_TYPE=0,C_SLOT_11_TYPE=0,C_SLOT_10_TYPE=0,C_SLOT_9_TYPE=0,C_SLOT_8_TYPE=0,C_SLOT_7_TYPE=0,C_SLOT_6_TYPE=0,C_SLOT_5_TYPE=0,C_SLOT_4_TYPE=0,C_SLOT_3_TYPE=0,C_SLOT_2_TYPE=0,C_SLOT_1_TYPE=0,C_SLOT_0_T\
|
||||
YPE=0,C_SLOT_0_MAX_RD_BURSTS=2,C_SLOT_0_MAX_WR_BURSTS=2,C_SLOT_1_MAX_RD_BURSTS=2,C_SLOT_1_MAX_WR_BURSTS=2,C_SLOT_2_MAX_RD_BURSTS=2,C_SLOT_2_MAX_WR_BURSTS=2,C_SLOT_3_MAX_RD_BURSTS=2,C_SLOT_3_MAX_WR_BURSTS=2,C_SLOT_4_MAX_RD_BURSTS=2,C_SLOT_4_MAX_WR_BURSTS=2,C_SLOT_5_MAX_RD_BURSTS=2,C_SLOT_5_MAX_WR_BURSTS=2,C_SLOT_6_MAX_RD_BURSTS=2,C_SLOT_6_MAX_WR_BURSTS=2,C_SLOT_7_MAX_RD_BURSTS=2,C_SLOT_7_MAX_WR_BURSTS=2,C_SLOT_8_MAX_RD_BURSTS=2,C_SLOT_8_MAX_WR_BURSTS=2,C_SLOT_9_MAX_RD_BURSTS=2,C_SLOT_9_MAX_WR_BUR\
|
||||
STS=2,C_SLOT_10_MAX_RD_BURSTS=2,C_SLOT_10_MAX_WR_BURSTS=2,C_SLOT_11_MAX_RD_BURSTS=2,C_SLOT_11_MAX_WR_BURSTS=2,C_SLOT_12_MAX_RD_BURSTS=2,C_SLOT_12_MAX_WR_BURSTS=2,C_SLOT_13_MAX_RD_BURSTS=2,C_SLOT_13_MAX_WR_BURSTS=2,C_SLOT_14_MAX_RD_BURSTS=2,C_SLOT_14_MAX_WR_BURSTS=2,C_SLOT_15_MAX_RD_BURSTS=2,C_SLOT_15_MAX_WR_BURSTS=2,C_SLOT_0_TXN_CNTR_EN=1,C_SLOT_1_TXN_CNTR_EN=1,C_SLOT_2_TXN_CNTR_EN=1,C_SLOT_3_TXN_CNTR_EN=1,C_SLOT_4_TXN_CNTR_EN=1,C_SLOT_5_TXN_CNTR_EN=1,C_SLOT_6_TXN_CNTR_EN=1,C_SLOT_7_TXN_CNTR_EN=\
|
||||
1,C_SLOT_8_TXN_CNTR_EN=1,C_SLOT_9_TXN_CNTR_EN=1,C_SLOT_10_TXN_CNTR_EN=1,C_SLOT_11_TXN_CNTR_EN=1,C_SLOT_12_TXN_CNTR_EN=1,C_SLOT_13_TXN_CNTR_EN=1,C_SLOT_14_TXN_CNTR_EN=1,C_SLOT_15_TXN_CNTR_EN=1,C_SLOT_0_APC_STS_EN=0,C_SLOT_1_APC_STS_EN=0,C_SLOT_2_APC_STS_EN=0,C_SLOT_3_APC_STS_EN=0,C_SLOT_4_APC_STS_EN=0,C_SLOT_5_APC_STS_EN=0,C_SLOT_6_APC_STS_EN=0,C_SLOT_7_APC_STS_EN=0,C_SLOT_8_APC_STS_EN=0,C_SLOT_9_APC_STS_EN=0,C_SLOT_10_APC_STS_EN=0,C_SLOT_11_APC_STS_EN=0,C_SLOT_12_APC_STS_EN=0,C_SLOT_13_APC_STS_E\
|
||||
N=0,C_SLOT_14_APC_STS_EN=0,C_SLOT_15_APC_STS_EN=0,C_SLOT_0_APC_EN=0,C_SLOT_1_APC_EN=0,C_SLOT_2_APC_EN=0,C_SLOT_3_APC_EN=0,C_SLOT_4_APC_EN=0,C_SLOT_5_APC_EN=0,C_SLOT_6_APC_EN=0,C_SLOT_7_APC_EN=0,C_SLOT_8_APC_EN=0,C_SLOT_9_APC_EN=0,C_SLOT_10_APC_EN=0,C_SLOT_11_APC_EN=0,C_SLOT_12_APC_EN=0,C_SLOT_13_APC_EN=0,C_SLOT_14_APC_EN=0,C_SLOT_15_APC_EN=0,C_SLOT_0_APC_MAX_AW_WAITS=0,C_SLOT_0_APC_MAX_AR_WAITS=0,C_SLOT_0_APC_MAX_W_WAITS=0,C_SLOT_0_APC_MAX_B_WAITS=0,C_SLOT_0_APC_MAX_R_WAITS=0,C_SLOT_0_APC_MAX_CO\
|
||||
NTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_0_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_0_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_0_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_AW_WAITS=0,C_SLOT_1_APC_MAX_AR_WAITS=0,C_SLOT_1_APC_MAX_W_WAITS=0,C_SLOT_1_APC_MAX_B_WAITS=0,C_SLOT_1_APC_MAX_R_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_1_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_AW_WAITS=0,\
|
||||
C_SLOT_2_APC_MAX_AR_WAITS=0,C_SLOT_2_APC_MAX_W_WAITS=0,C_SLOT_2_APC_MAX_B_WAITS=0,C_SLOT_2_APC_MAX_R_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_2_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_AW_WAITS=0,C_SLOT_3_APC_MAX_AR_WAITS=0,C_SLOT_3_APC_MAX_W_WAITS=0,C_SLOT_3_APC_MAX_B_WAITS=0,C_SLOT_3_APC_MAX_R_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_WLAST_TO_AWVA\
|
||||
LID_WAITS=0,C_SLOT_3_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_AW_WAITS=0,C_SLOT_4_APC_MAX_AR_WAITS=0,C_SLOT_4_APC_MAX_W_WAITS=0,C_SLOT_4_APC_MAX_B_WAITS=0,C_SLOT_4_APC_MAX_R_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_4_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_5_APC_MAX_AW_WAITS=0,C_SLOT_5_APC_MAX_AR_WAITS=0,C_SLOT_5_APC_MAX_W_WAITS=0,C_S\
|
||||
LOT_5_APC_MAX_B_WAITS=0,C_SLOT_5_APC_MAX_R_WAITS=0,C_SLOT_5_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_5_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_5_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_5_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_6_APC_MAX_AW_WAITS=0,C_SLOT_6_APC_MAX_AR_WAITS=0,C_SLOT_6_APC_MAX_W_WAITS=0,C_SLOT_6_APC_MAX_B_WAITS=0,C_SLOT_6_APC_MAX_R_WAITS=0,C_SLOT_6_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_6_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_6_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLO\
|
||||
T_6_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_7_APC_MAX_AW_WAITS=0,C_SLOT_7_APC_MAX_AR_WAITS=0,C_SLOT_7_APC_MAX_W_WAITS=0,C_SLOT_7_APC_MAX_B_WAITS=0,C_SLOT_7_APC_MAX_R_WAITS=0,C_SLOT_7_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_7_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_7_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_7_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_8_APC_MAX_AW_WAITS=0,C_SLOT_8_APC_MAX_AR_WAITS=0,C_SLOT_8_APC_MAX_W_WAITS=0,C_SLOT_8_APC_MAX_B_WAITS=0,C_SLOT_8_APC_MAX_R_WAITS=0,C_SLOT_\
|
||||
8_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_8_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_8_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_8_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_9_APC_MAX_AW_WAITS=0,C_SLOT_9_APC_MAX_AR_WAITS=0,C_SLOT_9_APC_MAX_W_WAITS=0,C_SLOT_9_APC_MAX_B_WAITS=0,C_SLOT_9_APC_MAX_R_WAITS=0,C_SLOT_9_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_9_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_9_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_9_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_10_APC_MA\
|
||||
X_AW_WAITS=0,C_SLOT_10_APC_MAX_AR_WAITS=0,C_SLOT_10_APC_MAX_W_WAITS=0,C_SLOT_10_APC_MAX_B_WAITS=0,C_SLOT_10_APC_MAX_R_WAITS=0,C_SLOT_10_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_10_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_10_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_10_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_11_APC_MAX_AW_WAITS=0,C_SLOT_11_APC_MAX_AR_WAITS=0,C_SLOT_11_APC_MAX_W_WAITS=0,C_SLOT_11_APC_MAX_B_WAITS=0,C_SLOT_11_APC_MAX_R_WAITS=0,C_SLOT_11_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_S\
|
||||
LOT_11_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_11_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_11_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_12_APC_MAX_AW_WAITS=0,C_SLOT_12_APC_MAX_AR_WAITS=0,C_SLOT_12_APC_MAX_W_WAITS=0,C_SLOT_12_APC_MAX_B_WAITS=0,C_SLOT_12_APC_MAX_R_WAITS=0,C_SLOT_12_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_12_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_12_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_12_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_13_APC_MAX_AW_WAITS=0,C_SLOT_13_APC_MAX_\
|
||||
AR_WAITS=0,C_SLOT_13_APC_MAX_W_WAITS=0,C_SLOT_13_APC_MAX_B_WAITS=0,C_SLOT_13_APC_MAX_R_WAITS=0,C_SLOT_13_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_13_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_13_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_13_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_14_APC_MAX_AW_WAITS=0,C_SLOT_14_APC_MAX_AR_WAITS=0,C_SLOT_14_APC_MAX_W_WAITS=0,C_SLOT_14_APC_MAX_B_WAITS=0,C_SLOT_14_APC_MAX_R_WAITS=0,C_SLOT_14_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_14_APC_MAX_WLAST_TO_AWVALID\
|
||||
_WAITS=0,C_SLOT_14_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_14_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_15_APC_MAX_AW_WAITS=0,C_SLOT_15_APC_MAX_AR_WAITS=0,C_SLOT_15_APC_MAX_W_WAITS=0,C_SLOT_15_APC_MAX_B_WAITS=0,C_SLOT_15_APC_MAX_R_WAITS=0,C_SLOT_15_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_15_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_15_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_15_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_BRAM_CNT=0.0,C_SLOT_0_AXI_AW_SEL_DATA=1,C_SLOT_0_AXI_W_SEL_DATA=1,C_SLOT_0_A\
|
||||
XI_B_SEL_DATA=1,C_SLOT_0_AXI_AR_SEL_DATA=1,C_SLOT_0_AXI_R_SEL_DATA=1,C_SLOT_1_AXI_AW_SEL_DATA=1,C_SLOT_1_AXI_W_SEL_DATA=1,C_SLOT_1_AXI_B_SEL_DATA=1,C_SLOT_1_AXI_AR_SEL_DATA=1,C_SLOT_1_AXI_R_SEL_DATA=1,C_SLOT_2_AXI_AW_SEL_DATA=1,C_SLOT_2_AXI_W_SEL_DATA=1,C_SLOT_2_AXI_B_SEL_DATA=1,C_SLOT_2_AXI_AR_SEL_DATA=1,C_SLOT_2_AXI_R_SEL_DATA=1,C_SLOT_3_AXI_AW_SEL_DATA=1,C_SLOT_3_AXI_W_SEL_DATA=1,C_SLOT_3_AXI_B_SEL_DATA=1,C_SLOT_3_AXI_AR_SEL_DATA=1,C_SLOT_3_AXI_R_SEL_DATA=1,C_SLOT_4_AXI_AW_SEL_DATA=1,C_SLOT_4\
|
||||
_AXI_W_SEL_DATA=1,C_SLOT_4_AXI_B_SEL_DATA=1,C_SLOT_4_AXI_AR_SEL_DATA=1,C_SLOT_4_AXI_R_SEL_DATA=1,C_SLOT_5_AXI_AW_SEL_DATA=1,C_SLOT_5_AXI_W_SEL_DATA=1,C_SLOT_5_AXI_B_SEL_DATA=1,C_SLOT_5_AXI_AR_SEL_DATA=1,C_SLOT_5_AXI_R_SEL_DATA=1,C_SLOT_6_AXI_AW_SEL_DATA=1,C_SLOT_6_AXI_W_SEL_DATA=1,C_SLOT_6_AXI_B_SEL_DATA=1,C_SLOT_6_AXI_AR_SEL_DATA=1,C_SLOT_6_AXI_R_SEL_DATA=1,C_SLOT_7_AXI_AW_SEL_DATA=1,C_SLOT_7_AXI_W_SEL_DATA=1,C_SLOT_7_AXI_B_SEL_DATA=1,C_SLOT_7_AXI_AR_SEL_DATA=1,C_SLOT_7_AXI_R_SEL_DATA=1,C_SLOT_\
|
||||
8_AXI_AW_SEL_DATA=1,C_SLOT_8_AXI_W_SEL_DATA=1,C_SLOT_8_AXI_B_SEL_DATA=1,C_SLOT_8_AXI_AR_SEL_DATA=1,C_SLOT_8_AXI_R_SEL_DATA=1,C_SLOT_9_AXI_AW_SEL_DATA=1,C_SLOT_9_AXI_W_SEL_DATA=1,C_SLOT_9_AXI_B_SEL_DATA=1,C_SLOT_9_AXI_AR_SEL_DATA=1,C_SLOT_9_AXI_R_SEL_DATA=1,C_SLOT_10_AXI_AW_SEL_DATA=1,C_SLOT_10_AXI_W_SEL_DATA=1,C_SLOT_10_AXI_B_SEL_DATA=1,C_SLOT_10_AXI_AR_SEL_DATA=1,C_SLOT_10_AXI_R_SEL_DATA=1,C_SLOT_11_AXI_AW_SEL_DATA=1,C_SLOT_11_AXI_W_SEL_DATA=1,C_SLOT_11_AXI_B_SEL_DATA=1,C_SLOT_11_AXI_AR_SEL_DAT\
|
||||
A=1,C_SLOT_11_AXI_R_SEL_DATA=1,C_SLOT_12_AXI_AW_SEL_DATA=1,C_SLOT_12_AXI_W_SEL_DATA=1,C_SLOT_12_AXI_B_SEL_DATA=1,C_SLOT_12_AXI_AR_SEL_DATA=1,C_SLOT_12_AXI_R_SEL_DATA=1,C_SLOT_13_AXI_AW_SEL_DATA=1,C_SLOT_13_AXI_W_SEL_DATA=1,C_SLOT_13_AXI_B_SEL_DATA=1,C_SLOT_13_AXI_AR_SEL_DATA=1,C_SLOT_13_AXI_R_SEL_DATA=1,C_SLOT_14_AXI_AW_SEL_DATA=1,C_SLOT_14_AXI_W_SEL_DATA=1,C_SLOT_14_AXI_B_SEL_DATA=1,C_SLOT_14_AXI_AR_SEL_DATA=1,C_SLOT_14_AXI_R_SEL_DATA=1,C_SLOT_15_AXI_AW_SEL_DATA=1,C_SLOT_15_AXI_W_SEL_DATA=1,C_S\
|
||||
LOT_15_AXI_B_SEL_DATA=1,C_SLOT_15_AXI_AR_SEL_DATA=1,C_SLOT_15_AXI_R_SEL_DATA=1,C_SLOT_0_AXI_AW_SEL_TRIG=1,C_SLOT_0_AXI_W_SEL_TRIG=1,C_SLOT_0_AXI_B_SEL_TRIG=1,C_SLOT_0_AXI_AR_SEL_TRIG=1,C_SLOT_0_AXI_R_SEL_TRIG=1,C_SLOT_1_AXI_AW_SEL_TRIG=1,C_SLOT_1_AXI_W_SEL_TRIG=1,C_SLOT_1_AXI_B_SEL_TRIG=1,C_SLOT_1_AXI_AR_SEL_TRIG=1,C_SLOT_1_AXI_R_SEL_TRIG=1,C_SLOT_2_AXI_AW_SEL_TRIG=1,C_SLOT_2_AXI_W_SEL_TRIG=1,C_SLOT_2_AXI_B_SEL_TRIG=1,C_SLOT_2_AXI_AR_SEL_TRIG=1,C_SLOT_2_AXI_R_SEL_TRIG=1,C_SLOT_3_AXI_AW_SEL_TRIG=\
|
||||
1,C_SLOT_3_AXI_W_SEL_TRIG=1,C_SLOT_3_AXI_B_SEL_TRIG=1,C_SLOT_3_AXI_AR_SEL_TRIG=1,C_SLOT_3_AXI_R_SEL_TRIG=1,C_SLOT_4_AXI_AW_SEL_TRIG=1,C_SLOT_4_AXI_W_SEL_TRIG=1,C_SLOT_4_AXI_B_SEL_TRIG=1,C_SLOT_4_AXI_AR_SEL_TRIG=1,C_SLOT_4_AXI_R_SEL_TRIG=1,C_SLOT_5_AXI_AW_SEL_TRIG=1,C_SLOT_5_AXI_W_SEL_TRIG=1,C_SLOT_5_AXI_B_SEL_TRIG=1,C_SLOT_5_AXI_AR_SEL_TRIG=1,C_SLOT_5_AXI_R_SEL_TRIG=1,C_SLOT_6_AXI_AW_SEL_TRIG=1,C_SLOT_6_AXI_W_SEL_TRIG=1,C_SLOT_6_AXI_B_SEL_TRIG=1,C_SLOT_6_AXI_AR_SEL_TRIG=1,C_SLOT_6_AXI_R_SEL_TRIG\
|
||||
=1,C_SLOT_7_AXI_AW_SEL_TRIG=1,C_SLOT_7_AXI_W_SEL_TRIG=1,C_SLOT_7_AXI_B_SEL_TRIG=1,C_SLOT_7_AXI_AR_SEL_TRIG=1,C_SLOT_7_AXI_R_SEL_TRIG=1,C_SLOT_8_AXI_AW_SEL_TRIG=1,C_SLOT_8_AXI_W_SEL_TRIG=1,C_SLOT_8_AXI_B_SEL_TRIG=1,C_SLOT_8_AXI_AR_SEL_TRIG=1,C_SLOT_8_AXI_R_SEL_TRIG=1,C_SLOT_9_AXI_AW_SEL_TRIG=1,C_SLOT_9_AXI_W_SEL_TRIG=1,C_SLOT_9_AXI_B_SEL_TRIG=1,C_SLOT_9_AXI_AR_SEL_TRIG=1,C_SLOT_9_AXI_R_SEL_TRIG=1,C_SLOT_10_AXI_AW_SEL_TRIG=1,C_SLOT_10_AXI_W_SEL_TRIG=1,C_SLOT_10_AXI_B_SEL_TRIG=1,C_SLOT_10_AXI_AR_SE\
|
||||
L_TRIG=1,C_SLOT_10_AXI_R_SEL_TRIG=1,C_SLOT_11_AXI_AW_SEL_TRIG=1,C_SLOT_11_AXI_W_SEL_TRIG=1,C_SLOT_11_AXI_B_SEL_TRIG=1,C_SLOT_11_AXI_AR_SEL_TRIG=1,C_SLOT_11_AXI_R_SEL_TRIG=1,C_SLOT_12_AXI_AW_SEL_TRIG=1,C_SLOT_12_AXI_W_SEL_TRIG=1,C_SLOT_12_AXI_B_SEL_TRIG=1,C_SLOT_12_AXI_AR_SEL_TRIG=1,C_SLOT_12_AXI_R_SEL_TRIG=1,C_SLOT_13_AXI_AW_SEL_TRIG=1,C_SLOT_13_AXI_W_SEL_TRIG=1,C_SLOT_13_AXI_B_SEL_TRIG=1,C_SLOT_13_AXI_AR_SEL_TRIG=1,C_SLOT_13_AXI_R_SEL_TRIG=1,C_SLOT_14_AXI_AW_SEL_TRIG=1,C_SLOT_14_AXI_W_SEL_TRIG=\
|
||||
1,C_SLOT_14_AXI_B_SEL_TRIG=1,C_SLOT_14_AXI_AR_SEL_TRIG=1,C_SLOT_14_AXI_R_SEL_TRIG=1,C_SLOT_15_AXI_AW_SEL_TRIG=1,C_SLOT_15_AXI_W_SEL_TRIG=1,C_SLOT_15_AXI_B_SEL_TRIG=1,C_SLOT_15_AXI_AR_SEL_TRIG=1,C_SLOT_15_AXI_R_SEL_TRIG=1,C_SLOT_0_AXI_AW_SEL=1,C_SLOT_0_AXI_W_SEL=1,C_SLOT_0_AXI_B_SEL=1,C_SLOT_0_AXI_AR_SEL=1,C_SLOT_0_AXI_R_SEL=1,C_SLOT_1_AXI_AW_SEL=1,C_SLOT_1_AXI_W_SEL=1,C_SLOT_1_AXI_B_SEL=1,C_SLOT_1_AXI_AR_SEL=1,C_SLOT_1_AXI_R_SEL=1,C_SLOT_2_AXI_AW_SEL=1,C_SLOT_2_AXI_W_SEL=1,C_SLOT_2_AXI_B_SEL=1,C\
|
||||
_SLOT_2_AXI_AR_SEL=1,C_SLOT_2_AXI_R_SEL=1,C_SLOT_3_AXI_AW_SEL=1,C_SLOT_3_AXI_W_SEL=1,C_SLOT_3_AXI_B_SEL=1,C_SLOT_3_AXI_AR_SEL=1,C_SLOT_3_AXI_R_SEL=1,C_SLOT_4_AXI_AW_SEL=1,C_SLOT_4_AXI_W_SEL=1,C_SLOT_4_AXI_B_SEL=1,C_SLOT_4_AXI_AR_SEL=1,C_SLOT_4_AXI_R_SEL=1,C_SLOT_5_AXI_AW_SEL=1,C_SLOT_5_AXI_W_SEL=1,C_SLOT_5_AXI_B_SEL=1,C_SLOT_5_AXI_AR_SEL=1,C_SLOT_5_AXI_R_SEL=1,C_SLOT_6_AXI_AW_SEL=1,C_SLOT_6_AXI_W_SEL=1,C_SLOT_6_AXI_B_SEL=1,C_SLOT_6_AXI_AR_SEL=1,C_SLOT_6_AXI_R_SEL=1,C_SLOT_7_AXI_AW_SEL=1,C_SLOT_7\
|
||||
_AXI_W_SEL=1,C_SLOT_7_AXI_B_SEL=1,C_SLOT_7_AXI_AR_SEL=1,C_SLOT_7_AXI_R_SEL=1,C_SLOT_8_AXI_AW_SEL=1,C_SLOT_8_AXI_W_SEL=1,C_SLOT_8_AXI_B_SEL=1,C_SLOT_8_AXI_AR_SEL=1,C_SLOT_8_AXI_R_SEL=1,C_SLOT_9_AXI_AW_SEL=1,C_SLOT_9_AXI_W_SEL=1,C_SLOT_9_AXI_B_SEL=1,C_SLOT_9_AXI_AR_SEL=1,C_SLOT_9_AXI_R_SEL=1,C_SLOT_10_AXI_AW_SEL=1,C_SLOT_10_AXI_W_SEL=1,C_SLOT_10_AXI_B_SEL=1,C_SLOT_10_AXI_AR_SEL=1,C_SLOT_10_AXI_R_SEL=1,C_SLOT_11_AXI_AW_SEL=1,C_SLOT_11_AXI_W_SEL=1,C_SLOT_11_AXI_B_SEL=1,C_SLOT_11_AXI_AR_SEL=1,C_SLOT_\
|
||||
11_AXI_R_SEL=1,C_SLOT_12_AXI_AW_SEL=1,C_SLOT_12_AXI_W_SEL=1,C_SLOT_12_AXI_B_SEL=1,C_SLOT_12_AXI_AR_SEL=1,C_SLOT_12_AXI_R_SEL=1,C_SLOT_13_AXI_AW_SEL=1,C_SLOT_13_AXI_W_SEL=1,C_SLOT_13_AXI_B_SEL=1,C_SLOT_13_AXI_AR_SEL=1,C_SLOT_13_AXI_R_SEL=1,C_SLOT_14_AXI_AW_SEL=1,C_SLOT_14_AXI_W_SEL=1,C_SLOT_14_AXI_B_SEL=1,C_SLOT_14_AXI_AR_SEL=1,C_SLOT_14_AXI_R_SEL=1,C_SLOT_15_AXI_AW_SEL=1,C_SLOT_15_AXI_W_SEL=1,C_SLOT_15_AXI_B_SEL=1,C_SLOT_15_AXI_AR_SEL=1,C_SLOT_15_AXI_R_SEL=1,C_SLOT_0_AXI_DATA_SEL=1,C_SLOT_1_AXI_\
|
||||
DATA_SEL=1,C_SLOT_2_AXI_DATA_SEL=1,C_SLOT_3_AXI_DATA_SEL=1,C_SLOT_4_AXI_DATA_SEL=1,C_SLOT_5_AXI_DATA_SEL=1,C_SLOT_6_AXI_DATA_SEL=1,C_SLOT_7_AXI_DATA_SEL=1,C_SLOT_8_AXI_DATA_SEL=1,C_SLOT_9_AXI_DATA_SEL=1,C_SLOT_10_AXI_DATA_SEL=1,C_SLOT_11_AXI_DATA_SEL=1,C_SLOT_12_AXI_DATA_SEL=1,C_SLOT_13_AXI_DATA_SEL=1,C_SLOT_14_AXI_DATA_SEL=1,C_SLOT_15_AXI_DATA_SEL=1,C_SLOT_0_AXI_TRIG_SEL=1,C_SLOT_1_AXI_TRIG_SEL=1,C_SLOT_2_AXI_TRIG_SEL=1,C_SLOT_3_AXI_TRIG_SEL=1,C_SLOT_4_AXI_TRIG_SEL=1,C_SLOT_5_AXI_TRIG_SEL=1,C_S\
|
||||
LOT_6_AXI_TRIG_SEL=1,C_SLOT_7_AXI_TRIG_SEL=1,C_SLOT_8_AXI_TRIG_SEL=1,C_SLOT_9_AXI_TRIG_SEL=1,C_SLOT_10_AXI_TRIG_SEL=1,C_SLOT_11_AXI_TRIG_SEL=1,C_SLOT_12_AXI_TRIG_SEL=1,C_SLOT_13_AXI_TRIG_SEL=1,C_SLOT_14_AXI_TRIG_SEL=1,C_SLOT_15_AXI_TRIG_SEL=1,C_PROBE1023_TYPE=0,C_PROBE1022_TYPE=0,C_PROBE1021_TYPE=0,C_PROBE1020_TYPE=0,C_PROBE1019_TYPE=0,C_PROBE1018_TYPE=0,C_PROBE1017_TYPE=0,C_PROBE1016_TYPE=0,C_PROBE1015_TYPE=0,C_PROBE1014_TYPE=0,C_PROBE1013_TYPE=0,C_PROBE1012_TYPE=0,C_PROBE1011_TYPE=0,C_PROBE101\
|
||||
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|
||||
_PROBE529_WIDTH=1,C_PROBE528_WIDTH=1,C_PROBE527_WIDTH=1,C_PROBE526_WIDTH=1,C_PROBE525_WIDTH=1,C_PROBE524_WIDTH=1,C_PROBE523_WIDTH=1,C_PROBE522_WIDTH=1,C_PROBE521_WIDTH=1,C_PROBE520_WIDTH=1,C_PROBE519_WIDTH=1,C_PROBE518_WIDTH=1,C_PROBE517_WIDTH=1,C_PROBE516_WIDTH=1,C_PROBE515_WIDTH=1,C_PROBE514_WIDTH=1,C_PROBE513_WIDTH=1,C_PROBE512_WIDTH=1,C_PROBE511_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE504_WIDTH=1,C_PROBE\
|
||||
503_WIDTH=1,C_PROBE502_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE500_WIDTH=1,C_PROBE499_WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE477_WI\
|
||||
DTH=1,C_PROBE476_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE474_WIDTH=1,C_PROBE473_WIDTH=1,C_PROBE472_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE454_WIDTH=1,C_PROBE453_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE451_WIDTH=1,\
|
||||
C_PROBE450_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE447_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE425_WIDTH=1,C_PROB\
|
||||
E424_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE398_W\
|
||||
IDTH=1,C_PROBE397_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE395_WIDTH=1,C_PROBE394_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE372_WIDTH=1\
|
||||
,C_PROBE371_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE368_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE354_WIDTH=1,C_PROBE353_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE346_WIDTH=1,C_PRO\
|
||||
BE345_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE319_\
|
||||
WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE293_WIDTH=\
|
||||
1,C_PROBE292_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE267_WIDTH=1,C_PR\
|
||||
OBE266_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE254_WIDTH=1,C_PROBE253_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE240\
|
||||
_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE214_WIDTH\
|
||||
=1,C_PROBE213_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE188_WIDTH=1,C_P\
|
||||
ROBE187_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE16\
|
||||
1_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE154_WIDTH=1,C_PROBE153_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE135_WIDT\
|
||||
H=1,C_PROBE134_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE109_WIDTH=1,C_\
|
||||
PROBE108_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE\
|
||||
81_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE53_WIDTH=1,C_P\
|
||||
ROBE52_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE25_WIDTH=1\
|
||||
,C_PROBE24_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE0_WIDTH=1,C_DATA_DEPTH=1024,C_NUM_OF_PROBES=1,C_XLNX_HW_PROBE_INFO=DE\
|
||||
FAULT,Component_Name=design_1_syn_system_ila_0_2,C_PROBE70_WIDTH=1,C_TRIGOUT_EN=false,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,C_DDR_CLK_GEN=FALSE,C_EN_DDR_ILA=FALSE,C_ADV_TRIGGER=FALSE,C_PROBE1023_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1009_MU_CNT=1,C\
|
||||
_PROBE1008_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE984_M\
|
||||
U_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE959_M\
|
||||
U_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE934_M\
|
||||
U_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE909_M\
|
||||
U_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE884_M\
|
||||
U_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE859_M\
|
||||
U_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE834_M\
|
||||
U_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE809_M\
|
||||
U_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE784_M\
|
||||
U_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE759_M\
|
||||
U_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE734_M\
|
||||
U_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE709_M\
|
||||
U_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE684_M\
|
||||
U_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE659_M\
|
||||
U_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE634_M\
|
||||
U_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE609_M\
|
||||
U_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE584_M\
|
||||
U_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE559_M\
|
||||
U_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE534_M\
|
||||
U_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE509_M\
|
||||
U_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE484_M\
|
||||
U_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE459_M\
|
||||
U_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE434_M\
|
||||
U_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE409_M\
|
||||
U_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE384_M\
|
||||
U_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE359_M\
|
||||
U_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE334_M\
|
||||
U_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE309_M\
|
||||
U_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE284_M\
|
||||
U_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE259_M\
|
||||
U_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE234_M\
|
||||
U_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE209_M\
|
||||
U_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE184_M\
|
||||
U_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE159_M\
|
||||
U_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE134_M\
|
||||
U_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE109_M\
|
||||
U_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE8\
|
||||
3_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE57_MU_C\
|
||||
NT=1,C_PROBE56_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE31_MU_CNT=1,C\
|
||||
_PROBE30_MU_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE4_MU_\
|
||||
CNT=1,C_PROBE3_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE0_MU_CNT=1,C_TRIGIN_EN=false,EN_BRAM_DRC=TRUE,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_NUM_MONITOR_SLOTS=2,C_SLOT_0_AXI_ARUSER_WIDTH=1,C_SLOT_0_AXI_RUSER_WIDTH=1,C_SLOT_0_AXI_AWUSER_WIDTH=1,C_SLOT_0_AXI_WUSER_WIDTH=1,C_SLOT_0_AXI_BUSER_WIDTH=1,C_SLOT_0_AXI_ID_WIDTH=AUTO,C_SLOT_0_AXI_DATA_WIDTH=AUTO,C_SLOT_0_AXI_ADDR_WIDTH=AUTO,C_SLOT_0_AXI_PROTOCOL=AXI4,C_SLOT_0_AXIS_TDATA_WIDTH=AUTO,C_SLOT_0_AXIS_TID_WIDTH=AUTO,C_SLOT_0_\
|
||||
AXIS_TUSER_WIDTH=AUTO,C_SLOT_0_AXIS_TDEST_WIDTH=AUTO,C_SLOT_1_AXI_ARUSER_WIDTH=1,C_SLOT_1_AXI_RUSER_WIDTH=1,C_SLOT_1_AXI_AWUSER_WIDTH=1,C_SLOT_1_AXI_WUSER_WIDTH=1,C_SLOT_1_AXI_BUSER_WIDTH=1,C_SLOT_1_AXI_ID_WIDTH=AUTO,C_SLOT_1_AXI_DATA_WIDTH=AUTO,C_SLOT_1_AXI_ADDR_WIDTH=AUTO,C_SLOT_1_AXI_PROTOCOL=AXI4,C_SLOT_1_AXIS_TDATA_WIDTH=AUTO,C_SLOT_1_AXIS_TID_WIDTH=AUTO,C_SLOT_1_AXIS_TUSER_WIDTH=AUTO,C_SLOT_1_AXIS_TDEST_WIDTH=AUTO,C_SLOT_0_INTF_TYPE=xilinx.com_interface_axis_rtl_1.0,C_SLOT_1_INTF_TYPE=xili\
|
||||
nx.com_interface_axis_rtl_1.0,C_SLOT_2_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_3_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_4_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_5_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_6_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_7_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_8_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_9_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_10_INTF_TYPE=xilinx.com_interfa\
|
||||
ce_aximm_rtl_1.0,C_SLOT_11_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_12_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_13_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_14_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_15_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_MON_TYPE=INTERFACE,C_SLOT_2_AXI_ARUSER_WIDTH=1,C_SLOT_2_AXI_RUSER_WIDTH=1,C_SLOT_2_AXI_AWUSER_WIDTH=1,C_SLOT_2_AXI_WUSER_WIDTH=1,C_SLOT_2_AXI_BUSER_WIDTH=1,C_SLOT_2_AXI_ID_WIDTH=AUTO,C_SLOT_2_AXI_DATA_WIDTH\
|
||||
=AUTO,C_SLOT_2_AXI_ADDR_WIDTH=AUTO,C_SLOT_2_AXI_PROTOCOL=AXI4,C_SLOT_2_AXIS_TDATA_WIDTH=AUTO,C_SLOT_2_AXIS_TID_WIDTH=AUTO,C_SLOT_2_AXIS_TUSER_WIDTH=AUTO,C_SLOT_2_AXIS_TDEST_WIDTH=AUTO,C_SLOT_3_AXI_ARUSER_WIDTH=1,C_SLOT_3_AXI_RUSER_WIDTH=1,C_SLOT_3_AXI_AWUSER_WIDTH=1,C_SLOT_3_AXI_WUSER_WIDTH=1,C_SLOT_3_AXI_BUSER_WIDTH=1,C_SLOT_3_AXI_ID_WIDTH=AUTO,C_SLOT_3_AXI_DATA_WIDTH=AUTO,C_SLOT_3_AXI_ADDR_WIDTH=AUTO,C_SLOT_3_AXI_PROTOCOL=AXI4,C_SLOT_3_AXIS_TDATA_WIDTH=AUTO,C_SLOT_3_AXIS_TID_WIDTH=AUTO,C_SLOT_\
|
||||
3_AXIS_TUSER_WIDTH=AUTO,C_SLOT_3_AXIS_TDEST_WIDTH=AUTO,C_SLOT_4_AXI_ARUSER_WIDTH=1,C_SLOT_4_AXI_RUSER_WIDTH=1,C_SLOT_4_AXI_AWUSER_WIDTH=1,C_SLOT_4_AXI_WUSER_WIDTH=1,C_SLOT_4_AXI_BUSER_WIDTH=1,C_SLOT_4_AXI_ID_WIDTH=AUTO,C_SLOT_4_AXI_DATA_WIDTH=AUTO,C_SLOT_4_AXI_ADDR_WIDTH=AUTO,C_SLOT_4_AXI_PROTOCOL=AXI4,C_SLOT_4_AXIS_TDATA_WIDTH=AUTO,C_SLOT_4_AXIS_TID_WIDTH=AUTO,C_SLOT_4_AXIS_TUSER_WIDTH=AUTO,C_SLOT_4_AXIS_TDEST_WIDTH=AUTO,C_SLOT_5_AXI_ARUSER_WIDTH=1,C_SLOT_5_AXI_RUSER_WIDTH=1,C_SLOT_5_AXI_AWUSER\
|
||||
_WIDTH=1,C_SLOT_5_AXI_WUSER_WIDTH=1,C_SLOT_5_AXI_BUSER_WIDTH=1,C_SLOT_5_AXI_ID_WIDTH=AUTO,C_SLOT_5_AXI_DATA_WIDTH=AUTO,C_SLOT_5_AXI_ADDR_WIDTH=AUTO,C_SLOT_5_AXI_PROTOCOL=AXI4,C_SLOT_5_AXIS_TDATA_WIDTH=AUTO,C_SLOT_5_AXIS_TID_WIDTH=AUTO,C_SLOT_5_AXIS_TUSER_WIDTH=AUTO,C_SLOT_5_AXIS_TDEST_WIDTH=AUTO,C_SLOT_6_AXI_ARUSER_WIDTH=1,C_SLOT_6_AXI_RUSER_WIDTH=1,C_SLOT_6_AXI_AWUSER_WIDTH=1,C_SLOT_6_AXI_WUSER_WIDTH=1,C_SLOT_6_AXI_BUSER_WIDTH=1,C_SLOT_6_AXI_ID_WIDTH=AUTO,C_SLOT_6_AXI_DATA_WIDTH=AUTO,C_SLOT_6_A\
|
||||
XI_ADDR_WIDTH=AUTO,C_SLOT_6_AXI_PROTOCOL=AXI4,C_SLOT_6_AXIS_TDATA_WIDTH=AUTO,C_SLOT_6_AXIS_TID_WIDTH=AUTO,C_SLOT_6_AXIS_TUSER_WIDTH=AUTO,C_SLOT_6_AXIS_TDEST_WIDTH=AUTO,C_SLOT_7_AXI_ARUSER_WIDTH=1,C_SLOT_7_AXI_RUSER_WIDTH=1,C_SLOT_7_AXI_AWUSER_WIDTH=1,C_SLOT_7_AXI_WUSER_WIDTH=1,C_SLOT_7_AXI_BUSER_WIDTH=1,C_SLOT_7_AXI_ID_WIDTH=AUTO,C_SLOT_7_AXI_DATA_WIDTH=AUTO,C_SLOT_7_AXI_ADDR_WIDTH=AUTO,C_SLOT_7_AXI_PROTOCOL=AXI4,C_SLOT_7_AXIS_TDATA_WIDTH=AUTO,C_SLOT_7_AXIS_TID_WIDTH=AUTO,C_SLOT_7_AXIS_TUSER_WID\
|
||||
TH=AUTO,C_SLOT_7_AXIS_TDEST_WIDTH=AUTO,C_SLOT_8_AXI_ARUSER_WIDTH=1,C_SLOT_8_AXI_RUSER_WIDTH=1,C_SLOT_8_AXI_AWUSER_WIDTH=1,C_SLOT_8_AXI_WUSER_WIDTH=1,C_SLOT_8_AXI_BUSER_WIDTH=1,C_SLOT_8_AXI_ID_WIDTH=AUTO,C_SLOT_8_AXI_DATA_WIDTH=AUTO,C_SLOT_8_AXI_ADDR_WIDTH=AUTO,C_SLOT_8_AXI_PROTOCOL=AXI4,C_SLOT_8_AXIS_TDATA_WIDTH=AUTO,C_SLOT_8_AXIS_TID_WIDTH=AUTO,C_SLOT_8_AXIS_TUSER_WIDTH=AUTO,C_SLOT_8_AXIS_TDEST_WIDTH=AUTO,C_SLOT_9_AXI_ARUSER_WIDTH=1,C_SLOT_9_AXI_RUSER_WIDTH=1,C_SLOT_9_AXI_AWUSER_WIDTH=1,C_SLOT_\
|
||||
9_AXI_WUSER_WIDTH=1,C_SLOT_9_AXI_BUSER_WIDTH=1,C_SLOT_9_AXI_ID_WIDTH=AUTO,C_SLOT_9_AXI_DATA_WIDTH=AUTO,C_SLOT_9_AXI_ADDR_WIDTH=AUTO,C_SLOT_9_AXI_PROTOCOL=AXI4,C_SLOT_9_AXIS_TDATA_WIDTH=AUTO,C_SLOT_9_AXIS_TID_WIDTH=AUTO,C_SLOT_9_AXIS_TUSER_WIDTH=AUTO,C_SLOT_9_AXIS_TDEST_WIDTH=AUTO,C_SLOT_10_AXI_ARUSER_WIDTH=1,C_SLOT_10_AXI_RUSER_WIDTH=1,C_SLOT_10_AXI_AWUSER_WIDTH=1,C_SLOT_10_AXI_WUSER_WIDTH=1,C_SLOT_10_AXI_BUSER_WIDTH=1,C_SLOT_10_AXI_ID_WIDTH=AUTO,C_SLOT_10_AXI_DATA_WIDTH=AUTO,C_SLOT_10_AXI_ADDR_\
|
||||
WIDTH=AUTO,C_SLOT_10_AXI_PROTOCOL=AXI4,C_SLOT_10_AXIS_TDATA_WIDTH=AUTO,C_SLOT_10_AXIS_TID_WIDTH=AUTO,C_SLOT_10_AXIS_TUSER_WIDTH=AUTO,C_SLOT_10_AXIS_TDEST_WIDTH=AUTO,C_SLOT_11_AXI_ARUSER_WIDTH=1,C_SLOT_11_AXI_RUSER_WIDTH=1,C_SLOT_11_AXI_AWUSER_WIDTH=1,C_SLOT_11_AXI_WUSER_WIDTH=1,C_SLOT_11_AXI_BUSER_WIDTH=1,C_SLOT_11_AXI_ID_WIDTH=AUTO,C_SLOT_11_AXI_DATA_WIDTH=AUTO,C_SLOT_11_AXI_ADDR_WIDTH=AUTO,C_SLOT_11_AXI_PROTOCOL=AXI4,C_SLOT_11_AXIS_TDATA_WIDTH=AUTO,C_SLOT_11_AXIS_TID_WIDTH=AUTO,C_SLOT_11_AXIS_\
|
||||
TUSER_WIDTH=AUTO,C_SLOT_11_AXIS_TDEST_WIDTH=AUTO,C_SLOT_12_AXI_ARUSER_WIDTH=1,C_SLOT_12_AXI_RUSER_WIDTH=1,C_SLOT_12_AXI_AWUSER_WIDTH=1,C_SLOT_12_AXI_WUSER_WIDTH=1,C_SLOT_12_AXI_BUSER_WIDTH=1,C_SLOT_12_AXI_ID_WIDTH=AUTO,C_SLOT_12_AXI_DATA_WIDTH=AUTO,C_SLOT_12_AXI_ADDR_WIDTH=AUTO,C_SLOT_12_AXI_PROTOCOL=AXI4,C_SLOT_12_AXIS_TDATA_WIDTH=AUTO,C_SLOT_12_AXIS_TID_WIDTH=AUTO,C_SLOT_12_AXIS_TUSER_WIDTH=AUTO,C_SLOT_12_AXIS_TDEST_WIDTH=AUTO,C_SLOT_13_AXI_ARUSER_WIDTH=1,C_SLOT_13_AXI_RUSER_WIDTH=1,C_SLOT_13_\
|
||||
AXI_AWUSER_WIDTH=1,C_SLOT_13_AXI_WUSER_WIDTH=1,C_SLOT_13_AXI_BUSER_WIDTH=1,C_SLOT_13_AXI_ID_WIDTH=AUTO,C_SLOT_13_AXI_DATA_WIDTH=AUTO,C_SLOT_13_AXI_ADDR_WIDTH=AUTO,C_SLOT_13_AXI_PROTOCOL=AXI4,C_SLOT_13_AXIS_TDATA_WIDTH=AUTO,C_SLOT_13_AXIS_TID_WIDTH=AUTO,C_SLOT_13_AXIS_TUSER_WIDTH=AUTO,C_SLOT_13_AXIS_TDEST_WIDTH=AUTO,C_SLOT_14_AXI_ARUSER_WIDTH=1,C_SLOT_14_AXI_RUSER_WIDTH=1,C_SLOT_14_AXI_AWUSER_WIDTH=1,C_SLOT_14_AXI_WUSER_WIDTH=1,C_SLOT_14_AXI_BUSER_WIDTH=1,C_SLOT_14_AXI_ID_WIDTH=AUTO,C_SLOT_14_AXI\
|
||||
_DATA_WIDTH=AUTO,C_SLOT_14_AXI_ADDR_WIDTH=AUTO,C_SLOT_14_AXI_PROTOCOL=AXI4,C_SLOT_14_AXIS_TDATA_WIDTH=AUTO,C_SLOT_14_AXIS_TID_WIDTH=AUTO,C_SLOT_14_AXIS_TUSER_WIDTH=AUTO,C_SLOT_14_AXIS_TDEST_WIDTH=AUTO,C_SLOT_15_AXI_ARUSER_WIDTH=1,C_SLOT_15_AXI_RUSER_WIDTH=1,C_SLOT_15_AXI_AWUSER_WIDTH=1,C_SLOT_15_AXI_WUSER_WIDTH=1,C_SLOT_15_AXI_BUSER_WIDTH=1,C_SLOT_15_AXI_ID_WIDTH=AUTO,C_SLOT_15_AXI_DATA_WIDTH=AUTO,C_SLOT_15_AXI_ADDR_WIDTH=AUTO,C_SLOT_15_AXI_PROTOCOL=AXI4,C_SLOT_15_AXIS_TDATA_WIDTH=AUTO,C_SLOT_15\
|
||||
_AXIS_TID_WIDTH=AUTO,C_SLOT_15_AXIS_TUSER_WIDTH=AUTO,C_SLOT_15_AXIS_TDEST_WIDTH=AUTO,C_PROBE_WIDTH_PROPAGATION=AUTO}" *)
|
||||
(* X_CORE_INFO = "bd_3e86_0,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "design_1_syn_system_ila_0_2,bd_3e86_0,{}" *)
|
||||
(* CORE_GENERATION_INFO = "design_1_syn_system_ila_0_2,bd_3e86_0,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=system_ila,x_ipVersion=1.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_SLOT=0,C_SLOT_15_TYPE=0,C_SLOT_14_TYPE=0,C_SLOT_13_TYPE=0,C_SLOT_12_TYPE=0,C_SLOT_11_TYPE=0,C_SLOT_10_TYPE=0,C_SLOT_9_TYPE=0,C_SLOT_8_TYPE=0,C_SLOT_7_TYPE=0,C_SLOT_6_TYPE=0,C_SLOT_5_TYPE=0,C_SLOT_4_TYPE=0,C_SLOT_3_TYPE=0,C_SLOT_2_TYPE=0,C_SLOT_1_TYPE=0,C_SLOT_0\
|
||||
_TYPE=0,C_SLOT_0_MAX_RD_BURSTS=2,C_SLOT_0_MAX_WR_BURSTS=2,C_SLOT_1_MAX_RD_BURSTS=2,C_SLOT_1_MAX_WR_BURSTS=2,C_SLOT_2_MAX_RD_BURSTS=2,C_SLOT_2_MAX_WR_BURSTS=2,C_SLOT_3_MAX_RD_BURSTS=2,C_SLOT_3_MAX_WR_BURSTS=2,C_SLOT_4_MAX_RD_BURSTS=2,C_SLOT_4_MAX_WR_BURSTS=2,C_SLOT_5_MAX_RD_BURSTS=2,C_SLOT_5_MAX_WR_BURSTS=2,C_SLOT_6_MAX_RD_BURSTS=2,C_SLOT_6_MAX_WR_BURSTS=2,C_SLOT_7_MAX_RD_BURSTS=2,C_SLOT_7_MAX_WR_BURSTS=2,C_SLOT_8_MAX_RD_BURSTS=2,C_SLOT_8_MAX_WR_BURSTS=2,C_SLOT_9_MAX_RD_BURSTS=2,C_SLOT_9_MAX_WR_B\
|
||||
URSTS=2,C_SLOT_10_MAX_RD_BURSTS=2,C_SLOT_10_MAX_WR_BURSTS=2,C_SLOT_11_MAX_RD_BURSTS=2,C_SLOT_11_MAX_WR_BURSTS=2,C_SLOT_12_MAX_RD_BURSTS=2,C_SLOT_12_MAX_WR_BURSTS=2,C_SLOT_13_MAX_RD_BURSTS=2,C_SLOT_13_MAX_WR_BURSTS=2,C_SLOT_14_MAX_RD_BURSTS=2,C_SLOT_14_MAX_WR_BURSTS=2,C_SLOT_15_MAX_RD_BURSTS=2,C_SLOT_15_MAX_WR_BURSTS=2,C_SLOT_0_TXN_CNTR_EN=1,C_SLOT_1_TXN_CNTR_EN=1,C_SLOT_2_TXN_CNTR_EN=1,C_SLOT_3_TXN_CNTR_EN=1,C_SLOT_4_TXN_CNTR_EN=1,C_SLOT_5_TXN_CNTR_EN=1,C_SLOT_6_TXN_CNTR_EN=1,C_SLOT_7_TXN_CNTR_E\
|
||||
N=1,C_SLOT_8_TXN_CNTR_EN=1,C_SLOT_9_TXN_CNTR_EN=1,C_SLOT_10_TXN_CNTR_EN=1,C_SLOT_11_TXN_CNTR_EN=1,C_SLOT_12_TXN_CNTR_EN=1,C_SLOT_13_TXN_CNTR_EN=1,C_SLOT_14_TXN_CNTR_EN=1,C_SLOT_15_TXN_CNTR_EN=1,C_SLOT_0_APC_STS_EN=0,C_SLOT_1_APC_STS_EN=0,C_SLOT_2_APC_STS_EN=0,C_SLOT_3_APC_STS_EN=0,C_SLOT_4_APC_STS_EN=0,C_SLOT_5_APC_STS_EN=0,C_SLOT_6_APC_STS_EN=0,C_SLOT_7_APC_STS_EN=0,C_SLOT_8_APC_STS_EN=0,C_SLOT_9_APC_STS_EN=0,C_SLOT_10_APC_STS_EN=0,C_SLOT_11_APC_STS_EN=0,C_SLOT_12_APC_STS_EN=0,C_SLOT_13_APC_STS\
|
||||
_EN=0,C_SLOT_14_APC_STS_EN=0,C_SLOT_15_APC_STS_EN=0,C_SLOT_0_APC_EN=0,C_SLOT_1_APC_EN=0,C_SLOT_2_APC_EN=0,C_SLOT_3_APC_EN=0,C_SLOT_4_APC_EN=0,C_SLOT_5_APC_EN=0,C_SLOT_6_APC_EN=0,C_SLOT_7_APC_EN=0,C_SLOT_8_APC_EN=0,C_SLOT_9_APC_EN=0,C_SLOT_10_APC_EN=0,C_SLOT_11_APC_EN=0,C_SLOT_12_APC_EN=0,C_SLOT_13_APC_EN=0,C_SLOT_14_APC_EN=0,C_SLOT_15_APC_EN=0,C_SLOT_0_APC_MAX_AW_WAITS=0,C_SLOT_0_APC_MAX_AR_WAITS=0,C_SLOT_0_APC_MAX_W_WAITS=0,C_SLOT_0_APC_MAX_B_WAITS=0,C_SLOT_0_APC_MAX_R_WAITS=0,C_SLOT_0_APC_MAX_\
|
||||
CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_0_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_0_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_0_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_AW_WAITS=0,C_SLOT_1_APC_MAX_AR_WAITS=0,C_SLOT_1_APC_MAX_W_WAITS=0,C_SLOT_1_APC_MAX_B_WAITS=0,C_SLOT_1_APC_MAX_R_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_1_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_AW_WAITS=\
|
||||
0,C_SLOT_2_APC_MAX_AR_WAITS=0,C_SLOT_2_APC_MAX_W_WAITS=0,C_SLOT_2_APC_MAX_B_WAITS=0,C_SLOT_2_APC_MAX_R_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_2_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_AW_WAITS=0,C_SLOT_3_APC_MAX_AR_WAITS=0,C_SLOT_3_APC_MAX_W_WAITS=0,C_SLOT_3_APC_MAX_B_WAITS=0,C_SLOT_3_APC_MAX_R_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_WLAST_TO_AW\
|
||||
VALID_WAITS=0,C_SLOT_3_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_AW_WAITS=0,C_SLOT_4_APC_MAX_AR_WAITS=0,C_SLOT_4_APC_MAX_W_WAITS=0,C_SLOT_4_APC_MAX_B_WAITS=0,C_SLOT_4_APC_MAX_R_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_4_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_5_APC_MAX_AW_WAITS=0,C_SLOT_5_APC_MAX_AR_WAITS=0,C_SLOT_5_APC_MAX_W_WAITS=0,C\
|
||||
_SLOT_5_APC_MAX_B_WAITS=0,C_SLOT_5_APC_MAX_R_WAITS=0,C_SLOT_5_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_5_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_5_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_5_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_6_APC_MAX_AW_WAITS=0,C_SLOT_6_APC_MAX_AR_WAITS=0,C_SLOT_6_APC_MAX_W_WAITS=0,C_SLOT_6_APC_MAX_B_WAITS=0,C_SLOT_6_APC_MAX_R_WAITS=0,C_SLOT_6_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_6_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_6_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_S\
|
||||
LOT_6_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_7_APC_MAX_AW_WAITS=0,C_SLOT_7_APC_MAX_AR_WAITS=0,C_SLOT_7_APC_MAX_W_WAITS=0,C_SLOT_7_APC_MAX_B_WAITS=0,C_SLOT_7_APC_MAX_R_WAITS=0,C_SLOT_7_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_7_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_7_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_7_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_8_APC_MAX_AW_WAITS=0,C_SLOT_8_APC_MAX_AR_WAITS=0,C_SLOT_8_APC_MAX_W_WAITS=0,C_SLOT_8_APC_MAX_B_WAITS=0,C_SLOT_8_APC_MAX_R_WAITS=0,C_SLO\
|
||||
T_8_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_8_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_8_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_8_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_9_APC_MAX_AW_WAITS=0,C_SLOT_9_APC_MAX_AR_WAITS=0,C_SLOT_9_APC_MAX_W_WAITS=0,C_SLOT_9_APC_MAX_B_WAITS=0,C_SLOT_9_APC_MAX_R_WAITS=0,C_SLOT_9_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_9_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_9_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_9_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_10_APC_\
|
||||
MAX_AW_WAITS=0,C_SLOT_10_APC_MAX_AR_WAITS=0,C_SLOT_10_APC_MAX_W_WAITS=0,C_SLOT_10_APC_MAX_B_WAITS=0,C_SLOT_10_APC_MAX_R_WAITS=0,C_SLOT_10_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_10_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_10_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_10_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_11_APC_MAX_AW_WAITS=0,C_SLOT_11_APC_MAX_AR_WAITS=0,C_SLOT_11_APC_MAX_W_WAITS=0,C_SLOT_11_APC_MAX_B_WAITS=0,C_SLOT_11_APC_MAX_R_WAITS=0,C_SLOT_11_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C\
|
||||
_SLOT_11_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_11_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_11_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_12_APC_MAX_AW_WAITS=0,C_SLOT_12_APC_MAX_AR_WAITS=0,C_SLOT_12_APC_MAX_W_WAITS=0,C_SLOT_12_APC_MAX_B_WAITS=0,C_SLOT_12_APC_MAX_R_WAITS=0,C_SLOT_12_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_12_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_12_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_12_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_13_APC_MAX_AW_WAITS=0,C_SLOT_13_APC_MA\
|
||||
X_AR_WAITS=0,C_SLOT_13_APC_MAX_W_WAITS=0,C_SLOT_13_APC_MAX_B_WAITS=0,C_SLOT_13_APC_MAX_R_WAITS=0,C_SLOT_13_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_13_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_13_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_13_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_14_APC_MAX_AW_WAITS=0,C_SLOT_14_APC_MAX_AR_WAITS=0,C_SLOT_14_APC_MAX_W_WAITS=0,C_SLOT_14_APC_MAX_B_WAITS=0,C_SLOT_14_APC_MAX_R_WAITS=0,C_SLOT_14_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_14_APC_MAX_WLAST_TO_AWVAL\
|
||||
ID_WAITS=0,C_SLOT_14_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_14_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_15_APC_MAX_AW_WAITS=0,C_SLOT_15_APC_MAX_AR_WAITS=0,C_SLOT_15_APC_MAX_W_WAITS=0,C_SLOT_15_APC_MAX_B_WAITS=0,C_SLOT_15_APC_MAX_R_WAITS=0,C_SLOT_15_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_15_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_15_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_15_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_BRAM_CNT=0.0,C_SLOT_0_AXI_AW_SEL_DATA=1,C_SLOT_0_AXI_W_SEL_DATA=1,C_SLOT_0\
|
||||
_AXI_B_SEL_DATA=1,C_SLOT_0_AXI_AR_SEL_DATA=1,C_SLOT_0_AXI_R_SEL_DATA=1,C_SLOT_1_AXI_AW_SEL_DATA=1,C_SLOT_1_AXI_W_SEL_DATA=1,C_SLOT_1_AXI_B_SEL_DATA=1,C_SLOT_1_AXI_AR_SEL_DATA=1,C_SLOT_1_AXI_R_SEL_DATA=1,C_SLOT_2_AXI_AW_SEL_DATA=1,C_SLOT_2_AXI_W_SEL_DATA=1,C_SLOT_2_AXI_B_SEL_DATA=1,C_SLOT_2_AXI_AR_SEL_DATA=1,C_SLOT_2_AXI_R_SEL_DATA=1,C_SLOT_3_AXI_AW_SEL_DATA=1,C_SLOT_3_AXI_W_SEL_DATA=1,C_SLOT_3_AXI_B_SEL_DATA=1,C_SLOT_3_AXI_AR_SEL_DATA=1,C_SLOT_3_AXI_R_SEL_DATA=1,C_SLOT_4_AXI_AW_SEL_DATA=1,C_SLOT\
|
||||
_4_AXI_W_SEL_DATA=1,C_SLOT_4_AXI_B_SEL_DATA=1,C_SLOT_4_AXI_AR_SEL_DATA=1,C_SLOT_4_AXI_R_SEL_DATA=1,C_SLOT_5_AXI_AW_SEL_DATA=1,C_SLOT_5_AXI_W_SEL_DATA=1,C_SLOT_5_AXI_B_SEL_DATA=1,C_SLOT_5_AXI_AR_SEL_DATA=1,C_SLOT_5_AXI_R_SEL_DATA=1,C_SLOT_6_AXI_AW_SEL_DATA=1,C_SLOT_6_AXI_W_SEL_DATA=1,C_SLOT_6_AXI_B_SEL_DATA=1,C_SLOT_6_AXI_AR_SEL_DATA=1,C_SLOT_6_AXI_R_SEL_DATA=1,C_SLOT_7_AXI_AW_SEL_DATA=1,C_SLOT_7_AXI_W_SEL_DATA=1,C_SLOT_7_AXI_B_SEL_DATA=1,C_SLOT_7_AXI_AR_SEL_DATA=1,C_SLOT_7_AXI_R_SEL_DATA=1,C_SLO\
|
||||
T_8_AXI_AW_SEL_DATA=1,C_SLOT_8_AXI_W_SEL_DATA=1,C_SLOT_8_AXI_B_SEL_DATA=1,C_SLOT_8_AXI_AR_SEL_DATA=1,C_SLOT_8_AXI_R_SEL_DATA=1,C_SLOT_9_AXI_AW_SEL_DATA=1,C_SLOT_9_AXI_W_SEL_DATA=1,C_SLOT_9_AXI_B_SEL_DATA=1,C_SLOT_9_AXI_AR_SEL_DATA=1,C_SLOT_9_AXI_R_SEL_DATA=1,C_SLOT_10_AXI_AW_SEL_DATA=1,C_SLOT_10_AXI_W_SEL_DATA=1,C_SLOT_10_AXI_B_SEL_DATA=1,C_SLOT_10_AXI_AR_SEL_DATA=1,C_SLOT_10_AXI_R_SEL_DATA=1,C_SLOT_11_AXI_AW_SEL_DATA=1,C_SLOT_11_AXI_W_SEL_DATA=1,C_SLOT_11_AXI_B_SEL_DATA=1,C_SLOT_11_AXI_AR_SEL_D\
|
||||
ATA=1,C_SLOT_11_AXI_R_SEL_DATA=1,C_SLOT_12_AXI_AW_SEL_DATA=1,C_SLOT_12_AXI_W_SEL_DATA=1,C_SLOT_12_AXI_B_SEL_DATA=1,C_SLOT_12_AXI_AR_SEL_DATA=1,C_SLOT_12_AXI_R_SEL_DATA=1,C_SLOT_13_AXI_AW_SEL_DATA=1,C_SLOT_13_AXI_W_SEL_DATA=1,C_SLOT_13_AXI_B_SEL_DATA=1,C_SLOT_13_AXI_AR_SEL_DATA=1,C_SLOT_13_AXI_R_SEL_DATA=1,C_SLOT_14_AXI_AW_SEL_DATA=1,C_SLOT_14_AXI_W_SEL_DATA=1,C_SLOT_14_AXI_B_SEL_DATA=1,C_SLOT_14_AXI_AR_SEL_DATA=1,C_SLOT_14_AXI_R_SEL_DATA=1,C_SLOT_15_AXI_AW_SEL_DATA=1,C_SLOT_15_AXI_W_SEL_DATA=1,C\
|
||||
_SLOT_15_AXI_B_SEL_DATA=1,C_SLOT_15_AXI_AR_SEL_DATA=1,C_SLOT_15_AXI_R_SEL_DATA=1,C_SLOT_0_AXI_AW_SEL_TRIG=1,C_SLOT_0_AXI_W_SEL_TRIG=1,C_SLOT_0_AXI_B_SEL_TRIG=1,C_SLOT_0_AXI_AR_SEL_TRIG=1,C_SLOT_0_AXI_R_SEL_TRIG=1,C_SLOT_1_AXI_AW_SEL_TRIG=1,C_SLOT_1_AXI_W_SEL_TRIG=1,C_SLOT_1_AXI_B_SEL_TRIG=1,C_SLOT_1_AXI_AR_SEL_TRIG=1,C_SLOT_1_AXI_R_SEL_TRIG=1,C_SLOT_2_AXI_AW_SEL_TRIG=1,C_SLOT_2_AXI_W_SEL_TRIG=1,C_SLOT_2_AXI_B_SEL_TRIG=1,C_SLOT_2_AXI_AR_SEL_TRIG=1,C_SLOT_2_AXI_R_SEL_TRIG=1,C_SLOT_3_AXI_AW_SEL_TRI\
|
||||
G=1,C_SLOT_3_AXI_W_SEL_TRIG=1,C_SLOT_3_AXI_B_SEL_TRIG=1,C_SLOT_3_AXI_AR_SEL_TRIG=1,C_SLOT_3_AXI_R_SEL_TRIG=1,C_SLOT_4_AXI_AW_SEL_TRIG=1,C_SLOT_4_AXI_W_SEL_TRIG=1,C_SLOT_4_AXI_B_SEL_TRIG=1,C_SLOT_4_AXI_AR_SEL_TRIG=1,C_SLOT_4_AXI_R_SEL_TRIG=1,C_SLOT_5_AXI_AW_SEL_TRIG=1,C_SLOT_5_AXI_W_SEL_TRIG=1,C_SLOT_5_AXI_B_SEL_TRIG=1,C_SLOT_5_AXI_AR_SEL_TRIG=1,C_SLOT_5_AXI_R_SEL_TRIG=1,C_SLOT_6_AXI_AW_SEL_TRIG=1,C_SLOT_6_AXI_W_SEL_TRIG=1,C_SLOT_6_AXI_B_SEL_TRIG=1,C_SLOT_6_AXI_AR_SEL_TRIG=1,C_SLOT_6_AXI_R_SEL_TR\
|
||||
IG=1,C_SLOT_7_AXI_AW_SEL_TRIG=1,C_SLOT_7_AXI_W_SEL_TRIG=1,C_SLOT_7_AXI_B_SEL_TRIG=1,C_SLOT_7_AXI_AR_SEL_TRIG=1,C_SLOT_7_AXI_R_SEL_TRIG=1,C_SLOT_8_AXI_AW_SEL_TRIG=1,C_SLOT_8_AXI_W_SEL_TRIG=1,C_SLOT_8_AXI_B_SEL_TRIG=1,C_SLOT_8_AXI_AR_SEL_TRIG=1,C_SLOT_8_AXI_R_SEL_TRIG=1,C_SLOT_9_AXI_AW_SEL_TRIG=1,C_SLOT_9_AXI_W_SEL_TRIG=1,C_SLOT_9_AXI_B_SEL_TRIG=1,C_SLOT_9_AXI_AR_SEL_TRIG=1,C_SLOT_9_AXI_R_SEL_TRIG=1,C_SLOT_10_AXI_AW_SEL_TRIG=1,C_SLOT_10_AXI_W_SEL_TRIG=1,C_SLOT_10_AXI_B_SEL_TRIG=1,C_SLOT_10_AXI_AR_\
|
||||
SEL_TRIG=1,C_SLOT_10_AXI_R_SEL_TRIG=1,C_SLOT_11_AXI_AW_SEL_TRIG=1,C_SLOT_11_AXI_W_SEL_TRIG=1,C_SLOT_11_AXI_B_SEL_TRIG=1,C_SLOT_11_AXI_AR_SEL_TRIG=1,C_SLOT_11_AXI_R_SEL_TRIG=1,C_SLOT_12_AXI_AW_SEL_TRIG=1,C_SLOT_12_AXI_W_SEL_TRIG=1,C_SLOT_12_AXI_B_SEL_TRIG=1,C_SLOT_12_AXI_AR_SEL_TRIG=1,C_SLOT_12_AXI_R_SEL_TRIG=1,C_SLOT_13_AXI_AW_SEL_TRIG=1,C_SLOT_13_AXI_W_SEL_TRIG=1,C_SLOT_13_AXI_B_SEL_TRIG=1,C_SLOT_13_AXI_AR_SEL_TRIG=1,C_SLOT_13_AXI_R_SEL_TRIG=1,C_SLOT_14_AXI_AW_SEL_TRIG=1,C_SLOT_14_AXI_W_SEL_TRI\
|
||||
G=1,C_SLOT_14_AXI_B_SEL_TRIG=1,C_SLOT_14_AXI_AR_SEL_TRIG=1,C_SLOT_14_AXI_R_SEL_TRIG=1,C_SLOT_15_AXI_AW_SEL_TRIG=1,C_SLOT_15_AXI_W_SEL_TRIG=1,C_SLOT_15_AXI_B_SEL_TRIG=1,C_SLOT_15_AXI_AR_SEL_TRIG=1,C_SLOT_15_AXI_R_SEL_TRIG=1,C_SLOT_0_AXI_AW_SEL=1,C_SLOT_0_AXI_W_SEL=1,C_SLOT_0_AXI_B_SEL=1,C_SLOT_0_AXI_AR_SEL=1,C_SLOT_0_AXI_R_SEL=1,C_SLOT_1_AXI_AW_SEL=1,C_SLOT_1_AXI_W_SEL=1,C_SLOT_1_AXI_B_SEL=1,C_SLOT_1_AXI_AR_SEL=1,C_SLOT_1_AXI_R_SEL=1,C_SLOT_2_AXI_AW_SEL=1,C_SLOT_2_AXI_W_SEL=1,C_SLOT_2_AXI_B_SEL=1\
|
||||
,C_SLOT_2_AXI_AR_SEL=1,C_SLOT_2_AXI_R_SEL=1,C_SLOT_3_AXI_AW_SEL=1,C_SLOT_3_AXI_W_SEL=1,C_SLOT_3_AXI_B_SEL=1,C_SLOT_3_AXI_AR_SEL=1,C_SLOT_3_AXI_R_SEL=1,C_SLOT_4_AXI_AW_SEL=1,C_SLOT_4_AXI_W_SEL=1,C_SLOT_4_AXI_B_SEL=1,C_SLOT_4_AXI_AR_SEL=1,C_SLOT_4_AXI_R_SEL=1,C_SLOT_5_AXI_AW_SEL=1,C_SLOT_5_AXI_W_SEL=1,C_SLOT_5_AXI_B_SEL=1,C_SLOT_5_AXI_AR_SEL=1,C_SLOT_5_AXI_R_SEL=1,C_SLOT_6_AXI_AW_SEL=1,C_SLOT_6_AXI_W_SEL=1,C_SLOT_6_AXI_B_SEL=1,C_SLOT_6_AXI_AR_SEL=1,C_SLOT_6_AXI_R_SEL=1,C_SLOT_7_AXI_AW_SEL=1,C_SLOT\
|
||||
_7_AXI_W_SEL=1,C_SLOT_7_AXI_B_SEL=1,C_SLOT_7_AXI_AR_SEL=1,C_SLOT_7_AXI_R_SEL=1,C_SLOT_8_AXI_AW_SEL=1,C_SLOT_8_AXI_W_SEL=1,C_SLOT_8_AXI_B_SEL=1,C_SLOT_8_AXI_AR_SEL=1,C_SLOT_8_AXI_R_SEL=1,C_SLOT_9_AXI_AW_SEL=1,C_SLOT_9_AXI_W_SEL=1,C_SLOT_9_AXI_B_SEL=1,C_SLOT_9_AXI_AR_SEL=1,C_SLOT_9_AXI_R_SEL=1,C_SLOT_10_AXI_AW_SEL=1,C_SLOT_10_AXI_W_SEL=1,C_SLOT_10_AXI_B_SEL=1,C_SLOT_10_AXI_AR_SEL=1,C_SLOT_10_AXI_R_SEL=1,C_SLOT_11_AXI_AW_SEL=1,C_SLOT_11_AXI_W_SEL=1,C_SLOT_11_AXI_B_SEL=1,C_SLOT_11_AXI_AR_SEL=1,C_SLO\
|
||||
T_11_AXI_R_SEL=1,C_SLOT_12_AXI_AW_SEL=1,C_SLOT_12_AXI_W_SEL=1,C_SLOT_12_AXI_B_SEL=1,C_SLOT_12_AXI_AR_SEL=1,C_SLOT_12_AXI_R_SEL=1,C_SLOT_13_AXI_AW_SEL=1,C_SLOT_13_AXI_W_SEL=1,C_SLOT_13_AXI_B_SEL=1,C_SLOT_13_AXI_AR_SEL=1,C_SLOT_13_AXI_R_SEL=1,C_SLOT_14_AXI_AW_SEL=1,C_SLOT_14_AXI_W_SEL=1,C_SLOT_14_AXI_B_SEL=1,C_SLOT_14_AXI_AR_SEL=1,C_SLOT_14_AXI_R_SEL=1,C_SLOT_15_AXI_AW_SEL=1,C_SLOT_15_AXI_W_SEL=1,C_SLOT_15_AXI_B_SEL=1,C_SLOT_15_AXI_AR_SEL=1,C_SLOT_15_AXI_R_SEL=1,C_SLOT_0_AXI_DATA_SEL=1,C_SLOT_1_AX\
|
||||
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|
||||
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|
||||
E582_WIDTH=1,C_PROBE581_WIDTH=1,C_PROBE580_WIDTH=1,C_PROBE579_WIDTH=1,C_PROBE578_WIDTH=1,C_PROBE577_WIDTH=1,C_PROBE576_WIDTH=1,C_PROBE575_WIDTH=1,C_PROBE574_WIDTH=1,C_PROBE573_WIDTH=1,C_PROBE572_WIDTH=1,C_PROBE571_WIDTH=1,C_PROBE570_WIDTH=1,C_PROBE569_WIDTH=1,C_PROBE568_WIDTH=1,C_PROBE567_WIDTH=1,C_PROBE566_WIDTH=1,C_PROBE565_WIDTH=1,C_PROBE564_WIDTH=1,C_PROBE563_WIDTH=1,C_PROBE562_WIDTH=1,C_PROBE561_WIDTH=1,C_PROBE560_WIDTH=1,C_PROBE559_WIDTH=1,C_PROBE558_WIDTH=1,C_PROBE557_WIDTH=1,C_PROBE556_W\
|
||||
IDTH=1,C_PROBE555_WIDTH=1,C_PROBE554_WIDTH=1,C_PROBE553_WIDTH=1,C_PROBE552_WIDTH=1,C_PROBE551_WIDTH=1,C_PROBE550_WIDTH=1,C_PROBE549_WIDTH=1,C_PROBE548_WIDTH=1,C_PROBE547_WIDTH=1,C_PROBE546_WIDTH=1,C_PROBE545_WIDTH=1,C_PROBE544_WIDTH=1,C_PROBE543_WIDTH=1,C_PROBE542_WIDTH=1,C_PROBE541_WIDTH=1,C_PROBE540_WIDTH=1,C_PROBE539_WIDTH=1,C_PROBE538_WIDTH=1,C_PROBE537_WIDTH=1,C_PROBE536_WIDTH=1,C_PROBE535_WIDTH=1,C_PROBE534_WIDTH=1,C_PROBE533_WIDTH=1,C_PROBE532_WIDTH=1,C_PROBE531_WIDTH=1,C_PROBE530_WIDTH=1\
|
||||
,C_PROBE529_WIDTH=1,C_PROBE528_WIDTH=1,C_PROBE527_WIDTH=1,C_PROBE526_WIDTH=1,C_PROBE525_WIDTH=1,C_PROBE524_WIDTH=1,C_PROBE523_WIDTH=1,C_PROBE522_WIDTH=1,C_PROBE521_WIDTH=1,C_PROBE520_WIDTH=1,C_PROBE519_WIDTH=1,C_PROBE518_WIDTH=1,C_PROBE517_WIDTH=1,C_PROBE516_WIDTH=1,C_PROBE515_WIDTH=1,C_PROBE514_WIDTH=1,C_PROBE513_WIDTH=1,C_PROBE512_WIDTH=1,C_PROBE511_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE504_WIDTH=1,C_PRO\
|
||||
BE503_WIDTH=1,C_PROBE502_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE500_WIDTH=1,C_PROBE499_WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE477_\
|
||||
WIDTH=1,C_PROBE476_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE474_WIDTH=1,C_PROBE473_WIDTH=1,C_PROBE472_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE454_WIDTH=1,C_PROBE453_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE451_WIDTH=\
|
||||
1,C_PROBE450_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE447_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE425_WIDTH=1,C_PR\
|
||||
OBE424_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE398\
|
||||
_WIDTH=1,C_PROBE397_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE395_WIDTH=1,C_PROBE394_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE372_WIDTH\
|
||||
=1,C_PROBE371_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE368_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE354_WIDTH=1,C_PROBE353_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE346_WIDTH=1,C_P\
|
||||
ROBE345_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE31\
|
||||
9_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE293_WIDT\
|
||||
H=1,C_PROBE292_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE267_WIDTH=1,C_\
|
||||
PROBE266_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE254_WIDTH=1,C_PROBE253_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE2\
|
||||
40_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE214_WID\
|
||||
TH=1,C_PROBE213_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE188_WIDTH=1,C\
|
||||
_PROBE187_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE\
|
||||
161_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE154_WIDTH=1,C_PROBE153_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE135_WI\
|
||||
DTH=1,C_PROBE134_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE109_WIDTH=1,\
|
||||
C_PROBE108_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE82_WIDTH=1,C_PRO\
|
||||
BE81_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE53_WIDTH=1,C\
|
||||
_PROBE52_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE25_WIDTH\
|
||||
=1,C_PROBE24_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE0_WIDTH=1,C_DATA_DEPTH=1024,C_NUM_OF_PROBES=1,C_XLNX_HW_PROBE_INFO=\
|
||||
DEFAULT,Component_Name=design_1_syn_system_ila_0_2,C_PROBE70_WIDTH=1,C_TRIGOUT_EN=false,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,C_DDR_CLK_GEN=FALSE,C_EN_DDR_ILA=FALSE,C_ADV_TRIGGER=FALSE,C_PROBE1023_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1009_MU_CNT=1\
|
||||
,C_PROBE1008_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE984\
|
||||
_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE959\
|
||||
_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE934\
|
||||
_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE909\
|
||||
_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE884\
|
||||
_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE859\
|
||||
_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE834\
|
||||
_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE809\
|
||||
_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE784\
|
||||
_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE759\
|
||||
_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE734\
|
||||
_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE709\
|
||||
_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE684\
|
||||
_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE659\
|
||||
_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE634\
|
||||
_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE609\
|
||||
_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE584\
|
||||
_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE559\
|
||||
_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE534\
|
||||
_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE509\
|
||||
_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE484\
|
||||
_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE459\
|
||||
_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE434\
|
||||
_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE409\
|
||||
_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE384\
|
||||
_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE359\
|
||||
_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE334\
|
||||
_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE309\
|
||||
_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE284\
|
||||
_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE259\
|
||||
_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE234\
|
||||
_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE209\
|
||||
_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE184\
|
||||
_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE159\
|
||||
_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE134\
|
||||
_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE109\
|
||||
_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROB\
|
||||
E83_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE57_MU\
|
||||
_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE31_MU_CNT=1\
|
||||
,C_PROBE30_MU_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE4_M\
|
||||
U_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE0_MU_CNT=1,C_TRIGIN_EN=false,EN_BRAM_DRC=TRUE,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_NUM_MONITOR_SLOTS=2,C_SLOT_0_AXI_ARUSER_WIDTH=1,C_SLOT_0_AXI_RUSER_WIDTH=1,C_SLOT_0_AXI_AWUSER_WIDTH=1,C_SLOT_0_AXI_WUSER_WIDTH=1,C_SLOT_0_AXI_BUSER_WIDTH=1,C_SLOT_0_AXI_ID_WIDTH=AUTO,C_SLOT_0_AXI_DATA_WIDTH=AUTO,C_SLOT_0_AXI_ADDR_WIDTH=AUTO,C_SLOT_0_AXI_PROTOCOL=AXI4,C_SLOT_0_AXIS_TDATA_WIDTH=AUTO,C_SLOT_0_AXIS_TID_WIDTH=AUTO,C_SLOT_\
|
||||
0_AXIS_TUSER_WIDTH=AUTO,C_SLOT_0_AXIS_TDEST_WIDTH=AUTO,C_SLOT_1_AXI_ARUSER_WIDTH=1,C_SLOT_1_AXI_RUSER_WIDTH=1,C_SLOT_1_AXI_AWUSER_WIDTH=1,C_SLOT_1_AXI_WUSER_WIDTH=1,C_SLOT_1_AXI_BUSER_WIDTH=1,C_SLOT_1_AXI_ID_WIDTH=AUTO,C_SLOT_1_AXI_DATA_WIDTH=AUTO,C_SLOT_1_AXI_ADDR_WIDTH=AUTO,C_SLOT_1_AXI_PROTOCOL=AXI4,C_SLOT_1_AXIS_TDATA_WIDTH=AUTO,C_SLOT_1_AXIS_TID_WIDTH=AUTO,C_SLOT_1_AXIS_TUSER_WIDTH=AUTO,C_SLOT_1_AXIS_TDEST_WIDTH=AUTO,C_SLOT_0_INTF_TYPE=xilinx.com_interface_axis_rtl_1.0,C_SLOT_1_INTF_TYPE=xi\
|
||||
linx.com_interface_axis_rtl_1.0,C_SLOT_2_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_3_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_4_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_5_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_6_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_7_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_8_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_9_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_10_INTF_TYPE=xilinx.com_inter\
|
||||
face_aximm_rtl_1.0,C_SLOT_11_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_12_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_13_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_14_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_15_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_MON_TYPE=INTERFACE,C_SLOT_2_AXI_ARUSER_WIDTH=1,C_SLOT_2_AXI_RUSER_WIDTH=1,C_SLOT_2_AXI_AWUSER_WIDTH=1,C_SLOT_2_AXI_WUSER_WIDTH=1,C_SLOT_2_AXI_BUSER_WIDTH=1,C_SLOT_2_AXI_ID_WIDTH=AUTO,C_SLOT_2_AXI_DATA_WID\
|
||||
TH=AUTO,C_SLOT_2_AXI_ADDR_WIDTH=AUTO,C_SLOT_2_AXI_PROTOCOL=AXI4,C_SLOT_2_AXIS_TDATA_WIDTH=AUTO,C_SLOT_2_AXIS_TID_WIDTH=AUTO,C_SLOT_2_AXIS_TUSER_WIDTH=AUTO,C_SLOT_2_AXIS_TDEST_WIDTH=AUTO,C_SLOT_3_AXI_ARUSER_WIDTH=1,C_SLOT_3_AXI_RUSER_WIDTH=1,C_SLOT_3_AXI_AWUSER_WIDTH=1,C_SLOT_3_AXI_WUSER_WIDTH=1,C_SLOT_3_AXI_BUSER_WIDTH=1,C_SLOT_3_AXI_ID_WIDTH=AUTO,C_SLOT_3_AXI_DATA_WIDTH=AUTO,C_SLOT_3_AXI_ADDR_WIDTH=AUTO,C_SLOT_3_AXI_PROTOCOL=AXI4,C_SLOT_3_AXIS_TDATA_WIDTH=AUTO,C_SLOT_3_AXIS_TID_WIDTH=AUTO,C_SLO\
|
||||
T_3_AXIS_TUSER_WIDTH=AUTO,C_SLOT_3_AXIS_TDEST_WIDTH=AUTO,C_SLOT_4_AXI_ARUSER_WIDTH=1,C_SLOT_4_AXI_RUSER_WIDTH=1,C_SLOT_4_AXI_AWUSER_WIDTH=1,C_SLOT_4_AXI_WUSER_WIDTH=1,C_SLOT_4_AXI_BUSER_WIDTH=1,C_SLOT_4_AXI_ID_WIDTH=AUTO,C_SLOT_4_AXI_DATA_WIDTH=AUTO,C_SLOT_4_AXI_ADDR_WIDTH=AUTO,C_SLOT_4_AXI_PROTOCOL=AXI4,C_SLOT_4_AXIS_TDATA_WIDTH=AUTO,C_SLOT_4_AXIS_TID_WIDTH=AUTO,C_SLOT_4_AXIS_TUSER_WIDTH=AUTO,C_SLOT_4_AXIS_TDEST_WIDTH=AUTO,C_SLOT_5_AXI_ARUSER_WIDTH=1,C_SLOT_5_AXI_RUSER_WIDTH=1,C_SLOT_5_AXI_AWUS\
|
||||
ER_WIDTH=1,C_SLOT_5_AXI_WUSER_WIDTH=1,C_SLOT_5_AXI_BUSER_WIDTH=1,C_SLOT_5_AXI_ID_WIDTH=AUTO,C_SLOT_5_AXI_DATA_WIDTH=AUTO,C_SLOT_5_AXI_ADDR_WIDTH=AUTO,C_SLOT_5_AXI_PROTOCOL=AXI4,C_SLOT_5_AXIS_TDATA_WIDTH=AUTO,C_SLOT_5_AXIS_TID_WIDTH=AUTO,C_SLOT_5_AXIS_TUSER_WIDTH=AUTO,C_SLOT_5_AXIS_TDEST_WIDTH=AUTO,C_SLOT_6_AXI_ARUSER_WIDTH=1,C_SLOT_6_AXI_RUSER_WIDTH=1,C_SLOT_6_AXI_AWUSER_WIDTH=1,C_SLOT_6_AXI_WUSER_WIDTH=1,C_SLOT_6_AXI_BUSER_WIDTH=1,C_SLOT_6_AXI_ID_WIDTH=AUTO,C_SLOT_6_AXI_DATA_WIDTH=AUTO,C_SLOT_6\
|
||||
_AXI_ADDR_WIDTH=AUTO,C_SLOT_6_AXI_PROTOCOL=AXI4,C_SLOT_6_AXIS_TDATA_WIDTH=AUTO,C_SLOT_6_AXIS_TID_WIDTH=AUTO,C_SLOT_6_AXIS_TUSER_WIDTH=AUTO,C_SLOT_6_AXIS_TDEST_WIDTH=AUTO,C_SLOT_7_AXI_ARUSER_WIDTH=1,C_SLOT_7_AXI_RUSER_WIDTH=1,C_SLOT_7_AXI_AWUSER_WIDTH=1,C_SLOT_7_AXI_WUSER_WIDTH=1,C_SLOT_7_AXI_BUSER_WIDTH=1,C_SLOT_7_AXI_ID_WIDTH=AUTO,C_SLOT_7_AXI_DATA_WIDTH=AUTO,C_SLOT_7_AXI_ADDR_WIDTH=AUTO,C_SLOT_7_AXI_PROTOCOL=AXI4,C_SLOT_7_AXIS_TDATA_WIDTH=AUTO,C_SLOT_7_AXIS_TID_WIDTH=AUTO,C_SLOT_7_AXIS_TUSER_W\
|
||||
IDTH=AUTO,C_SLOT_7_AXIS_TDEST_WIDTH=AUTO,C_SLOT_8_AXI_ARUSER_WIDTH=1,C_SLOT_8_AXI_RUSER_WIDTH=1,C_SLOT_8_AXI_AWUSER_WIDTH=1,C_SLOT_8_AXI_WUSER_WIDTH=1,C_SLOT_8_AXI_BUSER_WIDTH=1,C_SLOT_8_AXI_ID_WIDTH=AUTO,C_SLOT_8_AXI_DATA_WIDTH=AUTO,C_SLOT_8_AXI_ADDR_WIDTH=AUTO,C_SLOT_8_AXI_PROTOCOL=AXI4,C_SLOT_8_AXIS_TDATA_WIDTH=AUTO,C_SLOT_8_AXIS_TID_WIDTH=AUTO,C_SLOT_8_AXIS_TUSER_WIDTH=AUTO,C_SLOT_8_AXIS_TDEST_WIDTH=AUTO,C_SLOT_9_AXI_ARUSER_WIDTH=1,C_SLOT_9_AXI_RUSER_WIDTH=1,C_SLOT_9_AXI_AWUSER_WIDTH=1,C_SLO\
|
||||
T_9_AXI_WUSER_WIDTH=1,C_SLOT_9_AXI_BUSER_WIDTH=1,C_SLOT_9_AXI_ID_WIDTH=AUTO,C_SLOT_9_AXI_DATA_WIDTH=AUTO,C_SLOT_9_AXI_ADDR_WIDTH=AUTO,C_SLOT_9_AXI_PROTOCOL=AXI4,C_SLOT_9_AXIS_TDATA_WIDTH=AUTO,C_SLOT_9_AXIS_TID_WIDTH=AUTO,C_SLOT_9_AXIS_TUSER_WIDTH=AUTO,C_SLOT_9_AXIS_TDEST_WIDTH=AUTO,C_SLOT_10_AXI_ARUSER_WIDTH=1,C_SLOT_10_AXI_RUSER_WIDTH=1,C_SLOT_10_AXI_AWUSER_WIDTH=1,C_SLOT_10_AXI_WUSER_WIDTH=1,C_SLOT_10_AXI_BUSER_WIDTH=1,C_SLOT_10_AXI_ID_WIDTH=AUTO,C_SLOT_10_AXI_DATA_WIDTH=AUTO,C_SLOT_10_AXI_ADD\
|
||||
R_WIDTH=AUTO,C_SLOT_10_AXI_PROTOCOL=AXI4,C_SLOT_10_AXIS_TDATA_WIDTH=AUTO,C_SLOT_10_AXIS_TID_WIDTH=AUTO,C_SLOT_10_AXIS_TUSER_WIDTH=AUTO,C_SLOT_10_AXIS_TDEST_WIDTH=AUTO,C_SLOT_11_AXI_ARUSER_WIDTH=1,C_SLOT_11_AXI_RUSER_WIDTH=1,C_SLOT_11_AXI_AWUSER_WIDTH=1,C_SLOT_11_AXI_WUSER_WIDTH=1,C_SLOT_11_AXI_BUSER_WIDTH=1,C_SLOT_11_AXI_ID_WIDTH=AUTO,C_SLOT_11_AXI_DATA_WIDTH=AUTO,C_SLOT_11_AXI_ADDR_WIDTH=AUTO,C_SLOT_11_AXI_PROTOCOL=AXI4,C_SLOT_11_AXIS_TDATA_WIDTH=AUTO,C_SLOT_11_AXIS_TID_WIDTH=AUTO,C_SLOT_11_AXI\
|
||||
S_TUSER_WIDTH=AUTO,C_SLOT_11_AXIS_TDEST_WIDTH=AUTO,C_SLOT_12_AXI_ARUSER_WIDTH=1,C_SLOT_12_AXI_RUSER_WIDTH=1,C_SLOT_12_AXI_AWUSER_WIDTH=1,C_SLOT_12_AXI_WUSER_WIDTH=1,C_SLOT_12_AXI_BUSER_WIDTH=1,C_SLOT_12_AXI_ID_WIDTH=AUTO,C_SLOT_12_AXI_DATA_WIDTH=AUTO,C_SLOT_12_AXI_ADDR_WIDTH=AUTO,C_SLOT_12_AXI_PROTOCOL=AXI4,C_SLOT_12_AXIS_TDATA_WIDTH=AUTO,C_SLOT_12_AXIS_TID_WIDTH=AUTO,C_SLOT_12_AXIS_TUSER_WIDTH=AUTO,C_SLOT_12_AXIS_TDEST_WIDTH=AUTO,C_SLOT_13_AXI_ARUSER_WIDTH=1,C_SLOT_13_AXI_RUSER_WIDTH=1,C_SLOT_1\
|
||||
3_AXI_AWUSER_WIDTH=1,C_SLOT_13_AXI_WUSER_WIDTH=1,C_SLOT_13_AXI_BUSER_WIDTH=1,C_SLOT_13_AXI_ID_WIDTH=AUTO,C_SLOT_13_AXI_DATA_WIDTH=AUTO,C_SLOT_13_AXI_ADDR_WIDTH=AUTO,C_SLOT_13_AXI_PROTOCOL=AXI4,C_SLOT_13_AXIS_TDATA_WIDTH=AUTO,C_SLOT_13_AXIS_TID_WIDTH=AUTO,C_SLOT_13_AXIS_TUSER_WIDTH=AUTO,C_SLOT_13_AXIS_TDEST_WIDTH=AUTO,C_SLOT_14_AXI_ARUSER_WIDTH=1,C_SLOT_14_AXI_RUSER_WIDTH=1,C_SLOT_14_AXI_AWUSER_WIDTH=1,C_SLOT_14_AXI_WUSER_WIDTH=1,C_SLOT_14_AXI_BUSER_WIDTH=1,C_SLOT_14_AXI_ID_WIDTH=AUTO,C_SLOT_14_A\
|
||||
XI_DATA_WIDTH=AUTO,C_SLOT_14_AXI_ADDR_WIDTH=AUTO,C_SLOT_14_AXI_PROTOCOL=AXI4,C_SLOT_14_AXIS_TDATA_WIDTH=AUTO,C_SLOT_14_AXIS_TID_WIDTH=AUTO,C_SLOT_14_AXIS_TUSER_WIDTH=AUTO,C_SLOT_14_AXIS_TDEST_WIDTH=AUTO,C_SLOT_15_AXI_ARUSER_WIDTH=1,C_SLOT_15_AXI_RUSER_WIDTH=1,C_SLOT_15_AXI_AWUSER_WIDTH=1,C_SLOT_15_AXI_WUSER_WIDTH=1,C_SLOT_15_AXI_BUSER_WIDTH=1,C_SLOT_15_AXI_ID_WIDTH=AUTO,C_SLOT_15_AXI_DATA_WIDTH=AUTO,C_SLOT_15_AXI_ADDR_WIDTH=AUTO,C_SLOT_15_AXI_PROTOCOL=AXI4,C_SLOT_15_AXIS_TDATA_WIDTH=AUTO,C_SLOT_\
|
||||
15_AXIS_TID_WIDTH=AUTO,C_SLOT_15_AXIS_TUSER_WIDTH=AUTO,C_SLOT_15_AXIS_TDEST_WIDTH=AUTO,C_PROBE_WIDTH_PROPAGATION=AUTO}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_syn_system_ila_0_2 (
|
||||
clk,
|
||||
@@ -251,7 +251,7 @@ input wire SLOT_1_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.resetn RST" *)
|
||||
input wire resetn;
|
||||
|
||||
bd_3e86 inst (
|
||||
bd_3e86_0 inst (
|
||||
.clk(clk),
|
||||
.SLOT_0_AXIS_tdata(SLOT_0_AXIS_tdata),
|
||||
.SLOT_0_AXIS_tlast(SLOT_0_AXIS_tlast),
|
||||
|
||||
+552
@@ -0,0 +1,552 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
IYB6YMUpLRG67Sjv6mvLa0lJDa9M83l3pszRl7mNKDbm3JQq1xub6O3MDaxf4WUUoRlbj6UmK+ls
|
||||
5TT1rZBI42slY2M8d8G/12u9ZwNU0B9Ysw0A9f7H2/gZw+bCFVT2XOufXRtM8469/cgTzPdX6455
|
||||
eehGCOlFNzztUpCCBuo=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
a/7EQ8W4oMyysM5YxqT496V07EUaiHtsiTeMr+xwggjSXDgZBxdH9zS0ZwSbWGNiHwg8nXSCMzIT
|
||||
bUcHpdhYenBbvS6lFHc+OYja/GxpeotPfuhlGtbxN3fXZjw43NjXQI/ojWzEeo5ATyxr94HJ8sHD
|
||||
JA1CsMdglOQT6QZiD9TVY3RkvJVUxzXGEK/4umSz/Fc5dPh6gxxp7cVofeuJ+snpie5VVQQJoj4j
|
||||
tjyBNmGrIhr0Y0IV+3TgWooJ+r24u/VBLLE6lnzKxh0zYnJ5zUjs4eHuQTqInalvOAdYvbUSVqio
|
||||
Lzp5Bj6tb7kmD+A/qe86yLb4GbJzLTehOjcfdg==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
Bm8/8qhHbJitBA3cG0BWpho8+cHGNcXoWDJOit3rZ1HeeUrKdPeoNkL9hkzhf9ZUHxLpbdTUCjkz
|
||||
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|
||||
v0IjKU+PjNN3ZYIXCkA=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
bOGsLKO2Wjd3RNfQsUHtM5NcPLVbC6ZCRWCjSRRmyvuNhRjavSsIHbXkxLZHDjZnlnBuHdEZ8oea
|
||||
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|
||||
dxDZeGYfZaF3iUzWGpDyEDaQh7d/AMIR890b/cRJ0JPD6S/d68REfiAIau8ZUsXiSCgHP9ot5Why
|
||||
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|
||||
IHl8aYzdxpc89jXiMIYfoqN06f8LwbIAKe3Z+w==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
xyJ+44oGcnu3f/PRr5Q/pt05L20B492JqgiTtcs5oGrsK7nBtr3Jek5JEMvW6gatRMUMnyBEipiF
|
||||
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|
||||
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|
||||
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|
||||
mywjCvcVbMSrJkkJ6lHrazZzzBU8tJ9SXhvc1A==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
DKpQGvLhbUl8BJ/8XLn/tPRtGzCl6Z5B9dlBIZ3hIdMpvX5L6qTHJiPL+EPJzvKR3hwn+y3Kf0/e
|
||||
56tD0N9yqf/8HSBzUPN1Wx83eiE7+pWNxuGq7e15dNN7e3+AcR7gjUu0hLG5jSqOt75iiFr0vqqy
|
||||
UPb39HUFrCDaIRNh0fCFdGbydh7zEuizbnn7GRErU0r//wJ+WqhZsjKAuSH/9rkJXt5VJzrFRh2H
|
||||
2zZzduUfRWhphNTH09M8QAQ5RSWmlr7t9fXON4HIIaNpt14zvilBmCZgEfyV1N7+Mbi8zISGSVwM
|
||||
r20FpLJcMjFy8H4kZ7SMF51dIlCCySUMitZhBw==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ahGj9cu5vw+TGhDRETTpUmguNUrGkzj4c4HpfbBQWexaOi1CnxDewq4mIuyo2pPRt9bsxMyxinAi
|
||||
yqfZSys3iKpMLTF2rLlaJR5DR+s7MHg3TXo6DwE4YOUz2kUn+kcmB5Oipr2uxn5fY/2OTA6236rk
|
||||
kg96Xfcnb3hsRdNnyl3s8r1r/GO6lcYCfWw2HtuVB73JqZOdMK5WQnRs2nCzyarDak52q8w92CuR
|
||||
jtBAO6iM8C8YYYtdY3bZrNoY2ErKwC2x21gWULEUfsaHyjjhoA1gN+VnA1jThgYsbf0kWw13Grhs
|
||||
2COb8mAkB/0fC26SxfxSy30x8trX0jLDnfntAQ==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0Zjf5PrRbObEBaQt8a9CnelDkWVdP3uTr1rSFz+syFbYPJ/3XU2G/yLmk16QYP9kCQo9CAcIjwxh
|
||||
g41o91RxGZj8PwCpcnZrAoW7se6+/H5h2JrNvoOz8Yr09ZkOhWM0r75h8Rx3OyutUqeqr3BQ1b9B
|
||||
lvB/+l6p6intfTshH8BsTtE0j292jiNGV5cvexC4cczkPuzrIeMxa/xJ
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
eSvh9J2q6NyrGpZqUatGKIA8QDMInI2iwKgziwfCT+i9aojxHhLpFdTm0zLW6vVDbs/IusTTBrYn
|
||||
NVfkcSUH5/jvLRUwLbq9vzH+BhvxZBvdurXPgSJdE/TAka47qAK1KWzgbQ6eoz88SN7MyuoSGGc2
|
||||
6gS0Ba5hhKYx1b8sr66Gjx3DlfaRtcEogEfV8f3DF6j6eL2oGyE6eN3jJQqh8Pb+VBypaE4ia9pR
|
||||
761fYKzcrhd3nvqYI+jRFosC0ZHv3akRZ/GMMOUX9fnkYWn3o4X9t46tehxqU8PXPrS3v/ZJ5wrY
|
||||
YQ/jig9XDE4QndCSZD1niwWxZJrJd1mXs1KKGg==
|
||||
|
||||
`pragma protect key_keyowner = "Synplicity", key_keyname = "SYNP15_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ff7t8AbFHBpUzmzv37xcV3BaELGXwW2FFoCl9wmbcAMmSLJEeoiYqjiI3XDM4XpMM3cFNM8gQmKz
|
||||
BgEuusWTof+slNUrSsJ5oD354i7b4BucHhOJi1f+LOwqns8ZlfE/Rrpmykq3ApSBIOhbi9mNKfnK
|
||||
0MBBVAY6hK/VLC5VYOy/Nhmbs3uqrr3hY4m+IK3Chy3QTHRdwhQwtRH2hUniNN2nHd1JIS4VwB8x
|
||||
uPCb97uEaIy8cz6h1SApBmWrY9IZKiXvZnBlqAzoVGxsqGB41TtpIISbliL2hGXUFSu0bz8RHT2F
|
||||
fkM9u94uhLFDP/QYjq/SfpByClx8fogg7ejfDA==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-PREC-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
oBc5fYhhP4GDV60D8m6mIIi+6Xspsu6fa6mpRPbQL3lyyZOIW7aY9ehXKE4SewCv0/fpmHMByAsF
|
||||
aFhoGiVGdHT2TtQShdlc5CHrugjHogcTwVhX0awKmb62UeeyTfMrM2krGBcv+KTY+E9Yt4zJZAVM
|
||||
Sf+2Tmup8qb8oKz98yBNuBAlfxqK/VJZfPBeAYq5W5l7vgUBXOhnsiIKqnEuaPcfRrrjrrsrueT9
|
||||
RmvfXIlDjIIC1Vo8LUH+sn4SFtvEa6+9wj+hYFhalOtpexbpZgcDdBcHxxVsqh4fdv9fY6R1msRB
|
||||
ZZFKiIK50d7XvGw4Rs5DAg9ESYyF7BOlcRBOsg==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25472)
|
||||
`pragma protect data_block
|
||||
/9vfmgSxR/Rz5jH6WG+Vbr4TobbsOI1owrDDlkeEUmRviechxnb4JeBm0rumqx23QCmYo6p2Q00o
|
||||
BMwgC4UHixTsIVC3K7DTr0QzFajBYbdnkynjCejGnjlIjxdxz5qf12AePggB4LJXEx0Lv/MKJxp9
|
||||
OiAMa6w/YLl34eImd2P3vCX8r2jJnF3nZlOaW53bqZoGq8TzVQyk5lHWgkwIquCYMRUxSmLSrVWD
|
||||
i2/BnIBWZYq2Jo7PGTLaKk9zgjogdKiVWZD48olniusa673x30stQ0i2WLTbpk8wOt1RTSS48DWE
|
||||
cOFtEK7fzyZgIHPXta5+tHQ8HNf6Q6Aydb1F4d8Eidlaetp17hoGLE2Zdli/H8cY4TQmh/pkD13/
|
||||
B8jLAD286BTywt7XCSPGU+GkJH7+zq/qQQuNPKXCFRzahVkJ0vEgZFiCGEE7192SgHZ7hI1eLG+Z
|
||||
vSMhA3qIl8u2dmZoQPqwPsUDSqJU1u9zjHcsoVCj+4jrVqsFZ55jtLH6UIYb/Cq3IIcmS2cO+wvN
|
||||
/MYM02wyZUs3ivY8zw6Y1B4XISjGf5ff3Smo3xLtvu5dnBHnxb2nywTNv4KFzwh0HVB8z/eTLrs1
|
||||
5ACXQdKRPCQefxVeqm1vEigm9zoYQ+3gkByG9RNOdVi7pAOwAtawfcWtvLdinYsKFU9oUoEFF9YZ
|
||||
WEP6gfy4Dd/YNTLVxp7v0721mnHz4gSXuwzPkJ3XAUMCUXMr6PAS3pT3Mdv15Rb/n7fc3PUoodHv
|
||||
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|
||||
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|
||||
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|
||||
SPEKU/Ms9fJZof3cvJhpYjSnvuDEVT6iqpXm35Pbum1vTzYJk7eRcuAEnuyBcDTYTZ0zh6a/8MzZ
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
XSvy7ymlpCMVAVk0fBjIoIU6G63yq5rQu7BeiUaO3AojOk28dB5r8ssqaBZW1rtRUXP7CSdLnKxi
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
r/10w2V0gFkMSDhmv+PBfMBPTpeoT11J8AuBFMpGMXkyVlaILF6XuHQBG6TZ41aIKFuofVl8QbWi
|
||||
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|
||||
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|
||||
f3/mWYOomdjU+AXsG4VUN/Kfe9FRs3nkcwcZxdqn7/iVfppV9CvXKiL6SHuEKmliKf448ofBMVJm
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
g8YVI/vct7N5iy7CCldQtUh3XkuJLs1S/UL08Kq8inBLes/7ZAA9+L7yVXNEtLTj2aHeEHtsRy2R
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
pifEd/zZ691vGAmbd5uVkllTCmK5FlI1QQRaBcjJukdP3jcCX9cUuNr5TR9TG4gh5N3IuVHmrDNR
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0gzhH+sjJZlyzbK1vPN9PZWN9a03krWoz1cMboFth+zhcIvkWvv9AIxg76pimBHsOXnA8ehv/fph
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
F6+hJAizIG48Z3Ee/uvTIpzYJX0wEAuVrjTZRSzbyx2BDUxz5921JjCV3WrFR8oc9fH81SRz5JsW
|
||||
zD9Y4/OIbfLInO4N5NFAsM+Yxmk2CGs+KexqYUuF1MZhPrOWYGWJe9FiIMTd+Nejk9hvXeIbvtYW
|
||||
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|
||||
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|
||||
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|
||||
6QrgZDu16PWp2buBRAMUj4ktBh//jSl6h4BwKUHR3kiNh1/4Cnd9/wINx7cDK4lUtcg=
|
||||
`pragma protect end_protected
|
||||
+1241
File diff suppressed because it is too large
Load Diff
+7910
File diff suppressed because it is too large
Load Diff
+193171
File diff suppressed because it is too large
Load Diff
+8826
File diff suppressed because it is too large
Load Diff
+193219
File diff suppressed because it is too large
Load Diff
+31647
File diff suppressed because it is too large
Load Diff
+287
@@ -0,0 +1,287 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
k1jcY8lFjetrBZOo7Tg=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
AB1sYtukt5mXbeMyi/lgTz8BCAY61ptehv0vQg==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
a9/LrZ2uzBBzAo7zHMY=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
2Lodrp/uTk41S5ga0S142suf1vixEbsLt8Jd3A==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
OO2gqrMgzKMHqHx28cFT5P5wPltWhh+vkFAngA==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
EvHxMN5n4ZLBneMHuAMYzSAtuPSU/kW0Utuauw==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
b/ikbNkY/8vWVmXkQQuseZIc9Ft5dbZ7HhnvpYanTPQq8abw5e8ttsiUN5p0Gy4+TEKVw9wLZgxh
|
||||
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|
||||
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|
||||
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|
||||
zDoMHc5vM5cQ1BHDEzCITwQUL34e5amtzEO3HQ==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
lS23lbsML4iLFvURB3qgD7fuVIqK/Nr04HhjVvxDa0RN9Ql26FzIigHn
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
BL0oElfsCxTkqxNUXjTtgPCO9K4pIhF4qwi8Pg==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11376)
|
||||
`pragma protect data_block
|
||||
qvXUzIRz5FPcvtu+R954oR4c/CAPnWZYGcu/WVb49Z3b/mZaj9xZxuoWfcPJZKPH1ZhdV85cG/cF
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
pA9zR9FBA+Ukotntno0zCeJKsL2C81yPEdm+rzqKKWegoc27b2pBp3hmAz1/p/DTBhK7T3gye6dv
|
||||
K90P7C/5/rgvfW/31W+nHLf1IDE7CS00NptavQ5xzR2X55QfXWQTM2YU9gx/xNyjYA9FVM4MrG8D
|
||||
YOZQc6W9/mZmakkrOhf7ARa8MPLJ+n4Vl/1ce96LxRsBjOYDDsGRTXaYlNiXkr14h7fesgpp14xW
|
||||
6Xzg9bjTMfoVh+h0x0b1BdVczYIWN351lU111uCwnphRwqX621nMXr1OP234y6cD7X0I7kZ/TBoz
|
||||
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||||
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|
||||
2eSn/Wxnk8ddBMbFt6Ab3EgJAuqYqil+dWl4OI7li1RDFSGjyEeV4Ye/jGDEkrSKlp2DXuo/jw8S
|
||||
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|
||||
KzifgDZR4CUnJ+7KcmxiDCpREXhnVYYNySkFglCvOdmAF1QDeJjfrYoUMWq7xGJAOpVeICiGTqM8
|
||||
KGSBVvDCm6IeJ5d67NpBioxBgmSF6JmOSBGRyucev1SNnd22btku2i9DqD/cDnBL2bZKBLYS/rqM
|
||||
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|
||||
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||||
FkVBZKyvfqgK6LfCgfvsfBiLaFKMAzoEyAklbj2z0S1jPjcW7/2nYvX8yrrDL2U+UJz3m7xzFCy5
|
||||
GrWGq9Dz12IvI0fA9ZarpEfBeQjN99CbwKkfBXRcaH3bxsMW0XbOH0yy5kLhfNkJ7jIynTZTyPJ8
|
||||
QhGzUwRXdk4MMr45pfTUIMAeaCHEv8fJY6s5DYZ4/z15F67YmaGz9tWmti82jLNyIWJ1J4yvpDpv
|
||||
qY5yY+Z9REBIYqBIGaS27ku0bSbXwFPHQhHX0s/xqPiU
|
||||
`pragma protect end_protected
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Oct 28 22:04:25 2024
|
||||
//Date : Wed Nov 20 16:36:50 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_syn.bd
|
||||
//Design : design_1_syn
|
||||
|
||||
BIN
Binary file not shown.
+1
-1
@@ -2,7 +2,7 @@
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Oct 28 22:04:25 2024
|
||||
//Date : Wed Nov 20 16:36:50 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_syn.bd
|
||||
//Design : design_1_syn
|
||||
|
||||
+3
-3
@@ -145,7 +145,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>d95d689b</spirit:value>
|
||||
<spirit:value>c53ced1d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -158,7 +158,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>d95d689b</spirit:value>
|
||||
<spirit:value>c53ced1d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -386,7 +386,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-10-28T14:40:21Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2024-11-20T15:36:09Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
+6
-7
@@ -7,8 +7,7 @@
|
||||
"name": "design_1_sim",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
"tool_version": "2023.1"
|
||||
},
|
||||
"design_tree": {
|
||||
"clk_rst_generator_0": "",
|
||||
@@ -73,7 +72,7 @@
|
||||
"xci_path": "ip\\design_1_sim_axis_audio_bitcrusher_0_0\\design_1_sim_axis_audio_bitcrusher_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_bitcrusher_0",
|
||||
"reference_info": {
|
||||
"ref_type": "unknown",
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_audio_bitcrusher",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
@@ -269,17 +268,17 @@
|
||||
"clk_rst_generator_0/clk",
|
||||
"axis_audio_master_si_0/ACLK",
|
||||
"axis_audio_stereo2mo_0/AXIS_ACLK",
|
||||
"axis_audio_bitcrusher_0/AXIS_ACLK",
|
||||
"axis_audio_mono2ster_0/AXIS_ACLK",
|
||||
"axis_audio_slave_sim_0/ACLK"
|
||||
"axis_audio_slave_sim_0/ACLK",
|
||||
"axis_audio_bitcrusher_0/AXIS_ACLK"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_rst_n": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axis_audio_master_si_0/ARESETN",
|
||||
"axis_audio_bitcrusher_0/AXIS_ARESETN",
|
||||
"axis_audio_slave_sim_0/ARESETN"
|
||||
"axis_audio_slave_sim_0/ARESETN",
|
||||
"axis_audio_bitcrusher_0/AXIS_ARESETN"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
||||
+80
-80
@@ -11,12 +11,12 @@
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"axis_audio_bitcrusher_0": "",
|
||||
"clk_rst_generator_0": "",
|
||||
"axis_audio_stereo2mo_0": "",
|
||||
"axis_audio_mono2ster_0": "",
|
||||
"zybo_audio_0": "",
|
||||
"system_ila_0": ""
|
||||
"system_ila_0": "",
|
||||
"axis_audio_bitcrusher_0": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"i2c": {
|
||||
@@ -81,6 +81,80 @@
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"clk_rst_generator_0": {
|
||||
"vlnv": "wg:user:clk_rst_generator:1.0",
|
||||
"xci_name": "design_1_syn_clk_rst_generator_0_0",
|
||||
"xci_path": "ip\\design_1_syn_clk_rst_generator_0_0\\design_1_syn_clk_rst_generator_0_0.xci",
|
||||
"inst_hier_path": "clk_rst_generator_0"
|
||||
},
|
||||
"axis_audio_stereo2mo_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"xci_name": "design_1_syn_axis_audio_stereo2mo_0_0",
|
||||
"xci_path": "ip\\design_1_syn_axis_audio_stereo2mo_0_0\\design_1_syn_axis_audio_stereo2mo_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_stereo2mo_0"
|
||||
},
|
||||
"axis_audio_mono2ster_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"xci_name": "design_1_syn_axis_audio_mono2ster_0_0",
|
||||
"xci_path": "ip\\design_1_syn_axis_audio_mono2ster_0_0\\design_1_syn_axis_audio_mono2ster_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_mono2ster_0"
|
||||
},
|
||||
"zybo_audio_0": {
|
||||
"vlnv": "xilinx.com:user:zybo_audio:1.0",
|
||||
"xci_name": "design_1_syn_zybo_audio_0_0",
|
||||
"xci_path": "ip\\design_1_syn_zybo_audio_0_0\\design_1_syn_zybo_audio_0_0.xci",
|
||||
"inst_hier_path": "zybo_audio_0"
|
||||
},
|
||||
"system_ila_0": {
|
||||
"vlnv": "xilinx.com:ip:system_ila:1.1",
|
||||
"xci_name": "design_1_syn_system_ila_0_2",
|
||||
"xci_path": "ip\\design_1_syn_system_ila_0_2\\design_1_syn_system_ila_0_2.xci",
|
||||
"inst_hier_path": "system_ila_0",
|
||||
"parameters": {
|
||||
"C_MON_TYPE": {
|
||||
"value": "INTERFACE"
|
||||
},
|
||||
"C_NUM_MONITOR_SLOTS": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_SLOT_0_APC_EN": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_DATA_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_TRIG_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_INTF_TYPE": {
|
||||
"value": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"C_SLOT_1_APC_EN": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXI_DATA_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_AXI_TRIG_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_INTF_TYPE": {
|
||||
"value": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"SLOT_0_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_audio_bitcrusher_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_audio_bitcrusher:1.0",
|
||||
"xci_name": "design_1_syn_axis_audio_bitcrusher_0_0",
|
||||
@@ -237,80 +311,6 @@
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"clk_rst_generator_0": {
|
||||
"vlnv": "wg:user:clk_rst_generator:1.0",
|
||||
"xci_name": "design_1_syn_clk_rst_generator_0_0",
|
||||
"xci_path": "ip\\design_1_syn_clk_rst_generator_0_0\\design_1_syn_clk_rst_generator_0_0.xci",
|
||||
"inst_hier_path": "clk_rst_generator_0"
|
||||
},
|
||||
"axis_audio_stereo2mo_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"xci_name": "design_1_syn_axis_audio_stereo2mo_0_0",
|
||||
"xci_path": "ip\\design_1_syn_axis_audio_stereo2mo_0_0\\design_1_syn_axis_audio_stereo2mo_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_stereo2mo_0"
|
||||
},
|
||||
"axis_audio_mono2ster_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"xci_name": "design_1_syn_axis_audio_mono2ster_0_0",
|
||||
"xci_path": "ip\\design_1_syn_axis_audio_mono2ster_0_0\\design_1_syn_axis_audio_mono2ster_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_mono2ster_0"
|
||||
},
|
||||
"zybo_audio_0": {
|
||||
"vlnv": "xilinx.com:user:zybo_audio:1.0",
|
||||
"xci_name": "design_1_syn_zybo_audio_0_0",
|
||||
"xci_path": "ip\\design_1_syn_zybo_audio_0_0\\design_1_syn_zybo_audio_0_0.xci",
|
||||
"inst_hier_path": "zybo_audio_0"
|
||||
},
|
||||
"system_ila_0": {
|
||||
"vlnv": "xilinx.com:ip:system_ila:1.1",
|
||||
"xci_name": "design_1_syn_system_ila_0_2",
|
||||
"xci_path": "ip\\design_1_syn_system_ila_0_2\\design_1_syn_system_ila_0_2.xci",
|
||||
"inst_hier_path": "system_ila_0",
|
||||
"parameters": {
|
||||
"C_MON_TYPE": {
|
||||
"value": "INTERFACE"
|
||||
},
|
||||
"C_NUM_MONITOR_SLOTS": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_SLOT_0_APC_EN": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_DATA_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_TRIG_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_INTF_TYPE": {
|
||||
"value": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"C_SLOT_1_APC_EN": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXI_DATA_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_AXI_TRIG_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_INTF_TYPE": {
|
||||
"value": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"SLOT_0_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
@@ -374,17 +374,17 @@
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
"axis_audio_stereo2mo_0/AXIS_ACLK",
|
||||
"axis_audio_bitcrusher_0/AXIS_ACLK",
|
||||
"axis_audio_mono2ster_0/AXIS_ACLK",
|
||||
"zybo_audio_0/clk",
|
||||
"system_ila_0/clk"
|
||||
"system_ila_0/clk",
|
||||
"axis_audio_bitcrusher_0/AXIS_ACLK"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_rst_n": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axis_audio_bitcrusher_0/AXIS_ARESETN",
|
||||
"system_ila_0/resetn"
|
||||
"system_ila_0/resetn",
|
||||
"axis_audio_bitcrusher_0/AXIS_ARESETN"
|
||||
]
|
||||
},
|
||||
"rec_dat_0_1": {
|
||||
|
||||
+35
-55
@@ -3865,25 +3865,15 @@
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"SLOT_0_AXIS_tid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tdest": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tdata": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tstrb": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_0_AXIS_tkeep": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_0_AXIS_tlast": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tuser": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tvalid": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"SLOT_0_AXIS_tready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"SLOT_1_AXIS_tid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tdest": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tdata": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tstrb": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_1_AXIS_tkeep": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_1_AXIS_tlast": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tuser": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tvalid": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"SLOT_1_AXIS_tready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"resetn": [ { "direction": "in" } ]
|
||||
"SLOT_0_AXIS_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tready": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_1_AXIS_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tready": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"resetn": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.clk": {
|
||||
@@ -3891,13 +3881,13 @@
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "bd_3e86_clk", "value_src": "default_prop", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXIS:SLOT_1_AXIS", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "bd_3e86_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXIS:SLOT_1_AXIS", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
@@ -3909,7 +3899,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
@@ -3921,28 +3911,23 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "monitor",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "bd_3e86_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TID": [ { "physical_name": "SLOT_0_AXIS_tid" } ],
|
||||
"TDEST": [ { "physical_name": "SLOT_0_AXIS_tdest" } ],
|
||||
"TDATA": [ { "physical_name": "SLOT_0_AXIS_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "SLOT_0_AXIS_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "SLOT_0_AXIS_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "SLOT_0_AXIS_tlast" } ],
|
||||
"TUSER": [ { "physical_name": "SLOT_0_AXIS_tuser" } ],
|
||||
"TVALID": [ { "physical_name": "SLOT_0_AXIS_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "SLOT_0_AXIS_tready" } ]
|
||||
}
|
||||
@@ -3952,28 +3937,23 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "monitor",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "bd_3e86_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TID": [ { "physical_name": "SLOT_1_AXIS_tid" } ],
|
||||
"TDEST": [ { "physical_name": "SLOT_1_AXIS_tdest" } ],
|
||||
"TDATA": [ { "physical_name": "SLOT_1_AXIS_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "SLOT_1_AXIS_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "SLOT_1_AXIS_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "SLOT_1_AXIS_tlast" } ],
|
||||
"TUSER": [ { "physical_name": "SLOT_1_AXIS_tuser" } ],
|
||||
"TVALID": [ { "physical_name": "SLOT_1_AXIS_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "SLOT_1_AXIS_tready" } ]
|
||||
}
|
||||
|
||||
+6
-6
@@ -15,16 +15,16 @@ preplace port port-id_mute -pg 1 -lvl 6 -x 1360 -y 120 -defaultsOSRD
|
||||
preplace port port-id_rec_lrc -pg 1 -lvl 6 -x 1360 -y 270 -defaultsOSRD
|
||||
preplace port port-id_rec_dat -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
|
||||
preplace port port-id_reset -pg 1 -lvl 0 -x 0 -y 150 -defaultsOSRD
|
||||
preplace inst axis_audio_bitcrusher_0 -pg 1 -lvl 3 -x 660 -y 140 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 130 -y 150 -defaultsOSRD
|
||||
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 2 -x 360 -y 400 -defaultsOSRD
|
||||
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 950 -y 70 -defaultsOSRD
|
||||
preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1180 -y 140 -defaultsOSRD
|
||||
preplace inst system_ila_0 -pg 1 -lvl 4 -x 950 -y 230 -defaultsOSRD
|
||||
preplace inst axis_audio_bitcrusher_0 -pg 1 -lvl 3 -x 660 -y 140 -defaultsOSRD
|
||||
preplace netloc clk_1 1 0 1 20J 120n
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 250 140 520 50 830 320 1060
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 240 140 520 50 820 320 1070
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 NJ 160 510 260 N
|
||||
preplace netloc rec_dat_0_1 1 0 5 NJ 70 NJ 70 460J 60 840J 140 1050J
|
||||
preplace netloc rec_dat_0_1 1 0 5 NJ 70 NJ 70 470J 60 830J 140 1060J
|
||||
preplace netloc reset_1 1 0 1 NJ 150
|
||||
preplace netloc zybo_audio_0_bclk 1 5 1 1330J 150n
|
||||
preplace netloc zybo_audio_0_mclk 1 5 1 1340J 130n
|
||||
@@ -32,10 +32,10 @@ preplace netloc zybo_audio_0_mute 1 5 1 1340J 110n
|
||||
preplace netloc zybo_audio_0_pb_dat 1 5 1 1320J 170n
|
||||
preplace netloc zybo_audio_0_pb_lrc 1 5 1 1310J 190n
|
||||
preplace netloc zybo_audio_0_rec_lrc 1 5 1 1300J 210n
|
||||
preplace netloc axis_audio_bitcrusher_0_M_AXIS 1 3 1 850 60n
|
||||
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 1050 70n
|
||||
preplace netloc axis_audio_bitcrusher_0_M_AXIS 1 3 1 840 60n
|
||||
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 1060 70n
|
||||
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 530 220 NJ
|
||||
preplace netloc zybo_audio_0_axis_rec 1 1 5 260 330 NJ 330 NJ 330 NJ 330 1290
|
||||
preplace netloc zybo_audio_0_axis_rec 1 1 5 250 330 NJ 330 NJ 330 NJ 330 1290
|
||||
preplace netloc zybo_audio_0_i2c 1 5 1 NJ 90
|
||||
levelinfo -pg 1 0 130 360 660 950 1180 1360
|
||||
pagesize -pg 1 -db -bbox -sgen -100 0 1460 470
|
||||
|
||||
@@ -107,21 +107,21 @@
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_axis_audio_bitcrusher_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_axis_audio_stereo2mo_0_0/design_1_syn_axis_audio_stereo2mo_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_axis_audio_stereo2mo_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_zybo_audio_0_0/design_1_syn_zybo_audio_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_zybo_audio_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_clk_rst_generator_0_0/design_1_syn_clk_rst_generator_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_clk_rst_generator_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_axis_audio_stereo2mo_0_0/design_1_syn_axis_audio_stereo2mo_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_axis_audio_stereo2mo_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_system_ila_0_2/design_1_syn_system_ila_0_2.xci">
|
||||
<Proxy FileSetName="design_1_syn_system_ila_0_2"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_axis_audio_mono2ster_0_0/design_1_syn_axis_audio_mono2ster_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_axis_audio_mono2ster_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_zybo_audio_0_0/design_1_syn_zybo_audio_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_zybo_audio_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/design_1_syn/hdl/design_1_syn_wrapper.v">
|
||||
<FileInfo>
|
||||
@@ -188,6 +188,14 @@
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/design_1_syn_wrapper.dcp">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedInSteps" Val="synth_1"/>
|
||||
<Attr Name="AutoDcp" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
@@ -198,12 +206,6 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_syn_axis_audio_bitcrusher_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_syn_axis_audio_bitcrusher_0_0" RelGenDir="$PGENDIR/design_1_syn_axis_audio_bitcrusher_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_syn_axis_audio_bitcrusher_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_syn_axis_audio_mono2ster_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_syn_axis_audio_mono2ster_0_0" RelGenDir="$PGENDIR/design_1_syn_axis_audio_mono2ster_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_syn_axis_audio_mono2ster_0_0"/>
|
||||
@@ -228,6 +230,12 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_syn_axis_audio_bitcrusher_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_syn_axis_audio_bitcrusher_0_0" RelGenDir="$PGENDIR/design_1_syn_axis_audio_bitcrusher_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_syn_axis_audio_bitcrusher_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@@ -248,7 +256,7 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="20">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/design_1_syn_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
@@ -268,16 +276,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_bitcrusher_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_syn_axis_audio_bitcrusher_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_bitcrusher_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_syn_axis_audio_bitcrusher_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_mono2ster_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_syn_axis_audio_mono2ster_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_mono2ster_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_syn_axis_audio_mono2ster_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_mono2ster_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_mono2ster_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
@@ -318,6 +316,18 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_bitcrusher_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_syn_axis_audio_bitcrusher_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_bitcrusher_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_syn_axis_audio_bitcrusher_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
@@ -353,23 +363,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_bitcrusher_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_bitcrusher_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_syn_axis_audio_bitcrusher_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_mono2ster_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_mono2ster_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_syn_axis_audio_mono2ster_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_mono2ster_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_mono2ster_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
@@ -438,6 +431,25 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_bitcrusher_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_bitcrusher_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_syn_axis_audio_bitcrusher_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
|
||||
@@ -4,8 +4,8 @@ use ieee.numeric_std.all;
|
||||
|
||||
entity axis_audio_bitcrusher is
|
||||
generic(
|
||||
BIT_REDUCTION : integer := 14;
|
||||
HAS_LAST : boolean := false
|
||||
BIT_REDUCTION : integer := 14;
|
||||
HAS_LAST : boolean := false
|
||||
);
|
||||
port
|
||||
(
|
||||
|
||||
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1733073470"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1733073470"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1733073470"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1733073470"/>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1733753232"/>
|
||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1733753232"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1733753232"/>
|
||||
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1733753232"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
|
||||
+93
-96
@@ -1498,10 +1498,6 @@
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Dec 01 17:20:13 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a57455c3</spirit:value>
|
||||
@@ -1701,7 +1697,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1714,7 +1710,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1731,7 +1727,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1758,7 +1754,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1785,7 +1781,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1812,7 +1808,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1839,7 +1835,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1866,7 +1862,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1893,7 +1889,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1920,7 +1916,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1947,7 +1943,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1974,7 +1970,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2001,7 +1997,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2024,7 +2020,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2047,7 +2043,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2071,7 +2067,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2098,7 +2094,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2125,7 +2121,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2148,7 +2144,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2175,7 +2171,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2198,7 +2194,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2221,7 +2217,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2245,7 +2241,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2269,7 +2265,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2293,7 +2289,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2313,7 +2309,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2333,7 +2329,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2360,7 +2356,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2387,7 +2383,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2414,7 +2410,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2441,7 +2437,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2468,7 +2464,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2495,7 +2491,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2522,7 +2518,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2549,7 +2545,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2576,7 +2572,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2603,7 +2599,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2630,7 +2626,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2653,7 +2649,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2676,7 +2672,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2700,7 +2696,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2724,7 +2720,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2748,7 +2744,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2768,7 +2764,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2792,7 +2788,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2812,7 +2808,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2832,7 +2828,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2859,7 +2855,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2883,7 +2879,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2907,7 +2903,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2931,7 +2927,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2955,7 +2951,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2979,7 +2975,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3003,7 +2999,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3027,7 +3023,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3051,7 +3047,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3075,7 +3071,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3099,7 +3095,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3119,7 +3115,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3139,7 +3135,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3166,7 +3162,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3190,7 +3186,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3214,7 +3210,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3234,7 +3230,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3258,7 +3254,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3278,7 +3274,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3298,7 +3294,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3325,7 +3321,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3352,7 +3348,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3379,7 +3375,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3402,7 +3398,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3425,7 +3421,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3449,7 +3445,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3473,7 +3469,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3497,7 +3493,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3521,7 +3517,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3545,7 +3541,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3569,7 +3565,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3593,7 +3589,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3617,7 +3613,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3641,7 +3637,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3665,7 +3661,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3689,7 +3685,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3709,7 +3705,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3729,7 +3725,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3756,7 +3752,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3783,7 +3779,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3810,7 +3806,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3833,7 +3829,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3860,7 +3856,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3883,7 +3879,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3906,7 +3902,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -4583,6 +4579,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
|
||||
-12783
File diff suppressed because it is too large
Load Diff
-89
@@ -1,89 +0,0 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:20:13 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_stub.v
|
||||
// Design : design_1_auto_pc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_28_axi_protocol_converter,Vivado 2023.1" *)
|
||||
module design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
|
||||
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
|
||||
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
|
||||
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
|
||||
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
|
||||
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
|
||||
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
|
||||
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input [11:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [11:0]s_axi_wid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [11:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [11:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [11:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [2:0]m_axi_awprot;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [31:0]m_axi_wdata;
|
||||
output [3:0]m_axi_wstrb;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [2:0]m_axi_arprot;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [31:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+79
-82
@@ -1509,10 +1509,6 @@
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Dec 01 17:20:15 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:83e014ba</spirit:value>
|
||||
@@ -1746,7 +1742,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1762,7 +1758,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1782,7 +1778,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1809,7 +1805,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1836,7 +1832,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1863,7 +1859,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1890,7 +1886,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1917,7 +1913,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1944,7 +1940,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1971,7 +1967,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1998,7 +1994,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2025,7 +2021,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2048,7 +2044,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2071,7 +2067,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2095,7 +2091,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2122,7 +2118,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2145,7 +2141,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2168,7 +2164,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2191,7 +2187,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2215,7 +2211,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2239,7 +2235,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2259,7 +2255,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2279,7 +2275,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2306,7 +2302,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2333,7 +2329,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2360,7 +2356,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2387,7 +2383,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2414,7 +2410,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2441,7 +2437,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2468,7 +2464,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2495,7 +2491,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2522,7 +2518,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2549,7 +2545,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2572,7 +2568,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2595,7 +2591,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2619,7 +2615,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2643,7 +2639,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2667,7 +2663,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2687,7 +2683,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2707,7 +2703,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2727,7 +2723,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2750,7 +2746,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2773,7 +2769,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2800,7 +2796,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2824,7 +2820,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2848,7 +2844,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2872,7 +2868,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2896,7 +2892,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2920,7 +2916,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2944,7 +2940,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2968,7 +2964,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2992,7 +2988,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3012,7 +3008,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3032,7 +3028,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3059,7 +3055,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3083,7 +3079,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3103,7 +3099,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3123,7 +3119,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3143,7 +3139,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3170,7 +3166,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3193,7 +3189,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3216,7 +3212,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3240,7 +3236,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3264,7 +3260,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3288,7 +3284,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3312,7 +3308,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3336,7 +3332,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3360,7 +3356,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3384,7 +3380,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3408,7 +3404,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3432,7 +3428,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3452,7 +3448,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3472,7 +3468,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3499,7 +3495,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3526,7 +3522,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3549,7 +3545,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3572,7 +3568,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3595,7 +3591,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -4420,6 +4416,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
|
||||
-11670
File diff suppressed because it is too large
Load Diff
-105
@@ -1,105 +0,0 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:20:15 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_auto_us_0/design_1_auto_us_0_stub.v
|
||||
// Design : design_1_auto_us_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_28_top,Vivado 2023.1" *)
|
||||
module design_1_auto_us_0(s_axi_aclk, s_axi_aresetn, s_axi_awid,
|
||||
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
|
||||
s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
|
||||
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
|
||||
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
|
||||
s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen,
|
||||
m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
|
||||
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
|
||||
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arlen,
|
||||
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
|
||||
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
|
||||
m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awid[0:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[0:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awlen[3:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[1:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [0:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [0:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [0:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [0:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [3:0]m_axi_awlen;
|
||||
output [2:0]m_axi_awsize;
|
||||
output [1:0]m_axi_awburst;
|
||||
output [1:0]m_axi_awlock;
|
||||
output [3:0]m_axi_awcache;
|
||||
output [2:0]m_axi_awprot;
|
||||
output [3:0]m_axi_awqos;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [63:0]m_axi_wdata;
|
||||
output [7:0]m_axi_wstrb;
|
||||
output m_axi_wlast;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [3:0]m_axi_arlen;
|
||||
output [2:0]m_axi_arsize;
|
||||
output [1:0]m_axi_arburst;
|
||||
output [1:0]m_axi_arlock;
|
||||
output [3:0]m_axi_arcache;
|
||||
output [2:0]m_axi_arprot;
|
||||
output [3:0]m_axi_arqos;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [63:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rlast;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+1
-1
@@ -2115,7 +2115,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Dec 01 17:20:12 UTC 2024</spirit:value>
|
||||
<spirit:value>Mon Dec 09 14:18:31 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+3
-3
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:20:11 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Date : Mon Dec 9 15:18:29 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_axi_2d_mmvs_0_0/design_1_axi_2d_mmvs_0_0_sim_netlist.v
|
||||
// c:/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_axi_2d_mmvs_0_0/design_1_axi_2d_mmvs_0_0_sim_netlist.v
|
||||
// Design : design_1_axi_2d_mmvs_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
|
||||
+3
-3
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:20:11 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Date : Mon Dec 9 15:18:29 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_axi_2d_mmvs_0_0/design_1_axi_2d_mmvs_0_0_stub.v
|
||||
// c:/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_axi_2d_mmvs_0_0/design_1_axi_2d_mmvs_0_0_stub.v
|
||||
// Design : design_1_axi_2d_mmvs_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
|
||||
+5
-19
@@ -9107,7 +9107,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK0_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">100000000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK0_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">1e+08</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
@@ -9199,7 +9199,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK1.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK1_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">125000000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK1.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK1_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">1.25e+08</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
@@ -9291,7 +9291,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK2.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK2_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">200000000</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK2.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK2_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">2e+08</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
@@ -9383,7 +9383,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK3.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK3_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">66666672</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK3.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK3_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">6.66667e+07</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
@@ -15301,7 +15301,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Dec 01 17:19:53 UTC 2024</spirit:value>
|
||||
<spirit:value>Mon Dec 09 14:17:13 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -37741,13 +37741,6 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>PCW_ENET0_RESET_IO</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6104"><Select></spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET0_RESET_IO">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PCW_ENET1_PERIPHERAL_ENABLE</spirit:name>
|
||||
@@ -38539,13 +38532,6 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>PCW_I2C0_RESET_IO</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C0_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6904"><Select></spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C0_RESET_IO">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PCW_I2C1_PERIPHERAL_ENABLE</spirit:name>
|
||||
|
||||
+5
-5
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:52 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Date : Mon Dec 9 15:17:11 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v
|
||||
// c:/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v
|
||||
// Design : design_1_processing_system7_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
@@ -175,7 +175,7 @@ module design_1_processing_system7_0_0
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]M_AXI_GP0_RDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD
\\nS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]M_AXI_GP0_RDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARREADY" *) output S_AXI_ACP_ARREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWREADY" *) output S_AXI_ACP_AWREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP BVALID" *) output S_AXI_ACP_BVALID;
|
||||
@@ -216,7 +216,7 @@ module design_1_processing_system7_0_0
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARUSER" *) input [4:0]S_AXI_ACP_ARUSER;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWUSER" *) input [4:0]S_AXI_ACP_AWUSER;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WDATA" *) input [63:0]S_AXI_ACP_WDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WSTRB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 5, ARUSER_WIDTH 5, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [7:0]S_AXI_ACP_WSTRB;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WSTRB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 5, ARUSER_WIDTH 5, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS
\\n 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [7:0]S_AXI_ACP_WSTRB;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) input [0:0]IRQ_F2P;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *) output FCLK_CLK1;
|
||||
|
||||
+3
-3
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:52 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Date : Mon Dec 9 15:17:11 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v
|
||||
// c:/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v
|
||||
// Design : design_1_processing_system7_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
|
||||
+1
-1
@@ -398,7 +398,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Dec 01 17:19:53 UTC 2024</spirit:value>
|
||||
<spirit:value>Mon Dec 09 14:19:40 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+3
-3
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:53 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Date : Mon Dec 9 15:19:39 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_sim_netlist.v
|
||||
// c:/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_sim_netlist.v
|
||||
// Design : design_1_rst_ps7_0_100M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
|
||||
+3
-3
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:53 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Date : Mon Dec 9 15:19:39 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_stub.v
|
||||
// c:/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_stub.v
|
||||
// Design : design_1_rst_ps7_0_100M_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
|
||||
+1
-1
@@ -540,7 +540,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Dec 01 17:19:55 UTC 2024</spirit:value>
|
||||
<spirit:value>Mon Dec 09 14:17:17 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+3
-3
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:55 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Date : Mon Dec 9 15:17:17 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_sim_netlist.v
|
||||
// c:/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_sim_netlist.v
|
||||
// Design : design_1_zybo_audio_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
|
||||
+3
-3
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:55 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Date : Mon Dec 9 15:17:17 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.v
|
||||
// c:/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.v
|
||||
// Design : design_1_zybo_audio_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
|
||||
+1
-1
@@ -289,7 +289,7 @@
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
|
||||
+1
-1
@@ -315,7 +315,7 @@
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
|
||||
+6
-6
@@ -479,7 +479,7 @@
|
||||
"PCW_ENET_RESET_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET_RESET_SELECT": [ { "value": "Share reset pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET0_RESET_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_ENET0_RESET_IO": [ { "value": "<Select>", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET1_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET1_ENET1_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_ENET1_GRP_MDIO_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
@@ -570,7 +570,7 @@
|
||||
"PCW_I2C0_GRP_INT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C0_GRP_INT_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_I2C0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C0_RESET_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_I2C0_RESET_IO": [ { "value": "<Select>", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C1_PERIPHERAL_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C1_I2C1_IO": [ { "value": "MIO 12 .. 13", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C1_GRP_INT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -1324,7 +1324,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -1342,7 +1342,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "125000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1.25e+08", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -1360,7 +1360,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "2e+08", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK2", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -1378,7 +1378,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "66666672", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "6.66667e+07", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK3", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.xpr">
|
||||
<Project Product="Vivado" Version="7" Minor="63" Path="C:/es-praktikum/Milestone5/es-milestone5/es-milestone5.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="8020d0b56f4e4e82833d6ff81c448789"/>
|
||||
@@ -44,7 +44,7 @@
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.2"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
@@ -98,24 +98,24 @@
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="design_1_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_auto_us_0/design_1_auto_us_0.xci">
|
||||
<Proxy FileSetName="design_1_auto_us_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_2d_mmvs_0_0/design_1_axi_2d_mmvs_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axi_2d_mmvs_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xci">
|
||||
<Proxy FileSetName="design_1_zybo_audio_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0.xci">
|
||||
<Proxy FileSetName="design_1_rst_ps7_0_100M_0"/>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_auto_us_0/design_1_auto_us_0.xci">
|
||||
<Proxy FileSetName="design_1_auto_us_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="design_1_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_auto_pc_0/design_1_auto_pc_0.xci">
|
||||
<Proxy FileSetName="design_1_auto_pc_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0.xci">
|
||||
<Proxy FileSetName="design_1_rst_ps7_0_100M_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
|
||||
<FileInfo>
|
||||
@@ -222,9 +222,7 @@
|
||||
<Runs Version="1" Minor="20">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -234,9 +232,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_processing_system7_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -246,9 +242,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_auto_us_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_auto_us_0" Part="xc7z020clg400-1" ConstrsSet="design_1_auto_us_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_auto_us_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_auto_us_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_auto_us_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -258,9 +252,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_axi_2d_mmvs_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_2d_mmvs_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axi_2d_mmvs_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_2d_mmvs_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_2d_mmvs_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_2d_mmvs_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -270,9 +262,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_zybo_audio_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_zybo_audio_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_zybo_audio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_zybo_audio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -282,9 +272,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_rst_ps7_0_100M_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_rst_ps7_0_100M_0" Part="xc7z020clg400-1" ConstrsSet="design_1_rst_ps7_0_100M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_rst_ps7_0_100M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_100M_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_100M_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -294,9 +282,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_auto_pc_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_auto_pc_0" Part="xc7z020clg400-1" ConstrsSet="design_1_auto_pc_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_auto_pc_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_auto_pc_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_auto_pc_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -304,11 +290,9 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -321,16 +305,13 @@
|
||||
<Option Id="BinFile">1</Option>
|
||||
</Step>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -347,9 +328,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_auto_us_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_auto_us_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_auto_us_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_auto_us_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_auto_us_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -366,9 +345,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_axi_2d_mmvs_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axi_2d_mmvs_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_2d_mmvs_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_2d_mmvs_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_2d_mmvs_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -385,9 +362,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_zybo_audio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_zybo_audio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_zybo_audio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -404,9 +379,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_rst_ps7_0_100M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_rst_ps7_0_100M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_rst_ps7_0_100M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_100M_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_100M_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -423,9 +396,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_auto_pc_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_auto_pc_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_auto_pc_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_auto_pc_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_auto_pc_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -441,9 +412,7 @@
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
|
||||
@@ -16,10 +16,10 @@ entity axis_video_filter is
|
||||
|
||||
-- AXI Streaming Target Port (from linemem)
|
||||
S_AXIS_TVALID : in std_logic := '0';
|
||||
S_AXIS_TDATA : in std_logic_vector(23 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TDATA : in std_logic_vector(23 downto 0); --Blau, gruen, rot jeweils 8 Bit pro pixel
|
||||
S_AXIS_TLAST : in std_logic := '0'; --letztes Pixel
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TUSER : in std_logic_vector(2 downto 0);
|
||||
S_AXIS_TUSER : in std_logic_vector(2 downto 0); --ertes Pixel
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
|
||||
|
||||
@@ -0,0 +1,86 @@
|
||||
# Created by https://www.toptal.com/developers/gitignore/api/vivado
|
||||
# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
|
||||
|
||||
### Vivado ###
|
||||
#########################################################################################################
|
||||
## This is an example .gitignore file for Vivado, please treat it as an example as
|
||||
## it might not be complete. In addition, XAPP 1165 should be followed.
|
||||
#########
|
||||
#Exclude all
|
||||
*
|
||||
!*/
|
||||
!.gitignore
|
||||
###########################################################################
|
||||
## VIVADO
|
||||
#Source files:
|
||||
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
|
||||
!*.vhd
|
||||
!*.v
|
||||
!*.sv
|
||||
!*.bd
|
||||
!*.edif
|
||||
#IP files
|
||||
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
|
||||
#.xci + .dcp: implementation possible but not re-synthesis
|
||||
#*.xci(www.spiritconsortium.org)
|
||||
!*.xci
|
||||
#.xcix: Core container file
|
||||
#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
|
||||
!*.xcix
|
||||
#*.dcp(checkpoint files)
|
||||
!*.dcp
|
||||
!*.vds
|
||||
!*.pb
|
||||
#All bd comments and layout coordinates are stored within .ui
|
||||
!*.ui
|
||||
!*.ooc
|
||||
#System Generator
|
||||
!*.mdl
|
||||
!*.slx
|
||||
!*.bxml
|
||||
#Simulation logic analyzer
|
||||
!*.wcfg
|
||||
!*.coe
|
||||
#MIG
|
||||
!*.prj
|
||||
!*.mem
|
||||
#Project files
|
||||
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
|
||||
#Do NOT ignore *.xpr files
|
||||
!*.xpr
|
||||
#Include *.xml files for 2013.4 or earlier version
|
||||
!*.xml
|
||||
#Constraint files
|
||||
#Do NOT ignore *.xdc files
|
||||
!*.xdc
|
||||
#TCL - files
|
||||
!*.tcl
|
||||
#Journal - files
|
||||
!*.jou
|
||||
#Reports
|
||||
!*.rpt
|
||||
!*.txt
|
||||
!*.vdi
|
||||
#C-files
|
||||
!*.c
|
||||
!*.h
|
||||
!*.elf
|
||||
!*.bmm
|
||||
!*.xmp
|
||||
|
||||
# End of https://www.toptal.com/developers/gitignore/api/vivado
|
||||
|
||||
# Vidado project directories which are not needed
|
||||
.Xil/
|
||||
*.cache/
|
||||
*.hw/
|
||||
*.ip_user_files/
|
||||
*.runs/
|
||||
*.sim/
|
||||
# design checkpoint file
|
||||
*.dcp
|
||||
|
||||
# ignore Vivado log files
|
||||
*.log
|
||||
*.jou
|
||||
vivado_pid*.str
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
create_clock -period 16.666 -name video_clk [get_pins -regexp .*PS/FCLK_CLK3 -hierarchical]
|
||||
set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks video_clk]
|
||||
set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_fpga_3]
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks pllclk1x_pll]
|
||||
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
#Switches
|
||||
set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { SWITCH[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
|
||||
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { SWITCH[1] }]; #IO_L24P_T3_34 Sch=sw[1]
|
||||
set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { SWITCH[2] }]; #IO_L4N_T0_34 Sch=sw[2]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { SWITCH[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
|
||||
|
||||
|
||||
#Buttons
|
||||
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { BUTTON[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
|
||||
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { BUTTON[1] }]; #IO_L24N_T3_34 Sch=btn[1]
|
||||
set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { BUTTON[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
|
||||
set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { BUTTON[3] }]; #IO_L7P_T1_34 Sch=btn[3]
|
||||
|
||||
|
||||
#LEDs
|
||||
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L23P_T3_35 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L23N_T3_35 Sch=led[1]
|
||||
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_0_35 Sch=led[2]
|
||||
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
|
||||
|
||||
|
||||
#RGB LED 5 (Zybo Z7-20 only)
|
||||
set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[0] }]; #IO_L18N_T2_13 Sch=led5_r
|
||||
set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[1] }]; #IO_L19P_T3_13 Sch=led5_g
|
||||
set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[2] }]; #IO_L20P_T3_13 Sch=led5_b
|
||||
|
||||
#RGB LED 6
|
||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[3] }]; #IO_L18P_T2_34 Sch=led6_r
|
||||
set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[4] }]; #IO_L6N_T0_VREF_35 Sch=led6_g
|
||||
set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[5] }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
|
||||
|
||||
#HDMI TX
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { HDMI_CLK_N }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
|
||||
set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { HDMI_CLK_P }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
|
||||
set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { HDMI_DATA_N[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
|
||||
set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { HDMI_DATA_P[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
|
||||
set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { HDMI_DATA_N[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
|
||||
set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { HDMI_DATA_P[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
|
||||
set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { HDMI_DATA_N[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
|
||||
set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { HDMI_DATA_P[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
|
||||
@@ -0,0 +1,232 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="63" Path="C:/es-praktikum/Milestone6/milestone6/milestone6.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="8685839343394c1fb7ae4540054d577c"/>
|
||||
<Option Name="Part" Val="xc7z020clg400-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.1"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2022.3"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2022.3"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.1"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/basti/AppData/Roaming/Xilinx/Vivado/2023.1/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-20"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../axis_video_filter.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_video_filter"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/imports/Milestone6/Zybo-Z7-20_VideoOut-ImplementationOnly.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../Zybo-Z7-20_VideoOut-ImplementationOnly.xdc"/>
|
||||
<Attr Name="ImportTime" Val="1733753576"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/constrs_1/imports/Milestone6/Zybo-Z7-20_VideoOut.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../Zybo-Z7-20_VideoOut.xdc"/>
|
||||
<Attr Name="ImportTime" Val="1733753576"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_video_filter"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="20">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
Reference in New Issue
Block a user