From c1d3ff190fc319c5abbf37605a6dc846d0a06718 Mon Sep 17 00:00:00 2001 From: Matthias Biermann Date: Thu, 28 Nov 2024 13:30:01 +0100 Subject: [PATCH] M3: Praktikumstermin Abschluss --- .../sources_1/bd/af_sim/af_sim.bxml | 55 +---- .../sources_1/bd/af_sim/af_sim_ooc.xdc | 10 - .../af_sim_axis_prog_audio_filt_0_0.xml | 136 ++++-------- .../sources_1/bd/af_sim/sim/af_sim.vhd | 205 ------------------ .../sources_1/bd/af_sim/synth/af_sim.vhd | 205 ------------------ .../sources_1/bd/design_1/design_1.bxml | 8 +- .../bd/design_1/hdl/design_1_wrapper.vhd | 4 +- .../design_1_axil_master_with_rom_0_0.xml | 10 +- .../design_1_axis_audio_mono2ster_0_0.xml | 10 +- .../design_1_axis_audio_stereo2mo_0_0.xml | 10 +- .../design_1_axis_prog_audio_filt_0_1.xml | 76 ++++--- .../design_1_clk_rst_generator_0_0.xml | 10 +- .../design_1_system_ila_0_0/bd_0/bd_f60c.bd | 2 +- .../design_1_system_ila_0_0/bd_0/bd_f60c.bxml | 8 +- .../bd_0/ip/ip_0/bd_f60c_ila_lib_0.xci | 4 +- .../bd_0/ip/ip_0/bd_f60c_ila_lib_0.xml | 22 +- .../bd_0/ip/ip_1/bd_f60c_g_inst_0.xml | 8 +- .../bd_0/ip/ip_2/bd_f60c_slot_0_aw_0.xml | 8 +- .../bd_0/ip/ip_3/bd_f60c_slot_0_w_0.xml | 8 +- .../bd_0/ip/ip_4/bd_f60c_slot_0_b_0.xml | 8 +- .../bd_0/ip/ip_5/bd_f60c_slot_0_ar_0.xml | 8 +- .../bd_0/ip/ip_6/bd_f60c_slot_0_r_0.xml | 8 +- .../design_1_system_ila_0_0.xml | 89 ++++++-- .../design_1_zybo_audio_0_0.xml | 10 +- .../sources_1/bd/design_1/sim/design_1.vhd | 4 +- .../sources_1/bd/design_1/synth/design_1.vhd | 4 +- .../axis_prog_audio_filter3/component.xml | 6 +- .../sources_1/bd/af_sim/af_sim.bd | 3 +- .../af_sim_axis_prog_audio_filt_0_0.xci | 38 ++-- .../sources_1/bd/af_sim/ui/bd_279d689d.ui | 12 +- .../sources_1/bd/design_1/design_1.bd | 16 +- .../design_1_axis_prog_audio_filt_0_1.xci | 54 ++--- .../design_1_system_ila_0_0.xci | 108 ++++----- .../sources_1/bd/design_1/ui/bd_1f5defd0.ui | 14 +- Milestone3/es-milestone3/es-milestone3.xpr | 90 ++++---- Milestone3/sources/axis_audio_filter3.vhd | 2 +- 36 files changed, 417 insertions(+), 856 deletions(-) delete mode 100644 Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim_ooc.xdc delete mode 100644 Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/sim/af_sim.vhd delete mode 100644 Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/synth/af_sim.vhd diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim.bxml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim.bxml index 0aab29f..74e6626 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim.bxml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim.bxml @@ -2,55 +2,10 @@ Composite Fileset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim_ooc.xdc b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim_ooc.xdc deleted file mode 100644 index 7fac2b2..0000000 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim_ooc.xdc +++ /dev/null @@ -1,10 +0,0 @@ -################################################################################ - -# This XDC is used only for OOC mode of synthesis, implementation -# This constraints file contains default clock frequencies to be used during -# out-of-context flows such as OOC Synthesis and Hierarchical Designs. -# This constraints file is not used in normal top-down synthesis (default flow -# of Vivado) -################################################################################ - -################################################################################ \ No newline at end of file diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xml index eb215a8..c7bf94f 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xml @@ -882,40 +882,6 @@ - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - axis_prog_audio_filter3 - - - outputProductCRC - 9:08ca8409 - - - - - xilinx_vhdlsimulationwrapper - VHDL Simulation Wrapper - vhdlSource:vivado.xilinx.com:simulation.wrapper - vhdl - af_sim_axis_prog_audio_filt_0_0 - - xilinx_vhdlsimulationwrapper_view_fileset - - - - GENtimestamp - Tue Nov 26 14:22:42 UTC 2024 - - - outputProductCRC - 9:08ca8409 - - - - AXI_ACLK @@ -924,7 +890,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -936,7 +902,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -952,7 +918,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -967,7 +933,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -982,7 +948,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -998,7 +964,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1013,7 +979,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1028,7 +994,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1044,7 +1010,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1059,7 +1025,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1071,7 +1037,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1090,7 +1056,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1106,7 +1072,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1121,7 +1087,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1136,7 +1102,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1152,7 +1118,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1164,7 +1130,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1176,7 +1142,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1195,7 +1161,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1207,7 +1173,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1223,7 +1189,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1238,7 +1204,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1253,7 +1219,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1265,7 +1231,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1281,7 +1247,7 @@ std_logic_vector - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1293,7 +1259,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1305,7 +1271,7 @@ std_logic - xilinx_anylanguagebehavioralsimulation + dummy_view @@ -1354,16 +1320,6 @@ ACTIVE_LOW - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/af_sim_axis_prog_audio_filt_0_0.vhd - vhdlSource - xil_defaultlib - - - xilinx.com:module_ref:axis_prog_audio_filter3:1.0 @@ -1427,36 +1383,36 @@ - - - - + + + + - + - - - - - - - - - - + + + + + + + + + + - - + + - + - + diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/sim/af_sim.vhd b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/sim/af_sim.vhd deleted file mode 100644 index e824915..0000000 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/sim/af_sim.vhd +++ /dev/null @@ -1,205 +0,0 @@ ---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- ---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Tue Nov 26 15:22:42 2024 ---Host : BiermannSurface running 64-bit major release (build 9200) ---Command : generate_target af_sim.bd ---Design : af_sim ---Purpose : IP block netlist ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity af_sim is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of af_sim : entity is "af_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=af_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; - attribute HW_HANDOFF : string; - attribute HW_HANDOFF of af_sim : entity is "af_sim.hwdef"; -end af_sim; - -architecture STRUCTURE of af_sim is - component af_sim_clk_rst_generator_0_0 is - port ( - clk : out STD_LOGIC; - rst_n : out STD_LOGIC; - stop_simulation : in STD_LOGIC - ); - end component af_sim_clk_rst_generator_0_0; - component af_sim_axis_audio_master_si_0_0 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TREADY : in STD_LOGIC; - WAV_HEADER : out STD_LOGIC_VECTOR ( 351 downto 0 ) - ); - end component af_sim_axis_audio_master_si_0_0; - component af_sim_axis_audio_mono2ster_0_0 is - port ( - AXIS_ACLK : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); - S_AXIS_TREADY : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TREADY : in STD_LOGIC - ); - end component af_sim_axis_audio_mono2ster_0_0; - component af_sim_axis_audio_stereo2mo_0_0 is - port ( - AXIS_ACLK : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TREADY : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); - M_AXIS_TREADY : in STD_LOGIC - ); - end component af_sim_axis_audio_stereo2mo_0_0; - component af_sim_axis_audio_slave_sim_0_0 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TREADY : out STD_LOGIC; - FINISHED : out STD_LOGIC; - WAV_HEADER : in STD_LOGIC_VECTOR ( 351 downto 0 ) - ); - end component af_sim_axis_audio_slave_sim_0_0; - component af_sim_axis_prog_audio_filt_0_0 is - port ( - AXI_ACLK : in STD_LOGIC; - AXI_ARESETN : in STD_LOGIC; - S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); - S_AXIL_AWVALID : in STD_LOGIC; - S_AXIL_AWREADY : out STD_LOGIC; - S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIL_WVALID : in STD_LOGIC; - S_AXIL_WREADY : out STD_LOGIC; - S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); - S_AXIL_BVALID : out STD_LOGIC; - S_AXIL_BREADY : in STD_LOGIC; - S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); - S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); - S_AXIL_ARVALID : in STD_LOGIC; - S_AXIL_ARREADY : out STD_LOGIC; - S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIL_RVALID : out STD_LOGIC; - S_AXIL_RREADY : in STD_LOGIC; - S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC - ); - end component af_sim_axis_prog_audio_filt_0_0; - signal axis_audio_master_si_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_audio_master_si_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_audio_master_si_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_audio_master_si_0_WAV_HEADER : STD_LOGIC_VECTOR ( 351 downto 0 ); - signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_audio_slave_sim_0_FINISHED : STD_LOGIC; - signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC; - signal clk_rst_generator_0_clk : STD_LOGIC; - signal clk_rst_generator_0_rst_n : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); -begin -axis_audio_master_si_0: component af_sim_axis_audio_master_si_0_0 - port map ( - ACLK => clk_rst_generator_0_clk, - ARESETN => clk_rst_generator_0_rst_n, - M_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID, - WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0) - ); -axis_audio_mono2ster_0: component af_sim_axis_audio_mono2ster_0_0 - port map ( - AXIS_ACLK => clk_rst_generator_0_clk, - M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID, - S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0), - S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID - ); -axis_audio_slave_sim_0: component af_sim_axis_audio_slave_sim_0_0 - port map ( - ACLK => clk_rst_generator_0_clk, - ARESETN => clk_rst_generator_0_rst_n, - FINISHED => axis_audio_slave_sim_0_FINISHED, - S_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID, - WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0) - ); -axis_audio_stereo2mo_0: component af_sim_axis_audio_stereo2mo_0_0 - port map ( - AXIS_ACLK => clk_rst_generator_0_clk, - M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0), - M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID, - S_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID - ); -axis_prog_audio_filt_0: component af_sim_axis_prog_audio_filt_0_0 - port map ( - AXI_ACLK => clk_rst_generator_0_clk, - AXI_ARESETN => clk_rst_generator_0_rst_n, - M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0), - M_AXIS_TLAST => NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED, - M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID, - S_AXIL_ARADDR(7 downto 0) => B"00000000", - S_AXIL_ARREADY => NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED, - S_AXIL_ARVALID => '0', - S_AXIL_AWADDR(7 downto 0) => B"00000000", - S_AXIL_AWREADY => NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED, - S_AXIL_AWVALID => '0', - S_AXIL_BREADY => '0', - S_AXIL_BRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED(1 downto 0), - S_AXIL_BVALID => NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED, - S_AXIL_RDATA(31 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED(31 downto 0), - S_AXIL_RREADY => '0', - S_AXIL_RRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED(1 downto 0), - S_AXIL_RVALID => NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED, - S_AXIL_WDATA(31 downto 0) => B"00000000000000000000000000000000", - S_AXIL_WREADY => NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED, - S_AXIL_WSTRB(3 downto 0) => B"1111", - S_AXIL_WVALID => '0', - S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0), - S_AXIS_TLAST => '0', - S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID - ); -clk_rst_generator_0: component af_sim_clk_rst_generator_0_0 - port map ( - clk => clk_rst_generator_0_clk, - rst_n => clk_rst_generator_0_rst_n, - stop_simulation => axis_audio_slave_sim_0_FINISHED - ); -end STRUCTURE; diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/synth/af_sim.vhd b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/synth/af_sim.vhd deleted file mode 100644 index e824915..0000000 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/synth/af_sim.vhd +++ /dev/null @@ -1,205 +0,0 @@ ---Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- ---Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Tue Nov 26 15:22:42 2024 ---Host : BiermannSurface running 64-bit major release (build 9200) ---Command : generate_target af_sim.bd ---Design : af_sim ---Purpose : IP block netlist ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity af_sim is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of af_sim : entity is "af_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=af_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; - attribute HW_HANDOFF : string; - attribute HW_HANDOFF of af_sim : entity is "af_sim.hwdef"; -end af_sim; - -architecture STRUCTURE of af_sim is - component af_sim_clk_rst_generator_0_0 is - port ( - clk : out STD_LOGIC; - rst_n : out STD_LOGIC; - stop_simulation : in STD_LOGIC - ); - end component af_sim_clk_rst_generator_0_0; - component af_sim_axis_audio_master_si_0_0 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TREADY : in STD_LOGIC; - WAV_HEADER : out STD_LOGIC_VECTOR ( 351 downto 0 ) - ); - end component af_sim_axis_audio_master_si_0_0; - component af_sim_axis_audio_mono2ster_0_0 is - port ( - AXIS_ACLK : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); - S_AXIS_TREADY : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - M_AXIS_TREADY : in STD_LOGIC - ); - end component af_sim_axis_audio_mono2ster_0_0; - component af_sim_axis_audio_stereo2mo_0_0 is - port ( - AXIS_ACLK : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TREADY : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); - M_AXIS_TREADY : in STD_LOGIC - ); - end component af_sim_axis_audio_stereo2mo_0_0; - component af_sim_axis_audio_slave_sim_0_0 is - port ( - ACLK : in STD_LOGIC; - ARESETN : in STD_LOGIC; - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIS_TREADY : out STD_LOGIC; - FINISHED : out STD_LOGIC; - WAV_HEADER : in STD_LOGIC_VECTOR ( 351 downto 0 ) - ); - end component af_sim_axis_audio_slave_sim_0_0; - component af_sim_axis_prog_audio_filt_0_0 is - port ( - AXI_ACLK : in STD_LOGIC; - AXI_ARESETN : in STD_LOGIC; - S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); - S_AXIL_AWVALID : in STD_LOGIC; - S_AXIL_AWREADY : out STD_LOGIC; - S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIL_WVALID : in STD_LOGIC; - S_AXIL_WREADY : out STD_LOGIC; - S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); - S_AXIL_BVALID : out STD_LOGIC; - S_AXIL_BREADY : in STD_LOGIC; - S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); - S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); - S_AXIL_ARVALID : in STD_LOGIC; - S_AXIL_ARREADY : out STD_LOGIC; - S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); - S_AXIL_RVALID : out STD_LOGIC; - S_AXIL_RREADY : in STD_LOGIC; - S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); - S_AXIS_TVALID : in STD_LOGIC; - S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); - S_AXIS_TLAST : in STD_LOGIC; - S_AXIS_TREADY : out STD_LOGIC; - M_AXIS_TVALID : out STD_LOGIC; - M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); - M_AXIS_TLAST : out STD_LOGIC; - M_AXIS_TREADY : in STD_LOGIC - ); - end component af_sim_axis_prog_audio_filt_0_0; - signal axis_audio_master_si_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_audio_master_si_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_audio_master_si_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_audio_master_si_0_WAV_HEADER : STD_LOGIC_VECTOR ( 351 downto 0 ); - signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_audio_slave_sim_0_FINISHED : STD_LOGIC; - signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC; - signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC; - signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC; - signal clk_rst_generator_0_clk : STD_LOGIC; - signal clk_rst_generator_0_rst_n : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED : STD_LOGIC; - signal NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); -begin -axis_audio_master_si_0: component af_sim_axis_audio_master_si_0_0 - port map ( - ACLK => clk_rst_generator_0_clk, - ARESETN => clk_rst_generator_0_rst_n, - M_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID, - WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0) - ); -axis_audio_mono2ster_0: component af_sim_axis_audio_mono2ster_0_0 - port map ( - AXIS_ACLK => clk_rst_generator_0_clk, - M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0), - M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID, - S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0), - S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID - ); -axis_audio_slave_sim_0: component af_sim_axis_audio_slave_sim_0_0 - port map ( - ACLK => clk_rst_generator_0_clk, - ARESETN => clk_rst_generator_0_rst_n, - FINISHED => axis_audio_slave_sim_0_FINISHED, - S_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID, - WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0) - ); -axis_audio_stereo2mo_0: component af_sim_axis_audio_stereo2mo_0_0 - port map ( - AXIS_ACLK => clk_rst_generator_0_clk, - M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0), - M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID, - S_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0), - S_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID - ); -axis_prog_audio_filt_0: component af_sim_axis_prog_audio_filt_0_0 - port map ( - AXI_ACLK => clk_rst_generator_0_clk, - AXI_ARESETN => clk_rst_generator_0_rst_n, - M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0), - M_AXIS_TLAST => NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED, - M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY, - M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID, - S_AXIL_ARADDR(7 downto 0) => B"00000000", - S_AXIL_ARREADY => NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED, - S_AXIL_ARVALID => '0', - S_AXIL_AWADDR(7 downto 0) => B"00000000", - S_AXIL_AWREADY => NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED, - S_AXIL_AWVALID => '0', - S_AXIL_BREADY => '0', - S_AXIL_BRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED(1 downto 0), - S_AXIL_BVALID => NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED, - S_AXIL_RDATA(31 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED(31 downto 0), - S_AXIL_RREADY => '0', - S_AXIL_RRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED(1 downto 0), - S_AXIL_RVALID => NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED, - S_AXIL_WDATA(31 downto 0) => B"00000000000000000000000000000000", - S_AXIL_WREADY => NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED, - S_AXIL_WSTRB(3 downto 0) => B"1111", - S_AXIL_WVALID => '0', - S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0), - S_AXIS_TLAST => '0', - S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY, - S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID - ); -clk_rst_generator_0: component af_sim_clk_rst_generator_0_0 - port map ( - clk => clk_rst_generator_0_clk, - rst_n => clk_rst_generator_0_rst_n, - stop_simulation => axis_audio_slave_sim_0_FINISHED - ); -end STRUCTURE; diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/design_1.bxml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/design_1.bxml index 3f85fe1..8beebad 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/design_1.bxml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/design_1.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd index df2c19e..51c1f28 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd @@ -2,8 +2,8 @@ --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Tue Nov 26 15:15:29 2024 ---Host : BiermannSurface running 64-bit major release (build 9200) +--Date : Wed Nov 27 17:33:33 2024 +--Host : sb0217-172 running 64-bit major release (build 9200) --Command : generate_target design_1_wrapper.bd --Design : design_1_wrapper --Purpose : IP block netlist diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml index ee9a40e..ab1def4 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml @@ -577,7 +577,7 @@ GENtimestamp - Tue Nov 26 14:15:30 UTC 2024 + Wed Nov 27 15:51:55 UTC 2024 outputProductCRC @@ -596,7 +596,7 @@ GENtimestamp - Tue Nov 26 14:15:30 UTC 2024 + Wed Nov 27 15:51:55 UTC 2024 outputProductCRC @@ -614,7 +614,7 @@ GENtimestamp - Tue Nov 26 14:25:48 UTC 2024 + Wed Nov 27 15:53:20 UTC 2024 outputProductCRC @@ -645,7 +645,7 @@ GENtimestamp - Tue Nov 26 14:15:30 UTC 2024 + Wed Nov 27 15:51:55 UTC 2024 outputProductCRC @@ -665,7 +665,7 @@ GENtimestamp - Tue Nov 26 14:15:30 UTC 2024 + Wed Nov 27 15:51:55 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xml index 9124906..2260b6a 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xml @@ -422,7 +422,7 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 15:52:05 UTC 2024 outputProductCRC @@ -441,7 +441,7 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 15:52:05 UTC 2024 outputProductCRC @@ -459,7 +459,7 @@ GENtimestamp - Tue Nov 26 14:25:44 UTC 2024 + Wed Nov 27 15:53:16 UTC 2024 outputProductCRC @@ -490,7 +490,7 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 15:52:05 UTC 2024 outputProductCRC @@ -510,7 +510,7 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 15:52:05 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xml index 0ecbfbd..a6423e7 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xml @@ -422,7 +422,7 @@ GENtimestamp - Tue Nov 26 14:15:29 UTC 2024 + Wed Nov 27 15:51:55 UTC 2024 outputProductCRC @@ -441,7 +441,7 @@ GENtimestamp - Tue Nov 26 14:15:29 UTC 2024 + Wed Nov 27 15:51:55 UTC 2024 outputProductCRC @@ -459,7 +459,7 @@ GENtimestamp - Tue Nov 26 14:25:44 UTC 2024 + Wed Nov 27 15:53:16 UTC 2024 outputProductCRC @@ -490,7 +490,7 @@ GENtimestamp - Tue Nov 26 14:15:29 UTC 2024 + Wed Nov 27 15:51:55 UTC 2024 outputProductCRC @@ -510,7 +510,7 @@ GENtimestamp - Tue Nov 26 14:15:29 UTC 2024 + Wed Nov 27 15:51:55 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xml index bae3724..077991d 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xml @@ -891,7 +891,7 @@ outputProductCRC - 9:15e36279 + 9:d16ada26 @@ -903,7 +903,7 @@ outputProductCRC - 9:d2381e3b + 9:1bcb63e3 @@ -917,11 +917,11 @@ GENtimestamp - Tue Nov 26 14:25:50 UTC 2024 + Wed Nov 27 16:34:48 UTC 2024 outputProductCRC - 9:d2381e3b + 9:1bcb63e3 @@ -932,7 +932,7 @@ outputProductCRC - 9:d2381e3b + 9:1bcb63e3 @@ -948,11 +948,11 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 16:33:45 UTC 2024 outputProductCRC - 9:15e36279 + 9:d16ada26 @@ -968,11 +968,11 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 16:33:45 UTC 2024 outputProductCRC - 9:d2381e3b + 9:1bcb63e3 @@ -1406,22 +1406,22 @@ COEFF_0 Coeff 0 - 42 + 16 COEFF_1 Coeff 1 - 42 + 32 COEFF_2 Coeff 2 - 42 + 16 SHIFT Shift - 7 + 6 RUN_AFTER_RESET @@ -1501,22 +1501,22 @@ COEFF_0 Coeff 0 - 42 + 16 COEFF_1 Coeff 1 - 42 + 32 COEFF_2 Coeff 2 - 42 + 16 SHIFT Shift - 7 + 6 RUN_AFTER_RESET @@ -1559,36 +1559,36 @@ - - - - + + + + - + - - - - - - - - - - + + + + + + + + + + - - + + - + - + @@ -1601,6 +1601,10 @@ + + + + diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml index d38321a..c1b9d9f 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml @@ -17,7 +17,7 @@ GENtimestamp - Tue Nov 26 14:15:29 UTC 2024 + Wed Nov 27 15:51:54 UTC 2024 outputProductCRC @@ -36,7 +36,7 @@ GENtimestamp - Tue Nov 26 14:15:29 UTC 2024 + Wed Nov 27 15:51:54 UTC 2024 outputProductCRC @@ -54,7 +54,7 @@ GENtimestamp - Tue Nov 26 14:25:44 UTC 2024 + Wed Nov 27 15:53:17 UTC 2024 outputProductCRC @@ -85,7 +85,7 @@ GENtimestamp - Tue Nov 26 14:15:29 UTC 2024 + Wed Nov 27 15:51:54 UTC 2024 outputProductCRC @@ -105,7 +105,7 @@ GENtimestamp - Tue Nov 26 14:15:29 UTC 2024 + Wed Nov 27 15:51:54 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bd b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bd index ba127d4..3896f66 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bd +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bd @@ -336,7 +336,7 @@ "value": "FALSE" }, "C_DATA_DEPTH": { - "value": "16384" + "value": "8192" }, "C_EN_STRG_QUAL": { "value": "0" diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bxml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bxml index 4169131..eac10c9 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bxml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xci b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xci index 4badd26..5bef155 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xci +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xci @@ -2055,7 +2055,7 @@ "C_PROBE2_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_PROBE1_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_PROBE0_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "C_DATA_DEPTH": [ { "value": "16384", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_DATA_DEPTH": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_NUM_OF_PROBES": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Component_Name": [ { "value": "bd_f60c_ila_lib_0", "resolve_type": "user", "usage": "all" } ], @@ -3136,7 +3136,7 @@ "C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ENABLE_ILA_AXI_MON": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_NUM_OF_PROBES": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_DATA_DEPTH": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DATA_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MAJOR_VERSION": [ { "value": "2023", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MINOR_VERSION": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_BUILD_REVISION": [ { "value": "0", "format": "long", "usage": "all" } ], diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xml index 053b2ed..eb13f77 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xml @@ -1046,11 +1046,11 @@ GENtimestamp - Tue Nov 26 14:15:31 UTC 2024 + Wed Nov 27 16:33:39 UTC 2024 outputProductCRC - 9:1964941d + 9:0a92643b @@ -1065,11 +1065,11 @@ GENtimestamp - Tue Nov 26 14:15:31 UTC 2024 + Wed Nov 27 16:33:39 UTC 2024 outputProductCRC - 9:1964941d + 9:0a92643b @@ -1080,7 +1080,7 @@ outputProductCRC - 9:1964941d + 9:0a92643b @@ -1096,11 +1096,11 @@ GENtimestamp - Tue Nov 26 14:15:31 UTC 2024 + Wed Nov 27 16:33:39 UTC 2024 outputProductCRC - 9:6cb62d17 + 9:cdd9092f @@ -1116,11 +1116,11 @@ GENtimestamp - Tue Nov 26 14:15:31 UTC 2024 + Wed Nov 27 16:33:39 UTC 2024 outputProductCRC - 9:1964941d + 9:0a92643b @@ -28998,7 +28998,7 @@ C_DATA_DEPTH Sample Data Depth - 16384 + 8192 C_MAJOR_VERSION @@ -69461,7 +69461,7 @@ C_DATA_DEPTH Sample Data Depth - 16384 + 8192 diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/bd_f60c_g_inst_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/bd_f60c_g_inst_0.xml index da23f96..6976985 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/bd_f60c_g_inst_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/bd_f60c_g_inst_0.xml @@ -31172,7 +31172,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:41 UTC 2024 outputProductCRC @@ -31192,7 +31192,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:41 UTC 2024 outputProductCRC @@ -31212,7 +31212,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:41 UTC 2024 outputProductCRC @@ -31232,7 +31232,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:41 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/bd_f60c_slot_0_aw_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/bd_f60c_slot_0_aw_0.xml index 5af594f..d71dff1 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/bd_f60c_slot_0_aw_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/bd_f60c_slot_0_aw_0.xml @@ -29,7 +29,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -49,7 +49,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -69,7 +69,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -89,7 +89,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/bd_f60c_slot_0_w_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/bd_f60c_slot_0_w_0.xml index dbea34e..53649c6 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/bd_f60c_slot_0_w_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/bd_f60c_slot_0_w_0.xml @@ -29,7 +29,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -49,7 +49,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -69,7 +69,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -89,7 +89,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/bd_f60c_slot_0_b_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/bd_f60c_slot_0_b_0.xml index 70b21b3..b233fc4 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/bd_f60c_slot_0_b_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/bd_f60c_slot_0_b_0.xml @@ -29,7 +29,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -49,7 +49,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -69,7 +69,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -89,7 +89,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/bd_f60c_slot_0_ar_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/bd_f60c_slot_0_ar_0.xml index 1128a2d..6698a71 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/bd_f60c_slot_0_ar_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/bd_f60c_slot_0_ar_0.xml @@ -29,7 +29,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -49,7 +49,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -69,7 +69,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -89,7 +89,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/bd_f60c_slot_0_r_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/bd_f60c_slot_0_r_0.xml index 50e20c2..6c99380 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/bd_f60c_slot_0_r_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/bd_f60c_slot_0_r_0.xml @@ -29,7 +29,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -49,7 +49,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:44 UTC 2024 outputProductCRC @@ -69,7 +69,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:43 UTC 2024 outputProductCRC @@ -89,7 +89,7 @@ GENtimestamp - Tue Nov 26 14:15:33 UTC 2024 + Wed Nov 27 16:33:44 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xml index 0a6f7cf..9217ef6 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xml @@ -904,11 +904,11 @@ GENtimestamp - Tue Nov 26 14:15:30 UTC 2024 + Wed Nov 27 16:33:36 UTC 2024 outputProductCRC - 9:5a9d8cb3 + 9:f75ccf4d @@ -922,11 +922,11 @@ GENtimestamp - Tue Nov 26 14:01:38 UTC 2024 + Wed Nov 27 16:33:22 UTC 2024 outputProductCRC - 9:18b60821 + 9:2d6fafa7 @@ -940,11 +940,11 @@ GENtimestamp - Tue Nov 26 14:01:38 UTC 2024 + Wed Nov 27 16:33:06 UTC 2024 outputProductCRC - 9:1eaebf2b + 9:5d5ff010 @@ -958,11 +958,11 @@ GENtimestamp - Tue Nov 26 14:18:46 UTC 2024 + Wed Nov 27 16:35:56 UTC 2024 outputProductCRC - 9:5a9d8cb3 + 9:f75ccf4d @@ -977,11 +977,11 @@ GENtimestamp - Tue Nov 26 14:15:30 UTC 2024 + Wed Nov 27 16:33:36 UTC 2024 outputProductCRC - 9:5a9d8cb3 + 9:f75ccf4d @@ -994,7 +994,7 @@ outputProductCRC - 9:383766bf + 9:acafc754 sim_type @@ -1014,11 +1014,11 @@ GENtimestamp - Tue Nov 26 14:15:30 UTC 2024 + Wed Nov 27 16:33:37 UTC 2024 outputProductCRC - 9:383766bf + 9:acafc754 sim_type @@ -1038,11 +1038,11 @@ GENtimestamp - Tue Nov 26 14:15:30 UTC 2024 + Wed Nov 27 16:33:37 UTC 2024 outputProductCRC - 9:5a9d8cb3 + 9:f75ccf4d @@ -30629,7 +30629,7 @@ C_DATA_DEPTH Sample Data Depth - 16384 + 8192 @@ -37022,19 +37022,68 @@ mixed - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xml index c498e87..b2a9b1c 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xml @@ -503,7 +503,7 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 15:52:06 UTC 2024 outputProductCRC @@ -522,7 +522,7 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 15:52:06 UTC 2024 outputProductCRC @@ -540,7 +540,7 @@ GENtimestamp - Tue Nov 26 14:16:46 UTC 2024 + Wed Nov 27 15:53:19 UTC 2024 outputProductCRC @@ -571,7 +571,7 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 15:52:06 UTC 2024 outputProductCRC @@ -591,7 +591,7 @@ GENtimestamp - Tue Nov 26 14:15:34 UTC 2024 + Wed Nov 27 15:52:06 UTC 2024 outputProductCRC diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/sim/design_1.vhd b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/sim/design_1.vhd index 47403a8..1312ca8 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/sim/design_1.vhd +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/sim/design_1.vhd @@ -2,8 +2,8 @@ --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Tue Nov 26 15:15:29 2024 ---Host : BiermannSurface running 64-bit major release (build 9200) +--Date : Wed Nov 27 17:33:33 2024 +--Host : sb0217-172 running 64-bit major release (build 9200) --Command : generate_target design_1.bd --Design : design_1 --Purpose : IP block netlist diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/synth/design_1.vhd b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/synth/design_1.vhd index 47403a8..1312ca8 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/synth/design_1.vhd +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/synth/design_1.vhd @@ -2,8 +2,8 @@ --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 ---Date : Tue Nov 26 15:15:29 2024 ---Host : BiermannSurface running 64-bit major release (build 9200) +--Date : Wed Nov 27 17:33:33 2024 +--Host : sb0217-172 running 64-bit major release (build 9200) --Command : generate_target design_1.bd --Design : design_1 --Purpose : IP block netlist diff --git a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/mref/axis_prog_audio_filter3/component.xml b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/mref/axis_prog_audio_filter3/component.xml index 46052f9..ea9d45d 100644 --- a/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/mref/axis_prog_audio_filter3/component.xml +++ b/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/mref/axis_prog_audio_filter3/component.xml @@ -301,7 +301,7 @@ viewChecksum - f3a26ecd + 7d34b594 @@ -314,7 +314,7 @@ viewChecksum - f3a26ecd + 7d34b594 @@ -855,7 +855,7 @@ IPI 1 - 2024-11-26T14:02:40Z + 2024-11-27T16:32:03Z 2023.1 diff --git a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/af_sim.bd b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/af_sim.bd index 2d8d58c..6d32536 100644 --- a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/af_sim.bd +++ b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/af_sim.bd @@ -7,8 +7,7 @@ "name": "af_sim", "rev_ctrl_bd_flag": "RevCtrlBdOff", "synth_flow_mode": "Hierarchical", - "tool_version": "2023.1", - "validated": "true" + "tool_version": "2023.1" }, "design_tree": { "clk_rst_generator_0": "", diff --git a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xci b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xci index 24e700c..320ac01 100644 --- a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xci +++ b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xci @@ -137,26 +137,26 @@ "mode": "slave", "memory_map_ref": "S_AXIL", "parameters": { - "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ui/bd_279d689d.ui b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ui/bd_279d689d.ui index e9f1b6c..907ff82 100644 --- a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ui/bd_279d689d.ui +++ b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ui/bd_279d689d.ui @@ -8,10 +8,10 @@ "Interfaces View_Layout":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD preplace inst axis_audio_master_si_0 -pg 1 -lvl 2 -x 140 -y 60 -defaultsOSRD -preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 5 -x 780 -y 70 -defaultsOSRD -preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 3 -x 340 -y 60 -defaultsOSRD -preplace inst axis_audio_slave_sim_0 -pg 1 -lvl 6 -x 980 -y 70 -defaultsOSRD -preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 4 -x 560 -y 70 -defaultsOSRD +preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 5 -x 830 -y 70 -defaultsOSRD +preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 3 -x 350 -y 60 -defaultsOSRD +preplace inst axis_audio_slave_sim_0 -pg 1 -lvl 6 -x 1040 -y 70 -defaultsOSRD +preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 4 -x 590 -y 70 -defaultsOSRD preplace netloc axis_audio_master_si_0_WAV_HEADER 1 2 4 250J -40n NJ -40n NJ -40n 1080 preplace netloc axis_audio_slave_sim_0_FINISHED 1 0 7 -240 -30n NJ -30n NJ -30n NJ -30n NJ -30n NJ -30n 1360 preplace netloc clk_rst_generator_0_clk 1 1 5 -10 -80n 260 -80n 540 -70n 830 -60n 1060 @@ -20,8 +20,8 @@ preplace netloc axis_audio_master_si_0_M_AXIS 1 2 1 N 60 preplace netloc axis_audio_mono2ster_0_M_AXIS 1 5 1 N 70 preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 3 1 N 60 preplace netloc axis_prog_audio_filt_0_M_AXIS 1 4 1 N 70 -levelinfo -pg 1 0 20 140 340 560 780 980 1080 -pagesize -pg 1 -db -bbox -sgen 0 0 1080 140 +levelinfo -pg 1 0 20 140 350 590 830 1040 1140 +pagesize -pg 1 -db -bbox -sgen 0 0 1140 140 ", "Interfaces View_ScaleFactor":"1.39512", "Interfaces View_TopLeft":"32,-191", diff --git a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/design_1.bd b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/design_1.bd index 2ec1f55..e45df38 100644 --- a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/design_1.bd +++ b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/design_1.bd @@ -127,7 +127,7 @@ "inst_hier_path": "system_ila_0", "parameters": { "C_DATA_DEPTH": { - "value": "16384" + "value": "8192" }, "C_NUM_MONITOR_SLOTS": { "value": "3" @@ -177,6 +177,20 @@ "xci_name": "design_1_axis_prog_audio_filt_0_1", "xci_path": "ip\\design_1_axis_prog_audio_filt_0_1\\design_1_axis_prog_audio_filt_0_1.xci", "inst_hier_path": "axis_prog_audio_filt_0", + "parameters": { + "COEFF_0": { + "value": "16" + }, + "COEFF_1": { + "value": "32" + }, + "COEFF_2": { + "value": "16" + }, + "SHIFT": { + "value": "6" + } + }, "reference_info": { "ref_type": "hdl", "ref_name": "axis_prog_audio_filter3", diff --git a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci index 4b9de3b..2ae9e14 100644 --- a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci +++ b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci @@ -8,19 +8,19 @@ "gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1", "parameters": { "component_parameters": { - "COEFF_0": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ], - "COEFF_1": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ], - "COEFF_2": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ], - "SHIFT": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ], + "COEFF_0": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "COEFF_1": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "COEFF_2": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SHIFT": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Component_Name": [ { "value": "design_1_axis_prog_audio_filt_0_1", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "COEFF_0": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "COEFF_1": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "COEFF_2": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "SHIFT": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "COEFF_0": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "COEFF_1": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "COEFF_2": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SHIFT": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ], "RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ] }, @@ -137,26 +137,26 @@ "mode": "slave", "memory_map_ref": "S_AXIL", "parameters": { - "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci index 97bc159..1d41545 100644 --- a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci +++ b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci @@ -2571,7 +2571,7 @@ "C_PROBE2_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "C_PROBE1_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "C_PROBE0_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], - "C_DATA_DEPTH": [ { "value": "16384", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_DATA_DEPTH": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_NUM_OF_PROBES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "resolve_type": "user", "usage": "all" } ], "Component_Name": [ { "value": "design_1_system_ila_0_0", "resolve_type": "user", "usage": "all" } ], @@ -3900,13 +3900,13 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_src": "default_prop", "resolve_type": "generated", "is_static_object": false } ], - "ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] }, "port_maps": { @@ -3918,7 +3918,7 @@ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", "mode": "slave", "parameters": { - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "resolve_type": "generated", "is_static_object": false } ], + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] }, "port_maps": { @@ -3930,36 +3930,36 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "monitor", "parameters": { - "DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "generated", "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "is_static_object": false } ], - "HAS_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_LOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_CACHE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_READ_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], - "NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] }, "port_maps": { @@ -3989,18 +3989,18 @@ "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", "mode": "monitor", "parameters": { - "TDATA_NUM_BYTES": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "TDATA_NUM_BYTES": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], - "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] }, "port_maps": { @@ -4015,18 +4015,18 @@ "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", "mode": "monitor", "parameters": { - "TDATA_NUM_BYTES": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_TLAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "TDATA_NUM_BYTES": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], - "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] }, "port_maps": { diff --git a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui index 9b8a36e..780cd77 100644 --- a/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui +++ b/Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui @@ -1,7 +1,7 @@ { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"1.42004", - "Default View_TopLeft":"20,-332", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-825,-402", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD @@ -23,8 +23,8 @@ preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 940 -y 110 -defaultsOSRD preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1170 -y 130 -defaultsOSRD preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 3 -x 640 -y -110 -defaultsOSRD preplace netloc clk_1 1 0 1 -220 -40n -preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 500 0 820 180 1050 -preplace netloc clk_rst_generator_0_rst_n 1 1 3 190 -20 510 -20 830 +preplace netloc clk_rst_generator_0_clk 1 1 4 170 -160 490 0 820 180 1050 +preplace netloc clk_rst_generator_0_rst_n 1 1 3 180 -20 500 -20 830 preplace netloc rec_dat_1 1 0 5 NJ 200 NJ 200 NJ 200 NJ 200 1060 preplace netloc resez_1 1 0 1 N 0 preplace netloc zybo_audio_0_bclk 1 5 1 1290 140n @@ -33,11 +33,11 @@ preplace netloc zybo_audio_0_mute 1 5 1 1290 10n preplace netloc zybo_audio_0_pb_dat 1 5 1 1300 40n preplace netloc zybo_audio_0_pb_lrc 1 5 1 1280 180n preplace netloc zybo_audio_0_rec_lrc 1 5 1 1320 190n -preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 480 -210 NJ +preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 470 -210 NJ preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 N 110 -preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 490 -200 770J +preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 480 -200 780J preplace netloc axis_prog_audio_filt_0_M_AXIS 1 3 1 810 -170n -preplace netloc zybo_audio_0_axis_rec 1 1 5 200 -10 NJ -10 NJ -10 NJ -10 1280 +preplace netloc zybo_audio_0_axis_rec 1 1 5 190 -10 NJ -10 NJ -10 NJ -10 1280 preplace netloc zybo_audio_0_i2c 1 5 1 N 80 levelinfo -pg 1 -240 -20 320 640 940 1170 1340 pagesize -pg 1 -db -bbox -sgen -340 -420 1450 560 diff --git a/Milestone3/es-milestone3/es-milestone3.xpr b/Milestone3/es-milestone3/es-milestone3.xpr index 7ee3fc8..a7b66bc 100644 --- a/Milestone3/es-milestone3/es-milestone3.xpr +++ b/Milestone3/es-milestone3/es-milestone3.xpr @@ -4,7 +4,7 @@ - + @@ -186,6 +186,14 @@ + + + + + + + + @@ -214,12 +222,6 @@ - - - - + + + + @@ -252,7 +260,7 @@ - + @@ -302,7 +310,7 @@ - + @@ -312,19 +320,17 @@ - - - - Vivado Synthesis Defaults - - - - - - - - + + + + + + + + + + Vivado Synthesis Defaults @@ -336,7 +342,7 @@ - + @@ -422,7 +428,7 @@ - + @@ -439,11 +445,9 @@ - + - - Default settings for Implementation. - + @@ -458,7 +462,7 @@ - + Default settings for Implementation. diff --git a/Milestone3/sources/axis_audio_filter3.vhd b/Milestone3/sources/axis_audio_filter3.vhd index 28e90c2..eccb1f5 100644 --- a/Milestone3/sources/axis_audio_filter3.vhd +++ b/Milestone3/sources/axis_audio_filter3.vhd @@ -97,7 +97,6 @@ begin case state is when IDLE => - S_AXIS_TREADY <= '1'; if S_AXIS_TVALID = '1' then s2 := s1; s1 := s0; @@ -112,6 +111,7 @@ begin res := res + (p2(23)&p2(23)&p2); state <= CALC; + S_AXIS_TREADY <= '0'; end if; when CALC => M_AXIS_TVALID <= '1';