From ce96ef2158c28f681a78f4cce43a42d5e6e7a9d8 Mon Sep 17 00:00:00 2001 From: Sebastian Meyer Date: Tue, 10 Dec 2024 13:32:25 +0100 Subject: [PATCH] =?UTF-8?q?IP=20f=C3=BCr=20die=20n=C3=A4chste=20Aufagaben?= =?UTF-8?q?=20eingebunden.=20Loeffezienten=20direkt=20eingetragen?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Milestone6/axis_video_filter.vhd | 40 +- .../sources_1/bd/design_1/design_1.bxml | 8 +- .../bd/design_1/hdl/design_1_wrapper.v | 80 +- .../design_1_axis_video_filter_1_1.xml} | 14 +- .../sim/design_1_axis_video_filter_1_1.v} | 2 +- .../sources_1/bd/design_1/sim/design_1.v | 122 +- .../sources_1/bd/design_1/synth/design_1.v | 122 +- .../sources_1/bd/design_2/design_2.bxml | 11 + .../design_2_auto_pc_0/design_2_auto_pc_0.xml | 4016 ++ .../design_2_axi_2d_mmvs_0_0.xml | 3931 ++ .../design_2_axi_interconnect_0_0.xml | 1644 + .../design_2_axi_mem_intercon_0.xml | 1644 + .../design_2_axis_downsizer_0_0.xml | 721 + .../design_2_axis_linemem_single_0_0.xml | 834 + .../design_2_axis_upsizer_0_0.xml | 737 + .../design_2_axis_video_filter_0_0.xml | 1429 + .../design_2_processing_system7_0_0.xml | 40131 +++++++++++++ .../design_2_ps7_0_axi_periph_0.xml | 1644 + .../design_2_rst_ps7_0_100M_0.xml | 700 + .../ip/design_2_xbar_0/design_2_xbar_0.xml | 47191 ++++++++++++++++ .../design_2_xlconcat_0_0.xml | 4809 ++ .../design_2_xlconstant_0_0.xml | 69 + .../design_2_zynq_base_hdmi_0_0.xml | 3140 + .../bd/mref/axis_video_filter/component.xml | 6 +- .../sources_1/bd/design_1/design_1.bd | 262 +- .../design_1_axis_video_filter_1_1.xci | 232 + .../sources_1/bd/design_1/ui/bd_1f5defd0.ui | 43 +- .../sources_1/bd/design_2/design_2.bd | 3558 ++ .../design_2_auto_pc_0/design_2_auto_pc_0.xci | 301 + .../design_2_axi_2d_mmvs_0_0.xci | 433 + .../design_2_axi_interconnect_0_0.xci | 352 + .../design_2_axi_mem_intercon_0.xci | 352 + .../design_2_axis_downsizer_0_0.xci | 148 + .../design_2_axis_linemem_single_0_0.xci | 150 + .../design_2_axis_upsizer_0_0.xci | 148 + .../design_2_axis_video_filter_0_0.xci} | 8 +- .../design_2_processing_system7_0_0.xci | 1692 + .../design_2_ps7_0_axi_periph_0.xci | 352 + .../design_2_rst_ps7_0_100M_0.xci | 195 + .../ip/design_2_xbar_0/design_2_xbar_0.xci | 1673 + .../design_2_xlconcat_0_0.xci | 306 + .../design_2_xlconstant_0_0.xci | 49 + .../design_2_zynq_base_hdmi_0_0.xci | 390 + .../sources_1/bd/design_2/ui/bd_1fdbff51.ui | 59 + .../sources_1/bd/design_2/ui/bd_3b5c004.ui | 35 + .../sources_1/bd/design_2/ui/bd_9bff7ad4.ui | 37 + Milestone6/milestone6/milestone6.xpr | 30 +- 47 files changed, 123283 insertions(+), 567 deletions(-) rename Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/{design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xml => design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml} (99%) rename Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/{design_1_axis_video_filter_0_0/sim/design_1_axis_video_filter_0_0.v => design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.v} (99%) create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_interconnect_0_0/design_2_axi_interconnect_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_mem_intercon_0/design_2_axi_mem_intercon_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axis_downsizer_0_0/design_2_axis_downsizer_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axis_linemem_single_0_0/design_2_axis_linemem_single_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axis_upsizer_0_0/design_2_axis_upsizer_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0/design_2_axis_video_filter_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_ps7_0_axi_periph_0/design_2_ps7_0_axi_periph_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_rst_ps7_0_100M_0/design_2_rst_ps7_0_100M_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_xlconcat_0_0/design_2_xlconcat_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_xlconstant_0_0/design_2_xlconstant_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xml create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axi_interconnect_0_0/design_2_axi_interconnect_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axi_mem_intercon_0/design_2_axi_mem_intercon_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_downsizer_0_0/design_2_axis_downsizer_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_linemem_single_0_0/design_2_axis_linemem_single_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_upsizer_0_0/design_2_axis_upsizer_0_0.xci rename Milestone6/milestone6/milestone6.srcs/sources_1/bd/{design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xci => design_2/ip/design_2_axis_video_filter_0_0/design_2_axis_video_filter_0_0.xci} (98%) create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_ps7_0_axi_periph_0/design_2_ps7_0_axi_periph_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_rst_ps7_0_100M_0/design_2_rst_ps7_0_100M_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_xbar_0/design_2_xbar_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_xlconcat_0_0/design_2_xlconcat_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_xlconstant_0_0/design_2_xlconstant_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_zynq_base_hdmi_0_0/design_2_zynq_base_hdmi_0_0.xci create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_3b5c004.ui create mode 100644 Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_9bff7ad4.ui diff --git a/Milestone6/axis_video_filter.vhd b/Milestone6/axis_video_filter.vhd index b810fee..69ff729 100644 --- a/Milestone6/axis_video_filter.vhd +++ b/Milestone6/axis_video_filter.vhd @@ -16,7 +16,7 @@ entity axis_video_filter is -- AXI Streaming Target Port (from linemem) S_AXIS_TVALID : in std_logic := '0'; - S_AXIS_TDATA : in std_logic_vector(23 downto 0); --Blau, gruen, rot jeweils 8 Bit pro pixel + S_AXIS_TDATA : in std_logic_vector(23 downto 0); --drei Pixel S_AXIS_TLAST : in std_logic := '0'; --letztes Pixel S_AXIS_TREADY : out std_logic; S_AXIS_TUSER : in std_logic_vector(2 downto 0); --ertes Pixel @@ -176,7 +176,18 @@ process begin coeff_31 <= (others=>'0'); coeff_32 <= (others=>'0'); coeff_33 <= (others=>'0'); + coeff_11 <= to_signed(-1, wCoeff); + coeff_12 <= to_signed(-1, wCoeff); + coeff_13 <= to_signed(-1, wCoeff); + coeff_21 <= to_signed(-1, wCoeff); + coeff_22 <= to_signed(8, wCoeff); + coeff_23 <= to_signed(-1, wCoeff); + coeff_31 <= to_signed(-1, wCoeff); + coeff_32 <= to_signed(-1, wCoeff); + coeff_33 <= to_signed(-1, wCoeff); + shiftAmount <= to_unsigned(0,wShift); + shiftAmount <= to_unsigned(3, wShift); -- Skalierung für die Summe der Koeffizienten else if S_AXIL_RREADY = '1' then S_AXIL_RVALID <= '0'; @@ -201,25 +212,26 @@ process begin end if; if S_AXIL_BREADY = '1' then - S_AXIL_BVALID <= '1'; + S_AXIL_BVALID <= '0'; end if; --schreiblogik if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then - S_AXIL_BVALID <= '0'; + S_AXIL_BVALID <= '1'; S_AXIL_RDATA <= (others=>'0'); - + + --nur die unterseten sieben Bits werden benutzt if S_AXIL_WSTRB(0) = '1' then case (to_integer(unsigned(S_AXIL_AWADDR(5 downto 0)))) is - when 0 => if S_AXIL_WSTRB(0) = '1' then coeff_11(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; - when 4 => if S_AXIL_WSTRB(0) = '1' then coeff_12(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; - when 8 => if S_AXIL_WSTRB(0) = '1' then coeff_13(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; - when 12 => if S_AXIL_WSTRB(0) = '1' then coeff_21(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; - when 16 => if S_AXIL_WSTRB(0) = '1' then coeff_22(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; - when 20 => if S_AXIL_WSTRB(0) = '1' then coeff_23(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; - when 24 => if S_AXIL_WSTRB(0) = '1' then coeff_31(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; - when 28 => if S_AXIL_WSTRB(0) = '1' then coeff_32(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; - when 32 => if S_AXIL_WSTRB(0) = '1' then coeff_33(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if; - when 36 => if S_AXIL_WSTRB(0) = '1' then shiftAmount(3 downto 0) <= unsigned(S_AXIL_WDATA(3 downto 0)); end if; + when 0 => coeff_11(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); + when 4 => coeff_12(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); + when 8 => coeff_13(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); + when 12 => coeff_21(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); + when 16 => coeff_22(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); + when 20 => coeff_23(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); + when 24 => coeff_31(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); + when 28 => coeff_32(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); + when 32 => coeff_33(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); + when 36 => shiftAmount(3 downto 0) <= unsigned(S_AXIL_WDATA(3 downto 0)); when others => null; end case; end if; diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml index e3cc8f2..5d07ea8 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/design_1.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v index eb16751..4654857 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v @@ -2,7 +2,7 @@ //Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 -//Date : Tue Dec 10 00:45:24 2024 +//Date : Tue Dec 10 12:47:32 2024 //Host : Bastistablet running 64-bit major release (build 9200) //Command : generate_target design_1_wrapper.bd //Design : design_1_wrapper @@ -11,83 +11,9 @@ `timescale 1 ps / 1 ps module design_1_wrapper - (m_axi_lite_araddr, - m_axi_lite_arprot, - m_axi_lite_arready, - m_axi_lite_arvalid, - m_axi_lite_awaddr, - m_axi_lite_awprot, - m_axi_lite_awready, - m_axi_lite_awvalid, - m_axi_lite_bready, - m_axi_lite_bresp, - m_axi_lite_bvalid, - m_axi_lite_rdata, - m_axi_lite_rready, - m_axi_lite_rresp, - m_axi_lite_rvalid, - m_axi_lite_wdata, - m_axi_lite_wready, - m_axi_lite_wstrb, - m_axi_lite_wvalid); - output [31:0]m_axi_lite_araddr; - output [2:0]m_axi_lite_arprot; - input m_axi_lite_arready; - output m_axi_lite_arvalid; - output [31:0]m_axi_lite_awaddr; - output [2:0]m_axi_lite_awprot; - input m_axi_lite_awready; - output m_axi_lite_awvalid; - output m_axi_lite_bready; - input [1:0]m_axi_lite_bresp; - input m_axi_lite_bvalid; - input [31:0]m_axi_lite_rdata; - output m_axi_lite_rready; - input [1:0]m_axi_lite_rresp; - input m_axi_lite_rvalid; - output [31:0]m_axi_lite_wdata; - input m_axi_lite_wready; - output [3:0]m_axi_lite_wstrb; - output m_axi_lite_wvalid; + (); - wire [31:0]m_axi_lite_araddr; - wire [2:0]m_axi_lite_arprot; - wire m_axi_lite_arready; - wire m_axi_lite_arvalid; - wire [31:0]m_axi_lite_awaddr; - wire [2:0]m_axi_lite_awprot; - wire m_axi_lite_awready; - wire m_axi_lite_awvalid; - wire m_axi_lite_bready; - wire [1:0]m_axi_lite_bresp; - wire m_axi_lite_bvalid; - wire [31:0]m_axi_lite_rdata; - wire m_axi_lite_rready; - wire [1:0]m_axi_lite_rresp; - wire m_axi_lite_rvalid; - wire [31:0]m_axi_lite_wdata; - wire m_axi_lite_wready; - wire [3:0]m_axi_lite_wstrb; - wire m_axi_lite_wvalid; design_1 design_1_i - (.m_axi_lite_araddr(m_axi_lite_araddr), - .m_axi_lite_arprot(m_axi_lite_arprot), - .m_axi_lite_arready(m_axi_lite_arready), - .m_axi_lite_arvalid(m_axi_lite_arvalid), - .m_axi_lite_awaddr(m_axi_lite_awaddr), - .m_axi_lite_awprot(m_axi_lite_awprot), - .m_axi_lite_awready(m_axi_lite_awready), - .m_axi_lite_awvalid(m_axi_lite_awvalid), - .m_axi_lite_bready(m_axi_lite_bready), - .m_axi_lite_bresp(m_axi_lite_bresp), - .m_axi_lite_bvalid(m_axi_lite_bvalid), - .m_axi_lite_rdata(m_axi_lite_rdata), - .m_axi_lite_rready(m_axi_lite_rready), - .m_axi_lite_rresp(m_axi_lite_rresp), - .m_axi_lite_rvalid(m_axi_lite_rvalid), - .m_axi_lite_wdata(m_axi_lite_wdata), - .m_axi_lite_wready(m_axi_lite_wready), - .m_axi_lite_wstrb(m_axi_lite_wstrb), - .m_axi_lite_wvalid(m_axi_lite_wvalid)); + (); endmodule diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml similarity index 99% rename from Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xml rename to Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml index 75eff95..cfea191 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xml +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xml @@ -2,7 +2,7 @@ xilinx.com customized_ip - design_1_axis_video_filter_0_0 + design_1_axis_video_filter_1_1 1.0 @@ -902,7 +902,7 @@ outputProductCRC - 9:c39d825f + 9:4ec30ce6 @@ -911,18 +911,18 @@ Verilog Simulation Wrapper verilogSource:vivado.xilinx.com:simulation.wrapper verilog - design_1_axis_video_filter_0_0 + design_1_axis_video_filter_1_1 xilinx_verilogsimulationwrapper_view_fileset GENtimestamp - Mon Dec 09 23:45:24 UTC 2024 + Tue Dec 10 11:47:32 UTC 2024 outputProductCRC - 9:c39d825f + 9:4ec30ce6 @@ -1378,7 +1378,7 @@ xilinx_verilogsimulationwrapper_view_fileset - sim/design_1_axis_video_filter_0_0.v + sim/design_1_axis_video_filter_1_1.v verilogSource xil_defaultlib @@ -1393,7 +1393,7 @@ Component_Name - design_1_axis_video_filter_0_0 + design_1_axis_video_filter_1_1 diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/sim/design_1_axis_video_filter_0_0.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.v similarity index 99% rename from Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/sim/design_1_axis_video_filter_0_0.v rename to Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.v index 9a12f5f..a7fee97 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/sim/design_1_axis_video_filter_0_0.v +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/sim/design_1_axis_video_filter_1_1.v @@ -54,7 +54,7 @@ (* IP_DEFINITION_SOURCE = "module_ref" *) (* DowngradeIPIdentifiedWarnings = "yes" *) -module design_1_axis_video_filter_0_0 ( +module design_1_axis_video_filter_1_1 ( ACLK, ARESETN, S_AXIS_TVALID, diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.v index cea85a6..894393e 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.v +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/sim/design_1.v @@ -2,7 +2,7 @@ //Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 -//Date : Tue Dec 10 00:45:24 2024 +//Date : Tue Dec 10 12:47:32 2024 //Host : Bastistablet running 64-bit major release (build 9200) //Command : generate_target design_1.bd //Design : design_1 @@ -12,53 +12,14 @@ (* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *) module design_1 - (m_axi_lite_araddr, - m_axi_lite_arprot, - m_axi_lite_arready, - m_axi_lite_arvalid, - m_axi_lite_awaddr, - m_axi_lite_awprot, - m_axi_lite_awready, - m_axi_lite_awvalid, - m_axi_lite_bready, - m_axi_lite_bresp, - m_axi_lite_bvalid, - m_axi_lite_rdata, - m_axi_lite_rready, - m_axi_lite_rresp, - m_axi_lite_rvalid, - m_axi_lite_wdata, - m_axi_lite_wready, - m_axi_lite_wstrb, - m_axi_lite_wvalid); - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axi_lite, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]m_axi_lite_araddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARPROT" *) output [2:0]m_axi_lite_arprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARREADY" *) input m_axi_lite_arready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARVALID" *) output m_axi_lite_arvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWADDR" *) output [31:0]m_axi_lite_awaddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWPROT" *) output [2:0]m_axi_lite_awprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWREADY" *) input m_axi_lite_awready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWVALID" *) output m_axi_lite_awvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BREADY" *) output m_axi_lite_bready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BRESP" *) input [1:0]m_axi_lite_bresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BVALID" *) input m_axi_lite_bvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RDATA" *) input [31:0]m_axi_lite_rdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RREADY" *) output m_axi_lite_rready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RRESP" *) input [1:0]m_axi_lite_rresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RVALID" *) input m_axi_lite_rvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WDATA" *) output [31:0]m_axi_lite_wdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WREADY" *) input m_axi_lite_wready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WSTRB" *) output [3:0]m_axi_lite_wstrb; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WVALID" *) output m_axi_lite_wvalid; + (); wire Net; wire Net1; wire [31:0]axil_master_with_rom_0_M_AXIL_ARADDR; - wire [2:0]axil_master_with_rom_0_M_AXIL_ARPROT; wire axil_master_with_rom_0_M_AXIL_ARREADY; wire axil_master_with_rom_0_M_AXIL_ARVALID; wire [31:0]axil_master_with_rom_0_M_AXIL_AWADDR; - wire [2:0]axil_master_with_rom_0_M_AXIL_AWPROT; wire axil_master_with_rom_0_M_AXIL_AWREADY; wire axil_master_with_rom_0_M_AXIL_AWVALID; wire axil_master_with_rom_0_M_AXIL_BREADY; @@ -93,40 +54,19 @@ module design_1 wire axis_upsizer_0_M_AXIS_TREADY; wire axis_upsizer_0_M_AXIS_TUSER; wire axis_upsizer_0_M_AXIS_TVALID; - wire [7:0]axis_video_filter_0_M_AXIS_TDATA; - wire axis_video_filter_0_M_AXIS_TLAST; - wire axis_video_filter_0_M_AXIS_TREADY; - wire axis_video_filter_0_M_AXIS_TUSER; - wire axis_video_filter_0_M_AXIS_TVALID; + wire [7:0]axis_video_filter_1_M_AXIS_TDATA; + wire axis_video_filter_1_M_AXIS_TLAST; + wire axis_video_filter_1_M_AXIS_TREADY; + wire axis_video_filter_1_M_AXIS_TUSER; + wire axis_video_filter_1_M_AXIS_TVALID; - assign axil_master_with_rom_0_M_AXIL_ARREADY = m_axi_lite_arready; - assign axil_master_with_rom_0_M_AXIL_AWREADY = m_axi_lite_awready; - assign axil_master_with_rom_0_M_AXIL_BRESP = m_axi_lite_bresp[1:0]; - assign axil_master_with_rom_0_M_AXIL_BVALID = m_axi_lite_bvalid; - assign axil_master_with_rom_0_M_AXIL_RDATA = m_axi_lite_rdata[31:0]; - assign axil_master_with_rom_0_M_AXIL_RRESP = m_axi_lite_rresp[1:0]; - assign axil_master_with_rom_0_M_AXIL_RVALID = m_axi_lite_rvalid; - assign axil_master_with_rom_0_M_AXIL_WREADY = m_axi_lite_wready; - assign m_axi_lite_araddr[31:0] = axil_master_with_rom_0_M_AXIL_ARADDR; - assign m_axi_lite_arprot[2:0] = axil_master_with_rom_0_M_AXIL_ARPROT; - assign m_axi_lite_arvalid = axil_master_with_rom_0_M_AXIL_ARVALID; - assign m_axi_lite_awaddr[31:0] = axil_master_with_rom_0_M_AXIL_AWADDR; - assign m_axi_lite_awprot[2:0] = axil_master_with_rom_0_M_AXIL_AWPROT; - assign m_axi_lite_awvalid = axil_master_with_rom_0_M_AXIL_AWVALID; - assign m_axi_lite_bready = axil_master_with_rom_0_M_AXIL_BREADY; - assign m_axi_lite_rready = axil_master_with_rom_0_M_AXIL_RREADY; - assign m_axi_lite_wdata[31:0] = axil_master_with_rom_0_M_AXIL_WDATA; - assign m_axi_lite_wstrb[3:0] = axil_master_with_rom_0_M_AXIL_WSTRB; - assign m_axi_lite_wvalid = axil_master_with_rom_0_M_AXIL_WVALID; design_1_axil_master_with_rom_0_0 axil_master_with_rom_0 (.M_AXIL_ACLK(Net), .M_AXIL_ARADDR(axil_master_with_rom_0_M_AXIL_ARADDR), .M_AXIL_ARESETN(Net1), - .M_AXIL_ARPROT(axil_master_with_rom_0_M_AXIL_ARPROT), .M_AXIL_ARREADY(axil_master_with_rom_0_M_AXIL_ARREADY), .M_AXIL_ARVALID(axil_master_with_rom_0_M_AXIL_ARVALID), .M_AXIL_AWADDR(axil_master_with_rom_0_M_AXIL_AWADDR), - .M_AXIL_AWPROT(axil_master_with_rom_0_M_AXIL_AWPROT), .M_AXIL_AWREADY(axil_master_with_rom_0_M_AXIL_AWREADY), .M_AXIL_AWVALID(axil_master_with_rom_0_M_AXIL_AWVALID), .M_AXIL_BREADY(axil_master_with_rom_0_M_AXIL_BREADY), @@ -191,28 +131,36 @@ module design_1 .M_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY), .M_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER), .M_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID), - .S_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA), - .S_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST), - .S_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY), - .S_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER), - .S_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID)); - design_1_axis_video_filter_0_0 axis_video_filter_0 + .S_AXIS_TDATA(axis_video_filter_1_M_AXIS_TDATA), + .S_AXIS_TLAST(axis_video_filter_1_M_AXIS_TLAST), + .S_AXIS_TREADY(axis_video_filter_1_M_AXIS_TREADY), + .S_AXIS_TUSER(axis_video_filter_1_M_AXIS_TUSER), + .S_AXIS_TVALID(axis_video_filter_1_M_AXIS_TVALID)); + design_1_axis_video_filter_1_1 axis_video_filter_1 (.ACLK(Net), .ARESETN(Net1), - .M_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA), - .M_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST), - .M_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY), - .M_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER), - .M_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID), - .S_AXIL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXIL_ARVALID(1'b0), - .S_AXIL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXIL_AWVALID(1'b0), - .S_AXIL_BREADY(1'b0), - .S_AXIL_RREADY(1'b0), - .S_AXIL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXIL_WSTRB({1'b1,1'b1,1'b1,1'b1}), - .S_AXIL_WVALID(1'b0), + .M_AXIS_TDATA(axis_video_filter_1_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_video_filter_1_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_video_filter_1_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_video_filter_1_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_video_filter_1_M_AXIS_TVALID), + .S_AXIL_ARADDR(axil_master_with_rom_0_M_AXIL_ARADDR[14:0]), + .S_AXIL_ARREADY(axil_master_with_rom_0_M_AXIL_ARREADY), + .S_AXIL_ARVALID(axil_master_with_rom_0_M_AXIL_ARVALID), + .S_AXIL_AWADDR(axil_master_with_rom_0_M_AXIL_AWADDR[14:0]), + .S_AXIL_AWREADY(axil_master_with_rom_0_M_AXIL_AWREADY), + .S_AXIL_AWVALID(axil_master_with_rom_0_M_AXIL_AWVALID), + .S_AXIL_BREADY(axil_master_with_rom_0_M_AXIL_BREADY), + .S_AXIL_BRESP(axil_master_with_rom_0_M_AXIL_BRESP), + .S_AXIL_BVALID(axil_master_with_rom_0_M_AXIL_BVALID), + .S_AXIL_RDATA(axil_master_with_rom_0_M_AXIL_RDATA), + .S_AXIL_RREADY(axil_master_with_rom_0_M_AXIL_RREADY), + .S_AXIL_RRESP(axil_master_with_rom_0_M_AXIL_RRESP), + .S_AXIL_RVALID(axil_master_with_rom_0_M_AXIL_RVALID), + .S_AXIL_WDATA(axil_master_with_rom_0_M_AXIL_WDATA), + .S_AXIL_WREADY(axil_master_with_rom_0_M_AXIL_WREADY), + .S_AXIL_WSTRB(axil_master_with_rom_0_M_AXIL_WSTRB), + .S_AXIL_WVALID(axil_master_with_rom_0_M_AXIL_WVALID), .S_AXIS_TDATA(axis_linemem_single_0_m_axis_TDATA), .S_AXIS_TLAST(axis_linemem_single_0_m_axis_TLAST), .S_AXIS_TREADY(axis_linemem_single_0_m_axis_TREADY), diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.v b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.v index cea85a6..894393e 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.v +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_1/synth/design_1.v @@ -2,7 +2,7 @@ //Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 -//Date : Tue Dec 10 00:45:24 2024 +//Date : Tue Dec 10 12:47:32 2024 //Host : Bastistablet running 64-bit major release (build 9200) //Command : generate_target design_1.bd //Design : design_1 @@ -12,53 +12,14 @@ (* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *) module design_1 - (m_axi_lite_araddr, - m_axi_lite_arprot, - m_axi_lite_arready, - m_axi_lite_arvalid, - m_axi_lite_awaddr, - m_axi_lite_awprot, - m_axi_lite_awready, - m_axi_lite_awvalid, - m_axi_lite_bready, - m_axi_lite_bresp, - m_axi_lite_bvalid, - m_axi_lite_rdata, - m_axi_lite_rready, - m_axi_lite_rresp, - m_axi_lite_rvalid, - m_axi_lite_wdata, - m_axi_lite_wready, - m_axi_lite_wstrb, - m_axi_lite_wvalid); - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axi_lite, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]m_axi_lite_araddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARPROT" *) output [2:0]m_axi_lite_arprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARREADY" *) input m_axi_lite_arready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARVALID" *) output m_axi_lite_arvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWADDR" *) output [31:0]m_axi_lite_awaddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWPROT" *) output [2:0]m_axi_lite_awprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWREADY" *) input m_axi_lite_awready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWVALID" *) output m_axi_lite_awvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BREADY" *) output m_axi_lite_bready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BRESP" *) input [1:0]m_axi_lite_bresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BVALID" *) input m_axi_lite_bvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RDATA" *) input [31:0]m_axi_lite_rdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RREADY" *) output m_axi_lite_rready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RRESP" *) input [1:0]m_axi_lite_rresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RVALID" *) input m_axi_lite_rvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WDATA" *) output [31:0]m_axi_lite_wdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WREADY" *) input m_axi_lite_wready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WSTRB" *) output [3:0]m_axi_lite_wstrb; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WVALID" *) output m_axi_lite_wvalid; + (); wire Net; wire Net1; wire [31:0]axil_master_with_rom_0_M_AXIL_ARADDR; - wire [2:0]axil_master_with_rom_0_M_AXIL_ARPROT; wire axil_master_with_rom_0_M_AXIL_ARREADY; wire axil_master_with_rom_0_M_AXIL_ARVALID; wire [31:0]axil_master_with_rom_0_M_AXIL_AWADDR; - wire [2:0]axil_master_with_rom_0_M_AXIL_AWPROT; wire axil_master_with_rom_0_M_AXIL_AWREADY; wire axil_master_with_rom_0_M_AXIL_AWVALID; wire axil_master_with_rom_0_M_AXIL_BREADY; @@ -93,40 +54,19 @@ module design_1 wire axis_upsizer_0_M_AXIS_TREADY; wire axis_upsizer_0_M_AXIS_TUSER; wire axis_upsizer_0_M_AXIS_TVALID; - wire [7:0]axis_video_filter_0_M_AXIS_TDATA; - wire axis_video_filter_0_M_AXIS_TLAST; - wire axis_video_filter_0_M_AXIS_TREADY; - wire axis_video_filter_0_M_AXIS_TUSER; - wire axis_video_filter_0_M_AXIS_TVALID; + wire [7:0]axis_video_filter_1_M_AXIS_TDATA; + wire axis_video_filter_1_M_AXIS_TLAST; + wire axis_video_filter_1_M_AXIS_TREADY; + wire axis_video_filter_1_M_AXIS_TUSER; + wire axis_video_filter_1_M_AXIS_TVALID; - assign axil_master_with_rom_0_M_AXIL_ARREADY = m_axi_lite_arready; - assign axil_master_with_rom_0_M_AXIL_AWREADY = m_axi_lite_awready; - assign axil_master_with_rom_0_M_AXIL_BRESP = m_axi_lite_bresp[1:0]; - assign axil_master_with_rom_0_M_AXIL_BVALID = m_axi_lite_bvalid; - assign axil_master_with_rom_0_M_AXIL_RDATA = m_axi_lite_rdata[31:0]; - assign axil_master_with_rom_0_M_AXIL_RRESP = m_axi_lite_rresp[1:0]; - assign axil_master_with_rom_0_M_AXIL_RVALID = m_axi_lite_rvalid; - assign axil_master_with_rom_0_M_AXIL_WREADY = m_axi_lite_wready; - assign m_axi_lite_araddr[31:0] = axil_master_with_rom_0_M_AXIL_ARADDR; - assign m_axi_lite_arprot[2:0] = axil_master_with_rom_0_M_AXIL_ARPROT; - assign m_axi_lite_arvalid = axil_master_with_rom_0_M_AXIL_ARVALID; - assign m_axi_lite_awaddr[31:0] = axil_master_with_rom_0_M_AXIL_AWADDR; - assign m_axi_lite_awprot[2:0] = axil_master_with_rom_0_M_AXIL_AWPROT; - assign m_axi_lite_awvalid = axil_master_with_rom_0_M_AXIL_AWVALID; - assign m_axi_lite_bready = axil_master_with_rom_0_M_AXIL_BREADY; - assign m_axi_lite_rready = axil_master_with_rom_0_M_AXIL_RREADY; - assign m_axi_lite_wdata[31:0] = axil_master_with_rom_0_M_AXIL_WDATA; - assign m_axi_lite_wstrb[3:0] = axil_master_with_rom_0_M_AXIL_WSTRB; - assign m_axi_lite_wvalid = axil_master_with_rom_0_M_AXIL_WVALID; design_1_axil_master_with_rom_0_0 axil_master_with_rom_0 (.M_AXIL_ACLK(Net), .M_AXIL_ARADDR(axil_master_with_rom_0_M_AXIL_ARADDR), .M_AXIL_ARESETN(Net1), - .M_AXIL_ARPROT(axil_master_with_rom_0_M_AXIL_ARPROT), .M_AXIL_ARREADY(axil_master_with_rom_0_M_AXIL_ARREADY), .M_AXIL_ARVALID(axil_master_with_rom_0_M_AXIL_ARVALID), .M_AXIL_AWADDR(axil_master_with_rom_0_M_AXIL_AWADDR), - .M_AXIL_AWPROT(axil_master_with_rom_0_M_AXIL_AWPROT), .M_AXIL_AWREADY(axil_master_with_rom_0_M_AXIL_AWREADY), .M_AXIL_AWVALID(axil_master_with_rom_0_M_AXIL_AWVALID), .M_AXIL_BREADY(axil_master_with_rom_0_M_AXIL_BREADY), @@ -191,28 +131,36 @@ module design_1 .M_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY), .M_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER), .M_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID), - .S_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA), - .S_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST), - .S_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY), - .S_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER), - .S_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID)); - design_1_axis_video_filter_0_0 axis_video_filter_0 + .S_AXIS_TDATA(axis_video_filter_1_M_AXIS_TDATA), + .S_AXIS_TLAST(axis_video_filter_1_M_AXIS_TLAST), + .S_AXIS_TREADY(axis_video_filter_1_M_AXIS_TREADY), + .S_AXIS_TUSER(axis_video_filter_1_M_AXIS_TUSER), + .S_AXIS_TVALID(axis_video_filter_1_M_AXIS_TVALID)); + design_1_axis_video_filter_1_1 axis_video_filter_1 (.ACLK(Net), .ARESETN(Net1), - .M_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA), - .M_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST), - .M_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY), - .M_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER), - .M_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID), - .S_AXIL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXIL_ARVALID(1'b0), - .S_AXIL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXIL_AWVALID(1'b0), - .S_AXIL_BREADY(1'b0), - .S_AXIL_RREADY(1'b0), - .S_AXIL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXIL_WSTRB({1'b1,1'b1,1'b1,1'b1}), - .S_AXIL_WVALID(1'b0), + .M_AXIS_TDATA(axis_video_filter_1_M_AXIS_TDATA), + .M_AXIS_TLAST(axis_video_filter_1_M_AXIS_TLAST), + .M_AXIS_TREADY(axis_video_filter_1_M_AXIS_TREADY), + .M_AXIS_TUSER(axis_video_filter_1_M_AXIS_TUSER), + .M_AXIS_TVALID(axis_video_filter_1_M_AXIS_TVALID), + .S_AXIL_ARADDR(axil_master_with_rom_0_M_AXIL_ARADDR[14:0]), + .S_AXIL_ARREADY(axil_master_with_rom_0_M_AXIL_ARREADY), + .S_AXIL_ARVALID(axil_master_with_rom_0_M_AXIL_ARVALID), + .S_AXIL_AWADDR(axil_master_with_rom_0_M_AXIL_AWADDR[14:0]), + .S_AXIL_AWREADY(axil_master_with_rom_0_M_AXIL_AWREADY), + .S_AXIL_AWVALID(axil_master_with_rom_0_M_AXIL_AWVALID), + .S_AXIL_BREADY(axil_master_with_rom_0_M_AXIL_BREADY), + .S_AXIL_BRESP(axil_master_with_rom_0_M_AXIL_BRESP), + .S_AXIL_BVALID(axil_master_with_rom_0_M_AXIL_BVALID), + .S_AXIL_RDATA(axil_master_with_rom_0_M_AXIL_RDATA), + .S_AXIL_RREADY(axil_master_with_rom_0_M_AXIL_RREADY), + .S_AXIL_RRESP(axil_master_with_rom_0_M_AXIL_RRESP), + .S_AXIL_RVALID(axil_master_with_rom_0_M_AXIL_RVALID), + .S_AXIL_WDATA(axil_master_with_rom_0_M_AXIL_WDATA), + .S_AXIL_WREADY(axil_master_with_rom_0_M_AXIL_WREADY), + .S_AXIL_WSTRB(axil_master_with_rom_0_M_AXIL_WSTRB), + .S_AXIL_WVALID(axil_master_with_rom_0_M_AXIL_WVALID), .S_AXIS_TDATA(axis_linemem_single_0_m_axis_TDATA), .S_AXIS_TLAST(axis_linemem_single_0_m_axis_TLAST), .S_AXIS_TREADY(axis_linemem_single_0_m_axis_TREADY), diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml new file mode 100644 index 0000000..72a4257 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/design_2.bxml @@ -0,0 +1,11 @@ + + + + Composite Fileset + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xml new file mode 100644 index 0000000..5b96f9e --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_auto_pc_0/design_2_auto_pc_0.xml @@ -0,0 +1,4016 @@ + + + xilinx.com + customized_ip + design_2_auto_pc_0 + 1.0 + + + S_AXI + S_AXI + + + + + + + AWID + + + s_axi_awid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWLEN + + + s_axi_awlen + + + + + AWSIZE + + + s_axi_awsize + + + + + AWBURST + + + s_axi_awburst + + + + + AWLOCK + + + s_axi_awlock + + + + + AWCACHE + + + s_axi_awcache + + + + + AWPROT + + + s_axi_awprot + + + + + AWREGION + + + s_axi_awregion + + + + + AWQOS + + + s_axi_awqos + + + + + AWUSER + + + s_axi_awuser + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WID + + + s_axi_wid + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WLAST + + + s_axi_wlast + + + + + WUSER + + + s_axi_wuser + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BID + + + s_axi_bid + + + + + BRESP + + + s_axi_bresp + + + + + BUSER + + + s_axi_buser + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARID + + + s_axi_arid + + + + + ARADDR + + + s_axi_araddr + + + + + ARLEN + + + s_axi_arlen + + + + + ARSIZE + + + s_axi_arsize + + + + + ARBURST + + + s_axi_arburst + + + + + ARLOCK + + + s_axi_arlock + + + + + ARCACHE + + + s_axi_arcache + + + + + ARPROT + + + s_axi_arprot + + + + + ARREGION + + + s_axi_arregion + + + + + ARQOS + + + s_axi_arqos + + + + + ARUSER + + + s_axi_aruser + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RID + + + s_axi_rid + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RLAST + + + s_axi_rlast + + + + + RUSER + + + s_axi_ruser + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + DATA_WIDTH + 32 + + + simulation.tlm + + + + + PROTOCOL + AXI3 + + + simulation.tlm + + + + + FREQ_HZ + 100000000 + + + simulation.tlm + + + + + ID_WIDTH + 12 + + + simulation.tlm + + + + + ADDR_WIDTH + 32 + + + simulation.tlm + + + + + AWUSER_WIDTH + 0 + + + simulation.tlm + + + + + ARUSER_WIDTH + 0 + + + simulation.tlm + + + + + WUSER_WIDTH + 0 + + + simulation.tlm + + + + + RUSER_WIDTH + 0 + + + simulation.tlm + + + + + BUSER_WIDTH + 0 + + + simulation.tlm + + + + + READ_WRITE_MODE + READ_WRITE + + + simulation.tlm + + + + + HAS_BURST + 1 + + + simulation.tlm + + + + + HAS_LOCK + 1 + + + simulation.tlm + + + + + HAS_PROT + 1 + + + simulation.tlm + + + + + HAS_CACHE + 1 + + + simulation.tlm + + + + + HAS_QOS + 1 + + + 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C_IGNORE_ID + 0 + + + C_AXI_ID_WIDTH + 12 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 32 + + + C_AXI_SUPPORTS_WRITE + 1 + + + C_AXI_SUPPORTS_READ + 1 + + + C_AXI_SUPPORTS_USER_SIGNALS + 0 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_TRANSLATION_MODE + 2 + + + + + + choice_list_7235ff92 + AXI4 + AXI3 + AXI4LITE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_dfc23cd1 + AXI4 + AXI4LITE + + + choice_pairs_940700f2 + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_fc76701f + 2 + 0 + + + The AXI Protocol Converter IP provides the facility to change the protocol of the connection between an AXI4/AXI3/AXI4-Lite master and slave. It will convert between AXI4->AXI3/AXI4-Lite, AXI3->AXI4/AXI4-Lite, AXI4-Lite->AXI4/AXI3. + + + SI_PROTOCOL + SI PROTOCOL + AXI3 + + + MI_PROTOCOL + MI PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE Mode + READ_WRITE + + + TRANSLATION_MODE + Translation Mode + 2 + + + ADDR_WIDTH + Address Width + 32 + + + DATA_WIDTH + Data Width + 32 + + + ID_WIDTH + ID Width + 12 + + + AWUSER_WIDTH + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + ARUSER_WIDTH + 0 + + + RUSER_WIDTH + RUSER_WIDTH + 0 + + + WUSER_WIDTH + WUSER_WIDTH + 0 + + + BUSER_WIDTH + BUSER_WIDTH + 0 + + + Component_Name + design_2_auto_pc_0 + + + + + AXI Protocol Converter + + xtlm + + 28 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xml new file mode 100644 index 0000000..2594732 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_2d_mmvs_0_0/design_2_axi_2d_mmvs_0_0.xml @@ -0,0 +1,3931 @@ + + + Gehrke + customized_ip + design_2_axi_2d_mmvs_0_0 + 1.0 + + + M_AXI + + + + + + + + + AWID + + + M_AXI_AWID + + + + + AWADDR + + + M_AXI_AWADDR + + + + + AWLEN + + + M_AXI_AWLEN + + + + + AWSIZE + + + M_AXI_AWSIZE + + + + + AWBURST + + + M_AXI_AWBURST + + + + + AWCACHE + + + M_AXI_AWCACHE + + + + + AWPROT + + + M_AXI_AWPROT + + + + + AWVALID + + + M_AXI_AWVALID + + + + + AWREADY + + + M_AXI_AWREADY + + + + + WDATA + + + M_AXI_WDATA + + + + + WSTRB + + + M_AXI_WSTRB + + + + + WLAST + + + M_AXI_WLAST + + + + + WVALID + + + M_AXI_WVALID + + + + + WREADY + + + M_AXI_WREADY + + + + + BID + + + M_AXI_BID + + + + + BRESP + + + M_AXI_BRESP + + + + + BVALID + + + M_AXI_BVALID + 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0x38000000 + + + DEFAULT_MM2VS_REG_HOR_BYTES + MM2VS: Horizontal Size [Bytes] + 1024 + + + DEFAULT_MM2VS_REG_STRIDE + MM2VS: Stride [Bytes] + 1024 + + + DEFAULT_MM2VS_REG_VER_LINES + MM2VS: Vertical Size [Lines] + 1024 + + + DEFAULT_MM2VS_REG_INT_LINE + MM2VS INT Line + 0 + + + VS2MM_ENABLE + VS2MM Enable + true + + + VS2MM_MAX_BURSTLEN + VS2MM: Maximum Burst Length + 16 + + + VS2MM_FIFO_AWIDTH + VS2MM: FIFO Adress Width + 9 + + + DEFAULT_VS2MM_REG_STARTADDR + VS2MM: Startaddress + 0x38000000 + + + DEFAULT_VS2MM_REG_HOR_BYTES + VS2MM: Horizontal Size [Bytes] + 1024 + + + DEFAULT_VS2MM_REG_STRIDE + VS2MM: Stride [Bytes] + 1024 + + + DEFAULT_VS2MM_REG_VER_LINES + VS2MM: Vertical Size [Lines] + 1024 + + + DEFAULT_VS2MM_REG_INT_LINE + VS2MM INT Line + 0 + + + DEFAULT_REG_INT_ENABLE + INT Enable Register + 0 + + + Component_Name + design_2_axi_2d_mmvs_0_0 + + + DEFAULT_MM2VS_REG_CTRL_RUN + MM2VS: Run + 0 + + + DEFAULT_MM2VS_REG_CTRL_SYNC_SOF + MM2VS: Synchronisation with Start of Frame (SOF) + 0 + + + DEFAULT_MM2VS_REG_CTRL_NUM_BUFF + MM2VS: Number of additional (Frame) Buffers + 1 + + + DEFAULT_MM2VS_REG_CTRL_AxCACHE + MM2VS: AxCACHE Setting + 0 + + + DEFAULT_VS2MM_REG_CTRL_RUN + VS2MM: Run + 0 + + + DEFAULT_VS2MM_REG_CTRL_SYNC_SOF + VS2MM: Synchronisation with Start of Frame (SOF) + 0 + + + DEFAULT_VS2MM_REG_CTRL_NUM_BUFF + VS2MM: Number of additional (Frame) Buffers + 1 + + + DEFAULT_VS2MM_REG_CTRL_AxCACHE + VS2MM: AxCACHE Setting + 0 + + + MM2VS_VS2MM_IDWIDTH + ID width + 1 + + + HAS_INTERRUPT_OUTPUT + Interrupt Outputs present + true + + + HAS_FINISHED_OUTPUT + Finished Pulse Outputs present + false + + + SINGLE_CLOCK_AND_RESETN + Single Clock And Resetn + true + + + + + axi_2d_mmvs + 44 + + d:/Projekte/edvs/vivado/vivado/ip_projects/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + 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d:/ES-IP/IP/axi_2d_mmvs/axi_2d_mmvs.srcs/sources_1/new + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_interconnect_0_0/design_2_axi_interconnect_0_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_interconnect_0_0/design_2_axi_interconnect_0_0.xml new file mode 100644 index 0000000..eca3c7a --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_interconnect_0_0/design_2_axi_interconnect_0_0.xml @@ -0,0 +1,1644 @@ + + + xilinx.com + customized_ip + design_2_axi_interconnect_0_0 + 1.0 + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_661c4a03 + 2 + 4 + 8 + 16 + 32 + 64 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_76d086ea + 0 + 1 + 2 + + + choice_pairs_ab2668a2 + 0 + 1 + 2 + + + choice_pairs_b6c9535e + 0 + 1 + 3 + 4 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 1 + + + NUM_MI + Number of Master Interfaces + 1 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 3 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 0 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 0 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_SECURE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_SECURE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_SECURE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_SECURE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_SECURE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_SECURE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_SECURE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_SECURE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_SECURE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_SECURE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_SECURE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_SECURE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_SECURE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_SECURE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_SECURE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_SECURE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_SECURE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_SECURE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_SECURE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_SECURE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_SECURE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_SECURE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_SECURE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_SECURE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_SECURE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_SECURE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_SECURE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_SECURE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_SECURE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_SECURE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_SECURE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_SECURE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_SECURE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_SECURE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_SECURE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_SECURE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_SECURE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_SECURE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_SECURE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_SECURE + Incicates whether M63_AXI connects to a secure slave + 0 + + + S00_ARB_PRIORITY + Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S01_ARB_PRIORITY + Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S02_ARB_PRIORITY + Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S03_ARB_PRIORITY + Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S04_ARB_PRIORITY + Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S05_ARB_PRIORITY + Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S06_ARB_PRIORITY + Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S07_ARB_PRIORITY + Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S08_ARB_PRIORITY + Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S09_ARB_PRIORITY + Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S10_ARB_PRIORITY + Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S11_ARB_PRIORITY + Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S12_ARB_PRIORITY + Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S13_ARB_PRIORITY + Controls S13_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S14_ARB_PRIORITY + Controls S14_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S15_ARB_PRIORITY + Controls S15_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + Component_Name + design_2_axi_interconnect_0_0 + + + + + AXI Interconnect + 29 + + + + + + + + 2023.1 + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_mem_intercon_0/design_2_axi_mem_intercon_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_mem_intercon_0/design_2_axi_mem_intercon_0.xml new file mode 100644 index 0000000..3dae58c --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_axi_mem_intercon_0/design_2_axi_mem_intercon_0.xml @@ -0,0 +1,1644 @@ + + + xilinx.com + customized_ip + design_2_axi_mem_intercon_0 + 1.0 + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_661c4a03 + 2 + 4 + 8 + 16 + 32 + 64 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_76d086ea + 0 + 1 + 2 + + + choice_pairs_ab2668a2 + 0 + 1 + 2 + + + choice_pairs_b6c9535e + 0 + 1 + 3 + 4 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 1 + + + NUM_MI + Number of Master Interfaces + 3 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 3 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 0 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 0 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_SECURE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_SECURE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_SECURE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_SECURE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_SECURE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_SECURE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_SECURE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_SECURE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_SECURE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_SECURE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_SECURE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_SECURE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_SECURE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_SECURE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_SECURE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_SECURE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_SECURE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_SECURE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_SECURE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_SECURE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_SECURE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_SECURE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_SECURE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_SECURE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_SECURE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_SECURE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_SECURE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_SECURE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_SECURE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_SECURE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_SECURE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_SECURE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_SECURE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_SECURE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_SECURE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_SECURE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_SECURE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_SECURE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_SECURE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_SECURE + Incicates whether M63_AXI connects to a secure slave + 0 + + + S00_ARB_PRIORITY + Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S01_ARB_PRIORITY + Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S02_ARB_PRIORITY + Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S03_ARB_PRIORITY + Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S04_ARB_PRIORITY + Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S05_ARB_PRIORITY + Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S06_ARB_PRIORITY + Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S07_ARB_PRIORITY + Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S08_ARB_PRIORITY + Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S09_ARB_PRIORITY + Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S10_ARB_PRIORITY + Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S11_ARB_PRIORITY + Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S12_ARB_PRIORITY + Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S13_ARB_PRIORITY + Controls S13_ARB_PRIORITY on SI axi_crossbar instance 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<Select> + x8 + + + choice_list_3c74058c + <Select> + MIO 0 + MIO 2 + MIO 4 + MIO 6 + MIO 8 + MIO 10 + MIO 12 + MIO 14 + MIO 16 + MIO 18 + MIO 20 + MIO 22 + MIO 24 + MIO 26 + MIO 28 + MIO 30 + MIO 32 + MIO 34 + MIO 36 + MIO 38 + MIO 40 + MIO 42 + MIO 44 + MIO 46 + MIO 48 + MIO 50 + MIO 52 + + + choice_list_3f5f808e + LVCMOS 3.3V + LVCMOS 2.5V + HSTL 1.8V + LVCMOS 1.8V + + + choice_list_45a0fd9c + <Select> + EMIO + MIO 14 .. 15 + MIO 26 .. 27 + + + choice_list_46eb370a + DIRECT + REVERSE + + + choice_list_49727578 + 0x00100000 + 0x00040000 + + + choice_list_4d36a164 + <Select> + Low + Medium + High + + + choice_list_52fb759e + MIO 8 + + + choice_list_544741b4 + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + 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choice_list_6885bca1 + Share reset pin + Separate reset pins + + + choice_list_6a282484 + <Select> + EMIO + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choice_list_6a48f1e0 + MIO + + + choice_list_6bc4d474 + LVCMOS 3.3V + + + choice_list_6bd7fb73 + Active High + Active Low + + + choice_list_72f3e128 + LVCMOS 1.8V + LVCMOS 2.5V + LVCMOS 3.3V + HSTL 1.8V + + + choice_list_75a9626b + EMIO + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + 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fast + slow + + + choice_list_86cc57ee + EMIO + MIO 16 .. 27 + + + choice_list_88fe7673 + 0xE0000FFF + + + choice_list_893462de + <Select> + EMIO + MIO 8 .. 9 + MIO 12 .. 13 + MIO 16 .. 17 + MIO 20 .. 21 + MIO 24 .. 25 + MIO 28 .. 29 + MIO 32 .. 33 + MIO 36 .. 37 + MIO 40 .. 41 + MIO 44 .. 45 + MIO 48 .. 49 + MIO 52 .. 53 + + + choice_list_89b9cafe + 0xE0001FFF + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_8ca738ca + 0xE0005FFF + + + choice_list_8de08447 + 0xE0004FFF + + + choice_list_8e2841d0 + 0xE0007FFF + + + choice_list_8f11124f + EMIO + MIO 16 .. 21 + MIO 28 .. 33 + MIO 40 .. 45 + + + choice_list_8f6ffd5d + 0xE0006FFF + + + choice_list_908f40dd + <Select> + EMIO + MIO 16 .. 19 + + + choice_list_92aefd84 + 0xE0104000 + + + choice_list_935a3e6e + <Select> + EMIO + MIO 12 .. 13 + MIO 24 .. 25 + + + choice_list_93a2bb4f + <Select> + EMIO + MIO 13 + MIO 25 + MIO 37 + MIO 49 + + + choice_list_93e94109 + 0xE0105000 + + + choice_list_9478ca27 + 0xE0103000 + + + choice_list_953f76aa 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6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choice_list_b4a6147c + 0xE000B000 + + + choice_list_b5e1a8f1 + 0xE000C000 + + + choice_list_b66926f4 + <Select> + EMIO + MIO 28 .. 39 + + + choice_list_b6ff1ce3 + <Select> + EMIO + MIO 15 + MIO 27 + MIO 39 + MIO 51 + + + choice_list_b76ed1eb + 0xE000A000 + + + choice_list_ba65fe0e + <Select> + EMIO + MIO 2 .. 9 + + + choice_list_bbba28a6 + DDR3_1066E + DDR3_1066F + DDR3_1066G + DDR3_1333F + DDR3_1333G + DDR3_1333H + DDR3_1333J + DDR3_1600G + DDR3_1600H + DDR3_1600J + DDR3_1600K + + + choice_list_bc805c93 + <Select> + x1 + x2 + x4 + + + choice_list_bd8e4b31 + 6:2:1 + 4:2:1 + + + choice_list_be8ca58c + MT41J128M8 JP-125 + MT41J128M8 JP-15E + MT41J64M16 JT-125G + MT41J64M16 JT-15E + MT41J256M8 DA-107 + MT41K128M16 JT-125 + MT41J256M8 HX-125 + MT41J256M8 HX-15E + MT41J256M8 HX-187E + MT41J128M16 HA-107G + MT41J128M16 HA-125 + MT41J128M16 HA-15E + MT41J128M16 HA-187E + MT41J512M8 RA-15E + MT41K128M16 HA-15E + MT41K256M16 RE-125 + MT41K256M16 RE-15E + MT41K256M8 DA-125 + MT41K256M8 DA-15E + MT41K256M8 HX-15E + MT41J256M16 RE-125 + Custom + + + choice_list_bed41605 + PRODUCTION + + + choice_list_c11320b6 + 0x3FFFFFFF + + + choice_list_c4046e95 + 0xE0100FFF + + + choice_list_c543d218 + 0xE0101FFF + + + choice_list_c5ebb0ea + LPDDR 2 + DDR 2 + DDR 3 + DDR 3 (Low Voltage) + + + choice_list_ca108395 + 2 + 4 + 8 + 16 + 32 + + + choice_list_cbbe7bdf + MIO 1 .. 6 + + + choice_list_ce2e47bd + Share reset pin + + + choice_list_d0304fb3 + 0xE0009000 + + + choice_list_d10f4555 + FALSE + TRUE + + + choice_list_d177f33e + 0xE0008000 + + + choice_list_d282f9a2 + <Select> + EMIO + MIO 16 .. 17 + MIO 28 .. 29 + MIO 40 .. 41 + + + choice_list_d2a5f697 + CPU_1X + External + + + choice_list_d2f51b63 + <Select> + MIO 0 9 .. 13 + + + choice_list_d525dd8e + 0xFCFFFFFF + + + choice_list_d679c87d + <Select> + MIO 0 + MIO 1 + MIO 2 + MIO 3 + MIO 4 + MIO 5 + MIO 6 + MIO 7 + MIO 8 + MIO 9 + MIO 10 + MIO 11 + MIO 12 + MIO 13 + MIO 14 + MIO 15 + MIO 16 + MIO 17 + MIO 18 + MIO 19 + MIO 20 + MIO 21 + MIO 22 + MIO 23 + MIO 24 + MIO 25 + MIO 26 + MIO 27 + MIO 28 + MIO 29 + MIO 30 + MIO 31 + MIO 32 + MIO 33 + MIO 34 + MIO 35 + MIO 36 + MIO 37 + MIO 38 + MIO 39 + MIO 40 + MIO 41 + MIO 42 + MIO 43 + MIO 44 + MIO 45 + MIO 46 + MIO 47 + MIO 48 + MIO 49 + MIO 50 + MIO 51 + MIO 52 + MIO 53 + + + choice_list_da0dabdb + 0xE0001000 + + + choice_list_db4a1756 + 0xE0000000 + + + choice_list_dc85a6c5 + ARM PLL + DDR PLL + External + IO PLL + + + choice_list_dcdb9c78 + 0xE0006000 + + + choice_list_dd9c20f5 + 0xE0007000 + + + choice_list_de54e562 + 0xE0004000 + + + choice_list_df1359ef + 0xE0005000 + + + choice_list_e14dbfa8 + <Select> + MIO 0 + + + choice_list_e4dab0ce + 0xE000AFFF + + + choice_list_e655c9d4 + 0xE000CFFF + + + choice_list_e7127559 + 0xE000BFFF + + + choice_list_e743b0fa + DDR PLL + + + choice_list_ea556125 + ARM PLL + DDR PLL + IO PLL + + + choice_list_eaad72ce + 8 Bits + 16 Bits + 32 Bits + + + choice_list_f192fb1e + <Select> + EMIO + MIO 19 + MIO 31 + MIO 43 + + + choice_list_f585525a + 110 + 300 + 1200 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 128000 + 230400 + 460800 + 921600 + + + choice_list_f591e16e + DDR PLL + ARM PLL + IO PLL + + + choice_list_f5e7200e + 6 + 12 + + + choice_list_f632ce2e + EMIO + MIO 10 .. 11 + MIO 14 .. 15 + MIO 18 .. 19 + MIO 22 .. 23 + MIO 26 .. 27 + MIO 30 .. 31 + MIO 34 .. 35 + MIO 38 .. 39 + MIO 42 .. 43 + MIO 46 .. 47 + MIO 50 .. 51 + + + choice_list_f7022b26 + <Select> + EMIO + MIO 10 .. 15 + MIO 22 .. 27 + MIO 34 .. 39 + MIO 46 .. 51 + + + choice_list_f7b6ff1b + <Select> + EMIO + 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0xE0005000 + + + + true + + + + + + PCW_I2C1_HIGHADDR + PCW I2C1 HIGHADDR + 0xE0005FFF + + + + true + + + + + + PCW_SPI0_BASEADDR + PCW SPI0 BASEADDR + 0xE0006000 + + + + false + + + + + + PCW_SPI0_HIGHADDR + PCW SPI0 HIGHADDR + 0xE0006FFF + + + + false + + + + + + PCW_SPI1_BASEADDR + PCW SPI1 BASEADDR + 0xE0007000 + + + + false + + + + + + PCW_SPI1_HIGHADDR + PCW SPI1 HIGHADDR + 0xE0007FFF + + + + false + + + + + + PCW_CAN0_BASEADDR + PCW CAN0 BASEADDR + 0xE0008000 + + + + false + + + + + + PCW_CAN0_HIGHADDR + PCW CAN0 HIGHADDR + 0xE0008FFF + + + + false + + + + + + PCW_CAN1_BASEADDR + PCW CAN1 BASEADDR + 0xE0009000 + + + + false + + + + + + PCW_CAN1_HIGHADDR + PCW CAN1 HIGHADDR + 0xE0009FFF + + + + false + + + + + + PCW_GPIO_BASEADDR + PCW GPIO BASEADDR + 0xE000A000 + + + + true + + + + + + PCW_GPIO_HIGHADDR + PCW GPIO HIGHADDR + 0xE000AFFF + + + + true + + + + + + PCW_ENET0_BASEADDR + PCW ENET0 BASEADDR + 0xE000B000 + + + + true + + + + + + PCW_ENET0_HIGHADDR + PCW ENET0 HIGHADDR + 0xE000BFFF + + + + true + + + + + + PCW_ENET1_BASEADDR + PCW ENET1 BASEADDR + 0xE000C000 + + + + false + + + + + + PCW_ENET1_HIGHADDR + PCW ENET1 HIGHADDR + 0xE000CFFF + + + + false + + + + + + PCW_SDIO0_BASEADDR + PCW SDIO0 BASEADDR + 0xE0100000 + + + + true + + + + + + PCW_SDIO0_HIGHADDR + PCW SDIO0 HIGHADDR + 0xE0100FFF + + + + true + + + + + + PCW_SDIO1_BASEADDR + PCW SDIO1 BASEADDR + 0xE0101000 + + + + false + + + + + + PCW_SDIO1_HIGHADDR + PCW SDIO1 HIGHADDR + 0xE0101FFF + + + + false + + + + + + PCW_USB0_BASEADDR + PCW USB0 BASEADDR + 0xE0102000 + + + + true + + + + + + PCW_USB0_HIGHADDR + PCW USB0 HIGHADDR + 0xE0102fff + + + + true + + + + + + PCW_USB1_BASEADDR + PCW USB1 BASEADDR + 0xE0103000 + + + + false + + + + + + PCW_USB1_HIGHADDR + PCW USB1 HIGHADDR + 0xE0103fff + + + + false + + + + + + PCW_TTC0_BASEADDR + PCW TTC0 BASEADDR + 0xE0104000 + + + + true + + + + + + PCW_TTC0_HIGHADDR + PCW TTC0 HIGHADDR + 0xE0104fff + + + + true + + + + + + PCW_TTC1_BASEADDR + PCW TTC1 BASEADDR + 0xE0105000 + + + + false + + + + + + PCW_TTC1_HIGHADDR + PCW TTC1 HIGHADDR + 0xE0105fff + + + + false + + + + + + PCW_FCLK_CLK0_BUF + PCW FCLK CLK0 BUF + TRUE + + + + true + + + + + + PCW_FCLK_CLK1_BUF + PCW FCLK CLK1 BUF + TRUE + + + + true + + + + + + PCW_FCLK_CLK2_BUF + PCW FCLK CLK2 BUF + TRUE + + + + true + + + + + + PCW_FCLK_CLK3_BUF + PCW FCLK CLK3 BUF + TRUE + + + + true + + + + + + PCW_UIPARAM_DDR_FREQ_MHZ + PCW UIPARAM DDR FREQ MHZ + 533.333333 + + + PCW_UIPARAM_DDR_BANK_ADDR_COUNT + PCW UIPARAM DDR BANK ADDR COUNT + 3 + + + + false + + + + + + PCW_UIPARAM_DDR_ROW_ADDR_COUNT + PCW UIPARAM DDR ROW ADDR COUNT + 15 + + + + false + + + + + + PCW_UIPARAM_DDR_COL_ADDR_COUNT + PCW UIPARAM DDR COL ADDR COUNT + 10 + + + + false + + + + + + PCW_UIPARAM_DDR_CL + PCW UIPARAM DDR CL + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_CWL + PCW UIPARAM DDR CWL + 6 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RCD + PCW UIPARAM DDR T RCD + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RP + PCW UIPARAM DDR T RP + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RC + PCW UIPARAM DDR T RC + 48.75 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RAS_MIN + PCW UIPARAM DDR T RAS MIN + 35.0 + + + + false + + + + + + PCW_UIPARAM_DDR_T_FAW + PCW UIPARAM DDR T FAW + 40.0 + + + + false + + + + + + PCW_UIPARAM_DDR_AL + PCW UIPARAM DDR AL + 0 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 + PCW UIPARAM DDR DQS TO CLK DELAY 0 + -0.050 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 + PCW UIPARAM DDR DQS TO CLK DELAY 1 + -0.044 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 + PCW UIPARAM DDR DQS TO CLK DELAY 2 + -0.035 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 + PCW UIPARAM DDR DQS TO CLK DELAY 3 + -0.100 + + + PCW_UIPARAM_DDR_BOARD_DELAY0 + PCW UIPARAM DDR BOARD DELAY0 + 0.221 + + + PCW_UIPARAM_DDR_BOARD_DELAY1 + PCW UIPARAM DDR BOARD DELAY1 + 0.222 + + + PCW_UIPARAM_DDR_BOARD_DELAY2 + PCW UIPARAM DDR BOARD DELAY2 + 0.217 + + + PCW_UIPARAM_DDR_BOARD_DELAY3 + PCW UIPARAM DDR BOARD DELAY3 + 0.244 + + + PCW_UIPARAM_DDR_DQS_0_LENGTH_MM + PCW UIPARAM DDR DQS 0 LENGTH MM + 22.8 + + + PCW_UIPARAM_DDR_DQS_1_LENGTH_MM + PCW UIPARAM DDR DQS 1 LENGTH MM + 27.9 + + + PCW_UIPARAM_DDR_DQS_2_LENGTH_MM + PCW UIPARAM DDR DQS 2 LENGTH MM + 22.9 + + + PCW_UIPARAM_DDR_DQS_3_LENGTH_MM + PCW UIPARAM DDR DQS 3 LENGTH MM + 29.4 + + + PCW_UIPARAM_DDR_DQ_0_LENGTH_MM + PCW UIPARAM DDR DQ 0 LENGTH MM + 22.8 + + + PCW_UIPARAM_DDR_DQ_1_LENGTH_MM + PCW UIPARAM DDR DQ 1 LENGTH MM + 27.9 + + + PCW_UIPARAM_DDR_DQ_2_LENGTH_MM + PCW UIPARAM DDR DQ 2 LENGTH MM + 22.9 + + + PCW_UIPARAM_DDR_DQ_3_LENGTH_MM + PCW UIPARAM DDR DQ 3 LENGTH MM + 29.4 + + + PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM + PCW UIPARAM DDR CLOCK 0 LENGTH MM + 18.8 + + + PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM + PCW UIPARAM DDR CLOCK 1 LENGTH MM + 18.8 + + + PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM + PCW UIPARAM DDR CLOCK 2 LENGTH MM + 18.8 + + + PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM + PCW UIPARAM DDR CLOCK 3 LENGTH MM + 18.8 + + + PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 0 PACKAGE LENGTH + 105.056 + + + PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 1 PACKAGE LENGTH + 66.904 + + + PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 2 PACKAGE LENGTH + 89.1715 + + + PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 3 PACKAGE LENGTH + 113.63 + + + PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 0 PACKAGE LENGTH + 98.503 + + + PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 1 PACKAGE LENGTH + 68.5855 + + + PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 2 PACKAGE LENGTH + 90.295 + + + PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 3 PACKAGE LENGTH + 103.977 + + + PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 0 PACKAGE LENGTH + 80.4535 + + + PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 1 PACKAGE LENGTH + 80.4535 + + + PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 2 PACKAGE LENGTH + 80.4535 + + + PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 3 PACKAGE LENGTH + 80.4535 + + + PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 0 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 1 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 2 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 3 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 0 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 1 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 2 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 3 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 0 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 1 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 2 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 3 PROPOGATION DELAY + 160 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 + PCW PACKAGE DDR DQS TO CLK DELAY 0 + -0.050 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 + PCW PACKAGE DDR DQS TO CLK DELAY 1 + -0.044 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 + PCW PACKAGE DDR DQS TO CLK DELAY 2 + -0.035 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 + PCW PACKAGE DDR DQS TO CLK DELAY 3 + -0.100 + + + PCW_PACKAGE_DDR_BOARD_DELAY0 + PCW PACKAGE DDR BOARD DELAY0 + 0.221 + + + PCW_PACKAGE_DDR_BOARD_DELAY1 + PCW PACKAGE DDR BOARD DELAY1 + 0.222 + + + PCW_PACKAGE_DDR_BOARD_DELAY2 + PCW PACKAGE DDR BOARD DELAY2 + 0.217 + + + PCW_PACKAGE_DDR_BOARD_DELAY3 + PCW PACKAGE DDR BOARD DELAY3 + 0.244 + + + PCW_CPU_CPU_6X4X_MAX_RANGE + PCW CPU CPU 6X4X MAX RANGE + 667 + + + PCW_CRYSTAL_PERIPHERAL_FREQMHZ + PCW CRYSTAL PERIPHERAL FREQMHZ + 33.333333 + + + PCW_APU_PERIPHERAL_FREQMHZ + PCW APU PERIPHERAL FREQMHZ + 667 + + + PCW_DCI_PERIPHERAL_FREQMHZ + PCW DCI PERIPHERAL FREQMHZ + 10.159 + + + PCW_QSPI_PERIPHERAL_FREQMHZ + PCW QSPI PERIPHERAL FREQMHZ + 200 + + + PCW_SMC_PERIPHERAL_FREQMHZ + PCW SMC PERIPHERAL FREQMHZ + 100 + + + + false + + + + + + PCW_USB0_PERIPHERAL_FREQMHZ + PCW USB0 PERIPHERAL FREQMHZ + 60 + + + + false + + + + + + PCW_USB1_PERIPHERAL_FREQMHZ + PCW USB1 PERIPHERAL FREQMHZ + 60 + + + + false + + + + + + PCW_SDIO_PERIPHERAL_FREQMHZ + PCW SDIO PERIPHERAL FREQMHZ + 50 + + + PCW_UART_PERIPHERAL_FREQMHZ + PCW UART PERIPHERAL FREQMHZ + 100 + + + PCW_SPI_PERIPHERAL_FREQMHZ + PCW SPI PERIPHERAL FREQMHZ + 166.666666 + + + + false + + + + + + PCW_CAN_PERIPHERAL_FREQMHZ + PCW CAN PERIPHERAL FREQMHZ + 100 + + + + false + + + + + + PCW_CAN0_PERIPHERAL_FREQMHZ + PCW CAN0 PERIPHERAL FREQMHZ + -1 + + + + false + + + + + + PCW_CAN1_PERIPHERAL_FREQMHZ + PCW CAN1 PERIPHERAL FREQMHZ + -1 + + + + false + + + + + + PCW_I2C_PERIPHERAL_FREQMHZ + PCW I2C PERIPHERAL FREQMHZ + 111.111115 + + + PCW_WDT_PERIPHERAL_FREQMHZ + PCW WDT PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC_PERIPHERAL_FREQMHZ + PCW TTC PERIPHERAL FREQMHZ + 50 + + + PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ + PCW TTC0 CLK0 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ + PCW TTC0 CLK1 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ + PCW TTC0 CLK2 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ + PCW TTC1 CLK0 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ + PCW TTC1 CLK1 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ + PCW TTC1 CLK2 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_PCAP_PERIPHERAL_FREQMHZ + PCW PCAP PERIPHERAL FREQMHZ + 200 + + + PCW_TPIU_PERIPHERAL_FREQMHZ + PCW TPIU PERIPHERAL FREQMHZ + 200 + + + + false + + + + + + PCW_FPGA0_PERIPHERAL_FREQMHZ + PCW FPGA0 PERIPHERAL FREQMHZ + 100 + + + PCW_FPGA1_PERIPHERAL_FREQMHZ + PCW FPGA1 PERIPHERAL FREQMHZ + 125 + + + PCW_FPGA2_PERIPHERAL_FREQMHZ + PCW FPGA2 PERIPHERAL FREQMHZ + 200 + + + PCW_FPGA3_PERIPHERAL_FREQMHZ + PCW FPGA3 PERIPHERAL FREQMHZ + 65 + + + PCW_ACT_APU_PERIPHERAL_FREQMHZ + PCW ACT APU PERIPHERAL FREQMHZ + 666.666687 + + + PCW_UIPARAM_ACT_DDR_FREQ_MHZ + PCW UIPARAM ACT DDR FREQ MHZ + 533.333374 + + + PCW_ACT_DCI_PERIPHERAL_FREQMHZ + PCW ACT DCI PERIPHERAL FREQMHZ + 10.158730 + + + PCW_ACT_QSPI_PERIPHERAL_FREQMHZ + PCW ACT QSPI PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_SMC_PERIPHERAL_FREQMHZ + PCW ACT SMC PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_ENET0_PERIPHERAL_FREQMHZ + PCW ACT ENET0 PERIPHERAL FREQMHZ + 125.000000 + + + PCW_ACT_ENET1_PERIPHERAL_FREQMHZ + PCW ACT ENET1 PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_USB0_PERIPHERAL_FREQMHZ + PCW ACT USB0 PERIPHERAL FREQMHZ + 60 + + + PCW_ACT_USB1_PERIPHERAL_FREQMHZ + PCW ACT USB1 PERIPHERAL FREQMHZ + 60 + + + PCW_ACT_SDIO_PERIPHERAL_FREQMHZ + PCW ACT SDIO PERIPHERAL FREQMHZ + 50.000000 + + + PCW_ACT_UART_PERIPHERAL_FREQMHZ + PCW ACT UART PERIPHERAL FREQMHZ + 100.000000 + + + PCW_ACT_SPI_PERIPHERAL_FREQMHZ + PCW ACT SPI PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_CAN_PERIPHERAL_FREQMHZ + PCW ACT CAN PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_CAN0_PERIPHERAL_FREQMHZ + PCW ACT CAN0 PERIPHERAL FREQMHZ + 23.8095 + + + PCW_ACT_CAN1_PERIPHERAL_FREQMHZ + PCW ACT CAN0 PERIPHERAL FREQMHZ + 23.8095 + + + PCW_ACT_I2C_PERIPHERAL_FREQMHZ + PCW ACT I2C PERIPHERAL FREQMHZ + 50 + + + PCW_ACT_WDT_PERIPHERAL_FREQMHZ + PCW ACT WDT PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC_PERIPHERAL_FREQMHZ + PCW ACT TTC PERIPHERAL FREQMHZ + 50 + + + PCW_ACT_PCAP_PERIPHERAL_FREQMHZ + PCW ACT PCAP PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_TPIU_PERIPHERAL_FREQMHZ + PCW ACT TPIU PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ + PCW ACT FPGA0 PERIPHERAL FREQMHZ + 100.000000 + + + PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ + PCW ACT FPGA1 PERIPHERAL FREQMHZ + 125.000000 + + + PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ + PCW ACT FPGA2 PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ + PCW ACT FPGA3 PERIPHERAL FREQMHZ + 66.666672 + + + PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK0 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK1 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK2 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK0 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK1 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK2 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_CLK0_FREQ + PCW CLK0 FREQ + 100000000 + + + PCW_CLK1_FREQ + PCW CLK1 FREQ + 125000000 + + + PCW_CLK2_FREQ + PCW CLK2 FREQ + 200000000 + + + PCW_CLK3_FREQ + PCW CLK3 FREQ + 66666672 + + + PCW_OVERRIDE_BASIC_CLOCK + PCW OVERRIDE FREQ + 0 + + + PCW_CPU_PERIPHERAL_DIVISOR0 + CLKPARAM + 2 + + + + false + + + + + + PCW_DDR_PERIPHERAL_DIVISOR0 + CLKPARAM + 2 + + + + false + + + + + + PCW_SMC_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_QSPI_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_SDIO_PERIPHERAL_DIVISOR0 + CLKPARAM + 20 + + + + false + + + + + + PCW_UART_PERIPHERAL_DIVISOR0 + CLKPARAM + 10 + + + + false + + + + + + PCW_SPI_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_CAN_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_CAN_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_FCLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 4 + + + + false + + + + + + PCW_FCLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_FCLK3_PERIPHERAL_DIVISOR0 + CLKPARAM + 15 + + + + false + + + + + + PCW_FCLK0_PERIPHERAL_DIVISOR1 + CLKPARAM + 2 + + + + false + + + + + + PCW_FCLK1_PERIPHERAL_DIVISOR1 + CLKPARAM + 2 + + + + false + + + + + + PCW_FCLK2_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK3_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET0_PERIPHERAL_DIVISOR0 + CLKPARAM + 8 + + + + false + + + + + + PCW_ENET1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET0_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET1_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_TPIU_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_DCI_PERIPHERAL_DIVISOR0 + CLKPARAM + 15 + + + + false + + + + + + PCW_DCI_PERIPHERAL_DIVISOR1 + CLKPARAM + 7 + + + + false + + + + + + PCW_PCAP_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_WDT_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_ARMPLL_CTRL_FBDIV + CLKPARAM + 40 + + + + false + + + + + + PCW_IOPLL_CTRL_FBDIV + CLKPARAM + 30 + + + + false + + + + + + PCW_DDRPLL_CTRL_FBDIV + CLKPARAM + 32 + + + + false + + + + + + PCW_CPU_CPU_PLL_FREQMHZ + CLKPARAM + 1333.333 + + + + false + + + + + + PCW_IO_IO_PLL_FREQMHZ + CLKPARAM + 1000.000 + + + + false + + + + + + PCW_DDR_DDR_PLL_FREQMHZ + CLKPARAM + 1066.667 + + + + false + + + + + + PCW_SMC_PERIPHERAL_VALID + PCW SMC PERIPHERAL VALID + 0 + + + PCW_SDIO_PERIPHERAL_VALID + PCW SDIO PERIPHERAL VALID + 1 + + + PCW_SPI_PERIPHERAL_VALID + PCW SPI PERIPHERAL VALID + 0 + + + PCW_CAN_PERIPHERAL_VALID + PCW CAN PERIPHERAL VALID + 0 + + + PCW_UART_PERIPHERAL_VALID + PCW UART PERIPHERAL VALID + 1 + + + PCW_EN_EMIO_CAN0 + PCW EN EMIO CAN0 + 0 + + + PCW_EN_EMIO_CAN1 + PCW EN EMIO CAN1 + 0 + + + PCW_EN_EMIO_ENET0 + PCW EN EMIO ENET0 + 0 + + + PCW_EN_EMIO_ENET1 + PCW EN EMIO ENET1 + 0 + + + PCW_EN_PTP_ENET0 + PCW EN PTP ENET0 + 0 + + + PCW_EN_PTP_ENET1 + PCW EN PTP ENET1 + 0 + + + PCW_EN_EMIO_GPIO + PCW EN EMIO GPIO + 0 + + + PCW_EN_EMIO_I2C0 + PCW EN EMIO I2C0 + 0 + + + PCW_EN_EMIO_I2C1 + PCW EN EMIO I2C1 + 0 + + + PCW_EN_EMIO_PJTAG + PCW EN EMIO PJTAG + 0 + + + PCW_EN_EMIO_SDIO0 + PCW EN EMIO SDIO0 + 0 + + + PCW_EN_EMIO_CD_SDIO0 + PCW EN EMIO CD SDIO0 + 0 + + + PCW_EN_EMIO_WP_SDIO0 + PCW EN EMIO WP SDIO0 + 1 + + + PCW_EN_EMIO_SDIO1 + PCW EN EMIO SDIO1 + 0 + + + PCW_EN_EMIO_CD_SDIO1 + PCW EN EMIO CD SDIO1 + 0 + + + PCW_EN_EMIO_WP_SDIO1 + PCW EN EMIO WP SDIO1 + 0 + + + PCW_EN_EMIO_SPI0 + PCW EN EMIO SPI0 + 0 + + + PCW_EN_EMIO_SPI1 + PCW EN EMIO SPI1 + 0 + + + PCW_EN_EMIO_UART0 + PCW EN EMIO UART0 + 0 + + + PCW_EN_EMIO_UART1 + PCW EN EMIO UART1 + 0 + + + PCW_EN_EMIO_MODEM_UART0 + PCW EN EMIO MODEM UART0 + 0 + + + PCW_EN_EMIO_MODEM_UART1 + PCW EN EMIO MODEM UART1 + 0 + + + PCW_EN_EMIO_TTC0 + PCW EN EMIO TTC0 + 1 + + + PCW_EN_EMIO_TTC1 + PCW EN EMIO TTC1 + 0 + + + PCW_EN_EMIO_WDT + PCW EN EMIO WDT + 0 + + + PCW_EN_EMIO_TRACE + PCW EN EMIO TRACE + 0 + + + PCW_USE_AXI_NONSECURE + PCW USE AXI NON SECURE + 0 + + + PCW_USE_M_AXI_GP0 + PCW USE M AXI GP0 + 1 + + + PCW_USE_M_AXI_GP1 + PCW USE M AXI GP1 + 0 + + + PCW_USE_S_AXI_GP0 + PCW USE S AXI GP0 + 0 + + + PCW_USE_S_AXI_GP1 + PCW USE S AXI GP1 + 0 + + + PCW_USE_S_AXI_ACP + PCW USE S AXI ACP + 1 + + + PCW_USE_S_AXI_HP0 + PCW USE S AXI HP0 + 1 + + + PCW_USE_S_AXI_HP1 + PCW USE S AXI HP1 + 0 + + + PCW_USE_S_AXI_HP2 + PCW USE S AXI HP2 + 0 + + + PCW_USE_S_AXI_HP3 + PCW USE S AXI HP3 + 0 + + + PCW_M_AXI_GP0_FREQMHZ + PCW M AXI GP0 FREQMHZ + 100 + + + + true + + + + + + PCW_M_AXI_GP1_FREQMHZ + PCW M AXI GP1 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_GP0_FREQMHZ + PCW S AXI GP0 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_GP1_FREQMHZ + PCW S AXI GP1 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_ACP_FREQMHZ + PCW S AXI ACP FREQMHZ + 10 + + + + true + + + + + + PCW_S_AXI_HP0_FREQMHZ + PCW S AXI HP0 FREQMHZ + 100 + + + + true + + + + + + PCW_S_AXI_HP1_FREQMHZ + PCW S AXI HP1 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_HP2_FREQMHZ + PCW S AXI HP2 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_HP3_FREQMHZ + PCW S AXI HP3 FREQMHZ + 10 + + + + false + + + + + + PCW_USE_DMA0 + PCW USE DMA0 + 0 + + + PCW_USE_DMA1 + PCW USE DMA1 + 0 + + + PCW_USE_DMA2 + PCW USE DMA2 + 0 + + + PCW_USE_DMA3 + PCW USE DMA3 + 0 + + + PCW_USE_TRACE + PCW USE TRACE + Enable FTM Trace interface used to capture data from PL to PS debug system + 0 + + + PCW_TRACE_PIPELINE_WIDTH + PCW TRACE PIPELINE WIDTH + 8 + + + + false + + + + + + PCW_INCLUDE_TRACE_BUFFER + PCW INCLUDE TRACE BUFFER + 0 + + + + false + + + + + + PCW_TRACE_BUFFER_FIFO_SIZE + PCW TRACE BUFFER FIFO SIZE + 128 + + + + false + + + + + + PCW_USE_TRACE_DATA_EDGE_DETECTOR + PCW USE TRACE DATA EDGE DETECTOR + 0 + + + + false + + + + + + PCW_TRACE_BUFFER_CLOCK_DELAY + PCW TRACE BUFFER CLOCK DELAY + 12 + + + + false + + + + + + PCW_USE_CROSS_TRIGGER + PCW USE CROSS TRIGGER + 0 + + + PCW_FTM_CTI_IN0 + <Select> + + + + false + + + + + + PCW_FTM_CTI_IN1 + <Select> + + + + false + + + + + + PCW_FTM_CTI_IN2 + <Select> + + + + false + + + + + + PCW_FTM_CTI_IN3 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT0 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT1 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT2 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT3 + <Select> + + + + false + + + + + + PCW_USE_DEBUG + PCW USE DEBUG + 0 + + + PCW_USE_CR_FABRIC + PCW USE CR FABRIC + 1 + + + PCW_USE_AXI_FABRIC_IDLE + PCW USE AXI FABRIC IDLE + Enables idle AXI signal to the PS used to indicate that there are no outstanding AXI transactions in the PL + 0 + + + PCW_USE_DDR_BYPASS + PCW USE DDR BYPASS + Enables DDR urgent/arb signal used to signal a critical memory starvation situation to the DDR arbitration for the four AXI ports of the PS DDR memory controller + 0 + + + PCW_USE_FABRIC_INTERRUPT + PCW USE FABRIC INTERRUPT + 1 + + + PCW_USE_PROC_EVENT_BUS + PCW USE PROC EVENT BUS + 0 + + + PCW_USE_EXPANDED_IOP + PCW USE EXPANDED IOP + 0 + + + PCW_USE_HIGH_OCM + PCW USE HIGH OCM + 0 + + + PCW_USE_PS_SLCR_REGISTERS + PCW USE PS SLCR REGISTERS + 0 + + + PCW_USE_EXPANDED_PS_SLCR_REGISTERS + PCW USE EXPANDED PS SLCR REGISTERS + 0 + + + + false + + + + + + PCW_USE_CORESIGHT + PCW USE CORESIGHT + 0 + + + PCW_EN_EMIO_SRAM_INT + PCW EN EMIO SRAM INT + 0 + + + PCW_GPIO_EMIO_GPIO_WIDTH + PCW EMIO GPIO WIDTH + 64 + + + + false + + + + + + PCW_GP0_NUM_WRITE_THREADS + GP0 NUM WRITE THREADS + 4 + + + PCW_GP0_NUM_READ_THREADS + GP0 NUM READ THREADS + 4 + + + PCW_GP1_NUM_WRITE_THREADS + GP1 NUM WRITE THREADS + 4 + + + PCW_GP1_NUM_READ_THREADS + GP1 NUM READ THREADS + 4 + + + PCW_UART0_BAUD_RATE + PCW UART0 BAUD RATE + Configure baud rate to determine UART0 operating frequency + 115200 + + + + true + + + + + + PCW_UART1_BAUD_RATE + PCW UART1 BAUD RATE + Configure baud rate to determine UART1 operating frequency + 115200 + + + + true + + + + + + PCW_EN_4K_TIMER + PCW EN 4K TIMER + 0 + + + PCW_M_AXI_GP0_ID_WIDTH + PCW M AXI GP0 ID WIDTH + 12 + + + + true + + + + + + PCW_M_AXI_GP0_ENABLE_STATIC_REMAP + PCW M AXI GP0 ENABLE STATIC REMAP + 0 + + + + true + + + + + + PCW_M_AXI_GP0_SUPPORT_NARROW_BURST + PCW M AXI GP0 SUPPORT NARROW BURST + 0 + + + + true + + + + + + PCW_M_AXI_GP0_THREAD_ID_WIDTH + PCW M AXI GP0 THREAD ID WIDTH + 12 + + + + true + + + + + + PCW_M_AXI_GP1_ID_WIDTH + PCW M AXI GP1 ID WIDTH + 12 + + + + false + + + + + + PCW_M_AXI_GP1_ENABLE_STATIC_REMAP + PCW M AXI GP1 ENABLE STATIC REMAP + 0 + + + + false + + + + + + PCW_M_AXI_GP1_SUPPORT_NARROW_BURST + PCW M AXI GP1 SUPPORT NARROW BURST + 0 + + + + false + + + + + + PCW_M_AXI_GP1_THREAD_ID_WIDTH + PCW M AXI GP1 THREAD ID WIDTH + 12 + + + + false + + + + + + PCW_S_AXI_GP0_ID_WIDTH + PCW S AXI GP0 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_GP1_ID_WIDTH + PCW S AXI GP1 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_ACP_ID_WIDTH + PCW S AXI ACP ID WIDTH + 3 + + + + true + + + + + + PCW_INCLUDE_ACP_TRANS_CHECK + PCW INCLUDE ACP TRANS CHECK + 0 + + + PCW_USE_DEFAULT_ACP_USER_VAL + PCW USE DEFAULT ACP USER VAL + 1 + + + + true + + + + + + PCW_S_AXI_ACP_ARUSER_VAL + PCW S AXI ACP ARUSER VAL + 31 + + + + true + + + + + + PCW_S_AXI_ACP_AWUSER_VAL + PCW S AXI ACP AWUSER VAL + 31 + + + + true + + + + + + PCW_S_AXI_HP0_ID_WIDTH + PCW S AXI HP0 ID WIDTH + 6 + + + + true + + + + + + PCW_S_AXI_HP0_DATA_WIDTH + PCW S AXI HP0 DATA WIDTH + 64 + + + + true + + + + + + PCW_S_AXI_HP1_ID_WIDTH + PCW S AXI HP1 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP1_DATA_WIDTH + PCW S AXI HP1 DATA WIDTH + 64 + + + + true + + + + + + PCW_S_AXI_HP2_ID_WIDTH + PCW S AXI HP2 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP2_DATA_WIDTH + PCW S AXI HP2 DATA WIDTH + 64 + + + + true + + + + + + PCW_S_AXI_HP3_ID_WIDTH + PCW S AXI HP3 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP3_DATA_WIDTH + PCW S AXI HP3 DATA WIDTH + 64 + + + + true + + + + + + PCW_NUM_F2P_INTR_INPUTS + PCW NUM F2P INTR INPUTS + 1 + + + + true + + + + + + PCW_EN_DDR + PCW EN DDR + 1 + + + PCW_EN_SMC + PCW EN SMC + 0 + + + PCW_EN_QSPI + PCW EN QSPI + 1 + + + PCW_EN_CAN0 + PCW EN CAN0 + 0 + + + PCW_EN_CAN1 + PCW EN CAN1 + 0 + + + PCW_EN_ENET0 + PCW EN ENET0 + 1 + + + PCW_EN_ENET1 + PCW EN ENET1 + 0 + + + PCW_EN_GPIO + PCW EN GPIO + 1 + + + PCW_EN_I2C0 + PCW EN I2C0 + 1 + + + PCW_EN_I2C1 + PCW EN I2C1 + 1 + + + PCW_EN_PJTAG + PCW EN PJTAG + 0 + + + PCW_EN_SDIO0 + PCW EN SDIO0 + 1 + + + PCW_EN_SDIO1 + PCW EN SDIO1 + 0 + + + PCW_EN_SPI0 + PCW EN SPI0 + 0 + + + PCW_EN_SPI1 + PCW EN SPI1 + 0 + + + PCW_EN_UART0 + PCW EN UART0 + 1 + + + PCW_EN_UART1 + PCW EN UART1 + 1 + + + PCW_EN_MODEM_UART0 + PCW EN MODEM UART0 + 0 + + + PCW_EN_MODEM_UART1 + PCW EN MODEM UART1 + 0 + + + PCW_EN_TTC0 + PCW EN TTC0 + 1 + + + PCW_EN_TTC1 + PCW EN TTC1 + 0 + + + PCW_EN_WDT + PCW EN WDT + 0 + + + PCW_EN_TRACE + PCW EN TRACE + 0 + + + PCW_EN_USB0 + PCW EN USB0 + 1 + + + PCW_EN_USB1 + PCW EN USB1 + 0 + + + PCW_DQ_WIDTH + PCW DQ WIDTH + 32 + + + PCW_DQS_WIDTH + PCW DQS WIDTH + 4 + + + PCW_DM_WIDTH + PCW DM WIDTH + 4 + + + PCW_MIO_PRIMITIVE + PCW MIO PRIMITIVE + 54 + + + PCW_EN_CLK0_PORT + PCW EN CLK0 PORT + 1 + + + + true + + + + + + PCW_EN_CLK1_PORT + PCW EN CLK1 PORT + 1 + + + + true + + + + + + PCW_EN_CLK2_PORT + PCW EN CLK2 PORT + 1 + + + + true + + + + + + PCW_EN_CLK3_PORT + PCW EN CLK3 PORT + 1 + + + + true + + + + + + PCW_EN_RST0_PORT + PCW EN RST0 PORT + Enables general purpose reset signal 0 for PL logic + 1 + + + + true + + + + + + PCW_EN_RST1_PORT + PCW EN RST1 PORT + Enables general purpose reset signal 1 for PL logic + 0 + + + + true + + + + + + PCW_EN_RST2_PORT + PCW EN RST2 PORT + Enables general purpose reset signal 2 for PL logic + 0 + + + + true + + + + + + PCW_EN_RST3_PORT + PCW EN RST3 PORT + Enables general purpose reset signal 3 for PL logic + 0 + + + + true + + + + + + PCW_EN_CLKTRIG0_PORT + PCW EN CLKTRIG0 PORT + Enables PL clock trigger signal 0 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_EN_CLKTRIG1_PORT + PCW EN CLKTRIG1 PORT + Enables PL clock trigger signal 1 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_EN_CLKTRIG2_PORT + PCW EN CLKTRIG2 PORT + Enables PL clock trigger signal 2 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_EN_CLKTRIG3_PORT + PCW EN CLKTRIG3 PORT + Enables PL clock trigger signal 3 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_P2F_DMAC_ABORT_INTR + PCW P2F DMAC ABORT INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC0_INTR + PCW P2F DMAC0 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC1_INTR + PCW P2F DMAC1 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC2_INTR + PCW P2F DMAC2 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC3_INTR + PCW P2F DMAC3 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC4_INTR + PCW P2F DMAC4 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC5_INTR + PCW P2F DMAC5 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC6_INTR + PCW P2F DMAC6 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC7_INTR + PCW P2F DMAC7 INTR + 0 + + + + false + + + + + + PCW_P2F_SMC_INTR + PCW P2F SMC INTR + 0 + + + + false + + + + + + PCW_P2F_QSPI_INTR + PCW P2F QSPI INTR + 0 + + + + true + + + + + + PCW_P2F_CTI_INTR + PCW P2F CTI INTR + 0 + + + + false + + + + + + PCW_P2F_GPIO_INTR + PCW P2F GPIO INTR + 0 + + + + true + + + + + + PCW_P2F_USB0_INTR + PCW P2F USB0 INTR + 0 + + + + true + + + + + + PCW_P2F_ENET0_INTR + PCW P2F ENET0 INTR + 0 + + + + true + + + + + + PCW_P2F_SDIO0_INTR + PCW P2F SDIO0 INTR + 0 + + + + true + + + + + + PCW_P2F_I2C0_INTR + PCW P2F I2C0 INTR + 0 + + + + true + + + + + + PCW_P2F_SPI0_INTR + PCW P2F SPI0 INTR + 0 + + + + false + + + + + + PCW_P2F_UART0_INTR + PCW P2F UART0 INTR + 0 + + + + true + + + + + + PCW_P2F_CAN0_INTR + PCW P2F CAN0 INTR + 0 + + + + false + + + + + + PCW_P2F_USB1_INTR + PCW P2F USB1 INTR + 0 + + + + false + + + + + + PCW_P2F_ENET1_INTR + PCW P2F ENET1 INTR + 0 + + + + false + + + + + + PCW_P2F_SDIO1_INTR + PCW P2F SDIO1 INTR + 0 + + + + false + + + + + + PCW_P2F_I2C1_INTR + PCW P2F I2C1 INTR + 0 + + + + true + + + + + + PCW_P2F_SPI1_INTR + PCW P2F SPI1 INTR + 0 + + + + false + + + + + + PCW_P2F_UART1_INTR + PCW P2F UART1 INTR + 0 + + + + true + + + + + + PCW_P2F_CAN1_INTR + PCW P2F CAN1 INTR + 0 + + + + false + + + + + + PCW_IRQ_F2P_INTR + PCW IRQ F2P INTR + 1 + + + + true + + + + + + PCW_IRQ_F2P_MODE + PCW IRQ F2P MODE + DIRECT + + + + true + + + + + + PCW_CORE0_FIQ_INTR + PCW CORE0 FIQ INTR + 0 + + + + true + + + + + + PCW_CORE0_IRQ_INTR + PCW CORE0 IRQ INTR + 0 + + + + true + + + + + + PCW_CORE1_FIQ_INTR + PCW CORE1 FIQ INTR + 0 + + + + true + + + + + + PCW_CORE1_IRQ_INTR + PCW CORE1 IRQ INTR + 0 + + + + true + + + + + + PCW_VALUE_SILVERSION + PCW VALUE SILVERSION + 3 + + + PCW_GP0_EN_MODIFIABLE_TXN + PCW GP0 EN MODIFIABLE TXN + 1 + + + PCW_GP1_EN_MODIFIABLE_TXN + PCW GP1 EN MODIFIABLE TXN + 1 + + + PCW_IMPORT_BOARD_PRESET + PCW IMPORT BOARD PRESET + None + + + PCW_PERIPHERAL_BOARD_PRESET + PCW PERIPHERAL BOARD PRESET + part0 + + + PCW_PRESET_BANK0_VOLTAGE + PCW PRESET BANK0 VOLTAGE + LVCMOS 3.3V + + + PCW_PRESET_BANK1_VOLTAGE + PCW PRESET BANK1 VOLTAGE + LVCMOS 1.8V + + + PCW_UIPARAM_DDR_ENABLE + PCW UIPARAM DDR ENABLE + 1 + + + PCW_UIPARAM_DDR_ADV_ENABLE + PCW UIPARAM DDR ADV ENABLE + 0 + + + PCW_UIPARAM_DDR_MEMORY_TYPE + PCW UIPARAM DDR MEMORY TYPE + DDR 3 (Low Voltage) + + + PCW_UIPARAM_DDR_ECC + PCW UIPARAM DDR ECC + Disabled + + + + false + + + + + + PCW_UIPARAM_DDR_BUS_WIDTH + PCW UIPARAM DDR BUS WIDTH + 32 Bit + + + PCW_UIPARAM_DDR_BL + PCW UIPARAM DDR BL + 8 + + + PCW_UIPARAM_DDR_HIGH_TEMP + PCW UIPARAM DDR HIGH TEMP + Normal (0-85) + + + PCW_UIPARAM_DDR_PARTNO + PCW UIPARAM DDR PARTNO + MT41K256M16 RE-125 + + + PCW_UIPARAM_DDR_DRAM_WIDTH + PCW UIPARAM DDR DRAM WIDTH + 16 Bits + + + + false + + + + + + PCW_UIPARAM_DDR_DEVICE_CAPACITY + PCW UIPARAM DDR DEVICE CAPACITY + 4096 MBits + + + + false + + + + + + PCW_UIPARAM_DDR_SPEED_BIN + PCW UIPARAM DDR SPEED BIN + DDR3_1066F + + + + false + + + + + + PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL + PCW UIPARAM DDR TRAIN WRITE LEVEL + 1 + + + PCW_UIPARAM_DDR_TRAIN_READ_GATE + PCW UIPARAM DDR TRAIN READ GATE + 1 + + + PCW_UIPARAM_DDR_TRAIN_DATA_EYE + PCW UIPARAM DDR TRAIN DATA EYE + 1 + + + PCW_UIPARAM_DDR_CLOCK_STOP_EN + PCW UIPARAM DDR CLOCK STOP EN + 0 + + + PCW_UIPARAM_DDR_USE_INTERNAL_VREF + PCW UIPARAM DDR USE INTERNAL VREF + 0 + + + PCW_DDR_PRIORITY_WRITEPORT_0 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_1 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_2 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_3 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_0 + PCW DDR PRIORITY READPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_1 + PCW DDR PRIORITY READPORT 1 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_2 + PCW DDR PRIORITY READPORT 2 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_3 + PCW DDR PRIORITY READPORT 3 + <Select> + + + + false + + + + + + PCW_DDR_PORT0_HPR_ENABLE + PCW DDR PORT0 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT1_HPR_ENABLE + PCW DDR PORT1 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT2_HPR_ENABLE + PCW DDR PORT2 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT3_HPR_ENABLE + PCW DDR PORT3 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_HPRLPR_QUEUE_PARTITION + PCW DDR HPRLPR QUEUE PARTITION + HPR(0)/LPR(32) + + + + false + + + + + + PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR LPR TO CRITICAL PRIORITY LEVEL + 2 + + + + false + + + + + + PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR HPR TO CRITICAL PRIORITY LEVEL + 15 + + + + false + + + + + + PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR WRITE TO CRITICAL PRIORITY LEVEL + 2 + + + + false + + + + + + PCW_NAND_PERIPHERAL_ENABLE + PCW NAND PERIPHERAL ENABLE + 0 + + + + false + + + + + + PCW_NAND_NAND_IO + PCW NAND NAND IO + <Select> + + + + false + + + + + + PCW_NAND_GRP_D8_ENABLE + 0 + + + + false + + + + + + PCW_NAND_GRP_D8_IO + PCW NAND GRP D8 IO + <Select> + + + + false + + + + + + PCW_NOR_PERIPHERAL_ENABLE + PCW NOR PERIPHERAL ENABLE + 0 + + + + false + + + + + + PCW_NOR_NOR_IO + PCW NOR NOR IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_A25_ENABLE + PCW NOR GRP A25 IO + 0 + + + + false + + + + + + PCW_NOR_GRP_A25_IO + PCW NOR GRP CS0 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_CS0_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_CS0_IO + PCW NOR GRP CS1 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS0_ENABLE + PCW NOR GRP SRAM CS0 ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS0_IO + PCW NOR GRP SRAM CS1 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_CS1_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_CS1_IO + PCW NOR GRP SRAM CS0 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS1_ENABLE + PCW NOR GRP SRAM CS1 ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS1_IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_INT_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_INT_IO + <Select> + + + + false + + + + + + PCW_QSPI_PERIPHERAL_ENABLE + PCW QSPI PERIPHERAL ENABLE + 1 + + + PCW_QSPI_QSPI_IO + PCW QSPI QSPI IO + MIO 1 .. 6 + + + PCW_QSPI_GRP_SINGLE_SS_ENABLE + PCW QSPI GRP SINGLE SS ENABLE + 1 + + + PCW_QSPI_GRP_SINGLE_SS_IO + PCW QSPI GRP SINGLE SS IO + MIO 1 .. 6 + + + PCW_QSPI_GRP_SS1_ENABLE + 0 + + + PCW_QSPI_GRP_SS1_IO + PCW QSPI GRP SS1 IO + <Select> + + + + false + + + + + + PCW_SINGLE_QSPI_DATA_MODE + Single QSPI Data Mode + x4 + + + PCW_DUAL_STACK_QSPI_DATA_MODE + Dual Stack QSPI Data Mode + <Select> + + + + false + + + + + + PCW_DUAL_PARALLEL_QSPI_DATA_MODE + Dual Parallel QSPI Data Mode + <Select> + + + + false + + + + + + PCW_QSPI_GRP_IO1_ENABLE + 0 + + + PCW_QSPI_GRP_IO1_IO + PCW QSPI GRP IO1 IO + <Select> + + + + false + + + + + + PCW_QSPI_GRP_FBCLK_ENABLE + 1 + + + PCW_QSPI_GRP_FBCLK_IO + PCW QSPI GRP FBCLK IO + MIO 8 + + + PCW_QSPI_INTERNAL_HIGHADDRESS + PCW QSPI INTERNAL HIGHADDRESS + 0xFCFFFFFF + + + PCW_ENET0_PERIPHERAL_ENABLE + PCW ENET0 PERIPHERAL ENABLE + 1 + + + PCW_ENET0_ENET0_IO + PCW ENET0 ENET0 IO + MIO 16 .. 27 + + + PCW_ENET0_GRP_MDIO_ENABLE + 1 + + + PCW_ENET0_GRP_MDIO_IO + PCW ENET0 GRP MDIO IO + MIO 52 .. 53 + + + PCW_ENET_RESET_ENABLE + 1 + + + PCW_ENET_RESET_SELECT + Share reset pin + + + PCW_ENET0_RESET_ENABLE + 0 + + + PCW_ENET0_RESET_IO + <Select> + + + + false + + + + + + PCW_ENET1_PERIPHERAL_ENABLE + PCW ENET1 PERIPHERAL ENABLE + 0 + + + PCW_ENET1_ENET1_IO + PCW ENET1 ENET1 IO + <Select> + + + + false + + + + + + PCW_ENET1_GRP_MDIO_ENABLE + 0 + + + + false + + + + + + PCW_ENET1_GRP_MDIO_IO + PCW ENET1 GRP MDIO IO + <Select> + + + + false + + + + + + PCW_ENET1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_ENET1_RESET_IO + <Select> + + + + false + + + + + + PCW_SD0_PERIPHERAL_ENABLE + PCW SD0 PERIPHERAL ENABLE + 1 + + + PCW_SD0_SD0_IO + PCW SD0 SD0 IO + MIO 40 .. 45 + + + PCW_SD0_GRP_CD_ENABLE + 1 + + + PCW_SD0_GRP_CD_IO + PCW SD0 GRP CD IO + MIO 47 + + + PCW_SD0_GRP_WP_ENABLE + 1 + + + PCW_SD0_GRP_WP_IO + PCW SD0 GRP WP IO + EMIO + + + PCW_SD0_GRP_POW_ENABLE + 0 + + + PCW_SD0_GRP_POW_IO + PCW SD0 GRP POW IO + <Select> + + + + false + + + + + + PCW_SD1_PERIPHERAL_ENABLE + PCW SD1 PERIPHERAL ENABLE + 0 + + + PCW_SD1_SD1_IO + PCW SD1 SD1 IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_CD_ENABLE + 0 + + + + false + + + + + + PCW_SD1_GRP_CD_IO + PCW SD1 GRP CD IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_WP_ENABLE + 0 + + + + false + + + + + + PCW_SD1_GRP_WP_IO + PCW SD1 GRP WP IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_POW_ENABLE + 0 + + + + false + + + + + + PCW_SD1_GRP_POW_IO + PCW SD1 GRP POW IO + <Select> + + + + false + + + + + + PCW_UART0_PERIPHERAL_ENABLE + PCW UART0 PERIPHERAL ENABLE + 1 + + + PCW_UART0_UART0_IO + PCW UART0 UART0 IO + MIO 10 .. 11 + + + PCW_UART0_GRP_FULL_ENABLE + 0 + + + PCW_UART0_GRP_FULL_IO + <Select> + + + + false + + + + + + PCW_UART1_PERIPHERAL_ENABLE + PCW UART1 PERIPHERAL ENABLE + 1 + + + PCW_UART1_UART1_IO + PCW UART1 UART1 IO + MIO 48 .. 49 + + + PCW_UART1_GRP_FULL_ENABLE + 0 + + + PCW_UART1_GRP_FULL_IO + <Select> + + + + false + + + + + + PCW_SPI0_PERIPHERAL_ENABLE + PCW SPI0 PERIPHERAL ENABLE + 0 + + + PCW_SPI0_SPI0_IO + PCW SPI0 SPI0 IO + <Select> + + + + false + + + + + + PCW_SPI0_GRP_SS0_ENABLE + 0 + + + + false + + + + + + PCW_SPI0_GRP_SS0_IO + PCW SPI0 GRP SS0 IO + <Select> + + + + false + + + + + + PCW_SPI0_GRP_SS1_ENABLE + 0 + + + + false + + + + + + PCW_SPI0_GRP_SS1_IO + PCW SPI0 GRP SS1 IO + <Select> + + + + false + + + + + + PCW_SPI0_GRP_SS2_ENABLE + 0 + + + + false + + + + + + PCW_SPI0_GRP_SS2_IO + PCW SPI0 GRP SS2 IO + <Select> + + + + false + + + + + + PCW_SPI1_PERIPHERAL_ENABLE + PCW SPI1 PERIPHERAL ENABLE + 0 + + + PCW_SPI1_SPI1_IO + PCW SPI1 SPI1 IO + <Select> + + + + false + + + + + + PCW_SPI1_GRP_SS0_ENABLE + 0 + + + + false + + + + + + PCW_SPI1_GRP_SS0_IO + PCW SPI1 GRP SS0 IO + <Select> + + + + false + + + + + + PCW_SPI1_GRP_SS1_ENABLE + 0 + + + + false + + + + + + PCW_SPI1_GRP_SS1_IO + PCW SPI1 GRP SS1 IO + <Select> + + + + false + + + + + + PCW_SPI1_GRP_SS2_ENABLE + 0 + + + + false + + + + + + PCW_SPI1_GRP_SS2_IO + PCW SPI1 GRP SS2 IO + <Select> + + + + false + + + + + + PCW_CAN0_PERIPHERAL_ENABLE + PCW CAN0 PERIPHERAL ENABLE + 0 + + + PCW_CAN0_CAN0_IO + PCW CAN0 CAN0 IO + <Select> + + + + false + + + + + + PCW_CAN0_GRP_CLK_ENABLE + 0 + + + + false + + + + + + PCW_CAN0_GRP_CLK_IO + PCW CAN0 GRP CLK IO + <Select> + + + + false + + + + + + PCW_CAN1_PERIPHERAL_ENABLE + PCW CAN1 PERIPHERAL ENABLE + 0 + + + PCW_CAN1_CAN1_IO + PCW CAN1 CAN1 IO + <Select> + + + + false + + + + + + PCW_CAN1_GRP_CLK_ENABLE + 0 + + + + false + + + + + + PCW_CAN1_GRP_CLK_IO + PCW CAN1 GRP CLK IO + <Select> + + + + false + + + + + + PCW_TRACE_PERIPHERAL_ENABLE + PCW TRACE PERIPHERAL ENABLE + 0 + + + PCW_TRACE_TRACE_IO + PCW TRACE TRACE IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_2BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_2BIT_IO + PCW TRACE GRP 2BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_4BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_4BIT_IO + PCW TRACE GRP 4BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_8BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_8BIT_IO + PCW TRACE GRP 8BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_16BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_16BIT_IO + PCW TRACE GRP 16BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_32BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_32BIT_IO + PCW TRACE GRP 32BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_INTERNAL_WIDTH + PCW TRACE INTERNAL WIDTH + 2 + + + PCW_WDT_PERIPHERAL_ENABLE + PCW WDT PERIPHERAL ENABLE + 0 + + + PCW_WDT_WDT_IO + PCW WDT WDT IO + <Select> + + + + false + + + + + + PCW_TTC0_PERIPHERAL_ENABLE + PCW TTC0 PERIPHERAL ENABLE + 1 + + + PCW_TTC0_TTC0_IO + PCW TTC0 TTC0 IO + EMIO + + + PCW_TTC1_PERIPHERAL_ENABLE + PCW TTC1 PERIPHERAL ENABLE + 0 + + + PCW_TTC1_TTC1_IO + PCW TTC1 TTC1 IO + <Select> + + + + false + + + + + + PCW_PJTAG_PERIPHERAL_ENABLE + PCW PJTAG PERIPHERAL ENABLE + 0 + + + PCW_PJTAG_PJTAG_IO + PCW PJTAG PJTAG IO + <Select> + + + + false + + + + + + PCW_USB0_PERIPHERAL_ENABLE + PCW USB0 PERIPHERAL ENABLE + 1 + + + PCW_USB0_USB0_IO + PCW USB0 USB0 IO + MIO 28 .. 39 + + + PCW_USB_RESET_ENABLE + 1 + + + PCW_USB_RESET_SELECT + Share reset pin + + + PCW_USB0_RESET_ENABLE + 1 + + + PCW_USB0_RESET_IO + MIO 46 + + + PCW_USB1_PERIPHERAL_ENABLE + PCW USB1 PERIPHERAL ENABLE + 0 + + + PCW_USB1_USB1_IO + PCW USB1 USB1 IO + <Select> + + + + false + + + + + + PCW_USB1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_USB1_RESET_IO + <Select> + + + + false + + + + + + PCW_I2C0_PERIPHERAL_ENABLE + PCW I2C0 PERIPHERAL ENABLE + 1 + + + PCW_I2C0_I2C0_IO + PCW I2C0 I2C0 IO + MIO 14 .. 15 + + + PCW_I2C0_GRP_INT_ENABLE + 0 + + + PCW_I2C0_GRP_INT_IO + PCW I2C0 GRP INT IO + <Select> + + + + false + + + + + + PCW_I2C0_RESET_ENABLE + 0 + + + PCW_I2C0_RESET_IO + <Select> + + + + false + + + + + + PCW_I2C1_PERIPHERAL_ENABLE + PCW I2C1 PERIPHERAL ENABLE + 1 + + + PCW_I2C1_I2C1_IO + PCW I2C1 I2C1 IO + MIO 12 .. 13 + + + PCW_I2C1_GRP_INT_ENABLE + 0 + + + PCW_I2C1_GRP_INT_IO + PCW I2C1 GRP INT IO + <Select> + + + + false + + + + + + PCW_I2C_RESET_ENABLE + 1 + + + PCW_I2C_RESET_SELECT + Share reset pin + + + PCW_I2C1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_I2C1_RESET_IO + <Select> + + + + false + + + + + + PCW_GPIO_PERIPHERAL_ENABLE + PCW GPIO PERIPHERAL ENABLE + 0 + + + PCW_GPIO_MIO_GPIO_ENABLE + 1 + + + PCW_GPIO_MIO_GPIO_IO + PCW GPIO MIO GPIO IO + MIO + + + PCW_GPIO_EMIO_GPIO_ENABLE + PCW GPIO EMIO GPIO ENABLE + 0 + + + PCW_GPIO_EMIO_GPIO_IO + PCW GPIO EMIO GPIO IO + <Select> + + + + false + + + + + + PCW_APU_CLK_RATIO_ENABLE + PCW APU CLK RATIO ENABLE + 6:2:1 + + + PCW_ENET0_PERIPHERAL_FREQMHZ + PCW ENET0 PERIPHERAL FREQMHZ + 1000 Mbps + + + PCW_ENET1_PERIPHERAL_FREQMHZ + PCW ENET1 PERIPHERAL FREQMHZ + 1000 Mbps + + + + false + + + + + + PCW_CPU_PERIPHERAL_CLKSRC + PCW CPU PERIPHERAL CLKSRC + ARM PLL + + + PCW_DDR_PERIPHERAL_CLKSRC + PCW DDR PERIPHERAL CLKSRC + DDR PLL + + + PCW_SMC_PERIPHERAL_CLKSRC + PCW SMC PERIPHERAL CLKSRC + IO PLL + + + PCW_QSPI_PERIPHERAL_CLKSRC + PCW QSPI PERIPHERAL CLKSRC + IO PLL + + + PCW_SDIO_PERIPHERAL_CLKSRC + PCW SDIO PERIPHERAL CLKSRC + IO PLL + + + PCW_UART_PERIPHERAL_CLKSRC + PCW UART PERIPHERAL CLKSRC + IO PLL + + + PCW_SPI_PERIPHERAL_CLKSRC + PCW SPI PERIPHERAL CLKSRC + IO PLL + + + PCW_CAN_PERIPHERAL_CLKSRC + PCW CAN PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK0_PERIPHERAL_CLKSRC + PCW FCLK0 PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK1_PERIPHERAL_CLKSRC + PCW FCLK1 PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK2_PERIPHERAL_CLKSRC + PCW FCLK2 PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK3_PERIPHERAL_CLKSRC + PCW FCLK3 PERIPHERAL CLKSRC + IO PLL + + + PCW_ENET0_PERIPHERAL_CLKSRC + PCW ENET0 PERIPHERAL CLKSRC + IO PLL + + + PCW_ENET1_PERIPHERAL_CLKSRC + PCW ENET1 PERIPHERAL CLKSRC + IO PLL + + + PCW_CAN0_PERIPHERAL_CLKSRC + PCW CAN0 PERIPHERAL CLKSRC + External + + + PCW_CAN1_PERIPHERAL_CLKSRC + PCW CAN1 PERIPHERAL CLKSRC + External + + + PCW_TPIU_PERIPHERAL_CLKSRC + PCW TPIU PERIPHERAL CLKSRC + External + + + PCW_TTC0_CLK0_PERIPHERAL_CLKSRC + PCW TTC0 CLK0 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC0_CLK1_PERIPHERAL_CLKSRC + PCW TTC0 CLK1 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC0_CLK2_PERIPHERAL_CLKSRC + PCW TTC0 CLK2 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC1_CLK0_PERIPHERAL_CLKSRC + PCW TTC1 CLK0 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC1_CLK1_PERIPHERAL_CLKSRC + PCW TTC1 CLK1 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC1_CLK2_PERIPHERAL_CLKSRC + PCW TTC1 CLK2 PERIPHERAL CLKSRC + CPU_1X + + + PCW_WDT_PERIPHERAL_CLKSRC + PCW WDT PERIPHERAL CLKSRC + CPU_1X + + + PCW_DCI_PERIPHERAL_CLKSRC + PCW DCI PERIPHERAL CLKSRC + DDR PLL + + + PCW_PCAP_PERIPHERAL_CLKSRC + PCW PCAP PERIPHERAL CLKSRC + IO PLL + + + PCW_USB_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + PCW_ENET_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + PCW_I2C_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + PCW_MIO_0_PULLUP + PCW MIO 0 PULLUP + enabled + + + PCW_MIO_0_IOTYPE + PCW MIO 0 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_0_DIRECTION + PCW MIO 0 DIRECTION + inout + + + + false + + + + + + PCW_MIO_0_SLEW + PCW MIO 0 SLEW + slow + + + PCW_MIO_1_PULLUP + PCW MIO 1 PULLUP + enabled + + + PCW_MIO_1_IOTYPE + PCW MIO 1 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_1_DIRECTION + PCW MIO 1 DIRECTION + out + + + + false + + + + + + PCW_MIO_1_SLEW + PCW MIO 1 SLEW + slow + + + PCW_MIO_2_PULLUP + PCW MIO 2 PULLUP + disabled + + + + false + + + + + + PCW_MIO_2_IOTYPE + PCW MIO 2 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_2_DIRECTION + PCW MIO 2 DIRECTION + inout + + + + false + + + + + + PCW_MIO_2_SLEW + PCW MIO 2 SLEW + slow + + + PCW_MIO_3_PULLUP + PCW MIO 3 PULLUP + disabled + + + + false + + + + + + PCW_MIO_3_IOTYPE + PCW MIO 3 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_3_DIRECTION + PCW MIO 3 DIRECTION + inout + + + + false + + + + + + PCW_MIO_3_SLEW + PCW MIO 3 SLEW + slow + + + PCW_MIO_4_PULLUP + PCW MIO 4 PULLUP + disabled + + + + false + + + + + + PCW_MIO_4_IOTYPE + PCW MIO 4 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_4_DIRECTION + PCW MIO 4 DIRECTION + inout + + + + false + + + + + + PCW_MIO_4_SLEW + PCW MIO 4 SLEW + slow + + + PCW_MIO_5_PULLUP + PCW MIO 5 PULLUP + disabled + + + + false + + + + + + PCW_MIO_5_IOTYPE + PCW MIO 5 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_5_DIRECTION + PCW MIO 5 DIRECTION + inout + + + + false + + + + + + PCW_MIO_5_SLEW + PCW MIO 5 SLEW + slow + + + PCW_MIO_6_PULLUP + PCW MIO 6 PULLUP + disabled + + + + false + + + + + + PCW_MIO_6_IOTYPE + PCW MIO 6 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_6_DIRECTION + PCW MIO 6 DIRECTION + out + + + + false + + + + + + PCW_MIO_6_SLEW + PCW MIO 6 SLEW + slow + + + PCW_MIO_7_PULLUP + PCW MIO 7 PULLUP + disabled + + + + false + + + + + + PCW_MIO_7_IOTYPE + PCW MIO 7 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_7_DIRECTION + PCW MIO 7 DIRECTION + out + + + + false + + + + + + PCW_MIO_7_SLEW + PCW MIO 7 SLEW + slow + + + PCW_MIO_8_PULLUP + PCW MIO 8 PULLUP + disabled + + + + false + + + + + + PCW_MIO_8_IOTYPE + PCW MIO 8 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_8_DIRECTION + PCW MIO 8 DIRECTION + out + + + + false + + + + + + PCW_MIO_8_SLEW + PCW MIO 8 SLEW + slow + + + PCW_MIO_9_PULLUP + PCW MIO 9 PULLUP + enabled + + + PCW_MIO_9_IOTYPE + PCW MIO 9 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_9_DIRECTION + PCW MIO 9 DIRECTION + inout + + + + false + + + + + + PCW_MIO_9_SLEW + PCW MIO 9 SLEW + slow + + + PCW_MIO_10_PULLUP + PCW MIO 10 PULLUP + enabled + + + PCW_MIO_10_IOTYPE + PCW MIO 10 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_10_DIRECTION + PCW MIO 10 DIRECTION + in + + + + false + + + + + + PCW_MIO_10_SLEW + PCW MIO 10 SLEW + slow + + + PCW_MIO_11_PULLUP + PCW MIO 11 PULLUP + enabled + + + PCW_MIO_11_IOTYPE + PCW MIO 11 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_11_DIRECTION + PCW MIO 11 DIRECTION + out + + + + false + + + + + + PCW_MIO_11_SLEW + PCW MIO 11 SLEW + slow + + + PCW_MIO_12_PULLUP + PCW MIO 12 PULLUP + enabled + + + PCW_MIO_12_IOTYPE + PCW MIO 12 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_12_DIRECTION + PCW MIO 12 DIRECTION + inout + + + + false + + + + + + PCW_MIO_12_SLEW + PCW MIO 12 SLEW + slow + + + PCW_MIO_13_PULLUP + PCW MIO 13 PULLUP + enabled + + + PCW_MIO_13_IOTYPE + PCW MIO 13 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_13_DIRECTION + PCW MIO 13 DIRECTION + inout + + + + false + + + + + + PCW_MIO_13_SLEW + PCW MIO 13 SLEW + slow + + + PCW_MIO_14_PULLUP + PCW MIO 14 PULLUP + enabled + + + PCW_MIO_14_IOTYPE + PCW MIO 14 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_14_DIRECTION + PCW MIO 14 DIRECTION + inout + + + + false + + + + + + PCW_MIO_14_SLEW + PCW MIO 14 SLEW + slow + + + PCW_MIO_15_PULLUP + PCW MIO 15 PULLUP + enabled + + + PCW_MIO_15_IOTYPE + PCW MIO 15 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_15_DIRECTION + PCW MIO 15 DIRECTION + inout + + + + false + + + + + + PCW_MIO_15_SLEW + PCW MIO 15 SLEW + slow + + + PCW_MIO_16_PULLUP + PCW MIO 16 PULLUP + enabled + + + PCW_MIO_16_IOTYPE + PCW MIO 16 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_16_DIRECTION + PCW MIO 16 DIRECTION + out + + + + false + + + + + + PCW_MIO_16_SLEW + PCW MIO 16 SLEW + fast + + + PCW_MIO_17_PULLUP + PCW MIO 17 PULLUP + enabled + + + PCW_MIO_17_IOTYPE + PCW MIO 17 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_17_DIRECTION + PCW MIO 17 DIRECTION + out + + + + false + + + + + + PCW_MIO_17_SLEW + PCW MIO 17 SLEW + fast + + + PCW_MIO_18_PULLUP + PCW MIO 18 PULLUP + enabled + + + PCW_MIO_18_IOTYPE + PCW MIO 18 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_18_DIRECTION + PCW MIO 18 DIRECTION + out + + + + false + + + + + + PCW_MIO_18_SLEW + PCW MIO 18 SLEW + fast + + + PCW_MIO_19_PULLUP + PCW MIO 19 PULLUP + enabled + + + PCW_MIO_19_IOTYPE + PCW MIO 19 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_19_DIRECTION + PCW MIO 19 DIRECTION + out + + + + false + + + + + + PCW_MIO_19_SLEW + PCW MIO 19 SLEW + fast + + + PCW_MIO_20_PULLUP + PCW MIO 20 PULLUP + enabled + + + PCW_MIO_20_IOTYPE + PCW MIO 20 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_20_DIRECTION + PCW MIO 20 DIRECTION + out + + + + false + + + + + + PCW_MIO_20_SLEW + PCW MIO 20 SLEW + fast + + + PCW_MIO_21_PULLUP + PCW MIO 21 PULLUP + enabled + + + PCW_MIO_21_IOTYPE + PCW MIO 21 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_21_DIRECTION + PCW MIO 21 DIRECTION + out + + + + false + + + + + + PCW_MIO_21_SLEW + PCW MIO 21 SLEW + fast + + + PCW_MIO_22_PULLUP + PCW MIO 22 PULLUP + enabled + + + PCW_MIO_22_IOTYPE + PCW MIO 22 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_22_DIRECTION + PCW MIO 22 DIRECTION + in + + + + false + + + + + + PCW_MIO_22_SLEW + PCW MIO 22 SLEW + fast + + + PCW_MIO_23_PULLUP + PCW MIO 23 PULLUP + enabled + + + PCW_MIO_23_IOTYPE + PCW MIO 23 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_23_DIRECTION + PCW MIO 23 DIRECTION + in + + + + false + + + + + + PCW_MIO_23_SLEW + PCW MIO 23 SLEW + fast + + + PCW_MIO_24_PULLUP + PCW MIO 24 PULLUP + enabled + + + PCW_MIO_24_IOTYPE + PCW MIO 24 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_24_DIRECTION + PCW MIO 24 DIRECTION + in + + + + false + + + + + + PCW_MIO_24_SLEW + PCW MIO 24 SLEW + fast + + + PCW_MIO_25_PULLUP + PCW MIO 25 PULLUP + enabled + + + PCW_MIO_25_IOTYPE + PCW MIO 25 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_25_DIRECTION + PCW MIO 25 DIRECTION + in + + + + false + + + + + + PCW_MIO_25_SLEW + PCW MIO 25 SLEW + fast + + + PCW_MIO_26_PULLUP + PCW MIO 26 PULLUP + enabled + + + PCW_MIO_26_IOTYPE + PCW MIO 26 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_26_DIRECTION + PCW MIO 26 DIRECTION + in + + + + false + + + + + + PCW_MIO_26_SLEW + PCW MIO 26 SLEW + fast + + + PCW_MIO_27_PULLUP + PCW MIO 27 PULLUP + enabled + + + PCW_MIO_27_IOTYPE + PCW MIO 27 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_27_DIRECTION + PCW MIO 27 DIRECTION + in + + + + false + + + + + + PCW_MIO_27_SLEW + PCW MIO 27 SLEW + fast + + + PCW_MIO_28_PULLUP + PCW MIO 28 PULLUP + enabled + + + PCW_MIO_28_IOTYPE + PCW MIO 28 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_28_DIRECTION + PCW MIO 28 DIRECTION + inout + + + + false + + + + + + PCW_MIO_28_SLEW + PCW MIO 28 SLEW + fast + + + PCW_MIO_29_PULLUP + PCW MIO 29 PULLUP + enabled + + + PCW_MIO_29_IOTYPE + PCW MIO 29 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_29_DIRECTION + PCW MIO 29 DIRECTION + in + + + + false + + + + + + PCW_MIO_29_SLEW + PCW MIO 29 SLEW + fast + + + PCW_MIO_30_PULLUP + PCW MIO 30 PULLUP + enabled + + + PCW_MIO_30_IOTYPE + PCW MIO 30 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_30_DIRECTION + PCW MIO 30 DIRECTION + out + + + + false + + + + + + PCW_MIO_30_SLEW + PCW MIO 30 SLEW + fast + + + PCW_MIO_31_PULLUP + PCW MIO 31 PULLUP + enabled + + + PCW_MIO_31_IOTYPE + PCW MIO 31 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_31_DIRECTION + PCW MIO 31 DIRECTION + in + + + + false + + + + + + PCW_MIO_31_SLEW + PCW MIO 31 SLEW + fast + + + PCW_MIO_32_PULLUP + PCW MIO 32 PULLUP + enabled + + + PCW_MIO_32_IOTYPE + PCW MIO 32 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_32_DIRECTION + PCW MIO 32 DIRECTION + inout + + + + false + + + + + + PCW_MIO_32_SLEW + PCW MIO 32 SLEW + fast + + + PCW_MIO_33_PULLUP + PCW MIO 33 PULLUP + enabled + + + PCW_MIO_33_IOTYPE + PCW MIO 33 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_33_DIRECTION + PCW MIO 33 DIRECTION + inout + + + + false + + + + + + PCW_MIO_33_SLEW + PCW MIO 33 SLEW + fast + + + PCW_MIO_34_PULLUP + PCW MIO 34 PULLUP + enabled + + + PCW_MIO_34_IOTYPE + PCW MIO 34 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_34_DIRECTION + PCW MIO 34 DIRECTION + inout + + + + false + + + + + + PCW_MIO_34_SLEW + PCW MIO 34 SLEW + fast + + + PCW_MIO_35_PULLUP + PCW MIO 35 PULLUP + enabled + + + PCW_MIO_35_IOTYPE + PCW MIO 35 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_35_DIRECTION + PCW MIO 35 DIRECTION + inout + + + + false + + + + + + PCW_MIO_35_SLEW + PCW MIO 35 SLEW + fast + + + PCW_MIO_36_PULLUP + PCW MIO 36 PULLUP + enabled + + + PCW_MIO_36_IOTYPE + PCW MIO 36 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_36_DIRECTION + PCW MIO 36 DIRECTION + in + + + + false + + + + + + PCW_MIO_36_SLEW + PCW MIO 36 SLEW + fast + + + PCW_MIO_37_PULLUP + PCW MIO 37 PULLUP + enabled + + + PCW_MIO_37_IOTYPE + PCW MIO 37 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_37_DIRECTION + PCW MIO 37 DIRECTION + inout + + + + false + + + + + + PCW_MIO_37_SLEW + PCW MIO 37 SLEW + fast + + + PCW_MIO_38_PULLUP + PCW MIO 38 PULLUP + enabled + + + PCW_MIO_38_IOTYPE + PCW MIO 38 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_38_DIRECTION + PCW MIO 38 DIRECTION + inout + + + + false + + + + + + PCW_MIO_38_SLEW + PCW MIO 38 SLEW + fast + + + PCW_MIO_39_PULLUP + PCW MIO 39 PULLUP + enabled + + + PCW_MIO_39_IOTYPE + PCW MIO 39 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_39_DIRECTION + PCW MIO 39 DIRECTION + inout + + + + false + + + + + + PCW_MIO_39_SLEW + PCW MIO 39 SLEW + fast + + + PCW_MIO_40_PULLUP + PCW MIO 40 PULLUP + enabled + + + PCW_MIO_40_IOTYPE + PCW MIO 40 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_40_DIRECTION + PCW MIO 40 DIRECTION + inout + + + + false + + + + + + PCW_MIO_40_SLEW + PCW MIO 40 SLEW + slow + + + PCW_MIO_41_PULLUP + PCW MIO 41 PULLUP + enabled + + + PCW_MIO_41_IOTYPE + PCW MIO 41 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_41_DIRECTION + PCW MIO 41 DIRECTION + inout + + + + false + + + + + + PCW_MIO_41_SLEW + PCW MIO 41 SLEW + slow + + + PCW_MIO_42_PULLUP + PCW MIO 42 PULLUP + enabled + + + PCW_MIO_42_IOTYPE + PCW MIO 42 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_42_DIRECTION + PCW MIO 42 DIRECTION + inout + + + + false + + + + + + PCW_MIO_42_SLEW + PCW MIO 42 SLEW + slow + + + PCW_MIO_43_PULLUP + PCW MIO 43 PULLUP + enabled + + + PCW_MIO_43_IOTYPE + PCW MIO 43 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_43_DIRECTION + PCW MIO 43 DIRECTION + inout + + + + false + + + + + + PCW_MIO_43_SLEW + PCW MIO 43 SLEW + slow + + + PCW_MIO_44_PULLUP + PCW MIO 44 PULLUP + enabled + + + PCW_MIO_44_IOTYPE + PCW MIO 44 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_44_DIRECTION + PCW MIO 44 DIRECTION + inout + + + + false + + + + + + PCW_MIO_44_SLEW + PCW MIO 44 SLEW + slow + + + PCW_MIO_45_PULLUP + PCW MIO 45 PULLUP + enabled + + + PCW_MIO_45_IOTYPE + PCW MIO 45 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_45_DIRECTION + PCW MIO 45 DIRECTION + inout + + + + false + + + + + + PCW_MIO_45_SLEW + PCW MIO 45 SLEW + slow + + + PCW_MIO_46_PULLUP + PCW MIO 46 PULLUP + enabled + + + PCW_MIO_46_IOTYPE + PCW MIO 46 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_46_DIRECTION + PCW MIO 46 DIRECTION + out + + + + false + + + + + + PCW_MIO_46_SLEW + PCW MIO 46 SLEW + slow + + + PCW_MIO_47_PULLUP + PCW MIO 47 PULLUP + enabled + + + PCW_MIO_47_IOTYPE + PCW MIO 47 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_47_DIRECTION + PCW MIO 47 DIRECTION + in + + + + false + + + + + + PCW_MIO_47_SLEW + PCW MIO 47 SLEW + slow + + + PCW_MIO_48_PULLUP + PCW MIO 48 PULLUP + enabled + + + PCW_MIO_48_IOTYPE + PCW MIO 48 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_48_DIRECTION + PCW MIO 48 DIRECTION + out + + + + false + + + + + + PCW_MIO_48_SLEW + PCW MIO 48 SLEW + slow + + + PCW_MIO_49_PULLUP + PCW MIO 49 PULLUP + enabled + + + PCW_MIO_49_IOTYPE + PCW MIO 49 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_49_DIRECTION + PCW MIO 49 DIRECTION + in + + + + false + + + + + + PCW_MIO_49_SLEW + PCW MIO 49 SLEW + slow + + + PCW_MIO_50_PULLUP + PCW MIO 50 PULLUP + enabled + + + PCW_MIO_50_IOTYPE + PCW MIO 50 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_50_DIRECTION + PCW MIO 50 DIRECTION + inout + + + + false + + + + + + PCW_MIO_50_SLEW + PCW MIO 50 SLEW + slow + + + PCW_MIO_51_PULLUP + PCW MIO 51 PULLUP + enabled + + + PCW_MIO_51_IOTYPE + PCW MIO 51 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_51_DIRECTION + PCW MIO 51 DIRECTION + inout + + + + false + + + + + + PCW_MIO_51_SLEW + PCW MIO 51 SLEW + slow + + + PCW_MIO_52_PULLUP + PCW MIO 52 PULLUP + enabled + + + PCW_MIO_52_IOTYPE + PCW MIO 52 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_52_DIRECTION + PCW MIO 52 DIRECTION + out + + + + false + + + + + + PCW_MIO_52_SLEW + PCW MIO 52 SLEW + slow + + + PCW_MIO_53_PULLUP + PCW MIO 53 PULLUP + enabled + + + PCW_MIO_53_IOTYPE + PCW MIO 53 IOTYPE + LVCMOS 1.8V + + + PCW_MIO_53_DIRECTION + PCW MIO 53 DIRECTION + inout + + + + false + + + + + + PCW_MIO_53_SLEW + PCW MIO 53 SLEW + slow + + + preset + preset + None + + + PCW_UIPARAM_GENERATE_SUMMARY + PCW UIPARAM GENERATE SUMMARY + NA + + + PCW_MIO_TREE_PERIPHERALS + PCW MIO TREE PERIPHERALS + GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#UART 0#UART 0#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0 + + + PCW_MIO_TREE_SIGNALS + PCW MIO TREE SIGNALS + gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#rx#tx#scl#sda#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio + + + PCW_PS7_SI_REV + PCW PS7 SI REV + PRODUCTION + + + PCW_FPGA_FCLK0_ENABLE + PCW FPGA FCLK0 ENABLE + 1 + + + + true + + + + + + PCW_FPGA_FCLK1_ENABLE + PCW FPGA FCLK1 ENABLE + 1 + + + + true + + + + + + PCW_FPGA_FCLK2_ENABLE + PCW FPGA FCLK2 ENABLE + 1 + + + + true + + + + + + PCW_FPGA_FCLK3_ENABLE + PCW FPGA FCLK3 ENABLE + 1 + + + + true + + + + + + PCW_NOR_SRAM_CS0_T_TR + PCW NOR SRAM CS0 T TR + 1 + + + PCW_NOR_SRAM_CS0_T_PC + PCW NOR SRAM CS0 T PC + 1 + + + PCW_NOR_SRAM_CS0_T_WP + PCW NOR SRAM CS0 T WP + 1 + + + PCW_NOR_SRAM_CS0_T_CEOE + PCW NOR SRAM CS0 T CEOE + 1 + + + PCW_NOR_SRAM_CS0_T_WC + PCW NOR SRAM CS0 T WC + 11 + + + PCW_NOR_SRAM_CS0_T_RC + PCW NOR SRAM CS0 T RC + 11 + + + PCW_NOR_SRAM_CS0_WE_TIME + PCW NOR SRAM CS0 WE TIME + 0 + + + PCW_NOR_SRAM_CS1_T_TR + PCW NOR SRAM CS1 T TR + 1 + + + PCW_NOR_SRAM_CS1_T_PC + PCW NOR SRAM CS1 T PC + 1 + + + PCW_NOR_SRAM_CS1_T_WP + PCW NOR SRAM CS1 T WP + 1 + + + PCW_NOR_SRAM_CS1_T_CEOE + PCW NOR SRAM CS1 T CEOE + 1 + + + PCW_NOR_SRAM_CS1_T_WC + PCW NOR SRAM CS1 T WC + 11 + + + PCW_NOR_SRAM_CS1_T_RC + PCW NOR SRAM CS1 T RC + 11 + + + PCW_NOR_SRAM_CS1_WE_TIME + PCW NOR SRAM CS1 WE TIME + 0 + + + PCW_NOR_CS0_T_TR + PCW NOR CS0 T TR + 1 + + + PCW_NOR_CS0_T_PC + PCW NOR CS0 T PC + 1 + + + PCW_NOR_CS0_T_WP + PCW NOR CS0 T WP + 1 + + + PCW_NOR_CS0_T_CEOE + PCW NOR CS0 T CEOE + 1 + + + PCW_NOR_CS0_T_WC + PCW NOR CS0 T WC + 11 + + + PCW_NOR_CS0_T_RC + PCW NOR CS0 T RC + 11 + + + PCW_NOR_CS0_WE_TIME + PCW NOR CS0 WE TIME + 0 + + + PCW_NOR_CS1_T_TR + PCW NOR CS1 T TR + 1 + + + PCW_NOR_CS1_T_PC + PCW NOR CS1 T PC + 1 + + + PCW_NOR_CS1_T_WP + PCW NOR CS1 T WP + 1 + + + PCW_NOR_CS1_T_CEOE + PCW NOR CS1 T CEOE + 1 + + + PCW_NOR_CS1_T_WC + PCW NOR CS1 T WC + 11 + + + PCW_NOR_CS1_T_RC + PCW NOR CS1 T RC + 11 + + + PCW_NOR_CS1_WE_TIME + PCW NOR CS1 WE TIME + 0 + + + PCW_NAND_CYCLES_T_RR + PCW NAND CYCLES T RR + 1 + + + PCW_NAND_CYCLES_T_AR + PCW NAND CYCLES T AR + 1 + + + PCW_NAND_CYCLES_T_CLR + PCW NAND CYCLES T CLR + 1 + + + PCW_NAND_CYCLES_T_WP + PCW NAND CYCLES T WP + 1 + + + PCW_NAND_CYCLES_T_REA + PCW NAND CYCLES T REA + 1 + + + PCW_NAND_CYCLES_T_WC + PCW NAND CYCLES T WC + 11 + + + PCW_NAND_CYCLES_T_RC + PCW NAND CYCLES T RC + 11 + + + PCW_SMC_CYCLE_T0 + PCW SMC CYCLE T0 + NA + + + PCW_SMC_CYCLE_T1 + PCW SMC CYCLE T1 + NA + + + PCW_SMC_CYCLE_T2 + PCW SMC CYCLE T2 + NA + + + PCW_SMC_CYCLE_T3 + PCW SMC CYCLE T3 + NA + + + PCW_SMC_CYCLE_T4 + PCW SMC CYCLE T4 + NA + + + PCW_SMC_CYCLE_T5 + PCW SMC CYCLE T5 + NA + + + PCW_SMC_CYCLE_T6 + PCW SMC CYCLE T6 + NA + + + PCW_PACKAGE_NAME + PCW PACKAGE NAME + clg400 + + + PCW_PLL_BYPASSMODE_ENABLE + PCW PLL BYPASSMODE ENABLE + 0 + + + Component_Name + design_2_processing_system7_0_0 + + + + + ZYNQ7 Processing System + + remote_port_c_v4 + remote_port_sc_v4 + xtlm + + 6 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_ps7_0_axi_periph_0/design_2_ps7_0_axi_periph_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_ps7_0_axi_periph_0/design_2_ps7_0_axi_periph_0.xml new file mode 100644 index 0000000..45fd39f --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_ps7_0_axi_periph_0/design_2_ps7_0_axi_periph_0.xml @@ -0,0 +1,1644 @@ + + + xilinx.com + customized_ip + design_2_ps7_0_axi_periph_0 + 1.0 + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_661c4a03 + 2 + 4 + 8 + 16 + 32 + 64 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_76d086ea + 0 + 1 + 2 + + + choice_pairs_ab2668a2 + 0 + 1 + 2 + + + choice_pairs_b6c9535e + 0 + 1 + 3 + 4 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 1 + + + NUM_MI + Number of Master Interfaces + 1 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 3 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 0 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 0 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_SECURE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_SECURE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_SECURE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_SECURE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_SECURE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_SECURE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_SECURE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_SECURE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_SECURE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_SECURE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_SECURE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_SECURE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_SECURE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_SECURE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_SECURE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_SECURE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_SECURE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_SECURE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_SECURE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_SECURE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_SECURE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_SECURE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_SECURE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_SECURE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_SECURE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_SECURE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_SECURE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_SECURE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_SECURE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_SECURE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_SECURE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_SECURE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_SECURE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_SECURE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_SECURE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_SECURE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_SECURE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_SECURE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_SECURE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_SECURE + Incicates whether M63_AXI connects to a secure slave + 0 + + + S00_ARB_PRIORITY + Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S01_ARB_PRIORITY + Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S02_ARB_PRIORITY + Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S03_ARB_PRIORITY + Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S04_ARB_PRIORITY + Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S05_ARB_PRIORITY + Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S06_ARB_PRIORITY + Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S07_ARB_PRIORITY + Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S08_ARB_PRIORITY + Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S09_ARB_PRIORITY + Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S10_ARB_PRIORITY + Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S11_ARB_PRIORITY + Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S12_ARB_PRIORITY + Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S13_ARB_PRIORITY + Controls S13_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S14_ARB_PRIORITY + Controls S14_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S15_ARB_PRIORITY + Controls S15_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + Component_Name + design_2_ps7_0_axi_periph_0 + + + + + AXI Interconnect + 29 + + + + + + + + 2023.1 + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_rst_ps7_0_100M_0/design_2_rst_ps7_0_100M_0.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_rst_ps7_0_100M_0/design_2_rst_ps7_0_100M_0.xml new file mode 100644 index 0000000..4af6e33 --- /dev/null +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/design_2/ip/design_2_rst_ps7_0_100M_0/design_2_rst_ps7_0_100M_0.xml @@ -0,0 +1,700 @@ + + + xilinx.com + customized_ip + design_2_rst_ps7_0_100M_0 + 1.0 + + + clock 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M04_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A02_ADDR_WIDTH + My M04_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A03_ADDR_WIDTH + My M04_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A04_ADDR_WIDTH + My M04_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A05_ADDR_WIDTH + My M04_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A06_ADDR_WIDTH + My M04_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A07_ADDR_WIDTH + My M04_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A08_ADDR_WIDTH + My M04_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A09_ADDR_WIDTH + My M04_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A10_ADDR_WIDTH + My M04_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A11_ADDR_WIDTH + My M04_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A12_ADDR_WIDTH + My M04_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A13_ADDR_WIDTH + My M04_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A14_ADDR_WIDTH + My M04_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A15_ADDR_WIDTH + My M04_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A00_ADDR_WIDTH + My M05_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A01_ADDR_WIDTH + My M05_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A02_ADDR_WIDTH + My M05_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A03_ADDR_WIDTH + My M05_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A04_ADDR_WIDTH + My M05_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A05_ADDR_WIDTH + My M05_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A06_ADDR_WIDTH + My M05_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A07_ADDR_WIDTH + My M05_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A08_ADDR_WIDTH + My M05_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A09_ADDR_WIDTH + My M05_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A10_ADDR_WIDTH + My M05_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A11_ADDR_WIDTH + My M05_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A12_ADDR_WIDTH + My M05_A12_ADDR_WIDTH + 0 + + + + true + + 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true + + + + + + M06_A11_ADDR_WIDTH + My M06_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A12_ADDR_WIDTH + My M06_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A13_ADDR_WIDTH + My M06_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A14_ADDR_WIDTH + My M06_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A15_ADDR_WIDTH + My M06_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A00_ADDR_WIDTH + My M07_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A01_ADDR_WIDTH + My M07_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A02_ADDR_WIDTH + My M07_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A03_ADDR_WIDTH + My M07_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A04_ADDR_WIDTH + My M07_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A05_ADDR_WIDTH + My M07_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A06_ADDR_WIDTH + My M07_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A07_ADDR_WIDTH + My M07_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A08_ADDR_WIDTH + My M07_A08_ADDR_WIDTH + 0 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M08_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A07_ADDR_WIDTH + My M08_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A08_ADDR_WIDTH + My M08_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A09_ADDR_WIDTH + My M08_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A10_ADDR_WIDTH + My M08_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A11_ADDR_WIDTH + My M08_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A12_ADDR_WIDTH + My M08_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A13_ADDR_WIDTH + My M08_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A14_ADDR_WIDTH + My M08_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A15_ADDR_WIDTH + My M08_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A00_ADDR_WIDTH + My M09_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A01_ADDR_WIDTH + My M09_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A02_ADDR_WIDTH + My M09_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A03_ADDR_WIDTH + My M09_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A04_ADDR_WIDTH + My M09_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A05_ADDR_WIDTH + My M09_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A06_ADDR_WIDTH + My M09_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A07_ADDR_WIDTH + My M09_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A08_ADDR_WIDTH + My M09_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A09_ADDR_WIDTH + My M09_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A10_ADDR_WIDTH + My M09_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A11_ADDR_WIDTH + My M09_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A12_ADDR_WIDTH + My M09_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A13_ADDR_WIDTH + My M09_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A14_ADDR_WIDTH + My M09_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A15_ADDR_WIDTH + My M09_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A00_ADDR_WIDTH + My M10_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A01_ADDR_WIDTH + My M10_A01_ADDR_WIDTH + 0 + + + + true + + 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true + + + + + + M11_A00_ADDR_WIDTH + My M11_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A01_ADDR_WIDTH + My M11_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A02_ADDR_WIDTH + My M11_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A03_ADDR_WIDTH + My M11_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A04_ADDR_WIDTH + My M11_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A05_ADDR_WIDTH + My M11_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A06_ADDR_WIDTH + My M11_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A07_ADDR_WIDTH + My M11_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A08_ADDR_WIDTH + My M11_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A09_ADDR_WIDTH + My M11_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A10_ADDR_WIDTH + My M11_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A11_ADDR_WIDTH + My M11_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A12_ADDR_WIDTH + My M11_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A13_ADDR_WIDTH + My M11_A13_ADDR_WIDTH + 0 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DEFAULT_REG_FRAME_BASE + Default Reg Frame Base + 0x3F800000 + + + DEFAULT_REG_STRIDE + Default Reg Stride + 0x00001000 + + + DEFAULT_REG_HOR_BYTES + Default Reg Hor Bytes + 0x00001000 + + + DEFAULT_REG_VER_LINES + Default Reg Ver Lines + 0x00000300 + + + DEFAULT_REG_VGA_MODE + Default Reg Vga Mode + 0x00000000 + + + HSYNC + Hsync + "1" + + + VSYNC + Vsync + "1" + + + HSYNC_START + Hsync Start + 24 + + + HSYNC_END + Hsync End + 160 + + + HACTIVE_START + Hactive Start + 320 + + + TOTAL_HSIZE + Total Hsize + 1344 + + + VSYNC_START + Vsync Start + 3 + + + VSYNC_END + Vsync End + 9 + + + VACTIVE_START + Vactive Start + 38 + + + TOTAL_VSIZE + Total Vsize + 806 + + + COMPONENT_WIDTH_RED + Component Width Red + 5 + + + COMPONENT_WIDTH_GREEN + Component Width Green + 6 + + + COMPONENT_WIDTH_BLUE + Component Width Blue + 5 + + + RGB_LED_WIDTH + Rgb Led Width + 2 + + + LED_WIDTH + Led Width + 4 + + + SWITCH_WIDTH + Switch Width + 4 + + + BUTTON_WIDTH + Button Width + 4 + + + CLKGEN_CLKFBOUT_MULT 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[Bytes] + 0x00001000 + + + DEFAULT_REG_VER_LINES + Vertical Lines + 0x00000300 + + + DEFAULT_REG_VGA_MODE + VGA Mode + 0x00000000 + + + HSYNC + Hsync + "1" + + + VSYNC + Vsync + "1" + + + HSYNC_START + Hsync Start + 24 + + + HSYNC_END + Hsync End + 160 + + + HACTIVE_START + Hactive Start + 320 + + + TOTAL_HSIZE + Total Hsize + 1344 + + + VSYNC_START + Vsync Start + 3 + + + VSYNC_END + Vsync End + 9 + + + VACTIVE_START + Vactive Start + 38 + + + TOTAL_VSIZE + Total Vsize + 806 + + + COMPONENT_WIDTH_RED + Red + 5 + + + COMPONENT_WIDTH_GREEN + Green + 6 + + + COMPONENT_WIDTH_BLUE + Blue + 5 + + + RGB_LED_WIDTH + RGB LEDs + 2 + + + LED_WIDTH + LEDs + 4 + + + SWITCH_WIDTH + Switches + 4 + + + BUTTON_WIDTH + Buttons + 4 + + + CLKGEN_CLKFBOUT_MULT + PLL - Feedback Multiplier + 10 + + + CLKGEN_CLKOUT0_DIVIDE + PLL - Clock 0 Divider [x10] + 1 + + + CLKGEN_CLKOUT1_DIVIDE + PLL - Clock 1 Divider [x1] + 10 + + + CLKGEN_CLKOUT2_DIVIDE + PLL - Clock 2 Divider [x2] + 5 + + + Component_Name + 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d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + d:/ES-IP/IP/zynq_base_hdmi/zynq_base_hdmi.srcs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + + + diff --git a/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml index b368867..21f5aa8 100644 --- a/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml +++ b/Milestone6/milestone6/milestone6.gen/sources_1/bd/mref/axis_video_filter/component.xml @@ -321,7 +321,7 @@ viewChecksum - 9f5bf2d9 + 1ada2a66 @@ -334,7 +334,7 @@ viewChecksum - 9f5bf2d9 + 1ada2a66 @@ -861,7 +861,7 @@ IPI 1 - 2024-12-09T23:45:17Z + 2024-12-10T11:47:25Z 2023.1 diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd index 04a8d5c..3561c2b 100644 --- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/design_1.bd @@ -1,7 +1,7 @@ { "design": { "design_info": { - "boundary_crc": "0x29EA2656194EC7BE", + "boundary_crc": "0x0", "device": "xc7z020clg400-1", "gen_directory": "../../../../milestone6.gen/sources_1/bd/design_1", "name": "design_1", @@ -18,225 +18,7 @@ "axis_downsizer_0": "", "axis_linemem_single_0": "", "axis_upsizer_0": "", - "axis_video_filter_0": "" - }, - "interface_ports": { - "m_axi_lite": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "parameters": { - "ADDR_WIDTH": { - "value": "32" - }, - "ARUSER_WIDTH": { - "value": "0", - "value_src": "const_prop" - }, - "AWUSER_WIDTH": { - "value": "0", - "value_src": "const_prop" - }, - "BUSER_WIDTH": { - "value": "0", - "value_src": "const_prop" - }, - "DATA_WIDTH": { - "value": "32" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "default" - }, - "HAS_BRESP": { - "value": "1", - "value_src": "const_prop" - }, - "HAS_BURST": { - "value": "0" - }, - "HAS_CACHE": { - "value": "0" - }, - "HAS_LOCK": { - "value": "0" - }, - "HAS_PROT": { - "value": "1", - "value_src": "const_prop" - }, - "HAS_QOS": { - "value": "0" - }, - "HAS_REGION": { - "value": "0" - }, - "HAS_RRESP": { - "value": "1", - "value_src": "const_prop" - }, - "HAS_WSTRB": { - "value": "1", - "value_src": "const_prop" - }, - "ID_WIDTH": { - "value": "0", - "value_src": "const_prop" - }, - "INSERT_VIP": { - "value": "0", - "value_src": "default" - }, - "MAX_BURST_LENGTH": { - "value": "1", - "value_src": "auto_prop" - }, - "NUM_READ_OUTSTANDING": { - "value": "1", - "value_src": "auto_prop" - }, - "NUM_READ_THREADS": { - "value": "1", - "value_src": "default" - }, - "NUM_WRITE_OUTSTANDING": { - "value": "1", - "value_src": "auto_prop" - }, - "NUM_WRITE_THREADS": { - "value": "1", - "value_src": "default" - }, - "PHASE": { - "value": "0.0", - "value_src": "default" - }, - "PROTOCOL": { - "value": "AXI4LITE" - }, - "READ_WRITE_MODE": { - "value": "READ_WRITE", - "value_src": "const_prop" - }, - "RUSER_BITS_PER_BYTE": { - "value": "0", - "value_src": "default" - }, - "RUSER_WIDTH": { - "value": "0", - "value_src": "const_prop" - }, - "SUPPORTS_NARROW_BURST": { - "value": "0", - "value_src": "auto_prop" - }, - "WUSER_BITS_PER_BYTE": { - "value": "0", - "value_src": "default" - }, - "WUSER_WIDTH": { - "value": "0", - "value_src": "const_prop" - } - }, - "memory_map_ref": "m_axi_lite", - "port_maps": { - "AWADDR": { - "physical_name": "m_axi_lite_awaddr", - "direction": "O", - "left": "31", - "right": "0" - }, - "AWPROT": { - "physical_name": "m_axi_lite_awprot", - "direction": "O", - "left": "2", - "right": "0" - }, - "AWVALID": { - "physical_name": "m_axi_lite_awvalid", - "direction": "O" - }, - "AWREADY": { - "physical_name": "m_axi_lite_awready", - "direction": "I" - }, - "WDATA": { - "physical_name": "m_axi_lite_wdata", - "direction": "O", - "left": "31", - "right": "0" - }, - "WSTRB": { - "physical_name": "m_axi_lite_wstrb", - "direction": "O", - "left": "3", - "right": "0" - }, - "WVALID": { - "physical_name": "m_axi_lite_wvalid", - "direction": "O" - }, - "WREADY": { - "physical_name": "m_axi_lite_wready", - "direction": "I" - }, - "BRESP": { - "physical_name": "m_axi_lite_bresp", - "direction": "I", - "left": "1", - "right": "0" - }, - "BVALID": { - "physical_name": "m_axi_lite_bvalid", - "direction": "I" - }, - "BREADY": { - "physical_name": "m_axi_lite_bready", - "direction": "O" - }, - "ARADDR": { - "physical_name": "m_axi_lite_araddr", - "direction": "O", - "left": "31", - "right": "0" - }, - "ARPROT": { - "physical_name": "m_axi_lite_arprot", - "direction": "O", - "left": "2", - "right": "0" - }, - "ARVALID": { - "physical_name": "m_axi_lite_arvalid", - "direction": "O" - }, - "ARREADY": { - "physical_name": "m_axi_lite_arready", - "direction": "I" - }, - "RDATA": { - "physical_name": "m_axi_lite_rdata", - "direction": "I", - "left": "31", - "right": "0" - }, - "RRESP": { - "physical_name": "m_axi_lite_rresp", - "direction": "I", - "left": "1", - "right": "0" - }, - "RVALID": { - "physical_name": "m_axi_lite_rvalid", - "direction": "I" - }, - "RREADY": { - "physical_name": "m_axi_lite_rready", - "direction": "O" - } - } - } + "axis_video_filter_1": "" }, "components": { "axis_slave_simmodel_0": { @@ -357,11 +139,11 @@ } } }, - "axis_video_filter_0": { + "axis_video_filter_1": { "vlnv": "xilinx.com:module_ref:axis_video_filter:1.0", - "xci_name": "design_1_axis_video_filter_0_0", - "xci_path": "ip\\design_1_axis_video_filter_0_0\\design_1_axis_video_filter_0_0.xci", - "inst_hier_path": "axis_video_filter_0", + "xci_name": "design_1_axis_video_filter_1_1", + "xci_path": "ip\\design_1_axis_video_filter_1_1\\design_1_axis_video_filter_1_1.xci", + "inst_hier_path": "axis_video_filter_1", "reference_info": { "ref_type": "hdl", "ref_name": "axis_video_filter", @@ -712,8 +494,8 @@ "interface_nets": { "axil_master_with_rom_0_M_AXIL": { "interface_ports": [ - "axil_master_with_rom_0/M_AXIL", - "m_axi_lite" + "axis_video_filter_1/S_AXIL", + "axil_master_with_rom_0/M_AXIL" ] }, "axis_downsizer_0_M_AXIS": { @@ -725,7 +507,7 @@ "axis_linemem_single_0_m_axis": { "interface_ports": [ "axis_linemem_single_0/m_axis", - "axis_video_filter_0/S_AXIS" + "axis_video_filter_1/S_AXIS" ] }, "axis_master_simmodel_0_M_AXIS": { @@ -740,9 +522,9 @@ "axis_slave_simmodel_0/S_AXIS" ] }, - "axis_video_filter_0_M_AXIS": { + "axis_video_filter_1_M_AXIS": { "interface_ports": [ - "axis_video_filter_0/M_AXIS", + "axis_video_filter_1/M_AXIS", "axis_upsizer_0/S_AXIS" ] } @@ -757,19 +539,19 @@ "axis_downsizer_0/AXIS_ACLK", "axis_linemem_single_0/aclk", "axis_upsizer_0/AXIS_ACLK", - "axis_video_filter_0/ACLK" + "axis_video_filter_1/ACLK" ] }, "Net1": { "ports": [ "clk_rst_generator_0/rst_n", - "axis_upsizer_0/AXIS_ARESETN", "axis_slave_simmodel_0/S_AXIS_ARESETN", "axil_master_with_rom_0/M_AXIL_ARESETN", "axis_master_simmodel_0/ARESETN", "axis_linemem_single_0/aresetn", "axis_downsizer_0/AXIS_ARESETN", - "axis_video_filter_0/ARESETN" + "axis_upsizer_0/AXIS_ARESETN", + "axis_video_filter_1/ARESETN" ] }, "axis_slave_simmodel_0_FINISHED": { @@ -778,22 +560,6 @@ "clk_rst_generator_0/stop_simulation" ] } - }, - "addressing": { - "/": { - "memory_maps": { - "m_axi_lite": { - "address_blocks": { - "Reg": { - "base_address": "0", - "range": "64K", - "width": "16", - "usage": "register" - } - } - } - } - } } } } \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xci new file mode 100644 index 0000000..e7166fa --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1/design_1_axis_video_filter_1_1.xci @@ -0,0 +1,232 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_axis_video_filter_1_1", + "cell_name": "axis_video_filter_1", + "component_reference": "xilinx.com:module_ref:axis_video_filter:1.0", + "ip_revision": "1", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1", + "parameters": { + "component_parameters": { + "COEFF_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_axis_video_filter_1_1", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "COEFF_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "1" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_1_1" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ] + } + }, + "boundary": { + "ports": { + "ACLK": [ { "direction": "in" } ], + "ARESETN": [ { "direction": "in" } ], + "S_AXIS_TVALID": [ { "direction": "in", "driver_value": "0x0" } ], + "S_AXIS_TDATA": [ { "direction": "in", "size_left": "23", "size_right": "0", "driver_value": "0" } ], + "S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ], + "S_AXIS_TREADY": [ { "direction": "out" } ], + "S_AXIS_TUSER": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "M_AXIS_TVALID": [ { "direction": "out" } ], + "M_AXIS_TDATA": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], + "M_AXIS_TLAST": [ { "direction": "out" } ], + "M_AXIS_TREADY": [ { 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+ "display_name": "S_AXIL", + "address_blocks": { + "reg0": { + "base_address": "0x0", + "range": "0x8000", + "display_name": "reg0", + "usage": "register" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui index 5e491ac..d902781 100644 --- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui @@ -1,30 +1,29 @@ { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.705882", - "Default View_TopLeft":"20,-153", + "Default View_ScaleFactor":"0.920395", + "Default View_TopLeft":"12,-175", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 # -string -flagsOSRD -preplace port m_axi_lite -pg 1 -lvl 7 -x 1640 -y 80 -defaultsOSRD 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netloc axis_master_simmodel_0_M_AXIS 1 0 7 40 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 1620 -preplace netloc axis_upsizer_0_M_AXIS 1 3 1 N 300 -preplace netloc axis_video_filter_0_M_AXIS 1 2 1 N 280 -levelinfo -pg 1 0 170 450 730 1000 1240 1490 1640 -pagesize -pg 1 -db -bbox -sgen 0 0 1760 400 +preplace inst axis_slave_simmodel_0 -pg 1 -lvl 4 -x 920 -y 310 -defaultsOSRD +preplace inst clk_rst_generator_0 -pg 1 -lvl 5 -x 1150 -y 310 -defaultsOSRD +preplace inst axil_master_with_rom_0 -pg 1 -lvl 6 -x 1390 -y 100 -defaultsOSRD +preplace inst axis_master_simmodel_0 -pg 1 -lvl 6 -x 1390 -y 220 -defaultsOSRD +preplace inst axis_downsizer_0 -pg 1 -lvl 1 -x 150 -y 100 -defaultsOSRD +preplace inst axis_linemem_single_0 -pg 1 -lvl 2 -x 420 -y 120 -defaultsOSRD +preplace inst axis_upsizer_0 -pg 1 -lvl 3 -x 670 -y 290 -defaultsOSRD +preplace inst axis_video_filter_1 -pg 1 -lvl 2 -x 420 -y 270 -defaultsOSRD +preplace netloc Net 1 0 6 30 180 270 360 550 370 790 220 NJ 220 1260J +preplace netloc Net1 1 0 6 20 190 280 370 540 380 800 230 N 230 1270 +preplace netloc axis_slave_simmodel_0_FINISHED 1 4 1 N 310 +preplace netloc axis_downsizer_0_M_AXIS 1 1 1 N 100 +preplace netloc axis_master_simmodel_0_M_AXIS 1 0 7 30 20 NJ 20 NJ 20 N 20 NJ 20 NJ 20 1520 +preplace netloc axis_upsizer_0_M_AXIS 1 3 1 N 290 +preplace netloc axis_linemem_single_0_m_axis 1 1 2 300 40 540 +preplace netloc axis_video_filter_1_M_AXIS 1 2 1 N 270 +preplace netloc axil_master_with_rom_0_M_AXIL 1 1 6 290 30 NJ 30 NJ 30 NJ 30 NJ 30 1510 +levelinfo -pg 1 0 150 420 670 920 1150 1390 1540 +pagesize -pg 1 -db -bbox -sgen 0 0 1540 390 " } 0 diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd new file mode 100644 index 0000000..1cd7d47 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/design_2.bd @@ -0,0 +1,3558 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x3A6704D3ADB2B84D", + "device": "xc7z020clg400-1", + "gen_directory": "../../../../milestone6.gen/sources_1/bd/design_2", + "name": "design_2", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2023.1" + }, + "design_tree": { + "AXI_Intercon": { + "axi_mem_intercon": { + "xbar": "", + "s00_couplers": {}, + "m00_couplers": {}, + "m01_couplers": {}, + "m02_couplers": {} + }, + "ps7_0_axi_periph": { + "s00_couplers": { + "auto_pc": "" + } + }, + "axi_interconnect_0": { + "s00_couplers": {} + } + }, + "PS": { + "processing_system7_0": "", + "rst_ps7_0_100M": "", + "xlconcat_0": "", + "xlconstant_0": "" + }, + "ZYNQ_BASE": { + "zynq_base_hdmi_0": "" + }, + "axis_downsizer_0": "", + "axi_2d_mmvs_0": "", + "axis_upsizer_0": "", + "axis_linemem_single_0": "", + "axis_video_filter_0": "" + }, + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", + "parameters": { + "AXI_ARBITRATION_SCHEME": { + "value": "TDM", + "value_src": "default" + }, + "BURST_LENGTH": { + "value": "8", + "value_src": "default" + }, + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "CAS_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CAS_WRITE_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CS_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_MASK_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "8", + "value_src": "default" + }, + "MEMORY_TYPE": { + "value": "COMPONENTS", + "value_src": "default" + }, + "MEM_ADDR_MAP": { + "value": "ROW_COLUMN_BANK", + "value_src": "default" + }, + "SLOT": { + "value": "Single", + "value_src": "default" + }, + "TIMEPERIOD_PS": { + "value": "1250", + "value_src": "default" + } + }, + "port_maps": { + "CAS_N": { + "physical_name": "DDR_cas_n", + "direction": "IO" + }, + "CKE": { + "physical_name": "DDR_cke", + "direction": "IO" + }, + "CK_N": { + "physical_name": "DDR_ck_n", + "direction": "IO" + }, + "CK_P": { + "physical_name": "DDR_ck_p", + "direction": "IO" + }, + "CS_N": { + "physical_name": "DDR_cs_n", + "direction": "IO" + }, + "RESET_N": { + "physical_name": "DDR_reset_n", + "direction": "IO" + }, + "ODT": { + "physical_name": "DDR_odt", + "direction": "IO" + }, + "RAS_N": { + "physical_name": "DDR_ras_n", + "direction": "IO" + }, + "WE_N": { + "physical_name": "DDR_we_n", + "direction": "IO" + }, + "BA": { + "physical_name": "DDR_ba", + "direction": "IO", + "left": "2", + "right": "0" + }, + "ADDR": { + "physical_name": "DDR_addr", + "direction": "IO", + "left": "14", + "right": "0" + }, + "DM": { + "physical_name": "DDR_dm", + "direction": "IO", + "left": "3", + "right": "0" + }, + "DQ": { + "physical_name": "DDR_dq", + "direction": "IO", + "left": "31", + "right": "0" + }, + "DQS_N": { + "physical_name": "DDR_dqs_n", + "direction": "IO", + "left": "3", + "right": "0" + }, + "DQS_P": { + "physical_name": "DDR_dqs_p", + "direction": "IO", + "left": "3", + "right": "0" + } + } + }, + "FIXED_IO": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + } + }, + "port_maps": { + "MIO": { + "physical_name": "FIXED_IO_mio", + "direction": "IO", + "left": "53", + "right": "0" + }, + "DDR_VRN": { + "physical_name": "FIXED_IO_ddr_vrn", + "direction": "IO" + }, + "DDR_VRP": { + "physical_name": "FIXED_IO_ddr_vrp", + "direction": "IO" + }, + "PS_SRSTB": { + "physical_name": "FIXED_IO_ps_srstb", + "direction": "IO" + }, + "PS_CLK": { + "physical_name": "FIXED_IO_ps_clk", + "direction": "IO" + }, + "PS_PORB": { + "physical_name": "FIXED_IO_ps_porb", + "direction": "IO" + } + } + } + }, + "ports": { + "BUTTON": { + "direction": "I", + "left": "3", + "right": "0" + }, + "HDMI_CLK_N": { + "direction": "O" + }, + "HDMI_CLK_P": { + "direction": "O" + }, + "HDMI_DATA_N": { + "direction": "O", + "left": "2", + "right": "0" + }, + "HDMI_DATA_P": { + "direction": "O", + "left": "2", + "right": "0" + }, + "LED": { + "direction": "O", + "left": "3", + "right": "0" + }, + "RGB_LED": { + "direction": "O", + "left": "5", + "right": "0" + }, + "SWITCH": { + "direction": "I", + "left": "3", + "right": "0" + } + }, + "components": { + "AXI_Intercon": { + "interface_ports": { + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI1": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S00_AXI1": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI2": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI3": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S00_AXI_2": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI_4": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I" + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "axi_mem_intercon": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip\\design_2_axi_mem_intercon_0\\design_2_axi_mem_intercon_0.xci", + "inst_hier_path": "AXI_Intercon/axi_mem_intercon", + "xci_name": "design_2_axi_mem_intercon_0", + "parameters": { + "NUM_MI": { + "value": "3" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M02_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M02_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M02_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M02_ARESETN" + } + } + }, + "M02_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "design_2_xbar_0", + "xci_path": "ip\\design_2_xbar_0\\design_2_xbar_0.xci", + "inst_hier_path": "AXI_Intercon/axi_mem_intercon/xbar", + "parameters": { + "NUM_MI": { + "value": "3" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI", + "M02_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s00_couplers_to_s00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m02_couplers_to_m02_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "axi_mem_intercon_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "m00_couplers_to_axi_mem_intercon": { + "interface_ports": [ + "m00_couplers/M_AXI", + "M00_AXI" + ] + }, + "m01_couplers_to_axi_mem_intercon": { + "interface_ports": [ + "m01_couplers/M_AXI", + "M01_AXI" + ] + }, + "m02_couplers_to_axi_mem_intercon": { + "interface_ports": [ + "m02_couplers/M_AXI", + "M02_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + }, + "xbar_to_m02_couplers": { + "interface_ports": [ + "xbar/M02_AXI", + "m02_couplers/S_AXI" + ] + } + }, + "nets": { + "M00_ACLK_1": { + "ports": [ + "M00_ACLK", + "m00_couplers/M_ACLK" + ] + }, + "M00_ARESETN_1": { + "ports": [ + "M00_ARESETN", + "m00_couplers/M_ARESETN" + ] + }, + "M01_ACLK_1": { + "ports": [ + "M01_ACLK", + "m01_couplers/M_ACLK" + ] + }, + "M01_ARESETN_1": { + "ports": [ + "M01_ARESETN", + "m01_couplers/M_ARESETN" + ] + }, + "M02_ACLK_1": { + "ports": [ + "M02_ACLK", + "m02_couplers/M_ACLK" + ] + }, + "M02_ARESETN_1": { + "ports": [ + "M02_ARESETN", + "m02_couplers/M_ARESETN" + ] + }, + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "axi_mem_intercon_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK", + "m02_couplers/S_ACLK" + ] + }, + "axi_mem_intercon_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN", + "m02_couplers/S_ARESETN" + ] + } + } + }, + "ps7_0_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip\\design_2_ps7_0_axi_periph_0\\design_2_ps7_0_axi_periph_0.xci", + "inst_hier_path": "AXI_Intercon/ps7_0_axi_periph", + "xci_name": "design_2_ps7_0_axi_periph_0", + "parameters": { + "NUM_MI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "xci_name": "design_2_auto_pc_0", + "xci_path": "ip\\design_2_auto_pc_0\\design_2_auto_pc_0.xci", + "inst_hier_path": "AXI_Intercon/ps7_0_axi_periph/s00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI4LITE" + }, + "SI_PROTOCOL": { + "value": "AXI3" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_pc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + } + }, + "interface_nets": { + "ps7_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "s00_couplers/M_AXI", + "M00_AXI" + ] + } + }, + "nets": { + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "ps7_0_axi_periph_ACLK_net": { + "ports": [ + "M00_ACLK", + "s00_couplers/M_ACLK" + ] + }, + "ps7_0_axi_periph_ARESETN_net": { + "ports": [ + "M00_ARESETN", + "s00_couplers/M_ARESETN" + ] + } + } + }, + "axi_interconnect_0": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip\\design_2_axi_interconnect_0_0\\design_2_axi_interconnect_0_0.xci", + "inst_hier_path": "AXI_Intercon/axi_interconnect_0", + "xci_name": "design_2_axi_interconnect_0_0", + "parameters": { + "NUM_MI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s00_couplers_to_s00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "axi_interconnect_0_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_axi_interconnect_0": { + "interface_ports": [ + "s00_couplers/M_AXI", + "M00_AXI" + ] + } + }, + "nets": { + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "axi_interconnect_0_ACLK_net": { + "ports": [ + "M00_ACLK", + "s00_couplers/M_ACLK" + ] + }, + "axi_interconnect_0_ARESETN_net": { + "ports": [ + "M00_ARESETN", + "s00_couplers/M_ARESETN" + ] + } + } + } + }, + "interface_nets": { + "S00_AXI_1_1": { + "interface_ports": [ + "S00_AXI_2", + "axi_interconnect_0/S00_AXI" + ] + }, + "axi_interconnect_0_M00_AXI": { + "interface_ports": [ + "M00_AXI_4", + "axi_interconnect_0/M00_AXI" + ] + }, + "axi_mem_intercon_M00_AXI": { + "interface_ports": [ + "M00_AXI1", + "axi_mem_intercon/M00_AXI" + ] + }, + "axi_mem_intercon_M01_AXI": { + "interface_ports": [ + "M00_AXI2", + "axi_mem_intercon/M01_AXI" + ] + }, + "axi_mem_intercon_M02_AXI": { + "interface_ports": [ + "M00_AXI3", + "axi_mem_intercon/M02_AXI" + ] + }, + "processing_system7_0_M_AXI_GP0": { + "interface_ports": [ + "S00_AXI", + "ps7_0_axi_periph/S00_AXI" + ] + }, + "ps7_0_axi_periph_M00_AXI": { + "interface_ports": [ + "M00_AXI", + "ps7_0_axi_periph/M00_AXI" + ] + }, + "zynq_base_hdmi_0_M_AXI": { + "interface_ports": [ + "S00_AXI1", + "axi_mem_intercon/S00_AXI" + ] + } + }, + "nets": { + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "ACLK", + "axi_mem_intercon/ACLK", + "axi_mem_intercon/M00_ACLK", + "axi_mem_intercon/S00_ACLK", + "ps7_0_axi_periph/ACLK", + "ps7_0_axi_periph/M00_ACLK", + "ps7_0_axi_periph/S00_ACLK", + "axi_mem_intercon/M01_ACLK", + "axi_mem_intercon/M02_ACLK", + "axi_interconnect_0/ACLK", + "axi_interconnect_0/S00_ACLK", + "axi_interconnect_0/M00_ACLK" + ] + }, + "rst_ps7_0_100M_peripheral_aresetn": { + "ports": [ + "S00_ARESETN", + "axi_mem_intercon/ARESETN", + "axi_mem_intercon/M00_ARESETN", + "axi_mem_intercon/S00_ARESETN", + "ps7_0_axi_periph/ARESETN", + "ps7_0_axi_periph/M00_ARESETN", + "ps7_0_axi_periph/S00_ARESETN", + "axi_mem_intercon/M01_ARESETN", + "axi_mem_intercon/M02_ARESETN", + "axi_interconnect_0/ARESETN", + "axi_interconnect_0/S00_ARESETN", + "axi_interconnect_0/M00_ARESETN" + ] + } + } + }, + "PS": { + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0" + }, + "FIXED_IO": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0" + }, + "M_AXI_GP0": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI_HP0": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI_ACP": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "FCLK_CLK0": { + "type": "clk", + "direction": "O" + }, + "FCLK_CLK3": { + "type": "clk", + "direction": "O" + }, + "In0": { + "direction": "I", + "left": "0", + "right": "0" + }, + "peripheral_aresetn": { + "type": "rst", + "direction": "O", + "left": "0", + "right": "0" + } + }, + "components": { + "processing_system7_0": { + "vlnv": "xilinx.com:ip:processing_system7:5.5", + "xci_name": "design_2_processing_system7_0_0", + "xci_path": "ip\\design_2_processing_system7_0_0\\design_2_processing_system7_0_0.xci", + "inst_hier_path": "PS/processing_system7_0", + "parameters": { + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { + "value": "666.666687" + }, + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.158730" + }, + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "66.666672" + }, + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { + "value": "50.000000" + }, + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_APU_CLK_RATIO_ENABLE": { + "value": "6:2:1" + }, + "PCW_APU_PERIPHERAL_FREQMHZ": { + "value": "667" + }, + "PCW_CAN0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_CAN_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_CLK0_FREQ": { + "value": "100000000" + }, + "PCW_CLK1_FREQ": { + "value": "125000000" + }, + "PCW_CLK2_FREQ": { + "value": "200000000" + }, + "PCW_CLK3_FREQ": { + "value": "66666672" + }, + "PCW_CPU_CPU_6X4X_MAX_RANGE": { + "value": "667" + }, + "PCW_CPU_PERIPHERAL_CLKSRC": { + "value": "ARM PLL" + }, + "PCW_CRYSTAL_PERIPHERAL_FREQMHZ": { + "value": "33.333333" + }, + "PCW_DCI_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.159" + }, + "PCW_DDR_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DDR_RAM_HIGHADDR": { + "value": "0x3FFFFFFF" + }, + "PCW_ENET0_ENET0_IO": { + "value": "MIO 16 .. 27" + }, + "PCW_ENET0_GRP_MDIO_ENABLE": { + "value": "1" + }, + "PCW_ENET0_GRP_MDIO_IO": { + "value": "MIO 52 .. 53" + }, + "PCW_ENET0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_ENET0_PERIPHERAL_FREQMHZ": { + "value": "1000 Mbps" + }, + "PCW_ENET0_RESET_ENABLE": { + "value": "0" + }, + "PCW_ENET1_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_ENET_RESET_ENABLE": { + "value": "1" + }, + "PCW_ENET_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_ENET_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_EN_4K_TIMER": { + "value": "0" + }, + "PCW_EN_CAN0": { + "value": "0" + }, + "PCW_EN_CLK1_PORT": { + "value": "1" + }, + "PCW_EN_CLK2_PORT": { + "value": "1" + }, + "PCW_EN_CLK3_PORT": { + "value": "1" + }, + "PCW_EN_EMIO_CAN0": { + "value": "0" + }, + "PCW_EN_EMIO_I2C0": { + "value": "0" + }, + "PCW_EN_EMIO_I2C1": { + "value": "0" + }, + "PCW_EN_EMIO_SPI0": { + "value": "0" + }, + "PCW_EN_EMIO_SPI1": { + "value": "0" + }, + "PCW_EN_EMIO_TTC0": { + "value": "1" + }, + "PCW_EN_EMIO_UART0": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO0": { + "value": "1" + }, + "PCW_EN_ENET0": { + "value": "1" + }, + "PCW_EN_GPIO": { + "value": "1" + }, + "PCW_EN_I2C0": { + "value": "1" + }, + "PCW_EN_I2C1": { + "value": "1" + }, + "PCW_EN_QSPI": { + "value": "1" + }, + "PCW_EN_SDIO0": { + "value": "1" + }, + "PCW_EN_SPI0": { + "value": "0" + }, + "PCW_EN_SPI1": { + "value": "0" + }, + "PCW_EN_TTC0": { + "value": "1" + }, + "PCW_EN_UART0": { + "value": "1" + }, + "PCW_EN_UART1": { + "value": "1" + }, + "PCW_EN_USB0": { + "value": "1" + }, + "PCW_FCLK_CLK1_BUF": { + "value": "TRUE" + }, + "PCW_FCLK_CLK2_BUF": { + "value": "TRUE" + }, + "PCW_FCLK_CLK3_BUF": { + "value": "TRUE" + }, + "PCW_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "125" + }, + "PCW_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "65" + }, + "PCW_FPGA_FCLK0_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK1_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK2_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK3_ENABLE": { + "value": "1" + }, + "PCW_GPIO_MIO_GPIO_ENABLE": { + "value": "1" + }, + "PCW_GPIO_MIO_GPIO_IO": { + "value": "MIO" + }, + "PCW_GPIO_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C0_GRP_INT_ENABLE": { + "value": "0" + }, + "PCW_I2C0_I2C0_IO": { + "value": "MIO 14 .. 15" + }, + "PCW_I2C0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_I2C0_RESET_ENABLE": { + "value": "0" + }, + "PCW_I2C1_GRP_INT_ENABLE": { + "value": "0" + }, + "PCW_I2C1_I2C1_IO": { + "value": "MIO 12 .. 13" + }, + "PCW_I2C1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_I2C_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_I2C_RESET_ENABLE": { + "value": "1" + }, + "PCW_I2C_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_IRQ_F2P_INTR": { + "value": "1" + }, + "PCW_IRQ_F2P_MODE": { + "value": "DIRECT" + }, + "PCW_MIO_0_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_0_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_0_SLEW": { + "value": "slow" + }, + "PCW_MIO_10_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_10_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_10_SLEW": { + "value": "slow" + }, + "PCW_MIO_11_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_11_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_11_SLEW": { + "value": "slow" + }, + "PCW_MIO_12_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_12_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_12_SLEW": { + "value": "slow" + }, + "PCW_MIO_13_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_13_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_13_SLEW": { + "value": "slow" + }, + "PCW_MIO_14_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_14_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_14_SLEW": { + "value": "slow" + }, + "PCW_MIO_15_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_15_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_15_SLEW": { + "value": "slow" + }, + "PCW_MIO_16_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_16_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_16_SLEW": { + "value": "fast" + }, + "PCW_MIO_17_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_17_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_17_SLEW": { + "value": "fast" + }, + "PCW_MIO_18_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_18_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_18_SLEW": { + "value": "fast" + }, + "PCW_MIO_19_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_19_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_19_SLEW": { + "value": "fast" + }, + "PCW_MIO_1_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_1_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_1_SLEW": { + "value": "slow" + }, + "PCW_MIO_20_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_20_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_20_SLEW": { + "value": "fast" + }, + "PCW_MIO_21_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_21_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_21_SLEW": { + "value": "fast" + }, + "PCW_MIO_22_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_22_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_22_SLEW": { + "value": "fast" + }, + "PCW_MIO_23_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_23_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_23_SLEW": { + "value": "fast" + }, + "PCW_MIO_24_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_24_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_24_SLEW": { + "value": "fast" + }, + "PCW_MIO_25_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_25_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_25_SLEW": { + "value": "fast" + }, + "PCW_MIO_26_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_26_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_26_SLEW": { + "value": "fast" + }, + "PCW_MIO_27_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_27_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_27_SLEW": { + "value": "fast" + }, + "PCW_MIO_28_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_28_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_28_SLEW": { + "value": "fast" + }, + "PCW_MIO_29_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_29_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_29_SLEW": { + "value": "fast" + }, + "PCW_MIO_2_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_2_SLEW": { + "value": "slow" + }, + "PCW_MIO_30_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_30_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_30_SLEW": { + "value": "fast" + }, + "PCW_MIO_31_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_31_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_31_SLEW": { + "value": "fast" + }, + "PCW_MIO_32_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_32_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_32_SLEW": { + "value": "fast" + }, + "PCW_MIO_33_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_33_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_33_SLEW": { + "value": "fast" + }, + "PCW_MIO_34_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_34_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_34_SLEW": { + "value": "fast" + }, + "PCW_MIO_35_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_35_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_35_SLEW": { + "value": "fast" + }, + "PCW_MIO_36_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_36_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_36_SLEW": { + "value": "fast" + }, + "PCW_MIO_37_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_37_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_37_SLEW": { + "value": "fast" + }, + "PCW_MIO_38_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_38_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_38_SLEW": { + "value": "fast" + }, + "PCW_MIO_39_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_39_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_39_SLEW": { + "value": "fast" + }, + "PCW_MIO_3_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_3_SLEW": { + "value": "slow" + }, + "PCW_MIO_40_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_40_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_40_SLEW": { + "value": "slow" + }, + "PCW_MIO_41_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_41_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_41_SLEW": { + "value": "slow" + }, + "PCW_MIO_42_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_42_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_42_SLEW": { + "value": "slow" + }, + "PCW_MIO_43_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_43_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_43_SLEW": { + "value": "slow" + }, + "PCW_MIO_44_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_44_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_44_SLEW": { + "value": "slow" + }, + "PCW_MIO_45_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_45_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_45_SLEW": { + "value": "slow" + }, + "PCW_MIO_46_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_46_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_46_SLEW": { + "value": "slow" + }, + "PCW_MIO_47_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_47_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_47_SLEW": { + "value": "slow" + }, + "PCW_MIO_48_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_48_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_48_SLEW": { + "value": "slow" + }, + "PCW_MIO_49_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_49_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_49_SLEW": { + "value": "slow" + }, + "PCW_MIO_4_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_4_SLEW": { + "value": "slow" + }, + "PCW_MIO_50_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_50_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_50_SLEW": { + "value": "slow" + }, + "PCW_MIO_51_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_51_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_51_SLEW": { + "value": "slow" + }, + "PCW_MIO_52_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_52_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_52_SLEW": { + "value": "slow" + }, + "PCW_MIO_53_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_53_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_53_SLEW": { + "value": "slow" + }, + "PCW_MIO_5_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_5_SLEW": { + "value": "slow" + }, + "PCW_MIO_6_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_6_SLEW": { + "value": "slow" + }, + "PCW_MIO_7_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_7_SLEW": { + "value": "slow" + }, + "PCW_MIO_8_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_8_SLEW": { + "value": "slow" + }, + "PCW_MIO_9_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_9_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_9_SLEW": { + "value": "slow" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": [ + "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#UART 0#UART 0#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet", + "0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0" + ] + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#rx#tx#scl#sda#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio" + }, + "PCW_OVERRIDE_BASIC_CLOCK": { + "value": "0" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY0": { + "value": "0.221" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY1": { + "value": "0.222" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY2": { + "value": "0.217" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY3": { + "value": "0.244" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.050" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.044" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2": { + "value": "-0.035" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3": { + "value": "-0.100" + }, + "PCW_PCAP_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_PJTAG_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_PLL_BYPASSMODE_ENABLE": { + "value": "0" + }, + "PCW_PRESET_BANK0_VOLTAGE": { + "value": "LVCMOS 3.3V" + }, + "PCW_PRESET_BANK1_VOLTAGE": { + "value": "LVCMOS 1.8V" + }, + "PCW_QSPI_GRP_FBCLK_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_FBCLK_IO": { + "value": "MIO 8" + }, + "PCW_QSPI_GRP_IO1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_SINGLE_SS_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_SINGLE_SS_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_QSPI_GRP_SS1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_INTERNAL_HIGHADDRESS": { + "value": "0xFCFFFFFF" + }, + "PCW_QSPI_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_QSPI_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_QSPI_QSPI_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_SD0_GRP_CD_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_CD_IO": { + "value": "MIO 47" + }, + "PCW_SD0_GRP_POW_ENABLE": { + "value": "0" + }, + "PCW_SD0_GRP_WP_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_WP_IO": { + "value": "EMIO" + }, + "PCW_SD0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_SD0_SD0_IO": { + "value": "MIO 40 .. 45" + }, + "PCW_SDIO_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SDIO_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_SDIO_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_SINGLE_QSPI_DATA_MODE": { + "value": "x4" + }, + "PCW_SMC_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SPI0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_TPIU_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_TTC0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_TTC0_TTC0_IO": { + "value": "EMIO" + }, + "PCW_TTC_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_UART0_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART0_UART0_IO": { + "value": "MIO 10 .. 11" + }, + "PCW_UART1_BAUD_RATE": { + "value": "115200" + }, + "PCW_UART1_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART1_UART1_IO": { + "value": "MIO 48 .. 49" + }, + "PCW_UART_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_UART_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_UART_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { + "value": "533.333374" + }, + "PCW_UIPARAM_DDR_ADV_ENABLE": { + "value": "0" + }, + "PCW_UIPARAM_DDR_AL": { + "value": "0" + }, + "PCW_UIPARAM_DDR_BL": { + "value": "8" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY0": { + "value": "0.221" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY1": { + "value": "0.222" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY2": { + "value": "0.217" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY3": { + "value": "0.244" + }, + "PCW_UIPARAM_DDR_BUS_WIDTH": { + "value": "32 Bit" + }, + "PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM": { + "value": "18.8" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM": { + "value": "18.8" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM": { + "value": "18.8" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM": { + "value": "18.8" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_STOP_EN": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_0_LENGTH_MM": { + "value": "22.8" + }, + "PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH": { + "value": "105.056" + }, + "PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_1_LENGTH_MM": { + "value": "27.9" + }, + "PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH": { + "value": "66.904" + }, + "PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_2_LENGTH_MM": { + "value": "22.9" + }, + "PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH": { + "value": "89.1715" + }, + "PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_3_LENGTH_MM": { + "value": "29.4" + }, + "PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH": { + "value": "113.63" + }, + "PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.050" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.044" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2": { + "value": "-0.035" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3": { + "value": "-0.100" + }, + "PCW_UIPARAM_DDR_DQ_0_LENGTH_MM": { + "value": "22.8" + }, + "PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH": { + "value": "98.503" + }, + "PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_1_LENGTH_MM": { + "value": "27.9" + }, + "PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH": { + "value": "68.5855" + }, + "PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_2_LENGTH_MM": { + "value": "22.9" + }, + "PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH": { + "value": "90.295" + }, + "PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_3_LENGTH_MM": { + "value": "29.4" + }, + "PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH": { + "value": "103.977" + }, + "PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_ENABLE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_FREQ_MHZ": { + "value": "533.333333" + }, + "PCW_UIPARAM_DDR_HIGH_TEMP": { + "value": "Normal (0-85)" + }, + "PCW_UIPARAM_DDR_MEMORY_TYPE": { + "value": "DDR 3 (Low Voltage)" + }, + "PCW_UIPARAM_DDR_PARTNO": { + "value": "MT41K256M16 RE-125" + }, + "PCW_UIPARAM_DDR_TRAIN_DATA_EYE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_READ_GATE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL": { + "value": "1" + }, + "PCW_UIPARAM_DDR_USE_INTERNAL_VREF": { + "value": "0" + }, + "PCW_USB0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_USB0_RESET_ENABLE": { + "value": "1" + }, + "PCW_USB0_RESET_IO": { + "value": "MIO 46" + }, + "PCW_USB0_USB0_IO": { + "value": "MIO 28 .. 39" + }, + "PCW_USB_RESET_ENABLE": { + "value": "1" + }, + "PCW_USB_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_USB_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_USE_AXI_NONSECURE": { + "value": "0" + }, + "PCW_USE_CROSS_TRIGGER": { + "value": "0" + }, + "PCW_USE_DEFAULT_ACP_USER_VAL": { + "value": "1" + }, + "PCW_USE_FABRIC_INTERRUPT": { + "value": "1" + }, + "PCW_USE_M_AXI_GP0": { + "value": "1" + }, + "PCW_USE_S_AXI_ACP": { + "value": "1" + }, + "PCW_USE_S_AXI_GP0": { + "value": "0" + }, + "PCW_USE_S_AXI_HP0": { + "value": "1" + } + }, + "interface_ports": { + "M_AXI_GP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x40000000", + "maximum": "0x7FFFFFFF", + "width": "32" + } + }, + "S_AXI_ACP": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "memory_map_ref": "S_AXI_ACP" + }, + "S_AXI_HP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "memory_map_ref": "S_AXI_HP0" + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32", + "local_memory_map": { + "name": "Data", + "description": "Address Space Segments", + "address_blocks": { + "segment1": { + "name": "segment1", + "display_name": "segment1", + "base_address": "0x00000000", + "range": "256K", + "width": "18", + "usage": "register" + }, + "segment2": { + "name": "segment2", + "display_name": "segment2", + "base_address": "0x00040000", + "range": "256K", + "width": "19", + "usage": "register" + }, + "segment3": { + "name": "segment3", + "display_name": "segment3", + "base_address": "0x00080000", + "range": "512K", + "width": "20", + "usage": "register" + }, + "segment4": { + "name": "segment4", + "display_name": "segment4", + "base_address": "0x00100000", + "range": "1023M", + "width": "30", + "usage": "register" + }, + "M_AXI_GP0": { + "name": "M_AXI_GP0", + "display_name": "M_AXI_GP0", + "base_address": "0x40000000", + "range": "1G", + "width": "31", + "usage": "register" + }, + "M_AXI_GP1": { + "name": "M_AXI_GP1", + "display_name": "M_AXI_GP1", + "base_address": "0x80000000", + "range": "1G", + "width": "32", + "usage": "register" + }, + "IO_Peripheral_Registers": { + "name": "IO_Peripheral_Registers", + "display_name": "IO Peripheral Registers", + "base_address": "0xE0000000", + "range": "3M", + "width": "32", + "usage": "register" + }, + "SMC_Memories": { + "name": "SMC_Memories", + "display_name": "SMC Memories", + "base_address": "0xE1000000", + "range": "80M", + "width": "32", + "usage": "register" + }, + "SLCR_Registers": { + "name": "SLCR_Registers", + "display_name": "SLCR Registers", + "base_address": "0xF8000000", + "range": "3K", + "width": "32", + "usage": "register" + }, + "PS_System_Registers": { + "name": "PS_System_Registers", + "display_name": "PS System Registers", + "base_address": "0xF8001000", + "range": "8252K", + "width": "32", + "usage": "register" + }, + "CPU_Private_Registers": { + "name": "CPU_Private_Registers", + "display_name": "CPU Private Registers", + "base_address": "0xF8900000", + "range": "6156K", + "width": "32", + "usage": "register" + }, + "segment5": { + "name": "segment5", + "display_name": "segment5", + "base_address": "0xFC000000", + "range": "32M", + "width": "32", + "usage": "register" + }, + "segment6": { + "name": "segment6", + "display_name": "segment6", + "base_address": "0xFFFC0000", + "range": "256K", + "width": "32", + "usage": "register" + } + } + } + } + } + } + }, + "rst_ps7_0_100M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "design_2_rst_ps7_0_100M_0", + "xci_path": "ip\\design_2_rst_ps7_0_100M_0\\design_2_rst_ps7_0_100M_0.xci", + "inst_hier_path": "PS/rst_ps7_0_100M" + }, + "xlconcat_0": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "xci_name": "design_2_xlconcat_0_0", + "xci_path": "ip\\design_2_xlconcat_0_0\\design_2_xlconcat_0_0.xci", + "inst_hier_path": "PS/xlconcat_0", + "parameters": { + "NUM_PORTS": { + "value": "1" + } + } + }, + "xlconstant_0": { + "vlnv": "xilinx.com:ip:xlconstant:1.1", + "xci_name": "design_2_xlconstant_0_0", + "xci_path": "ip\\design_2_xlconstant_0_0\\design_2_xlconstant_0_0.xci", + "inst_hier_path": "PS/xlconstant_0" + } + }, + "interface_nets": { + "S_AXI_ACP_1": { + "interface_ports": [ + "S_AXI_HP0", + "processing_system7_0/S_AXI_HP0" + ] + }, + "S_AXI_ACP_2": { + "interface_ports": [ + "S_AXI_ACP", + "processing_system7_0/S_AXI_ACP" + ] + }, + "processing_system7_0_DDR": { + "interface_ports": [ + "DDR", + "processing_system7_0/DDR" + ] + }, + "processing_system7_0_FIXED_IO": { + "interface_ports": [ + "FIXED_IO", + "processing_system7_0/FIXED_IO" + ] + }, + "processing_system7_0_M_AXI_GP0": { + "interface_ports": [ + "M_AXI_GP0", + "processing_system7_0/M_AXI_GP0" + ] + } + }, + "nets": { + "In0_1": { + "ports": [ + "In0", + "xlconcat_0/In0" + ] + }, + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "processing_system7_0/FCLK_CLK0", + "FCLK_CLK0", + "processing_system7_0/M_AXI_GP0_ACLK", + "processing_system7_0/S_AXI_HP0_ACLK", + "rst_ps7_0_100M/slowest_sync_clk", + "processing_system7_0/S_AXI_ACP_ACLK" + ] + }, + "processing_system7_0_FCLK_CLK3": { + "ports": [ + "processing_system7_0/FCLK_CLK3", + "FCLK_CLK3" + ] + }, + "processing_system7_0_FCLK_RESET0_N": { + "ports": [ + "processing_system7_0/FCLK_RESET0_N", + "rst_ps7_0_100M/ext_reset_in" + ] + }, + "rst_ps7_0_100M_peripheral_aresetn": { + "ports": [ + "rst_ps7_0_100M/peripheral_aresetn", + "peripheral_aresetn" + ] + }, + "xlconcat_0_dout": { + "ports": [ + "xlconcat_0/dout", + "processing_system7_0/IRQ_F2P" + ] + }, + "xlconstant_0_dout": { + "ports": [ + "xlconstant_0/dout", + "processing_system7_0/SDIO0_WP" + ] + } + } + }, + "ZYNQ_BASE": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXIL": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "BUTTON_0": { + "direction": "I", + "left": "3", + "right": "0" + }, + "HDMI_CLK_N_0": { + "direction": "O" + }, + "HDMI_CLK_P_0": { + "direction": "O" + }, + "HDMI_DATA_N_0": { + "direction": "O", + "left": "2", + "right": "0" + }, + "HDMI_DATA_P_0": { + "direction": "O", + "left": "2", + "right": "0" + }, + "LED_0": { + "direction": "O", + "left": "3", + "right": "0" + }, + "M_AXI_ACLK": { + "type": "clk", + "direction": "I" + }, + "M_AXI_ARESETN": { + "type": "rst", + "direction": "I" + }, + "RGB_LED_0": { + "direction": "O", + "left": "5", + "right": "0" + }, + "SWITCH_0": { + "direction": "I", + "left": "3", + "right": "0" + }, + "VIDEO_CLK": { + "direction": "I" + }, + "VIDEO_INTERRUPT": { + "direction": "O" + } + }, + "components": { + "zynq_base_hdmi_0": { + "vlnv": "xilinx.com:user:zynq_base_hdmi:1.0", + "xci_name": "design_2_zynq_base_hdmi_0_0", + "xci_path": "ip\\design_2_zynq_base_hdmi_0_0\\design_2_zynq_base_hdmi_0_0.xci", + "inst_hier_path": "ZYNQ_BASE/zynq_base_hdmi_0", + "parameters": { + "FIFO_AWIDTH": { + "value": "12" + }, + "HAS_HDMI": { + "value": "true" + }, + "HAS_VGA_OUTPUTS": { + "value": "false" + } + }, + "interface_ports": { + "M_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "M_AXI", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "M_AXI": { + "range": "4G", + "width": "32" + } + } + } + } + }, + "interface_nets": { + "ps7_0_axi_periph_M00_AXI": { + "interface_ports": [ + "S_AXIL", + "zynq_base_hdmi_0/S_AXIL" + ] + }, + "zynq_base_hdmi_0_M_AXI": { + "interface_ports": [ + "M_AXI", + "zynq_base_hdmi_0/M_AXI" + ] + } + }, + "nets": { + "BUTTON_0_1": { + "ports": [ + "BUTTON_0", + "zynq_base_hdmi_0/BUTTON" + ] + }, + "SWITCH_0_1": { + "ports": [ + "SWITCH_0", + "zynq_base_hdmi_0/SWITCH" + ] + }, + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "M_AXI_ACLK", + "zynq_base_hdmi_0/M_AXI_ACLK", + "zynq_base_hdmi_0/S_AXIL_ACLK" + ] + }, + "processing_system7_0_FCLK_CLK3": { + "ports": [ + "VIDEO_CLK", + "zynq_base_hdmi_0/VIDEO_CLK" + ] + }, + "rst_ps7_0_100M_peripheral_aresetn": { + "ports": [ + "M_AXI_ARESETN", + "zynq_base_hdmi_0/M_AXI_ARESETN", + "zynq_base_hdmi_0/S_AXIL_ARESETN", + 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"resolve_type": "generated", "format": "long", "usage": "all" } ], + "SIZE_FACTOR": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "BIG_ENDIAN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "3" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": 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"long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "S_AXIS_TDATA" } ], + "TLAST": [ { "physical_name": "S_AXIS_TLAST" } ], + "TUSER": [ { "physical_name": "S_AXIS_TUSER" } ], + "TVALID": [ { "physical_name": "S_AXIS_TVALID" } ], + "TREADY": [ { "physical_name": "S_AXIS_TREADY" } ] + } + }, + "AXIS_ARESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "AXIS_ARESETN" } ] + } + }, + "AXIS_ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "AXIS_ACLK" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0/design_2_axis_video_filter_0_0.xci similarity index 98% rename from Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xci rename to Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0/design_2_axis_video_filter_0_0.xci index 2dade27..55140a1 100644 --- a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0/design_1_axis_video_filter_0_0.xci +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0/design_2_axis_video_filter_0_0.xci @@ -1,15 +1,15 @@ { "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { - "xci_name": "design_1_axis_video_filter_0_0", + "xci_name": "design_2_axis_video_filter_0_0", "cell_name": "axis_video_filter_0", "component_reference": "xilinx.com:module_ref:axis_video_filter:1.0", "ip_revision": "1", - "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0", "parameters": { "component_parameters": { "COEFF_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Component_Name": [ { "value": "design_1_axis_video_filter_0_0", "resolve_type": "user", "usage": "all" } ] + "Component_Name": [ { "value": "design_2_axis_video_filter_0_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { "COEFF_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ] @@ -31,7 +31,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "1" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0" } ], + "OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_2/ip/design_2_axis_video_filter_0_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2023.1" } ], diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xci b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xci new file mode 100644 index 0000000..b1eb993 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ip/design_2_processing_system7_0_0/design_2_processing_system7_0_0.xci @@ -0,0 +1,1692 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_2_processing_system7_0_0", + "cell_name": "PS/processing_system7_0", + "component_reference": "xilinx.com:ip:processing_system7:5.5", + "ip_revision": "6", + "gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_2/ip/design_2_processing_system7_0_0", + "parameters": { + "component_parameters": { + "PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_DDR_RAM_HIGHADDR": [ { "value": "0x3FFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART1_BASEADDR": [ { "value": "0xE0001000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART1_HIGHADDR": [ { "value": "0xE0001FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_I2C0_BASEADDR": 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"value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C0_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C_RESET_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C_RESET_SELECT": [ { "value": "Share reset pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C1_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C1_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_APU_CLK_RATIO_ENABLE": [ { "value": "6:2:1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET0_PERIPHERAL_FREQMHZ": [ { "value": "1000 Mbps", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET1_PERIPHERAL_FREQMHZ": [ { "value": "1000 Mbps", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CPU_PERIPHERAL_CLKSRC": [ { "value": "ARM PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_DDR_PERIPHERAL_CLKSRC": [ { "value": "DDR PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_QSPI_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SDIO_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UART_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SPI_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_CAN_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK0_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK1_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK2_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK3_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET0_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET1_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_CAN0_PERIPHERAL_CLKSRC": [ { "value": "External", "resolve_type": "user", "usage": "all" } ], + "PCW_CAN1_PERIPHERAL_CLKSRC": [ { "value": "External", "resolve_type": "user", "usage": "all" } ], + "PCW_TPIU_PERIPHERAL_CLKSRC": [ { "value": "External", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC0_CLK0_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC0_CLK1_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC0_CLK2_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC1_CLK0_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC1_CLK1_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC1_CLK2_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ], + "PCW_WDT_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ], + "PCW_DCI_PERIPHERAL_CLKSRC": [ { "value": "DDR PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_PCAP_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_USB_RESET_POLARITY": [ { "value": "Active Low", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET_RESET_POLARITY": [ { "value": "Active Low", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C_RESET_POLARITY": [ { "value": "Active Low", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_0_PULLUP": [ { "value": "enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_0_IOTYPE": [ { "value": "LVCMOS 3.3V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_0_DIRECTION": [ { "value": "inout", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_0_SLEW": [ { "value": "slow", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_1_PULLUP": [ { "value": "enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_1_IOTYPE": [ { "value": "LVCMOS 3.3V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_1_DIRECTION": [ { "value": "out", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_1_SLEW": [ { "value": "slow", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_2_PULLUP": [ { "value": "disabled", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_2_IOTYPE": [ { "value": "LVCMOS 3.3V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_2_DIRECTION": [ { "value": "inout", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_2_SLEW": [ { "value": "slow", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_3_PULLUP": [ { "value": "disabled", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_3_IOTYPE": [ { "value": "LVCMOS 3.3V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_MIO_3_DIRECTION": [ { "value": "inout", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], 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"M01_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A00_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + 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"is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_2_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "M_AXI_ACLK" } ] + } + }, + "S_AXIL_ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "S_AXIL_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_2_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "S_AXIL_ACLK" } ] + } + } + }, + "address_spaces": { + "M_AXI": { + "range": "4294967296", + "width": "32" + } + }, + "memory_maps": { + "S_AXIL": { + "address_blocks": { + "reg0": { + "base_address": "0", + "range": "65536", + "usage": "register" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui new file mode 100644 index 0000000..fd4a673 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_1fdbff51.ui @@ -0,0 +1,59 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.22367", + "Default View_TopLeft":"-326,-2", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace port DDR -pg 1 -lvl 5 -x 1260 -y 110 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 5 -x 1260 -y 140 -defaultsOSRD +preplace port port-id_HDMI_CLK_N -pg 1 -lvl 5 -x 1260 -y 300 -defaultsOSRD +preplace port port-id_HDMI_CLK_P -pg 1 -lvl 5 -x 1260 -y 330 -defaultsOSRD +preplace portBus BUTTON -pg 1 -lvl 0 -x 0 -y 350 -defaultsOSRD +preplace portBus HDMI_DATA_N -pg 1 -lvl 5 -x 1260 -y 360 -defaultsOSRD +preplace portBus HDMI_DATA_P -pg 1 -lvl 5 -x 1260 -y 390 -defaultsOSRD +preplace portBus LED -pg 1 -lvl 5 -x 1260 -y 420 -defaultsOSRD +preplace portBus RGB_LED -pg 1 -lvl 5 -x 1260 -y 450 -defaultsOSRD +preplace portBus SWITCH -pg 1 -lvl 0 -x 0 -y 410 -defaultsOSRD +preplace inst AXI_Intercon -pg 1 -lvl 2 -x 470 -y 150 -defaultsOSRD +preplace inst PS -pg 1 -lvl 3 -x 830 -y 170 -defaultsOSRD +preplace inst ZYNQ_BASE -pg 1 -lvl 3 -x 830 -y 380 -defaultsOSRD +preplace inst axis_downsizer_0 -pg 1 -lvl 1 -x 150 -y 730 -defaultsOSRD +preplace inst axi_2d_mmvs_0 -pg 1 -lvl 2 -x 470 -y 1010 -defaultsOSRD +preplace inst axis_upsizer_0 -pg 1 -lvl 3 -x 830 -y 740 -defaultsOSRD +preplace inst axis_linemem_single_0 -pg 1 -lvl 4 -x 1130 -y 810 -defaultsOSRD +preplace inst axis_video_filter_0 -pg 1 -lvl 2 -x 470 -y 740 -defaultsOSRD +preplace netloc BUTTON_0_1 1 0 3 NJ 350 N 350 NJ +preplace netloc SWITCH_0_1 1 0 3 NJ 410 N 410 NJ +preplace netloc processing_system7_0_FCLK_CLK0 1 1 3 310 40 650 40 1020 +preplace netloc processing_system7_0_FCLK_CLK3 1 2 2 670 10 1030 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 3 340 240 660 60 980 +preplace netloc zynq_base_hdmi_0_HDMI_CLK_N 1 3 2 NJ 330 1230 +preplace netloc zynq_base_hdmi_0_HDMI_CLK_P 1 3 2 NJ 350 1240 +preplace netloc zynq_base_hdmi_0_HDMI_DATA_N 1 3 2 NJ 370 1230 +preplace netloc zynq_base_hdmi_0_HDMI_DATA_P 1 3 2 NJ 390 N +preplace netloc zynq_base_hdmi_0_LED 1 3 2 NJ 410 1240 +preplace netloc zynq_base_hdmi_0_RGB_LED 1 3 2 NJ 430 1230 +preplace netloc zynq_base_hdmi_0_VIDEO_INTERRUPT 1 2 2 680 30 1010 +preplace netloc Net 1 0 4 30 810 290J 630 660 660 1000 +preplace netloc Net1 1 0 4 20 650 270J 610 680 610 1020 +preplace netloc axi_mem_intercon_M00_AXI 1 2 1 630 130n +preplace netloc processing_system7_0_DDR 1 3 2 NJ 120 1230 +preplace netloc processing_system7_0_FIXED_IO 1 3 2 NJ 140 N +preplace netloc processing_system7_0_M_AXI_GP0 1 1 3 340 20 NJ 20 990 +preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 640 110n +preplace netloc zynq_base_hdmi_0_M_AXI 1 1 3 320 50 NJ 50 1000 +preplace netloc axis_upsizer_0_M_AXIS 1 1 3 340 650 NJ 650 990 +preplace netloc axis_video_filter_0_M_AXIS 1 2 1 630 720n +preplace netloc axis_downsizer_0_M_AXIS 1 1 3 280J 620 NJ 620 1030 +preplace netloc axis_linemem_single_0_m_axis 1 1 4 330 640 NJ 640 NJ 640 1230 +preplace netloc axi_2d_mmvs_0_M_AXIS 1 0 3 30 600 NJ 600 600 +preplace netloc AXI_Intercon_M00_AXI2 1 1 2 310 260 620 +preplace netloc AXI_Intercon_M00_AXI3 1 1 2 300 250 610 +preplace netloc S00_AXI_2_1 1 1 2 270 270 610 +preplace netloc AXI_Intercon_M00_AXI_4 1 2 1 630 170n +levelinfo -pg 1 0 150 470 830 1130 1260 +pagesize -pg 1 -db -bbox -sgen -140 0 1440 1100 +" +} + diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_3b5c004.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_3b5c004.ui new file mode 100644 index 0000000..d280402 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_3b5c004.ui @@ -0,0 +1,35 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.61965", + "Default View_TopLeft":"-379,-7", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace port M00_AXI -pg 1 -lvl 2 -x 630 -y 110 -defaultsOSRD +preplace port M00_AXI1 -pg 1 -lvl 2 -x 630 -y 330 -defaultsOSRD +preplace port S00_AXI -pg 1 -lvl 0 -x -10 -y 50 -defaultsOSRD +preplace port S00_AXI1 -pg 1 -lvl 0 -x -10 -y 250 -defaultsOSRD +preplace port M00_AXI2 -pg 1 -lvl 2 -x 630 -y 360 -defaultsOSRD +preplace port M00_AXI3 -pg 1 -lvl 2 -x 630 -y 390 -defaultsOSRD +preplace port S00_AXI_2 -pg 1 -lvl 0 -x -10 -y 610 -defaultsOSRD +preplace port M00_AXI_4 -pg 1 -lvl 2 -x 630 -y 670 -defaultsOSRD +preplace port port-id_ACLK -pg 1 -lvl 0 -x -10 -y 280 -defaultsOSRD +preplace port port-id_S00_ARESETN -pg 1 -lvl 0 -x -10 -y 310 -defaultsOSRD +preplace inst axi_mem_intercon -pg 1 -lvl 1 -x 450 -y 370 -defaultsOSRD +preplace inst ps7_0_axi_periph -pg 1 -lvl 1 -x 450 -y 110 -defaultsOSRD +preplace inst axi_interconnect_0 -pg 1 -lvl 1 -x 450 -y 670 -defaultsOSRD +preplace netloc processing_system7_0_FCLK_CLK0 1 0 1 300 70n +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 1 310 90n +preplace netloc axi_mem_intercon_M00_AXI 1 1 1 590J 330n +preplace netloc processing_system7_0_M_AXI_GP0 1 0 1 NJ 50 +preplace netloc ps7_0_axi_periph_M00_AXI 1 1 1 NJ 110 +preplace netloc zynq_base_hdmi_0_M_AXI 1 0 1 10J 250n +preplace netloc axi_mem_intercon_M01_AXI 1 1 1 590 360n +preplace netloc axi_mem_intercon_M02_AXI 1 1 1 N 390 +preplace netloc S00_AXI_1_1 1 0 1 N 610 +preplace netloc axi_interconnect_0_M00_AXI 1 1 1 N 670 +levelinfo -pg 1 -10 450 630 +pagesize -pg 1 -db -bbox -sgen -150 -120 750 810 +" +} + diff --git a/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_9bff7ad4.ui b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_9bff7ad4.ui new file mode 100644 index 0000000..4b36669 --- /dev/null +++ b/Milestone6/milestone6/milestone6.srcs/sources_1/bd/design_2/ui/bd_9bff7ad4.ui @@ -0,0 +1,37 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.6443", + "Default View_TopLeft":"-117,-120", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 +# -string -flagsOSRD +preplace port DDR -pg 1 -lvl 4 -x 1040 -y 140 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 4 -x 1040 -y 170 -defaultsOSRD +preplace port M_AXI_GP0 -pg 1 -lvl 4 -x 1040 -y 250 -defaultsOSRD +preplace port S_AXI_HP0 -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD +preplace port S_AXI_ACP -pg 1 -lvl 0 -x 0 -y 230 -defaultsOSRD +preplace port port-id_FCLK_CLK0 -pg 1 -lvl 4 -x 1040 -y 330 -defaultsOSRD +preplace port port-id_FCLK_CLK3 -pg 1 -lvl 4 -x 1040 -y 530 -defaultsOSRD +preplace portBus In0 -pg 1 -lvl 0 -x 0 -y 320 -defaultsOSRD +preplace portBus peripheral_aresetn -pg 1 -lvl 4 -x 1040 -y 470 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 2 -x 440 -y 280 -defaultsOSRD +preplace inst rst_ps7_0_100M -pg 1 -lvl 3 -x 840 -y 430 -defaultsOSRD +preplace inst xlconcat_0 -pg 1 -lvl 1 -x 120 -y 320 -defaultsOSRD +preplace inst xlconstant_0 -pg 1 -lvl 2 -x 440 -y 50 -defaultsOSRD +preplace netloc In0_1 1 0 1 NJ 320 +preplace netloc processing_system7_0_FCLK_CLK0 1 1 3 220 470 660 320 1020J +preplace netloc processing_system7_0_FCLK_CLK3 1 2 2 670J 330 1010J +preplace netloc processing_system7_0_FCLK_RESET0_N 1 2 1 N 410 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 3 1 NJ 470 +preplace netloc xlconcat_0_dout 1 1 1 210J 320n +preplace netloc xlconstant_0_dout 1 2 1 660 50n +preplace netloc S_AXI_ACP_1 1 0 2 NJ 260 NJ +preplace netloc processing_system7_0_DDR 1 2 2 670J 140 NJ +preplace netloc processing_system7_0_FIXED_IO 1 2 2 NJ 170 NJ +preplace netloc processing_system7_0_M_AXI_GP0 1 2 2 NJ 250 NJ +preplace netloc S_AXI_ACP_2 1 0 2 NJ 230 220 +levelinfo -pg 1 0 120 440 840 1040 +pagesize -pg 1 -db -bbox -sgen -120 -20 1260 550 +" +} + diff --git a/Milestone6/milestone6/milestone6.xpr b/Milestone6/milestone6/milestone6.xpr index 07f7c3d..f66b857 100644 --- a/Milestone6/milestone6/milestone6.xpr +++ b/Milestone6/milestone6/milestone6.xpr @@ -61,20 +61,20 @@ + + + + + + + +