M4: Blockdesign / Hardware

Milestone4/es_milestone4/.gitignore

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+# Created by https://www.toptal.com/developers/gitignore/api/vivado
+# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
+
+### Vivado ###
+#########################################################################################################
+##	This is an example .gitignore file for Vivado, please treat it as an example as
+##	it might not be complete. In addition, XAPP 1165 should be followed.
+#########
+#Exclude all
+*
+!*/
+!.gitignore
+###########################################################################
+##	VIVADO
+#Source files:
+#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
+!*.vhd
+!*.v
+!*.sv
+!*.bd
+!*.edif
+#IP files
+#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
+#.xci + .dcp: implementation possible but not re-synthesis
+#*.xci(www.spiritconsortium.org)
+!*.xci
+#.xcix: Core container file
+#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
+!*.xcix
+#*.dcp(checkpoint files)
+!*.dcp
+!*.vds
+!*.pb
+#All bd comments and layout coordinates are stored within .ui
+!*.ui
+!*.ooc
+#System Generator
+!*.mdl
+!*.slx
+!*.bxml
+#Simulation logic analyzer
+!*.wcfg
+!*.coe
+#MIG
+!*.prj
+!*.mem
+#Project files
+#XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
+#Do NOT ignore *.xpr files
+!*.xpr
+#Include *.xml files for 2013.4 or earlier version
+!*.xml
+#Constraint files
+#Do NOT ignore *.xdc files
+!*.xdc
+#TCL - files
+!*.tcl
+#Journal - files
+!*.jou
+#Reports
+!*.rpt
+!*.txt
+!*.vdi
+#C-files
+!*.c
+!*.h
+!*.elf
+!*.bmm
+!*.xmp
+
+# End of https://www.toptal.com/developers/gitignore/api/vivado
+
+# Vidado project directories which are not needed
+.Xil/
+*.cache/
+*.hw/
+*.ip_user_files/
+*.runs/
+*.sim/
+# design checkpoint file
+*.dcp
+
+# ignore Vivado log files
+*.log
+*.jou
+vivado_pid*.str

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/design_1.bxml

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+<?xml version="1.0" encoding="UTF-8"?>
+<Root MajorVersion="0" MinorVersion="40">
+  <CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
+    <Description>Composite Fileset</Description>
+    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1733047732"/>
+    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1733047732"/>
+    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1733047732"/>
+    <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1733047732"/>
+    <FileCollection Name="SOURCES" Type="SOURCES">
+      <File Name="synth\design_1.vhd" Type="VHDL">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="sim\design_1.vhd" Type="VHDL">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SIMULATION"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="design_1_ooc.xdc" Type="XDC">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="OUT_OF_CONTEXT"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="hw_handoff\design_1.hwh" Type="HwHandoff">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="design_1.bda">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="synth\design_1.hwdef">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="sim\design_1.protoinst">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SIMULATION"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+    </FileCollection>
+  </CompositeFile>
+</Root>

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/design_1_ooc.xdc

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+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# This constraints file contains default clock frequencies to be used during
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
+# This constraints file is not used in normal top-down synthesis (default flow
+# of Vivado)
+################################################################################
+create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0]
+create_clock -name processing_system7_0_FCLK_CLK1 -period 8 [get_pins processing_system7_0/FCLK_CLK1]
+create_clock -name processing_system7_0_FCLK_CLK2 -period 5 [get_pins processing_system7_0/FCLK_CLK2]
+create_clock -name processing_system7_0_FCLK_CLK3 -period 15 [get_pins processing_system7_0/FCLK_CLK3]
+
+################################################################################

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd

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+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+--Date        : Sun Dec  1 11:08:22 2024
+--Host        : BiermannSurface running 64-bit major release  (build 9200)
+--Command     : generate_target design_1_wrapper.bd
+--Design      : design_1_wrapper
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity design_1_wrapper is
+  port (
+    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+    DDR_cas_n : inout STD_LOGIC;
+    DDR_ck_n : inout STD_LOGIC;
+    DDR_ck_p : inout STD_LOGIC;
+    DDR_cke : inout STD_LOGIC;
+    DDR_cs_n : inout STD_LOGIC;
+    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_odt : inout STD_LOGIC;
+    DDR_ras_n : inout STD_LOGIC;
+    DDR_reset_n : inout STD_LOGIC;
+    DDR_we_n : inout STD_LOGIC;
+    FIXED_IO_ddr_vrn : inout STD_LOGIC;
+    FIXED_IO_ddr_vrp : inout STD_LOGIC;
+    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+    FIXED_IO_ps_clk : inout STD_LOGIC;
+    FIXED_IO_ps_porb : inout STD_LOGIC;
+    FIXED_IO_ps_srstb : inout STD_LOGIC;
+    rgbled : out STD_LOGIC_VECTOR ( 5 downto 0 );
+    sw : in STD_LOGIC_VECTOR ( 2 downto 0 )
+  );
+end design_1_wrapper;
+
+architecture STRUCTURE of design_1_wrapper is
+  component design_1 is
+  port (
+    DDR_cas_n : inout STD_LOGIC;
+    DDR_cke : inout STD_LOGIC;
+    DDR_ck_n : inout STD_LOGIC;
+    DDR_ck_p : inout STD_LOGIC;
+    DDR_cs_n : inout STD_LOGIC;
+    DDR_reset_n : inout STD_LOGIC;
+    DDR_odt : inout STD_LOGIC;
+    DDR_ras_n : inout STD_LOGIC;
+    DDR_we_n : inout STD_LOGIC;
+    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+    FIXED_IO_ddr_vrn : inout STD_LOGIC;
+    FIXED_IO_ddr_vrp : inout STD_LOGIC;
+    FIXED_IO_ps_srstb : inout STD_LOGIC;
+    FIXED_IO_ps_clk : inout STD_LOGIC;
+    FIXED_IO_ps_porb : inout STD_LOGIC;
+    sw : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    rgbled : out STD_LOGIC_VECTOR ( 5 downto 0 )
+  );
+  end component design_1;
+begin
+design_1_i: component design_1
+     port map (
+      DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
+      DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
+      DDR_cas_n => DDR_cas_n,
+      DDR_ck_n => DDR_ck_n,
+      DDR_ck_p => DDR_ck_p,
+      DDR_cke => DDR_cke,
+      DDR_cs_n => DDR_cs_n,
+      DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
+      DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
+      DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
+      DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
+      DDR_odt => DDR_odt,
+      DDR_ras_n => DDR_ras_n,
+      DDR_reset_n => DDR_reset_n,
+      DDR_we_n => DDR_we_n,
+      FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
+      FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
+      FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
+      FIXED_IO_ps_clk => FIXED_IO_ps_clk,
+      FIXED_IO_ps_porb => FIXED_IO_ps_porb,
+      FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
+      rgbled(5 downto 0) => rgbled(5 downto 0),
+      sw(2 downto 0) => sw(2 downto 0)
+    );
+end STRUCTURE;

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_ooc.xdc

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+# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of AMD and is protected under U.S. and international copyright
+# and other intellectual property laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# AMD, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) AMD shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or AMD had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# AMD products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of AMD products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 10 -name aclk [get_ports aclk]
+
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_stub.v

@@ -0,0 +1,89 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Sun Dec  1 11:10:36 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_stub.v
+// Design      : design_1_auto_pc_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "axi_protocol_converter_v2_1_28_axi_protocol_converter,Vivado 2023.1" *)
+module design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr, 
+  s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, 
+  s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, 
+  s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, 
+  s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, 
+  s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, 
+  s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid, 
+  m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp, 
+  m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready, 
+  m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
+/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */
+/* synthesis syn_force_seq_prim="aclk" */;
+  input aclk /* synthesis syn_isclock = 1 */;
+  input aresetn;
+  input [11:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [3:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awqos;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [11:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wlast;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [11:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [11:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [3:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arqos;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [11:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rlast;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output [31:0]m_axi_awaddr;
+  output [2:0]m_axi_awprot;
+  output m_axi_awvalid;
+  input m_axi_awready;
+  output [31:0]m_axi_wdata;
+  output [3:0]m_axi_wstrb;
+  output m_axi_wvalid;
+  input m_axi_wready;
+  input [1:0]m_axi_bresp;
+  input m_axi_bvalid;
+  output m_axi_bready;
+  output [31:0]m_axi_araddr;
+  output [2:0]m_axi_arprot;
+  output m_axi_arvalid;
+  input m_axi_arready;
+  input [31:0]m_axi_rdata;
+  input [1:0]m_axi_rresp;
+  input m_axi_rvalid;
+  output m_axi_rready;
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.h

@@ -0,0 +1,573 @@
+#ifndef IP_DESIGN_1_AUTO_PC_0_H_
+#define IP_DESIGN_1_AUTO_PC_0_H_
+
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "design_1_auto_pc_0_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
+{
+public:
+
+  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
+{
+public:
+
+  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
+{
+public:
+
+  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
+{
+public:
+
+  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
+{
+public:
+
+  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
+  sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
+  xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_DESIGN_1_AUTO_PC_0_H_

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v

@@ -0,0 +1,354 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 28
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_auto_pc_0 (
+  aclk,
+  aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wid,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [11 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [3 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [1 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
+input wire [11 : 0] s_axi_wid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [11 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [11 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [3 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [1 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [11 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4,\
+ NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
+4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_protocol_converter_v2_1_28_axi_protocol_converter #(
+    .C_FAMILY("zynq"),
+    .C_M_AXI_PROTOCOL(2),
+    .C_S_AXI_PROTOCOL(1),
+    .C_IGNORE_ID(0),
+    .C_AXI_ID_WIDTH(12),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_TRANSLATION_MODE(2)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(4'H0),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(s_axi_wid),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(4'H0),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(12'H000),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(12'H000),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(1'H1),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0_sc.h

@@ -0,0 +1,98 @@
+#ifndef IP_DESIGN_1_AUTO_PC_0_SC_H_
+#define IP_DESIGN_1_AUTO_PC_0_SC_H_
+
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_protocol_converter;
+
+class DllExport design_1_auto_pc_0_sc : public sc_core::sc_module
+{
+public:
+
+  design_1_auto_pc_0_sc(const sc_core::sc_module_name& nm);
+  virtual ~design_1_auto_pc_0_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* target_rd_socket;
+  xtlm::xtlm_aximm_target_socket* target_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_protocol_converter* mp_impl;
+
+private:
+
+  design_1_auto_pc_0_sc(const design_1_auto_pc_0_sc&);
+  const design_1_auto_pc_0_sc& operator=(const design_1_auto_pc_0_sc&);
+
+};
+
+#endif // IP_DESIGN_1_AUTO_PC_0_SC_H_

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0_stub.sv

@@ -0,0 +1,197 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    design_1_auto_pc_0_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module design_1_auto_pc_0 (
+  input bit_as_bool aclk,
+  input bit_as_bool aresetn,
+  input bit [11 : 0] s_axi_awid,
+  input bit [31 : 0] s_axi_awaddr,
+  input bit [3 : 0] s_axi_awlen,
+  input bit [2 : 0] s_axi_awsize,
+  input bit [1 : 0] s_axi_awburst,
+  input bit [1 : 0] s_axi_awlock,
+  input bit [3 : 0] s_axi_awcache,
+  input bit [2 : 0] s_axi_awprot,
+  input bit [3 : 0] s_axi_awqos,
+  input bit_as_bool s_axi_awvalid,
+  output bit_as_bool s_axi_awready,
+  input bit [11 : 0] s_axi_wid,
+  input bit [31 : 0] s_axi_wdata,
+  input bit [3 : 0] s_axi_wstrb,
+  input bit_as_bool s_axi_wlast,
+  input bit_as_bool s_axi_wvalid,
+  output bit_as_bool s_axi_wready,
+  output bit [11 : 0] s_axi_bid,
+  output bit [1 : 0] s_axi_bresp,
+  output bit_as_bool s_axi_bvalid,
+  input bit_as_bool s_axi_bready,
+  input bit [11 : 0] s_axi_arid,
+  input bit [31 : 0] s_axi_araddr,
+  input bit [3 : 0] s_axi_arlen,
+  input bit [2 : 0] s_axi_arsize,
+  input bit [1 : 0] s_axi_arburst,
+  input bit [1 : 0] s_axi_arlock,
+  input bit [3 : 0] s_axi_arcache,
+  input bit [2 : 0] s_axi_arprot,
+  input bit [3 : 0] s_axi_arqos,
+  input bit_as_bool s_axi_arvalid,
+  output bit_as_bool s_axi_arready,
+  output bit [11 : 0] s_axi_rid,
+  output bit [31 : 0] s_axi_rdata,
+  output bit [1 : 0] s_axi_rresp,
+  output bit_as_bool s_axi_rlast,
+  output bit_as_bool s_axi_rvalid,
+  input bit_as_bool s_axi_rready,
+  output bit [31 : 0] m_axi_awaddr,
+  output bit [2 : 0] m_axi_awprot,
+  output bit_as_bool m_axi_awvalid,
+  input bit_as_bool m_axi_awready,
+  output bit [31 : 0] m_axi_wdata,
+  output bit [3 : 0] m_axi_wstrb,
+  output bit_as_bool m_axi_wvalid,
+  input bit_as_bool m_axi_wready,
+  input bit [1 : 0] m_axi_bresp,
+  input bit_as_bool m_axi_bvalid,
+  output bit_as_bool m_axi_bready,
+  output bit [31 : 0] m_axi_araddr,
+  output bit [2 : 0] m_axi_arprot,
+  output bit_as_bool m_axi_arvalid,
+  input bit_as_bool m_axi_arready,
+  input bit [31 : 0] m_axi_rdata,
+  input bit [1 : 0] m_axi_rresp,
+  input bit_as_bool m_axi_rvalid,
+  output bit_as_bool m_axi_rready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module design_1_auto_pc_0 (aclk,aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wid,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
+(* integer foreign = "SystemC";
+*);
+  input bit aclk;
+  input bit aresetn;
+  input bit [11 : 0] s_axi_awid;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [3 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [1 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [11 : 0] s_axi_wid;
+  input bit [31 : 0] s_axi_wdata;
+  input bit [3 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [11 : 0] s_axi_bid;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [11 : 0] s_axi_arid;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [3 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [1 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [11 : 0] s_axi_rid;
+  output wire [31 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [2 : 0] m_axi_awprot;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [31 : 0] m_axi_wdata;
+  output wire [3 : 0] m_axi_wstrb;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [2 : 0] m_axi_arprot;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [31 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/src/axi_protocol_converter.h

@@ -0,0 +1,71 @@
+// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+#ifndef _axi_protocol_converter_
+#define _axi_protocol_converter_
+#include <xtlm.h>
+#include <utils/xtlm_aximm_passthru_module.h>
+#include <systemc>
+
+class axi_protocol_converter:public sc_module{
+	public:
+		axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
+		virtual ~axi_protocol_converter();
+		SC_HAS_PROCESS(axi_protocol_converter);
+	xtlm::xtlm_aximm_target_socket* target_rd_socket;
+	xtlm::xtlm_aximm_target_socket* target_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket*  initiator_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+  	sc_in<bool> aclk;
+	sc_in<bool> aresetn;
+	private:
+	xtlm::xtlm_aximm_passthru_module *P1;
+	xtlm::xtlm_aximm_passthru_module *P2;	
+};
+
+#endif
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/synth/design_1_auto_pc_0.v

@@ -0,0 +1,356 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 28
+
+(* X_CORE_INFO = "axi_protocol_converter_v2_1_28_axi_protocol_converter,Vivado 2023.1" *)
+(* CHECK_LICENSE_TYPE = "design_1_auto_pc_0,axi_protocol_converter_v2_1_28_axi_protocol_converter,{}" *)
+(* CORE_GENERATION_INFO = "design_1_auto_pc_0,axi_protocol_converter_v2_1_28_axi_protocol_converter,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=28,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WID\
+TH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_auto_pc_0 (
+  aclk,
+  aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wid,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [11 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [3 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [1 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
+input wire [11 : 0] s_axi_wid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [11 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [11 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [3 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [1 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [11 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4,\
+ NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
+4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_protocol_converter_v2_1_28_axi_protocol_converter #(
+    .C_FAMILY("zynq"),
+    .C_M_AXI_PROTOCOL(2),
+    .C_S_AXI_PROTOCOL(1),
+    .C_IGNORE_ID(0),
+    .C_AXI_ID_WIDTH(12),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_TRANSLATION_MODE(2)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(4'H0),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(s_axi_wid),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(4'H0),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(12'H000),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(12'H000),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(1'H1),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0/constrs_1/new/axil_gpio_ooc.xdc

@@ -0,0 +1 @@
+create_clock -period 8.000 [get_ports S_AXIL_ACLK]

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0/design_1_axil_gpio_0_0_sim_netlist.v

@@ -0,0 +1,528 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Sun Dec  1 11:10:19 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/hs/es-praktikum/Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0/design_1_axil_gpio_0_0_sim_netlist.v
+// Design      : design_1_axil_gpio_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_axil_gpio_0_0,axil_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) 
+(* x_core_info = "axil_gpio,Vivado 2023.1" *) 
+(* NotValidForBitStream *)
+module design_1_axil_gpio_0_0
+   (S_AXIL_ACLK,
+    S_AXIL_ARESETN,
+    S_AXIL_AWADDR,
+    S_AXIL_AWVALID,
+    S_AXIL_AWREADY,
+    S_AXIL_WDATA,
+    S_AXIL_WVALID,
+    S_AXIL_WREADY,
+    S_AXIL_WSTRB,
+    S_AXIL_BVALID,
+    S_AXIL_BREADY,
+    S_AXIL_BRESP,
+    S_AXIL_ARADDR,
+    S_AXIL_ARVALID,
+    S_AXIL_ARREADY,
+    S_AXIL_RDATA,
+    S_AXIL_RVALID,
+    S_AXIL_RREADY,
+    S_AXIL_RRESP,
+    GPI,
+    GPO);
+  (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXIL_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIL_ACLK, ASSOCIATED_BUSIF S_AXIL, ASSOCIATED_RESET S_AXIL_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input S_AXIL_ACLK;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXIL_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input S_AXIL_ARESETN;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [14:0]S_AXIL_AWADDR;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID" *) input S_AXIL_AWVALID;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY" *) output S_AXIL_AWREADY;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL WDATA" *) input [31:0]S_AXIL_WDATA;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL WVALID" *) input S_AXIL_WVALID;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL WREADY" *) output S_AXIL_WREADY;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB" *) input [3:0]S_AXIL_WSTRB;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL BVALID" *) output S_AXIL_BVALID;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL BREADY" *) input S_AXIL_BREADY;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL BRESP" *) output [1:0]S_AXIL_BRESP;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR" *) input [14:0]S_AXIL_ARADDR;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID" *) input S_AXIL_ARVALID;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY" *) output S_AXIL_ARREADY;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL RDATA" *) output [31:0]S_AXIL_RDATA;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL RVALID" *) output S_AXIL_RVALID;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL RREADY" *) input S_AXIL_RREADY;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXIL RRESP" *) output [1:0]S_AXIL_RRESP;
+  input [2:0]GPI;
+  output [5:0]GPO;
+
+  wire \<const0> ;
+  wire \<const1> ;
+  wire [2:0]GPI;
+  wire [5:0]GPO;
+  wire S_AXIL_ACLK;
+  wire [14:0]S_AXIL_ARADDR;
+  wire S_AXIL_ARESETN;
+  wire S_AXIL_ARVALID;
+  wire [14:0]S_AXIL_AWADDR;
+  wire S_AXIL_AWREADY;
+  wire S_AXIL_AWVALID;
+  wire S_AXIL_BREADY;
+  wire S_AXIL_BVALID;
+  wire [5:0]\^S_AXIL_RDATA ;
+  wire S_AXIL_RREADY;
+  wire S_AXIL_RVALID;
+  wire [31:0]S_AXIL_WDATA;
+  wire S_AXIL_WREADY;
+  wire [3:0]S_AXIL_WSTRB;
+  wire S_AXIL_WVALID;
+  wire NLW_U0_S_AXIL_ARREADY_UNCONNECTED;
+  wire [1:0]NLW_U0_S_AXIL_BRESP_UNCONNECTED;
+  wire [31:6]NLW_U0_S_AXIL_RDATA_UNCONNECTED;
+  wire [1:0]NLW_U0_S_AXIL_RRESP_UNCONNECTED;
+
+  assign S_AXIL_ARREADY = \<const1> ;
+  assign S_AXIL_BRESP[1] = \<const0> ;
+  assign S_AXIL_BRESP[0] = \<const0> ;
+  assign S_AXIL_RDATA[31] = \<const0> ;
+  assign S_AXIL_RDATA[30] = \<const0> ;
+  assign S_AXIL_RDATA[29] = \<const0> ;
+  assign S_AXIL_RDATA[28] = \<const0> ;
+  assign S_AXIL_RDATA[27] = \<const0> ;
+  assign S_AXIL_RDATA[26] = \<const0> ;
+  assign S_AXIL_RDATA[25] = \<const0> ;
+  assign S_AXIL_RDATA[24] = \<const0> ;
+  assign S_AXIL_RDATA[23] = \<const0> ;
+  assign S_AXIL_RDATA[22] = \<const0> ;
+  assign S_AXIL_RDATA[21] = \<const0> ;
+  assign S_AXIL_RDATA[20] = \<const0> ;
+  assign S_AXIL_RDATA[19] = \<const0> ;
+  assign S_AXIL_RDATA[18] = \<const0> ;
+  assign S_AXIL_RDATA[17] = \<const0> ;
+  assign S_AXIL_RDATA[16] = \<const0> ;
+  assign S_AXIL_RDATA[15] = \<const0> ;
+  assign S_AXIL_RDATA[14] = \<const0> ;
+  assign S_AXIL_RDATA[13] = \<const0> ;
+  assign S_AXIL_RDATA[12] = \<const0> ;
+  assign S_AXIL_RDATA[11] = \<const0> ;
+  assign S_AXIL_RDATA[10] = \<const0> ;
+  assign S_AXIL_RDATA[9] = \<const0> ;
+  assign S_AXIL_RDATA[8] = \<const0> ;
+  assign S_AXIL_RDATA[7] = \<const0> ;
+  assign S_AXIL_RDATA[6] = \<const0> ;
+  assign S_AXIL_RDATA[5:0] = \^S_AXIL_RDATA [5:0];
+  assign S_AXIL_RRESP[1] = \<const0> ;
+  assign S_AXIL_RRESP[0] = \<const0> ;
+  GND GND
+       (.G(\<const0> ));
+  (* GPI_WIDTH = "3" *) 
+  (* GPO_WIDTH = "6" *) 
+  design_1_axil_gpio_0_0_axil_gpio U0
+       (.GPI(GPI),
+        .GPO(GPO),
+        .S_AXIL_ACLK(S_AXIL_ACLK),
+        .S_AXIL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,S_AXIL_ARADDR[2],1'b0,1'b0}),
+        .S_AXIL_ARESETN(S_AXIL_ARESETN),
+        .S_AXIL_ARREADY(NLW_U0_S_AXIL_ARREADY_UNCONNECTED),
+        .S_AXIL_ARVALID(S_AXIL_ARVALID),
+        .S_AXIL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,S_AXIL_AWADDR[2],1'b0,1'b0}),
+        .S_AXIL_AWREADY(S_AXIL_AWREADY),
+        .S_AXIL_AWVALID(S_AXIL_AWVALID),
+        .S_AXIL_BREADY(S_AXIL_BREADY),
+        .S_AXIL_BRESP(NLW_U0_S_AXIL_BRESP_UNCONNECTED[1:0]),
+        .S_AXIL_BVALID(S_AXIL_BVALID),
+        .S_AXIL_RDATA({NLW_U0_S_AXIL_RDATA_UNCONNECTED[31:6],\^S_AXIL_RDATA }),
+        .S_AXIL_RREADY(S_AXIL_RREADY),
+        .S_AXIL_RRESP(NLW_U0_S_AXIL_RRESP_UNCONNECTED[1:0]),
+        .S_AXIL_RVALID(S_AXIL_RVALID),
+        .S_AXIL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,S_AXIL_WDATA[5:0]}),
+        .S_AXIL_WREADY(S_AXIL_WREADY),
+        .S_AXIL_WSTRB({1'b0,1'b0,1'b0,S_AXIL_WSTRB[0]}),
+        .S_AXIL_WVALID(S_AXIL_WVALID));
+  VCC VCC
+       (.P(\<const1> ));
+endmodule
+
+(* GPI_WIDTH = "3" *) (* GPO_WIDTH = "6" *) (* ORIG_REF_NAME = "axil_gpio" *) 
+module design_1_axil_gpio_0_0_axil_gpio
+   (S_AXIL_ACLK,
+    S_AXIL_ARESETN,
+    S_AXIL_AWADDR,
+    S_AXIL_AWVALID,
+    S_AXIL_AWREADY,
+    S_AXIL_WDATA,
+    S_AXIL_WVALID,
+    S_AXIL_WREADY,
+    S_AXIL_WSTRB,
+    S_AXIL_BVALID,
+    S_AXIL_BREADY,
+    S_AXIL_BRESP,
+    S_AXIL_ARADDR,
+    S_AXIL_ARVALID,
+    S_AXIL_ARREADY,
+    S_AXIL_RDATA,
+    S_AXIL_RVALID,
+    S_AXIL_RREADY,
+    S_AXIL_RRESP,
+    GPI,
+    GPO);
+  input S_AXIL_ACLK;
+  input S_AXIL_ARESETN;
+  input [14:0]S_AXIL_AWADDR;
+  input S_AXIL_AWVALID;
+  output S_AXIL_AWREADY;
+  input [31:0]S_AXIL_WDATA;
+  input S_AXIL_WVALID;
+  output S_AXIL_WREADY;
+  input [3:0]S_AXIL_WSTRB;
+  output S_AXIL_BVALID;
+  input S_AXIL_BREADY;
+  output [1:0]S_AXIL_BRESP;
+  input [14:0]S_AXIL_ARADDR;
+  input S_AXIL_ARVALID;
+  output S_AXIL_ARREADY;
+  output [31:0]S_AXIL_RDATA;
+  output S_AXIL_RVALID;
+  input S_AXIL_RREADY;
+  output [1:0]S_AXIL_RRESP;
+  input [2:0]GPI;
+  output [5:0]GPO;
+
+  wire \<const0> ;
+  wire [2:0]GPI;
+  wire [5:0]GPO;
+  wire S_AXIL_ACLK;
+  wire [14:0]S_AXIL_ARADDR;
+  wire S_AXIL_ARESETN;
+  wire S_AXIL_ARVALID;
+  wire [14:0]S_AXIL_AWADDR;
+  wire S_AXIL_AWREADY;
+  wire S_AXIL_AWVALID;
+  wire S_AXIL_BREADY;
+  wire S_AXIL_BVALID;
+  wire S_AXIL_BVALID_i_1_n_0;
+  wire [5:0]\^S_AXIL_RDATA ;
+  wire \S_AXIL_RDATA[0]_i_1_n_0 ;
+  wire \S_AXIL_RDATA[1]_i_1_n_0 ;
+  wire \S_AXIL_RDATA[2]_i_1_n_0 ;
+  wire \S_AXIL_RDATA[3]_i_1_n_0 ;
+  wire \S_AXIL_RDATA[4]_i_1_n_0 ;
+  wire \S_AXIL_RDATA[5]_i_1_n_0 ;
+  wire \S_AXIL_RDATA[5]_i_2_n_0 ;
+  wire S_AXIL_RREADY;
+  wire S_AXIL_RVALID;
+  wire S_AXIL_RVALID_i_1_n_0;
+  wire [31:0]S_AXIL_WDATA;
+  wire [3:0]S_AXIL_WSTRB;
+  wire S_AXIL_WVALID;
+  wire \gpo_sig[5]_i_2_n_0 ;
+  wire p_0_in;
+
+  assign S_AXIL_ARREADY = \<const0> ;
+  assign S_AXIL_BRESP[1] = \<const0> ;
+  assign S_AXIL_BRESP[0] = \<const0> ;
+  assign S_AXIL_RDATA[31] = \<const0> ;
+  assign S_AXIL_RDATA[30] = \<const0> ;
+  assign S_AXIL_RDATA[29] = \<const0> ;
+  assign S_AXIL_RDATA[28] = \<const0> ;
+  assign S_AXIL_RDATA[27] = \<const0> ;
+  assign S_AXIL_RDATA[26] = \<const0> ;
+  assign S_AXIL_RDATA[25] = \<const0> ;
+  assign S_AXIL_RDATA[24] = \<const0> ;
+  assign S_AXIL_RDATA[23] = \<const0> ;
+  assign S_AXIL_RDATA[22] = \<const0> ;
+  assign S_AXIL_RDATA[21] = \<const0> ;
+  assign S_AXIL_RDATA[20] = \<const0> ;
+  assign S_AXIL_RDATA[19] = \<const0> ;
+  assign S_AXIL_RDATA[18] = \<const0> ;
+  assign S_AXIL_RDATA[17] = \<const0> ;
+  assign S_AXIL_RDATA[16] = \<const0> ;
+  assign S_AXIL_RDATA[15] = \<const0> ;
+  assign S_AXIL_RDATA[14] = \<const0> ;
+  assign S_AXIL_RDATA[13] = \<const0> ;
+  assign S_AXIL_RDATA[12] = \<const0> ;
+  assign S_AXIL_RDATA[11] = \<const0> ;
+  assign S_AXIL_RDATA[10] = \<const0> ;
+  assign S_AXIL_RDATA[9] = \<const0> ;
+  assign S_AXIL_RDATA[8] = \<const0> ;
+  assign S_AXIL_RDATA[7] = \<const0> ;
+  assign S_AXIL_RDATA[6] = \<const0> ;
+  assign S_AXIL_RDATA[5:0] = \^S_AXIL_RDATA [5:0];
+  assign S_AXIL_RRESP[1] = \<const0> ;
+  assign S_AXIL_RRESP[0] = \<const0> ;
+  assign S_AXIL_WREADY = S_AXIL_AWREADY;
+  GND GND
+       (.G(\<const0> ));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT5 #(
+    .INIT(32'hF2220000)) 
+    S_AXIL_BVALID_i_1
+       (.I0(S_AXIL_BVALID),
+        .I1(S_AXIL_BREADY),
+        .I2(S_AXIL_AWVALID),
+        .I3(S_AXIL_WVALID),
+        .I4(S_AXIL_ARESETN),
+        .O(S_AXIL_BVALID_i_1_n_0));
+  FDRE S_AXIL_BVALID_reg
+       (.C(S_AXIL_ACLK),
+        .CE(1'b1),
+        .D(S_AXIL_BVALID_i_1_n_0),
+        .Q(S_AXIL_BVALID),
+        .R(1'b0));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT3 #(
+    .INIT(8'hAC)) 
+    \S_AXIL_RDATA[0]_i_1 
+       (.I0(GPI[0]),
+        .I1(GPO[0]),
+        .I2(S_AXIL_ARADDR[2]),
+        .O(\S_AXIL_RDATA[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT3 #(
+    .INIT(8'hAC)) 
+    \S_AXIL_RDATA[1]_i_1 
+       (.I0(GPI[1]),
+        .I1(GPO[1]),
+        .I2(S_AXIL_ARADDR[2]),
+        .O(\S_AXIL_RDATA[1]_i_1_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT3 #(
+    .INIT(8'hAC)) 
+    \S_AXIL_RDATA[2]_i_1 
+       (.I0(GPI[2]),
+        .I1(GPO[2]),
+        .I2(S_AXIL_ARADDR[2]),
+        .O(\S_AXIL_RDATA[2]_i_1_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT2 #(
+    .INIT(4'h2)) 
+    \S_AXIL_RDATA[3]_i_1 
+       (.I0(GPO[3]),
+        .I1(S_AXIL_ARADDR[2]),
+        .O(\S_AXIL_RDATA[3]_i_1_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair3" *) 
+  LUT2 #(
+    .INIT(4'h2)) 
+    \S_AXIL_RDATA[4]_i_1 
+       (.I0(GPO[4]),
+        .I1(S_AXIL_ARADDR[2]),
+        .O(\S_AXIL_RDATA[4]_i_1_n_0 ));
+  LUT2 #(
+    .INIT(4'h8)) 
+    \S_AXIL_RDATA[5]_i_1 
+       (.I0(S_AXIL_ARESETN),
+        .I1(S_AXIL_ARVALID),
+        .O(\S_AXIL_RDATA[5]_i_1_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair3" *) 
+  LUT2 #(
+    .INIT(4'h2)) 
+    \S_AXIL_RDATA[5]_i_2 
+       (.I0(GPO[5]),
+        .I1(S_AXIL_ARADDR[2]),
+        .O(\S_AXIL_RDATA[5]_i_2_n_0 ));
+  FDRE \S_AXIL_RDATA_reg[0] 
+       (.C(S_AXIL_ACLK),
+        .CE(\S_AXIL_RDATA[5]_i_1_n_0 ),
+        .D(\S_AXIL_RDATA[0]_i_1_n_0 ),
+        .Q(\^S_AXIL_RDATA [0]),
+        .R(1'b0));
+  FDRE \S_AXIL_RDATA_reg[1] 
+       (.C(S_AXIL_ACLK),
+        .CE(\S_AXIL_RDATA[5]_i_1_n_0 ),
+        .D(\S_AXIL_RDATA[1]_i_1_n_0 ),
+        .Q(\^S_AXIL_RDATA [1]),
+        .R(1'b0));
+  FDRE \S_AXIL_RDATA_reg[2] 
+       (.C(S_AXIL_ACLK),
+        .CE(\S_AXIL_RDATA[5]_i_1_n_0 ),
+        .D(\S_AXIL_RDATA[2]_i_1_n_0 ),
+        .Q(\^S_AXIL_RDATA [2]),
+        .R(1'b0));
+  FDRE \S_AXIL_RDATA_reg[3] 
+       (.C(S_AXIL_ACLK),
+        .CE(\S_AXIL_RDATA[5]_i_1_n_0 ),
+        .D(\S_AXIL_RDATA[3]_i_1_n_0 ),
+        .Q(\^S_AXIL_RDATA [3]),
+        .R(1'b0));
+  FDRE \S_AXIL_RDATA_reg[4] 
+       (.C(S_AXIL_ACLK),
+        .CE(\S_AXIL_RDATA[5]_i_1_n_0 ),
+        .D(\S_AXIL_RDATA[4]_i_1_n_0 ),
+        .Q(\^S_AXIL_RDATA [4]),
+        .R(1'b0));
+  FDRE \S_AXIL_RDATA_reg[5] 
+       (.C(S_AXIL_ACLK),
+        .CE(\S_AXIL_RDATA[5]_i_1_n_0 ),
+        .D(\S_AXIL_RDATA[5]_i_2_n_0 ),
+        .Q(\^S_AXIL_RDATA [5]),
+        .R(1'b0));
+  LUT4 #(
+    .INIT(16'hF200)) 
+    S_AXIL_RVALID_i_1
+       (.I0(S_AXIL_RVALID),
+        .I1(S_AXIL_RREADY),
+        .I2(S_AXIL_ARVALID),
+        .I3(S_AXIL_ARESETN),
+        .O(S_AXIL_RVALID_i_1_n_0));
+  FDRE S_AXIL_RVALID_reg
+       (.C(S_AXIL_ACLK),
+        .CE(1'b1),
+        .D(S_AXIL_RVALID_i_1_n_0),
+        .Q(S_AXIL_RVALID),
+        .R(1'b0));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT2 #(
+    .INIT(4'h8)) 
+    S_AXIL_WREADY_INST_0
+       (.I0(S_AXIL_AWVALID),
+        .I1(S_AXIL_WVALID),
+        .O(S_AXIL_AWREADY));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \gpo_sig[5]_i_1 
+       (.I0(S_AXIL_ARESETN),
+        .O(p_0_in));
+  LUT4 #(
+    .INIT(16'h0800)) 
+    \gpo_sig[5]_i_2 
+       (.I0(S_AXIL_WVALID),
+        .I1(S_AXIL_AWVALID),
+        .I2(S_AXIL_AWADDR[2]),
+        .I3(S_AXIL_WSTRB[0]),
+        .O(\gpo_sig[5]_i_2_n_0 ));
+  FDRE #(
+    .INIT(1'b0)) 
+    \gpo_sig_reg[0] 
+       (.C(S_AXIL_ACLK),
+        .CE(\gpo_sig[5]_i_2_n_0 ),
+        .D(S_AXIL_WDATA[0]),
+        .Q(GPO[0]),
+        .R(p_0_in));
+  FDRE #(
+    .INIT(1'b0)) 
+    \gpo_sig_reg[1] 
+       (.C(S_AXIL_ACLK),
+        .CE(\gpo_sig[5]_i_2_n_0 ),
+        .D(S_AXIL_WDATA[1]),
+        .Q(GPO[1]),
+        .R(p_0_in));
+  FDRE #(
+    .INIT(1'b0)) 
+    \gpo_sig_reg[2] 
+       (.C(S_AXIL_ACLK),
+        .CE(\gpo_sig[5]_i_2_n_0 ),
+        .D(S_AXIL_WDATA[2]),
+        .Q(GPO[2]),
+        .R(p_0_in));
+  FDRE #(
+    .INIT(1'b0)) 
+    \gpo_sig_reg[3] 
+       (.C(S_AXIL_ACLK),
+        .CE(\gpo_sig[5]_i_2_n_0 ),
+        .D(S_AXIL_WDATA[3]),
+        .Q(GPO[3]),
+        .R(p_0_in));
+  FDRE #(
+    .INIT(1'b0)) 
+    \gpo_sig_reg[4] 
+       (.C(S_AXIL_ACLK),
+        .CE(\gpo_sig[5]_i_2_n_0 ),
+        .D(S_AXIL_WDATA[4]),
+        .Q(GPO[4]),
+        .R(p_0_in));
+  FDRE #(
+    .INIT(1'b0)) 
+    \gpo_sig_reg[5] 
+       (.C(S_AXIL_ACLK),
+        .CE(\gpo_sig[5]_i_2_n_0 ),
+        .D(S_AXIL_WDATA[5]),
+        .Q(GPO[5]),
+        .R(p_0_in));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0/design_1_axil_gpio_0_0_stub.v

@@ -0,0 +1,45 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Sun Dec  1 11:10:19 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0/design_1_axil_gpio_0_0_stub.v
+// Design      : design_1_axil_gpio_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axil_gpio,Vivado 2023.1" *)
+module design_1_axil_gpio_0_0(S_AXIL_ACLK, S_AXIL_ARESETN, S_AXIL_AWADDR, 
+  S_AXIL_AWVALID, S_AXIL_AWREADY, S_AXIL_WDATA, S_AXIL_WVALID, S_AXIL_WREADY, S_AXIL_WSTRB, 
+  S_AXIL_BVALID, S_AXIL_BREADY, S_AXIL_BRESP, S_AXIL_ARADDR, S_AXIL_ARVALID, S_AXIL_ARREADY, 
+  S_AXIL_RDATA, S_AXIL_RVALID, S_AXIL_RREADY, S_AXIL_RRESP, GPI, GPO)
+/* synthesis syn_black_box black_box_pad_pin="S_AXIL_ARESETN,S_AXIL_AWADDR[14:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[14:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],GPI[2:0],GPO[5:0]" */
+/* synthesis syn_force_seq_prim="S_AXIL_ACLK" */;
+  input S_AXIL_ACLK /* synthesis syn_isclock = 1 */;
+  input S_AXIL_ARESETN;
+  input [14:0]S_AXIL_AWADDR;
+  input S_AXIL_AWVALID;
+  output S_AXIL_AWREADY;
+  input [31:0]S_AXIL_WDATA;
+  input S_AXIL_WVALID;
+  output S_AXIL_WREADY;
+  input [3:0]S_AXIL_WSTRB;
+  output S_AXIL_BVALID;
+  input S_AXIL_BREADY;
+  output [1:0]S_AXIL_BRESP;
+  input [14:0]S_AXIL_ARADDR;
+  input S_AXIL_ARVALID;
+  output S_AXIL_ARREADY;
+  output [31:0]S_AXIL_RDATA;
+  output S_AXIL_RVALID;
+  input S_AXIL_RREADY;
+  output [1:0]S_AXIL_RRESP;
+  input [2:0]GPI;
+  output [5:0]GPO;
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0/sim/design_1_axil_gpio_0_0.vhd

@@ -0,0 +1,168 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axil_gpio:1.0
+-- IP Revision: 7
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axil_gpio_0_0 IS
+  PORT (
+    S_AXIL_ACLK : IN STD_LOGIC;
+    S_AXIL_ARESETN : IN STD_LOGIC;
+    S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    S_AXIL_AWVALID : IN STD_LOGIC;
+    S_AXIL_AWREADY : OUT STD_LOGIC;
+    S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_WVALID : IN STD_LOGIC;
+    S_AXIL_WREADY : OUT STD_LOGIC;
+    S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXIL_BVALID : OUT STD_LOGIC;
+    S_AXIL_BREADY : IN STD_LOGIC;
+    S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    S_AXIL_ARVALID : IN STD_LOGIC;
+    S_AXIL_ARREADY : OUT STD_LOGIC;
+    S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_RVALID : OUT STD_LOGIC;
+    S_AXIL_RREADY : IN STD_LOGIC;
+    S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    GPI : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    GPO : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+  );
+END design_1_axil_gpio_0_0;
+
+ARCHITECTURE design_1_axil_gpio_0_0_arch OF design_1_axil_gpio_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_gpio_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axil_gpio IS
+    GENERIC (
+      GPI_WIDTH : INTEGER;
+      GPO_WIDTH : INTEGER
+    );
+    PORT (
+      S_AXIL_ACLK : IN STD_LOGIC;
+      S_AXIL_ARESETN : IN STD_LOGIC;
+      S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+      S_AXIL_AWVALID : IN STD_LOGIC;
+      S_AXIL_AWREADY : OUT STD_LOGIC;
+      S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_WVALID : IN STD_LOGIC;
+      S_AXIL_WREADY : OUT STD_LOGIC;
+      S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXIL_BVALID : OUT STD_LOGIC;
+      S_AXIL_BREADY : IN STD_LOGIC;
+      S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+      S_AXIL_ARVALID : IN STD_LOGIC;
+      S_AXIL_ARREADY : OUT STD_LOGIC;
+      S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_RVALID : OUT STD_LOGIC;
+      S_AXIL_RREADY : IN STD_LOGIC;
+      S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      GPI : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      GPO : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+    );
+  END COMPONENT axil_gpio;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIL_ACLK, ASSOCIATED_BUSIF S_AXIL, ASSOCIATED_RESET S_AXIL_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIL_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIL_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" & 
+" 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
+BEGIN
+  U0 : axil_gpio
+    GENERIC MAP (
+      GPI_WIDTH => 3,
+      GPO_WIDTH => 6
+    )
+    PORT MAP (
+      S_AXIL_ACLK => S_AXIL_ACLK,
+      S_AXIL_ARESETN => S_AXIL_ARESETN,
+      S_AXIL_AWADDR => S_AXIL_AWADDR,
+      S_AXIL_AWVALID => S_AXIL_AWVALID,
+      S_AXIL_AWREADY => S_AXIL_AWREADY,
+      S_AXIL_WDATA => S_AXIL_WDATA,
+      S_AXIL_WVALID => S_AXIL_WVALID,
+      S_AXIL_WREADY => S_AXIL_WREADY,
+      S_AXIL_WSTRB => S_AXIL_WSTRB,
+      S_AXIL_BVALID => S_AXIL_BVALID,
+      S_AXIL_BREADY => S_AXIL_BREADY,
+      S_AXIL_BRESP => S_AXIL_BRESP,
+      S_AXIL_ARADDR => S_AXIL_ARADDR,
+      S_AXIL_ARVALID => S_AXIL_ARVALID,
+      S_AXIL_ARREADY => S_AXIL_ARREADY,
+      S_AXIL_RDATA => S_AXIL_RDATA,
+      S_AXIL_RVALID => S_AXIL_RVALID,
+      S_AXIL_RREADY => S_AXIL_RREADY,
+      S_AXIL_RRESP => S_AXIL_RRESP,
+      GPI => GPI,
+      GPO => GPO
+    );
+END design_1_axil_gpio_0_0_arch;

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0/synth/design_1_axil_gpio_0_0.vhd

@@ -0,0 +1,176 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axil_gpio:1.0
+-- IP Revision: 7
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_axil_gpio_0_0 IS
+  PORT (
+    S_AXIL_ACLK : IN STD_LOGIC;
+    S_AXIL_ARESETN : IN STD_LOGIC;
+    S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    S_AXIL_AWVALID : IN STD_LOGIC;
+    S_AXIL_AWREADY : OUT STD_LOGIC;
+    S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_WVALID : IN STD_LOGIC;
+    S_AXIL_WREADY : OUT STD_LOGIC;
+    S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXIL_BVALID : OUT STD_LOGIC;
+    S_AXIL_BREADY : IN STD_LOGIC;
+    S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    S_AXIL_ARVALID : IN STD_LOGIC;
+    S_AXIL_ARREADY : OUT STD_LOGIC;
+    S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXIL_RVALID : OUT STD_LOGIC;
+    S_AXIL_RREADY : IN STD_LOGIC;
+    S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    GPI : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    GPO : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+  );
+END design_1_axil_gpio_0_0;
+
+ARCHITECTURE design_1_axil_gpio_0_0_arch OF design_1_axil_gpio_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_gpio_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axil_gpio IS
+    GENERIC (
+      GPI_WIDTH : INTEGER;
+      GPO_WIDTH : INTEGER
+    );
+    PORT (
+      S_AXIL_ACLK : IN STD_LOGIC;
+      S_AXIL_ARESETN : IN STD_LOGIC;
+      S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+      S_AXIL_AWVALID : IN STD_LOGIC;
+      S_AXIL_AWREADY : OUT STD_LOGIC;
+      S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_WVALID : IN STD_LOGIC;
+      S_AXIL_WREADY : OUT STD_LOGIC;
+      S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXIL_BVALID : OUT STD_LOGIC;
+      S_AXIL_BREADY : IN STD_LOGIC;
+      S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+      S_AXIL_ARVALID : IN STD_LOGIC;
+      S_AXIL_ARREADY : OUT STD_LOGIC;
+      S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXIL_RVALID : OUT STD_LOGIC;
+      S_AXIL_RREADY : IN STD_LOGIC;
+      S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      GPI : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      GPO : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+    );
+  END COMPONENT axil_gpio;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_axil_gpio_0_0_arch: ARCHITECTURE IS "axil_gpio,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axil_gpio_0_0_arch : ARCHITECTURE IS "design_1_axil_gpio_0_0,axil_gpio,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_axil_gpio_0_0_arch: ARCHITECTURE IS "design_1_axil_gpio_0_0,axil_gpio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axil_gpio,x_ipVersion=1.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,GPI_WIDTH=3,GPO_WIDTH=6}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axil_gpio_0_0_arch: ARCHITECTURE IS "package_project";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIL_ACLK, ASSOCIATED_BUSIF S_AXIL, ASSOCIATED_RESET S_AXIL_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIL_ACLK CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIL_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" & 
+" 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
+BEGIN
+  U0 : axil_gpio
+    GENERIC MAP (
+      GPI_WIDTH => 3,
+      GPO_WIDTH => 6
+    )
+    PORT MAP (
+      S_AXIL_ACLK => S_AXIL_ACLK,
+      S_AXIL_ARESETN => S_AXIL_ARESETN,
+      S_AXIL_AWADDR => S_AXIL_AWADDR,
+      S_AXIL_AWVALID => S_AXIL_AWVALID,
+      S_AXIL_AWREADY => S_AXIL_AWREADY,
+      S_AXIL_WDATA => S_AXIL_WDATA,
+      S_AXIL_WVALID => S_AXIL_WVALID,
+      S_AXIL_WREADY => S_AXIL_WREADY,
+      S_AXIL_WSTRB => S_AXIL_WSTRB,
+      S_AXIL_BVALID => S_AXIL_BVALID,
+      S_AXIL_BREADY => S_AXIL_BREADY,
+      S_AXIL_BRESP => S_AXIL_BRESP,
+      S_AXIL_ARADDR => S_AXIL_ARADDR,
+      S_AXIL_ARVALID => S_AXIL_ARVALID,
+      S_AXIL_ARREADY => S_AXIL_ARREADY,
+      S_AXIL_RDATA => S_AXIL_RDATA,
+      S_AXIL_RVALID => S_AXIL_RVALID,
+      S_AXIL_RREADY => S_AXIL_RREADY,
+      S_AXIL_RRESP => S_AXIL_RRESP,
+      GPI => GPI,
+      GPO => GPO
+    );
+END design_1_axil_gpio_0_0_arch;

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc

@@ -0,0 +1,710 @@
+############################################################################
+##
+##  Xilinx, Inc. 2006            www.xilinx.com
+############################################################################
+##  File name :       ps7_constraints.xdc
+##
+##  Details :     Constraints file
+##                    FPGA family:       zynq
+##                    FPGA:              xc7z020clg400-1
+##                    Device Size:        xc7z020
+##                    Package:            clg400
+##                    Speedgrade:         -1
+##
+##
+############################################################################
+############################################################################
+############################################################################
+# Clock constraints                                                        #
+############################################################################
+create_clock -name clk_fpga_2 -period "5" [get_pins "PS7_i/FCLKCLK[2]"]
+set_input_jitter clk_fpga_2 0.15
+#The clocks are asynchronous, user should constrain them appropriately.#
+create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
+set_input_jitter clk_fpga_0 0.3
+#The clocks are asynchronous, user should constrain them appropriately.#
+create_clock -name clk_fpga_1 -period "8" [get_pins "PS7_i/FCLKCLK[1]"]
+set_input_jitter clk_fpga_1 0.24
+#The clocks are asynchronous, user should constrain them appropriately.#
+create_clock -name clk_fpga_3 -period "14.999" [get_pins "PS7_i/FCLKCLK[3]"]
+set_input_jitter clk_fpga_3 0.44997
+#The clocks are asynchronous, user should constrain them appropriately.#
+
+
+############################################################################
+# I/O STANDARDS and Location Constraints                                   #
+############################################################################
+
+#  Enet 0 / mdio / MIO[53]
+set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
+set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
+set_property slew "slow" [get_ports "MIO[53]"]
+set_property drive "8" [get_ports "MIO[53]"]
+set_property pullup "TRUE" [get_ports "MIO[53]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
+#  Enet 0 / mdc / MIO[52]
+set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
+set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
+set_property slew "slow" [get_ports "MIO[52]"]
+set_property drive "8" [get_ports "MIO[52]"]
+set_property pullup "TRUE" [get_ports "MIO[52]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
+#  GPIO / gpio[51] / MIO[51]
+set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
+set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
+set_property slew "slow" [get_ports "MIO[51]"]
+set_property drive "8" [get_ports "MIO[51]"]
+set_property pullup "TRUE" [get_ports "MIO[51]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
+#  GPIO / gpio[50] / MIO[50]
+set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
+set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
+set_property slew "slow" [get_ports "MIO[50]"]
+set_property drive "8" [get_ports "MIO[50]"]
+set_property pullup "TRUE" [get_ports "MIO[50]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
+#  UART 1 / rx / MIO[49]
+set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
+set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
+set_property slew "slow" [get_ports "MIO[49]"]
+set_property drive "8" [get_ports "MIO[49]"]
+set_property pullup "TRUE" [get_ports "MIO[49]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
+#  UART 1 / tx / MIO[48]
+set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
+set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
+set_property slew "slow" [get_ports "MIO[48]"]
+set_property drive "8" [get_ports "MIO[48]"]
+set_property pullup "TRUE" [get_ports "MIO[48]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
+#  SD 0 / cd / MIO[47]
+set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
+set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
+set_property slew "slow" [get_ports "MIO[47]"]
+set_property drive "8" [get_ports "MIO[47]"]
+set_property pullup "TRUE" [get_ports "MIO[47]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
+#  USB Reset / reset / MIO[46]
+set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
+set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
+set_property slew "slow" [get_ports "MIO[46]"]
+set_property drive "8" [get_ports "MIO[46]"]
+set_property pullup "TRUE" [get_ports "MIO[46]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[46]"]
+#  SD 0 / data[3] / MIO[45]
+set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
+set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
+set_property slew "slow" [get_ports "MIO[45]"]
+set_property drive "8" [get_ports "MIO[45]"]
+set_property pullup "TRUE" [get_ports "MIO[45]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
+#  SD 0 / data[2] / MIO[44]
+set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
+set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
+set_property slew "slow" [get_ports "MIO[44]"]
+set_property drive "8" [get_ports "MIO[44]"]
+set_property pullup "TRUE" [get_ports "MIO[44]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
+#  SD 0 / data[1] / MIO[43]
+set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
+set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
+set_property slew "slow" [get_ports "MIO[43]"]
+set_property drive "8" [get_ports "MIO[43]"]
+set_property pullup "TRUE" [get_ports "MIO[43]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
+#  SD 0 / data[0] / MIO[42]
+set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
+set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
+set_property slew "slow" [get_ports "MIO[42]"]
+set_property drive "8" [get_ports "MIO[42]"]
+set_property pullup "TRUE" [get_ports "MIO[42]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
+#  SD 0 / cmd / MIO[41]
+set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
+set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
+set_property slew "slow" [get_ports "MIO[41]"]
+set_property drive "8" [get_ports "MIO[41]"]
+set_property pullup "TRUE" [get_ports "MIO[41]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
+#  SD 0 / clk / MIO[40]
+set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
+set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
+set_property slew "slow" [get_ports "MIO[40]"]
+set_property drive "8" [get_ports "MIO[40]"]
+set_property pullup "TRUE" [get_ports "MIO[40]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
+#  USB 0 / data[7] / MIO[39]
+set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
+set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
+set_property slew "fast" [get_ports "MIO[39]"]
+set_property drive "8" [get_ports "MIO[39]"]
+set_property pullup "TRUE" [get_ports "MIO[39]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
+#  USB 0 / data[6] / MIO[38]
+set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
+set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
+set_property slew "fast" [get_ports "MIO[38]"]
+set_property drive "8" [get_ports "MIO[38]"]
+set_property pullup "TRUE" [get_ports "MIO[38]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
+#  USB 0 / data[5] / MIO[37]
+set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
+set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
+set_property slew "fast" [get_ports "MIO[37]"]
+set_property drive "8" [get_ports "MIO[37]"]
+set_property pullup "TRUE" [get_ports "MIO[37]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
+#  USB 0 / clk / MIO[36]
+set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
+set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
+set_property slew "fast" [get_ports "MIO[36]"]
+set_property drive "8" [get_ports "MIO[36]"]
+set_property pullup "TRUE" [get_ports "MIO[36]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
+#  USB 0 / data[3] / MIO[35]
+set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
+set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
+set_property slew "fast" [get_ports "MIO[35]"]
+set_property drive "8" [get_ports "MIO[35]"]
+set_property pullup "TRUE" [get_ports "MIO[35]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
+#  USB 0 / data[2] / MIO[34]
+set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
+set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
+set_property slew "fast" [get_ports "MIO[34]"]
+set_property drive "8" [get_ports "MIO[34]"]
+set_property pullup "TRUE" [get_ports "MIO[34]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
+#  USB 0 / data[1] / MIO[33]
+set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
+set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
+set_property slew "fast" [get_ports "MIO[33]"]
+set_property drive "8" [get_ports "MIO[33]"]
+set_property pullup "TRUE" [get_ports "MIO[33]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
+#  USB 0 / data[0] / MIO[32]
+set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
+set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
+set_property slew "fast" [get_ports "MIO[32]"]
+set_property drive "8" [get_ports "MIO[32]"]
+set_property pullup "TRUE" [get_ports "MIO[32]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
+#  USB 0 / nxt / MIO[31]
+set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
+set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
+set_property slew "fast" [get_ports "MIO[31]"]
+set_property drive "8" [get_ports "MIO[31]"]
+set_property pullup "TRUE" [get_ports "MIO[31]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
+#  USB 0 / stp / MIO[30]
+set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
+set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
+set_property slew "fast" [get_ports "MIO[30]"]
+set_property drive "8" [get_ports "MIO[30]"]
+set_property pullup "TRUE" [get_ports "MIO[30]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
+#  USB 0 / dir / MIO[29]
+set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
+set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
+set_property slew "fast" [get_ports "MIO[29]"]
+set_property drive "8" [get_ports "MIO[29]"]
+set_property pullup "TRUE" [get_ports "MIO[29]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
+#  USB 0 / data[4] / MIO[28]
+set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
+set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
+set_property slew "fast" [get_ports "MIO[28]"]
+set_property drive "8" [get_ports "MIO[28]"]
+set_property pullup "TRUE" [get_ports "MIO[28]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
+#  Enet 0 / rx_ctl / MIO[27]
+set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
+set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
+set_property slew "fast" [get_ports "MIO[27]"]
+set_property drive "8" [get_ports "MIO[27]"]
+set_property pullup "TRUE" [get_ports "MIO[27]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
+#  Enet 0 / rxd[3] / MIO[26]
+set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
+set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
+set_property slew "fast" [get_ports "MIO[26]"]
+set_property drive "8" [get_ports "MIO[26]"]
+set_property pullup "TRUE" [get_ports "MIO[26]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
+#  Enet 0 / rxd[2] / MIO[25]
+set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
+set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
+set_property slew "fast" [get_ports "MIO[25]"]
+set_property drive "8" [get_ports "MIO[25]"]
+set_property pullup "TRUE" [get_ports "MIO[25]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
+#  Enet 0 / rxd[1] / MIO[24]
+set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
+set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
+set_property slew "fast" [get_ports "MIO[24]"]
+set_property drive "8" [get_ports "MIO[24]"]
+set_property pullup "TRUE" [get_ports "MIO[24]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
+#  Enet 0 / rxd[0] / MIO[23]
+set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
+set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
+set_property slew "fast" [get_ports "MIO[23]"]
+set_property drive "8" [get_ports "MIO[23]"]
+set_property pullup "TRUE" [get_ports "MIO[23]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
+#  Enet 0 / rx_clk / MIO[22]
+set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
+set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
+set_property slew "fast" [get_ports "MIO[22]"]
+set_property drive "8" [get_ports "MIO[22]"]
+set_property pullup "TRUE" [get_ports "MIO[22]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
+#  Enet 0 / tx_ctl / MIO[21]
+set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
+set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
+set_property slew "fast" [get_ports "MIO[21]"]
+set_property drive "8" [get_ports "MIO[21]"]
+set_property pullup "TRUE" [get_ports "MIO[21]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
+#  Enet 0 / txd[3] / MIO[20]
+set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
+set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
+set_property slew "fast" [get_ports "MIO[20]"]
+set_property drive "8" [get_ports "MIO[20]"]
+set_property pullup "TRUE" [get_ports "MIO[20]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
+#  Enet 0 / txd[2] / MIO[19]
+set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
+set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
+set_property slew "fast" [get_ports "MIO[19]"]
+set_property drive "8" [get_ports "MIO[19]"]
+set_property pullup "TRUE" [get_ports "MIO[19]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
+#  Enet 0 / txd[1] / MIO[18]
+set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
+set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
+set_property slew "fast" [get_ports "MIO[18]"]
+set_property drive "8" [get_ports "MIO[18]"]
+set_property pullup "TRUE" [get_ports "MIO[18]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
+#  Enet 0 / txd[0] / MIO[17]
+set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
+set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
+set_property slew "fast" [get_ports "MIO[17]"]
+set_property drive "8" [get_ports "MIO[17]"]
+set_property pullup "TRUE" [get_ports "MIO[17]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
+#  Enet 0 / tx_clk / MIO[16]
+set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
+set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
+set_property slew "fast" [get_ports "MIO[16]"]
+set_property drive "8" [get_ports "MIO[16]"]
+set_property pullup "TRUE" [get_ports "MIO[16]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
+#  I2C 0 / sda / MIO[15]
+set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
+set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
+set_property slew "slow" [get_ports "MIO[15]"]
+set_property drive "8" [get_ports "MIO[15]"]
+set_property pullup "TRUE" [get_ports "MIO[15]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
+#  I2C 0 / scl / MIO[14]
+set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
+set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
+set_property slew "slow" [get_ports "MIO[14]"]
+set_property drive "8" [get_ports "MIO[14]"]
+set_property pullup "TRUE" [get_ports "MIO[14]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
+#  I2C 1 / sda / MIO[13]
+set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
+set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
+set_property slew "slow" [get_ports "MIO[13]"]
+set_property drive "8" [get_ports "MIO[13]"]
+set_property pullup "TRUE" [get_ports "MIO[13]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
+#  I2C 1 / scl / MIO[12]
+set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
+set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
+set_property slew "slow" [get_ports "MIO[12]"]
+set_property drive "8" [get_ports "MIO[12]"]
+set_property pullup "TRUE" [get_ports "MIO[12]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
+#  UART 0 / tx / MIO[11]
+set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
+set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
+set_property slew "slow" [get_ports "MIO[11]"]
+set_property drive "8" [get_ports "MIO[11]"]
+set_property pullup "TRUE" [get_ports "MIO[11]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[11]"]
+#  UART 0 / rx / MIO[10]
+set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
+set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
+set_property slew "slow" [get_ports "MIO[10]"]
+set_property drive "8" [get_ports "MIO[10]"]
+set_property pullup "TRUE" [get_ports "MIO[10]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[10]"]
+#  GPIO / gpio[9] / MIO[9]
+set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
+set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
+set_property slew "slow" [get_ports "MIO[9]"]
+set_property drive "8" [get_ports "MIO[9]"]
+set_property pullup "TRUE" [get_ports "MIO[9]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
+#  Quad SPI Flash / qspi_fbclk / MIO[8]
+set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
+set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
+set_property slew "slow" [get_ports "MIO[8]"]
+set_property drive "8" [get_ports "MIO[8]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
+#  GPIO / gpio[7] / MIO[7]
+set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
+set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
+set_property slew "slow" [get_ports "MIO[7]"]
+set_property drive "8" [get_ports "MIO[7]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
+#  Quad SPI Flash / qspi0_sclk / MIO[6]
+set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
+set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
+set_property slew "slow" [get_ports "MIO[6]"]
+set_property drive "8" [get_ports "MIO[6]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
+#  Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
+set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
+set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
+set_property slew "slow" [get_ports "MIO[5]"]
+set_property drive "8" [get_ports "MIO[5]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
+#  Quad SPI Flash / qspi0_io[2] / MIO[4]
+set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
+set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
+set_property slew "slow" [get_ports "MIO[4]"]
+set_property drive "8" [get_ports "MIO[4]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
+#  Quad SPI Flash / qspi0_io[1] / MIO[3]
+set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
+set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
+set_property slew "slow" [get_ports "MIO[3]"]
+set_property drive "8" [get_ports "MIO[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
+#  Quad SPI Flash / qspi0_io[0] / MIO[2]
+set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
+set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
+set_property slew "slow" [get_ports "MIO[2]"]
+set_property drive "8" [get_ports "MIO[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
+#  Quad SPI Flash / qspi0_ss_b / MIO[1]
+set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
+set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
+set_property slew "slow" [get_ports "MIO[1]"]
+set_property drive "8" [get_ports "MIO[1]"]
+set_property pullup "TRUE" [get_ports "MIO[1]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
+#  GPIO / gpio[0] / MIO[0]
+set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
+set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
+set_property slew "slow" [get_ports "MIO[0]"]
+set_property drive "8" [get_ports "MIO[0]"]
+set_property pullup "TRUE" [get_ports "MIO[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRP"]
+set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
+set_property slew "FAST" [get_ports "DDR_VRP"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRN"]
+set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
+set_property slew "FAST" [get_ports "DDR_VRN"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
+set_property iostandard "SSTL135" [get_ports "DDR_WEB"]
+set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
+set_property slew "SLOW" [get_ports "DDR_WEB"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
+set_property iostandard "SSTL135" [get_ports "DDR_RAS_n"]
+set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
+set_property slew "SLOW" [get_ports "DDR_RAS_n"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
+set_property iostandard "SSTL135" [get_ports "DDR_ODT"]
+set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
+set_property slew "SLOW" [get_ports "DDR_ODT"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
+set_property iostandard "SSTL135" [get_ports "DDR_DRSTB"]
+set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
+set_property slew "FAST" [get_ports "DDR_DRSTB"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
+set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[3]"]
+set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
+set_property slew "FAST" [get_ports "DDR_DQS[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
+set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[2]"]
+set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
+set_property slew "FAST" [get_ports "DDR_DQS[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
+set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[1]"]
+set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
+set_property slew "FAST" [get_ports "DDR_DQS[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
+set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[0]"]
+set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
+set_property slew "FAST" [get_ports "DDR_DQS[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
+set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[3]"]
+set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
+set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[2]"]
+set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
+set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[1]"]
+set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
+set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[0]"]
+set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[9]"]
+set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
+set_property slew "FAST" [get_ports "DDR_DQ[9]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[8]"]
+set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
+set_property slew "FAST" [get_ports "DDR_DQ[8]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[7]"]
+set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
+set_property slew "FAST" [get_ports "DDR_DQ[7]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[6]"]
+set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
+set_property slew "FAST" [get_ports "DDR_DQ[6]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[5]"]
+set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
+set_property slew "FAST" [get_ports "DDR_DQ[5]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[4]"]
+set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
+set_property slew "FAST" [get_ports "DDR_DQ[4]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[3]"]
+set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
+set_property slew "FAST" [get_ports "DDR_DQ[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[31]"]
+set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
+set_property slew "FAST" [get_ports "DDR_DQ[31]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[30]"]
+set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
+set_property slew "FAST" [get_ports "DDR_DQ[30]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[2]"]
+set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
+set_property slew "FAST" [get_ports "DDR_DQ[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[29]"]
+set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
+set_property slew "FAST" [get_ports "DDR_DQ[29]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[28]"]
+set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
+set_property slew "FAST" [get_ports "DDR_DQ[28]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[27]"]
+set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
+set_property slew "FAST" [get_ports "DDR_DQ[27]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[26]"]
+set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
+set_property slew "FAST" [get_ports "DDR_DQ[26]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[25]"]
+set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
+set_property slew "FAST" [get_ports "DDR_DQ[25]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[24]"]
+set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
+set_property slew "FAST" [get_ports "DDR_DQ[24]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[23]"]
+set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
+set_property slew "FAST" [get_ports "DDR_DQ[23]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[22]"]
+set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
+set_property slew "FAST" [get_ports "DDR_DQ[22]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[21]"]
+set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
+set_property slew "FAST" [get_ports "DDR_DQ[21]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[20]"]
+set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
+set_property slew "FAST" [get_ports "DDR_DQ[20]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[1]"]
+set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
+set_property slew "FAST" [get_ports "DDR_DQ[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[19]"]
+set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
+set_property slew "FAST" [get_ports "DDR_DQ[19]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[18]"]
+set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
+set_property slew "FAST" [get_ports "DDR_DQ[18]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[17]"]
+set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
+set_property slew "FAST" [get_ports "DDR_DQ[17]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[16]"]
+set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
+set_property slew "FAST" [get_ports "DDR_DQ[16]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[15]"]
+set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
+set_property slew "FAST" [get_ports "DDR_DQ[15]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[14]"]
+set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
+set_property slew "FAST" [get_ports "DDR_DQ[14]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[13]"]
+set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
+set_property slew "FAST" [get_ports "DDR_DQ[13]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[12]"]
+set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
+set_property slew "FAST" [get_ports "DDR_DQ[12]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[11]"]
+set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
+set_property slew "FAST" [get_ports "DDR_DQ[11]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[10]"]
+set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
+set_property slew "FAST" [get_ports "DDR_DQ[10]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[0]"]
+set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
+set_property slew "FAST" [get_ports "DDR_DQ[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[3]"]
+set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
+set_property slew "FAST" [get_ports "DDR_DM[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[2]"]
+set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
+set_property slew "FAST" [get_ports "DDR_DM[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[1]"]
+set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
+set_property slew "FAST" [get_ports "DDR_DM[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
+set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[0]"]
+set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
+set_property slew "FAST" [get_ports "DDR_DM[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
+set_property iostandard "SSTL135" [get_ports "DDR_CS_n"]
+set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
+set_property slew "SLOW" [get_ports "DDR_CS_n"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
+set_property iostandard "SSTL135" [get_ports "DDR_CKE"]
+set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
+set_property slew "SLOW" [get_ports "DDR_CKE"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
+set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk"]
+set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
+set_property slew "FAST" [get_ports "DDR_Clk"]
+set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
+set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk_n"]
+set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
+set_property slew "FAST" [get_ports "DDR_Clk_n"]
+set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
+set_property iostandard "SSTL135" [get_ports "DDR_CAS_n"]
+set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
+set_property slew "SLOW" [get_ports "DDR_CAS_n"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
+set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[2]"]
+set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
+set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
+set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[1]"]
+set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
+set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
+set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[0]"]
+set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
+set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[9]"]
+set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[8]"]
+set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[7]"]
+set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[6]"]
+set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[5]"]
+set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[4]"]
+set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[3]"]
+set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[2]"]
+set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[1]"]
+set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[14]"]
+set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[13]"]
+set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[12]"]
+set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[11]"]
+set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[10]"]
+set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
+set_property iostandard "SSTL135" [get_ports "DDR_Addr[0]"]
+set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
+set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
+set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
+set_property slew "fast" [get_ports "PS_PORB"]
+set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
+set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
+set_property slew "fast" [get_ports "PS_SRSTB"]
+set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
+set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
+set_property slew "fast" [get_ports "PS_CLK"]
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v

@@ -0,0 +1,111 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Sun Dec  1 11:10:22 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2023.1" *)
+module design_1_processing_system7_0_0(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, 
+  TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, 
+  M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, 
+  M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, 
+  M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, 
+  M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, 
+  M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, 
+  M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, 
+  M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, 
+  M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, 
+  M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_CLK1, FCLK_CLK2, FCLK_CLK3, 
+  FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, 
+  DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, 
+  PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */
+/* synthesis syn_force_seq_prim="M_AXI_GP0_ACLK" */
+/* synthesis syn_force_seq_prim="FCLK_CLK0" */
+/* synthesis syn_force_seq_prim="FCLK_CLK1" */
+/* synthesis syn_force_seq_prim="FCLK_CLK2" */
+/* synthesis syn_force_seq_prim="FCLK_CLK3" */;
+  input SDIO0_WP;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK /* synthesis syn_isclock = 1 */;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  input [0:0]IRQ_F2P;
+  output FCLK_CLK0 /* synthesis syn_isclock = 1 */;
+  output FCLK_CLK1 /* synthesis syn_isclock = 1 */;
+  output FCLK_CLK2 /* synthesis syn_isclock = 1 */;
+  output FCLK_CLK3 /* synthesis syn_isclock = 1 */;
+  output FCLK_RESET0_N;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.h

@@ -0,0 +1,117 @@
+/******************************************************************************
+*
+* Copyright (C) 2010-2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  125000000
+#define FPGA2_FREQ  200000000
+#define FPGA3_FREQ  66666672
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl

@@ -0,0 +1,853 @@
+proc ps7_pll_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00001401
+    mask_write 0XF8000154 0x00003F33 0x00000A03
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00200500
+    mask_write 0XF8000180 0x03F03F30 0x00200400
+    mask_write 0XF8000190 0x03F03F30 0x00100500
+    mask_write 0XF80001A0 0x03F03F30 0x00100F00
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_3_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x0007FFFF 0x00001082
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004285B
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+    mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+    mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
+    mask_write 0XF8006024 0x0FFFFFC3 0x00000000
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00000003 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x0003F03F 0x0003C008
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x00010000 0x00000000
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x00000200 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFCF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFCF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00027000
+    mask_write 0XF8006130 0x000FFFFF 0x00027000
+    mask_write 0XF8006134 0x000FFFFF 0x00026C00
+    mask_write 0XF8006138 0x000FFFFF 0x00028800
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x0000007A
+    mask_write 0XF8006158 0x000FFFFF 0x0000007A
+    mask_write 0XF800615C 0x000FFFFF 0x0000007C
+    mask_write 0XF8006160 0x000FFFFF 0x00000073
+    mask_write 0XF8006168 0x001FFFFF 0x000000F1
+    mask_write 0XF800616C 0x001FFFFF 0x000000F1
+    mask_write 0XF8006170 0x001FFFFF 0x000000F0
+    mask_write 0XF8006174 0x001FFFFF 0x000000F7
+    mask_write 0XF800617C 0x000FFFFF 0x000000BA
+    mask_write 0XF8006180 0x000FFFFF 0x000000BA
+    mask_write 0XF8006184 0x000FFFFF 0x000000BC
+    mask_write 0XF8006188 0x000FFFFF 0x000000B3
+    mask_write 0XF8006190 0x6FFFFEFE 0x00040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000703FF 0x000003FF
+    mask_write 0XF800620C 0x000703FF 0x000003FF
+    mask_write 0XF8006210 0x000703FF 0x000003FF
+    mask_write 0XF8006214 0x000703FF 0x000003FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF5 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000001 0x00000001
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FEFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001602
+    mask_write 0XF8000708 0x00003FFF 0x00000602
+    mask_write 0XF800070C 0x00003FFF 0x00000602
+    mask_write 0XF8000710 0x00003FFF 0x00000602
+    mask_write 0XF8000714 0x00003FFF 0x00000602
+    mask_write 0XF8000718 0x00003FFF 0x00000602
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000602
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x000016E1
+    mask_write 0XF800072C 0x00003FFF 0x000016E0
+    mask_write 0XF8000730 0x00003FFF 0x00001640
+    mask_write 0XF8000734 0x00003FFF 0x00001640
+    mask_write 0XF8000738 0x00003FFF 0x00001640
+    mask_write 0XF800073C 0x00003FFF 0x00001640
+    mask_write 0XF8000740 0x00003FFF 0x00001302
+    mask_write 0XF8000744 0x00003FFF 0x00001302
+    mask_write 0XF8000748 0x00003FFF 0x00001302
+    mask_write 0XF800074C 0x00003FFF 0x00001302
+    mask_write 0XF8000750 0x00003FFF 0x00001302
+    mask_write 0XF8000754 0x00003FFF 0x00001302
+    mask_write 0XF8000758 0x00003FFF 0x00001303
+    mask_write 0XF800075C 0x00003FFF 0x00001303
+    mask_write 0XF8000760 0x00003FFF 0x00001303
+    mask_write 0XF8000764 0x00003FFF 0x00001303
+    mask_write 0XF8000768 0x00003FFF 0x00001303
+    mask_write 0XF800076C 0x00003FFF 0x00001303
+    mask_write 0XF8000770 0x00003FFF 0x00001304
+    mask_write 0XF8000774 0x00003FFF 0x00001305
+    mask_write 0XF8000778 0x00003FFF 0x00001304
+    mask_write 0XF800077C 0x00003FFF 0x00001305
+    mask_write 0XF8000780 0x00003FFF 0x00001304
+    mask_write 0XF8000784 0x00003FFF 0x00001304
+    mask_write 0XF8000788 0x00003FFF 0x00001304
+    mask_write 0XF800078C 0x00003FFF 0x00001304
+    mask_write 0XF8000790 0x00003FFF 0x00001305
+    mask_write 0XF8000794 0x00003FFF 0x00001304
+    mask_write 0XF8000798 0x00003FFF 0x00001304
+    mask_write 0XF800079C 0x00003FFF 0x00001304
+    mask_write 0XF80007A0 0x00003FFF 0x00001280
+    mask_write 0XF80007A4 0x00003FFF 0x00001280
+    mask_write 0XF80007A8 0x00003FFF 0x00001280
+    mask_write 0XF80007AC 0x00003FFF 0x00001280
+    mask_write 0XF80007B0 0x00003FFF 0x00001280
+    mask_write 0XF80007B4 0x00003FFF 0x00001280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x000003FF 0x00000020
+    mask_write 0XE0000034 0x000000FF 0x00000006
+    mask_write 0XE0000018 0x0000FFFF 0x0000007C
+    mask_write 0XE0000000 0x000001FF 0x00000017
+    mask_write 0XE0000004 0x000003FF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A244 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+    mask_write 0XE000A248 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_3_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00001401
+    mask_write 0XF8000154 0x00003F33 0x00000A03
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00200500
+    mask_write 0XF8000180 0x03F03F30 0x00200400
+    mask_write 0XF8000190 0x03F03F30 0x00100500
+    mask_write 0XF80001A0 0x03F03F30 0x00100F00
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_2_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004285B
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+    mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00027000
+    mask_write 0XF8006130 0x000FFFFF 0x00027000
+    mask_write 0XF8006134 0x000FFFFF 0x00026C00
+    mask_write 0XF8006138 0x000FFFFF 0x00028800
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x0000007A
+    mask_write 0XF8006158 0x000FFFFF 0x0000007A
+    mask_write 0XF800615C 0x000FFFFF 0x0000007C
+    mask_write 0XF8006160 0x000FFFFF 0x00000073
+    mask_write 0XF8006168 0x001FFFFF 0x000000F1
+    mask_write 0XF800616C 0x001FFFFF 0x000000F1
+    mask_write 0XF8006170 0x001FFFFF 0x000000F0
+    mask_write 0XF8006174 0x001FFFFF 0x000000F7
+    mask_write 0XF800617C 0x000FFFFF 0x000000BA
+    mask_write 0XF8006180 0x000FFFFF 0x000000BA
+    mask_write 0XF8006184 0x000FFFFF 0x000000BC
+    mask_write 0XF8006188 0x000FFFFF 0x000000B3
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001602
+    mask_write 0XF8000708 0x00003FFF 0x00000602
+    mask_write 0XF800070C 0x00003FFF 0x00000602
+    mask_write 0XF8000710 0x00003FFF 0x00000602
+    mask_write 0XF8000714 0x00003FFF 0x00000602
+    mask_write 0XF8000718 0x00003FFF 0x00000602
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000602
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x000016E1
+    mask_write 0XF800072C 0x00003FFF 0x000016E0
+    mask_write 0XF8000730 0x00003FFF 0x00001640
+    mask_write 0XF8000734 0x00003FFF 0x00001640
+    mask_write 0XF8000738 0x00003FFF 0x00001640
+    mask_write 0XF800073C 0x00003FFF 0x00001640
+    mask_write 0XF8000740 0x00003FFF 0x00001302
+    mask_write 0XF8000744 0x00003FFF 0x00001302
+    mask_write 0XF8000748 0x00003FFF 0x00001302
+    mask_write 0XF800074C 0x00003FFF 0x00001302
+    mask_write 0XF8000750 0x00003FFF 0x00001302
+    mask_write 0XF8000754 0x00003FFF 0x00001302
+    mask_write 0XF8000758 0x00003FFF 0x00001303
+    mask_write 0XF800075C 0x00003FFF 0x00001303
+    mask_write 0XF8000760 0x00003FFF 0x00001303
+    mask_write 0XF8000764 0x00003FFF 0x00001303
+    mask_write 0XF8000768 0x00003FFF 0x00001303
+    mask_write 0XF800076C 0x00003FFF 0x00001303
+    mask_write 0XF8000770 0x00003FFF 0x00001304
+    mask_write 0XF8000774 0x00003FFF 0x00001305
+    mask_write 0XF8000778 0x00003FFF 0x00001304
+    mask_write 0XF800077C 0x00003FFF 0x00001305
+    mask_write 0XF8000780 0x00003FFF 0x00001304
+    mask_write 0XF8000784 0x00003FFF 0x00001304
+    mask_write 0XF8000788 0x00003FFF 0x00001304
+    mask_write 0XF800078C 0x00003FFF 0x00001304
+    mask_write 0XF8000790 0x00003FFF 0x00001305
+    mask_write 0XF8000794 0x00003FFF 0x00001304
+    mask_write 0XF8000798 0x00003FFF 0x00001304
+    mask_write 0XF800079C 0x00003FFF 0x00001304
+    mask_write 0XF80007A0 0x00003FFF 0x00001280
+    mask_write 0XF80007A4 0x00003FFF 0x00001280
+    mask_write 0XF80007A8 0x00003FFF 0x00001280
+    mask_write 0XF80007AC 0x00003FFF 0x00001280
+    mask_write 0XF80007B0 0x00003FFF 0x00001280
+    mask_write 0XF80007B4 0x00003FFF 0x00001280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE0000034 0x000000FF 0x00000006
+    mask_write 0XE0000018 0x0000FFFF 0x0000007C
+    mask_write 0XE0000000 0x000001FF 0x00000017
+    mask_write 0XE0000004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A244 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+    mask_write 0XE000A248 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_2_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00001401
+    mask_write 0XF8000154 0x00003F33 0x00000A03
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00200500
+    mask_write 0XF8000180 0x03F03F30 0x00200400
+    mask_write 0XF8000190 0x03F03F30 0x00100500
+    mask_write 0XF80001A0 0x03F03F30 0x00100F00
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_1_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004285B
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+    mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00027000
+    mask_write 0XF8006130 0x000FFFFF 0x00027000
+    mask_write 0XF8006134 0x000FFFFF 0x00026C00
+    mask_write 0XF8006138 0x000FFFFF 0x00028800
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x0000007A
+    mask_write 0XF8006158 0x000FFFFF 0x0000007A
+    mask_write 0XF800615C 0x000FFFFF 0x0000007C
+    mask_write 0XF8006160 0x000FFFFF 0x00000073
+    mask_write 0XF8006168 0x001FFFFF 0x000000F1
+    mask_write 0XF800616C 0x001FFFFF 0x000000F1
+    mask_write 0XF8006170 0x001FFFFF 0x000000F0
+    mask_write 0XF8006174 0x001FFFFF 0x000000F7
+    mask_write 0XF800617C 0x000FFFFF 0x000000BA
+    mask_write 0XF8006180 0x000FFFFF 0x000000BA
+    mask_write 0XF8006184 0x000FFFFF 0x000000BC
+    mask_write 0XF8006188 0x000FFFFF 0x000000B3
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
+    mask_write 0XF8000B6C 0x000073FF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001602
+    mask_write 0XF8000708 0x00003FFF 0x00000602
+    mask_write 0XF800070C 0x00003FFF 0x00000602
+    mask_write 0XF8000710 0x00003FFF 0x00000602
+    mask_write 0XF8000714 0x00003FFF 0x00000602
+    mask_write 0XF8000718 0x00003FFF 0x00000602
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000602
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x000016E1
+    mask_write 0XF800072C 0x00003FFF 0x000016E0
+    mask_write 0XF8000730 0x00003FFF 0x00001640
+    mask_write 0XF8000734 0x00003FFF 0x00001640
+    mask_write 0XF8000738 0x00003FFF 0x00001640
+    mask_write 0XF800073C 0x00003FFF 0x00001640
+    mask_write 0XF8000740 0x00003FFF 0x00001302
+    mask_write 0XF8000744 0x00003FFF 0x00001302
+    mask_write 0XF8000748 0x00003FFF 0x00001302
+    mask_write 0XF800074C 0x00003FFF 0x00001302
+    mask_write 0XF8000750 0x00003FFF 0x00001302
+    mask_write 0XF8000754 0x00003FFF 0x00001302
+    mask_write 0XF8000758 0x00003FFF 0x00001303
+    mask_write 0XF800075C 0x00003FFF 0x00001303
+    mask_write 0XF8000760 0x00003FFF 0x00001303
+    mask_write 0XF8000764 0x00003FFF 0x00001303
+    mask_write 0XF8000768 0x00003FFF 0x00001303
+    mask_write 0XF800076C 0x00003FFF 0x00001303
+    mask_write 0XF8000770 0x00003FFF 0x00001304
+    mask_write 0XF8000774 0x00003FFF 0x00001305
+    mask_write 0XF8000778 0x00003FFF 0x00001304
+    mask_write 0XF800077C 0x00003FFF 0x00001305
+    mask_write 0XF8000780 0x00003FFF 0x00001304
+    mask_write 0XF8000784 0x00003FFF 0x00001304
+    mask_write 0XF8000788 0x00003FFF 0x00001304
+    mask_write 0XF800078C 0x00003FFF 0x00001304
+    mask_write 0XF8000790 0x00003FFF 0x00001305
+    mask_write 0XF8000794 0x00003FFF 0x00001304
+    mask_write 0XF8000798 0x00003FFF 0x00001304
+    mask_write 0XF800079C 0x00003FFF 0x00001304
+    mask_write 0XF80007A0 0x00003FFF 0x00001280
+    mask_write 0XF80007A4 0x00003FFF 0x00001280
+    mask_write 0XF80007A8 0x00003FFF 0x00001280
+    mask_write 0XF80007AC 0x00003FFF 0x00001280
+    mask_write 0XF80007B0 0x00003FFF 0x00001280
+    mask_write 0XF80007B4 0x00003FFF 0x00001280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE0000034 0x000000FF 0x00000006
+    mask_write 0XE0000018 0x0000FFFF 0x0000007C
+    mask_write 0XE0000000 0x000001FF 0x00000017
+    mask_write 0XE0000004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A244 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+    mask_write 0XE000A248 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_1_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+set PCW_SILICON_VER_1_0 "0x0"
+set PCW_SILICON_VER_2_0 "0x1"
+set PCW_SILICON_VER_3_0 "0x2"
+set APU_FREQ  667000000
+
+
+
+proc mask_poll { addr mask } {
+    set count 1
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    while { $maskedval == 0 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval & $mask}]
+        set count [ expr { $count + 1 } ]
+        if { $count == 100000000 } {
+          puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+          break
+        }
+    }
+}
+
+
+
+proc mask_delay { addr val } {
+    set delay  [ get_number_of_cycles_for_delay $val ]
+    perf_reset_and_start_timer
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval < $delay}]
+    while { $maskedval == 1 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval < $delay}]
+    }
+    perf_reset_clock 
+}
+
+proc ps_version { } {
+    set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
+    set mask_sil_ver "0x[expr {$si_ver >> 28}]"
+    return $mask_sil_ver;
+}
+
+proc ps7_post_config {} {
+    set saved_mode [configparams force-mem-accesses]                  
+    configparams force-mem-accesses 1 
+    
+	variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_post_config_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_post_config_2_0   
+    } else {
+        ps7_post_config_3_0   
+    }
+	configparams force-mem-accesses $saved_mode                                       
+}
+
+proc ps7_debug {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_debug_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_debug_2_0   
+    } else {
+        ps7_debug_3_0   
+    }
+}
+proc ps7_init {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+            ps7_mio_init_data_1_0
+            ps7_pll_init_data_1_0
+            ps7_clock_init_data_1_0
+            ps7_ddr_init_data_1_0
+            ps7_peripherals_init_data_1_0
+            #puts "PCW Silicon Version : 1.0"
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+            ps7_mio_init_data_2_0
+            ps7_pll_init_data_2_0
+            ps7_clock_init_data_2_0
+            ps7_ddr_init_data_2_0
+            ps7_peripherals_init_data_2_0
+            #puts "PCW Silicon Version : 2.0"
+    } else {
+            ps7_mio_init_data_3_0
+            ps7_pll_init_data_3_0
+            ps7_clock_init_data_3_0
+            ps7_ddr_init_data_3_0
+            ps7_peripherals_init_data_3_0
+            #puts "PCW Silicon Version : 3.0"
+    }
+}
+
+
+# For delay calculation using global timer 
+
+# start timer 
+ proc perf_start_clock { } {
+
+    #writing SCU_GLOBAL_TIMER_CONTROL register
+
+    mask_write 0xF8F00208 0x00000109 0x00000009
+}
+
+# stop timer and reset timer count regs 
+ proc perf_reset_clock { } {
+	perf_disable_clock
+    mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
+    mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
+}
+
+# Compute mask for given delay in miliseconds
+proc get_number_of_cycles_for_delay { delay } {
+
+  # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  variable APU_FREQ
+  return [ expr ($delay * $APU_FREQ /(2 * 1000))]
+}
+
+
+# stop timer 
+proc perf_disable_clock {} {
+    mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 
+}
+
+proc perf_reset_and_start_timer {} {
+  	    perf_reset_clock 
+	    perf_start_clock 
+}
+
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.h

@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2010-2020 <Xilinx Inc.>
+* 
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see <http://www.gnu.org/licenses/>
+* 
+* 
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  125000000
+#define FPGA2_FREQ  200000000
+#define FPGA3_FREQ  66666672
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_parameters.xml

@@ -0,0 +1,643 @@
+<?xml version="1.0" encoding="UTF-8" ?> 
+<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
+<designInfo version="1.0" >
+  <MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
+    <PARAMETERS >
+      <PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
+      <PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="667" />
+      <PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
+      <PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
+      <PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
+      <PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
+      <PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
+      <PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
+      <PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
+      <PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
+      <PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
+      <PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
+      <PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
+      <PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
+      <PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
+      <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
+      <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
+      <PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
+      <PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
+      <PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
+      <PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
+      <PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
+      <PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
+      <PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
+      <PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
+      <PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
+      <PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
+      <PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
+      <PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
+      <PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
+      <PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
+      <PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
+      <PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin" />
+      <PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
+      <PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
+      <PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="1" />
+      <PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="1" />
+      <PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="1" />
+      <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" />
+      <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
+      <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="4" />
+      <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="2" />
+      <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="5" />
+      <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="15" />
+      <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
+      <PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="TRUE" />
+      <PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="TRUE" />
+      <PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="TRUE" />
+      <PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100" />
+      <PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="125" />
+      <PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="200" />
+      <PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="65" />
+      <PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
+      <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
+      <PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
+      <PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="MIO 14 .. 15" />
+      <PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="MIO 12 .. 13" />
+      <PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
+      <PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="Share reset pin" />
+      <PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
+      <PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
+      <PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
+      <PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
+      <PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="fast" />
+      <PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
+      <PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
+      <PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
+      <PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
+      <PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
+      <PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
+      <PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout" />
+      <PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
+      <PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
+      <PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
+      <PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
+      <PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
+      <PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
+      <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8" />
+      <PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
+      <PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
+      <PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5" />
+      <PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
+      <PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
+      <PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 47" />
+      <PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="EMIO" />
+      <PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45" />
+      <PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="20" />
+      <PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="50" />
+      <PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
+      <PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
+      <PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
+      <PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
+      <PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
+      <PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
+      <PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
+      <PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
+      <PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
+      <PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="EMIO" />
+      <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
+      <PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
+      <PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
+      <PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 10 .. 11" />
+      <PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
+      <PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
+      <PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
+      <PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10" />
+      <PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.221" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.222" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.217" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.244" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="18.8" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.4535" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="18.8" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.4535" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="18.8" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.4535" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="18.8" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.4535" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="22.8" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="105.056" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="27.9" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="66.904" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="22.9" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="89.1715" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="29.4" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="113.63" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="-0.050" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="-0.044" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="-0.035" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="-0.100" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="22.8" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="98.503" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="27.9" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="68.5855" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="22.9" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="90.295" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="29.4" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="103.977" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3 (Low Voltage)" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-125" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
+      <PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
+      <PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="MIO 46" />
+      <PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39" />
+      <PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
+      <PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
+      <PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin" />
+      <PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
+      <PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
+      <PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
+    </PARAMETERS>
+    <BUSINTERFACES >
+      <BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
+      <BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
+    </BUSINTERFACES>
+    <CLOCKOUTS >
+      <CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="100.000000" />
+      <CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="125.000000" />
+      <CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="200.000000" />
+      <CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="66.666672" />
+    </CLOCKOUTS>
+  </MODULE>
+</designInfo>

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.h

@@ -0,0 +1,635 @@
+#ifndef IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
+#define IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
+
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "design_1_processing_system7_0_0_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
+{
+public:
+
+  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_processing_system7_0_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > SDIO0_WP;
+  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
+  sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
+  sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
+  sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
+  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
+  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
+  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
+  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
+  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
+  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
+  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
+  sc_core::sc_out< bool > FCLK_CLK0;
+  sc_core::sc_out< bool > FCLK_CLK1;
+  sc_core::sc_out< bool > FCLK_CLK2;
+  sc_core::sc_out< bool > FCLK_CLK3;
+  sc_core::sc_out< bool > FCLK_RESET0_N;
+  sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
+  sc_core::sc_out< bool > DDR_CAS_n;
+  sc_core::sc_out< bool > DDR_CKE;
+  sc_core::sc_out< bool > DDR_Clk_n;
+  sc_core::sc_out< bool > DDR_Clk;
+  sc_core::sc_out< bool > DDR_CS_n;
+  sc_core::sc_out< bool > DDR_DRSTB;
+  sc_core::sc_out< bool > DDR_ODT;
+  sc_core::sc_out< bool > DDR_RAS_n;
+  sc_core::sc_out< bool > DDR_WEB;
+  sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
+  sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
+  sc_core::sc_out< bool > DDR_VRN;
+  sc_core::sc_out< bool > DDR_VRP;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
+  sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
+  sc_core::sc_out< bool > PS_SRSTB;
+  sc_core::sc_out< bool > PS_CLK;
+  sc_core::sc_out< bool > PS_PORB;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
+  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
+{
+public:
+
+  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_processing_system7_0_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > SDIO0_WP;
+  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
+  sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
+  sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
+  sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
+  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
+  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
+  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
+  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
+  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
+  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
+  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
+  sc_core::sc_out< bool > FCLK_CLK0;
+  sc_core::sc_out< bool > FCLK_CLK1;
+  sc_core::sc_out< bool > FCLK_CLK2;
+  sc_core::sc_out< bool > FCLK_CLK3;
+  sc_core::sc_out< bool > FCLK_RESET0_N;
+  sc_core::sc_inout< sc_dt::sc_bv<54> > MIO;
+  sc_core::sc_inout< bool > DDR_CAS_n;
+  sc_core::sc_inout< bool > DDR_CKE;
+  sc_core::sc_inout< bool > DDR_Clk_n;
+  sc_core::sc_inout< bool > DDR_Clk;
+  sc_core::sc_inout< bool > DDR_CS_n;
+  sc_core::sc_inout< bool > DDR_DRSTB;
+  sc_core::sc_inout< bool > DDR_ODT;
+  sc_core::sc_inout< bool > DDR_RAS_n;
+  sc_core::sc_inout< bool > DDR_WEB;
+  sc_core::sc_inout< sc_dt::sc_bv<3> > DDR_BankAddr;
+  sc_core::sc_inout< sc_dt::sc_bv<15> > DDR_Addr;
+  sc_core::sc_inout< bool > DDR_VRN;
+  sc_core::sc_inout< bool > DDR_VRP;
+  sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DM;
+  sc_core::sc_inout< sc_dt::sc_bv<32> > DDR_DQ;
+  sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS_n;
+  sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS;
+  sc_core::sc_inout< bool > PS_SRSTB;
+  sc_core::sc_inout< bool > PS_CLK;
+  sc_core::sc_inout< bool > PS_PORB;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
+  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
+{
+public:
+
+  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_processing_system7_0_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > SDIO0_WP;
+  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
+  sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
+  sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
+  sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
+  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
+  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
+  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
+  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
+  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
+  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
+  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
+  sc_core::sc_out< bool > FCLK_CLK0;
+  sc_core::sc_out< bool > FCLK_CLK1;
+  sc_core::sc_out< bool > FCLK_CLK2;
+  sc_core::sc_out< bool > FCLK_CLK3;
+  sc_core::sc_out< bool > FCLK_RESET0_N;
+  sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
+  sc_core::sc_out< bool > DDR_CAS_n;
+  sc_core::sc_out< bool > DDR_CKE;
+  sc_core::sc_out< bool > DDR_Clk_n;
+  sc_core::sc_out< bool > DDR_Clk;
+  sc_core::sc_out< bool > DDR_CS_n;
+  sc_core::sc_out< bool > DDR_DRSTB;
+  sc_core::sc_out< bool > DDR_ODT;
+  sc_core::sc_out< bool > DDR_RAS_n;
+  sc_core::sc_out< bool > DDR_WEB;
+  sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
+  sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
+  sc_core::sc_out< bool > DDR_VRN;
+  sc_core::sc_out< bool > DDR_VRP;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
+  sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
+  sc_core::sc_out< bool > PS_SRSTB;
+  sc_core::sc_out< bool > PS_CLK;
+  sc_core::sc_out< bool > PS_PORB;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
+  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
+{
+public:
+
+  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_processing_system7_0_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > SDIO0_WP;
+  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
+  sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
+  sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
+  sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
+  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
+  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
+  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
+  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
+  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
+  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
+  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
+  sc_core::sc_out< bool > FCLK_CLK0;
+  sc_core::sc_out< bool > FCLK_CLK1;
+  sc_core::sc_out< bool > FCLK_CLK2;
+  sc_core::sc_out< bool > FCLK_CLK3;
+  sc_core::sc_out< bool > FCLK_RESET0_N;
+  sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
+  sc_core::sc_out< bool > DDR_CAS_n;
+  sc_core::sc_out< bool > DDR_CKE;
+  sc_core::sc_out< bool > DDR_Clk_n;
+  sc_core::sc_out< bool > DDR_Clk;
+  sc_core::sc_out< bool > DDR_CS_n;
+  sc_core::sc_out< bool > DDR_DRSTB;
+  sc_core::sc_out< bool > DDR_ODT;
+  sc_core::sc_out< bool > DDR_RAS_n;
+  sc_core::sc_out< bool > DDR_WEB;
+  sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
+  sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
+  sc_core::sc_out< bool > DDR_VRN;
+  sc_core::sc_out< bool > DDR_VRP;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
+  sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
+  sc_core::sc_out< bool > PS_SRSTB;
+  sc_core::sc_out< bool > PS_CLK;
+  sc_core::sc_out< bool > PS_PORB;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
+  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
+{
+public:
+
+  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
+  virtual ~design_1_processing_system7_0_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > SDIO0_WP;
+  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
+  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
+  sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
+  sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
+  sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
+  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
+  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
+  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
+  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
+  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
+  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
+  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
+  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
+  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
+  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
+  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
+  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
+  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
+  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
+  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
+  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
+  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
+  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
+  sc_core::sc_out< bool > FCLK_CLK0;
+  sc_core::sc_out< bool > FCLK_CLK1;
+  sc_core::sc_out< bool > FCLK_CLK2;
+  sc_core::sc_out< bool > FCLK_CLK3;
+  sc_core::sc_out< bool > FCLK_RESET0_N;
+  sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
+  sc_core::sc_out< bool > DDR_CAS_n;
+  sc_core::sc_out< bool > DDR_CKE;
+  sc_core::sc_out< bool > DDR_Clk_n;
+  sc_core::sc_out< bool > DDR_Clk;
+  sc_core::sc_out< bool > DDR_CS_n;
+  sc_core::sc_out< bool > DDR_DRSTB;
+  sc_core::sc_out< bool > DDR_ODT;
+  sc_core::sc_out< bool > DDR_RAS_n;
+  sc_core::sc_out< bool > DDR_WEB;
+  sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
+  sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
+  sc_core::sc_out< bool > DDR_VRN;
+  sc_core::sc_out< bool > DDR_VRP;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
+  sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
+  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
+  sc_core::sc_out< bool > PS_SRSTB;
+  sc_core::sc_out< bool > PS_CLK;
+  sc_core::sc_out< bool > PS_PORB;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
+  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
+  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
+  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
+  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
+  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v

@@ -0,0 +1,600 @@
+ 
+
+
+// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
+// IP Revision: 1
+
+`timescale 1ns/1ps
+
+module design_1_processing_system7_0_0 (
+SDIO0_WP, 
+TTC0_WAVE0_OUT, 
+TTC0_WAVE1_OUT, 
+TTC0_WAVE2_OUT, 
+USB0_PORT_INDCTL, 
+USB0_VBUS_PWRSELECT, 
+USB0_VBUS_PWRFAULT, 
+M_AXI_GP0_ARVALID, 
+M_AXI_GP0_AWVALID, 
+M_AXI_GP0_BREADY, 
+M_AXI_GP0_RREADY, 
+M_AXI_GP0_WLAST, 
+M_AXI_GP0_WVALID, 
+M_AXI_GP0_ARID, 
+M_AXI_GP0_AWID, 
+M_AXI_GP0_WID, 
+M_AXI_GP0_ARBURST, 
+M_AXI_GP0_ARLOCK, 
+M_AXI_GP0_ARSIZE, 
+M_AXI_GP0_AWBURST, 
+M_AXI_GP0_AWLOCK, 
+M_AXI_GP0_AWSIZE, 
+M_AXI_GP0_ARPROT, 
+M_AXI_GP0_AWPROT, 
+M_AXI_GP0_ARADDR, 
+M_AXI_GP0_AWADDR, 
+M_AXI_GP0_WDATA, 
+M_AXI_GP0_ARCACHE, 
+M_AXI_GP0_ARLEN, 
+M_AXI_GP0_ARQOS, 
+M_AXI_GP0_AWCACHE, 
+M_AXI_GP0_AWLEN, 
+M_AXI_GP0_AWQOS, 
+M_AXI_GP0_WSTRB, 
+M_AXI_GP0_ACLK, 
+M_AXI_GP0_ARREADY, 
+M_AXI_GP0_AWREADY, 
+M_AXI_GP0_BVALID, 
+M_AXI_GP0_RLAST, 
+M_AXI_GP0_RVALID, 
+M_AXI_GP0_WREADY, 
+M_AXI_GP0_BID, 
+M_AXI_GP0_RID, 
+M_AXI_GP0_BRESP, 
+M_AXI_GP0_RRESP, 
+M_AXI_GP0_RDATA, 
+IRQ_F2P, 
+FCLK_CLK0, 
+FCLK_CLK1, 
+FCLK_CLK2, 
+FCLK_CLK3, 
+FCLK_RESET0_N, 
+MIO, 
+DDR_CAS_n, 
+DDR_CKE, 
+DDR_Clk_n, 
+DDR_Clk, 
+DDR_CS_n, 
+DDR_DRSTB, 
+DDR_ODT, 
+DDR_RAS_n, 
+DDR_WEB, 
+DDR_BankAddr, 
+DDR_Addr, 
+DDR_VRN, 
+DDR_VRP, 
+DDR_DM, 
+DDR_DQ, 
+DDR_DQS_n, 
+DDR_DQS, 
+PS_SRSTB, 
+PS_CLK, 
+PS_PORB 
+);
+input SDIO0_WP;
+output TTC0_WAVE0_OUT;
+output TTC0_WAVE1_OUT;
+output TTC0_WAVE2_OUT;
+output [1 : 0] USB0_PORT_INDCTL;
+output USB0_VBUS_PWRSELECT;
+input USB0_VBUS_PWRFAULT;
+output M_AXI_GP0_ARVALID;
+output M_AXI_GP0_AWVALID;
+output M_AXI_GP0_BREADY;
+output M_AXI_GP0_RREADY;
+output M_AXI_GP0_WLAST;
+output M_AXI_GP0_WVALID;
+output [11 : 0] M_AXI_GP0_ARID;
+output [11 : 0] M_AXI_GP0_AWID;
+output [11 : 0] M_AXI_GP0_WID;
+output [1 : 0] M_AXI_GP0_ARBURST;
+output [1 : 0] M_AXI_GP0_ARLOCK;
+output [2 : 0] M_AXI_GP0_ARSIZE;
+output [1 : 0] M_AXI_GP0_AWBURST;
+output [1 : 0] M_AXI_GP0_AWLOCK;
+output [2 : 0] M_AXI_GP0_AWSIZE;
+output [2 : 0] M_AXI_GP0_ARPROT;
+output [2 : 0] M_AXI_GP0_AWPROT;
+output [31 : 0] M_AXI_GP0_ARADDR;
+output [31 : 0] M_AXI_GP0_AWADDR;
+output [31 : 0] M_AXI_GP0_WDATA;
+output [3 : 0] M_AXI_GP0_ARCACHE;
+output [3 : 0] M_AXI_GP0_ARLEN;
+output [3 : 0] M_AXI_GP0_ARQOS;
+output [3 : 0] M_AXI_GP0_AWCACHE;
+output [3 : 0] M_AXI_GP0_AWLEN;
+output [3 : 0] M_AXI_GP0_AWQOS;
+output [3 : 0] M_AXI_GP0_WSTRB;
+input M_AXI_GP0_ACLK;
+input M_AXI_GP0_ARREADY;
+input M_AXI_GP0_AWREADY;
+input M_AXI_GP0_BVALID;
+input M_AXI_GP0_RLAST;
+input M_AXI_GP0_RVALID;
+input M_AXI_GP0_WREADY;
+input [11 : 0] M_AXI_GP0_BID;
+input [11 : 0] M_AXI_GP0_RID;
+input [1 : 0] M_AXI_GP0_BRESP;
+input [1 : 0] M_AXI_GP0_RRESP;
+input [31 : 0] M_AXI_GP0_RDATA;
+input [0 : 0] IRQ_F2P;
+output FCLK_CLK0;
+output FCLK_CLK1;
+output FCLK_CLK2;
+output FCLK_CLK3;
+output FCLK_RESET0_N;
+input [53 : 0] MIO;
+input DDR_CAS_n;
+input DDR_CKE;
+input DDR_Clk_n;
+input DDR_Clk;
+input DDR_CS_n;
+input DDR_DRSTB;
+input DDR_ODT;
+input DDR_RAS_n;
+input DDR_WEB;
+input [2 : 0] DDR_BankAddr;
+input [14 : 0] DDR_Addr;
+input DDR_VRN;
+input DDR_VRP;
+input [3 : 0] DDR_DM;
+input [31 : 0] DDR_DQ;
+input [3 : 0] DDR_DQS_n;
+input [3 : 0] DDR_DQS;
+input PS_SRSTB;
+input PS_CLK;
+input PS_PORB;
+
+  processing_system7_vip_v1_0_16 #(
+    .C_USE_M_AXI_GP0(1),
+    .C_USE_M_AXI_GP1(0),
+    .C_USE_S_AXI_ACP(0),
+    .C_USE_S_AXI_GP0(0),
+    .C_USE_S_AXI_GP1(0),
+    .C_USE_S_AXI_HP0(0),
+    .C_USE_S_AXI_HP1(0),
+    .C_USE_S_AXI_HP2(0),
+    .C_USE_S_AXI_HP3(0),
+    .C_S_AXI_HP0_DATA_WIDTH(64),
+    .C_S_AXI_HP1_DATA_WIDTH(64),
+    .C_S_AXI_HP2_DATA_WIDTH(64),
+    .C_S_AXI_HP3_DATA_WIDTH(64),
+    .C_HIGH_OCM_EN(0),
+    .C_FCLK_CLK0_FREQ(100.0),
+    .C_FCLK_CLK1_FREQ(125.0),
+    .C_FCLK_CLK2_FREQ(200.0),
+    .C_FCLK_CLK3_FREQ(66.666672),
+	.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
+	.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
+	.C_M_AXI_GP0_THREAD_ID_WIDTH (12), 
+	.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
+  ) inst (
+    .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+    .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+    .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+    .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+    .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+    .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+    .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+    .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+    .M_AXI_GP0_WID(M_AXI_GP0_WID),
+    .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+    .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+    .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+    .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+    .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+    .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+    .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+    .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+    .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+    .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+    .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+    .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+    .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+    .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+    .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+    .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+    .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+    .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+    .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+    .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+    .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+    .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+    .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+    .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+    .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+    .M_AXI_GP0_BID(M_AXI_GP0_BID),
+    .M_AXI_GP0_RID(M_AXI_GP0_RID),
+    .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+    .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+    .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+    .M_AXI_GP1_ARVALID(),
+    .M_AXI_GP1_AWVALID(),
+    .M_AXI_GP1_BREADY(),
+    .M_AXI_GP1_RREADY(),
+    .M_AXI_GP1_WLAST(),
+    .M_AXI_GP1_WVALID(),
+    .M_AXI_GP1_ARID(),
+    .M_AXI_GP1_AWID(),
+    .M_AXI_GP1_WID(),
+    .M_AXI_GP1_ARBURST(),
+    .M_AXI_GP1_ARLOCK(),
+    .M_AXI_GP1_ARSIZE(),
+    .M_AXI_GP1_AWBURST(),
+    .M_AXI_GP1_AWLOCK(),
+    .M_AXI_GP1_AWSIZE(),
+    .M_AXI_GP1_ARPROT(),
+    .M_AXI_GP1_AWPROT(),
+    .M_AXI_GP1_ARADDR(),
+    .M_AXI_GP1_AWADDR(),
+    .M_AXI_GP1_WDATA(),
+    .M_AXI_GP1_ARCACHE(),
+    .M_AXI_GP1_ARLEN(),
+    .M_AXI_GP1_ARQOS(),
+    .M_AXI_GP1_AWCACHE(),
+    .M_AXI_GP1_AWLEN(),
+    .M_AXI_GP1_AWQOS(),
+    .M_AXI_GP1_WSTRB(),
+    .M_AXI_GP1_ACLK(1'B0),
+    .M_AXI_GP1_ARREADY(1'B0),
+    .M_AXI_GP1_AWREADY(1'B0),
+    .M_AXI_GP1_BVALID(1'B0),
+    .M_AXI_GP1_RLAST(1'B0),
+    .M_AXI_GP1_RVALID(1'B0),
+    .M_AXI_GP1_WREADY(1'B0),
+    .M_AXI_GP1_BID(12'B0),
+    .M_AXI_GP1_RID(12'B0),
+    .M_AXI_GP1_BRESP(2'B0),
+    .M_AXI_GP1_RRESP(2'B0),
+    .M_AXI_GP1_RDATA(32'B0),
+    .S_AXI_GP0_ARREADY(),
+    .S_AXI_GP0_AWREADY(),
+    .S_AXI_GP0_BVALID(),
+    .S_AXI_GP0_RLAST(),
+    .S_AXI_GP0_RVALID(),
+    .S_AXI_GP0_WREADY(),
+    .S_AXI_GP0_BRESP(),
+    .S_AXI_GP0_RRESP(),
+    .S_AXI_GP0_RDATA(),
+    .S_AXI_GP0_BID(),
+    .S_AXI_GP0_RID(),
+    .S_AXI_GP0_ACLK(1'B0),
+    .S_AXI_GP0_ARVALID(1'B0),
+    .S_AXI_GP0_AWVALID(1'B0),
+    .S_AXI_GP0_BREADY(1'B0),
+    .S_AXI_GP0_RREADY(1'B0),
+    .S_AXI_GP0_WLAST(1'B0),
+    .S_AXI_GP0_WVALID(1'B0),
+    .S_AXI_GP0_ARBURST(2'B0),
+    .S_AXI_GP0_ARLOCK(2'B0),
+    .S_AXI_GP0_ARSIZE(3'B0),
+    .S_AXI_GP0_AWBURST(2'B0),
+    .S_AXI_GP0_AWLOCK(2'B0),
+    .S_AXI_GP0_AWSIZE(3'B0),
+    .S_AXI_GP0_ARPROT(3'B0),
+    .S_AXI_GP0_AWPROT(3'B0),
+    .S_AXI_GP0_ARADDR(32'B0),
+    .S_AXI_GP0_AWADDR(32'B0),
+    .S_AXI_GP0_WDATA(32'B0),
+    .S_AXI_GP0_ARCACHE(4'B0),
+    .S_AXI_GP0_ARLEN(4'B0),
+    .S_AXI_GP0_ARQOS(4'B0),
+    .S_AXI_GP0_AWCACHE(4'B0),
+    .S_AXI_GP0_AWLEN(4'B0),
+    .S_AXI_GP0_AWQOS(4'B0),
+    .S_AXI_GP0_WSTRB(4'B0),
+    .S_AXI_GP0_ARID(6'B0),
+    .S_AXI_GP0_AWID(6'B0),
+    .S_AXI_GP0_WID(6'B0),
+    .S_AXI_GP1_ARREADY(),
+    .S_AXI_GP1_AWREADY(),
+    .S_AXI_GP1_BVALID(),
+    .S_AXI_GP1_RLAST(),
+    .S_AXI_GP1_RVALID(),
+    .S_AXI_GP1_WREADY(),
+    .S_AXI_GP1_BRESP(),
+    .S_AXI_GP1_RRESP(),
+    .S_AXI_GP1_RDATA(),
+    .S_AXI_GP1_BID(),
+    .S_AXI_GP1_RID(),
+    .S_AXI_GP1_ACLK(1'B0),
+    .S_AXI_GP1_ARVALID(1'B0),
+    .S_AXI_GP1_AWVALID(1'B0),
+    .S_AXI_GP1_BREADY(1'B0),
+    .S_AXI_GP1_RREADY(1'B0),
+    .S_AXI_GP1_WLAST(1'B0),
+    .S_AXI_GP1_WVALID(1'B0),
+    .S_AXI_GP1_ARBURST(2'B0),
+    .S_AXI_GP1_ARLOCK(2'B0),
+    .S_AXI_GP1_ARSIZE(3'B0),
+    .S_AXI_GP1_AWBURST(2'B0),
+    .S_AXI_GP1_AWLOCK(2'B0),
+    .S_AXI_GP1_AWSIZE(3'B0),
+    .S_AXI_GP1_ARPROT(3'B0),
+    .S_AXI_GP1_AWPROT(3'B0),
+    .S_AXI_GP1_ARADDR(32'B0),
+    .S_AXI_GP1_AWADDR(32'B0),
+    .S_AXI_GP1_WDATA(32'B0),
+    .S_AXI_GP1_ARCACHE(4'B0),
+    .S_AXI_GP1_ARLEN(4'B0),
+    .S_AXI_GP1_ARQOS(4'B0),
+    .S_AXI_GP1_AWCACHE(4'B0),
+    .S_AXI_GP1_AWLEN(4'B0),
+    .S_AXI_GP1_AWQOS(4'B0),
+    .S_AXI_GP1_WSTRB(4'B0),
+    .S_AXI_GP1_ARID(6'B0),
+    .S_AXI_GP1_AWID(6'B0),
+    .S_AXI_GP1_WID(6'B0),
+    .S_AXI_ACP_ARREADY(),
+    .S_AXI_ACP_AWREADY(),
+    .S_AXI_ACP_BVALID(),
+    .S_AXI_ACP_RLAST(),
+    .S_AXI_ACP_RVALID(),
+    .S_AXI_ACP_WREADY(),
+    .S_AXI_ACP_BRESP(),
+    .S_AXI_ACP_RRESP(),
+    .S_AXI_ACP_BID(),
+    .S_AXI_ACP_RID(),
+    .S_AXI_ACP_RDATA(),
+    .S_AXI_ACP_ACLK(1'B0),
+    .S_AXI_ACP_ARVALID(1'B0),
+    .S_AXI_ACP_AWVALID(1'B0),
+    .S_AXI_ACP_BREADY(1'B0),
+    .S_AXI_ACP_RREADY(1'B0),
+    .S_AXI_ACP_WLAST(1'B0),
+    .S_AXI_ACP_WVALID(1'B0),
+    .S_AXI_ACP_ARID(3'B0),
+    .S_AXI_ACP_ARPROT(3'B0),
+    .S_AXI_ACP_AWID(3'B0),
+    .S_AXI_ACP_AWPROT(3'B0),
+    .S_AXI_ACP_WID(3'B0),
+    .S_AXI_ACP_ARADDR(32'B0),
+    .S_AXI_ACP_AWADDR(32'B0),
+    .S_AXI_ACP_ARCACHE(4'B0),
+    .S_AXI_ACP_ARLEN(4'B0),
+    .S_AXI_ACP_ARQOS(4'B0),
+    .S_AXI_ACP_AWCACHE(4'B0),
+    .S_AXI_ACP_AWLEN(4'B0),
+    .S_AXI_ACP_AWQOS(4'B0),
+    .S_AXI_ACP_ARBURST(2'B0),
+    .S_AXI_ACP_ARLOCK(2'B0),
+    .S_AXI_ACP_ARSIZE(3'B0),
+    .S_AXI_ACP_AWBURST(2'B0),
+    .S_AXI_ACP_AWLOCK(2'B0),
+    .S_AXI_ACP_AWSIZE(3'B0),
+    .S_AXI_ACP_ARUSER(5'B0),
+    .S_AXI_ACP_AWUSER(5'B0),
+    .S_AXI_ACP_WDATA(64'B0),
+    .S_AXI_ACP_WSTRB(8'B0),
+    .S_AXI_HP0_ARREADY(),
+    .S_AXI_HP0_AWREADY(),
+    .S_AXI_HP0_BVALID(),
+    .S_AXI_HP0_RLAST(),
+    .S_AXI_HP0_RVALID(),
+    .S_AXI_HP0_WREADY(),
+    .S_AXI_HP0_BRESP(),
+    .S_AXI_HP0_RRESP(),
+    .S_AXI_HP0_BID(),
+    .S_AXI_HP0_RID(),
+    .S_AXI_HP0_RDATA(),
+    .S_AXI_HP0_ACLK(1'B0),
+    .S_AXI_HP0_ARVALID(1'B0),
+    .S_AXI_HP0_AWVALID(1'B0),
+    .S_AXI_HP0_BREADY(1'B0),
+    .S_AXI_HP0_RREADY(1'B0),
+    .S_AXI_HP0_WLAST(1'B0),
+    .S_AXI_HP0_WVALID(1'B0),
+    .S_AXI_HP0_ARBURST(2'B0),
+    .S_AXI_HP0_ARLOCK(2'B0),
+    .S_AXI_HP0_ARSIZE(3'B0),
+    .S_AXI_HP0_AWBURST(2'B0),
+    .S_AXI_HP0_AWLOCK(2'B0),
+    .S_AXI_HP0_AWSIZE(3'B0),
+    .S_AXI_HP0_ARPROT(3'B0),
+    .S_AXI_HP0_AWPROT(3'B0),
+    .S_AXI_HP0_ARADDR(32'B0),
+    .S_AXI_HP0_AWADDR(32'B0),
+    .S_AXI_HP0_ARCACHE(4'B0),
+    .S_AXI_HP0_ARLEN(4'B0),
+    .S_AXI_HP0_ARQOS(4'B0),
+    .S_AXI_HP0_AWCACHE(4'B0),
+    .S_AXI_HP0_AWLEN(4'B0),
+    .S_AXI_HP0_AWQOS(4'B0),
+    .S_AXI_HP0_ARID(6'B0),
+    .S_AXI_HP0_AWID(6'B0),
+    .S_AXI_HP0_WID(6'B0),
+    .S_AXI_HP0_WDATA(64'B0),
+    .S_AXI_HP0_WSTRB(8'B0),
+    .S_AXI_HP1_ARREADY(),
+    .S_AXI_HP1_AWREADY(),
+    .S_AXI_HP1_BVALID(),
+    .S_AXI_HP1_RLAST(),
+    .S_AXI_HP1_RVALID(),
+    .S_AXI_HP1_WREADY(),
+    .S_AXI_HP1_BRESP(),
+    .S_AXI_HP1_RRESP(),
+    .S_AXI_HP1_BID(),
+    .S_AXI_HP1_RID(),
+    .S_AXI_HP1_RDATA(),
+    .S_AXI_HP1_ACLK(1'B0),
+    .S_AXI_HP1_ARVALID(1'B0),
+    .S_AXI_HP1_AWVALID(1'B0),
+    .S_AXI_HP1_BREADY(1'B0),
+    .S_AXI_HP1_RREADY(1'B0),
+    .S_AXI_HP1_WLAST(1'B0),
+    .S_AXI_HP1_WVALID(1'B0),
+    .S_AXI_HP1_ARBURST(2'B0),
+    .S_AXI_HP1_ARLOCK(2'B0),
+    .S_AXI_HP1_ARSIZE(3'B0),
+    .S_AXI_HP1_AWBURST(2'B0),
+    .S_AXI_HP1_AWLOCK(2'B0),
+    .S_AXI_HP1_AWSIZE(3'B0),
+    .S_AXI_HP1_ARPROT(3'B0),
+    .S_AXI_HP1_AWPROT(3'B0),
+    .S_AXI_HP1_ARADDR(32'B0),
+    .S_AXI_HP1_AWADDR(32'B0),
+    .S_AXI_HP1_ARCACHE(4'B0),
+    .S_AXI_HP1_ARLEN(4'B0),
+    .S_AXI_HP1_ARQOS(4'B0),
+    .S_AXI_HP1_AWCACHE(4'B0),
+    .S_AXI_HP1_AWLEN(4'B0),
+    .S_AXI_HP1_AWQOS(4'B0),
+    .S_AXI_HP1_ARID(6'B0),
+    .S_AXI_HP1_AWID(6'B0),
+    .S_AXI_HP1_WID(6'B0),
+    .S_AXI_HP1_WDATA(64'B0),
+    .S_AXI_HP1_WSTRB(8'B0),
+    .S_AXI_HP2_ARREADY(),
+    .S_AXI_HP2_AWREADY(),
+    .S_AXI_HP2_BVALID(),
+    .S_AXI_HP2_RLAST(),
+    .S_AXI_HP2_RVALID(),
+    .S_AXI_HP2_WREADY(),
+    .S_AXI_HP2_BRESP(),
+    .S_AXI_HP2_RRESP(),
+    .S_AXI_HP2_BID(),
+    .S_AXI_HP2_RID(),
+    .S_AXI_HP2_RDATA(),
+    .S_AXI_HP2_ACLK(1'B0),
+    .S_AXI_HP2_ARVALID(1'B0),
+    .S_AXI_HP2_AWVALID(1'B0),
+    .S_AXI_HP2_BREADY(1'B0),
+    .S_AXI_HP2_RREADY(1'B0),
+    .S_AXI_HP2_WLAST(1'B0),
+    .S_AXI_HP2_WVALID(1'B0),
+    .S_AXI_HP2_ARBURST(2'B0),
+    .S_AXI_HP2_ARLOCK(2'B0),
+    .S_AXI_HP2_ARSIZE(3'B0),
+    .S_AXI_HP2_AWBURST(2'B0),
+    .S_AXI_HP2_AWLOCK(2'B0),
+    .S_AXI_HP2_AWSIZE(3'B0),
+    .S_AXI_HP2_ARPROT(3'B0),
+    .S_AXI_HP2_AWPROT(3'B0),
+    .S_AXI_HP2_ARADDR(32'B0),
+    .S_AXI_HP2_AWADDR(32'B0),
+    .S_AXI_HP2_ARCACHE(4'B0),
+    .S_AXI_HP2_ARLEN(4'B0),
+    .S_AXI_HP2_ARQOS(4'B0),
+    .S_AXI_HP2_AWCACHE(4'B0),
+    .S_AXI_HP2_AWLEN(4'B0),
+    .S_AXI_HP2_AWQOS(4'B0),
+    .S_AXI_HP2_ARID(6'B0),
+    .S_AXI_HP2_AWID(6'B0),
+    .S_AXI_HP2_WID(6'B0),
+    .S_AXI_HP2_WDATA(64'B0),
+    .S_AXI_HP2_WSTRB(8'B0),
+    .S_AXI_HP3_ARREADY(),
+    .S_AXI_HP3_AWREADY(),
+    .S_AXI_HP3_BVALID(),
+    .S_AXI_HP3_RLAST(),
+    .S_AXI_HP3_RVALID(),
+    .S_AXI_HP3_WREADY(),
+    .S_AXI_HP3_BRESP(),
+    .S_AXI_HP3_RRESP(),
+    .S_AXI_HP3_BID(),
+    .S_AXI_HP3_RID(),
+    .S_AXI_HP3_RDATA(),
+    .S_AXI_HP3_ACLK(1'B0),
+    .S_AXI_HP3_ARVALID(1'B0),
+    .S_AXI_HP3_AWVALID(1'B0),
+    .S_AXI_HP3_BREADY(1'B0),
+    .S_AXI_HP3_RREADY(1'B0),
+    .S_AXI_HP3_WLAST(1'B0),
+    .S_AXI_HP3_WVALID(1'B0),
+    .S_AXI_HP3_ARBURST(2'B0),
+    .S_AXI_HP3_ARLOCK(2'B0),
+    .S_AXI_HP3_ARSIZE(3'B0),
+    .S_AXI_HP3_AWBURST(2'B0),
+    .S_AXI_HP3_AWLOCK(2'B0),
+    .S_AXI_HP3_AWSIZE(3'B0),
+    .S_AXI_HP3_ARPROT(3'B0),
+    .S_AXI_HP3_AWPROT(3'B0),
+    .S_AXI_HP3_ARADDR(32'B0),
+    .S_AXI_HP3_AWADDR(32'B0),
+    .S_AXI_HP3_ARCACHE(4'B0),
+    .S_AXI_HP3_ARLEN(4'B0),
+    .S_AXI_HP3_ARQOS(4'B0),
+    .S_AXI_HP3_AWCACHE(4'B0),
+    .S_AXI_HP3_AWLEN(4'B0),
+    .S_AXI_HP3_AWQOS(4'B0),
+    .S_AXI_HP3_ARID(6'B0),
+    .S_AXI_HP3_AWID(6'B0),
+    .S_AXI_HP3_WID(6'B0),
+    .S_AXI_HP3_WDATA(64'B0),
+    .S_AXI_HP3_WSTRB(8'B0),
+    .FCLK_CLK0(FCLK_CLK0),
+	
+    .FCLK_CLK1(FCLK_CLK1),
+	
+    .FCLK_CLK2(FCLK_CLK2),
+	
+    .FCLK_CLK3(FCLK_CLK3),
+    .FCLK_RESET0_N(FCLK_RESET0_N),
+    .FCLK_RESET1_N(),
+    .FCLK_RESET2_N(),
+    .FCLK_RESET3_N(),
+    .IRQ_F2P(IRQ_F2P),
+    .PS_SRSTB(PS_SRSTB),
+    .PS_CLK(PS_CLK),
+    .PS_PORB(PS_PORB)
+  );
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_sc.h

@@ -0,0 +1,96 @@
+#ifndef IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
+#define IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
+
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class processing_system7_v5_5_tlm;
+
+class DllExport design_1_processing_system7_0_0_sc : public sc_core::sc_module
+{
+public:
+
+  design_1_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
+  virtual ~design_1_processing_system7_0_0_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  processing_system7_v5_5_tlm* mp_impl;
+
+private:
+
+  design_1_processing_system7_0_0_sc(const design_1_processing_system7_0_0_sc&);
+  const design_1_processing_system7_0_0_sc& operator=(const design_1_processing_system7_0_0_sc&);
+
+};
+
+#endif // IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_stub.sv

@@ -0,0 +1,225 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    design_1_processing_system7_0_0_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module design_1_processing_system7_0_0 (
+  input bit_as_bool SDIO0_WP,
+  output bit_as_bool TTC0_WAVE0_OUT,
+  output bit_as_bool TTC0_WAVE1_OUT,
+  output bit_as_bool TTC0_WAVE2_OUT,
+  output bit [1 : 0] USB0_PORT_INDCTL,
+  output bit_as_bool USB0_VBUS_PWRSELECT,
+  input bit_as_bool USB0_VBUS_PWRFAULT,
+  output bit_as_bool M_AXI_GP0_ARVALID,
+  output bit_as_bool M_AXI_GP0_AWVALID,
+  output bit_as_bool M_AXI_GP0_BREADY,
+  output bit_as_bool M_AXI_GP0_RREADY,
+  output bit_as_bool M_AXI_GP0_WLAST,
+  output bit_as_bool M_AXI_GP0_WVALID,
+  output bit [11 : 0] M_AXI_GP0_ARID,
+  output bit [11 : 0] M_AXI_GP0_AWID,
+  output bit [11 : 0] M_AXI_GP0_WID,
+  output bit [1 : 0] M_AXI_GP0_ARBURST,
+  output bit [1 : 0] M_AXI_GP0_ARLOCK,
+  output bit [2 : 0] M_AXI_GP0_ARSIZE,
+  output bit [1 : 0] M_AXI_GP0_AWBURST,
+  output bit [1 : 0] M_AXI_GP0_AWLOCK,
+  output bit [2 : 0] M_AXI_GP0_AWSIZE,
+  output bit [2 : 0] M_AXI_GP0_ARPROT,
+  output bit [2 : 0] M_AXI_GP0_AWPROT,
+  output bit [31 : 0] M_AXI_GP0_ARADDR,
+  output bit [31 : 0] M_AXI_GP0_AWADDR,
+  output bit [31 : 0] M_AXI_GP0_WDATA,
+  output bit [3 : 0] M_AXI_GP0_ARCACHE,
+  output bit [3 : 0] M_AXI_GP0_ARLEN,
+  output bit [3 : 0] M_AXI_GP0_ARQOS,
+  output bit [3 : 0] M_AXI_GP0_AWCACHE,
+  output bit [3 : 0] M_AXI_GP0_AWLEN,
+  output bit [3 : 0] M_AXI_GP0_AWQOS,
+  output bit [3 : 0] M_AXI_GP0_WSTRB,
+  input bit_as_bool M_AXI_GP0_ACLK,
+  input bit_as_bool M_AXI_GP0_ARREADY,
+  input bit_as_bool M_AXI_GP0_AWREADY,
+  input bit_as_bool M_AXI_GP0_BVALID,
+  input bit_as_bool M_AXI_GP0_RLAST,
+  input bit_as_bool M_AXI_GP0_RVALID,
+  input bit_as_bool M_AXI_GP0_WREADY,
+  input bit [11 : 0] M_AXI_GP0_BID,
+  input bit [11 : 0] M_AXI_GP0_RID,
+  input bit [1 : 0] M_AXI_GP0_BRESP,
+  input bit [1 : 0] M_AXI_GP0_RRESP,
+  input bit [31 : 0] M_AXI_GP0_RDATA,
+  input bit [0 : 0] IRQ_F2P,
+  output bit_as_bool FCLK_CLK0,
+  output bit_as_bool FCLK_CLK1,
+  output bit_as_bool FCLK_CLK2,
+  output bit_as_bool FCLK_CLK3,
+  output bit_as_bool FCLK_RESET0_N,
+  output bit [53 : 0] MIO,
+  output bit_as_bool DDR_CAS_n,
+  output bit_as_bool DDR_CKE,
+  output bit_as_bool DDR_Clk_n,
+  output bit_as_bool DDR_Clk,
+  output bit_as_bool DDR_CS_n,
+  output bit_as_bool DDR_DRSTB,
+  output bit_as_bool DDR_ODT,
+  output bit_as_bool DDR_RAS_n,
+  output bit_as_bool DDR_WEB,
+  output bit [2 : 0] DDR_BankAddr,
+  output bit [14 : 0] DDR_Addr,
+  output bit_as_bool DDR_VRN,
+  output bit_as_bool DDR_VRP,
+  output bit [3 : 0] DDR_DM,
+  output bit [31 : 0] DDR_DQ,
+  output bit [3 : 0] DDR_DQS_n,
+  output bit [3 : 0] DDR_DQS,
+  output bit_as_bool PS_SRSTB,
+  output bit_as_bool PS_CLK,
+  output bit_as_bool PS_PORB
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module design_1_processing_system7_0_0 (SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL,USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID,M_AXI_GP0_AWID,M_AXI_GP0_WID,M_AXI_GP0_ARBURST,M_AXI_GP0_ARLOCK,M_AXI_GP0_ARSIZE,M_AXI_GP0_AWBURST,M_AXI_GP0_AWLOCK,M_AXI_GP0_AWSIZE,M_AXI_GP0_ARPROT,M_AXI_GP0_AWPROT,M_AXI_GP0_ARADDR,M_AXI_GP0_AWADDR,M_AXI_GP0_WDATA,M_AXI_GP0_ARCACHE,M_AXI_GP0_ARLEN,M_AXI_GP0_ARQOS,M_AXI_GP0_AWCACHE,M_AXI_GP0_AWLEN,M_AXI_GP0_AWQOS,M_AXI_GP0_WSTRB,M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID,M_AXI_GP0_RID,M_AXI_GP0_BRESP,M_AXI_GP0_RRESP,M_AXI_GP0_RDATA,IRQ_F2P,FCLK_CLK0,FCLK_CLK1,FCLK_CLK2,FCLK_CLK3,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
+(* integer foreign = "SystemC";
+*);
+  input bit SDIO0_WP;
+  output wire TTC0_WAVE0_OUT;
+  output wire TTC0_WAVE1_OUT;
+  output wire TTC0_WAVE2_OUT;
+  output wire [1 : 0] USB0_PORT_INDCTL;
+  output wire USB0_VBUS_PWRSELECT;
+  input bit USB0_VBUS_PWRFAULT;
+  output wire M_AXI_GP0_ARVALID;
+  output wire M_AXI_GP0_AWVALID;
+  output wire M_AXI_GP0_BREADY;
+  output wire M_AXI_GP0_RREADY;
+  output wire M_AXI_GP0_WLAST;
+  output wire M_AXI_GP0_WVALID;
+  output wire [11 : 0] M_AXI_GP0_ARID;
+  output wire [11 : 0] M_AXI_GP0_AWID;
+  output wire [11 : 0] M_AXI_GP0_WID;
+  output wire [1 : 0] M_AXI_GP0_ARBURST;
+  output wire [1 : 0] M_AXI_GP0_ARLOCK;
+  output wire [2 : 0] M_AXI_GP0_ARSIZE;
+  output wire [1 : 0] M_AXI_GP0_AWBURST;
+  output wire [1 : 0] M_AXI_GP0_AWLOCK;
+  output wire [2 : 0] M_AXI_GP0_AWSIZE;
+  output wire [2 : 0] M_AXI_GP0_ARPROT;
+  output wire [2 : 0] M_AXI_GP0_AWPROT;
+  output wire [31 : 0] M_AXI_GP0_ARADDR;
+  output wire [31 : 0] M_AXI_GP0_AWADDR;
+  output wire [31 : 0] M_AXI_GP0_WDATA;
+  output wire [3 : 0] M_AXI_GP0_ARCACHE;
+  output wire [3 : 0] M_AXI_GP0_ARLEN;
+  output wire [3 : 0] M_AXI_GP0_ARQOS;
+  output wire [3 : 0] M_AXI_GP0_AWCACHE;
+  output wire [3 : 0] M_AXI_GP0_AWLEN;
+  output wire [3 : 0] M_AXI_GP0_AWQOS;
+  output wire [3 : 0] M_AXI_GP0_WSTRB;
+  input bit M_AXI_GP0_ACLK;
+  input bit M_AXI_GP0_ARREADY;
+  input bit M_AXI_GP0_AWREADY;
+  input bit M_AXI_GP0_BVALID;
+  input bit M_AXI_GP0_RLAST;
+  input bit M_AXI_GP0_RVALID;
+  input bit M_AXI_GP0_WREADY;
+  input bit [11 : 0] M_AXI_GP0_BID;
+  input bit [11 : 0] M_AXI_GP0_RID;
+  input bit [1 : 0] M_AXI_GP0_BRESP;
+  input bit [1 : 0] M_AXI_GP0_RRESP;
+  input bit [31 : 0] M_AXI_GP0_RDATA;
+  input bit [0 : 0] IRQ_F2P;
+  output wire FCLK_CLK0;
+  output wire FCLK_CLK1;
+  output wire FCLK_CLK2;
+  output wire FCLK_CLK3;
+  output wire FCLK_RESET0_N;
+  inout wire [53 : 0] MIO;
+  inout wire DDR_CAS_n;
+  inout wire DDR_CKE;
+  inout wire DDR_Clk_n;
+  inout wire DDR_Clk;
+  inout wire DDR_CS_n;
+  inout wire DDR_DRSTB;
+  inout wire DDR_ODT;
+  inout wire DDR_RAS_n;
+  inout wire DDR_WEB;
+  inout wire [2 : 0] DDR_BankAddr;
+  inout wire [14 : 0] DDR_Addr;
+  inout wire DDR_VRN;
+  inout wire DDR_VRP;
+  inout wire [3 : 0] DDR_DM;
+  inout wire [31 : 0] DDR_DQ;
+  inout wire [3 : 0] DDR_DQS_n;
+  inout wire [3 : 0] DDR_DQS;
+  inout wire PS_SRSTB;
+  inout wire PS_CLK;
+  inout wire PS_PORB;
+endmodule
+`endif

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/b_transport_converter.h

@@ -0,0 +1,170 @@
+// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+
+#ifndef _B_TRANSPORT_CONVERTER_H_
+#define _B_TRANSPORT_CONVERTER_H_
+
+#include <systemc>
+#include "tlm_utils/simple_target_socket.h"
+#include "tlm_utils/simple_initiator_socket.h"
+#include <utility>
+#include <vector>
+
+template<int IN_WIDTH, int OUT_WIDTH>
+class b_transport_converter: public sc_core::sc_module 
+{
+    enum TLM_IF_TYPE
+    {
+        B_TRANSPORT = 0,
+        NB_TRANSPORT,
+        TRANSPORT_DBG,
+        DMI_IF,
+        INVALID_IF
+    };
+    typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
+
+    public:
+        SC_HAS_PROCESS(b_transport_converter);
+        b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name): 
+            sc_module(name)
+    {
+        target_socket.register_b_transport(
+                this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
+        initiator_socket.register_nb_transport_bw(
+                this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
+
+    }
+
+        //simple tlm target/initiator socket...
+        tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH>    target_socket;
+        tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
+
+
+    public:
+        void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
+        {
+            tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
+            switch(get_tlm_if_type(payload.get_address()))
+            {
+                case B_TRANSPORT:
+                    initiator_socket->b_transport(payload, time);
+                    break;
+
+                case NB_TRANSPORT:
+                    initiator_socket->nb_transport_fw(payload, phase, time);
+                    wait(resp_complete_event); //! Wait for the response to complete
+                    break;
+
+                case TRANSPORT_DBG:
+                    initiator_socket->transport_dbg(payload);
+                    break;
+
+                case DMI_IF:
+                    break;
+
+                default:
+                    SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
+            }
+        }
+
+        tlm::tlm_sync_enum
+            nb_transport_bw(tlm::tlm_generic_payload& payload, 
+                    tlm::tlm_phase& phase, sc_core::sc_time& time)
+            {
+                if(phase == tlm::BEGIN_RESP) {
+                    resp_complete_event.notify();
+                    phase = tlm::END_RESP;
+                    return tlm::TLM_UPDATED;
+                }
+                return tlm::TLM_ACCEPTED;
+            }
+
+    private:
+        TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
+        {
+            //check for b_transport addresses
+            for(auto& addr_range: m_b_transport_addr_list) {
+                if(address >= addr_range.first && address < addr_range.second) {
+                    return B_TRANSPORT;
+                }
+            }
+
+            //check for nb_transport addresses
+            for(auto& addr_range: m_nb_transport_addr_list) {
+                if(address >= addr_range.first && address < addr_range.second) {
+                    return NB_TRANSPORT;
+                }
+            }
+            //check for dbg_transport addresses
+            for(auto& addr_range: m_dbg_transport_addr_list) {
+                if(address >= addr_range.first && address < addr_range.second) {
+                    return TRANSPORT_DBG;
+                }
+            }
+
+            //By default return NB_TRANSPORT
+            return NB_TRANSPORT;
+        }
+
+        //Start and End Address List for each of interfaces...
+        static addr_range_list  m_b_transport_addr_list;
+        static addr_range_list  m_nb_transport_addr_list;
+        static addr_range_list  m_dbg_transport_addr_list;
+
+        //event to notify completion of transaction
+        sc_core::sc_event  resp_complete_event;
+};
+
+template<int IN_WIDTH, int OUT_WIDTH>
+typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
+template<int IN_WIDTH, int OUT_WIDTH>
+typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
+template<int IN_WIDTH, int OUT_WIDTH>
+typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
+
+
+#endif /* _B_TRANSPORT_CONVERTER_H_ */
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.h

@@ -0,0 +1,240 @@
+
+
+// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
+// IP Revision: 1
+#ifndef __PS7_H__
+#define __PS7_H__
+
+#include "systemc.h"
+#include "xtlm.h"
+#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
+#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
+#include "tlm_utils/simple_initiator_socket.h"
+#include "tlm_utils/simple_target_socket.h"
+#include "genattr.h"
+#include "xilinx-zynq.h"
+#include "b_transport_converter.h"
+#include "utils/xtlm_aximm_fifo.h"
+
+/***************************************************************************************
+*
+* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
+* calls to xTLM sockets bn_transport_x() calls..
+* 
+* This is Only specific to remote-port so not creating seperate header for it.
+*
+***************************************************************************************/
+template <int IN_WIDTH, int OUT_WIDTH>
+class rptlm2xtlm_converter : public sc_module{
+    public:
+    tlm::tlm_target_socket<IN_WIDTH> target_socket;
+    xtlm::xtlm_aximm_initiator_socket wr_socket;
+    xtlm::xtlm_aximm_initiator_socket rd_socket;
+    rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
+	void registerUserExtensionHandlerCallback(
+			void (*callback)(xtlm::aximm_payload*,
+					const tlm::tlm_generic_payload*));
+
+    private:
+    b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
+    xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
+};
+
+/***************************************************************************************
+*   Global method, get registered with tlm2xtlm bridge
+*   This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
+*
+*   caller:     tlm2xtlm bridge
+*   purpose:    To get master id and other parameters out of genattr_extension 
+*               and use master id to AxUSER PIN of xtlm payload.
+*
+*
+***************************************************************************************/
+extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
+
+/***************************************************************************************
+*   Global method, get registered with xtlm2tlm bridge
+*   This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
+*
+*   caller:     xtlm2tlm bridge
+*   purpose:    To create and add master id and other parameters to genattr_extension.
+*               Master id red from AxID PIN of xtlm payload.
+*
+*
+***************************************************************************************/
+extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//                                                                                                              //
+// File:            processing_system7_tlm.h                                                                       //
+//                                                                                                              //
+// Description:     zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between                 //
+//                  xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper.              //
+//                  it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado        //
+//                  generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set         //
+//                  to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper.           //
+//                  it fill the the gap between input/output ports of vivado generated wrapper to               //
+//                  xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts               //
+//                  based on IP configuration in vivado.                                                        //
+//                                                                                                              //
+//                                                                                                              //
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+class processing_system7_v5_5_tlm : public sc_core::sc_module   {
+    
+    public:
+    // Non-AXI ports are declared here
+    sc_core::sc_in<bool> SDIO0_WP;
+    sc_core::sc_out<bool> TTC0_WAVE0_OUT;
+    sc_core::sc_out<bool> TTC0_WAVE1_OUT;
+    sc_core::sc_out<bool> TTC0_WAVE2_OUT;
+    sc_core::sc_out<sc_dt::sc_bv<2> >  USB0_PORT_INDCTL;
+    sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
+    sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
+    sc_core::sc_in<bool> M_AXI_GP0_ACLK;
+    sc_core::sc_in<sc_dt::sc_bv<1> >  IRQ_F2P;
+    sc_core::sc_out<bool> FCLK_CLK0;
+    sc_core::sc_out<bool> FCLK_CLK1;
+    sc_core::sc_out<bool> FCLK_CLK2;
+    sc_core::sc_out<bool> FCLK_CLK3;
+    sc_core::sc_out<bool> FCLK_RESET0_N;
+    sc_core::sc_inout<sc_dt::sc_bv<54> >  MIO;
+    sc_core::sc_inout<bool> DDR_CAS_n;
+    sc_core::sc_inout<bool> DDR_CKE;
+    sc_core::sc_inout<bool> DDR_Clk_n;
+    sc_core::sc_inout<bool> DDR_Clk;
+    sc_core::sc_inout<bool> DDR_CS_n;
+    sc_core::sc_inout<bool> DDR_DRSTB;
+    sc_core::sc_inout<bool> DDR_ODT;
+    sc_core::sc_inout<bool> DDR_RAS_n;
+    sc_core::sc_inout<bool> DDR_WEB;
+    sc_core::sc_inout<sc_dt::sc_bv<3> >  DDR_BankAddr;
+    sc_core::sc_inout<sc_dt::sc_bv<15> >  DDR_Addr;
+    sc_core::sc_inout<bool> DDR_VRN;
+    sc_core::sc_inout<bool> DDR_VRP;
+    sc_core::sc_inout<sc_dt::sc_bv<4> >  DDR_DM;
+    sc_core::sc_inout<sc_dt::sc_bv<32> >  DDR_DQ;
+    sc_core::sc_inout<sc_dt::sc_bv<4> >  DDR_DQS_n;
+    sc_core::sc_inout<sc_dt::sc_bv<4> >  DDR_DQS;
+    sc_core::sc_inout<bool> PS_SRSTB;
+    sc_core::sc_inout<bool> PS_CLK;
+    sc_core::sc_inout<bool> PS_PORB;
+
+    xtlm::xtlm_aximm_initiator_socket*      M_AXI_GP0_wr_socket;
+    xtlm::xtlm_aximm_initiator_socket*      M_AXI_GP0_rd_socket;
+
+    //constructor having three paramters
+    // 1. module name in sc_module_name objec, 
+    // 2. reference to map object of name and integer value pairs 
+    // 3. reference to map object of name and string value pairs
+    // All the model parameters (integer and string) which are configuration parameters 
+    // of Processing System 7 IP propogated from Vivado
+processing_system7_v5_5_tlm(sc_core::sc_module_name name,
+    xsc::common_cpp::properties&);
+    
+    ~processing_system7_v5_5_tlm();
+    SC_HAS_PROCESS(processing_system7_v5_5_tlm);
+    
+    private:
+    
+    //zynq tlm wrapper provided by Edgar
+    //module with interfaces of standard tlm 
+    //and input/output ports at signal level
+    xilinx_zynq* m_zynq_tlm_model;
+
+    // Xtlm2tlm_t Bridges
+    // Converts Xtlm transactions to tlm transactions
+    // Bridge's Xtlm wr/rd target sockets binds with 
+    // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator 
+    // socket with xilinx_zynq's target socket
+
+    // This Bridges converts b_transport to nb_transports and also
+    // Converts tlm transactions to xtlm transactions.
+    // Bridge's tlm simple target socket binds with 
+    // simple initiator socket of xilinx_zynqmp and xtlm 
+    // socket with xilinx_zynq's simple target socket
+    rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;     
+    
+    // sc_clocks for generating pl clocks
+    // output pins FCLK_CLK0..3 are drived by these clocks
+    sc_core::sc_clock FCLK_CLK0_clk;
+    sc_core::sc_clock FCLK_CLK1_clk;
+    sc_core::sc_clock FCLK_CLK2_clk;
+    sc_core::sc_clock FCLK_CLK3_clk;
+
+    
+    //Method which is sentive to FCLK_CLK0_clk sc_clock object
+    //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value 
+    void trigger_FCLK_CLK0_pin();
+    //Method which is sentive to FCLK_CLK1_clk sc_clock object
+    //FCLK_CLK1 pin written based on FCLK_CLK1_clk clock value 
+    void trigger_FCLK_CLK1_pin();
+    //Method which is sentive to FCLK_CLK2_clk sc_clock object
+    //FCLK_CLK2 pin written based on FCLK_CLK2_clk clock value 
+    void trigger_FCLK_CLK2_pin();
+    //Method which is sentive to FCLK_CLK3_clk sc_clock object
+    //FCLK_CLK3 pin written based on FCLK_CLK3_clk clock value 
+    void trigger_FCLK_CLK3_pin();
+    
+    void IRQ_F2P_method();
+    //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
+    //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
+    void FCLK_RESET0_N_trigger();
+
+    sc_signal<bool> qemu_rst;
+    void start_of_simulation();
+
+    xsc::common_cpp::properties prop;
+
+};
+#endif

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/xilinx-zynq.h

@@ -0,0 +1,104 @@
+/*
+ * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ *
+ * Copyright (c) 2016, Xilinx Inc.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "systemc.h"
+
+#include "tlm_utils/simple_initiator_socket.h"
+#include "tlm_utils/simple_target_socket.h"
+#include "tlm_utils/tlm_quantumkeeper.h"
+
+#include "remote-port-tlm.h"
+#include "remote-port-tlm-memory-master.h"
+#include "remote-port-tlm-memory-slave.h"
+#include "remote-port-tlm-wires.h"
+
+class xilinx_zynq
+: public remoteport_tlm
+{
+private:
+	remoteport_tlm_memory_master rp_m_axi_gp0;
+	remoteport_tlm_memory_master rp_m_axi_gp1;
+
+	remoteport_tlm_memory_slave rp_s_axi_gp0;
+	remoteport_tlm_memory_slave rp_s_axi_gp1;
+
+	remoteport_tlm_memory_slave rp_s_axi_hp0;
+	remoteport_tlm_memory_slave rp_s_axi_hp1;
+	remoteport_tlm_memory_slave rp_s_axi_hp2;
+	remoteport_tlm_memory_slave rp_s_axi_hp3;
+
+	remoteport_tlm_memory_slave rp_s_axi_acp;
+
+	remoteport_tlm_wires rp_wires_in;
+	remoteport_tlm_wires rp_wires_out;
+	remoteport_tlm_wires rp_irq_out;
+
+public:
+	/*
+	 * M_AXI_GP 0 - 1.
+	 * These sockets represent the High speed PS to PL interfaces.
+	 * These are AXI Slave ports on the PS side and AXI Master ports
+	 * on the PL side.
+	 *
+	 * Used to transfer data from the PS to the PL.
+	 */
+	tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
+
+	/*
+	 * S_AXI_GP0 - 1.
+	 * These sockets represent the High speed IO Coherent PL to PS
+	 * interfaces.
+	 *
+	 * HP0 - 3.
+	 * These sockets represent the High performance dataflow PL to PS interfaces.
+	 *
+	 * ACP
+	 * Accelerator Coherency Port, used to transfered coherent data to
+	 * the PS via the Cortex-A9 subsystem.
+	 *
+	 * These are AXI Master ports on the PS side and AXI Slave ports
+	 * on the PL side.
+	 *
+	 * Used to transfer data from the PL to the PS.
+	 */
+	tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
+	tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
+	tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
+
+	/* PL (fabric) to PS interrupt signals.  */
+	sc_vector<sc_signal<bool> > pl2ps_irq;
+
+	/* PS to PL Interrupt signals.  */
+	sc_vector<sc_signal<bool> > ps2pl_irq;
+
+	/* FPGA out resets.  */
+	sc_vector<sc_signal<bool> > ps2pl_rst;
+
+	xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
+	//xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
+	//		Iremoteport_tlm_sync *sync = NULL);
+};

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0.xdc

@@ -0,0 +1,49 @@
+
+# file: design_1_rst_ps7_0_100M_0.xdc
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+set_false_path -to [get_pins -hier *cdc_to*/D]

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0.xml

@@ -0,0 +1,978 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_rst_ps7_0_100M_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>clock</spirit:name>
+      <spirit:displayName>Clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>slowest_sync_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
+          <spirit:description>Slowest Synchronous clock frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">design_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_PORT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ext_reset</spirit:name>
+      <spirit:displayName>Ext_Reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>aux_reset</spirit:name>
+      <spirit:displayName>aux_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>aux_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dbg_reset</spirit:name>
+      <spirit:displayName>DBG_Reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
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+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+        <spirit:displayName>Ext Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+        <spirit:displayName>Aux Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+        <spirit:displayName>Aux Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_BUS_RST</spirit:name>
+        <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_RST</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+        <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_ac75ef1e</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_rst_ps7_0_100M_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_rst_ps7_0_100M_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_rst_ps7_0_100M_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_rst_ps7_0_100M_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_rst_ps7_0_100M_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_rst_ps7_0_100M_0_board.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:userFileType>USED_IN_board</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_synthesisconstraints_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_rst_ps7_0_100M_0_ooc.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
+      </spirit:file>
+      <spirit:vendorExtensions>
+        <xilinx:subCoreRef>
+          <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
+            <xilinx:mode xilinx:name="copy_mode"/>
+          </xilinx:componentRef>
+        </xilinx:subCoreRef>
+      </spirit:vendorExtensions>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>proc_sys_reset_v5_0_13</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_rst_ps7_0_100M_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
+      </spirit:file>
+      <spirit:vendorExtensions>
+        <xilinx:subCoreRef>
+          <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
+            <xilinx:mode xilinx:name="copy_mode"/>
+          </xilinx:componentRef>
+        </xilinx:subCoreRef>
+      </spirit:vendorExtensions>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>proc_sys_reset_v5_0_13</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_rst_ps7_0_100M_0.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_rst_ps7_0_100M_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>Processor Reset System</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+      <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_RST</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_BUS_RST</spirit:name>
+      <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+      <spirit:displayName>Aux Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+      <spirit:displayName>Ext Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+      <spirit:displayName>Aux Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+      <spirit:displayName>Ext Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_rst_ps7_0_100M_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Processor System Reset</xilinx:displayName>
+      <xilinx:coreRevision>13</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_board.xdc

@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_ooc.xdc

@@ -0,0 +1,57 @@
+# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of AMD and is protected under U.S. and international copyright
+# and other intellectual property laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# AMD, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) AMD shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or AMD had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# AMD products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of AMD products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk]
+
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_sim_netlist.v

@@ -0,0 +1,985 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Sun Dec  1 11:10:19 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/hs/es-praktikum/Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_sim_netlist.v
+// Design      : design_1_rst_ps7_0_100M_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.1" *) 
+(* NotValidForBitStream *)
+module design_1_rst_ps7_0_100M_0
+   (slowest_sync_clk,
+    ext_reset_in,
+    aux_reset_in,
+    mb_debug_sys_rst,
+    dcm_locked,
+    mb_reset,
+    bus_struct_reset,
+    peripheral_reset,
+    interconnect_aresetn,
+    peripheral_aresetn);
+  (* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
+  input dcm_locked;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
+
+  wire aux_reset_in;
+  wire [0:0]bus_struct_reset;
+  wire dcm_locked;
+  wire ext_reset_in;
+  wire [0:0]interconnect_aresetn;
+  wire mb_debug_sys_rst;
+  wire mb_reset;
+  wire [0:0]peripheral_aresetn;
+  wire [0:0]peripheral_reset;
+  wire slowest_sync_clk;
+
+  (* C_AUX_RESET_HIGH = "1'b0" *) 
+  (* C_AUX_RST_WIDTH = "4" *) 
+  (* C_EXT_RESET_HIGH = "1'b0" *) 
+  (* C_EXT_RST_WIDTH = "4" *) 
+  (* C_FAMILY = "zynq" *) 
+  (* C_NUM_BUS_RST = "1" *) 
+  (* C_NUM_INTERCONNECT_ARESETN = "1" *) 
+  (* C_NUM_PERP_ARESETN = "1" *) 
+  (* C_NUM_PERP_RST = "1" *) 
+  design_1_rst_ps7_0_100M_0_proc_sys_reset U0
+       (.aux_reset_in(aux_reset_in),
+        .bus_struct_reset(bus_struct_reset),
+        .dcm_locked(dcm_locked),
+        .ext_reset_in(ext_reset_in),
+        .interconnect_aresetn(interconnect_aresetn),
+        .mb_debug_sys_rst(mb_debug_sys_rst),
+        .mb_reset(mb_reset),
+        .peripheral_aresetn(peripheral_aresetn),
+        .peripheral_reset(peripheral_reset),
+        .slowest_sync_clk(slowest_sync_clk));
+endmodule
+
+(* ORIG_REF_NAME = "cdc_sync" *) 
+module design_1_rst_ps7_0_100M_0_cdc_sync
+   (lpf_asr_reg,
+    scndry_out,
+    lpf_asr,
+    p_1_in,
+    p_2_in,
+    asr_lpf,
+    aux_reset_in,
+    slowest_sync_clk);
+  output lpf_asr_reg;
+  output scndry_out;
+  input lpf_asr;
+  input p_1_in;
+  input p_2_in;
+  input [0:0]asr_lpf;
+  input aux_reset_in;
+  input slowest_sync_clk;
+
+  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
+  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
+  wire Q;
+  wire asr_d1;
+  wire [0:0]asr_lpf;
+  wire aux_reset_in;
+  wire lpf_asr;
+  wire lpf_asr_reg;
+  wire p_1_in;
+  wire p_2_in;
+  wire scndry_out;
+  wire slowest_sync_clk;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = "FDR" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(asr_d1),
+        .Q(Q),
+        .R(1'b0));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 
+       (.I0(aux_reset_in),
+        .O(asr_d1));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = "FDR" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(Q),
+        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
+        .R(1'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = "FDR" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
+        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
+        .R(1'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = "FDR" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
+        .Q(scndry_out),
+        .R(1'b0));
+  LUT5 #(
+    .INIT(32'hEAAAAAA8)) 
+    lpf_asr_i_1
+       (.I0(lpf_asr),
+        .I1(p_1_in),
+        .I2(p_2_in),
+        .I3(scndry_out),
+        .I4(asr_lpf),
+        .O(lpf_asr_reg));
+endmodule
+
+(* ORIG_REF_NAME = "cdc_sync" *) 
+module design_1_rst_ps7_0_100M_0_cdc_sync_0
+   (lpf_exr_reg,
+    scndry_out,
+    lpf_exr,
+    p_1_in4_in,
+    p_2_in3_in,
+    exr_lpf,
+    mb_debug_sys_rst,
+    ext_reset_in,
+    slowest_sync_clk);
+  output lpf_exr_reg;
+  output scndry_out;
+  input lpf_exr;
+  input p_1_in4_in;
+  input p_2_in3_in;
+  input [0:0]exr_lpf;
+  input mb_debug_sys_rst;
+  input ext_reset_in;
+  input slowest_sync_clk;
+
+  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
+  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
+  wire Q;
+  wire exr_d1;
+  wire [0:0]exr_lpf;
+  wire ext_reset_in;
+  wire lpf_exr;
+  wire lpf_exr_reg;
+  wire mb_debug_sys_rst;
+  wire p_1_in4_in;
+  wire p_2_in3_in;
+  wire scndry_out;
+  wire slowest_sync_clk;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = "FDR" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(exr_d1),
+        .Q(Q),
+        .R(1'b0));
+  LUT2 #(
+    .INIT(4'hB)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 
+       (.I0(mb_debug_sys_rst),
+        .I1(ext_reset_in),
+        .O(exr_d1));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = "FDR" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(Q),
+        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
+        .R(1'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = "FDR" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
+        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
+        .R(1'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = "FDR" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0)) 
+    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
+        .Q(scndry_out),
+        .R(1'b0));
+  LUT5 #(
+    .INIT(32'hEAAAAAA8)) 
+    lpf_exr_i_1
+       (.I0(lpf_exr),
+        .I1(p_1_in4_in),
+        .I2(p_2_in3_in),
+        .I3(scndry_out),
+        .I4(exr_lpf),
+        .O(lpf_exr_reg));
+endmodule
+
+(* ORIG_REF_NAME = "lpf" *) 
+module design_1_rst_ps7_0_100M_0_lpf
+   (lpf_int,
+    slowest_sync_clk,
+    dcm_locked,
+    mb_debug_sys_rst,
+    ext_reset_in,
+    aux_reset_in);
+  output lpf_int;
+  input slowest_sync_clk;
+  input dcm_locked;
+  input mb_debug_sys_rst;
+  input ext_reset_in;
+  input aux_reset_in;
+
+  wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
+  wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
+  wire Q;
+  wire [0:0]asr_lpf;
+  wire aux_reset_in;
+  wire dcm_locked;
+  wire [0:0]exr_lpf;
+  wire ext_reset_in;
+  wire lpf_asr;
+  wire lpf_exr;
+  wire lpf_int;
+  wire lpf_int0__0;
+  wire mb_debug_sys_rst;
+  wire p_1_in;
+  wire p_1_in4_in;
+  wire p_2_in;
+  wire p_2_in3_in;
+  wire p_3_in1_in;
+  wire p_3_in6_in;
+  wire slowest_sync_clk;
+
+  design_1_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX 
+       (.asr_lpf(asr_lpf),
+        .aux_reset_in(aux_reset_in),
+        .lpf_asr(lpf_asr),
+        .lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
+        .p_1_in(p_1_in),
+        .p_2_in(p_2_in),
+        .scndry_out(p_3_in1_in),
+        .slowest_sync_clk(slowest_sync_clk));
+  design_1_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT 
+       (.exr_lpf(exr_lpf),
+        .ext_reset_in(ext_reset_in),
+        .lpf_exr(lpf_exr),
+        .lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
+        .mb_debug_sys_rst(mb_debug_sys_rst),
+        .p_1_in4_in(p_1_in4_in),
+        .p_2_in3_in(p_2_in3_in),
+        .scndry_out(p_3_in6_in),
+        .slowest_sync_clk(slowest_sync_clk));
+  FDRE #(
+    .INIT(1'b0)) 
+    \AUX_LPF[1].asr_lpf_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_3_in1_in),
+        .Q(p_2_in),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \AUX_LPF[2].asr_lpf_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_2_in),
+        .Q(p_1_in),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \AUX_LPF[3].asr_lpf_reg[3] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_1_in),
+        .Q(asr_lpf),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \EXT_LPF[1].exr_lpf_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_3_in6_in),
+        .Q(p_2_in3_in),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \EXT_LPF[2].exr_lpf_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_2_in3_in),
+        .Q(p_1_in4_in),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \EXT_LPF[3].exr_lpf_reg[3] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_1_in4_in),
+        .Q(exr_lpf),
+        .R(1'b0));
+  (* XILINX_LEGACY_PRIM = "SRL16" *) 
+  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
+  (* box_type = "PRIMITIVE" *) 
+  (* srl_name = "U0/\\EXT_LPF/POR_SRL_I " *) 
+  SRL16E #(
+    .INIT(16'hFFFF)) 
+    POR_SRL_I
+       (.A0(1'b1),
+        .A1(1'b1),
+        .A2(1'b1),
+        .A3(1'b1),
+        .CE(1'b1),
+        .CLK(slowest_sync_clk),
+        .D(1'b0),
+        .Q(Q));
+  FDRE #(
+    .INIT(1'b0)) 
+    lpf_asr_reg
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
+        .Q(lpf_asr),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    lpf_exr_reg
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
+        .Q(lpf_exr),
+        .R(1'b0));
+  LUT4 #(
+    .INIT(16'hFFFD)) 
+    lpf_int0
+       (.I0(dcm_locked),
+        .I1(lpf_exr),
+        .I2(lpf_asr),
+        .I3(Q),
+        .O(lpf_int0__0));
+  FDRE #(
+    .INIT(1'b0)) 
+    lpf_int_reg
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(lpf_int0__0),
+        .Q(lpf_int),
+        .R(1'b0));
+endmodule
+
+(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *) 
+(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *) 
+(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *) 
+(* ORIG_REF_NAME = "proc_sys_reset" *) 
+module design_1_rst_ps7_0_100M_0_proc_sys_reset
+   (slowest_sync_clk,
+    ext_reset_in,
+    aux_reset_in,
+    mb_debug_sys_rst,
+    dcm_locked,
+    mb_reset,
+    bus_struct_reset,
+    peripheral_reset,
+    interconnect_aresetn,
+    peripheral_aresetn);
+  input slowest_sync_clk;
+  input ext_reset_in;
+  input aux_reset_in;
+  input mb_debug_sys_rst;
+  input dcm_locked;
+  output mb_reset;
+  output [0:0]bus_struct_reset;
+  output [0:0]peripheral_reset;
+  output [0:0]interconnect_aresetn;
+  output [0:0]peripheral_aresetn;
+
+  wire Bsr_out;
+  wire MB_out;
+  wire Pr_out;
+  wire SEQ_n_3;
+  wire SEQ_n_4;
+  wire aux_reset_in;
+  wire [0:0]bus_struct_reset;
+  wire dcm_locked;
+  wire ext_reset_in;
+  wire [0:0]interconnect_aresetn;
+  wire lpf_int;
+  wire mb_debug_sys_rst;
+  wire mb_reset;
+  wire [0:0]peripheral_aresetn;
+  wire [0:0]peripheral_reset;
+  wire slowest_sync_clk;
+
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0),
+    .IS_C_INVERTED(1'b0),
+    .IS_D_INVERTED(1'b0),
+    .IS_R_INVERTED(1'b0)) 
+    \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(SEQ_n_3),
+        .Q(interconnect_aresetn),
+        .R(1'b0));
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b0),
+    .IS_C_INVERTED(1'b0),
+    .IS_D_INVERTED(1'b0),
+    .IS_R_INVERTED(1'b0)) 
+    \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(SEQ_n_4),
+        .Q(peripheral_aresetn),
+        .R(1'b0));
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b1),
+    .IS_C_INVERTED(1'b0),
+    .IS_D_INVERTED(1'b0),
+    .IS_R_INVERTED(1'b0)) 
+    \BSR_OUT_DFF[0].FDRE_BSR 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(Bsr_out),
+        .Q(bus_struct_reset),
+        .R(1'b0));
+  design_1_rst_ps7_0_100M_0_lpf EXT_LPF
+       (.aux_reset_in(aux_reset_in),
+        .dcm_locked(dcm_locked),
+        .ext_reset_in(ext_reset_in),
+        .lpf_int(lpf_int),
+        .mb_debug_sys_rst(mb_debug_sys_rst),
+        .slowest_sync_clk(slowest_sync_clk));
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b1),
+    .IS_C_INVERTED(1'b0),
+    .IS_D_INVERTED(1'b0),
+    .IS_R_INVERTED(1'b0)) 
+    FDRE_inst
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(MB_out),
+        .Q(mb_reset),
+        .R(1'b0));
+  (* box_type = "PRIMITIVE" *) 
+  FDRE #(
+    .INIT(1'b1),
+    .IS_C_INVERTED(1'b0),
+    .IS_D_INVERTED(1'b0),
+    .IS_R_INVERTED(1'b0)) 
+    \PR_OUT_DFF[0].FDRE_PER 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(Pr_out),
+        .Q(peripheral_reset),
+        .R(1'b0));
+  design_1_rst_ps7_0_100M_0_sequence_psr SEQ
+       (.Bsr_out(Bsr_out),
+        .MB_out(MB_out),
+        .Pr_out(Pr_out),
+        .bsr_reg_0(SEQ_n_3),
+        .lpf_int(lpf_int),
+        .pr_reg_0(SEQ_n_4),
+        .slowest_sync_clk(slowest_sync_clk));
+endmodule
+
+(* ORIG_REF_NAME = "sequence_psr" *) 
+module design_1_rst_ps7_0_100M_0_sequence_psr
+   (MB_out,
+    Bsr_out,
+    Pr_out,
+    bsr_reg_0,
+    pr_reg_0,
+    lpf_int,
+    slowest_sync_clk);
+  output MB_out;
+  output Bsr_out;
+  output Pr_out;
+  output bsr_reg_0;
+  output pr_reg_0;
+  input lpf_int;
+  input slowest_sync_clk;
+
+  wire Bsr_out;
+  wire Core_i_1_n_0;
+  wire MB_out;
+  wire Pr_out;
+  wire \bsr_dec_reg_n_0_[0] ;
+  wire \bsr_dec_reg_n_0_[2] ;
+  wire bsr_i_1_n_0;
+  wire bsr_reg_0;
+  wire \core_dec[0]_i_1_n_0 ;
+  wire \core_dec[2]_i_1_n_0 ;
+  wire \core_dec_reg_n_0_[0] ;
+  wire \core_dec_reg_n_0_[1] ;
+  wire from_sys_i_1_n_0;
+  wire lpf_int;
+  wire p_0_in;
+  wire [2:0]p_3_out;
+  wire [2:0]p_5_out;
+  wire pr_dec0__0;
+  wire \pr_dec_reg_n_0_[0] ;
+  wire \pr_dec_reg_n_0_[2] ;
+  wire pr_i_1_n_0;
+  wire pr_reg_0;
+  wire seq_clr;
+  wire [5:0]seq_cnt;
+  wire seq_cnt_en;
+  wire slowest_sync_clk;
+
+  (* SOFT_HLUTNM = "soft_lutpair4" *) 
+  LUT1 #(
+    .INIT(2'h1)) 
+    \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1 
+       (.I0(Bsr_out),
+        .O(bsr_reg_0));
+  (* SOFT_HLUTNM = "soft_lutpair5" *) 
+  LUT1 #(
+    .INIT(2'h1)) 
+    \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1 
+       (.I0(Pr_out),
+        .O(pr_reg_0));
+  (* SOFT_HLUTNM = "soft_lutpair3" *) 
+  LUT2 #(
+    .INIT(4'h2)) 
+    Core_i_1
+       (.I0(MB_out),
+        .I1(p_0_in),
+        .O(Core_i_1_n_0));
+  FDSE #(
+    .INIT(1'b1)) 
+    Core_reg
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(Core_i_1_n_0),
+        .Q(MB_out),
+        .S(lpf_int));
+  design_1_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
+       (.Q(seq_cnt),
+        .seq_clr(seq_clr),
+        .seq_cnt_en(seq_cnt_en),
+        .slowest_sync_clk(slowest_sync_clk));
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT4 #(
+    .INIT(16'h0090)) 
+    \bsr_dec[0]_i_1 
+       (.I0(seq_cnt_en),
+        .I1(seq_cnt[4]),
+        .I2(seq_cnt[3]),
+        .I3(seq_cnt[5]),
+        .O(p_5_out[0]));
+  (* SOFT_HLUTNM = "soft_lutpair6" *) 
+  LUT2 #(
+    .INIT(4'h8)) 
+    \bsr_dec[2]_i_1 
+       (.I0(\core_dec_reg_n_0_[1] ),
+        .I1(\bsr_dec_reg_n_0_[0] ),
+        .O(p_5_out[2]));
+  FDRE #(
+    .INIT(1'b0)) 
+    \bsr_dec_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_5_out[0]),
+        .Q(\bsr_dec_reg_n_0_[0] ),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \bsr_dec_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_5_out[2]),
+        .Q(\bsr_dec_reg_n_0_[2] ),
+        .R(1'b0));
+  (* SOFT_HLUTNM = "soft_lutpair4" *) 
+  LUT2 #(
+    .INIT(4'h2)) 
+    bsr_i_1
+       (.I0(Bsr_out),
+        .I1(\bsr_dec_reg_n_0_[2] ),
+        .O(bsr_i_1_n_0));
+  FDSE #(
+    .INIT(1'b1)) 
+    bsr_reg
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(bsr_i_1_n_0),
+        .Q(Bsr_out),
+        .S(lpf_int));
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT4 #(
+    .INIT(16'h9000)) 
+    \core_dec[0]_i_1 
+       (.I0(seq_cnt_en),
+        .I1(seq_cnt[4]),
+        .I2(seq_cnt[3]),
+        .I3(seq_cnt[5]),
+        .O(\core_dec[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair6" *) 
+  LUT2 #(
+    .INIT(4'h8)) 
+    \core_dec[2]_i_1 
+       (.I0(\core_dec_reg_n_0_[1] ),
+        .I1(\core_dec_reg_n_0_[0] ),
+        .O(\core_dec[2]_i_1_n_0 ));
+  FDRE #(
+    .INIT(1'b0)) 
+    \core_dec_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(\core_dec[0]_i_1_n_0 ),
+        .Q(\core_dec_reg_n_0_[0] ),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \core_dec_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(pr_dec0__0),
+        .Q(\core_dec_reg_n_0_[1] ),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \core_dec_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(\core_dec[2]_i_1_n_0 ),
+        .Q(p_0_in),
+        .R(1'b0));
+  (* SOFT_HLUTNM = "soft_lutpair3" *) 
+  LUT2 #(
+    .INIT(4'h8)) 
+    from_sys_i_1
+       (.I0(MB_out),
+        .I1(seq_cnt_en),
+        .O(from_sys_i_1_n_0));
+  FDSE #(
+    .INIT(1'b0)) 
+    from_sys_reg
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(from_sys_i_1_n_0),
+        .Q(seq_cnt_en),
+        .S(lpf_int));
+  LUT4 #(
+    .INIT(16'h0018)) 
+    pr_dec0
+       (.I0(seq_cnt_en),
+        .I1(seq_cnt[0]),
+        .I2(seq_cnt[2]),
+        .I3(seq_cnt[1]),
+        .O(pr_dec0__0));
+  LUT4 #(
+    .INIT(16'h0480)) 
+    \pr_dec[0]_i_1 
+       (.I0(seq_cnt_en),
+        .I1(seq_cnt[3]),
+        .I2(seq_cnt[5]),
+        .I3(seq_cnt[4]),
+        .O(p_3_out[0]));
+  LUT2 #(
+    .INIT(4'h8)) 
+    \pr_dec[2]_i_1 
+       (.I0(\core_dec_reg_n_0_[1] ),
+        .I1(\pr_dec_reg_n_0_[0] ),
+        .O(p_3_out[2]));
+  FDRE #(
+    .INIT(1'b0)) 
+    \pr_dec_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_3_out[0]),
+        .Q(\pr_dec_reg_n_0_[0] ),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \pr_dec_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(p_3_out[2]),
+        .Q(\pr_dec_reg_n_0_[2] ),
+        .R(1'b0));
+  (* SOFT_HLUTNM = "soft_lutpair5" *) 
+  LUT2 #(
+    .INIT(4'h2)) 
+    pr_i_1
+       (.I0(Pr_out),
+        .I1(\pr_dec_reg_n_0_[2] ),
+        .O(pr_i_1_n_0));
+  FDSE #(
+    .INIT(1'b1)) 
+    pr_reg
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(pr_i_1_n_0),
+        .Q(Pr_out),
+        .S(lpf_int));
+  FDRE #(
+    .INIT(1'b0)) 
+    seq_clr_reg
+       (.C(slowest_sync_clk),
+        .CE(1'b1),
+        .D(1'b1),
+        .Q(seq_clr),
+        .R(lpf_int));
+endmodule
+
+(* ORIG_REF_NAME = "upcnt_n" *) 
+module design_1_rst_ps7_0_100M_0_upcnt_n
+   (Q,
+    seq_clr,
+    seq_cnt_en,
+    slowest_sync_clk);
+  output [5:0]Q;
+  input seq_clr;
+  input seq_cnt_en;
+  input slowest_sync_clk;
+
+  wire [5:0]Q;
+  wire clear;
+  wire [5:0]q_int0;
+  wire seq_clr;
+  wire seq_cnt_en;
+  wire slowest_sync_clk;
+
+  LUT1 #(
+    .INIT(2'h1)) 
+    \q_int[0]_i_1 
+       (.I0(Q[0]),
+        .O(q_int0[0]));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT2 #(
+    .INIT(4'h6)) 
+    \q_int[1]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .O(q_int0[1]));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT3 #(
+    .INIT(8'h78)) 
+    \q_int[2]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .I2(Q[2]),
+        .O(q_int0[2]));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT4 #(
+    .INIT(16'h7F80)) 
+    \q_int[3]_i_1 
+       (.I0(Q[1]),
+        .I1(Q[0]),
+        .I2(Q[2]),
+        .I3(Q[3]),
+        .O(q_int0[3]));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT5 #(
+    .INIT(32'h7FFF8000)) 
+    \q_int[4]_i_1 
+       (.I0(Q[2]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(Q[3]),
+        .I4(Q[4]),
+        .O(q_int0[4]));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \q_int[5]_i_1 
+       (.I0(seq_clr),
+        .O(clear));
+  LUT6 #(
+    .INIT(64'h7FFFFFFF80000000)) 
+    \q_int[5]_i_2 
+       (.I0(Q[3]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(Q[2]),
+        .I4(Q[4]),
+        .I5(Q[5]),
+        .O(q_int0[5]));
+  FDRE #(
+    .INIT(1'b1)) 
+    \q_int_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[0]),
+        .Q(Q[0]),
+        .R(clear));
+  FDRE #(
+    .INIT(1'b1)) 
+    \q_int_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[1]),
+        .Q(Q[1]),
+        .R(clear));
+  FDRE #(
+    .INIT(1'b1)) 
+    \q_int_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[2]),
+        .Q(Q[2]),
+        .R(clear));
+  FDRE #(
+    .INIT(1'b1)) 
+    \q_int_reg[3] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[3]),
+        .Q(Q[3]),
+        .R(clear));
+  FDRE #(
+    .INIT(1'b1)) 
+    \q_int_reg[4] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[4]),
+        .Q(Q[4]),
+        .R(clear));
+  FDRE #(
+    .INIT(1'b1)) 
+    \q_int_reg[5] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[5]),
+        .Q(Q[5]),
+        .R(clear));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_stub.v

@@ -0,0 +1,33 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
+// Date        : Sun Dec  1 11:10:19 2024
+// Host        : BiermannSurface running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/hs/es-praktikum/Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_stub.v
+// Design      : design_1_rst_ps7_0_100M_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "proc_sys_reset,Vivado 2023.1" *)
+module design_1_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in, 
+  mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset, 
+  interconnect_aresetn, peripheral_aresetn)
+/* synthesis syn_black_box black_box_pad_pin="ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */
+/* synthesis syn_force_seq_prim="slowest_sync_clk" */;
+  input slowest_sync_clk /* synthesis syn_isclock = 1 */;
+  input ext_reset_in;
+  input aux_reset_in;
+  input mb_debug_sys_rst;
+  input dcm_locked;
+  output mb_reset;
+  output [0:0]bus_struct_reset;
+  output [0:0]peripheral_reset;
+  output [0:0]interconnect_aresetn;
+  output [0:0]peripheral_aresetn;
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/sim/design_1_rst_ps7_0_100M_0.vhd

@@ -0,0 +1,147 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
+-- IP Revision: 13
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY proc_sys_reset_v5_0_13;
+USE proc_sys_reset_v5_0_13.proc_sys_reset;
+
+ENTITY design_1_rst_ps7_0_100M_0 IS
+  PORT (
+    slowest_sync_clk : IN STD_LOGIC;
+    ext_reset_in : IN STD_LOGIC;
+    aux_reset_in : IN STD_LOGIC;
+    mb_debug_sys_rst : IN STD_LOGIC;
+    dcm_locked : IN STD_LOGIC;
+    mb_reset : OUT STD_LOGIC;
+    bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+  );
+END design_1_rst_ps7_0_100M_0;
+
+ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT proc_sys_reset IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_EXT_RST_WIDTH : INTEGER;
+      C_AUX_RST_WIDTH : INTEGER;
+      C_EXT_RESET_HIGH : STD_LOGIC;
+      C_AUX_RESET_HIGH : STD_LOGIC;
+      C_NUM_BUS_RST : INTEGER;
+      C_NUM_PERP_RST : INTEGER;
+      C_NUM_INTERCONNECT_ARESETN : INTEGER;
+      C_NUM_PERP_ARESETN : INTEGER
+    );
+    PORT (
+      slowest_sync_clk : IN STD_LOGIC;
+      ext_reset_in : IN STD_LOGIC;
+      aux_reset_in : IN STD_LOGIC;
+      mb_debug_sys_rst : IN STD_LOGIC;
+      dcm_locked : IN STD_LOGIC;
+      mb_reset : OUT STD_LOGIC;
+      bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+    );
+  END COMPONENT proc_sys_reset;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
+BEGIN
+  U0 : proc_sys_reset
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_EXT_RST_WIDTH => 4,
+      C_AUX_RST_WIDTH => 4,
+      C_EXT_RESET_HIGH => '0',
+      C_AUX_RESET_HIGH => '0',
+      C_NUM_BUS_RST => 1,
+      C_NUM_PERP_RST => 1,
+      C_NUM_INTERCONNECT_ARESETN => 1,
+      C_NUM_PERP_ARESETN => 1
+    )
+    PORT MAP (
+      slowest_sync_clk => slowest_sync_clk,
+      ext_reset_in => ext_reset_in,
+      aux_reset_in => aux_reset_in,
+      mb_debug_sys_rst => mb_debug_sys_rst,
+      dcm_locked => dcm_locked,
+      mb_reset => mb_reset,
+      bus_struct_reset => bus_struct_reset,
+      peripheral_reset => peripheral_reset,
+      interconnect_aresetn => interconnect_aresetn,
+      peripheral_aresetn => peripheral_aresetn
+    );
+END design_1_rst_ps7_0_100M_0_arch;

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/synth/design_1_rst_ps7_0_100M_0.vhd

@@ -0,0 +1,153 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
+-- IP Revision: 13
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY proc_sys_reset_v5_0_13;
+USE proc_sys_reset_v5_0_13.proc_sys_reset;
+
+ENTITY design_1_rst_ps7_0_100M_0 IS
+  PORT (
+    slowest_sync_clk : IN STD_LOGIC;
+    ext_reset_in : IN STD_LOGIC;
+    aux_reset_in : IN STD_LOGIC;
+    mb_debug_sys_rst : IN STD_LOGIC;
+    dcm_locked : IN STD_LOGIC;
+    mb_reset : OUT STD_LOGIC;
+    bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+  );
+END design_1_rst_ps7_0_100M_0;
+
+ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT proc_sys_reset IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_EXT_RST_WIDTH : INTEGER;
+      C_AUX_RST_WIDTH : INTEGER;
+      C_EXT_RESET_HIGH : STD_LOGIC;
+      C_AUX_RESET_HIGH : STD_LOGIC;
+      C_NUM_BUS_RST : INTEGER;
+      C_NUM_PERP_RST : INTEGER;
+      C_NUM_INTERCONNECT_ARESETN : INTEGER;
+      C_NUM_PERP_ARESETN : INTEGER
+    );
+    PORT (
+      slowest_sync_clk : IN STD_LOGIC;
+      ext_reset_in : IN STD_LOGIC;
+      aux_reset_in : IN STD_LOGIC;
+      mb_debug_sys_rst : IN STD_LOGIC;
+      dcm_locked : IN STD_LOGIC;
+      mb_reset : OUT STD_LOGIC;
+      bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+    );
+  END COMPONENT proc_sys_reset;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2023.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
+BEGIN
+  U0 : proc_sys_reset
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_EXT_RST_WIDTH => 4,
+      C_AUX_RST_WIDTH => 4,
+      C_EXT_RESET_HIGH => '0',
+      C_AUX_RESET_HIGH => '0',
+      C_NUM_BUS_RST => 1,
+      C_NUM_PERP_RST => 1,
+      C_NUM_INTERCONNECT_ARESETN => 1,
+      C_NUM_PERP_ARESETN => 1
+    )
+    PORT MAP (
+      slowest_sync_clk => slowest_sync_clk,
+      ext_reset_in => ext_reset_in,
+      aux_reset_in => aux_reset_in,
+      mb_debug_sys_rst => mb_debug_sys_rst,
+      dcm_locked => dcm_locked,
+      mb_reset => mb_reset,
+      bus_struct_reset => bus_struct_reset,
+      peripheral_reset => peripheral_reset,
+      interconnect_aresetn => interconnect_aresetn,
+      peripheral_aresetn => peripheral_aresetn
+    );
+END design_1_rst_ps7_0_100M_0_arch;

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xml

@@ -0,0 +1,270 @@
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+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/design_1_xlconstant_0_0.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/design_1_xlconstant_0_0_stub.sv</spirit:name>
+        <spirit:fileType>systemVerilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>xlconstant_v1_1_7</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_xlconstant_0_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xlconstant_v1_1_7</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_xlconstant_0_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>Gives a constant signed value.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_xlconstant_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_WIDTH</spirit:name>
+      <spirit:displayName>Const Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_VAL</spirit:name>
+      <spirit:displayName>Const Val</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Constant</xilinx:displayName>
+      <xilinx:coreRevision>7</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="412efde3"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.h

@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v

@@ -0,0 +1,68 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_0 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0_stub.sv

@@ -0,0 +1,79 @@
+// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+//------------------------------------------------------------------------------------
+// Filename:    xl_Constant_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//
+//------------------------------------------------------------------------------------
+`ifdef XILINX_SIMULATOR
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module design_1_xlconstant_0_0 (
+  output bit [0 : 0 ] dout
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module design_1_xlconstant_0_0 (dout)
+(* integer foreign = "SystemC";
+*);
+ output wire [0 : 0 ] dout;  
+endmodule
+`endif
+
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h

@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,long int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/synth/design_1_xlconstant_0_0.v

@@ -0,0 +1,69 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2023.1" *)
+(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{}" *)
+(* CORE_GENERATION_INFO = "design_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,CONST_WIDTH=1,CONST_VAL=0x1}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_0 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/399e/sources_1/new/axil_gpio.vhd

@@ -0,0 +1,89 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axil_gpio is
+
+generic (
+    GPI_WIDTH           : integer  := 4;
+    GPO_WIDTH           : integer  := 4     
+    );
+port (
+    S_AXIL_ACLK         : in  std_logic;
+    S_AXIL_ARESETN      : in  std_logic := '1';
+
+    S_AXIL_AWADDR       : in  std_logic_vector(14 downto 0) := (others=>'0');
+    S_AXIL_AWVALID      : in  std_logic := '0';
+    S_AXIL_AWREADY      : out std_logic;
+    S_AXIL_WDATA        : in  std_logic_vector(31 downto 0) := (others=>'0');
+    S_AXIL_WVALID       : in  std_logic := '0';
+    S_AXIL_WREADY       : out std_logic;    
+    S_AXIL_WSTRB        : in  std_logic_vector( 3 downto 0) := (others=>'0');    
+    S_AXIL_BVALID       : out std_logic;    
+    S_AXIL_BREADY       : in  std_logic := '1';
+    S_AXIL_BRESP        : out std_logic_vector( 1 downto 0);
+    S_AXIL_ARADDR       : in  std_logic_vector(14 downto 0) := (others=>'0');
+    S_AXIL_ARVALID      : in  std_logic := '0';
+    S_AXIL_ARREADY      : out std_logic;
+    S_AXIL_RDATA        : out std_logic_vector(31 downto 0);
+    S_AXIL_RVALID       : out std_logic;
+    S_AXIL_RREADY       : in  std_logic := '1';
+    S_AXIL_RRESP        : out std_logic_vector( 1 downto 0);
+
+    GPI	              : in  std_logic_vector (GPI_WIDTH-1 downto 0) := (others=>'0');
+    GPO	              : out std_logic_vector (GPO_WIDTH-1 downto 0)
+    );
+end;
+
+
+architecture rtl of axil_gpio is
+
+    signal gpo_sig : std_logic_vector (GPO_WIDTH-1 downto 0) := (others=>'0');
+
+begin
+    GPO            <= gpo_sig;
+    S_AXIL_BRESP   <= (others=>'0');    -- No write errors
+    S_AXIL_RRESP   <= (others=>'0');    -- No read errors   
+    S_AXIL_ARREADY <= '1';              -- IP is always ready
+    S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
+    S_AXIL_WREADY  <= S_AXIL_AWVALID and S_AXIL_WVALID;
+
+process begin
+    wait until rising_edge (S_AXIL_ACLK);
+         
+    if S_AXIL_ARESETN = '0' then
+        S_AXIL_BVALID  <= '0';
+        S_AXIL_RVALID  <= '0';
+        gpo_sig        <= (others=>'0');
+    else
+        if S_AXIL_RREADY = '1' then
+            S_AXIL_RVALID  <= '0';
+        end if;
+
+        if S_AXIL_ARVALID = '1' then
+            S_AXIL_RDATA   <= (others=>'0'); 
+            if S_AXIL_ARADDR(2) = '0' then
+                S_AXIL_RDATA(GPO_WIDTH-1 downto 0) <= gpo_sig;
+            else
+                S_AXIL_RDATA(GPI_WIDTH-1 downto 0) <= GPI;
+            end if;
+            S_AXIL_RVALID  <= '1';
+        end if;
+        
+        if S_AXIL_BREADY = '1' then
+            S_AXIL_BVALID  <= '0';
+        end if;
+
+        if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then    
+            S_AXIL_BVALID  <= '1';
+            for i in 0 to GPO_WIDTH-1 loop
+                if S_AXIL_WSTRB(i/8) = '1' then
+                    if S_AXIL_AWADDR(2) = '0' then
+                        gpo_sig(i) <= S_AXIL_WDATA(i);
+                    end if;
+                end if;
+            end loop;
+        end if;
+    end if;
+end process;
+end;

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v

@@ -0,0 +1,409 @@
+//-----------------------------------------------------------------------------
+//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+//--
+//-- This file contains confidential and proprietary information
+//-- of Xilinx, Inc. and is protected under U.S. and
+//-- international copyright and other intellectual property
+//-- laws.
+//--
+//-- DISCLAIMER
+//-- This disclaimer is not a license and does not grant any
+//-- rights to the materials distributed herewith. Except as
+//-- otherwise provided in a valid license issued to you by
+//-- Xilinx, and to the maximum extent permitted by applicable
+//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//-- (2) Xilinx shall not be liable (whether in contract or tort,
+//-- including negligence, or under any other theory of
+//-- liability) for any loss or damage of any kind or nature
+//-- related to, arising under or in connection with these
+//-- materials, including for any direct, or any indirect,
+//-- special, incidental, or consequential loss or damage
+//-- (including loss of data, profits, goodwill, or any type of
+//-- loss or damage suffered as a result of any action brought
+//-- by a third party) even if such damage or loss was
+//-- reasonably foreseeable or Xilinx had been advised of the
+//-- possibility of the same.
+//--
+//-- CRITICAL APPLICATIONS
+//-- Xilinx products are not designed or intended to be fail-
+//-- safe, or for use in any application requiring fail-safe
+//-- performance, such as life-support or safety devices or
+//-- systems, Class III medical devices, nuclear facilities,
+//-- applications related to the deployment of airbags, or any
+//-- other applications that could lead to death, personal
+//-- injury, or severe property or environmental damage
+//-- (individually and collectively, "Critical
+//-- Applications"). Customer assumes the sole risk and
+//-- liability of any use of Xilinx products in Critical
+//-- Applications, subject only to applicable laws and
+//-- regulations governing limitations on product liability.
+//--
+//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//-- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: ACP Transaction Checker
+// 
+// Check for optimized ACP transactions and flag if they are broken.
+// 
+// 
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   atc
+//     aw_atc
+//     w_atc
+//     b_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+module processing_system7_v5_5_atc #
+  (
+   parameter         C_FAMILY                         = "rtl",
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4,
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_ADDR_WIDTH                 = 32,
+                       // Width of all ADDR signals on SI and MI side of checker.
+                       // Range: 32.
+   parameter integer C_AXI_DATA_WIDTH                 = 64,
+                       // Width of all DATA signals on SI and MI side of checker.
+                       // Range: 64.
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_ARUSER_WIDTH               = 1,
+                       // Width of ARUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_WUSER_WIDTH                = 1,
+                       // Width of WUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_RUSER_WIDTH                = 1,
+                       // Width of RUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_BUSER_WIDTH                = 1
+                       // Width of BUSER signals. 
+                       // Range: >= 1.
+   )
+  (
+   // Global Signals
+   input  wire                                  ACLK,
+   input  wire                                  ARESETN,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [4-1:0]                          S_AXI_AWLEN,
+   input  wire [3-1:0]                          S_AXI_AWSIZE,
+   input  wire [2-1:0]                          S_AXI_AWBURST,
+   input  wire [2-1:0]                          S_AXI_AWLOCK,
+   input  wire [4-1:0]                          S_AXI_AWCACHE,
+   input  wire [3-1:0]                          S_AXI_AWPROT,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire                                  S_AXI_AWVALID,
+   output wire                                  S_AXI_AWREADY,
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_WID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0]         S_AXI_WSTRB,
+   input  wire                                  S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire                                  S_AXI_WVALID,
+   output wire                                  S_AXI_WREADY,
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_BID,
+   output wire [2-1:0]                          S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire                                  S_AXI_BVALID,
+   input  wire                                  S_AXI_BREADY,
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_ARID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,
+   input  wire [4-1:0]                          S_AXI_ARLEN,
+   input  wire [3-1:0]                          S_AXI_ARSIZE,
+   input  wire [2-1:0]                          S_AXI_ARBURST,
+   input  wire [2-1:0]                          S_AXI_ARLOCK,
+   input  wire [4-1:0]                          S_AXI_ARCACHE,
+   input  wire [3-1:0]                          S_AXI_ARPROT,
+   input  wire [C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,
+   input  wire                                  S_AXI_ARVALID,
+   output wire                                  S_AXI_ARREADY,
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_RID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_RDATA,
+   output wire [2-1:0]                          S_AXI_RRESP,
+   output wire                                  S_AXI_RLAST,
+   output wire [C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,
+   output wire                                  S_AXI_RVALID,
+   input  wire                                  S_AXI_RREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_AWID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_AWADDR,
+   output wire [4-1:0]                          M_AXI_AWLEN,
+   output wire [3-1:0]                          M_AXI_AWSIZE,
+   output wire [2-1:0]                          M_AXI_AWBURST,
+   output wire [2-1:0]                          M_AXI_AWLOCK,
+   output wire [4-1:0]                          M_AXI_AWCACHE,
+   output wire [3-1:0]                          M_AXI_AWPROT,
+   output wire [C_AXI_AWUSER_WIDTH-1:0]         M_AXI_AWUSER,
+   output wire                                  M_AXI_AWVALID,
+   input  wire                                  M_AXI_AWREADY,
+   // Master Interface Write Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0]         M_AXI_WSTRB,
+   output wire                                  M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]          M_AXI_WUSER,
+   output wire                                  M_AXI_WVALID,
+   input  wire                                  M_AXI_WREADY,
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_BID,
+   input  wire [2-1:0]                          M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]          M_AXI_BUSER,
+   input  wire                                  M_AXI_BVALID,
+   output wire                                  M_AXI_BREADY,
+   // Master Interface Read Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_ARID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_ARADDR,
+   output wire [4-1:0]                          M_AXI_ARLEN,
+   output wire [3-1:0]                          M_AXI_ARSIZE,
+   output wire [2-1:0]                          M_AXI_ARBURST,
+   output wire [2-1:0]                          M_AXI_ARLOCK,
+   output wire [4-1:0]                          M_AXI_ARCACHE,
+   output wire [3-1:0]                          M_AXI_ARPROT,
+   output wire [C_AXI_ARUSER_WIDTH-1:0]         M_AXI_ARUSER,
+   output wire                                  M_AXI_ARVALID,
+   input  wire                                  M_AXI_ARREADY,
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_RID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_RDATA,
+   input  wire [2-1:0]                          M_AXI_RRESP,
+   input  wire                                  M_AXI_RLAST,
+   input  wire [C_AXI_RUSER_WIDTH-1:0]          M_AXI_RUSER,
+   input  wire                                  M_AXI_RVALID,
+   output wire                                  M_AXI_RREADY,
+   
+   output wire                                  ERROR_TRIGGER,
+   output wire [C_AXI_ID_WIDTH-1:0]             ERROR_TRANSACTION_ID
+   );
+
+   
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  localparam C_FIFO_DEPTH_LOG            = 4;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Internal reset.
+  reg                                   ARESET;
+  
+  // AW->W command queue signals.
+  wire                                  cmd_w_valid;
+  wire                                  cmd_w_check;
+  wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id;
+  wire                                  cmd_w_ready;
+  
+  // W->B command queue signals.
+  wire                                  cmd_b_push;
+  wire                                  cmd_b_error;
+  wire [C_AXI_ID_WIDTH-1:0]             cmd_b_id;
+  wire                                  cmd_b_full;
+  wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr;
+  wire                                  cmd_b_ready;
+  
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Internal Reset
+  /////////////////////////////////////////////////////////////////////////////
+  always @ (posedge ACLK) begin
+    ARESET <= !ARESETN;
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Write Channels (AW/W/B)
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Write Address Channel.
+  processing_system7_v5_5_aw_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
+   .C_AXI_AWUSER_WIDTH          (C_AXI_AWUSER_WIDTH),
+   .C_FIFO_DEPTH_LOG            (C_FIFO_DEPTH_LOG)
+    ) write_addr_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (Out)
+    .cmd_w_valid                (cmd_w_valid),
+    .cmd_w_check                (cmd_w_check),
+    .cmd_w_id                   (cmd_w_id),
+    .cmd_w_ready                (cmd_w_ready),
+    .cmd_b_addr                 (cmd_b_addr),
+    .cmd_b_ready                (cmd_b_ready),
+   
+    // Slave Interface Write Address Ports
+    .S_AXI_AWID                 (S_AXI_AWID),
+    .S_AXI_AWADDR               (S_AXI_AWADDR),
+    .S_AXI_AWLEN                (S_AXI_AWLEN),
+    .S_AXI_AWSIZE               (S_AXI_AWSIZE),
+    .S_AXI_AWBURST              (S_AXI_AWBURST),
+    .S_AXI_AWLOCK               (S_AXI_AWLOCK),
+    .S_AXI_AWCACHE              (S_AXI_AWCACHE),
+    .S_AXI_AWPROT               (S_AXI_AWPROT),
+    .S_AXI_AWUSER               (S_AXI_AWUSER),
+    .S_AXI_AWVALID              (S_AXI_AWVALID),
+    .S_AXI_AWREADY              (S_AXI_AWREADY),
+    
+    // Master Interface Write Address Port
+    .M_AXI_AWID                 (M_AXI_AWID),
+    .M_AXI_AWADDR               (M_AXI_AWADDR),
+    .M_AXI_AWLEN                (M_AXI_AWLEN),
+    .M_AXI_AWSIZE               (M_AXI_AWSIZE),
+    .M_AXI_AWBURST              (M_AXI_AWBURST),
+    .M_AXI_AWLOCK               (M_AXI_AWLOCK),
+    .M_AXI_AWCACHE              (M_AXI_AWCACHE),
+    .M_AXI_AWPROT               (M_AXI_AWPROT),
+    .M_AXI_AWUSER               (M_AXI_AWUSER),
+    .M_AXI_AWVALID              (M_AXI_AWVALID),
+    .M_AXI_AWREADY              (M_AXI_AWREADY)
+   );
+   
+  // Write Data channel.
+  processing_system7_v5_5_w_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
+   .C_AXI_WUSER_WIDTH           (C_AXI_WUSER_WIDTH)
+    ) write_data_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (In)
+    .cmd_w_valid                (cmd_w_valid),
+    .cmd_w_check                (cmd_w_check),
+    .cmd_w_id                   (cmd_w_id),
+    .cmd_w_ready                (cmd_w_ready),
+    
+    // Command Interface (Out)
+    .cmd_b_push                 (cmd_b_push),
+    .cmd_b_error                (cmd_b_error),
+    .cmd_b_id                   (cmd_b_id),
+    .cmd_b_full                 (cmd_b_full),
+    
+    // Slave Interface Write Data Ports
+    .S_AXI_WID                  (S_AXI_WID),
+    .S_AXI_WDATA                (S_AXI_WDATA),
+    .S_AXI_WSTRB                (S_AXI_WSTRB),
+    .S_AXI_WLAST                (S_AXI_WLAST),
+    .S_AXI_WUSER                (S_AXI_WUSER),
+    .S_AXI_WVALID               (S_AXI_WVALID),
+    .S_AXI_WREADY               (S_AXI_WREADY),
+    
+    // Master Interface Write Data Ports
+    .M_AXI_WID                  (M_AXI_WID),
+    .M_AXI_WDATA                (M_AXI_WDATA),
+    .M_AXI_WSTRB                (M_AXI_WSTRB),
+    .M_AXI_WLAST                (M_AXI_WLAST),
+    .M_AXI_WUSER                (M_AXI_WUSER),
+    .M_AXI_WVALID               (M_AXI_WVALID),
+    .M_AXI_WREADY               (M_AXI_WREADY)
+   );
+   
+  // Write Response channel.
+  processing_system7_v5_5_b_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_BUSER_WIDTH           (C_AXI_BUSER_WIDTH),
+   .C_FIFO_DEPTH_LOG            (C_FIFO_DEPTH_LOG)
+    ) write_response_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (In)
+    .cmd_b_push                 (cmd_b_push),
+    .cmd_b_error                (cmd_b_error),
+    .cmd_b_id                   (cmd_b_id),
+    .cmd_b_full                 (cmd_b_full),
+    .cmd_b_addr                 (cmd_b_addr),
+    .cmd_b_ready                (cmd_b_ready),
+    
+    // Slave Interface Write Response Ports
+    .S_AXI_BID                  (S_AXI_BID),
+    .S_AXI_BRESP                (S_AXI_BRESP),
+    .S_AXI_BUSER                (S_AXI_BUSER),
+    .S_AXI_BVALID               (S_AXI_BVALID),
+    .S_AXI_BREADY               (S_AXI_BREADY),
+    
+    // Master Interface Write Response Ports
+    .M_AXI_BID                  (M_AXI_BID),
+    .M_AXI_BRESP                (M_AXI_BRESP),
+    .M_AXI_BUSER                (M_AXI_BUSER),
+    .M_AXI_BVALID               (M_AXI_BVALID),
+    .M_AXI_BREADY               (M_AXI_BREADY),
+    
+    // Trigger detection
+    .ERROR_TRIGGER              (ERROR_TRIGGER),
+    .ERROR_TRANSACTION_ID       (ERROR_TRANSACTION_ID)
+   );
+  
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Read Channels (AR/R)
+  /////////////////////////////////////////////////////////////////////////////
+  // Read Address Port
+  assign M_AXI_ARID     = S_AXI_ARID;
+  assign M_AXI_ARADDR   = S_AXI_ARADDR;
+  assign M_AXI_ARLEN    = S_AXI_ARLEN;
+  assign M_AXI_ARSIZE   = S_AXI_ARSIZE;
+  assign M_AXI_ARBURST  = S_AXI_ARBURST;
+  assign M_AXI_ARLOCK   = S_AXI_ARLOCK;
+  assign M_AXI_ARCACHE  = S_AXI_ARCACHE;
+  assign M_AXI_ARPROT   = S_AXI_ARPROT;
+  assign M_AXI_ARUSER   = S_AXI_ARUSER;
+  assign M_AXI_ARVALID  = S_AXI_ARVALID;
+  assign S_AXI_ARREADY  = M_AXI_ARREADY;
+   
+  // Read Data Port
+  assign S_AXI_RID      = M_AXI_RID;
+  assign S_AXI_RDATA    = M_AXI_RDATA;
+  assign S_AXI_RRESP    = M_AXI_RRESP;
+  assign S_AXI_RLAST    = M_AXI_RLAST;
+  assign S_AXI_RUSER    = M_AXI_RUSER;
+  assign S_AXI_RVALID   = M_AXI_RVALID;
+  assign M_AXI_RREADY   = S_AXI_RREADY;
+  
+  
+endmodule
+`default_nettype wire

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v

@@ -0,0 +1,298 @@
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Address Write Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   aw_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_aw_atc #
+  (
+   parameter         C_FAMILY                         = "rtl", 
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4, 
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_ADDR_WIDTH                 = 32, 
+                       // Width of all ADDR signals on SI and MI side of checker.
+                       // Range: 32.
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_FIFO_DEPTH_LOG                 = 4
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface
+   output reg                                   cmd_w_valid,
+   output wire                                  cmd_w_check,
+   output wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id,
+   input  wire                                  cmd_w_ready,
+   input  wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr,
+   input  wire                                  cmd_b_ready,
+   
+   // Slave Interface Write Address Port
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [4-1:0]                          S_AXI_AWLEN,
+   input  wire [3-1:0]                          S_AXI_AWSIZE,
+   input  wire [2-1:0]                          S_AXI_AWBURST,
+   input  wire [2-1:0]                          S_AXI_AWLOCK,
+   input  wire [4-1:0]                          S_AXI_AWCACHE,
+   input  wire [3-1:0]                          S_AXI_AWPROT,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire                                  S_AXI_AWVALID,
+   output wire                                  S_AXI_AWREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_AWID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_AWADDR,
+   output wire [4-1:0]                          M_AXI_AWLEN,
+   output wire [3-1:0]                          M_AXI_AWSIZE,
+   output wire [2-1:0]                          M_AXI_AWBURST,
+   output wire [2-1:0]                          M_AXI_AWLOCK,
+   output wire [4-1:0]                          M_AXI_AWCACHE,
+   output wire [3-1:0]                          M_AXI_AWPROT,
+   output wire [C_AXI_AWUSER_WIDTH-1:0]         M_AXI_AWUSER,
+   output wire                                  M_AXI_AWVALID,
+   input  wire                                  M_AXI_AWREADY
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for burst types.
+  localparam [2-1:0] C_FIX_BURST         = 2'b00;
+  localparam [2-1:0] C_INCR_BURST        = 2'b01;
+  localparam [2-1:0] C_WRAP_BURST        = 2'b10;
+  
+  // Constants for size.
+  localparam [3-1:0] C_OPTIMIZED_SIZE    = 3'b011;
+  
+  // Constants for length.
+  localparam [4-1:0] C_OPTIMIZED_LEN     = 4'b0011;
+
+  // Constants for cacheline address.
+  localparam [4-1:0] C_NO_ADDR_OFFSET    = 5'b0;
+  
+  // Command FIFO settings
+  localparam C_FIFO_WIDTH                = C_AXI_ID_WIDTH + 1;
+  localparam C_FIFO_DEPTH                = 2 ** C_FIFO_DEPTH_LOG;
+    
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  integer index;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Transaction properties.
+  wire                                access_is_incr;
+  wire                                access_is_wrap;
+  wire                                access_is_coherent;
+  wire                                access_optimized_size;
+  wire                                incr_addr_boundary;
+  wire                                incr_is_optimized;
+  wire                                wrap_is_optimized;
+  wire                                access_is_optimized;
+  
+  // Command FIFO.
+  wire                                cmd_w_push;
+  reg                                 cmd_full;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         addr_ptr;
+  wire [C_FIFO_DEPTH_LOG-1:0]         all_addr_ptr;
+  reg  [C_FIFO_WIDTH-1:0]             data_srl[C_FIFO_DEPTH-1:0];
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Decode:
+  //
+  // Detect if transaction is of correct typ, size and length to qualify as
+  // an optimized transaction that has to be checked for errors.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Transaction burst type.
+  assign access_is_incr         = ( S_AXI_AWBURST == C_INCR_BURST );
+  assign access_is_wrap         = ( S_AXI_AWBURST == C_WRAP_BURST );
+  
+  // Transaction has to be Coherent.
+  assign access_is_coherent     = ( S_AXI_AWUSER[0]  == 1'b1 ) &
+                                  ( S_AXI_AWCACHE[1] == 1'b1 );
+  
+  // Transaction cacheline boundary address.
+  assign incr_addr_boundary     = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
+  
+  // Transaction length & size.
+  assign access_optimized_size  = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & 
+                                  ( S_AXI_AWLEN  == C_OPTIMIZED_LEN  );
+  
+  // Transaction is optimized.
+  assign incr_is_optimized      = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
+  assign wrap_is_optimized      = access_is_wrap & access_is_coherent & access_optimized_size;
+  assign access_is_optimized    = ( incr_is_optimized | wrap_is_optimized );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command FIFO:
+  //
+  // Since supported write interleaving is only 1, it is safe to use only a 
+  // simple SRL based FIFO as a command queue.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+    
+  // Determine when transaction infromation is pushed to the FIFO.
+  assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
+  
+  // SRL FIFO Pointer.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
+    end else begin
+      if ( cmd_w_push & ~cmd_w_ready ) begin
+        addr_ptr <= addr_ptr + 1;
+      end else if ( ~cmd_w_push & cmd_w_ready ) begin
+        addr_ptr <= addr_ptr - 1;
+      end
+    end
+  end
+  
+  // Total number of buffered commands.
+  assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
+  
+  // FIFO Flags.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_full    <= 1'b0;
+      cmd_w_valid <= 1'b0;
+    end else begin
+      if ( cmd_w_push & ~cmd_w_ready ) begin
+        cmd_w_valid <= 1'b1;
+      end else if ( ~cmd_w_push & cmd_w_ready ) begin
+        cmd_w_valid <= ( addr_ptr != 0 );
+      end
+      if ( cmd_w_push & ~cmd_b_ready ) begin
+        // Going to full.
+        cmd_full    <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
+      end else if ( ~cmd_w_push & cmd_b_ready ) begin
+        // Pop in middle of queue doesn't affect full status.
+        cmd_full    <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
+      end
+    end
+  end
+  
+  // Infere SRL for storage.
+  always @ (posedge ACLK) begin
+    if ( cmd_w_push ) begin
+      for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
+        data_srl[index+1] <= data_srl[index];
+      end
+      data_srl[0]   <= {access_is_optimized, S_AXI_AWID};
+    end
+  end
+  
+  // Get current transaction info.
+  assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Stall commands if FIFO is full. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign M_AXI_AWVALID   = S_AXI_AWVALID & ~cmd_full;
+  
+  // Return ready with push back.
+  assign S_AXI_AWREADY   = M_AXI_AWREADY & ~cmd_full;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Address Write propagation:
+  //
+  // All information is simply forwarded on from the SI- to MI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign M_AXI_AWID      = S_AXI_AWID; 
+  assign M_AXI_AWADDR    = S_AXI_AWADDR;
+  assign M_AXI_AWLEN     = S_AXI_AWLEN;
+  assign M_AXI_AWSIZE    = S_AXI_AWSIZE;
+  assign M_AXI_AWBURST   = S_AXI_AWBURST;
+  assign M_AXI_AWLOCK    = S_AXI_AWLOCK;
+  assign M_AXI_AWCACHE   = S_AXI_AWCACHE;
+  assign M_AXI_AWPROT    = S_AXI_AWPROT;
+  assign M_AXI_AWUSER    = S_AXI_AWUSER;
+  
+  
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v

@@ -0,0 +1,413 @@
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Response Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   b_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_b_atc #
+  (
+   parameter         C_FAMILY                         = "rtl", 
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4, 
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_BUSER_WIDTH                = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_FIFO_DEPTH_LOG                 = 4
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface
+   input  wire                                  cmd_b_push,
+   input  wire                                  cmd_b_error,
+   input  wire [C_AXI_ID_WIDTH-1:0]             cmd_b_id,
+   output wire                                  cmd_b_ready,
+   output wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr,
+   output reg                                   cmd_b_full,
+   
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_BID,
+   output reg  [2-1:0]                          S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire                                  S_AXI_BVALID,
+   input  wire                                  S_AXI_BREADY,
+
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_BID,
+   input  wire [2-1:0]                          M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]          M_AXI_BUSER,
+   input  wire                                  M_AXI_BVALID,
+   output wire                                  M_AXI_BREADY,
+   
+   // Trigger detection
+   output reg                                   ERROR_TRIGGER,
+   output reg  [C_AXI_ID_WIDTH-1:0]             ERROR_TRANSACTION_ID
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for packing levels.
+  localparam [2-1:0] C_RESP_OKAY         = 2'b00;
+  localparam [2-1:0] C_RESP_EXOKAY       = 2'b01;
+  localparam [2-1:0] C_RESP_SLVERROR     = 2'b10;
+  localparam [2-1:0] C_RESP_DECERR       = 2'b11;
+  
+  // Command FIFO settings
+  localparam C_FIFO_WIDTH                = C_AXI_ID_WIDTH + 1;
+  localparam C_FIFO_DEPTH                = 2 ** C_FIFO_DEPTH_LOG;
+    
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  integer index;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Command Queue.
+  reg  [C_FIFO_DEPTH_LOG-1:0]         addr_ptr;
+  reg  [C_FIFO_WIDTH-1:0]             data_srl[C_FIFO_DEPTH-1:0];
+  reg                                 cmd_b_valid;
+  wire                                cmd_b_ready_i;
+  wire                                inject_error;
+  wire [C_AXI_ID_WIDTH-1:0]           current_id;
+  
+  // Search command.
+  wire                                found_match;
+  wire                                use_match;
+  wire                                matching_id;
+  
+  // Manage valid command.
+  wire                                write_valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             updated_valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             next_valid_cmd;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         search_addr_ptr;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         collapsed_addr_ptr;
+  
+  // Pipelined data
+  reg  [C_AXI_ID_WIDTH-1:0]           M_AXI_BID_I;
+  reg  [2-1:0]                        M_AXI_BRESP_I;
+  reg  [C_AXI_BUSER_WIDTH-1:0]        M_AXI_BUSER_I;
+  reg                                 M_AXI_BVALID_I;
+  wire                                M_AXI_BREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command Queue:
+  //
+  // Keep track of depth of Queue to generate full flag.
+  // 
+  // Also generate valid to mark pressence of commands in Queue.
+  // 
+  // Maintain Queue and extract data from currently searched entry.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // SRL FIFO Pointer.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
+    end else begin
+      if ( cmd_b_push & ~cmd_b_ready_i ) begin
+        // Pushing data increase length/addr.
+        addr_ptr <= addr_ptr + 1;
+      end else if ( cmd_b_ready_i ) begin
+        // Collapse addr when data is popped.
+        addr_ptr <= collapsed_addr_ptr;
+      end
+    end
+  end
+  
+  // FIFO Flags.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_b_full  <= 1'b0;
+      cmd_b_valid <= 1'b0;
+    end else begin
+      if ( cmd_b_push & ~cmd_b_ready_i ) begin
+        cmd_b_full  <= ( addr_ptr == C_FIFO_DEPTH-3 );
+        cmd_b_valid <= 1'b1;
+      end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
+        cmd_b_full  <= 1'b0;
+        cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
+      end
+    end
+  end
+  
+  // Infere SRL for storage.
+  always @ (posedge ACLK) begin
+    if ( cmd_b_push ) begin
+      for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
+        data_srl[index+1] <= data_srl[index];
+      end
+      data_srl[0]   <= {cmd_b_error, cmd_b_id};
+    end
+  end
+  
+  // Get current transaction info.
+  assign {inject_error, current_id} = data_srl[search_addr_ptr];
+  
+  // Assign outputs.
+  assign cmd_b_addr = collapsed_addr_ptr;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Search Command Queue:
+  //
+  // Search for matching valid command in queue.
+  // 
+  // A command is found when an valid entry with correct ID is found. The queue
+  // is search from the oldest entry, i.e. from a high value.
+  // When new commands are pushed the search address has to be updated to always 
+  // start the search from the oldest available.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Handle search addr.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
+    end else begin
+      if ( cmd_b_ready_i ) begin
+        // Collapse addr when data is popped.
+        search_addr_ptr <= collapsed_addr_ptr;
+        
+      end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
+        // Skip non valid command.
+        search_addr_ptr <= search_addr_ptr - 1;
+        
+      end else if ( cmd_b_push ) begin
+        search_addr_ptr <= search_addr_ptr + 1;
+        
+      end
+    end
+  end
+  
+  // Check if searched command is valid and match ID (for existing response on MI side).
+  assign matching_id  = ( M_AXI_BID_I == current_id );
+  assign found_match  = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
+  assign use_match    = found_match & S_AXI_BREADY;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Track Used Commands:
+  //
+  // Actions that affect Valid Command:
+  // * When a new command is pushed
+  //   => Shift valid vector one step
+  // * When a command is used
+  //   => Clear corresponding valid bit
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Valid command status is updated when a command is used or a new one is pushed.
+  assign write_valid_cmd  = cmd_b_push | cmd_b_ready_i;
+  
+  // Update the used command valid bit.
+  always @ *
+  begin
+    updated_valid_cmd                   = valid_cmd;
+    updated_valid_cmd[search_addr_ptr]  = ~use_match;
+  end
+  
+  // Shift valid vector when command is pushed.
+  always @ *
+  begin
+    if ( cmd_b_push ) begin
+      next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
+    end else begin
+      next_valid_cmd = updated_valid_cmd;
+    end
+  end
+  
+  // Valid signals for next cycle.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      valid_cmd <= {C_FIFO_WIDTH{1'b0}};
+    end else if ( write_valid_cmd ) begin
+      valid_cmd <= next_valid_cmd;
+    end
+  end
+  
+  // Detect oldest available command in Queue.
+  always @ *
+  begin
+    // Default to empty.
+    collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
+    
+    for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
+      if ( next_valid_cmd[index] ) begin
+        collapsed_addr_ptr = index;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Pipe incoming data:
+  // 
+  // The B channel is piped to improve timing and avoid impact in search
+  // mechanism due to late arriving signals.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Clock data.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      M_AXI_BID_I     <= {C_AXI_ID_WIDTH{1'b0}};
+      M_AXI_BRESP_I   <= 2'b00;
+      M_AXI_BUSER_I   <= {C_AXI_BUSER_WIDTH{1'b0}};
+      M_AXI_BVALID_I  <= 1'b0;
+    end else begin
+      if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
+        M_AXI_BVALID_I  <= 1'b0;
+      end
+      if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
+        M_AXI_BID_I     <= M_AXI_BID;
+        M_AXI_BRESP_I   <= M_AXI_BRESP;
+        M_AXI_BUSER_I   <= M_AXI_BUSER;
+        M_AXI_BVALID_I  <= 1'b1;
+      end
+    end
+  end
+  
+  // Generate ready to get new transaction.
+  assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Inject Error:
+  //
+  // BRESP is modified according to command information.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Inject error in response.
+  always @ *
+  begin
+    if ( inject_error ) begin
+      S_AXI_BRESP = C_RESP_SLVERROR;
+    end else begin
+      S_AXI_BRESP = M_AXI_BRESP_I;
+    end
+  end
+  
+  // Handle interrupt generation.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      ERROR_TRIGGER        <= 1'b0;
+      ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
+    end else begin
+      if ( inject_error & cmd_b_ready_i ) begin
+        ERROR_TRIGGER        <= 1'b1;
+        ERROR_TRANSACTION_ID <= M_AXI_BID_I;
+      end else begin
+        ERROR_TRIGGER        <= 1'b0;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Response is passed forward when a matching entry has been found in queue.
+  // Both ready and valid are set when the command is completed.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign S_AXI_BVALID   = M_AXI_BVALID_I & cmd_b_valid & found_match;
+  
+  // Return ready with push back.
+  assign M_AXI_BREADY_I = cmd_b_valid & use_match;
+  
+  // Command has been handled.
+  assign cmd_b_ready_i  = M_AXI_BVALID_I & cmd_b_valid & use_match;
+  assign cmd_b_ready    = cmd_b_ready_i;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Write Response Propagation:
+  //
+  // All information is simply forwarded on from MI- to SI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign S_AXI_BID    = M_AXI_BID_I;
+  assign S_AXI_BUSER  = M_AXI_BUSER_I;
+  
+  
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v

@@ -0,0 +1,310 @@
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+// Filename:      trace_buffer.v
+// Description:   Trace port buffer 
+//-----------------------------------------------------------------------------
+// Structure:   This section shows the hierarchical structure of 
+//              pss_wrapper.
+//
+//              --processing_system7
+//							 |	
+//							 --trace_buffer
+//-----------------------------------------------------------------------------
+
+
+module processing_system7_v5_5_trace_buffer #
+  (
+   parameter integer FIFO_SIZE = 128,
+	parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
+   parameter integer C_DELAY_CLKS = 12
+   )
+  (
+   input wire TRACE_CLK,
+   input wire RST,
+   input wire TRACE_VALID_IN,
+   input wire [3:0] TRACE_ATID_IN,
+   input wire [31:0] TRACE_DATA_IN,
+   output wire TRACE_VALID_OUT,
+   output wire [3:0] TRACE_ATID_OUT,
+   output wire [31:0] TRACE_DATA_OUT
+  );
+
+//------------------------------------------------------------
+// Architecture section
+//------------------------------------------------------------
+
+// function called clogb2 that returns an integer which has the 
+// value of the ceiling of the log base 2.
+
+function integer clogb2 (input integer bit_depth);
+ integer i;
+ integer temp_log;
+ begin
+  temp_log = 0;
+  for(i=bit_depth; i > 0; i = i>>1)
+  clogb2 = temp_log;
+  temp_log=temp_log+1;		
+ end
+endfunction
+
+localparam DEPTH  = clogb2(FIFO_SIZE-1);
+
+wire [31:0] reset_zeros;
+reg  [31:0] trace_pedge; // write enable for FIFO
+reg  [31:0] ti;
+reg  [31:0] tom;
+
+reg  [3:0] atid;
+
+reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory 
+
+reg  [4:0]  dly_ctr;
+reg  [DEPTH-1:0]  fifo_wp;
+reg  [DEPTH-1:0]  fifo_rp;
+
+reg         fifo_re;
+wire        fifo_empty;
+wire        fifo_full;
+reg         fifo_full_reg;
+
+assign reset_zeros = 32'h0;  
+
+
+// Pipeline Stage for Traceport ATID ports
+  always @(posedge TRACE_CLK) begin
+    // process pedge_ti
+    // rising clock edge
+    if((RST == 1'b1)) begin
+      atid <= reset_zeros;
+    end
+    else begin	 
+      atid <= TRACE_ATID_IN;
+	 end
+  end
+
+  assign TRACE_ATID_OUT = atid;
+  
+  /////////////////////////////////////////////
+  // Generate FIFO data based on TRACE_VALID_IN
+  /////////////////////////////////////////////
+  generate
+    if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
+  /////////////////////////////////////////////
+        
+		  // memory update process
+		  // Update memory when positive edge detected and FIFO not full
+		  always @(posedge TRACE_CLK) begin
+				if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
+					trace_fifo[fifo_wp]  <= TRACE_DATA_IN;
+				end
+		  end
+
+		  // fifo write pointer
+		  always @(posedge TRACE_CLK) begin
+				// process
+			 if(RST == 1'b1) begin
+				fifo_wp <= {DEPTH{1'b0}};
+			 end
+			 else if(TRACE_VALID_IN ) begin
+				if(fifo_wp == (FIFO_SIZE - 1)) begin
+				  if (fifo_empty) begin
+					 fifo_wp <= {DEPTH{1'b0}};
+				  end
+				end
+				else begin
+				  fifo_wp <= fifo_wp + 1;
+				end
+			 end
+		  end
+
+
+  /////////////////////////////////////////////
+  // Generate FIFO data based on data edge
+  /////////////////////////////////////////////
+    end else begin : gen_data_edge_detector
+  /////////////////////////////////////////////
+
+
+		  // purpose: check for pos edge on any trace input
+		  always @(posedge TRACE_CLK) begin
+			 // process pedge_ti
+			 // rising clock edge
+			 if((RST == 1'b1)) begin
+				ti          <= reset_zeros;
+				trace_pedge <= reset_zeros;
+			 end
+			 else begin
+				ti          <= TRACE_DATA_IN;
+				trace_pedge <= (~ti & TRACE_DATA_IN);
+				//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) &  ~ti;
+				// posedge only
+			 end
+		  end
+		  
+		  // memory update process
+		  // Update memory when positive edge detected and FIFO not full
+		  always @(posedge TRACE_CLK) begin
+			 if(|(trace_pedge)  == 1'b1 && fifo_full_reg != 1'b1) begin
+				trace_fifo[fifo_wp]  <= trace_pedge;
+			 end
+		  end
+
+		  // fifo write pointer
+		  always @(posedge TRACE_CLK) begin
+				// process
+			 if(RST == 1'b1) begin
+				fifo_wp <= {DEPTH{1'b0}};
+			 end
+			 else if(|(trace_pedge)  == 1'b1) begin
+				if(fifo_wp == (FIFO_SIZE - 1)) begin
+				  if (fifo_empty) begin
+					 fifo_wp <= {DEPTH{1'b0}};
+				  end
+				end
+				else begin
+				  fifo_wp <= fifo_wp + 1;
+				end
+			 end
+		  end
+
+
+    end
+  endgenerate
+
+
+  always @(posedge TRACE_CLK) begin
+    tom <= trace_fifo[fifo_rp] ;
+  end
+
+
+//  // fifo write pointer
+//  always @(posedge TRACE_CLK) begin
+//      // process
+//    if(RST == 1'b1) begin
+//      fifo_wp <= {DEPTH{1'b0}};
+//    end
+//    else if(|(trace_pedge)  == 1'b1) begin
+//      if(fifo_wp == (FIFO_SIZE - 1)) begin
+//        fifo_wp <= {DEPTH{1'b0}};
+//      end
+//      else begin
+//        fifo_wp <= fifo_wp + 1;
+//      end
+//    end
+//  end
+
+
+  // fifo read pointer update
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1'b1) begin
+      fifo_rp <= {DEPTH{1'b0}};
+      fifo_re <= 1'b0;
+    end
+    else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
+      fifo_re <= 1'b1;
+      if(fifo_rp == (FIFO_SIZE - 1)) begin
+        fifo_rp <= {DEPTH{1'b0}};
+      end
+      else begin
+        fifo_rp <= fifo_rp + 1;
+      end
+    end
+    else begin
+      fifo_re <= 1'b0;
+    end
+  end
+  
+  // delay counter update
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1'b1) begin
+      dly_ctr <= 5'h0;
+    end
+    else if (fifo_re == 1'b1) begin
+      dly_ctr <= C_DELAY_CLKS-1;
+    end
+    else if(dly_ctr != 5'h0) begin
+      dly_ctr <= dly_ctr - 1;
+    end
+  end
+
+  // fifo empty update
+  assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
+
+  // fifo full update
+  assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
+
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1'b1) begin
+      fifo_full_reg <= 1'b0;
+    end
+    else if (fifo_empty) begin
+      fifo_full_reg <= 1'b0;
+	 end else begin	
+      fifo_full_reg <= fifo_full;
+    end
+  end  
+  
+//  always @(posedge TRACE_CLK) begin
+//    if(RST == 1'b1) begin
+//      fifo_full_reg <= 1'b0;
+//    end
+//    else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
+//      fifo_full_reg <= 1'b1;
+//    end
+//	 else begin
+//        fifo_full_reg <= 1'b0;
+//    end
+//  end  
+//  
+  assign TRACE_DATA_OUT     = tom;
+  
+  assign TRACE_VALID_OUT    = fifo_re;  
+  
+  
+
+
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v

@@ -0,0 +1,244 @@
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   w_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_w_atc #
+  (
+   parameter         C_FAMILY                         = "rtl",
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4,
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_DATA_WIDTH                 = 64,
+                       // Width of all DATA signals on SI and MI side of checker.
+                       // Range: 64.
+   parameter integer C_AXI_WUSER_WIDTH                = 1
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface (In)
+   input  wire                                  cmd_w_valid,
+   input  wire                                  cmd_w_check,
+   input  wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id,
+   output wire                                  cmd_w_ready,
+   
+   // Command Interface (Out)
+   output wire                                  cmd_b_push,
+   output wire                                  cmd_b_error,
+   output reg  [C_AXI_ID_WIDTH-1:0]             cmd_b_id,
+   input  wire                                  cmd_b_full,
+   
+   // Slave Interface Write Port
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_WID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0]         S_AXI_WSTRB,
+   input  wire                                  S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire                                  S_AXI_WVALID,
+   output wire                                  S_AXI_WREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0]         M_AXI_WSTRB,
+   output wire                                  M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]          M_AXI_WUSER,
+   output wire                                  M_AXI_WVALID,
+   input  wire                                  M_AXI_WREADY
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Detecttion.
+  wire                                any_strb_deasserted;
+  wire                                incoming_strb_issue;
+  reg                                 first_word;
+  reg                                 strb_issue;
+  
+  // Data flow.
+  wire                                data_pop;
+  wire                                cmd_b_push_blocked;
+  reg                                 cmd_b_push_i;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Detect error:
+  //
+  // Detect and accumulate error when a transaction shall be scanned for
+  // potential issues.
+  // Accumulation of error is restarted for each ne transaction. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Check stobe information
+  assign any_strb_deasserted  = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
+  assign incoming_strb_issue  = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
+  
+  // Keep track of first word in a transaction.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      first_word  <= 1'b1;
+    end else if ( data_pop ) begin
+      first_word  <= S_AXI_WLAST;
+    end
+  end
+  
+  // Keep track of error status.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      strb_issue  <= 1'b0;
+      cmd_b_id    <= {C_AXI_ID_WIDTH{1'b0}};
+    end else if ( data_pop ) begin
+      if ( first_word ) begin
+        strb_issue  <= incoming_strb_issue;
+      end else begin
+        strb_issue  <= incoming_strb_issue | strb_issue;
+      end
+      cmd_b_id    <= cmd_w_id;
+    end
+  end
+  
+  assign cmd_b_error  = strb_issue;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Control command queue to B:
+  //
+  // Push command to B queue when all data for the transaction has flowed  
+  // through.
+  // Delay pipelined command until there is room in the Queue.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Detect when data is popped.
+  assign data_pop   = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; 
+  
+  // Push command when last word in transfered (pipelined).
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_b_push_i  <= 1'b0;
+    end else begin
+      cmd_b_push_i  <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
+    end
+  end
+  
+  // Detect if pipelined push is blocked.
+  assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
+  
+  // Assign output.
+  assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Stall commands if FIFO is full or there is no valid command information 
+  // from AW. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign M_AXI_WVALID   = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
+  
+  // Return ready with push back.
+  assign S_AXI_WREADY   = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
+  
+  // End of burst.
+  assign cmd_w_ready    = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Write propagation:
+  //
+  // All information is simply forwarded on from the SI- to MI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign M_AXI_WID      = S_AXI_WID;
+  assign M_AXI_WDATA    = S_AXI_WDATA;
+  assign M_AXI_WSTRB    = S_AXI_WSTRB;
+  assign M_AXI_WLAST    = S_AXI_WLAST;
+  assign M_AXI_WUSER    = S_AXI_WUSER;
+  
+  
+endmodule

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_apis.v

@@ -0,0 +1,867 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_16_apis.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Set of Zynq VIP APIs that are used for writing tests.
+ *                
+ *****************************************************************************/
+
+  /* API for setting the STOP_ON_ERROR*/  
+  task automatic set_stop_on_error;
+    input LEVEL;
+    begin
+      $display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL);
+      STOP_ON_ERROR = LEVEL;
+//    M_AXI_GP0.master.set_stop_on_error(LEVEL);
+//    M_AXI_GP1.master.set_stop_on_error(LEVEL);
+//    S_AXI_GP0.slave.set_stop_on_error(LEVEL);
+//    S_AXI_GP1.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP0.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP1.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP2.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP3.slave.set_stop_on_error(LEVEL);
+//    S_AXI_ACP.slave.set_stop_on_error(LEVEL);
+      M_AXI_GP0.STOP_ON_ERROR = LEVEL;
+      M_AXI_GP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_GP0.STOP_ON_ERROR = LEVEL;
+      S_AXI_GP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP0.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP2.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP3.STOP_ON_ERROR = LEVEL;
+      S_AXI_ACP.STOP_ON_ERROR = LEVEL;
+
+    end
+  endtask 
+
+  /* API for setting the verbosity for channel level info*/  
+  task automatic set_channel_level_info;
+    input [1023:0] name;
+    input LEVEL;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO,  name , LEVEL);
+     case(name)
+//     "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
+//     "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
+//    "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
+      "ALL"       : begin
+//                     M_AXI_GP0.master.set_channel_level_info(LEVEL);
+//                     M_AXI_GP1.master.set_channel_level_info(LEVEL);
+//                    S_AXI_GP0.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_GP1.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP0.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP1.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP2.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP3.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_ACP.slave.set_channel_level_info(LEVEL);
+                    end
+      default     : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting the verbosity for function level info*/  
+  task automatic set_function_level_info;
+    input [1023:0] name;
+    input LEVEL;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO,  name , LEVEL);
+     case(name)
+//     "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL);
+//     "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL);
+//    "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
+//    "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
+//    "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
+      "ALL"       : begin
+//                     M_AXI_GP0.master.set_function_level_info(LEVEL);
+//                     M_AXI_GP1.master.set_function_level_info(LEVEL);
+//                    S_AXI_GP0.slave.set_function_level_info(LEVEL);
+//                    S_AXI_GP1.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP0.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP1.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP2.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP3.slave.set_function_level_info(LEVEL);
+//                    S_AXI_ACP.slave.set_function_level_info(LEVEL);
+                    end
+      default     : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting the Message verbosity */  
+  task automatic set_debug_level_info;
+    input LEVEL;
+    begin
+      $display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO,  LEVEL);
+      DEBUG_INFO = LEVEL;
+      M_AXI_GP0.DEBUG_INFO = LEVEL;
+      M_AXI_GP1.DEBUG_INFO = LEVEL;
+      S_AXI_GP0.DEBUG_INFO = LEVEL;
+      S_AXI_GP1.DEBUG_INFO = LEVEL;
+      S_AXI_HP0.DEBUG_INFO = LEVEL;
+      S_AXI_HP1.DEBUG_INFO = LEVEL;
+      S_AXI_HP2.DEBUG_INFO = LEVEL;
+      S_AXI_HP3.DEBUG_INFO = LEVEL;
+      S_AXI_ACP.DEBUG_INFO = LEVEL;
+      
+      ddrc.ddr.DEBUG_INFO = LEVEL;
+      ddrc.ddr_write_ports.DEBUG_INFO = LEVEL;
+      ddrc.ddr_read_ports.DEBUG_INFO = LEVEL;
+      
+      ocmc.ocm_write_ports.DEBUG_INFO = LEVEL;
+      ocmc.ocm_read_ports.DEBUG_INFO = LEVEL;
+      
+      icm.ssw.ocm_wr_hp.DEBUG_INFO = LEVEL;
+      icm.ssw.ocm_rd_hp.DEBUG_INFO = LEVEL;
+      icm.ssw.ddr_hp01.ddr_hp_wr.DEBUG_INFO = LEVEL;
+      icm.ssw.ddr_hp01.ddr_hp_rd.DEBUG_INFO = LEVEL;
+      icm.ssw.ddr_hp23.ddr_hp_wr.DEBUG_INFO = LEVEL;
+      icm.ssw.ddr_hp23.ddr_hp_rd.DEBUG_INFO = LEVEL;
+
+      icm.fmsw.ocm_gp_wr.DEBUG_INFO = LEVEL;
+      icm.fmsw.ddr_gp_wr.DEBUG_INFO = LEVEL;
+      icm.fmsw.ocm_gp_rd.DEBUG_INFO = LEVEL;
+      icm.fmsw.ddr_gp_rd.DEBUG_INFO = LEVEL;
+      icm.fmsw.reg_gp_rd.DEBUG_INFO = LEVEL;
+
+      icm.osw_wr.DEBUG_INFO = LEVEL;
+      icm.osw_rd.DEBUG_INFO = LEVEL;
+
+      regc.reg_read_ports.DEBUG_INFO = LEVEL;
+    end
+  endtask
+
+  /* API for setting ARQos Values */  
+  task automatic set_arqos;
+    input [1023:0] name;
+    input [axi_qos_width-1:0] value;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO,  name , value);
+     case(name)
+      "S_AXI_GP0" : S_AXI_GP0.set_arqos(value);
+      "S_AXI_GP1" : S_AXI_GP1.set_arqos(value);
+      "S_AXI_HP0" : S_AXI_HP0.set_arqos(value);
+      "S_AXI_HP1" : S_AXI_HP1.set_arqos(value);
+      "S_AXI_HP2" : S_AXI_HP2.set_arqos(value);
+      "S_AXI_HP3" : S_AXI_HP3.set_arqos(value);
+      "S_AXI_ACP" : S_AXI_ACP.set_arqos(value);
+      default     : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting AWQos Values */  
+  task automatic set_awqos;
+    input [1023:0] name;
+    input [axi_qos_width-1:0] value;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO,  name , value);
+     case(name)
+      "S_AXI_GP0" : S_AXI_GP0.set_awqos(value);
+      "S_AXI_GP1" : S_AXI_GP1.set_awqos(value);
+      "S_AXI_HP0" : S_AXI_HP0.set_awqos(value);
+      "S_AXI_HP1" : S_AXI_HP1.set_awqos(value);
+      "S_AXI_HP2" : S_AXI_HP2.set_awqos(value);
+      "S_AXI_HP3" : S_AXI_HP3.set_awqos(value);
+      "S_AXI_ACP" : S_AXI_ACP.set_awqos(value);
+      default     : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for soft reset control */
+  task automatic fpga_soft_reset;
+    input[data_width-1:0] reset_ctrl;
+    begin
+      if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO,  reset_ctrl); 
+      gen_rst.fpga_soft_reset(reset_ctrl);  
+    end
+  endtask
+
+    /* API for por and strb reset control */
+//    task automatic por_srstb_reset;
+//      input por_reset_ctrl;
+//      begin
+//        if(DEBUG_INFO) $display("[%0d] : %0s : POR and STRB Reset called for 0x%0h",$time, DISP_INFO,  por_reset_ctrl); 
+//  //      gen_rst.por_srstb_reset(por_reset_ctrl); 
+//        gen_rst.por_srstb_reset(por_reset_ctrl);  
+//  
+//      end
+//    endtask
+
+  /* API for pre-loading memories from (DDR/OCM model) */
+  task automatic pre_load_mem_from_file;
+    input [(max_chars*8)-1:0] file_name;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      succ = $fopen(file_name,"r");
+      if(succ == 0) begin
+        $display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name); 
+        if(STOP_ON_ERROR) $stop; 
+      end   
+      else if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+ 
+  /* API for pre-loading memories (DDR/OCM) */
+  task automatic pre_load_mem;
+    input [1:0] data_type;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+		          if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end
+        DDR_MEM : begin
+                  ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR) $stop; 
+      end
+    end
+  endtask
+
+  /* API for backdoor write to memories (DDR/OCM) */
+  task automatic write_mem;
+    input [max_burst_bits-1 :0] data;
+    input [addr_width-1:0] start_addr;
+    input [max_burst_bytes_width:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+		          if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.write_mem(data,start_addr,no_of_bytes,all_strb_valid); 
+                  else
+                    ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes,all_strb_valid); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end 
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+
+    /* read_memory */
+    task automatic read_mem;
+      input [addr_width-1:0] start_addr;
+      input [max_burst_bytes_width :0] no_of_bytes;
+      output[max_burst_bits-1 :0] data;
+      reg [1:0] mem_type;
+      integer succ;
+      begin
+        mem_type = decode_address(start_addr);
+        if(check_addr_aligned(start_addr)) begin    
+          case(mem_type)
+          OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.read_mem(data,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                    if(DEBUG_INFO)
+                      $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                    end 
+          DDR_MEM : begin
+                    ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
+                    if(DEBUG_INFO)
+                      $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                    end 
+          default : begin
+                    $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                    if(STOP_ON_ERROR) $stop; 
+                    end 
+          endcase
+        end else begin 
+          $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr);
+          if(STOP_ON_ERROR)
+            $stop; 
+        end
+      end
+  endtask
+
+  /* API for backdoor read to memories (DDR/OCM) */
+  task automatic peek_mem_to_file;
+    input [(max_chars*8)-1:0] file_name;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+
+  /* API to read interrupt status */
+  task automatic read_interrupt;
+    output[irq_width-1:0] irq_status;
+    begin
+      irq_status = IRQ_F2P;
+      if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO,  irq_status);
+    end
+  endtask
+
+  /* API to wait on interrup */
+  task automatic wait_interrupt;
+    input [3:0] irq;
+    output[irq_width-1:0] irq_status;
+    begin
+      if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO,  irq);
+
+      case(irq) 
+      0 :  wait(IRQ_F2P[0] === 1'b1);
+      1 :  wait(IRQ_F2P[1] === 1'b1);
+      2 :  wait(IRQ_F2P[2] === 1'b1);
+      3 :  wait(IRQ_F2P[3] === 1'b1);
+      4 :  wait(IRQ_F2P[4] === 1'b1);
+      5 :  wait(IRQ_F2P[5] === 1'b1);
+      6 :  wait(IRQ_F2P[6] === 1'b1);
+      7 :  wait(IRQ_F2P[7] === 1'b1);
+      8 :  wait(IRQ_F2P[8] === 1'b1);
+      9 :  wait(IRQ_F2P[9] === 1'b1);
+      10:  wait(IRQ_F2P[10] === 1'b1);
+      11:  wait(IRQ_F2P[11] === 1'b1);
+      12:  wait(IRQ_F2P[12] === 1'b1);
+      13:  wait(IRQ_F2P[13] === 1'b1);
+      14:  wait(IRQ_F2P[14] === 1'b1);
+      15:  wait(IRQ_F2P[15] === 1'b1);
+      default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR);
+      endcase
+      if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO,  irq);
+      irq_status = IRQ_F2P;
+    end
+  endtask
+
+  /* API to wait for a certain match pattern*/ 
+  task automatic wait_mem_update;
+    input[addr_width-1:0] address;
+    input[data_width-1:0] data_in;
+    output[data_width-1:0] data_out;
+    reg[data_width-1:0] datao;
+    begin
+      if(mem_update_key) begin
+        mem_update_key = 0;
+        if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in); 
+        if(check_addr_aligned(address)) begin
+         ddrc.ddr.wait_mem_update(address, datao);
+         if(datao != data_in)begin 
+           $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao);
+           $stop;
+         end else
+           $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO,  address, data_in);
+         data_out = datao;
+        end else begin
+           $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR,  address); 
+           if(STOP_ON_ERROR) $stop;
+        end
+        mem_update_key = 1;
+      end else 
+        $display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); 
+    end
+  endtask
+
+
+ /* API to initiate a WRITE transaction on one of the AXI-Master ports*/ 
+ task automatic write_from_file;
+   input [(max_chars*8)-1:0] file_name;
+   input [addr_width-1:0] start_addr;
+   input [int_width-1:0] wr_size;
+   output [axi_rsp_width-1:0] response;
+   integer succ;
+   begin
+      succ = $fopen(file_name,"r");
+      if(succ == 0) begin
+        $display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name); 
+        if(STOP_ON_ERROR) $stop; 
+      end   
+      else if(!check_master_address(start_addr)) begin
+         $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+      end else if(check_addr_aligned(start_addr)) begin
+         $fclose(succ);
+         // case(start_addr[31:30])
+         if (start_addr[31:30] === 2'b01) begin
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO,  start_addr, wr_size, file_name); 
+            M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end else if(start_addr[31:30] === 2'b10) begin
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO,  start_addr, wr_size, file_name); 
+            M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end else begin
+           $display("[%0d] : %0s : Invalid Address(0x%0h)  'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr); 
+          end
+         // endcase
+      end else begin
+          $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+          if(STOP_ON_ERROR) $stop;
+      end
+   end
+ endtask
+
+ /* API to initiate a READ transaction on one of the AXI-Master ports*/ 
+ task automatic read_to_file;
+   input [(max_chars*8)-1:0] file_name;
+   input [addr_width-1:0] start_addr;
+   input [int_width-1:0] rd_size;
+   output [axi_rsp_width-1:0] response;
+   begin
+      if(!check_master_address(start_addr)) begin
+         $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR ,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+      end else if(check_addr_aligned(start_addr)) begin
+         // case(start_addr[31:30])
+         if (start_addr[31:30] === 2'b01) begin
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO,  start_addr, rd_size, file_name); 
+            M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end else if(start_addr[31:30] === 2'b10) begin
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO,  start_addr, rd_size, file_name); 
+            M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          // end
+          // default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr); 
+         // endcase
+      end else begin
+          $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+          if(STOP_ON_ERROR) $stop;
+      end
+   end
+   end
+ endtask
+
+ /* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/ 
+ task automatic write_data;
+   input [addr_width-1:0] start_addr;
+   input [max_transfer_bytes_width:0] wr_size;
+   input [(max_transfer_bytes*8)-1:0] w_data;
+   output [axi_rsp_width-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+         $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(wr_size > max_transfer_bytes) begin
+         $display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, wr_size); 
+       M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, wr_size); 
+       M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); 
+   end
+ endtask
+
+ /* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/ 
+ task automatic read_data;
+   input [addr_width-1:0] start_addr;
+   input [max_transfer_bytes_width:0] rd_size;
+   output[(max_transfer_bytes*8)-1:0] rd_data;
+   output [axi_rsp_width-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(rd_size > max_transfer_bytes) begin
+         $display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO,  start_addr, rd_size); 
+       M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO,  start_addr, rd_size); 
+       M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr); 
+    end
+ endtask
+
+/* Hooks to call to VIP APIs */
+ task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === 2'b01) begin
+    // end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === 2'b10) begin
+    // end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr); 
+   end
+ endtask 
+
+ task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+   reg[511:0] rsp; /// string for response
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === 2'b01) begin
+    // end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === 2'b10) begin
+    // end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr); 
+   end
+ endtask 
+
+ task automatic read_burst;
+   input [addr_width-1:0] start_addr;
+   input [axi_len_width-1:0] len;
+   input [axi_size_width-1:0] siz;
+   input [axi_brst_type_width-1:0] burst;
+   input [axi_lock_width-1:0] lck;
+   input [axi_cache_width-1:0] cache;
+   input [axi_prot_width-1:0] prot;
+   output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
+   output [(axi_rsp_width*axi_burst_len)-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === 2'b01) begin
+    // end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO,  start_addr); 
+       M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === 2'b10) begin
+    // end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO,  start_addr); 
+       M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr); 
+    end
+ endtask 
+
+ task automatic wait_reg_update;
+   input [addr_width-1:0] addr;
+   input [data_width-1:0] data_i;
+   input [data_width-1:0] mask_i;
+   input [int_width-1:0] time_interval;
+   input [int_width-1:0] time_out;
+   output [data_width-1:0] data_o;
+
+   reg upd_done0;
+   reg upd_done1;
+   begin
+    if(!check_master_address(addr)) begin
+       $display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR,  addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(addr[31:30] === 2'b01) begin
+    // end else if(addr[31:30] === GP_M0) begin
+     if(reg_update_key_0) begin
+       reg_update_key_0 = 0;
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); 
+       M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
+       if(DEBUG_INFO && upd_done0)
+         $display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); 
+       reg_update_key_0 = 1;
+     end else
+       $display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); 
+    end else if(addr[31:30] === 2'b10) begin
+    // end else if(addr[31:30] === GP_M1) begin
+     if(reg_update_key_1) begin
+       reg_update_key_1 = 0;
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); 
+       M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
+       if(DEBUG_INFO && upd_done1)
+         $display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO,  addr); 
+       reg_update_key_1 = 1;
+     end else
+       $display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr); 
+   end
+ endtask 
+
+/* API to read register map */
+ task read_register_map;
+   input [addr_width-1:0] start_addr;
+   input [max_regs_width:0] no_of_registers;
+   output[max_burst_bits-1 :0] data;
+   reg [max_regs_width:0] no_of_regs;
+   begin
+    no_of_regs = no_of_registers;
+    if(no_of_registers > 32) begin
+      $display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr);
+      no_of_regs = 32;
+    end
+    if(check_addr_aligned(start_addr)) begin
+      if(decode_address(start_addr) == REG_MEM) begin
+        if(DEBUG_INFO)  $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO,  start_addr,no_of_regs ); 
+        regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
+        if(DEBUG_INFO)  $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO,  start_addr, data ); 
+      end else begin
+       $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
+      end
+    end else begin
+       data = 0;
+       $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
+    end
+   end
+ endtask
+
+/* API to read single register */
+ task read_register;
+   input [addr_width-1:0] addr;
+   output[data_width-1:0] data;
+   begin
+    if(check_addr_aligned(addr)) begin
+       if(decode_address(addr) == REG_MEM) begin
+         if(DEBUG_INFO)  $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO,  addr ); 
+         regc.regm.get_data(addr >> 2, data);
+         if(DEBUG_INFO)  $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO,  addr, data ); 
+       end else begin
+         $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr);
+       end
+    end else begin
+       data = 0;
+       $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr);
+    end
+
+   end
+ endtask
+
+  /* API to set the AXI-Slave profile*/ 
+ task automatic set_slave_profile;
+    input[1023:0] name;
+    input[1:0] latency ;
+    begin 
+     if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO,  name);
+     case(name)
+      "S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency);
+      "S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency);
+      "S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency);
+      "S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency);
+      "S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency);
+      "S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency);
+      "S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency);
+      "ALL"       : begin
+                     S_AXI_GP0.set_latency_type(latency);
+                     S_AXI_GP1.set_latency_type(latency);
+                     S_AXI_HP0.set_latency_type(latency);
+                     S_AXI_HP1.set_latency_type(latency);
+                     S_AXI_HP2.set_latency_type(latency);
+                     S_AXI_HP3.set_latency_type(latency);
+                     S_AXI_ACP.set_latency_type(latency);
+                    end  
+     endcase
+    end
+ endtask
+
+
+/*------------------------------ LOCAL APIs ------------------------------------------------ */
+
+  /* local API for address decoding*/
+  function automatic [1:0] decode_address;
+    input [addr_width-1:0] address;
+    begin
+      if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr )) 
+        decode_address = OCM_MEM; /// OCM 
+      else if(address >= ddr_start_addr && address <= ddr_end_addr)
+        decode_address = DDR_MEM; /// DDR 
+      else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
+        decode_address = OCM_MEM; /// OCM 
+      else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
+        decode_address = REG_MEM; /// Register Map
+      else
+        decode_address = INVALID_MEM_TYPE; /// ERROR in Address 
+    end
+  endfunction 
+
+  /* local API for checking address is 32-bit (4-byte) aligned */
+  function automatic check_addr_aligned;
+    input [addr_width-1:0] address;
+    begin 
+      if((address%4) !=0 ) begin // 
+        check_addr_aligned = 0; ///not_aligned
+      end else
+        check_addr_aligned = 1;
+    end
+  endfunction
+
+ /* local API to check address for GP Masters */
+ function check_master_address; 
+   input [addr_width-1:0] address;
+   begin
+     if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr) 
+       check_master_address = 1'b1; 
+     else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr) 
+       check_master_address = 1'b1; 
+     else
+       check_master_address = 1'b0; /// ERROR in Address 
+   end
+ endfunction
+
+ /* Response decode */
+ function automatic [511:0] get_resp;
+   input[axi_rsp_width-1:0] response;
+   begin 
+    case(response)
+     2'b00 : get_resp = "OKAY";
+     2'b01 : get_resp = "EXOKAY";
+     2'b10 : get_resp = "SLVERR";
+     2'b11 : get_resp = "DECERR";
+    endcase
+   end
+ endfunction 

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_axi_acp.v

@@ -0,0 +1,94 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_16_axi_acp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for ACP port
+ *
+ *****************************************************************************/
+
+/* AXI Slave ACP */
+  processing_system7_vip_v1_0_16_axi_slave_acp #( C_USE_S_AXI_ACP, // enable
+               axi_acp_name, // name
+               axi_acp_data_width, // data width
+               addr_width, /// address width
+               axi_acp_id_width, // ID width
+               C_S_AXI_ACP_BASEADDR, // slave base address
+               C_S_AXI_ACP_HIGHADDR,// slave size
+               axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes 
+               axi_slv_excl_support, // Exclusive access support
+               axi_acp_wr_outstanding,
+               axi_acp_rd_outstanding)
+  S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
+            .S_ACLK   (S_AXI_ACP_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_ACP_AWID),
+            .S_AWADDR  (S_AXI_ACP_AWADDR),
+            .S_AWLEN   (S_AXI_ACP_AWLEN),
+            .S_AWSIZE  (S_AXI_ACP_AWSIZE),
+            .S_AWBURST (S_AXI_ACP_AWBURST),
+            .S_AWLOCK  (S_AXI_ACP_AWLOCK),
+            .S_AWCACHE (S_AXI_ACP_AWCACHE),
+            .S_AWPROT  (S_AXI_ACP_AWPROT),
+            .S_AWVALID (S_AXI_ACP_AWVALID),
+            .S_AWREADY (S_AXI_ACP_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_ACP_WID),
+            .S_WDATA  (S_AXI_ACP_WDATA),
+            .S_WSTRB  (S_AXI_ACP_WSTRB), 
+            .S_WLAST  (S_AXI_ACP_WLAST), 
+            .S_WVALID (S_AXI_ACP_WVALID),
+            .S_WREADY (S_AXI_ACP_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_ACP_BID),
+            .S_BRESP  (S_AXI_ACP_BRESP),
+            .S_BVALID (S_AXI_ACP_BVALID),
+            .S_BREADY (S_AXI_ACP_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_ACP_ARID),
+            .S_ARADDR  (S_AXI_ACP_ARADDR),
+            .S_ARLEN   (S_AXI_ACP_ARLEN),
+            .S_ARSIZE  (S_AXI_ACP_ARSIZE),
+            .S_ARBURST (S_AXI_ACP_ARBURST),
+            .S_ARLOCK  (S_AXI_ACP_ARLOCK),
+            .S_ARCACHE (S_AXI_ACP_ARCACHE),
+            .S_ARPROT  (S_AXI_ACP_ARPROT),
+            .S_ARVALID (S_AXI_ACP_ARVALID),
+            .S_ARREADY (S_AXI_ACP_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_ACP_RID),
+            .S_RDATA  (S_AXI_ACP_RDATA),
+            .S_RRESP  (S_AXI_ACP_RRESP),
+            .S_RLAST  (S_AXI_ACP_RLAST),
+            .S_RVALID (S_AXI_ACP_RVALID),
+            .S_RREADY (S_AXI_ACP_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_ACP_AWQOS),
+            .S_ARQOS  (S_AXI_ACP_ARQOS),            // Side band signals 
+
+            .SW_CLK   (net_sw_clk),
+/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
+            .WR_DATA_ACK_DDR (ddr_wr_ack_port0),
+            .WR_DATA_ACK_OCM (ocm_wr_ack_port0),
+            .WR_DATA  (net_wr_data_acp), 
+            .WR_DATA_STRB  (net_wr_strb_acp), 
+            .WR_ADDR  (net_wr_addr_acp), 
+            .WR_BYTES  (net_wr_bytes_acp), 
+            .WR_DATA_VALID_DDR  (ddr_wr_dv_port0), 
+            .WR_DATA_VALID_OCM  (ocm_wr_dv_port0), 
+            .WR_QOS (net_wr_qos_acp),
+
+            .RD_REQ_DDR (ddr_rd_req_port0),
+            .RD_REQ_OCM (ocm_rd_req_port0),
+            .RD_REQ_REG (reg_rd_req_port0),
+            .RD_ADDR (net_rd_addr_acp),
+            .RD_DATA_DDR (ddr_rd_data_port0),
+            .RD_DATA_OCM (ocm_rd_data_port0),
+            .RD_DATA_REG (reg_rd_data_port0),
+            .RD_BYTES (net_rd_bytes_acp),
+            .RD_DATA_VALID_DDR (ddr_rd_dv_port0),
+            .RD_DATA_VALID_OCM (ocm_rd_dv_port0),
+            .RD_DATA_VALID_REG (reg_rd_dv_port0),
+            .RD_QOS (net_rd_qos_acp)
+
+);

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_axi_gp.v

@@ -0,0 +1,311 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_16_axi_gp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for AXI GP ports
+ *
+ *****************************************************************************/
+
+    /* IDs for Masters 
+       // l2m1 (CPU000)
+       12'b11_000_000_00_00    
+       12'b11_010_000_00_00     
+       12'b11_011_000_00_00   
+       12'b11_100_000_00_00   
+       12'b11_101_000_00_00   
+       12'b11_110_000_00_00     
+       12'b11_111_000_00_00     
+       // l2m1 (CPU001)
+       12'b11_000_001_00_00    
+       12'b11_010_001_00_00     
+       12'b11_011_001_00_00    
+       12'b11_100_001_00_00    
+       12'b11_101_001_00_00    
+       12'b11_110_001_00_00     
+       12'b11_111_001_00_00    
+   */
+ 
+/* AXI -Master GP0 */
+  processing_system7_vip_v1_0_16_axi_master #(C_USE_M_AXI_GP0, // enable
+               axi_mgp0_name,// name
+               axi_mgp_data_width, /// Data Width
+               addr_width, /// Address width
+               axi_mgp_id_width,  //// ID Width
+               axi_mgp_outstanding,  //// Outstanding transactions
+               axi_mst_excl_support, // EXCL Access Support
+               axi_mgp_wr_id, //WR_ID
+               axi_mgp_rd_id) //RD_ID
+  M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
+            .M_ACLK   (M_AXI_GP0_ACLK),
+            // Write Address Channel
+            .M_AWID    (M_AXI_GP0_AWID_FULL),
+            .M_AWADDR  (M_AXI_GP0_AWADDR),
+            .M_AWLEN   (M_AXI_GP0_AWLEN),
+            .M_AWSIZE  (M_AXI_GP0_AWSIZE),
+            .M_AWBURST (M_AXI_GP0_AWBURST),
+            .M_AWLOCK  (M_AXI_GP0_AWLOCK),
+            .M_AWCACHE (M_AXI_GP0_AWCACHE),
+            .M_AWPROT  (M_AXI_GP0_AWPROT),
+            .M_AWVALID (M_AXI_GP0_AWVALID),
+            .M_AWREADY (M_AXI_GP0_AWREADY),
+            // Write Data Channel Signals.
+            .M_WID    (M_AXI_GP0_WID_FULL),
+            .M_WDATA  (M_AXI_GP0_WDATA),
+            .M_WSTRB  (M_AXI_GP0_WSTRB), 
+            .M_WLAST  (M_AXI_GP0_WLAST), 
+            .M_WVALID (M_AXI_GP0_WVALID),
+            .M_WREADY (M_AXI_GP0_WREADY),
+            // Write Response Channel Signals.
+            .M_BID    (M_AXI_GP0_BID_FULL),
+            .M_BRESP  (M_AXI_GP0_BRESP),
+            .M_BVALID (M_AXI_GP0_BVALID),
+            .M_BREADY (M_AXI_GP0_BREADY),
+            // Read Address Channel Signals.
+            .M_ARID    (M_AXI_GP0_ARID_FULL),
+            .M_ARADDR  (M_AXI_GP0_ARADDR),
+            .M_ARLEN   (M_AXI_GP0_ARLEN),
+            .M_ARSIZE  (M_AXI_GP0_ARSIZE),
+            .M_ARBURST (M_AXI_GP0_ARBURST),
+            .M_ARLOCK  (M_AXI_GP0_ARLOCK),
+            .M_ARCACHE (M_AXI_GP0_ARCACHE),
+            .M_ARPROT  (M_AXI_GP0_ARPROT),
+            .M_ARVALID (M_AXI_GP0_ARVALID),
+            .M_ARREADY (M_AXI_GP0_ARREADY),
+            // Read Data Channel Signals.
+            .M_RID    (M_AXI_GP0_RID_FULL),
+            .M_RDATA  (M_AXI_GP0_RDATA),
+            .M_RRESP  (M_AXI_GP0_RRESP),
+            .M_RLAST  (M_AXI_GP0_RLAST),
+            .M_RVALID (M_AXI_GP0_RVALID),
+            .M_RREADY (M_AXI_GP0_RREADY),
+            // Side band signals 
+            .M_AWQOS  (M_AXI_GP0_AWQOS),
+            .M_ARQOS  (M_AXI_GP0_ARQOS)
+            ); 
+ 
+ /* AXI Master GP1 */
+  processing_system7_vip_v1_0_16_axi_master #(C_USE_M_AXI_GP1, // enable
+               axi_mgp1_name,// name
+               axi_mgp_data_width, /// Data Width
+               addr_width, /// Address width
+               axi_mgp_id_width,  //// ID Width
+               axi_mgp_outstanding,  //// Outstanding transactions
+               axi_mst_excl_support, // EXCL Access Support
+               axi_mgp_wr_id, //WR_ID
+               axi_mgp_rd_id) //RD_ID
+  M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
+            .M_ACLK   (M_AXI_GP1_ACLK),
+            // Write Address Channel
+            .M_AWID    (M_AXI_GP1_AWID_FULL),
+            .M_AWADDR  (M_AXI_GP1_AWADDR),
+            .M_AWLEN   (M_AXI_GP1_AWLEN),
+            .M_AWSIZE  (M_AXI_GP1_AWSIZE),
+            .M_AWBURST (M_AXI_GP1_AWBURST),
+            .M_AWLOCK  (M_AXI_GP1_AWLOCK),
+            .M_AWCACHE (M_AXI_GP1_AWCACHE),
+            .M_AWPROT  (M_AXI_GP1_AWPROT),
+            .M_AWVALID (M_AXI_GP1_AWVALID),
+            .M_AWREADY (M_AXI_GP1_AWREADY),
+            // Write Data Channel Signals.
+            .M_WID    (M_AXI_GP1_WID_FULL),
+            .M_WDATA  (M_AXI_GP1_WDATA),
+            .M_WSTRB  (M_AXI_GP1_WSTRB), 
+            .M_WLAST  (M_AXI_GP1_WLAST), 
+            .M_WVALID (M_AXI_GP1_WVALID),
+            .M_WREADY (M_AXI_GP1_WREADY),
+            // Write Response Channel Signals.
+            .M_BID    (M_AXI_GP1_BID_FULL),
+            .M_BRESP  (M_AXI_GP1_BRESP),
+            .M_BVALID (M_AXI_GP1_BVALID),
+            .M_BREADY (M_AXI_GP1_BREADY),
+            // Read Address Channel Signals.
+            .M_ARID    (M_AXI_GP1_ARID_FULL),
+            .M_ARADDR  (M_AXI_GP1_ARADDR),
+            .M_ARLEN   (M_AXI_GP1_ARLEN),
+            .M_ARSIZE  (M_AXI_GP1_ARSIZE),
+            .M_ARBURST (M_AXI_GP1_ARBURST),
+            .M_ARLOCK  (M_AXI_GP1_ARLOCK),
+            .M_ARCACHE (M_AXI_GP1_ARCACHE),
+            .M_ARPROT  (M_AXI_GP1_ARPROT),
+            .M_ARVALID (M_AXI_GP1_ARVALID),
+            .M_ARREADY (M_AXI_GP1_ARREADY),
+            // Read Data Channel Signals.
+            .M_RID    (M_AXI_GP1_RID_FULL),
+            .M_RDATA  (M_AXI_GP1_RDATA),
+            .M_RRESP  (M_AXI_GP1_RRESP),
+            .M_RLAST  (M_AXI_GP1_RLAST),
+            .M_RVALID (M_AXI_GP1_RVALID),
+            .M_RREADY (M_AXI_GP1_RREADY),
+            // Side band signals 
+            .M_AWQOS  (M_AXI_GP1_AWQOS),
+            .M_ARQOS  (M_AXI_GP1_ARQOS)
+           );
+
+/* AXI Slave GP0 */
+  processing_system7_vip_v1_0_16_axi_slave #(C_USE_S_AXI_GP0, /// enable
+              axi_sgp0_name, //name
+              axi_sgp_data_width, /// data width
+              addr_width, /// address width
+              axi_sgp_id_width,  /// ID width
+              C_S_AXI_GP0_BASEADDR,//// base address
+              C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr) 
+              axi_sgp_outstanding, // outstanding transactions
+              axi_slv_excl_support, // exclusive access not supported
+              axi_sgp_wr_outstanding,
+              axi_sgp_rd_outstanding)
+  S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
+            .S_ACLK   (S_AXI_GP0_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_GP0_AWID),
+            .S_AWADDR  (S_AXI_GP0_AWADDR),
+            .S_AWLEN   (S_AXI_GP0_AWLEN),
+            .S_AWSIZE  (S_AXI_GP0_AWSIZE),
+            .S_AWBURST (S_AXI_GP0_AWBURST),
+            .S_AWLOCK  (S_AXI_GP0_AWLOCK),
+            .S_AWCACHE (S_AXI_GP0_AWCACHE),
+            .S_AWPROT  (S_AXI_GP0_AWPROT),
+            .S_AWVALID (S_AXI_GP0_AWVALID),
+            .S_AWREADY (S_AXI_GP0_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_GP0_WID),
+            .S_WDATA  (S_AXI_GP0_WDATA),
+            .S_WSTRB  (S_AXI_GP0_WSTRB), 
+            .S_WLAST  (S_AXI_GP0_WLAST), 
+            .S_WVALID (S_AXI_GP0_WVALID),
+            .S_WREADY (S_AXI_GP0_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_GP0_BID),
+            .S_BRESP  (S_AXI_GP0_BRESP),
+            .S_BVALID (S_AXI_GP0_BVALID),
+            .S_BREADY (S_AXI_GP0_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_GP0_ARID),
+            .S_ARADDR  (S_AXI_GP0_ARADDR),
+            .S_ARLEN   (S_AXI_GP0_ARLEN),
+            .S_ARSIZE  (S_AXI_GP0_ARSIZE),
+            .S_ARBURST (S_AXI_GP0_ARBURST),
+            .S_ARLOCK  (S_AXI_GP0_ARLOCK),
+            .S_ARCACHE (S_AXI_GP0_ARCACHE),
+            .S_ARPROT  (S_AXI_GP0_ARPROT),
+            .S_ARVALID (S_AXI_GP0_ARVALID),
+            .S_ARREADY (S_AXI_GP0_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_GP0_RID),
+            .S_RDATA  (S_AXI_GP0_RDATA),
+            .S_RRESP  (S_AXI_GP0_RRESP),
+            .S_RLAST  (S_AXI_GP0_RLAST),
+            .S_RVALID (S_AXI_GP0_RVALID),
+            .S_RREADY (S_AXI_GP0_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_GP0_AWQOS),
+            .S_ARQOS  (S_AXI_GP0_ARQOS),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
+            .WR_DATA  (net_wr_data_gp0), 
+            .WR_DATA_STRB  (net_wr_strb_gp0), 
+            .WR_ADDR  (net_wr_addr_gp0), 
+            .WR_BYTES  (net_wr_bytes_gp0), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_gp0), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_gp0), 
+            .WR_QOS (net_wr_qos_gp0),
+            .RD_REQ_DDR (net_rd_req_ddr_gp0),
+            .RD_REQ_OCM (net_rd_req_ocm_gp0),
+            .RD_REQ_REG (net_rd_req_reg_gp0),
+            .RD_ADDR (net_rd_addr_gp0),
+            .RD_DATA_DDR (net_rd_data_ddr_gp0),
+            .RD_DATA_OCM (net_rd_data_ocm_gp0),
+            .RD_DATA_REG (net_rd_data_reg_gp0),
+            .RD_BYTES (net_rd_bytes_gp0),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
+            .RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
+            .RD_QOS (net_rd_qos_gp0)
+
+);
+
+/* AXI Slave GP1 */
+  processing_system7_vip_v1_0_16_axi_slave #(C_USE_S_AXI_GP1, /// enable
+              axi_sgp1_name, //name
+              axi_sgp_data_width, /// data width
+              addr_width, /// address width
+              axi_sgp_id_width,  /// ID width
+              C_S_AXI_GP1_BASEADDR,//// base address
+              C_S_AXI_GP1_HIGHADDR,/// HIGh_addr 
+              axi_sgp_outstanding, // outstanding transactions
+              axi_slv_excl_support, // exclusive access
+              axi_sgp_wr_outstanding,
+              axi_sgp_rd_outstanding)
+  S_AXI_GP1(.S_RESETN  (net_axi_gp1_rstn),
+            .S_ACLK    (S_AXI_GP1_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_GP1_AWID),
+            .S_AWADDR  (S_AXI_GP1_AWADDR),
+            .S_AWLEN   (S_AXI_GP1_AWLEN),
+            .S_AWSIZE  (S_AXI_GP1_AWSIZE),
+            .S_AWBURST (S_AXI_GP1_AWBURST),
+            .S_AWLOCK  (S_AXI_GP1_AWLOCK),
+            .S_AWCACHE (S_AXI_GP1_AWCACHE),
+            .S_AWPROT  (S_AXI_GP1_AWPROT),
+            .S_AWVALID (S_AXI_GP1_AWVALID),
+            .S_AWREADY (S_AXI_GP1_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_GP1_WID),
+            .S_WDATA  (S_AXI_GP1_WDATA),
+            .S_WSTRB  (S_AXI_GP1_WSTRB), 
+            .S_WLAST  (S_AXI_GP1_WLAST), 
+            .S_WVALID (S_AXI_GP1_WVALID),
+            .S_WREADY (S_AXI_GP1_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_GP1_BID),
+            .S_BRESP  (S_AXI_GP1_BRESP),
+            .S_BVALID (S_AXI_GP1_BVALID),
+            .S_BREADY (S_AXI_GP1_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_GP1_ARID),
+            .S_ARADDR  (S_AXI_GP1_ARADDR),
+            .S_ARLEN   (S_AXI_GP1_ARLEN),
+            .S_ARSIZE  (S_AXI_GP1_ARSIZE),
+            .S_ARBURST (S_AXI_GP1_ARBURST),
+            .S_ARLOCK  (S_AXI_GP1_ARLOCK),
+            .S_ARCACHE (S_AXI_GP1_ARCACHE),
+            .S_ARPROT  (S_AXI_GP1_ARPROT),
+            .S_ARVALID (S_AXI_GP1_ARVALID),
+            .S_ARREADY (S_AXI_GP1_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_GP1_RID),
+            .S_RDATA  (S_AXI_GP1_RDATA),
+            .S_RRESP  (S_AXI_GP1_RRESP),
+            .S_RLAST  (S_AXI_GP1_RLAST),
+            .S_RVALID (S_AXI_GP1_RVALID),
+            .S_RREADY (S_AXI_GP1_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_GP1_AWQOS),
+            .S_ARQOS  (S_AXI_GP1_ARQOS),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
+            .WR_DATA  (net_wr_data_gp1), 
+            .WR_DATA_STRB  (net_wr_strb_gp1), 
+            .WR_ADDR  (net_wr_addr_gp1), 
+            .WR_BYTES  (net_wr_bytes_gp1), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_gp1), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_gp1), 
+            .WR_QOS (net_wr_qos_gp1),
+            .RD_REQ_OCM (net_rd_req_ocm_gp1),
+            .RD_REQ_DDR (net_rd_req_ddr_gp1),
+            .RD_REQ_REG (net_rd_req_reg_gp1),
+            .RD_ADDR (net_rd_addr_gp1),
+            .RD_DATA_DDR (net_rd_data_ddr_gp1),
+            .RD_DATA_OCM (net_rd_data_ocm_gp1),
+            .RD_DATA_REG (net_rd_data_reg_gp1),
+            .RD_BYTES (net_rd_bytes_gp1),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
+            .RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
+            .RD_QOS (net_rd_qos_gp1)
+
+);

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_axi_hp.v

@@ -0,0 +1,350 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_16_axi_hp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for AXI HP ports
+ *
+ *****************************************************************************/
+
+/* AXI Slave HP0 */  
+ processing_system7_vip_v1_0_16_afi_slave #(  C_USE_S_AXI_HP0, // enable
+               axi_hp0_name, // name
+               C_S_AXI_HP0_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP0_BASEADDR, // slave base address
+               C_S_AXI_HP0_HIGHADDR, // slave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+  S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
+            .S_ACLK   (S_AXI_HP0_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP0_AWID),
+            .S_AWADDR  (S_AXI_HP0_AWADDR),
+            .S_AWLEN   (S_AXI_HP0_AWLEN),
+            .S_AWSIZE  (S_AXI_HP0_AWSIZE),
+            .S_AWBURST (S_AXI_HP0_AWBURST),
+            .S_AWLOCK  (S_AXI_HP0_AWLOCK),
+            .S_AWCACHE (S_AXI_HP0_AWCACHE),
+            .S_AWPROT  (S_AXI_HP0_AWPROT),
+            .S_AWVALID (S_AXI_HP0_AWVALID),
+            .S_AWREADY (S_AXI_HP0_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP0_WID),
+            .S_WDATA  (S_AXI_HP0_WDATA),
+            .S_WSTRB  (S_AXI_HP0_WSTRB), 
+            .S_WLAST  (S_AXI_HP0_WLAST), 
+            .S_WVALID (S_AXI_HP0_WVALID),
+            .S_WREADY (S_AXI_HP0_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP0_BID),
+            .S_BRESP  (S_AXI_HP0_BRESP),
+            .S_BVALID (S_AXI_HP0_BVALID),
+            .S_BREADY (S_AXI_HP0_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP0_ARID),
+            .S_ARADDR  (S_AXI_HP0_ARADDR),
+            .S_ARLEN   (S_AXI_HP0_ARLEN),
+            .S_ARSIZE  (S_AXI_HP0_ARSIZE),
+            .S_ARBURST (S_AXI_HP0_ARBURST),
+            .S_ARLOCK  (S_AXI_HP0_ARLOCK),
+            .S_ARCACHE (S_AXI_HP0_ARCACHE),
+            .S_ARPROT  (S_AXI_HP0_ARPROT),
+            .S_ARVALID (S_AXI_HP0_ARVALID),
+            .S_ARREADY (S_AXI_HP0_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP0_RID),
+            .S_RDATA  (S_AXI_HP0_RDATA),
+            .S_RRESP  (S_AXI_HP0_RRESP),
+            .S_RLAST  (S_AXI_HP0_RLAST),
+            .S_RVALID (S_AXI_HP0_RVALID),
+            .S_RREADY (S_AXI_HP0_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP0_AWQOS), 
+            .S_ARQOS  (S_AXI_HP0_ARQOS), 
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP0_RCOUNT),
+            .S_WCOUNT (S_AXI_HP0_WCOUNT),
+            .S_RACOUNT (S_AXI_HP0_RACOUNT),
+            .S_WACOUNT (S_AXI_HP0_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
+            .WR_DATA  (net_wr_data_hp0), 
+            .WR_DATA_STRB  (net_wr_strb_hp0), 
+            .WR_ADDR  (net_wr_addr_hp0), 
+            .WR_BYTES (net_wr_bytes_hp0), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp0), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp0), 
+            .WR_QOS (net_wr_qos_hp0),
+            .RD_REQ_DDR (net_rd_req_ddr_hp0),
+            .RD_REQ_OCM (net_rd_req_ocm_hp0),
+            .RD_ADDR (net_rd_addr_hp0),
+            .RD_DATA_DDR (net_rd_data_ddr_hp0),
+            .RD_DATA_OCM (net_rd_data_ocm_hp0),
+            .RD_BYTES (net_rd_bytes_hp0),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
+            .RD_QOS (net_rd_qos_hp0)
+ );
+
+/* AXI Slave HP1 */  
+ processing_system7_vip_v1_0_16_afi_slave #( C_USE_S_AXI_HP1, // enable
+               axi_hp1_name, // name
+               C_S_AXI_HP1_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP1_BASEADDR, // slave base address
+               C_S_AXI_HP1_HIGHADDR, // Slave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
+            .S_ACLK   (S_AXI_HP1_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP1_AWID),
+            .S_AWADDR  (S_AXI_HP1_AWADDR),
+            .S_AWLEN   (S_AXI_HP1_AWLEN),
+            .S_AWSIZE  (S_AXI_HP1_AWSIZE),
+            .S_AWBURST (S_AXI_HP1_AWBURST),
+            .S_AWLOCK  (S_AXI_HP1_AWLOCK),
+            .S_AWCACHE (S_AXI_HP1_AWCACHE),
+            .S_AWPROT  (S_AXI_HP1_AWPROT),
+            .S_AWVALID (S_AXI_HP1_AWVALID),
+            .S_AWREADY (S_AXI_HP1_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP1_WID),
+            .S_WDATA  (S_AXI_HP1_WDATA),
+            .S_WSTRB  (S_AXI_HP1_WSTRB), 
+            .S_WLAST  (S_AXI_HP1_WLAST), 
+            .S_WVALID (S_AXI_HP1_WVALID),
+            .S_WREADY (S_AXI_HP1_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP1_BID),
+            .S_BRESP  (S_AXI_HP1_BRESP),
+            .S_BVALID (S_AXI_HP1_BVALID),
+            .S_BREADY (S_AXI_HP1_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP1_ARID),
+            .S_ARADDR  (S_AXI_HP1_ARADDR),
+            .S_ARLEN   (S_AXI_HP1_ARLEN),
+            .S_ARSIZE  (S_AXI_HP1_ARSIZE),
+            .S_ARBURST (S_AXI_HP1_ARBURST),
+            .S_ARLOCK  (S_AXI_HP1_ARLOCK),
+            .S_ARCACHE (S_AXI_HP1_ARCACHE),
+            .S_ARPROT  (S_AXI_HP1_ARPROT),
+            .S_ARVALID (S_AXI_HP1_ARVALID),
+            .S_ARREADY (S_AXI_HP1_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP1_RID),
+            .S_RDATA  (S_AXI_HP1_RDATA),
+            .S_RRESP  (S_AXI_HP1_RRESP),
+            .S_RLAST  (S_AXI_HP1_RLAST),
+            .S_RVALID (S_AXI_HP1_RVALID),
+            .S_RREADY (S_AXI_HP1_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP1_AWQOS), 
+            .S_ARQOS  (S_AXI_HP1_ARQOS), 
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP1_RCOUNT),
+            .S_WCOUNT (S_AXI_HP1_WCOUNT),
+            .S_RACOUNT (S_AXI_HP1_RACOUNT),
+            .S_WACOUNT (S_AXI_HP1_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
+            .WR_DATA  (net_wr_data_hp1), 
+			.WR_DATA_STRB  (net_wr_strb_hp1),
+            .WR_ADDR  (net_wr_addr_hp1), 
+            .WR_BYTES (net_wr_bytes_hp1), 
+            .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1), 
+            .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1), 
+            .WR_QOS (net_wr_qos_hp1),
+            .RD_REQ_DDR (net_rd_req_ddr_hp1),
+            .RD_REQ_OCM (net_rd_req_ocm_hp1),
+            .RD_ADDR (net_rd_addr_hp1),
+            .RD_DATA_DDR (net_rd_data_ddr_hp1),
+            .RD_DATA_OCM (net_rd_data_ocm_hp1),
+            .RD_BYTES (net_rd_bytes_hp1),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
+            .RD_QOS (net_rd_qos_hp1)
+
+  );
+
+/* AXI Slave HP2 */  
+ processing_system7_vip_v1_0_16_afi_slave #( C_USE_S_AXI_HP2, // enable
+               axi_hp2_name, // name
+               C_S_AXI_HP2_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP2_BASEADDR, // slave base address
+               C_S_AXI_HP2_HIGHADDR, // SLave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
+            .S_ACLK    (S_AXI_HP2_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP2_AWID),
+            .S_AWADDR  (S_AXI_HP2_AWADDR),
+            .S_AWLEN   (S_AXI_HP2_AWLEN),
+            .S_AWSIZE  (S_AXI_HP2_AWSIZE),
+            .S_AWBURST (S_AXI_HP2_AWBURST),
+            .S_AWLOCK  (S_AXI_HP2_AWLOCK),
+            .S_AWCACHE (S_AXI_HP2_AWCACHE),
+            .S_AWPROT  (S_AXI_HP2_AWPROT),
+            .S_AWVALID (S_AXI_HP2_AWVALID),
+            .S_AWREADY (S_AXI_HP2_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP2_WID),
+            .S_WDATA  (S_AXI_HP2_WDATA),
+            .S_WSTRB  (S_AXI_HP2_WSTRB), 
+            .S_WLAST  (S_AXI_HP2_WLAST), 
+            .S_WVALID (S_AXI_HP2_WVALID),
+            .S_WREADY (S_AXI_HP2_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP2_BID),
+            .S_BRESP  (S_AXI_HP2_BRESP),
+            .S_BVALID (S_AXI_HP2_BVALID),
+            .S_BREADY (S_AXI_HP2_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP2_ARID),
+            .S_ARADDR  (S_AXI_HP2_ARADDR),
+            .S_ARLEN   (S_AXI_HP2_ARLEN),
+            .S_ARSIZE  (S_AXI_HP2_ARSIZE),
+            .S_ARBURST (S_AXI_HP2_ARBURST),
+            .S_ARLOCK  (S_AXI_HP2_ARLOCK),
+            .S_ARCACHE (S_AXI_HP2_ARCACHE),
+            .S_ARPROT  (S_AXI_HP2_ARPROT),
+            .S_ARVALID (S_AXI_HP2_ARVALID),
+            .S_ARREADY (S_AXI_HP2_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP2_RID),
+            .S_RDATA  (S_AXI_HP2_RDATA),
+            .S_RRESP  (S_AXI_HP2_RRESP),
+            .S_RLAST  (S_AXI_HP2_RLAST),
+            .S_RVALID (S_AXI_HP2_RVALID),
+            .S_RREADY (S_AXI_HP2_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP2_AWQOS), 
+            .S_ARQOS  (S_AXI_HP2_ARQOS), 
+             // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP2_RCOUNT),
+            .S_WCOUNT (S_AXI_HP2_WCOUNT),
+            .S_RACOUNT (S_AXI_HP2_RACOUNT),
+            .S_WACOUNT (S_AXI_HP2_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
+            .WR_DATA  (net_wr_data_hp2), 
+			.WR_DATA_STRB  (net_wr_strb_hp2),
+            .WR_ADDR  (net_wr_addr_hp2), 
+            .WR_BYTES (net_wr_bytes_hp2), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp2), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp2), 
+            .WR_QOS (net_wr_qos_hp2),
+            .RD_REQ_DDR (net_rd_req_ddr_hp2),
+            .RD_REQ_OCM (net_rd_req_ocm_hp2),
+            .RD_ADDR (net_rd_addr_hp2),
+            .RD_DATA_DDR (net_rd_data_ddr_hp2),
+            .RD_DATA_OCM (net_rd_data_ocm_hp2),
+            .RD_BYTES (net_rd_bytes_hp2),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
+            .RD_QOS (net_rd_qos_hp2)
+
+ );
+
+/* AXI Slave HP3 */  
+ processing_system7_vip_v1_0_16_afi_slave #( C_USE_S_AXI_HP3, // enable
+               axi_hp3_name, // name
+               C_S_AXI_HP3_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP3_BASEADDR, // slave base address
+               C_S_AXI_HP3_HIGHADDR, // SLave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
+            .S_ACLK   (S_AXI_HP3_ACLK),
+            // Write ADDRESS CHANNEL
+            .S_AWID    (S_AXI_HP3_AWID),
+            .S_AWADDR  (S_AXI_HP3_AWADDR),
+            .S_AWLEN   (S_AXI_HP3_AWLEN),
+            .S_AWSIZE  (S_AXI_HP3_AWSIZE),
+            .S_AWBURST (S_AXI_HP3_AWBURST),
+            .S_AWLOCK  (S_AXI_HP3_AWLOCK),
+            .S_AWCACHE (S_AXI_HP3_AWCACHE),
+            .S_AWPROT  (S_AXI_HP3_AWPROT),
+            .S_AWVALID (S_AXI_HP3_AWVALID),
+            .S_AWREADY (S_AXI_HP3_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP3_WID),
+            .S_WDATA  (S_AXI_HP3_WDATA),
+            .S_WSTRB  (S_AXI_HP3_WSTRB), 
+            .S_WLAST  (S_AXI_HP3_WLAST), 
+            .S_WVALID (S_AXI_HP3_WVALID),
+            .S_WREADY (S_AXI_HP3_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP3_BID),
+            .S_BRESP  (S_AXI_HP3_BRESP),
+            .S_BVALID (S_AXI_HP3_BVALID),
+            .S_BREADY (S_AXI_HP3_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP3_ARID),
+            .S_ARADDR  (S_AXI_HP3_ARADDR),
+            .S_ARLEN   (S_AXI_HP3_ARLEN),
+            .S_ARSIZE  (S_AXI_HP3_ARSIZE),
+            .S_ARBURST (S_AXI_HP3_ARBURST),
+            .S_ARLOCK  (S_AXI_HP3_ARLOCK),
+            .S_ARCACHE (S_AXI_HP3_ARCACHE),
+            .S_ARPROT  (S_AXI_HP3_ARPROT),
+            .S_ARVALID (S_AXI_HP3_ARVALID),
+            .S_ARREADY (S_AXI_HP3_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP3_RID),
+            .S_RDATA  (S_AXI_HP3_RDATA),
+            .S_RRESP  (S_AXI_HP3_RRESP),
+            .S_RLAST  (S_AXI_HP3_RLAST),
+            .S_RVALID (S_AXI_HP3_RVALID),
+            .S_RREADY (S_AXI_HP3_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP3_AWQOS), 
+            .S_ARQOS  (S_AXI_HP3_ARQOS),
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP3_RCOUNT),
+            .S_WCOUNT (S_AXI_HP3_WCOUNT),
+            .S_RACOUNT (S_AXI_HP3_RACOUNT),
+            .S_WACOUNT (S_AXI_HP3_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
+            .WR_DATA  (net_wr_data_hp3), 
+			.WR_DATA_STRB  (net_wr_strb_hp3),
+            .WR_ADDR  (net_wr_addr_hp3), 
+            .WR_BYTES (net_wr_bytes_hp3), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp3), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp3), 
+            .WR_QOS (net_wr_qos_hp3),
+            .RD_REQ_DDR (net_rd_req_ddr_hp3),
+            .RD_REQ_OCM (net_rd_req_ocm_hp3),
+            .RD_ADDR (net_rd_addr_hp3),
+            .RD_DATA_DDR (net_rd_data_ddr_hp3),
+            .RD_DATA_OCM (net_rd_data_ocm_hp3),
+            .RD_BYTES (net_rd_bytes_hp3),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
+            .RD_QOS (net_rd_qos_hp3)
+ );

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_local_params.v

@@ -0,0 +1,244 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_16_local_params.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Parameters used in Zynq VIP
+ *
+ *****************************************************************************/
+
+
+/* local */ 
+parameter m_axi_gp0_baseaddr = 32'h4000_0000;
+parameter m_axi_gp1_baseaddr = 32'h8000_0000;
+parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF;
+parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF;
+
+parameter addr_width = 32;   // maximum address width
+parameter data_width = 32;   // maximum data width.
+parameter max_chars  = 128;  // max characters for file name
+parameter mem_width  = data_width/8; /// memory width in bytes
+parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
+parameter int_width  = 32; //integre width
+
+/* for internal read/write APIs used for data transfers */
+parameter max_burst_len   = 16;  /// maximum brst length on axi 
+parameter max_data_width  = 64; // maximum data width for internal AXI bursts 
+parameter max_burst_bits  = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts 
+parameter max_burst_bytes = (max_burst_bits)/8;                // maximum data bytes in each transfer 
+parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts 
+
+parameter max_registers   = 32;
+parameter max_regs_width  = clogb2(max_registers);
+
+parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11; 
+
+/* Interrupt bits supported */
+parameter irq_width = 16;
+
+/* GP Master0 & Master1 address decode */
+parameter GP_M0 = 2'b01;
+parameter GP_M1 = 2'b10;
+
+parameter ALL_RANDOM= 2'b00;
+parameter ALL_ZEROS = 2'b01;
+parameter ALL_ONES  = 2'b10;
+
+parameter ddr_start_addr = 32'h0008_0000;
+parameter ddr_end_addr   = 32'h7FFF_FFFF;
+
+parameter ocm_start_addr = 32'h0000_0000;
+parameter ocm_end_addr   = 32'h0003_FFFF;
+parameter high_ocm_start_addr = 32'hFFFC_0000;
+parameter high_ocm_end_addr   = 32'hFFFF_FFFF;
+parameter ocm_low_addr   = 32'hFFFF_0000;
+
+parameter reg_start_addr = 32'hE000_0000;
+parameter reg_end_addr   = 32'hF8F0_2F80;
+
+
+/* for Master port APIs and AXI protocol related signal widths*/
+parameter axi_burst_len  = 16;
+parameter axi_len_width  = clogb2(axi_burst_len);
+parameter axi_size_width = 3;
+parameter axi_brst_type_width = 2;
+parameter axi_lock_width = 2;
+parameter axi_cache_width = 4;
+parameter axi_prot_width = 3;
+parameter axi_rsp_width = 2;
+parameter axi_mgp_data_width = 32;
+parameter axi_mgp_id_width   = 12;
+parameter axi_mgp_outstanding = 8;
+parameter axi_mgp_wr_id = 12'hC00;
+parameter axi_mgp_rd_id = 12'hC0C;
+parameter axi_mgp0_name  = "M_AXI_GP0";
+parameter axi_mgp1_name  = "M_AXI_GP1";
+parameter axi_qos_width  = 4;
+parameter max_transfer_bytes = 256; // For Master APIs.
+parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
+
+
+/* for GP slave ports*/
+parameter axi_sgp_data_width = 32;
+parameter axi_sgp_id_width   = 6;
+parameter axi_sgp_rd_outstanding = 8;
+parameter axi_sgp_wr_outstanding = 8;
+parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
+parameter axi_sgp0_name  = "S_AXI_GP0";
+parameter axi_sgp1_name  = "S_AXI_GP1";
+
+/* for ACP slave ports*/
+parameter axi_acp_data_width = 64;
+parameter axi_acp_id_width   = 3;
+parameter axi_acp_rd_outstanding = 7;
+parameter axi_acp_wr_outstanding = 3;
+parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
+parameter axi_acp_name  = "S_AXI_ACP";
+
+/* for HP slave ports*/
+parameter axi_hp_id_width   = 6;
+parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
+parameter axi_hp0_name  = "S_AXI_HP0";
+parameter axi_hp1_name  = "S_AXI_HP1";
+parameter axi_hp2_name  = "S_AXI_HP2";
+parameter axi_hp3_name  = "S_AXI_HP3";
+
+
+parameter axi_slv_excl_support = 0; // For Slave  ports EXCL access is not supported
+parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
+
+/* AXI transfer types */
+parameter AXI_FIXED = 2'b00;
+parameter AXI_INCR  = 2'b01;
+parameter AXI_WRAP  = 2'b10;
+
+/* Exclusive Access */
+parameter AXI_NRML  = 2'b00;
+parameter AXI_EXCL  = 2'b01;
+parameter AXI_LOCK  = 2'b10;
+
+/* AXI Response types */
+parameter AXI_OK = 2'b00;
+parameter AXI_EXCL_OK  = 2'b01;
+parameter AXI_SLV_ERR  = 2'b10;
+parameter AXI_DEC_ERR  = 2'b11;
+
+function automatic integer clogb2;
+  input [31:0] value;
+  begin
+      value = value - 1;
+      for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
+          value = value >> 1;
+      end
+  end
+endfunction
+
+/* needed only for AFI modules  and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
+  /* WR FIFO data */
+  // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
+  // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
+  // parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1);
+  // parameter wr_bytes_lsb = 0;
+  // parameter wr_bytes_msb = max_burst_bytes_width;
+  // parameter wr_addr_lsb  = wr_bytes_msb + 1;
+  // parameter wr_addr_msb  = wr_addr_lsb + addr_width-1;
+  // parameter wr_data_lsb  = wr_addr_msb + 1;
+  // parameter wr_data_msb  = wr_data_lsb + max_burst_bits-1;
+  // parameter wr_data_msb  = wr_data_lsb + (data_bus_width*axi_burst_len)-1;
+  // parameter wr_qos_lsb   = wr_data_msb + 1;
+  // `parameter wr_qos_msb   = wr_qos_lsb + axi_qos_width-1;
+ 
+  /* WR AFI FIFO data */ 
+    /* ID -  1071:1066
+     Resp - 1065:1064
+     data - 1063:40   
+     address - 39:8
+     valid_bytes - 7:0
+    */
+  // parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
+  // parameter wr_afi_bytes_lsb = 0;
+  // parameter wr_afi_bytes_msb = max_burst_bytes_width;
+  // parameter wr_afi_addr_lsb  = wr_afi_bytes_msb + 1;
+  // parameter wr_afi_addr_msb  = wr_afi_addr_lsb + addr_width-1;
+  // parameter wr_afi_data_lsb  = wr_afi_addr_msb + 1;
+  // parameter wr_afi_rsp_msb   = wr_afi_rsp_lsb + axi_rsp_width-1; 
+  // parameter wr_afi_id_lsb    = wr_afi_rsp_msb + 1; 
+  // parameter wr_afi_id_msb    = wr_afi_id_lsb + axi_hp_id_width-1; 
+  // parameter wr_afi_ln_lsb    = wr_afi_id_msb + 1;
+  // parameter wr_afi_ln_msb    = wr_afi_ln_lsb + axi_len_width-1;
+  // parameter wr_afi_qos_lsb   = wr_afi_ln_msb + 1;
+  // parameter wr_afi_qos_msb   = wr_afi_qos_lsb + axi_qos_width-1;
+
+
+  parameter afi_fifo_size    = 1024; /// AFI FIFO is stored as 1024-bytes 
+  parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
+  parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
+
+/* for interconnect fifo models */
+  parameter intr_max_outstanding = 8;
+  parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
+  parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width +  axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
+  parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
+
+  //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
+  parameter rd_afi_bytes_lsb = 0;
+  parameter rd_afi_bytes_msb = max_burst_bytes_width;
+  parameter rd_afi_rsp_lsb   = rd_afi_bytes_msb + 1; 
+  parameter rd_afi_rsp_msb   = rd_afi_rsp_lsb + axi_rsp_width-1; 
+  parameter rd_afi_id_lsb    = rd_afi_rsp_msb + 1; 
+  parameter rd_afi_id_msb    = rd_afi_id_lsb + axi_hp_id_width-1; 
+  parameter rd_afi_ln_lsb    = rd_afi_id_msb + 1;
+  parameter rd_afi_ln_msb    = rd_afi_ln_lsb + axi_len_width-1;
+  parameter rd_afi_brst_lsb  = rd_afi_ln_msb + 1;
+  parameter rd_afi_brst_msb  = rd_afi_brst_lsb + axi_brst_type_width-1;
+  parameter rd_afi_siz_lsb   = rd_afi_brst_msb + 1;
+  parameter rd_afi_siz_msb   = rd_afi_siz_lsb + axi_size_width-1;
+  parameter rd_afi_addr_lsb  = rd_afi_siz_msb + 1;
+  parameter rd_afi_addr_msb  = rd_afi_addr_lsb + addr_width-1;
+  parameter rd_afi_data_lsb  = rd_afi_addr_msb + 1;
+  parameter rd_afi_data_msb  = rd_afi_data_lsb + max_burst_bits-1; 
+
+
+/* Latency types */
+ parameter BEST_CASE  = 0;
+ parameter AVG_CASE   = 1;
+ parameter WORST_CASE = 2;
+ parameter RANDOM_CASE  = 3;
+
+/* Latency Parameters ACP  */
+  parameter acp_wr_min   =  21;
+  parameter acp_wr_avg   =  16;
+  parameter acp_wr_max   =  27;
+  parameter acp_rd_min   =  34;
+  parameter acp_rd_avg   =  125;
+  parameter acp_rd_max   =  130; 
+
+/* Latency Parameters GP  */
+  parameter gp_wr_min   =  21;
+  parameter gp_wr_avg   =  16;
+  parameter gp_wr_max   =  46;
+  parameter gp_rd_min   =  38;
+  parameter gp_rd_avg   =  125;
+  parameter gp_rd_max   =  130; 
+
+/* Latency Parameters HP  */
+  parameter afi_wr_min  =  37;
+  parameter afi_wr_avg  =  41;
+  parameter afi_wr_max  =  42;
+  parameter afi_rd_min  =  41;
+  parameter afi_rd_avg  =  221;
+  parameter afi_rd_max  =  229; 
+
+/* ID VALID and INVALID */
+  parameter secure_access_enabled = 0;
+  parameter id_invalid = 0;
+  parameter id_valid = 1;
+
+/* Display */
+  parameter DISP_INFO = "*ZYNQ_VIP_INFO";
+  parameter DISP_WARN = "*ZYNQ_VIP_WARNING";
+  parameter DISP_ERR  = "*ZYNQ_VIP_ERROR";
+  parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO";
+
+  parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/aed8/hdl/processing_system7_vip_v1_0_16_unused_ports.v

@@ -0,0 +1,433 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_16_unused_ports.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Semantic checks for unused ports.
+ *
+ *****************************************************************************/
+
+/* CAN */
+assign CAN0_PHY_TX = 0;
+assign CAN1_PHY_TX = 0;
+always @(CAN0_PHY_RX or CAN1_PHY_RX)
+begin 
+ if(CAN0_PHY_RX | CAN1_PHY_RX)
+  $display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* ETHERNET */
+/* ------------------------------------------- */
+
+assign ENET0_GMII_TX_EN = 0;
+assign ENET0_GMII_TX_ER = 0;
+assign ENET0_MDIO_MDC = 0;
+assign ENET0_MDIO_O = 0; /// confirm
+assign ENET0_MDIO_T = 0;
+assign ENET0_PTP_DELAY_REQ_RX = 0;
+assign ENET0_PTP_DELAY_REQ_TX = 0;
+assign ENET0_PTP_PDELAY_REQ_RX = 0;
+assign ENET0_PTP_PDELAY_REQ_TX = 0;
+assign ENET0_PTP_PDELAY_RESP_RX = 0;
+assign ENET0_PTP_PDELAY_RESP_TX = 0;
+assign ENET0_PTP_SYNC_FRAME_RX = 0;
+assign ENET0_PTP_SYNC_FRAME_TX = 0;
+assign ENET0_SOF_RX = 0;
+assign ENET0_SOF_TX = 0;
+assign ENET0_GMII_TXD = 0;
+always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or 
+        ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
+        ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
+begin 
+ if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN | 
+        ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
+        ENET0_GMII_TX_CLK | ENET0_MDIO_I )
+  $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
+end
+
+assign ENET1_GMII_TX_EN = 0;
+assign ENET1_GMII_TX_ER = 0;
+assign ENET1_MDIO_MDC = 0;
+assign ENET1_MDIO_O = 0;/// confirm
+assign ENET1_MDIO_T = 0;
+assign ENET1_PTP_DELAY_REQ_RX = 0;
+assign ENET1_PTP_DELAY_REQ_TX = 0;
+assign ENET1_PTP_PDELAY_REQ_RX = 0;
+assign ENET1_PTP_PDELAY_REQ_TX = 0;
+assign ENET1_PTP_PDELAY_RESP_RX = 0;
+assign ENET1_PTP_PDELAY_RESP_TX = 0;
+assign ENET1_PTP_SYNC_FRAME_RX = 0;
+assign ENET1_PTP_SYNC_FRAME_TX = 0;
+assign ENET1_SOF_RX = 0;
+assign ENET1_SOF_TX = 0;
+assign ENET1_GMII_TXD = 0;
+always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or 
+        ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
+        ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
+begin 
+ if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN | 
+        ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
+        ENET1_GMII_TX_CLK | ENET1_MDIO_I )
+  $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* GPIO */
+/* ------------------------------------------- */
+
+assign GPIO_O = 0;
+assign GPIO_T = 0;
+always@(GPIO_I)
+begin
+// if(GPIO_I !== 0)
+// $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* I2C */
+/* ------------------------------------------- */
+
+assign I2C0_SDA_O = 0;
+assign I2C0_SDA_T = 0;
+assign I2C0_SCL_O = 0;
+assign I2C0_SCL_T = 0;
+assign I2C1_SDA_O = 0;
+assign I2C1_SDA_T = 0;
+assign I2C1_SCL_O = 0;
+assign I2C1_SCL_T = 0;
+always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
+begin
+ if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
+  $display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* JTAG  */
+/* ------------------------------------------- */
+
+assign PJTAG_TD_T = 0;
+assign PJTAG_TD_O = 0;
+always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
+begin
+ if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
+  $display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* SDIO  */
+/* ------------------------------------------- */
+
+assign SDIO0_CLK = 0;
+assign SDIO0_CMD_O = 0;
+assign SDIO0_CMD_T = 0;
+assign SDIO0_DATA_O = 0;
+assign SDIO0_DATA_T = 0;
+assign SDIO0_LED = 0;
+assign SDIO0_BUSPOW = 0;
+assign SDIO0_BUSVOLT = 0;
+always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
+begin
+ if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
+  $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
+end
+
+assign SDIO1_CLK = 0;
+assign SDIO1_CMD_O = 0;
+assign SDIO1_CMD_T = 0;
+assign SDIO1_DATA_O = 0;
+assign SDIO1_DATA_T = 0;
+assign SDIO1_LED = 0;
+assign SDIO1_BUSPOW = 0;
+assign SDIO1_BUSVOLT = 0;
+always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
+begin
+ if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
+  $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* SPI  */
+/* ------------------------------------------- */
+
+assign SPI0_SCLK_O = 0;
+assign SPI0_SCLK_T = 0;
+assign SPI0_MOSI_O = 0;
+assign SPI0_MOSI_T = 0;
+assign SPI0_MISO_O = 0;
+assign SPI0_MISO_T = 0;
+assign SPI0_SS_O = 0; /// confirm
+assign SPI0_SS1_O = 0;/// confirm
+assign SPI0_SS2_O = 0;/// confirm
+assign SPI0_SS_T = 0;
+always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
+begin
+ if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
+  $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
+end
+
+assign SPI1_SCLK_O = 0;
+assign SPI1_SCLK_T = 0;
+assign SPI1_MOSI_O = 0;
+assign SPI1_MOSI_T = 0;
+assign SPI1_MISO_O = 0;
+assign SPI1_MISO_T = 0;
+assign SPI1_SS_O = 0;
+assign SPI1_SS1_O = 0;
+assign SPI1_SS2_O = 0;
+assign SPI1_SS_T = 0;
+always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
+begin
+ if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
+  $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* UART  */
+/* ------------------------------------------- */
+/// confirm
+assign UART0_DTRN = 0;
+assign UART0_RTSN = 0;
+assign UART0_TX = 0;
+always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
+begin
+ if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
+  $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
+end
+
+assign UART1_DTRN = 0;
+assign UART1_RTSN = 0;
+assign UART1_TX = 0;
+always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
+begin
+ if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
+  $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* TTC  */
+/* ------------------------------------------- */
+
+assign TTC0_WAVE0_OUT = 0;
+assign TTC0_WAVE1_OUT = 0;
+assign TTC0_WAVE2_OUT = 0;
+always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
+begin
+ if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
+  $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
+end
+
+assign TTC1_WAVE0_OUT = 0;
+assign TTC1_WAVE1_OUT = 0;
+assign TTC1_WAVE2_OUT = 0;
+always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
+begin
+ if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
+  $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* WDT  */
+/* ------------------------------------------- */
+
+assign WDT_RST_OUT = 0;
+always@(WDT_CLK_IN)
+begin
+ if(WDT_CLK_IN)
+  $display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* TRACE  */
+/* ------------------------------------------- */
+
+assign TRACE_CTL = 0;
+assign TRACE_DATA = 0;
+always@(TRACE_CLK)
+begin
+ if(TRACE_CLK)
+  $display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* USB  */
+/* ------------------------------------------- */
+assign USB0_PORT_INDCTL = 0;
+assign USB0_VBUS_PWRSELECT = 0;
+always@(USB0_VBUS_PWRFAULT)
+begin
+ if(USB0_VBUS_PWRFAULT)
+  $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
+end
+
+assign USB1_PORT_INDCTL = 0;
+assign USB1_VBUS_PWRSELECT = 0;
+always@(USB1_VBUS_PWRFAULT)
+begin
+ if(USB1_VBUS_PWRFAULT)
+  $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
+end
+
+always@(SRAM_INTIN)
+begin
+ if(SRAM_INTIN)
+  $display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
+end 
+
+/* ------------------------------------------- */
+/* DMA  */
+/* ------------------------------------------- */
+
+assign DMA0_DATYPE = 0;
+assign DMA0_DAVALID = 0;
+assign DMA0_DRREADY = 0;
+assign DMA0_RSTN = 0;
+always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
+begin
+ if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+assign DMA1_DATYPE = 0;
+assign DMA1_DAVALID = 0;
+assign DMA1_DRREADY = 0;
+assign DMA1_RSTN = 0;
+always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
+begin
+ if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+assign DMA2_DATYPE = 0;
+assign DMA2_DAVALID = 0;
+assign DMA2_DRREADY = 0;
+assign DMA2_RSTN = 0;
+always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
+begin
+ if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+assign DMA3_DATYPE = 0;
+assign DMA3_DAVALID = 0;
+assign DMA3_DRREADY = 0;
+assign DMA3_RSTN = 0;
+always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
+begin
+ if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* FTM  */
+/* ------------------------------------------- */
+
+assign FTMT_F2P_TRIGACK = 0;
+assign FTMT_P2F_TRIG = 0;
+assign FTMT_P2F_DEBUG = 0;
+always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or 
+        FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
+begin
+ if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
+  $display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* EVENT  */
+/* ------------------------------------------- */
+
+assign EVENT_EVENTO = 0;
+assign EVENT_STANDBYWFE = 0;  
+assign EVENT_STANDBYWFI = 0;
+always@(EVENT_EVENTI)
+begin
+ if(EVENT_EVENTI)
+  $display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* MIO */
+/* ------------------------------------------- */
+
+always@(MIO)
+begin
+// if(MIO !== 0)
+// $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* FCLK_TRIG */
+/* ------------------------------------------- */
+
+always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
+begin
+ if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
+  $display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* MISC */
+/* ------------------------------------------- */
+
+always@(FPGA_IDLE_N)
+begin
+ if(FPGA_IDLE_N)
+  $display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
+end
+
+always@(DDR_ARB)
+begin
+//  if(DDR_ARB !== 0)
+//  $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
+end
+
+always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
+begin
+ if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ) 
+  $display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* DDR */
+/* ------------------------------------------- */
+
+assign DDR_WEB = 0;
+always@(DDR_Clk or DDR_CS_n)
+begin
+if(!DDR_CS_n)
+ $display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* IRQ_P2F */
+/* ------------------------------------------- */
+
+assign IRQ_P2F_DMAC_ABORT = 0;
+assign IRQ_P2F_DMAC0 = 0;
+assign IRQ_P2F_DMAC1 = 0;
+assign IRQ_P2F_DMAC2 = 0;
+assign IRQ_P2F_DMAC3 = 0;
+assign IRQ_P2F_DMAC4 = 0;
+assign IRQ_P2F_DMAC5 = 0;
+assign IRQ_P2F_DMAC6 = 0;
+assign IRQ_P2F_DMAC7 = 0;
+assign IRQ_P2F_SMC = 0;
+assign IRQ_P2F_QSPI = 0;
+assign IRQ_P2F_CTI = 0;
+assign IRQ_P2F_GPIO = 0;
+assign IRQ_P2F_USB0 = 0;
+assign IRQ_P2F_ENET0 = 0;
+assign IRQ_P2F_ENET_WAKE0 = 0;
+assign IRQ_P2F_SDIO0 = 0;
+assign IRQ_P2F_I2C0 = 0;
+assign IRQ_P2F_SPI0 = 0;
+assign IRQ_P2F_UART0 = 0;
+assign IRQ_P2F_CAN0 = 0;
+assign IRQ_P2F_USB1 = 0;
+assign IRQ_P2F_ENET1 = 0;
+assign IRQ_P2F_ENET_WAKE1 = 0;
+assign IRQ_P2F_SDIO1 = 0;
+assign IRQ_P2F_I2C1 = 0;
+assign IRQ_P2F_SPI1 = 0;
+assign IRQ_P2F_UART1 = 0;
+assign IRQ_P2F_CAN1 = 0;

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v

@@ -0,0 +1,31 @@
+//------------------------------------------------------------------------
+//--
+//--  Filename      : xlconstant.v
+//--
+//--  Date          : 06/05/12
+//--
+//--  Description   : VERILOG description of a constant block.  This
+//--                  block does not use a core.
+//--
+//------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------
+//--
+//--  Module        : xlconstant
+//--
+//--  Architecture  : behavior
+//--
+//--  Description   : Top level VERILOG description of constant block
+//--
+//------------------------------------------------------------------------
+`timescale 1ps/1ps
+module xlconstant_v1_1_7_xlconstant (dout);
+	parameter CONST_VAL = 1;
+	parameter CONST_WIDTH = 1;
+	output [CONST_WIDTH-1:0] dout;
+
+	assign dout = CONST_VAL;
+endmodule
+
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v

@@ -0,0 +1,670 @@
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// axis to vector
+//   A generic module to merge all axi signals into one signal called payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_infrastructure_v1_1_0_axi2vector #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_AXI_PROTOCOL                = 0,
+  parameter integer C_AXI_ID_WIDTH                = 4,
+  parameter integer C_AXI_ADDR_WIDTH              = 32,
+  parameter integer C_AXI_DATA_WIDTH              = 32,
+  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
+  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
+  parameter integer C_AXI_AWUSER_WIDTH            = 1,
+  parameter integer C_AXI_WUSER_WIDTH             = 1,
+  parameter integer C_AXI_BUSER_WIDTH             = 1,
+  parameter integer C_AXI_ARUSER_WIDTH            = 1,
+  parameter integer C_AXI_RUSER_WIDTH             = 1,
+  parameter integer C_AWPAYLOAD_WIDTH             = 61,
+  parameter integer C_WPAYLOAD_WIDTH              = 73,
+  parameter integer C_BPAYLOAD_WIDTH              = 6,
+  parameter integer C_ARPAYLOAD_WIDTH             = 61,
+  parameter integer C_RPAYLOAD_WIDTH              = 69
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave Interface Write Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
+  input  wire [3-1:0]                               s_axi_awsize,
+  input  wire [2-1:0]                               s_axi_awburst,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
+  input  wire [4-1:0]                               s_axi_awcache,
+  input  wire [3-1:0]                               s_axi_awprot,
+  input  wire [4-1:0]                               s_axi_awregion,
+  input  wire [4-1:0]                               s_axi_awqos,
+  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,
+
+  // Slave Interface Write Data Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,
+  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,
+  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,
+  input  wire                                       s_axi_wlast,
+  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,
+
+  // Slave Interface Write Response Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,
+  output wire [2-1:0]                               s_axi_bresp,
+  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,
+
+   // Slave Interface Read Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
+  input  wire [3-1:0]                               s_axi_arsize,
+  input  wire [2-1:0]                               s_axi_arburst,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
+  input  wire [4-1:0]                               s_axi_arcache,
+  input  wire [3-1:0]                               s_axi_arprot,
+  input  wire [4-1:0]                               s_axi_arregion,
+  input  wire [4-1:0]                               s_axi_arqos,
+  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,
+
+  // Slave Interface Read Data Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,
+  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,
+  output wire [2-1:0]                               s_axi_rresp,
+  output wire                                       s_axi_rlast,
+  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,
+
+  // payloads
+  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,
+  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,
+  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,
+  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,
+  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axi_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// AXI4, AXI4LITE, AXI3 packing
+assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
+assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
+
+assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
+assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
+
+assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
+
+assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
+assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
+
+assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
+assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
+
+generate
+  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
+    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;
+    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
+    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
+    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;
+    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;
+    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;
+    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;
+
+    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;
+    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
+      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;
+    end
+    else begin : gen_no_axi3_wid_packing
+    end
+
+    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
+
+    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;
+    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
+    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
+    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;
+    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;
+    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;
+    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;
+
+    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
+    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
+
+    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
+      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
+      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
+    end 
+    else begin : gen_no_region_signals
+    end
+    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
+      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
+      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;
+      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
+      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
+      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
+    end 
+    else begin : gen_no_user_signals
+      assign s_axi_buser = 'b0;
+      assign s_axi_ruser = 'b0;
+    end
+  end
+  else begin : gen_axi4lite_packing
+    assign s_axi_bid = 'b0;
+    assign s_axi_buser = 'b0;
+
+    assign s_axi_rlast = 1'b1;
+    assign s_axi_rid   = 'b0;
+    assign s_axi_ruser = 'b0;
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+
+
+//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+// Description: SRL based FIFO for AXIS/AXI Channels.
+//--------------------------------------------------------------------------
+
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_infrastructure_v1_1_0_axic_srl_fifo #(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter         C_FAMILY     = "virtex7",
+  parameter integer C_PAYLOAD_WIDTH = 1,
+  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                        aclk,    // Clock
+  input  wire                        aresetn,  // Reset
+  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data
+  input  wire                        s_valid, // Input data valid
+  output reg                         s_ready, // Input data ready
+  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data
+  output reg                         m_valid, // Output data valid
+  input  wire                        m_ready  // Output data ready
+);
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+// ceiling logb2
+function integer f_clogb2 (input integer size);
+  integer s;
+  begin
+    s = size;
+    s = s - 1;
+    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
+          s = s >> 1;
+  end
+endfunction // clogb2
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+reg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;
+wire [4-1:0]                        fifo_addr;
+wire                                push;
+wire                                pop ;
+reg                                 areset_r1;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+always @(posedge aclk) begin 
+  areset_r1 <= ~aresetn;
+end
+
+always @(posedge aclk) begin 
+  if (~aresetn) begin
+    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
+  end
+  else begin
+    fifo_index <= push & ~pop ? fifo_index + 1'b1 :
+                  ~push & pop ? fifo_index - 1'b1 : 
+                  fifo_index;
+  end
+end
+
+assign push = s_valid & s_ready;
+
+always @(posedge aclk) begin 
+  if (~aresetn) begin 
+    s_ready <= 1'b0;
+  end
+  else begin 
+    s_ready <= areset_r1 ? 1'b1 : 
+               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
+               ~push & pop ? 1'b1 : 
+               s_ready;
+  end
+end
+
+assign pop = m_valid & m_ready;
+               
+always @(posedge aclk) begin 
+  if (~aresetn) begin 
+    m_valid <= 1'b0;
+  end
+  else begin 
+    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
+               push & ~pop ? 1'b1 : 
+               m_valid;
+  end
+end
+
+generate 
+  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
+    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
+    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
+  end
+  else begin : gen_fifo_addr
+    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
+  end
+endgenerate
+
+
+generate
+  genvar i;
+  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
+    SRL16E 
+    u_srl_fifo(
+      .Q   ( m_payload[i] ) ,
+      .A0  ( fifo_addr[0]     ) ,
+      .A1  ( fifo_addr[1]     ) ,
+      .A2  ( fifo_addr[2]     ) ,
+      .A3  ( fifo_addr[3]     ) ,
+      .CE  ( push              ) ,
+      .CLK ( aclk              ) ,
+      .D   ( s_payload[i] ) 
+    );
+  end
+endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// axi to vector
+//   A generic module to merge all axi signals into one signal called payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_infrastructure_v1_1_0_vector2axi #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_AXI_PROTOCOL                = 0,
+  parameter integer C_AXI_ID_WIDTH                = 4,
+  parameter integer C_AXI_ADDR_WIDTH              = 32,
+  parameter integer C_AXI_DATA_WIDTH              = 32,
+  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
+  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
+  parameter integer C_AXI_AWUSER_WIDTH            = 1,
+  parameter integer C_AXI_WUSER_WIDTH             = 1,
+  parameter integer C_AXI_BUSER_WIDTH             = 1,
+  parameter integer C_AXI_ARUSER_WIDTH            = 1,
+  parameter integer C_AXI_RUSER_WIDTH             = 1,
+  parameter integer C_AWPAYLOAD_WIDTH             = 61,
+  parameter integer C_WPAYLOAD_WIDTH              = 73,
+  parameter integer C_BPAYLOAD_WIDTH              = 6,
+  parameter integer C_ARPAYLOAD_WIDTH             = 61,
+  parameter integer C_RPAYLOAD_WIDTH              = 69
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave Interface Write Address Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,
+  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,
+  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
+  output wire [3-1:0]                               m_axi_awsize,
+  output wire [2-1:0]                               m_axi_awburst,
+  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
+  output wire [4-1:0]                               m_axi_awcache,
+  output wire [3-1:0]                               m_axi_awprot,
+  output wire [4-1:0]                               m_axi_awregion,
+  output wire [4-1:0]                               m_axi_awqos,
+  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,
+
+  // Slave Interface Write Data Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,
+  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,
+  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,
+  output wire                                       m_axi_wlast,
+  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,
+
+  // Slave Interface Write Response Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,
+  input  wire [2-1:0]                               m_axi_bresp,
+  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,
+
+   // Slave Interface Read Address Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,
+  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,
+  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
+  output wire [3-1:0]                               m_axi_arsize,
+  output wire [2-1:0]                               m_axi_arburst,
+  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
+  output wire [4-1:0]                               m_axi_arcache,
+  output wire [3-1:0]                               m_axi_arprot,
+  output wire [4-1:0]                               m_axi_arregion,
+  output wire [4-1:0]                               m_axi_arqos,
+  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,
+
+  // Slave Interface Read Data Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,
+  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,
+  input  wire [2-1:0]                               m_axi_rresp,
+  input  wire                                       m_axi_rlast,
+  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,
+
+  // payloads
+  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,
+  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,
+  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,
+  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,
+  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axi_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// AXI4, AXI4LITE, AXI3 packing
+assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
+assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
+
+assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
+assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
+
+assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
+
+assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
+assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
+
+assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
+assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
+
+generate
+  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
+    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;
+    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
+    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
+    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;
+    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;
+    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;
+    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;
+
+    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;
+    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
+      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;
+    end
+    else begin : gen_no_axi3_wid_packing
+      assign m_axi_wid = 1'b0;
+    end
+
+    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
+
+    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;
+    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
+    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
+    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;
+    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;
+    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;
+    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;
+
+    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
+    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;
+
+    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
+      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
+      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
+    end 
+    else begin : gen_no_region_signals
+      assign m_axi_awregion = 'b0;
+      assign m_axi_arregion = 'b0;
+    end
+    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
+      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
+      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;
+      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;
+      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
+      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;
+    end 
+    else begin : gen_no_user_signals
+      assign m_axi_awuser = 'b0;
+      assign m_axi_wuser = 'b0;
+      assign m_axi_aruser = 'b0;
+    end
+  end
+  else begin : gen_axi4lite_packing
+    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
+    assign m_axi_awburst = 'b0;
+    assign m_axi_awcache = 'b0;
+    assign m_axi_awlen = 'b0;
+    assign m_axi_awlock = 'b0;
+    assign m_axi_awid = 'b0;
+    assign m_axi_awqos = 'b0;
+
+    assign m_axi_wlast = 1'b1;
+    assign m_axi_wid = 'b0;
+
+
+    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
+    assign m_axi_arburst = 'b0;
+    assign m_axi_arcache = 'b0;
+    assign m_axi_arlen = 'b0;
+    assign m_axi_arlock = 'b0;
+    assign m_axi_arid = 'b0;
+    assign m_axi_arqos = 'b0;
+
+    assign m_axi_awregion = 'b0;
+    assign m_axi_arregion = 'b0;
+
+    assign m_axi_awuser = 'b0;
+    assign m_axi_wuser = 'b0;
+    assign m_axi_aruser = 'b0;
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+
+

Milestone4/es_milestone4/es_milestone4.gen/sources_1/bd/design_1/ipshared/ed63/hdl/axi_vip_v1_1_vl_rfs.sv

@@ -0,0 +1,633 @@
+//  (c) Copyright 2016 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// AXI VIP wrapper
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axi_vip
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_vip_v1_1_14_top #
+  (
+   parameter C_AXI_PROTOCOL                      = 0,
+   parameter C_AXI_INTERFACE_MODE                = 1,  //master, slave and bypass
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_WDATA_WIDTH           = 32,
+   parameter integer C_AXI_RDATA_WIDTH           = 32,
+   parameter integer C_AXI_WID_WIDTH             = 0,
+   parameter integer C_AXI_RID_WIDTH             = 0,
+   parameter integer C_AXI_AWUSER_WIDTH          = 0,
+   parameter integer C_AXI_ARUSER_WIDTH          = 0,
+   parameter integer C_AXI_WUSER_WIDTH           = 0,
+   parameter integer C_AXI_RUSER_WIDTH           = 0,
+   parameter integer C_AXI_BUSER_WIDTH           = 0,
+   parameter integer C_AXI_SUPPORTS_NARROW       = 1,
+   parameter integer C_AXI_HAS_BURST             = 1,
+   parameter integer C_AXI_HAS_LOCK              = 1,
+   parameter integer C_AXI_HAS_CACHE             = 1,
+   parameter integer C_AXI_HAS_REGION            = 1,
+   parameter integer C_AXI_HAS_PROT              = 1,
+   parameter integer C_AXI_HAS_QOS               = 1,
+   parameter integer C_AXI_HAS_WSTRB             = 1,
+   parameter integer C_AXI_HAS_BRESP             = 1,
+   parameter integer C_AXI_HAS_RRESP             = 1,
+   parameter integer C_AXI_HAS_ARESETN           = 1
+   )
+  (
+   //NOTE:  C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE
+   //Please refer xgui tcl and coreinfo.yml
+   
+   // System Signals
+   input wire aclk,
+   input wire aclken,
+   input wire aresetn,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          s_axi_awid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]                              s_axi_awaddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               s_axi_awlen,
+   input  wire [3-1:0]                                             s_axi_awsize,
+   input  wire [2-1:0]                                             s_axi_awburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               s_axi_awlock,
+   input  wire [4-1:0]                                             s_axi_awcache,
+   input  wire [3-1:0]                                             s_axi_awprot,
+   input  wire [4-1:0]                                             s_axi_awregion,
+   input  wire [4-1:0]                                             s_axi_awqos,
+   input  wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0]    s_axi_awuser,
+   input  wire                                                     s_axi_awvalid,
+   output wire                                                     s_axi_awready,
+
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          s_axi_wid,
+   input  wire [C_AXI_WDATA_WIDTH-1:0]                             s_axi_wdata,
+   input  wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb,
+   input  wire                                                     s_axi_wlast,
+   input  wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0]      s_axi_wuser,
+   input  wire                                                     s_axi_wvalid,
+   output wire                                                     s_axi_wready,
+
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          s_axi_bid,
+   output wire [2-1:0]                                             s_axi_bresp,
+   output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,
+   output wire                                                     s_axi_bvalid,
+   input  wire                                                     s_axi_bready,
+
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          s_axi_arid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]                              s_axi_araddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               s_axi_arlen,
+   input  wire [3-1:0]                                             s_axi_arsize,
+   input  wire [2-1:0]                                             s_axi_arburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               s_axi_arlock,
+   input  wire [4-1:0]                                             s_axi_arcache,
+   input  wire [3-1:0]                                             s_axi_arprot,
+   input  wire [4-1:0]                                             s_axi_arregion,
+   input  wire [4-1:0]                                             s_axi_arqos,
+   input  wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0]    s_axi_aruser,
+   input  wire                                                     s_axi_arvalid,
+   output wire                                                     s_axi_arready,
+
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          s_axi_rid,
+   output wire [C_AXI_RDATA_WIDTH-1:0]                             s_axi_rdata,
+   output wire [2-1:0]                                             s_axi_rresp,
+   output wire                                                     s_axi_rlast,
+   output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,
+   output wire                                                     s_axi_rvalid,
+   input  wire                                                     s_axi_rready,
+   
+   // Master Interface Write Address Port
+   output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          m_axi_awid,
+   output wire [C_AXI_ADDR_WIDTH-1:0]                              m_axi_awaddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               m_axi_awlen,
+   output wire [3-1:0]                                             m_axi_awsize,
+   output wire [2-1:0]                                             m_axi_awburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               m_axi_awlock,
+   output wire [4-1:0]                                             m_axi_awcache,
+   output wire [3-1:0]                                             m_axi_awprot,
+   output wire [4-1:0]                                             m_axi_awregion,
+   output wire [4-1:0]                                             m_axi_awqos,
+   output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0]    m_axi_awuser,
+   output wire                                                     m_axi_awvalid,
+   input  wire                                                     m_axi_awready,
+   
+   // Master Interface Write Data Ports
+   output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          m_axi_wid,
+   output wire [C_AXI_WDATA_WIDTH-1:0]                             m_axi_wdata,
+   output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb,
+   output wire                                                     m_axi_wlast,
+   output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,
+   output wire                                                     m_axi_wvalid,
+   input  wire                                                     m_axi_wready,
+   
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          m_axi_bid,
+   input  wire [2-1:0]                                             m_axi_bresp,
+   input  wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0]      m_axi_buser,
+   input  wire                                                     m_axi_bvalid,
+   output wire                                                     m_axi_bready,
+   
+   // Master Interface Read Address Port
+   output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          m_axi_arid,
+   output wire [ C_AXI_ADDR_WIDTH-1:0]                             m_axi_araddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               m_axi_arlen,
+   output wire [3-1:0]                                             m_axi_arsize,
+   output wire [2-1:0]                                             m_axi_arburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               m_axi_arlock,
+   output wire [4-1:0]                                             m_axi_arcache,
+   output wire [3-1:0]                                             m_axi_arprot,
+   output wire [4-1:0]                                             m_axi_arregion,
+   output wire [4-1:0]                                             m_axi_arqos,
+   output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0]    m_axi_aruser,
+   output wire                                                     m_axi_arvalid,
+   input  wire                                                     m_axi_arready,
+   
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          m_axi_rid,
+   input  wire [C_AXI_RDATA_WIDTH-1:0]                             m_axi_rdata,
+   input  wire [2-1:0]                                             m_axi_rresp,
+   input  wire                                                     m_axi_rlast,
+   input  wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0]      m_axi_ruser,
+   input  wire                                                     m_axi_rvalid,
+   output wire                                                     m_axi_rready
+  );
+   
+  /**********************************************************************************************
+  * NOTE:  
+  *   C_AXI_INTERFACE_MODE =0 -- MASTER MODE, 
+  *   C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE 
+  *   C_AXI_INTERFACE_MODE =2 -- SLAVE MODE
+  *   Please refer xgui tcl and coreinfo.yml
+  *   User can change PASS_THROUGH VIP to run time master mode or run time slave mode during 
+  *   the simulation 
+  *********************************************************************************************/
+
+  /**********************************************************************************************
+  * Master_mode means that either the dut is statically being configured to be in master mode
+  * or it statically being configured to be pass-through mode and switched to be in master mode
+  * in run time. 
+   
+  * Slave mode means that either the dut is statically being configured to be in slave mode
+  * or it statically being configured to be pass-through mode and switched to be in slave mode
+  * in run time. 
+
+   * Pass-through mode means that either the dut is statically being configured to be in
+   * pass-through mode or it statically being configured to be pass-through mode and switched
+   * to be in master/slave mode and then switch back to be in pass-through mode in run time
+  *********************************************************************************************/
+
+  logic runtime_master =0;
+  logic runtime_slave =0;
+
+  wire run_slave_mode;
+  wire run_master_mode;
+  wire run_passth_mode;
+  wire compile_master_mode;
+  wire compile_slave_mode;
+  wire master_mode;
+  wire slave_mode;
+
+  assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0);
+  assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0;
+  assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0);
+
+  assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ;   
+  assign compile_slave_mode  = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ;
+
+  assign master_mode = compile_master_mode || run_master_mode; 
+  assign slave_mode = compile_slave_mode || run_slave_mode;
+
+  // Slave Interface Write Address Ports Internal
+  assign IF.AWID        = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
+  assign IF.AWADDR      = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}};
+  assign IF.AWLEN       = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
+  assign IF.AWSIZE      = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}};
+  assign IF.AWBURST     = slave_mode? s_axi_awburst : {2{1'bz}};
+  assign IF.AWLOCK      = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
+  assign IF.AWCACHE     = slave_mode? s_axi_awcache : {4{1'bz}};
+  assign IF.AWPROT      = slave_mode? s_axi_awprot : {3{1'bz}};
+  assign IF.AWREGION    = slave_mode? s_axi_awregion : {4{1'bz}};
+  assign IF.AWQOS       = slave_mode? s_axi_awqos : {4{1'bz}};
+  assign IF.AWUSER      = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}};
+  assign IF.AWVALID     = slave_mode? s_axi_awvalid : {1'bz};
+  assign s_axi_awready  = slave_mode? IF.AWREADY : {1'b0};
+
+  // Slave Interface Write Data Ports  
+  assign IF.WID         = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
+  assign IF.WDATA       = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}};
+  assign IF.WSTRB       = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};
+  assign IF.WLAST       = slave_mode? s_axi_wlast: {1'bz};
+  assign IF.WUSER       = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}};
+  assign IF.WVALID      = slave_mode? s_axi_wvalid : {1'bz}; 
+  assign s_axi_wready   = slave_mode? IF.WREADY : {1'b0};
+
+  // Slave Interface Write Response Ports
+  assign s_axi_bid      = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
+  assign s_axi_bresp    = slave_mode? IF.BRESP : {2{1'b0}};
+  assign s_axi_buser    = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}};
+  assign s_axi_bvalid   = slave_mode? IF.BVALID : {1{1'b0}};
+  assign IF.BREADY      = slave_mode? s_axi_bready :{1{1'bz}};
+
+  // Slave Interface Read Address Ports 
+  assign IF.ARID        = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
+  assign IF.ARADDR      = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ;
+  assign IF.ARLEN       = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
+  assign IF.ARSIZE      = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}};
+  assign IF.ARBURST     = slave_mode? s_axi_arburst : {2{1'bz}};
+  assign IF.ARLOCK      = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
+  assign IF.ARCACHE     = slave_mode? s_axi_arcache : {4{1'bz}};
+  assign IF.ARPROT      = slave_mode? s_axi_arprot : {3{1'bz}};
+  assign IF.ARREGION    = slave_mode? s_axi_arregion :{4{1'bz}} ;
+  assign IF.ARQOS       = slave_mode? s_axi_arqos : {4{1'bz}};
+  assign IF.ARUSER      = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}};
+  assign IF.ARVALID     = slave_mode? s_axi_arvalid : {1'bz};
+  assign s_axi_arready  = slave_mode? IF.ARREADY : {1'b0};
+
+  //Slave Interface Read Data Ports 
+  assign s_axi_rid      = slave_mode?  IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
+  assign s_axi_rdata    = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}};
+  assign s_axi_rresp    = slave_mode? IF.RRESP : {2{1'b0}};
+  assign s_axi_rlast    = slave_mode? IF.RLAST : {{1'b0}};
+  assign s_axi_ruser    = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}};
+  assign s_axi_rvalid   = slave_mode? IF.RVALID : {{1'b0}};
+  assign IF.RREADY      = slave_mode? s_axi_rready:{{1'bz}};
+
+  // Master Interface Write Address Port 
+  assign m_axi_awid     = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
+  assign m_axi_awaddr   = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}};
+  assign m_axi_awlen    = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
+  assign m_axi_awsize   = master_mode? IF.AWSIZE : {3{1'b0}};
+  assign m_axi_awburst  = master_mode? IF.AWBURST : {2{1'b0}};
+  assign m_axi_awlock   = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
+  assign m_axi_awcache  = master_mode? IF.AWCACHE : {4{1'b0}};
+  assign m_axi_awprot   = master_mode? IF.AWPROT : {3{1'b0}};
+  assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}};
+  assign m_axi_awqos    = master_mode? IF.AWQOS : {4{1'b0}};
+  assign m_axi_awuser   = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}};
+  assign m_axi_awvalid  = master_mode? IF.AWVALID :{1'b0};
+  assign IF.AWREADY     = master_mode? m_axi_awready :{1'bz};
+
+  // Master Interface Write Data Ports Internal
+  assign m_axi_wid      = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
+  assign m_axi_wdata    = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}};
+  assign m_axi_wstrb    = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}};
+  assign m_axi_wlast    = master_mode? IF.WLAST : {1'b0};
+  assign m_axi_wuser    = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}};
+  assign m_axi_wvalid   = master_mode? IF.WVALID : {1'b0};
+  assign IF.WREADY      = master_mode? m_axi_wready : {1'bz};
+
+  // Master Interface Write Response Ports Internal
+  assign IF.BID        = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
+  assign IF.BRESP      = master_mode? m_axi_bresp : {2{1'bz}};
+  assign IF.BUSER      = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}};
+  assign IF.BVALID     = master_mode? m_axi_bvalid : 1'bz;
+  assign m_axi_bready  = master_mode? IF.BREADY : 1'b0;
+
+  // Master Interface Read Address Port Internal
+  assign m_axi_arid     = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
+  assign m_axi_araddr   = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}};
+  assign m_axi_arlen    = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
+  assign m_axi_arsize   = master_mode? IF.ARSIZE : {3{1'b0}};
+  assign m_axi_arburst  = master_mode? IF.ARBURST : {2{1'b0}};
+  assign m_axi_arlock   = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
+  assign m_axi_arcache  = master_mode?IF.ARCACHE : {4{1'b0}};
+  assign m_axi_arprot   = master_mode? IF.ARPROT : {3{1'b0}};
+  assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}};
+  assign m_axi_arqos    = master_mode? IF.ARQOS : {4{1'b0}};
+  assign m_axi_aruser   = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}};
+  assign m_axi_arvalid  = master_mode? IF.ARVALID :{1'b0};
+  assign IF.ARREADY     = master_mode? m_axi_arready : {1{1'bz}};
+
+  // Master Interface Read Data Ports Internal
+  assign IF.RID        = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
+  assign IF.RDATA      = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}};
+  assign IF.RRESP      = master_mode? m_axi_rresp : {2{1'bz}};
+  assign IF.RLAST      = master_mode? m_axi_rlast : {1{1'bz}};
+  assign IF.RUSER      = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}};
+  assign IF.RVALID     = master_mode? m_axi_rvalid : {1{1'bz}};
+  assign m_axi_rready  = master_mode? IF.RREADY : {1{1'b0}};
+
+  axi_vip_if #(
+    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),
+    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ),
+    .C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ),
+    .C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ),
+    .C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ),
+    .C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ), 
+    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ), 
+    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ),
+    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ),
+    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ),
+    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ),
+    .C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),
+    .C_AXI_HAS_BURST(C_AXI_HAS_BURST),
+    .C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),
+    .C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),
+    .C_AXI_HAS_REGION(C_AXI_HAS_REGION),
+    .C_AXI_HAS_PROT(C_AXI_HAS_PROT),
+    .C_AXI_HAS_QOS(C_AXI_HAS_QOS),
+    .C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),
+    .C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),
+    .C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),
+    .C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN)
+  ) IF (
+    .ACLK(aclk),
+    .ARESET_N(aresetn),
+    .ACLKEN(aclken)
+  );  
+
+
+  //synthesis translate_off
+  initial begin
+    $display("XilinxAXIVIP: Found at Path: %m");
+  end
+
+  //set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode  
+  generate
+    initial begin
+      if(C_AXI_INTERFACE_MODE ==0) begin
+        IF.set_intf_master;
+      end else if(C_AXI_INTERFACE_MODE ==2) begin
+        IF.set_intf_slave;
+      end else if(C_AXI_INTERFACE_MODE ==1) begin
+        $display("This AXI VIP is in passthrough mode");
+      end else begin
+        $fatal(0,"This AXI VIP's mode is out of range");
+      end
+    end  
+  endgenerate
+
+  /*
+   Function: set_passthrough_mode
+   Sets AXI VIP passthrough into run time passthrough mode
+  */
+  function void set_passthrough_mode();
+    if (C_AXI_INTERFACE_MODE == 1) begin
+      runtime_master = 0;
+      runtime_slave = 0;
+      IF.set_intf_monitor();
+    end else begin
+      $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
+    end
+  endfunction: set_passthrough_mode
+
+  /*
+   Function: set_master_mode
+   Sets AXI VIP passthrough into run time master mode
+  */
+  function void set_master_mode();
+    if (C_AXI_INTERFACE_MODE == 1) begin
+      runtime_master = 1;
+      runtime_slave = 0;
+      IF.set_intf_master();
+    end else begin
+      $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP ");
+    end
+  endfunction : set_master_mode
+
+  /*
+   Function: set_slave_mode
+   Sets AXI VIP passthrough into run time slave mode
+  */
+  function void set_slave_mode();
+    if (C_AXI_INTERFACE_MODE == 1) begin
+      runtime_master = 0;
+      runtime_slave = 1;
+      IF.set_intf_slave();
+    end else begin
+      $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete  non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
+    end
+  endfunction : set_slave_mode
+
+  /*
+  Function: set_xilinx_slave_ready_check
+  Sets xilinx_slave_ready_check_enable of IF to be 1
+  */
+  function void set_xilinx_slave_ready_check();
+    IF.xilinx_slave_ready_check_enable = 1;
+  endfunction
+
+  /*
+   Function: clr_xilinx_slave_ready_check
+   Sets xilinx_slave_ready_check_enable of IF to be 0
+  */
+  function void clr_xilinx_slave_ready_check();
+    IF.xilinx_slave_ready_check_enable = 0;
+  endfunction
+
+  /*
+   Function: set_max_aw_wait_cycles (not available in VIVADO Simulator)
+   Sets max_aw_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_aw_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_aw_wait_cycles = new_num;
+  endfunction : set_max_aw_wait_cycles
+
+  /*
+   Function: set_max_ar_wait_cycles (not available in VIVADO Simulator)
+   Sets max_ar_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_ar_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_ar_wait_cycles = new_num;
+  endfunction : set_max_ar_wait_cycles
+
+  /*
+   Function: set_max_r_wait_cycles (not available in VIVADO Simulator)
+   Sets max_r_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_r_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_r_wait_cycles = new_num;
+  endfunction : set_max_r_wait_cycles
+
+  /*
+   Function: set_max_b_wait_cycles (not available in VIVADO Simulator)
+   Sets max_b_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_b_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_b_wait_cycles = new_num;
+  endfunction : set_max_b_wait_cycles
+
+  /*
+   Function: set_max_w_wait_cycles (not available in VIVADO Simulator)
+   Sets max_w_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_w_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_w_wait_cycles = new_num;
+  endfunction : set_max_w_wait_cycles
+
+  /*
+   Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator)
+   Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_wlast_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_wlast_to_awvalid_wait_cycles = new_num;
+  endfunction : set_max_wlast_wait_cycles
+
+  /*
+   Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
+   Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_rtransfers_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_rtransfers_wait_cycles = new_num;
+  endfunction : set_max_rtransfers_wait_cycles
+
+  /*
+   Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
+   Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_wtransfers_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_wtransfers_wait_cycles = new_num;
+  endfunction : set_max_wtransfers_wait_cycles
+
+  /*
+   Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
+   Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_wlcmd_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_wlcmd_wait_cycles = new_num;
+  endfunction : set_max_wlcmd_wait_cycles
+
+  /*
+   Function: get_max_aw_wait_cycles (not available in VIVADO Simulator)
+   Returns max_aw_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_aw_wait_cycles();
+    return(IF.PC.max_aw_wait_cycles);
+  endfunction : get_max_aw_wait_cycles
+
+  /*
+   Function: get_max_ar_wait_cycles (not available in VIVADO Simulator)
+   Returns max_ar_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_ar_wait_cycles();
+    return(IF.PC.max_ar_wait_cycles);
+  endfunction : get_max_ar_wait_cycles
+
+  /*
+   Function: get_max_r_wait_cycles (not available in VIVADO Simulator)
+   Returns max_r_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_r_wait_cycles();
+    return(IF.PC.max_r_wait_cycles);
+  endfunction : get_max_r_wait_cycles
+
+  /*
+   Function: get_max_b_wait_cycles (not available in VIVADO Simulator)
+   Returns max_b_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_b_wait_cycles();
+    return(IF.PC.max_b_wait_cycles);
+  endfunction : get_max_b_wait_cycles
+
+  /*
+   Function: get_max_w_wait_cycles (not available in VIVADO Simulator)
+   Returns max_w_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_w_wait_cycles();
+    return(IF.PC.max_w_wait_cycles);
+  endfunction :get_max_w_wait_cycles
+
+  /*
+   Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator)
+   Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_wlast_wait_cycles();
+    return(IF.PC.max_wlast_to_awvalid_wait_cycles);
+  endfunction :get_max_wlast_wait_cycles
+
+  /*
+   Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
+   Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_rtransfers_wait_cycles();
+    return(IF.PC.max_rtransfers_wait_cycles);
+  endfunction :get_max_rtransfers_wait_cycles
+
+  /*
+   Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
+   Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_wtransfers_wait_cycles();
+    return(IF.PC.max_wtransfers_wait_cycles);
+  endfunction :get_max_wtransfers_wait_cycles
+
+  /*
+   Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
+   Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_wlcmd_wait_cycles();
+    return(IF.PC.max_wlcmd_wait_cycles);
+  endfunction :get_max_wlcmd_wait_cycles
+
+  /*
+   Function:  set_fatal_to_warnings (not available in VIVADO Simulator)
+   Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1
+  */
+  function void set_fatal_to_warnings();
+    IF.PC.fatal_to_warnings = 1;
+  endfunction : set_fatal_to_warnings
+
+  /*
+   Function:   clr_fatal_to_warnings (not available in VIVADO Simulator)
+   Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0
+  */
+  function void clr_fatal_to_warnings();
+    IF.PC.fatal_to_warnings = 0;
+  endfunction : clr_fatal_to_warnings
+  //synthesis translate_on
+
+endmodule // axi_vip_v1_1_14_top
+
+

Milestone4/es_milestone4/es_milestone4.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.xci

@@ -0,0 +1,301 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_auto_pc_0",
+    "cell_name": "ps7_0_axi_periph/s00_couplers/auto_pc",
+    "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
+    "ip_revision": "28",
+    "gen_directory": "../../../../../../es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0",
+    "parameters": {
+      "component_parameters": {
+        "SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "design_1_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z020" } ],
+        "PACKAGE": [ { "value": "clg400" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "VHDL" } ],
+        "SPEEDGRADE": [ { "value": "-1" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "28" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../es_milestone4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "s_axi_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
+        "s_axi_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rlast": [ { "direction": "out" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awvalid": [ { "direction": "out" } ],
+        "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_wvalid": [ { "direction": "out" } ],
+        "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bready": [ { "direction": "out" } ],
+        "m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_arvalid": [ { "direction": "out" } ],
+        "m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
+        "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_rready": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWID": [ { "physical_name": "s_axi_awid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WID": [ { "physical_name": "s_axi_wid" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BID": [ { "physical_name": "s_axi_bid" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARID": [ { "physical_name": "s_axi_arid" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARLEN": [ { "physical_name": "s_axi_arlen" } ],
+            "ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
+            "ARBURST": [ { "physical_name": "s_axi_arburst" } ],
+            "ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
+            "ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+            "ARQOS": [ { "physical_name": "s_axi_arqos" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RID": [ { "physical_name": "s_axi_rid" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RLAST": [ { "physical_name": "s_axi_rlast" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "M_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "m_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "m_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "m_axi_arready" } ],
+            "RDATA": [ { "physical_name": "m_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "m_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "m_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "m_axi_rready" } ]
+          }
+        },
+        "CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

Milestone4/es_milestone4/es_milestone4.srcs/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0/design_1_axil_gpio_0_0.xci

@@ -0,0 +1,170 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_axil_gpio_0_0",
+    "cell_name": "axil_gpio_0",
+    "component_reference": "xilinx.com:user:axil_gpio:1.0",
+    "ip_revision": "7",
+    "gen_directory": "../../../../../../es_milestone4.gen/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0",
+    "parameters": {
+      "component_parameters": {
+        "GPI_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "GPO_WIDTH": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "design_1_axil_gpio_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "GPI_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "GPO_WIDTH": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z020" } ],
+        "PACKAGE": [ { "value": "clg400" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "VHDL" } ],
+        "SPEEDGRADE": [ { "value": "-1" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "7" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../es_milestone4.gen/sources_1/bd/design_1/ip/design_1_axil_gpio_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "S_AXIL_ACLK": [ { "direction": "in" } ],
+        "S_AXIL_ARESETN": [ { "direction": "in", "driver_value": "0x1" } ],
+        "S_AXIL_AWADDR": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
+        "S_AXIL_AWVALID": [ { "direction": "in", "driver_value": "0x0" } ],
+        "S_AXIL_AWREADY": [ { "direction": "out" } ],
+        "S_AXIL_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "S_AXIL_WVALID": [ { "direction": "in", "driver_value": "0x0" } ],
+        "S_AXIL_WREADY": [ { "direction": "out" } ],
+        "S_AXIL_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S_AXIL_BVALID": [ { "direction": "out" } ],
+        "S_AXIL_BREADY": [ { "direction": "in", "driver_value": "0x1" } ],
+        "S_AXIL_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "S_AXIL_ARADDR": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
+        "S_AXIL_ARVALID": [ { "direction": "in", "driver_value": "0x0" } ],
+        "S_AXIL_ARREADY": [ { "direction": "out" } ],
+        "S_AXIL_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "S_AXIL_RVALID": [ { "direction": "out" } ],
+        "S_AXIL_RREADY": [ { "direction": "in", "driver_value": "0x1" } ],
+        "S_AXIL_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "GPI": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "GPO": [ { "direction": "out", "size_left": "5", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "S_AXIL": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S_AXIL",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "15", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "S_AXIL_AWADDR" } ],
+            "AWVALID": [ { "physical_name": "S_AXIL_AWVALID" } ],
+            "AWREADY": [ { "physical_name": "S_AXIL_AWREADY" } ],
+            "WDATA": [ { "physical_name": "S_AXIL_WDATA" } ],
+            "WSTRB": [ { "physical_name": "S_AXIL_WSTRB" } ],
+            "WVALID": [ { "physical_name": "S_AXIL_WVALID" } ],
+            "WREADY": [ { "physical_name": "S_AXIL_WREADY" } ],
+            "BRESP": [ { "physical_name": "S_AXIL_BRESP" } ],
+            "BVALID": [ { "physical_name": "S_AXIL_BVALID" } ],
+            "BREADY": [ { "physical_name": "S_AXIL_BREADY" } ],
+            "ARADDR": [ { "physical_name": "S_AXIL_ARADDR" } ],
+            "ARVALID": [ { "physical_name": "S_AXIL_ARVALID" } ],
+            "ARREADY": [ { "physical_name": "S_AXIL_ARREADY" } ],
+            "RDATA": [ { "physical_name": "S_AXIL_RDATA" } ],
+            "RRESP": [ { "physical_name": "S_AXIL_RRESP" } ],
+            "RVALID": [ { "physical_name": "S_AXIL_RVALID" } ],
+            "RREADY": [ { "physical_name": "S_AXIL_RREADY" } ]
+          }
+        },
+        "S_AXIL_ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "S_AXIL_ARESETN" } ]
+          }
+        },
+        "S_AXIL_ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "S_AXIL_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "S_AXIL_ACLK" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_AXIL": {
+          "address_blocks": {
+            "reg0": {
+              "base_address": "0",
+              "range": "32768",
+              "usage": "register"
+            }
+          }
+        }
+      }
+    }
+  }
+}

Milestone4/es_milestone4/es_milestone4.srcs/sources_1/bd/design_1/ip/design_1_ps7_0_axi_periph_0/design_1_ps7_0_axi_periph_0.xci

@@ -0,0 +1,352 @@
+{
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+    "xci_name": "design_1_ps7_0_axi_periph_0",
+    "cell_name": "ps7_0_axi_periph",
+    "component_reference": "xilinx.com:ip:axi_interconnect:2.1",
+    "ip_revision": "29",
+    "gen_directory": "../../../../../../es_milestone4.gen/sources_1/bd/design_1/ip/design_1_ps7_0_axi_periph_0",
+    "parameters": {
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+        "ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "XBAR_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PCHK_WAITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PCHK_MAX_RD_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PCHK_MAX_WR_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
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Milestone4/es_milestone4/es_milestone4.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0.xci

@@ -0,0 +1,195 @@
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+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_rst_ps7_0_100M_0",
+    "cell_name": "rst_ps7_0_100M",
+    "component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
+    "ip_revision": "13",
+    "gen_directory": "../../../../../../es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0",
+    "parameters": {
+      "component_parameters": {
+        "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "design_1_rst_ps7_0_100M_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z020" } ],
+        "PACKAGE": [ { "value": "clg400" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "VHDL" } ],
+        "SPEEDGRADE": [ { "value": "-1" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "13" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../es_milestone4.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "slowest_sync_clk": [ { "direction": "in" } ],
+        "ext_reset_in": [ { "direction": "in" } ],
+        "aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
+        "mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
+        "dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
+        "mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
+        "bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
+        "peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
+      },
+      "interfaces": {
+        "clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "slowest_sync_clk" } ]
+          }
+        },
+        "ext_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "ext_reset_in" } ]
+          }
+        },
+        "aux_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aux_reset_in" } ]
+          }
+        },
+        "dbg_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "mb_debug_sys_rst" } ]
+          }
+        },
+        "mb_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "mb_reset" } ]
+          }
+        },
+        "bus_struct_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "bus_struct_reset" } ]
+          }
+        },
+        "interconnect_low_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "interconnect_aresetn" } ]
+          }
+        },
+        "peripheral_high_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "peripheral_reset" } ]
+          }
+        },
+        "peripheral_low_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "peripheral_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

Milestone4/es_milestone4/es_milestone4.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci

@@ -0,0 +1,49 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_xlconstant_0_0",
+    "cell_name": "xlconstant_0",
+    "component_reference": "xilinx.com:ip:xlconstant:1.1",
+    "ip_revision": "7",
+    "gen_directory": "../../../../../../es_milestone4.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "design_1_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
+        "CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CONST_VAL": [ { "value": "1", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CONST_VAL": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z020" } ],
+        "PACKAGE": [ { "value": "clg400" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "VHDL" } ],
+        "SPEEDGRADE": [ { "value": "-1" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "7" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../es_milestone4.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
+      }
+    }
+  }
+}

Milestone4/es_milestone4/es_milestone4.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui

@@ -0,0 +1,33 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.01291",
+   "Default View_TopLeft":"-185,-102",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
+#  -string -flagsOSRD
+preplace port DDR -pg 1 -lvl 4 -x 1280 -y 20 -defaultsOSRD
+preplace port FIXED_IO -pg 1 -lvl 4 -x 1280 -y 50 -defaultsOSRD
+preplace portBus sw -pg 1 -lvl 0 -x -10 -y 540 -defaultsOSRD
+preplace portBus rgbled -pg 1 -lvl 4 -x 1280 -y 510 -defaultsOSRD
+preplace inst processing_system7_0 -pg 1 -lvl 1 -x 240 -y 100 -defaultsOSRD
+preplace inst xlconstant_0 -pg 1 -lvl 1 -x 240 -y 330 -defaultsOSRD
+preplace inst axil_gpio_0 -pg 1 -lvl 1 -x 240 -y 510 -defaultsOSRD
+preplace inst ps7_0_axi_periph -pg 1 -lvl 3 -x 1090 -y 20 -defaultsOSRD
+preplace inst rst_ps7_0_100M -pg 1 -lvl 2 -x 650 -y 390 -defaultsOSRD
+preplace netloc xlconstant_0_dout 1 1 1 440 30n
+preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 30 390 450 160 930
+preplace netloc processing_system7_0_FCLK_RESET0_N 1 1 1 470 230n
+preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 3 40 420 440J 490 950
+preplace netloc sw_1 1 0 1 N 540
+preplace netloc axil_gpio_0_GPO 1 1 3 NJ 510 NJ 510 N
+preplace netloc processing_system7_0_DDR 1 1 3 470 140 N 140 1240
+preplace netloc processing_system7_0_FIXED_IO 1 1 3 460 150 N 150 1250
+preplace netloc processing_system7_0_M_AXI_GP0 1 1 2 NJ 70 820
+preplace netloc ps7_0_axi_periph_M00_AXI 1 0 4 20 -90 NJ -90 940J 160 1230
+levelinfo -pg 1 -10 240 650 1090 1280
+pagesize -pg 1 -db -bbox -sgen -110 -100 1630 600
+"
+}
+{
+   "da_axi4_cnt":"1"
+}

Milestone4/es_milestone4/es_milestone4.xpr

@@ -0,0 +1,396 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-praktikum/Milestone4/es_milestone4/es_milestone4.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="988f72fda1284cd2be7e180348f0d531"/>
+    <Option Name="Part" Val="xc7z020clg400-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2023.1"/>
+    <Option Name="SimulatorVersionModelSim" Val="2022.3"/>
+    <Option Name="SimulatorVersionQuesta" Val="2022.3"/>
+    <Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
+    <Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="SimulatorLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.2"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../../IP"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="zybo-z7-20"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
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+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+          <Attr Name="UsedIn" Val="simulation"/>
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+        <Option Name="TopModule" Val="design_1_wrapper"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
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+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../milestone4.xdc">
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+          <Attr Name="UsedIn" Val="implementation"/>
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+        <Option Name="ConstrsType" Val="XDC"/>
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+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="design_1_wrapper"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
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+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
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+      <Config>
+        <Option Name="TopModule" Val="design_1_axil_gpio_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
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+      <Config>
+        <Option Name="TopModule" Val="design_1_processing_system7_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
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+      <Config>
+        <Option Name="TopModule" Val="design_1_auto_pc_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
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+      <Config>
+        <Option Name="TopModule" Val="design_1_rst_ps7_0_100M_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
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+      <Option Name="CompiledLib" Val="0"/>
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+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
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+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
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+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
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+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+      <RQSFiles/>
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+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
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+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream">
+          <Option Id="BinFile">1</Option>
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+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
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+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
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+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
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+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
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+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
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+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
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+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
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+      <Strategy Version="1" Minor="2">
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+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
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+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
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+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+        <Step Id="power_opt_design"/>
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+        <Step Id="phys_opt_design"/>
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+        <Step Id="write_bitstream"/>
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+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
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+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
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+      <CurrentDashboard>default_dashboard</CurrentDashboard>
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