Matthias Biermann
35 lines
768 B
VHDL
35 lines
768 B
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
|
|
entity spi2display_rom is
|
|
generic(
|
|
AW : positive := 8
|
|
);
|
|
port (
|
|
clk : in std_logic;
|
|
addr : in std_logic_vector(AW-1 downto 0); -- Address
|
|
dout : out std_logic_vector(9 downto 0) -- Data out
|
|
);
|
|
end;
|
|
|
|
|
|
architecture rtl of spi2display_rom is
|
|
type tmem is array(0 to 2**AW-1) of std_logic_vector(9 downto 0);
|
|
signal mem : tmem := (
|
|
-- finished,repeat,8xdata
|
|
"00"&x"48",
|
|
"00"&x"61",
|
|
"00"&x"6C",
|
|
"00"&x"6C",
|
|
"10"&x"6F",
|
|
others=>"00"&x"20");
|
|
|
|
begin
|
|
process begin
|
|
wait until rising_edge(clk);
|
|
dout <= mem(to_integer(unsigned(addr)));
|
|
end process;
|
|
end;
|
|
|