Sebastian Meyer
147 lines
4.9 KiB
VHDL
147 lines
4.9 KiB
VHDL
library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axis_audio_bitcrusher is
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generic(
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BIT_REDUCTION : integer := 14;
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HAS_LAST : boolean := false
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);
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port
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(
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AXIS_ACLK : in std_logic;
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AXIS_ARESETN : in std_logic;
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-- AXI Streaming Target Port
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S_AXIS_TVALID : in std_logic := '0';
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S_AXIS_TDATA : in std_logic_vector(15 downto 0) := (others => '0');
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S_AXIS_TLAST : in std_logic := '0';
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S_AXIS_TREADY : out std_logic;
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-- AXI Streaming Initiator Port
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M_AXIS_TVALID : out std_logic;
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M_AXIS_TDATA : out std_logic_vector(15 downto 0);
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M_AXIS_TLAST : out std_logic;
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M_AXIS_TREADY : in std_logic := '1'
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);
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end;
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architecture rtl of axis_audio_bitcrusher is
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-- Steuersignale zwischen Steuerwerk und Rechenwerk
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signal RegInputEn : std_logic := '0';
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signal RegOutputEn : std_logic := '0';
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-- Signale innerhalb des Rechenwerks
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signal caculatorInput : std_logic_vector(15 downto 0);
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signal caculatorOutput : std_logic_vector(15 downto 0);
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signal safeTLast : std_logic := '0';
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-- Finite state machine
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type state_t is (S_INPUT, S_CALCULATE, S_OUTPUT, S_ERROR);
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signal state : state_t := S_INPUT;
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signal state_next : state_t;
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begin
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-- Register fuer die Inputdaten
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RegInput: process
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begin
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wait until rising_edge(AXIS_ACLK);
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if RegInputEn = '1' then
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caculatorInput <= S_AXIS_TDATA;
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end if;
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end process;
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-- Kombinatorik fuer Bitcrusherberechnung
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Bitcrusher: process (caculatorInput)
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begin
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caculatorOutput <= caculatorInput(15 downto BIT_REDUCTION + 1) & (BIT_REDUCTION downto 0 => '0');
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end process;
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-- Register fuer die Outputdaten
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RegOutput: process
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begin
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wait until rising_edge(AXIS_ACLK);
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if RegOutputEn = '1' then
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M_AXIS_TDATA <= caculatorOutput;
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end if;
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end process;
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-- Prozesse fuer endlichen Automaten
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Transition: process(state, AXIS_ARESETN, M_AXIS_TREADY, S_AXIS_TVALID, S_AXIS_TLAST)
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begin
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-- Default-Werte fuer Folgezustand und Mealy-Ausgaenge
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state_next <= S_ERROR;
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-- Berechnung des Folgezustandes und der Mealy-Ausgaenge
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case state is
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when S_INPUT =>
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if HAS_LAST = true then
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if S_AXIS_TLAST = '1' then
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safeTLast <= '1';
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elsif S_AXIS_TLAST = '0' then
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safeTLast <= '0';
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end if;
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end if;
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if S_AXIS_TVALID = '1' then
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state_next <= S_CALCULATE;
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elsif S_AXIS_TVALID = '0' then
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state_next <= S_INPUT;
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end if;
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when S_CALCULATE =>
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state_next <= S_OUTPUT;
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when S_OUTPUT =>
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if HAS_LAST = true then
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if safeTLast = '1' then
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M_AXIS_TLAST <= '1';
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elsif safeTLast = '0' then
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M_AXIS_TLAST <= '0';
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end if;
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end if;
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if M_AXIS_TREADY = '1' then
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state_next <= S_INPUT;
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elsif M_AXIS_TREADY = '0' then
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state_next <= S_OUTPUT;
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end if;
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when S_ERROR =>
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if AXIS_ARESETN = '1' then
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state_next <= S_OUTPUT;
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else
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state_next <= S_ERROR;
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end if;
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end case;
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end process;
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-- Register fuer Zustand und Ausgaenge
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Reg: process
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begin
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wait until rising_edge(AXIS_ACLK);
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-- Zustandswechsel
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state <= state_next;
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-- Berechnung der Moore-Ausgaenge, die nur vom Zustand abhaengen
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-- Default-Werte
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S_AXIS_TREADY <= 'X';
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RegOutputEn <= 'X';
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RegInputEn <= 'X';
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M_AXIS_TVALID <= 'X';
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case state_next is
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when S_INPUT =>
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S_AXIS_TREADY <= '1';
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RegOutputEn <= '0';
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RegInputEn <= '1';
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M_AXIS_TVALID <= '0';
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when S_CALCULATE =>
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S_AXIS_TREADY <= '0';
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RegOutputEn <= '1';
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RegInputEn <= '0';
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M_AXIS_TVALID <= '0';
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when S_OUTPUT =>
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S_AXIS_TREADY <= '0';
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RegOutputEn <= '0';
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RegInputEn <= '0';
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M_AXIS_TVALID <= '1';
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when S_ERROR =>
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S_AXIS_TREADY <= 'X';
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RegOutputEn <= 'X';
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RegInputEn <= 'X';
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M_AXIS_TVALID <= 'X';
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end case;
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end process;
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end rtl; |