Matthias Biermann
349 lines
14 KiB
Tcl
349 lines
14 KiB
Tcl
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################################################################
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# This is a generated script based on design: m6_sim
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2023.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source m6_sim_script.tcl
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xc7z020clg400-1
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set_property BOARD_PART digilentinc.com:zybo-z7-20:part0:1.1 [current_project]
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name m6_sim
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:user:axis_downsizer:1.0\
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xilinx.com:user:axis_linemem_single_master:1.0\
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xilinx.com:user:axis_filter_dummy:1.0\
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xilinx.com:user:axis_upsizer:1.0\
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wg:user:clk_rst_generator:1.0\
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Gehrke:user:axis_master_simmodel:1.0\
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Gehrke:user:axis_slave_simmodel:1.0\
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wg:user:axil_master_with_rom:1.0\
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"
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set list_ips_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Hierarchical cell: SIM_Environment
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proc create_hier_cell_SIM_Environment { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_SIM_Environment() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create cell and set as current instance
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set hier_obj [create_bd_cell -type hier $nameHier]
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current_bd_instance $hier_obj
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# Create interface pins
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXIL
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# Create pins
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create_bd_pin -dir O -type clk M_AXIL_ACLK
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create_bd_pin -dir O -type rst M_AXIL_ARESETN
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# Create instance: clk_rst_generator_0, and set properties
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set clk_rst_generator_0 [ create_bd_cell -type ip -vlnv wg:user:clk_rst_generator:1.0 clk_rst_generator_0 ]
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set_property -dict [list \
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CONFIG.HAS_CLK_INPUT {false} \
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CONFIG.HAS_RESET_INPUT {false} \
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CONFIG.HAS_STOP_INPUT {true} \
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] $clk_rst_generator_0
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# Create instance: axis_master_simmodel_0, and set properties
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set axis_master_simmodel_0 [ create_bd_cell -type ip -vlnv Gehrke:user:axis_master_simmodel:1.0 axis_master_simmodel_0 ]
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set_property -dict [list \
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CONFIG.FILE_NAME {../../../../Moewe-192x192} \
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CONFIG.NUM_LINES {192} \
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CONFIG.NUM_PIX_PER_LINE {192} \
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CONFIG.PIXEL_FORMAT {13} \
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] $axis_master_simmodel_0
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# Create instance: axis_slave_simmodel_0, and set properties
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set axis_slave_simmodel_0 [ create_bd_cell -type ip -vlnv Gehrke:user:axis_slave_simmodel:1.0 axis_slave_simmodel_0 ]
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set_property -dict [list \
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CONFIG.FILE_NAME {../../../../tst_out} \
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CONFIG.NUM_LINES {192} \
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CONFIG.NUM_PIX_PER_LINE {192} \
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CONFIG.PIXEL_FORMAT {13} \
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] $axis_slave_simmodel_0
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# Create instance: axil_master_with_rom_0, and set properties
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set axil_master_with_rom_0 [ create_bd_cell -type ip -vlnv wg:user:axil_master_with_rom:1.0 axil_master_with_rom_0 ]
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set_property -dict [list \
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CONFIG.HAS_FINISHED_OUT {false} \
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CONFIG.HAS_INTERRUPT_IN {false} \
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] $axil_master_with_rom_0
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# Create interface connections
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connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axil_master_with_rom_0/M_AXIL] [get_bd_intf_pins M_AXIL]
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connect_bd_intf_net -intf_net axis_master_simmodel_0_M_AXIS [get_bd_intf_pins M_AXIS] [get_bd_intf_pins axis_master_simmodel_0/M_AXIS]
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connect_bd_intf_net -intf_net axis_upsizer_0_M_AXIS [get_bd_intf_pins S_AXIS] [get_bd_intf_pins axis_slave_simmodel_0/S_AXIS]
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# Create port connections
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connect_bd_net -net axis_slave_simmodel_0_FINISHED [get_bd_pins axis_slave_simmodel_0/FINISHED] [get_bd_pins clk_rst_generator_0/stop_simulation]
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connect_bd_net -net clk_rst_generator_0_clk [get_bd_pins clk_rst_generator_0/clk] [get_bd_pins M_AXIL_ACLK] [get_bd_pins axil_master_with_rom_0/M_AXIL_ACLK] [get_bd_pins axis_slave_simmodel_0/S_AXIS_ACLK] [get_bd_pins axis_master_simmodel_0/ACLK]
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connect_bd_net -net clk_rst_generator_0_rst_n [get_bd_pins clk_rst_generator_0/rst_n] [get_bd_pins M_AXIL_ARESETN] [get_bd_pins axil_master_with_rom_0/M_AXIL_ARESETN] [get_bd_pins axis_slave_simmodel_0/S_AXIS_ARESETN] [get_bd_pins axis_master_simmodel_0/ARESETN]
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# Restore current instance
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current_bd_instance $oldCurInst
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}
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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# Create ports
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# Create instance: axis_downsizer_0, and set properties
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set axis_downsizer_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_downsizer:1.0 axis_downsizer_0 ]
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set_property CONFIG.SIZE_FACTOR {4} $axis_downsizer_0
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# Create instance: axis_linemem_single_0, and set properties
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set axis_linemem_single_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_linemem_single_master:1.0 axis_linemem_single_0 ]
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set_property CONFIG.DATA_WIDTH {8} $axis_linemem_single_0
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# Create instance: axis_filter_dummy_0, and set properties
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set axis_filter_dummy_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_filter_dummy:1.0 axis_filter_dummy_0 ]
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# Create instance: axis_upsizer_0, and set properties
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set axis_upsizer_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_upsizer:1.0 axis_upsizer_0 ]
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set_property CONFIG.SIZE_FACTOR {4} $axis_upsizer_0
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# Create instance: SIM_Environment
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create_hier_cell_SIM_Environment [current_bd_instance .] SIM_Environment
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# Create interface connections
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connect_bd_intf_net -intf_net axis_downsizer_0_M_AXIS [get_bd_intf_pins axis_downsizer_0/M_AXIS] [get_bd_intf_pins axis_linemem_single_0/s_axis]
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connect_bd_intf_net -intf_net axis_filter_dummy_0_M_AXIS [get_bd_intf_pins axis_filter_dummy_0/M_AXIS] [get_bd_intf_pins axis_upsizer_0/S_AXIS]
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connect_bd_intf_net -intf_net axis_linemem_single_0_m_axis [get_bd_intf_pins axis_linemem_single_0/m_axis] [get_bd_intf_pins axis_filter_dummy_0/S_AXIS]
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connect_bd_intf_net -intf_net axis_master_simmodel_0_M_AXIS [get_bd_intf_pins axis_downsizer_0/S_AXIS] [get_bd_intf_pins SIM_Environment/M_AXIS]
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connect_bd_intf_net -intf_net axis_upsizer_0_M_AXIS [get_bd_intf_pins axis_upsizer_0/M_AXIS] [get_bd_intf_pins SIM_Environment/S_AXIS]
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# Create port connections
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connect_bd_net -net clk_rst_generator_0_clk [get_bd_pins SIM_Environment/M_AXIL_ACLK] [get_bd_pins axis_filter_dummy_0/AXIS_ACLK] [get_bd_pins axis_linemem_single_0/aclk] [get_bd_pins axis_upsizer_0/AXIS_ACLK] [get_bd_pins axis_downsizer_0/AXIS_ACLK]
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connect_bd_net -net clk_rst_generator_0_rst_n [get_bd_pins SIM_Environment/M_AXIL_ARESETN] [get_bd_pins axis_filter_dummy_0/AXIS_ARESETN] [get_bd_pins axis_linemem_single_0/aresetn] [get_bd_pins axis_upsizer_0/AXIS_ARESETN] [get_bd_pins axis_downsizer_0/AXIS_ARESETN]
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# Create address segments
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# Restore current instance
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current_bd_instance $oldCurInst
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validate_bd_design
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save_bd_design
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}
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# End of create_root_design()
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##################################################################
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# MAIN FLOW
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##################################################################
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create_root_design ""
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