Matthias Biermann
77 lines
2.1 KiB
VHDL
77 lines
2.1 KiB
VHDL
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-- AXI-Lite Interface
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-----------------------
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S_AXIL_AWREADY <= '1';
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S_AXIL_WREADY <= '1';
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S_AXIL_BRESP <= "00";
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S_AXIL_ARREADY <= '1';
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S_AXIL_RRESP <= "00";
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process begin
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wait until rising_edge (ACLK);
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if ARESETN = '0' then
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S_AXIL_BVALID <= '0';
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S_AXIL_RVALID <= '0';
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coeff_11 <= (others=>'0');
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coeff_12 <= (others=>'0');
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coeff_13 <= (others=>'0');
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coeff_21 <= (others=>'0');
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coeff_22 <= (0=>'1',others=>'0');
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coeff_23 <= (others=>'0');
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coeff_31 <= (others=>'0');
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coeff_32 <= (others=>'0');
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coeff_33 <= (others=>'0');
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shiftAmount <= to_unsigned(0,wShift);
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else
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if S_AXIL_RREADY = '1' then
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S_AXIL_RVALID <= '0';
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end if;
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if S_AXIL_ARVALID = '1' then
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S_AXIL_RDATA <= (others=>'0');
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case (to_integer(unsigned(S_AXIL_ARADDR(5 downto 0)))) is
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when 0 =>
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when 4 =>
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when 8 =>
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when 12 =>
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when 16 =>
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when 20 =>
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when 24 =>
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when 28 =>
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when 32 =>
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when 36 =>
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when others => null;
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end case;
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S_AXIL_RVALID <= '1';
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end if;
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if S_AXIL_BREADY = '1' then
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S_AXIL_BVALID <= '';
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end if;
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if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
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S_AXIL_BVALID <= '';
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S_AXIL_RDATA <= (others=>'0');
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if S_AXIL_WSTRB(0) = '1' then
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case (to_integer(unsigned(S_AXIL_AWADDR(5 downto 0)))) is
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when 0 =>
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when 4 =>
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when 8 =>
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when 12 =>
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when 16 =>
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when 20 =>
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when 24 =>
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when 28 =>
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when 32 =>
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when 36 =>
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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