Matthias Biermann
63 lines
2.5 KiB
VHDL
63 lines
2.5 KiB
VHDL
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S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig1) or (not m_valid_sig2);
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-----------------------
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-- Filter Kernel
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-----------------------
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process
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variable data_11 : signed (wPixelSigned-1 downto 0);
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variable data_12 : signed (wPixelSigned-1 downto 0);
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variable data_13 : signed (wPixelSigned-1 downto 0);
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variable data_21 : signed (wPixelSigned-1 downto 0);
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variable data_22 : signed (wPixelSigned-1 downto 0);
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variable data_23 : signed (wPixelSigned-1 downto 0);
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variable data_31 : signed (wPixelSigned-1 downto 0);
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variable data_32 : signed (wPixelSigned-1 downto 0);
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variable data_33 : signed (wPixelSigned-1 downto 0);
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variable filterResult : signed (wFilterRes-1 downto 0);
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begin
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wait until rising_edge (ACLK);
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if ARESETN = '0' then
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m_valid_sig1 <= '0';
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m_valid_sig2 <= '0';
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else
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if M_AXIS_TREADY = '1' or m_valid_sig1='0' then
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data_11 := data_12;
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data_12 := data_13;
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data_13 := signed("0"&S_AXIS_TDATA(wPixel*3-1 downto wPixel*2));
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data_21 := data_22;
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data_22 := data_23;
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data_23 := signed("0"&S_AXIS_TDATA(wPixel*2-1 downto wPixel*1));
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data_31 := data_32;
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data_32 := data_33;
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data_33 := signed("0"&S_AXIS_TDATA(wPixel*1-1 downto wPixel*0));
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row1Result <= resize(data_11*coeff_11,wRowProd) + resize(data_12*coeff_12,wRowProd) + resize(data_13*coeff_13,wRowProd);
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row2Result <= ;
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row3Result <= ;
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m_last_sig1 <= S_AXIS_TLAST;
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m_user_sig1 <= S_AXIS_TUSER(1);
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m_valid_sig1 <= S_AXIS_TVALID;
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end if;
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if M_AXIS_TREADY = '1' or m_valid_sig2='0' then
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filterResult := resize(row1Result,wFilterRes)+resize()+resize();
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filterResult := shift_right(filterResult, to_integer());
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if (filterResult < 0) then
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filterResult := to_signed(0,wFilterRes);
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elsif (filterResult > 255) then
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filterResult := to_signed(255,wFilterRes);
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end if;
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M_AXIS_TDATA <= std_logic_vector(filterResult(7 downto 0));
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M_AXIS_TVALID <= m_valid_sig1;
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M_AXIS_TLAST <= m_last_sig1;
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M_AXIS_TUSER <= m_user_sig1;
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m_valid_sig2 <= m_valid_sig1;
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end if;
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end if;
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end process;
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