Sebastian Meyer
34 lines
1.0 KiB
VHDL
34 lines
1.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all
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use ieee.numeric_std.all
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entity axis_audio_bitcrusher is
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generic
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(
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BIT_REDUCTION : integer := 14;
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HAS_LAST : boolean := false
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);
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port
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(
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AXIS_ACLK : in std_logic;
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AXIS_ARESETN : in std_logic;
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-- AXI Streaming Target Port
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S_AXIS_TVALID : in std_logic := '0';
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S_AXIS_TDATA : in std_logic_vector(15 downto 0) := (others => '0');
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S_AXIS_TLAST : in std_logic := '0';
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S_AXIS_TREADY : out std_logic;
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-- AXI Streaming Initiator Port
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M_AXIS_TVALID : out std_logic;
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M_AXIS_TDATA : out std_logic_vector(15 downto 0);
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M_AXIS_TLAST : out std_logic;
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M_AXIS_TREADY : in std_logic := '1'
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);
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end;
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architecture rtl of axis_audio_bitcrusher is
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reg_out <= reg_in(31 downto x) & (others => '0'); -- Setze die Bits 0 bis (x-1) auf Null
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begin
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end; |