Sebastian Meyer
91 lines
3.6 KiB
VHDL
91 lines
3.6 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- File: SyncAsyncReset.vhd
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-- Author: Elod Gyorgy
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-- Original Project: HDMI input on 7-series Xilinx FPGA
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-- Date: 20 October 2014
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--
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-------------------------------------------------------------------------------
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-- (c) 2014 Copyright Digilent Incorporated
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-- All Rights Reserved
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--
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-- This program is free software; distributed under the terms of BSD 3-clause
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-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice, this
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-- list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright notice,
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-- this list of conditions and the following disclaimer in the documentation
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-- and/or other materials provided with the distribution.
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-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
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-- of its contributors may be used to endorse or promote products derived
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-- from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-------------------------------------------------------------------------------
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--
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-- Purpose:
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-- This module is a reset-bridge. It takes a reset signal asynchronous to the
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-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
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-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately
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-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
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-- edge. This means it can be used to safely reset any FF in the OutClk domain,
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-- respecting recovery time specs for FFs.
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ResetBridge is
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Generic (
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kPolarity : std_logic := '1');
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Port (
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aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
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OutClk : in STD_LOGIC;
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oRst : out STD_LOGIC);
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end ResetBridge;
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architecture Behavioral of ResetBridge is
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signal aRst_int : std_logic;
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attribute KEEP : string;
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attribute KEEP of aRst_int: signal is "TRUE";
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begin
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aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
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SyncAsyncx: entity work.SyncAsync
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generic map (
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kResetTo => kPolarity,
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kStages => 2) --use double FF synchronizer
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port map (
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aReset => aRst_int,
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aIn => not kPolarity,
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OutClk => OutClk,
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oOut => oRst);
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end Behavioral;
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