Sebastian Meyer
200 lines
7.6 KiB
VHDL
200 lines
7.6 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- File: DebugLib.vhd
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-- Author: Elod Gyorgy
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-- Original Project: MIPI CSI-2 Receiver IP
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-- Date: 15 December 2017
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--
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-------------------------------------------------------------------------------
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--MIT License
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--
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--Copyright (c) 2016 Digilent
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--
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--Permission is hereby granted, free of charge, to any person obtaining a copy
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--of this software and associated documentation files (the "Software"), to deal
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--in the Software without restriction, including without limitation the rights
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--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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--copies of the Software, and to permit persons to whom the Software is
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--furnished to do so, subject to the following conditions:
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--
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--The above copyright notice and this permission notice shall be included in all
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--copies or substantial portions of the Software.
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--
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--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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--SOFTWARE.
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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package DebugLib is
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COMPONENT ila_rxclk
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PORT (
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clk : IN STD_LOGIC;
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trig_out : OUT STD_LOGIC;
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trig_out_ack : IN STD_LOGIC;
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probe0 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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probe1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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probe3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
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);
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END COMPONENT ;
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COMPONENT ila_vidclk
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PORT (
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clk : IN STD_LOGIC;
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trig_in : IN STD_LOGIC;
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trig_in_ack : OUT STD_LOGIC;
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probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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probe5 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe12 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe20 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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probe21 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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probe22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe30 : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
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probe31 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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probe32 : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
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probe33 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe34 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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probe35 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
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);
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END COMPONENT ;
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COMPONENT ila_rxclk_lane
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PORT (
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clk : IN STD_LOGIC;
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trig_out : OUT STD_LOGIC;
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trig_out_ack : IN STD_LOGIC;
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probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END COMPONENT ;
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type DebugLMLane_t is record
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rbSkwRdEn : std_logic;
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rbSkwWrEn : std_logic;
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rbSkwFull : std_logic;
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rbActiveHS : std_logic;
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rbSyncHS : std_logic;
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rbValidHS : std_logic;
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rbDataHS : std_logic_vector(7 downto 0);
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end record;
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constant C_M_AXIS_TDATA_WIDTH : natural := 40;
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constant kMaxLaneCount : natural := 4;
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type DebugLMLanes_t is array(0 to kMaxLaneCount - 1) of DebugLMLane_t;
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type DebugLM_t is record
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state : std_logic_vector(2 downto 0);
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rbByteCnt : std_logic_vector(1 downto 0);
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end record;
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type DebugLLP_t is record
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-- LLP CDC FIFO signals, RxByteClkHS domain
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rbRst : std_logic;
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rbOvf : std_logic;
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rbFIFO_Rstn : std_logic;
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-- LLP CDC FIFO signals, video_clk domain
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mRst : std_logic;
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mFIFO_Tvalid : std_logic;
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mFIFO_Tready : std_logic;
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mFIFO_Tlast : std_logic;
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mFIFO_Tdata : std_logic_vector(kMaxLaneCount*8-1 downto 0);
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mFIFO_Tkeep : std_logic_vector(kMaxLaneCount-1 downto 0);
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mIsHeader : std_logic; -- '1' for CSI-2 header
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mECC_En : std_logic; -- Enable signal for ECC processing
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mECC_Ready : std_logic; -- ECC block ready to accept new data
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mECC_Valid : std_logic; -- ECC processing done, output valid
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mECC_Error : std_logic; -- ECC processing done, input had errors
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mWC : std_logic_vector(15 downto 0); --Word Count from header
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mDT : std_logic_vector(5 downto 0); --Data Type from header
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mFlush : std_logic; -- flushes packet from CDC FIFO
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mKeep : std_logic; -- passes flushed packet through
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mWordCount : std_logic_vector(15 downto 0);
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-- Counted, CRC- and header-stripped packet
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mReg_Tvalid : std_logic;
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mReg_Tready : std_logic;
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mReg_Tlast : std_logic;
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mReg_Tuser : std_logic;
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mReg_Tdata : std_logic_vector(kMaxLaneCount*8-1 downto 0);
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mReg_Tkeep : std_logic_vector(kMaxLaneCount-1 downto 0);
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mCRC_Sent : std_logic_vector(15 downto 0); -- Transmitted packet CRC
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mCRC_En : std_logic; -- Enable signal for CRC processing
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mCRC_Rst : std_logic; -- Reset signal for CRC processing
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mCRC_Out : std_logic_vector(15 downto 0); -- Receiver packet CRC
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-- Video-formatted packet written to Line Buffer
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mFmt_Tvalid : std_logic;
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mFmt_Tready : std_logic;
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mFmt_Tlast : std_logic;
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mFmt_Tuser : std_logic;
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mFmt_Tdata : std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
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mFmt_cnt : std_logic_vector(2 downto 0);
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mBufDataCnt : std_logic_vector(10 downto 0);
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end record;
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end package;
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