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This commit is contained in:
Matthias Biermann
2025-02-13 22:55:36 +01:00
parent 49b5702aa4
commit 2fc4a31322
64 changed files with 94639 additions and 113609 deletions
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Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip.bxml
+5 -50
View File
@@ -2,55 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="axi_crc_dma_ip" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739462143"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739462143"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739462143"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739462143"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\axi_crc_dma_ip.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\axi_crc_dma_ip.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="axi_crc_dma_ip_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\axi_crc_dma_ip.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="axi_crc_dma_ip.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\axi_crc_dma_ip.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\axi_crc_dma_ip.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739483262"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1739483262"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739483262"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739483262"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip_ooc.xdc
-11
View File
@@ -1,11 +0,0 @@
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
create_clock -name CLK -period 10 [get_ports CLK]
################################################################################
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/hdl/axi_crc_dma_ip_wrapper.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Thu Feb 13 16:55:43 2025
--Date : Thu Feb 13 21:15:23 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_ip_wrapper.bd
--Design : axi_crc_dma_ip_wrapper
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0.xml
+82 -299
View File
@@ -137,7 +137,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -296,7 +296,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -832,7 +832,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1259,7 +1259,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1397,7 +1397,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1479,101 +1479,6 @@
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_dma</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:74186c0d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>axis_dma</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f89707e9</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 15:57:18 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f89707e9</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f89707e9</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axi_crc_dma_ip_axis_dma_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 15:55:43 UTC 2025</spirit:value>
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<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:74186c0d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axi_crc_dma_ip_axis_dma_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 15:55:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f89707e9</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>CLK</spirit:name>
@@ -1582,8 +1487,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1595,8 +1499,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
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@@ -1608,8 +1511,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1628,8 +1530,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1645,8 +1546,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1662,8 +1562,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -1679,8 +1578,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -1696,8 +1594,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:driver>
@@ -1712,8 +1609,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -1728,8 +1624,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -1745,8 +1640,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -1761,8 +1655,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -1777,8 +1670,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -1794,8 +1686,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -1810,8 +1701,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -1823,8 +1713,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:driver>
@@ -1843,8 +1732,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1860,8 +1748,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:driver>
@@ -1876,8 +1763,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -1892,8 +1778,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1909,8 +1794,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1922,8 +1806,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1935,8 +1818,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:driver>
@@ -1955,8 +1837,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1968,8 +1849,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -1984,8 +1864,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2004,8 +1883,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2021,8 +1899,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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@@ -2038,8 +1915,7 @@
<spirit:wireTypeDefs>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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@@ -2055,8 +1931,7 @@
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@@ -2072,8 +1947,7 @@
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2089,8 +1963,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
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@@ -2106,8 +1979,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2119,8 +1991,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2132,8 +2003,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2152,8 +2022,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2172,8 +2041,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2192,8 +2060,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2208,8 +2075,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2224,8 +2090,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2240,8 +2105,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2260,8 +2124,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2277,8 +2140,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2294,8 +2156,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2311,8 +2172,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2328,8 +2188,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2345,8 +2204,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2362,8 +2220,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2375,8 +2232,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
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@@ -2391,8 +2247,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2411,8 +2266,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2428,8 +2282,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2441,8 +2294,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2461,8 +2313,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2474,8 +2325,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2487,8 +2337,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2507,8 +2356,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2527,8 +2375,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2543,8 +2390,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
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@@ -2560,8 +2406,7 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2576,8 +2421,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2592,8 +2436,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2609,8 +2452,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2622,8 +2464,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
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@@ -2639,8 +2480,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2652,8 +2492,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2665,8 +2504,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2685,8 +2523,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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</spirit:wire>
@@ -2734,60 +2571,6 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>axi_crc_dma_ip_axis_dma_0_0.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_ip_axis_dma_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_ip_axis_dma_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_ip_axis_dma_0_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_ip_axis_dma_0_0_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/axi_crc_dma_ip_axis_dma_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/axi_crc_dma_ip_axis_dma_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axis_dma:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
@@ -2829,7 +2612,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
@@ -2839,7 +2622,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
@@ -2865,7 +2648,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
@@ -2882,7 +2665,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
@@ -2897,18 +2680,18 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0_sim_netlist.v
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Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Thu Feb 13 16:57:17 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt2/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0_stub.v
// Design : axi_crc_dma_ip_axis_dma_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axis_dma,Vivado 2023.1" *)
module axi_crc_dma_ip_axis_dma_0_0(CLK, RESETN, INTERRUPT, initialValue, polynomial,
finalXOR, inOutReflected, S_AXIL_AWADDR, S_AXIL_AWVALID, S_AXIL_AWREADY, S_AXIL_WDATA,
S_AXIL_WVALID, S_AXIL_WREADY, S_AXIL_WSTRB, S_AXIL_BVALID, S_AXIL_BREADY, S_AXIL_BRESP,
S_AXIL_ARADDR, S_AXIL_ARVALID, S_AXIL_ARREADY, S_AXIL_RDATA, S_AXIL_RVALID, S_AXIL_RREADY,
S_AXIL_RRESP, M_AXI_ARREADY, M_AXI_ARVALID, M_AXI_ARADDR, M_AXI_ARID, M_AXI_ARLEN,
M_AXI_ARSIZE, M_AXI_ARBURST, M_AXI_ARPROT, M_AXI_ARCACHE, M_AXI_RREADY, M_AXI_RVALID,
M_AXI_RDATA, M_AXI_RRESP, M_AXI_RID, M_AXI_RLAST, M_AXI_AWREADY, M_AXI_AWVALID, M_AXI_AWADDR,
M_AXI_AWLEN, M_AXI_AWSIZE, M_AXI_AWID, M_AXI_AWBURST, M_AXI_AWPROT, M_AXI_AWCACHE,
M_AXI_WREADY, M_AXI_WVALID, M_AXI_WDATA, M_AXI_WSTRB, M_AXI_WLAST, M_AXI_WID, M_AXI_BREADY,
M_AXI_BVALID, M_AXI_BID, M_AXI_BRESP, S_AXIS_TVALID, S_AXIS_TDATA, S_AXIS_TLAST,
S_AXIS_TREADY, S_AXIS_NUM_AVAIL, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY,
M_AXIS_NUM_FREE)
/* synthesis syn_black_box black_box_pad_pin="RESETN,INTERRUPT,initialValue[31:0],polynomial[31:0],finalXOR[31:0],inOutReflected[1:0],S_AXIL_AWADDR[7:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[7:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARID[0:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[0:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[0:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[31:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[31:0],M_AXI_BRESP[1:0],S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,S_AXIS_NUM_AVAIL[7:0],M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY,M_AXIS_NUM_FREE[7:0]" */
/* synthesis syn_force_seq_prim="CLK" */;
input CLK /* synthesis syn_isclock = 1 */;
input RESETN;
output INTERRUPT;
output [31:0]initialValue;
output [31:0]polynomial;
output [31:0]finalXOR;
output [1:0]inOutReflected;
input [7:0]S_AXIL_AWADDR;
input S_AXIL_AWVALID;
output S_AXIL_AWREADY;
input [31:0]S_AXIL_WDATA;
input S_AXIL_WVALID;
output S_AXIL_WREADY;
input [3:0]S_AXIL_WSTRB;
output S_AXIL_BVALID;
input S_AXIL_BREADY;
output [1:0]S_AXIL_BRESP;
input [7:0]S_AXIL_ARADDR;
input S_AXIL_ARVALID;
output S_AXIL_ARREADY;
output [31:0]S_AXIL_RDATA;
output S_AXIL_RVALID;
input S_AXIL_RREADY;
output [1:0]S_AXIL_RRESP;
input M_AXI_ARREADY;
output M_AXI_ARVALID;
output [31:0]M_AXI_ARADDR;
output [0:0]M_AXI_ARID;
output [3:0]M_AXI_ARLEN;
output [2:0]M_AXI_ARSIZE;
output [1:0]M_AXI_ARBURST;
output [2:0]M_AXI_ARPROT;
output [3:0]M_AXI_ARCACHE;
output M_AXI_RREADY;
input M_AXI_RVALID;
input [31:0]M_AXI_RDATA;
input [1:0]M_AXI_RRESP;
input [0:0]M_AXI_RID;
input M_AXI_RLAST;
input M_AXI_AWREADY;
output M_AXI_AWVALID;
output [31:0]M_AXI_AWADDR;
output [3:0]M_AXI_AWLEN;
output [2:0]M_AXI_AWSIZE;
output [0:0]M_AXI_AWID;
output [1:0]M_AXI_AWBURST;
output [2:0]M_AXI_AWPROT;
output [3:0]M_AXI_AWCACHE;
input M_AXI_WREADY;
output M_AXI_WVALID;
output [31:0]M_AXI_WDATA;
output [3:0]M_AXI_WSTRB;
output M_AXI_WLAST;
output [31:0]M_AXI_WID;
output M_AXI_BREADY;
input M_AXI_BVALID;
input [31:0]M_AXI_BID;
input [1:0]M_AXI_BRESP;
input S_AXIS_TVALID;
input [31:0]S_AXIS_TDATA;
input S_AXIS_TLAST;
output S_AXIS_TREADY;
input [7:0]S_AXIS_NUM_AVAIL;
output M_AXIS_TVALID;
output [31:0]M_AXIS_TDATA;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
input [7:0]M_AXIS_NUM_FREE;
endmodule
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/sim/axi_crc_dma_ip_axis_dma_0_0.vhd
-363
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axis_dma:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_ip_axis_dma_0_0 IS
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
initialValue : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_RREADY : OUT STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END axi_crc_dma_ip_axis_dma_0_0;
ARCHITECTURE axi_crc_dma_ip_axis_dma_0_0_arch OF axi_crc_dma_ip_axis_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_ip_axis_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_dma IS
GENERIC (
DWIDTH : INTEGER;
IDWIDTH : INTEGER;
MAX_BURSTLEN : INTEGER;
FIFO_AWIDTH : INTEGER;
polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
initialValue : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_RREADY : OUT STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT axis_dma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RU" &
"SER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1," &
" RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_dma
GENERIC MAP (
DWIDTH => 32,
IDWIDTH => 1,
MAX_BURSTLEN => 16,
FIFO_AWIDTH => 8,
polynomial_default => X"04C11DB7"
)
PORT MAP (
CLK => CLK,
RESETN => RESETN,
INTERRUPT => INTERRUPT,
initialValue => initialValue,
polynomial => polynomial,
finalXOR => finalXOR,
inOutReflected => inOutReflected,
S_AXIL_AWADDR => S_AXIL_AWADDR,
S_AXIL_AWVALID => S_AXIL_AWVALID,
S_AXIL_AWREADY => S_AXIL_AWREADY,
S_AXIL_WDATA => S_AXIL_WDATA,
S_AXIL_WVALID => S_AXIL_WVALID,
S_AXIL_WREADY => S_AXIL_WREADY,
S_AXIL_WSTRB => S_AXIL_WSTRB,
S_AXIL_BVALID => S_AXIL_BVALID,
S_AXIL_BREADY => S_AXIL_BREADY,
S_AXIL_BRESP => S_AXIL_BRESP,
S_AXIL_ARADDR => S_AXIL_ARADDR,
S_AXIL_ARVALID => S_AXIL_ARVALID,
S_AXIL_ARREADY => S_AXIL_ARREADY,
S_AXIL_RDATA => S_AXIL_RDATA,
S_AXIL_RVALID => S_AXIL_RVALID,
S_AXIL_RREADY => S_AXIL_RREADY,
S_AXIL_RRESP => S_AXIL_RRESP,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_RREADY => M_AXI_RREADY,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RID => M_AXI_RID,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WID => M_AXI_WID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BID => M_AXI_BID,
M_AXI_BRESP => M_AXI_BRESP,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_NUM_AVAIL => S_AXIS_NUM_AVAIL,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_NUM_FREE => M_AXIS_NUM_FREE
);
END axi_crc_dma_ip_axis_dma_0_0_arch;
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/synth/axi_crc_dma_ip_axis_dma_0_0.vhd
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@@ -1,371 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axis_dma:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_ip_axis_dma_0_0 IS
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
initialValue : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_RREADY : OUT STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END axi_crc_dma_ip_axis_dma_0_0;
ARCHITECTURE axi_crc_dma_ip_axis_dma_0_0_arch OF axi_crc_dma_ip_axis_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_ip_axis_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_dma IS
GENERIC (
DWIDTH : INTEGER;
IDWIDTH : INTEGER;
MAX_BURSTLEN : INTEGER;
FIFO_AWIDTH : INTEGER;
polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
initialValue : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_RREADY : OUT STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT axis_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axi_crc_dma_ip_axis_dma_0_0_arch: ARCHITECTURE IS "axis_dma,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_ip_axis_dma_0_0_arch : ARCHITECTURE IS "axi_crc_dma_ip_axis_dma_0_0,axis_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF axi_crc_dma_ip_axis_dma_0_0_arch: ARCHITECTURE IS "axi_crc_dma_ip_axis_dma_0_0,axis_dma,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_dma,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DWIDTH=32,IDWIDTH=1,MAX_BURSTLEN=16,FIFO_AWIDTH=8,polynomial_default=0x04C11DB7}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF axi_crc_dma_ip_axis_dma_0_0_arch: ARCHITECTURE IS "module_ref";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RU" &
"SER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1," &
" RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_ip_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_dma
GENERIC MAP (
DWIDTH => 32,
IDWIDTH => 1,
MAX_BURSTLEN => 16,
FIFO_AWIDTH => 8,
polynomial_default => X"04C11DB7"
)
PORT MAP (
CLK => CLK,
RESETN => RESETN,
INTERRUPT => INTERRUPT,
initialValue => initialValue,
polynomial => polynomial,
finalXOR => finalXOR,
inOutReflected => inOutReflected,
S_AXIL_AWADDR => S_AXIL_AWADDR,
S_AXIL_AWVALID => S_AXIL_AWVALID,
S_AXIL_AWREADY => S_AXIL_AWREADY,
S_AXIL_WDATA => S_AXIL_WDATA,
S_AXIL_WVALID => S_AXIL_WVALID,
S_AXIL_WREADY => S_AXIL_WREADY,
S_AXIL_WSTRB => S_AXIL_WSTRB,
S_AXIL_BVALID => S_AXIL_BVALID,
S_AXIL_BREADY => S_AXIL_BREADY,
S_AXIL_BRESP => S_AXIL_BRESP,
S_AXIL_ARADDR => S_AXIL_ARADDR,
S_AXIL_ARVALID => S_AXIL_ARVALID,
S_AXIL_ARREADY => S_AXIL_ARREADY,
S_AXIL_RDATA => S_AXIL_RDATA,
S_AXIL_RVALID => S_AXIL_RVALID,
S_AXIL_RREADY => S_AXIL_RREADY,
S_AXIL_RRESP => S_AXIL_RRESP,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_RREADY => M_AXI_RREADY,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RID => M_AXI_RID,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WID => M_AXI_WID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BID => M_AXI_BID,
M_AXI_BRESP => M_AXI_BRESP,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_NUM_AVAIL => S_AXIS_NUM_AVAIL,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_NUM_FREE => M_AXIS_NUM_FREE
);
END axi_crc_dma_ip_axis_dma_0_0_arch;
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/sim/axi_crc_dma_ip.vhd
-531
View File
@@ -1,531 +0,0 @@
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Thu Feb 13 16:55:43 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_ip.bd
--Design : axi_crc_dma_ip
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axi_crc_dma_ip is
port (
CLK : in STD_LOGIC;
INTERRUPT : out STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXIL_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_arready : out STD_LOGIC;
S_AXIL_arvalid : in STD_LOGIC;
S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_awready : out STD_LOGIC;
S_AXIL_awvalid : in STD_LOGIC;
S_AXIL_bready : in STD_LOGIC;
S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_bvalid : out STD_LOGIC;
S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_rready : in STD_LOGIC;
S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_rvalid : out STD_LOGIC;
S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_wready : out STD_LOGIC;
S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_wvalid : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of axi_crc_dma_ip : entity is "axi_crc_dma_ip,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axi_crc_dma_ip,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=4,numReposBlks=4,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_clkrst_cnt=3,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of axi_crc_dma_ip : entity is "axi_crc_dma_ip.hwdef";
end axi_crc_dma_ip;
architecture STRUCTURE of axi_crc_dma_ip is
component axi_crc_dma_ip_axis_fifo_0_0 is
port (
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_ip_axis_fifo_0_0;
component axi_crc_dma_ip_axis_fifo_1_0 is
port (
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_ip_axis_fifo_1_0;
component axi_crc_dma_ip_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initialValue : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_ip_axis_crc_0_0;
component axi_crc_dma_ip_axis_dma_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
INTERRUPT : out STD_LOGIC;
initialValue : out STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : out STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARREADY : in STD_LOGIC;
M_AXI_ARVALID : out STD_LOGIC;
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_RREADY : out STD_LOGIC;
M_AXI_RVALID : in STD_LOGIC;
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_RLAST : in STD_LOGIC;
M_AXI_AWREADY : in STD_LOGIC;
M_AXI_AWVALID : out STD_LOGIC;
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WREADY : in STD_LOGIC;
M_AXI_WVALID : out STD_LOGIC;
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WLAST : out STD_LOGIC;
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_BREADY : out STD_LOGIC;
M_AXI_BVALID : in STD_LOGIC;
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_NUM_AVAIL : in STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_ip_axis_dma_0_0;
signal CLK_0_1 : STD_LOGIC;
signal RESETN_0_1 : STD_LOGIC;
signal S_AXIL_0_1_ARADDR : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S_AXIL_0_1_ARREADY : STD_LOGIC;
signal S_AXIL_0_1_ARVALID : STD_LOGIC;
signal S_AXIL_0_1_AWADDR : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S_AXIL_0_1_AWREADY : STD_LOGIC;
signal S_AXIL_0_1_AWVALID : STD_LOGIC;
signal S_AXIL_0_1_BREADY : STD_LOGIC;
signal S_AXIL_0_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXIL_0_1_BVALID : STD_LOGIC;
signal S_AXIL_0_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXIL_0_1_RREADY : STD_LOGIC;
signal S_AXIL_0_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXIL_0_1_RVALID : STD_LOGIC;
signal S_AXIL_0_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXIL_0_1_WREADY : STD_LOGIC;
signal S_AXIL_0_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXIL_0_1_WVALID : STD_LOGIC;
signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_dma_0_INTERRUPT : STD_LOGIC;
signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axis_dma_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axis_dma_0_M_AXI_ARREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axis_dma_0_M_AXI_ARVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axis_dma_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axis_dma_0_M_AXI_AWREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axis_dma_0_M_AXI_AWVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_BID : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_BREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_M_AXI_BVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axis_dma_0_M_AXI_RLAST : STD_LOGIC;
signal axis_dma_0_M_AXI_RREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_M_AXI_RVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_WLAST : STD_LOGIC;
signal axis_dma_0_M_AXI_WREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_WVALID : STD_LOGIC;
signal axis_dma_0_finalXOR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_inOutReflected : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_initialValue : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_fifo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_fifo_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_fifo_0_S_NUM_FREE : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axis_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_1_M_AXIS_TLAST : STD_LOGIC;
signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC;
signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC;
signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of CLK : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of CLK : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF S_AXIL:M_AXI, ASSOCIATED_RESET RESETN, CLK_DOMAIN axi_crc_dma_ip_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_INFO of INTERRUPT : signal is "xilinx.com:signal:interrupt:1.0 INTR.INTERRUPT INTERRUPT";
attribute X_INTERFACE_PARAMETER of INTERRUPT : signal is "XIL_INTERFACENAME INTR.INTERRUPT, PortWidth 1, SENSITIVITY LEVEL_HIGH";
attribute X_INTERFACE_INFO of M_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
attribute X_INTERFACE_INFO of M_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
attribute X_INTERFACE_INFO of M_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
attribute X_INTERFACE_INFO of M_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
attribute X_INTERFACE_INFO of M_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
attribute X_INTERFACE_INFO of M_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
attribute X_INTERFACE_INFO of M_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
attribute X_INTERFACE_INFO of M_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
attribute X_INTERFACE_INFO of M_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
attribute X_INTERFACE_INFO of M_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
attribute X_INTERFACE_INFO of M_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
attribute X_INTERFACE_INFO of M_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
attribute X_INTERFACE_INFO of RESETN : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST";
attribute X_INTERFACE_PARAMETER of RESETN : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of S_AXIL_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
attribute X_INTERFACE_INFO of S_AXIL_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
attribute X_INTERFACE_INFO of S_AXIL_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
attribute X_INTERFACE_INFO of S_AXIL_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
attribute X_INTERFACE_INFO of S_AXIL_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
attribute X_INTERFACE_INFO of S_AXIL_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
attribute X_INTERFACE_INFO of S_AXIL_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
attribute X_INTERFACE_INFO of S_AXIL_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
attribute X_INTERFACE_INFO of S_AXIL_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
attribute X_INTERFACE_INFO of S_AXIL_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
attribute X_INTERFACE_INFO of M_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of M_AXI_araddr : signal is "XIL_INTERFACENAME M_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_ip_CLK, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of M_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
attribute X_INTERFACE_INFO of M_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARID";
attribute X_INTERFACE_INFO of M_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
attribute X_INTERFACE_INFO of M_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
attribute X_INTERFACE_INFO of M_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
attribute X_INTERFACE_INFO of M_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
attribute X_INTERFACE_INFO of M_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWID";
attribute X_INTERFACE_INFO of M_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
attribute X_INTERFACE_INFO of M_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
attribute X_INTERFACE_INFO of M_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BID";
attribute X_INTERFACE_INFO of M_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
attribute X_INTERFACE_INFO of M_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
attribute X_INTERFACE_INFO of M_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RID";
attribute X_INTERFACE_INFO of M_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
attribute X_INTERFACE_INFO of M_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
attribute X_INTERFACE_INFO of M_AXI_wid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WID";
attribute X_INTERFACE_INFO of M_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
attribute X_INTERFACE_INFO of S_AXIL_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
attribute X_INTERFACE_PARAMETER of S_AXIL_araddr : signal is "XIL_INTERFACENAME S_AXIL, ADDR_WIDTH 16, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_ip_CLK, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of S_AXIL_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
attribute X_INTERFACE_INFO of S_AXIL_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
attribute X_INTERFACE_INFO of S_AXIL_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
attribute X_INTERFACE_INFO of S_AXIL_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
attribute X_INTERFACE_INFO of S_AXIL_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
attribute X_INTERFACE_INFO of S_AXIL_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
begin
CLK_0_1 <= CLK;
INTERRUPT <= axis_dma_0_INTERRUPT;
M_AXI_araddr(31 downto 0) <= axis_dma_0_M_AXI_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= axis_dma_0_M_AXI_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= axis_dma_0_M_AXI_ARCACHE(3 downto 0);
M_AXI_arid(0) <= axis_dma_0_M_AXI_ARID(0);
M_AXI_arlen(3 downto 0) <= axis_dma_0_M_AXI_ARLEN(3 downto 0);
M_AXI_arprot(2 downto 0) <= axis_dma_0_M_AXI_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= axis_dma_0_M_AXI_ARSIZE(2 downto 0);
M_AXI_arvalid <= axis_dma_0_M_AXI_ARVALID;
M_AXI_awaddr(31 downto 0) <= axis_dma_0_M_AXI_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= axis_dma_0_M_AXI_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= axis_dma_0_M_AXI_AWCACHE(3 downto 0);
M_AXI_awid(0) <= axis_dma_0_M_AXI_AWID(0);
M_AXI_awlen(3 downto 0) <= axis_dma_0_M_AXI_AWLEN(3 downto 0);
M_AXI_awprot(2 downto 0) <= axis_dma_0_M_AXI_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= axis_dma_0_M_AXI_AWSIZE(2 downto 0);
M_AXI_awvalid <= axis_dma_0_M_AXI_AWVALID;
M_AXI_bready <= axis_dma_0_M_AXI_BREADY;
M_AXI_rready <= axis_dma_0_M_AXI_RREADY;
M_AXI_wdata(31 downto 0) <= axis_dma_0_M_AXI_WDATA(31 downto 0);
M_AXI_wid(31 downto 0) <= axis_dma_0_M_AXI_WID(31 downto 0);
M_AXI_wlast <= axis_dma_0_M_AXI_WLAST;
M_AXI_wstrb(3 downto 0) <= axis_dma_0_M_AXI_WSTRB(3 downto 0);
M_AXI_wvalid <= axis_dma_0_M_AXI_WVALID;
RESETN_0_1 <= RESETN;
S_AXIL_0_1_ARADDR(7 downto 0) <= S_AXIL_araddr(7 downto 0);
S_AXIL_0_1_ARVALID <= S_AXIL_arvalid;
S_AXIL_0_1_AWADDR(7 downto 0) <= S_AXIL_awaddr(7 downto 0);
S_AXIL_0_1_AWVALID <= S_AXIL_awvalid;
S_AXIL_0_1_BREADY <= S_AXIL_bready;
S_AXIL_0_1_RREADY <= S_AXIL_rready;
S_AXIL_0_1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0);
S_AXIL_0_1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0);
S_AXIL_0_1_WVALID <= S_AXIL_wvalid;
S_AXIL_arready <= S_AXIL_0_1_ARREADY;
S_AXIL_awready <= S_AXIL_0_1_AWREADY;
S_AXIL_bresp(1 downto 0) <= S_AXIL_0_1_BRESP(1 downto 0);
S_AXIL_bvalid <= S_AXIL_0_1_BVALID;
S_AXIL_rdata(31 downto 0) <= S_AXIL_0_1_RDATA(31 downto 0);
S_AXIL_rresp(1 downto 0) <= S_AXIL_0_1_RRESP(1 downto 0);
S_AXIL_rvalid <= S_AXIL_0_1_RVALID;
S_AXIL_wready <= S_AXIL_0_1_WREADY;
axis_dma_0_M_AXI_ARREADY <= M_AXI_arready;
axis_dma_0_M_AXI_AWREADY <= M_AXI_awready;
axis_dma_0_M_AXI_BID(31 downto 0) <= M_AXI_bid(31 downto 0);
axis_dma_0_M_AXI_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
axis_dma_0_M_AXI_BVALID <= M_AXI_bvalid;
axis_dma_0_M_AXI_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
axis_dma_0_M_AXI_RID(0) <= M_AXI_rid(0);
axis_dma_0_M_AXI_RLAST <= M_AXI_rlast;
axis_dma_0_M_AXI_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
axis_dma_0_M_AXI_RVALID <= M_AXI_rvalid;
axis_dma_0_M_AXI_WREADY <= M_AXI_wready;
axis_crc_0: component axi_crc_dma_ip_axis_crc_0_0
port map (
CLK => CLK_0_1,
M_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
RESETN => RESETN_0_1,
S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
initialValue(31 downto 0) => axis_dma_0_initialValue(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_dma_0: component axi_crc_dma_ip_axis_dma_0_0
port map (
CLK => CLK_0_1,
INTERRUPT => axis_dma_0_INTERRUPT,
M_AXIS_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0),
M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
M_AXI_ARADDR(31 downto 0) => axis_dma_0_M_AXI_ARADDR(31 downto 0),
M_AXI_ARBURST(1 downto 0) => axis_dma_0_M_AXI_ARBURST(1 downto 0),
M_AXI_ARCACHE(3 downto 0) => axis_dma_0_M_AXI_ARCACHE(3 downto 0),
M_AXI_ARID(0) => axis_dma_0_M_AXI_ARID(0),
M_AXI_ARLEN(3 downto 0) => axis_dma_0_M_AXI_ARLEN(3 downto 0),
M_AXI_ARPROT(2 downto 0) => axis_dma_0_M_AXI_ARPROT(2 downto 0),
M_AXI_ARREADY => axis_dma_0_M_AXI_ARREADY,
M_AXI_ARSIZE(2 downto 0) => axis_dma_0_M_AXI_ARSIZE(2 downto 0),
M_AXI_ARVALID => axis_dma_0_M_AXI_ARVALID,
M_AXI_AWADDR(31 downto 0) => axis_dma_0_M_AXI_AWADDR(31 downto 0),
M_AXI_AWBURST(1 downto 0) => axis_dma_0_M_AXI_AWBURST(1 downto 0),
M_AXI_AWCACHE(3 downto 0) => axis_dma_0_M_AXI_AWCACHE(3 downto 0),
M_AXI_AWID(0) => axis_dma_0_M_AXI_AWID(0),
M_AXI_AWLEN(3 downto 0) => axis_dma_0_M_AXI_AWLEN(3 downto 0),
M_AXI_AWPROT(2 downto 0) => axis_dma_0_M_AXI_AWPROT(2 downto 0),
M_AXI_AWREADY => axis_dma_0_M_AXI_AWREADY,
M_AXI_AWSIZE(2 downto 0) => axis_dma_0_M_AXI_AWSIZE(2 downto 0),
M_AXI_AWVALID => axis_dma_0_M_AXI_AWVALID,
M_AXI_BID(31 downto 0) => axis_dma_0_M_AXI_BID(31 downto 0),
M_AXI_BREADY => axis_dma_0_M_AXI_BREADY,
M_AXI_BRESP(1 downto 0) => axis_dma_0_M_AXI_BRESP(1 downto 0),
M_AXI_BVALID => axis_dma_0_M_AXI_BVALID,
M_AXI_RDATA(31 downto 0) => axis_dma_0_M_AXI_RDATA(31 downto 0),
M_AXI_RID(0) => axis_dma_0_M_AXI_RID(0),
M_AXI_RLAST => axis_dma_0_M_AXI_RLAST,
M_AXI_RREADY => axis_dma_0_M_AXI_RREADY,
M_AXI_RRESP(1 downto 0) => axis_dma_0_M_AXI_RRESP(1 downto 0),
M_AXI_RVALID => axis_dma_0_M_AXI_RVALID,
M_AXI_WDATA(31 downto 0) => axis_dma_0_M_AXI_WDATA(31 downto 0),
M_AXI_WID(31 downto 0) => axis_dma_0_M_AXI_WID(31 downto 0),
M_AXI_WLAST => axis_dma_0_M_AXI_WLAST,
M_AXI_WREADY => axis_dma_0_M_AXI_WREADY,
M_AXI_WSTRB(3 downto 0) => axis_dma_0_M_AXI_WSTRB(3 downto 0),
M_AXI_WVALID => axis_dma_0_M_AXI_WVALID,
RESETN => RESETN_0_1,
S_AXIL_ARADDR(7 downto 0) => S_AXIL_0_1_ARADDR(7 downto 0),
S_AXIL_ARREADY => S_AXIL_0_1_ARREADY,
S_AXIL_ARVALID => S_AXIL_0_1_ARVALID,
S_AXIL_AWADDR(7 downto 0) => S_AXIL_0_1_AWADDR(7 downto 0),
S_AXIL_AWREADY => S_AXIL_0_1_AWREADY,
S_AXIL_AWVALID => S_AXIL_0_1_AWVALID,
S_AXIL_BREADY => S_AXIL_0_1_BREADY,
S_AXIL_BRESP(1 downto 0) => S_AXIL_0_1_BRESP(1 downto 0),
S_AXIL_BVALID => S_AXIL_0_1_BVALID,
S_AXIL_RDATA(31 downto 0) => S_AXIL_0_1_RDATA(31 downto 0),
S_AXIL_RREADY => S_AXIL_0_1_RREADY,
S_AXIL_RRESP(1 downto 0) => S_AXIL_0_1_RRESP(1 downto 0),
S_AXIL_RVALID => S_AXIL_0_1_RVALID,
S_AXIL_WDATA(31 downto 0) => S_AXIL_0_1_WDATA(31 downto 0),
S_AXIL_WREADY => S_AXIL_0_1_WREADY,
S_AXIL_WSTRB(3 downto 0) => S_AXIL_0_1_WSTRB(3 downto 0),
S_AXIL_WVALID => S_AXIL_0_1_WVALID,
S_AXIS_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
S_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
S_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
initialValue(31 downto 0) => axis_dma_0_initialValue(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_fifo_0: component axi_crc_dma_ip_axis_fifo_0_0
port map (
M_AXIS_ACLK => CLK_0_1,
M_AXIS_ARESETN => RESETN_0_1,
M_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
M_NUM_AVAIL(7 downto 0) => NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED(7 downto 0),
S_AXIS_ACLK => CLK_0_1,
S_AXIS_ARESETN => RESETN_0_1,
S_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
S_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0)
);
axis_fifo_1: component axi_crc_dma_ip_axis_fifo_1_0
port map (
M_AXIS_ACLK => CLK_0_1,
M_AXIS_ARESETN => RESETN_0_1,
M_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
M_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
S_AXIS_ACLK => CLK_0_1,
S_AXIS_ARESETN => RESETN_0_1,
S_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0)
);
end STRUCTURE;
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/synth/axi_crc_dma_ip.vhd
-531
View File
@@ -1,531 +0,0 @@
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Thu Feb 13 16:55:43 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_ip.bd
--Design : axi_crc_dma_ip
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axi_crc_dma_ip is
port (
CLK : in STD_LOGIC;
INTERRUPT : out STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXIL_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_arready : out STD_LOGIC;
S_AXIL_arvalid : in STD_LOGIC;
S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_awready : out STD_LOGIC;
S_AXIL_awvalid : in STD_LOGIC;
S_AXIL_bready : in STD_LOGIC;
S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_bvalid : out STD_LOGIC;
S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_rready : in STD_LOGIC;
S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_rvalid : out STD_LOGIC;
S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_wready : out STD_LOGIC;
S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_wvalid : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of axi_crc_dma_ip : entity is "axi_crc_dma_ip,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axi_crc_dma_ip,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=4,numReposBlks=4,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_clkrst_cnt=3,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of axi_crc_dma_ip : entity is "axi_crc_dma_ip.hwdef";
end axi_crc_dma_ip;
architecture STRUCTURE of axi_crc_dma_ip is
component axi_crc_dma_ip_axis_fifo_0_0 is
port (
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_ip_axis_fifo_0_0;
component axi_crc_dma_ip_axis_fifo_1_0 is
port (
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_ip_axis_fifo_1_0;
component axi_crc_dma_ip_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initialValue : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_ip_axis_crc_0_0;
component axi_crc_dma_ip_axis_dma_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
INTERRUPT : out STD_LOGIC;
initialValue : out STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : out STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARREADY : in STD_LOGIC;
M_AXI_ARVALID : out STD_LOGIC;
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_RREADY : out STD_LOGIC;
M_AXI_RVALID : in STD_LOGIC;
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_RLAST : in STD_LOGIC;
M_AXI_AWREADY : in STD_LOGIC;
M_AXI_AWVALID : out STD_LOGIC;
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WREADY : in STD_LOGIC;
M_AXI_WVALID : out STD_LOGIC;
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WLAST : out STD_LOGIC;
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_BREADY : out STD_LOGIC;
M_AXI_BVALID : in STD_LOGIC;
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_NUM_AVAIL : in STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_ip_axis_dma_0_0;
signal CLK_0_1 : STD_LOGIC;
signal RESETN_0_1 : STD_LOGIC;
signal S_AXIL_0_1_ARADDR : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S_AXIL_0_1_ARREADY : STD_LOGIC;
signal S_AXIL_0_1_ARVALID : STD_LOGIC;
signal S_AXIL_0_1_AWADDR : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S_AXIL_0_1_AWREADY : STD_LOGIC;
signal S_AXIL_0_1_AWVALID : STD_LOGIC;
signal S_AXIL_0_1_BREADY : STD_LOGIC;
signal S_AXIL_0_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXIL_0_1_BVALID : STD_LOGIC;
signal S_AXIL_0_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXIL_0_1_RREADY : STD_LOGIC;
signal S_AXIL_0_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXIL_0_1_RVALID : STD_LOGIC;
signal S_AXIL_0_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXIL_0_1_WREADY : STD_LOGIC;
signal S_AXIL_0_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXIL_0_1_WVALID : STD_LOGIC;
signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_dma_0_INTERRUPT : STD_LOGIC;
signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axis_dma_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axis_dma_0_M_AXI_ARREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axis_dma_0_M_AXI_ARVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axis_dma_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axis_dma_0_M_AXI_AWREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axis_dma_0_M_AXI_AWVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_BID : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_BREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_M_AXI_BVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axis_dma_0_M_AXI_RLAST : STD_LOGIC;
signal axis_dma_0_M_AXI_RREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_M_AXI_RVALID : STD_LOGIC;
signal axis_dma_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXI_WLAST : STD_LOGIC;
signal axis_dma_0_M_AXI_WREADY : STD_LOGIC;
signal axis_dma_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_dma_0_M_AXI_WVALID : STD_LOGIC;
signal axis_dma_0_finalXOR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_inOutReflected : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axis_dma_0_initialValue : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_fifo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_fifo_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_fifo_0_S_NUM_FREE : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axis_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_1_M_AXIS_TLAST : STD_LOGIC;
signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC;
signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC;
signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of CLK : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of CLK : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF S_AXIL:M_AXI, ASSOCIATED_RESET RESETN, CLK_DOMAIN axi_crc_dma_ip_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_INFO of INTERRUPT : signal is "xilinx.com:signal:interrupt:1.0 INTR.INTERRUPT INTERRUPT";
attribute X_INTERFACE_PARAMETER of INTERRUPT : signal is "XIL_INTERFACENAME INTR.INTERRUPT, PortWidth 1, SENSITIVITY LEVEL_HIGH";
attribute X_INTERFACE_INFO of M_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
attribute X_INTERFACE_INFO of M_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
attribute X_INTERFACE_INFO of M_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
attribute X_INTERFACE_INFO of M_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
attribute X_INTERFACE_INFO of M_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
attribute X_INTERFACE_INFO of M_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
attribute X_INTERFACE_INFO of M_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
attribute X_INTERFACE_INFO of M_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
attribute X_INTERFACE_INFO of M_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
attribute X_INTERFACE_INFO of M_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
attribute X_INTERFACE_INFO of M_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
attribute X_INTERFACE_INFO of M_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
attribute X_INTERFACE_INFO of RESETN : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST";
attribute X_INTERFACE_PARAMETER of RESETN : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of S_AXIL_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
attribute X_INTERFACE_INFO of S_AXIL_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
attribute X_INTERFACE_INFO of S_AXIL_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
attribute X_INTERFACE_INFO of S_AXIL_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
attribute X_INTERFACE_INFO of S_AXIL_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
attribute X_INTERFACE_INFO of S_AXIL_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
attribute X_INTERFACE_INFO of S_AXIL_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
attribute X_INTERFACE_INFO of S_AXIL_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
attribute X_INTERFACE_INFO of S_AXIL_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
attribute X_INTERFACE_INFO of S_AXIL_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
attribute X_INTERFACE_INFO of M_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of M_AXI_araddr : signal is "XIL_INTERFACENAME M_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_ip_CLK, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of M_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
attribute X_INTERFACE_INFO of M_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARID";
attribute X_INTERFACE_INFO of M_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
attribute X_INTERFACE_INFO of M_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
attribute X_INTERFACE_INFO of M_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
attribute X_INTERFACE_INFO of M_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
attribute X_INTERFACE_INFO of M_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWID";
attribute X_INTERFACE_INFO of M_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
attribute X_INTERFACE_INFO of M_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
attribute X_INTERFACE_INFO of M_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BID";
attribute X_INTERFACE_INFO of M_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
attribute X_INTERFACE_INFO of M_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
attribute X_INTERFACE_INFO of M_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RID";
attribute X_INTERFACE_INFO of M_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
attribute X_INTERFACE_INFO of M_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
attribute X_INTERFACE_INFO of M_AXI_wid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WID";
attribute X_INTERFACE_INFO of M_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
attribute X_INTERFACE_INFO of S_AXIL_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
attribute X_INTERFACE_PARAMETER of S_AXIL_araddr : signal is "XIL_INTERFACENAME S_AXIL, ADDR_WIDTH 16, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_ip_CLK, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of S_AXIL_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
attribute X_INTERFACE_INFO of S_AXIL_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
attribute X_INTERFACE_INFO of S_AXIL_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
attribute X_INTERFACE_INFO of S_AXIL_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
attribute X_INTERFACE_INFO of S_AXIL_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
attribute X_INTERFACE_INFO of S_AXIL_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
begin
CLK_0_1 <= CLK;
INTERRUPT <= axis_dma_0_INTERRUPT;
M_AXI_araddr(31 downto 0) <= axis_dma_0_M_AXI_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= axis_dma_0_M_AXI_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= axis_dma_0_M_AXI_ARCACHE(3 downto 0);
M_AXI_arid(0) <= axis_dma_0_M_AXI_ARID(0);
M_AXI_arlen(3 downto 0) <= axis_dma_0_M_AXI_ARLEN(3 downto 0);
M_AXI_arprot(2 downto 0) <= axis_dma_0_M_AXI_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= axis_dma_0_M_AXI_ARSIZE(2 downto 0);
M_AXI_arvalid <= axis_dma_0_M_AXI_ARVALID;
M_AXI_awaddr(31 downto 0) <= axis_dma_0_M_AXI_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= axis_dma_0_M_AXI_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= axis_dma_0_M_AXI_AWCACHE(3 downto 0);
M_AXI_awid(0) <= axis_dma_0_M_AXI_AWID(0);
M_AXI_awlen(3 downto 0) <= axis_dma_0_M_AXI_AWLEN(3 downto 0);
M_AXI_awprot(2 downto 0) <= axis_dma_0_M_AXI_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= axis_dma_0_M_AXI_AWSIZE(2 downto 0);
M_AXI_awvalid <= axis_dma_0_M_AXI_AWVALID;
M_AXI_bready <= axis_dma_0_M_AXI_BREADY;
M_AXI_rready <= axis_dma_0_M_AXI_RREADY;
M_AXI_wdata(31 downto 0) <= axis_dma_0_M_AXI_WDATA(31 downto 0);
M_AXI_wid(31 downto 0) <= axis_dma_0_M_AXI_WID(31 downto 0);
M_AXI_wlast <= axis_dma_0_M_AXI_WLAST;
M_AXI_wstrb(3 downto 0) <= axis_dma_0_M_AXI_WSTRB(3 downto 0);
M_AXI_wvalid <= axis_dma_0_M_AXI_WVALID;
RESETN_0_1 <= RESETN;
S_AXIL_0_1_ARADDR(7 downto 0) <= S_AXIL_araddr(7 downto 0);
S_AXIL_0_1_ARVALID <= S_AXIL_arvalid;
S_AXIL_0_1_AWADDR(7 downto 0) <= S_AXIL_awaddr(7 downto 0);
S_AXIL_0_1_AWVALID <= S_AXIL_awvalid;
S_AXIL_0_1_BREADY <= S_AXIL_bready;
S_AXIL_0_1_RREADY <= S_AXIL_rready;
S_AXIL_0_1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0);
S_AXIL_0_1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0);
S_AXIL_0_1_WVALID <= S_AXIL_wvalid;
S_AXIL_arready <= S_AXIL_0_1_ARREADY;
S_AXIL_awready <= S_AXIL_0_1_AWREADY;
S_AXIL_bresp(1 downto 0) <= S_AXIL_0_1_BRESP(1 downto 0);
S_AXIL_bvalid <= S_AXIL_0_1_BVALID;
S_AXIL_rdata(31 downto 0) <= S_AXIL_0_1_RDATA(31 downto 0);
S_AXIL_rresp(1 downto 0) <= S_AXIL_0_1_RRESP(1 downto 0);
S_AXIL_rvalid <= S_AXIL_0_1_RVALID;
S_AXIL_wready <= S_AXIL_0_1_WREADY;
axis_dma_0_M_AXI_ARREADY <= M_AXI_arready;
axis_dma_0_M_AXI_AWREADY <= M_AXI_awready;
axis_dma_0_M_AXI_BID(31 downto 0) <= M_AXI_bid(31 downto 0);
axis_dma_0_M_AXI_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
axis_dma_0_M_AXI_BVALID <= M_AXI_bvalid;
axis_dma_0_M_AXI_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
axis_dma_0_M_AXI_RID(0) <= M_AXI_rid(0);
axis_dma_0_M_AXI_RLAST <= M_AXI_rlast;
axis_dma_0_M_AXI_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
axis_dma_0_M_AXI_RVALID <= M_AXI_rvalid;
axis_dma_0_M_AXI_WREADY <= M_AXI_wready;
axis_crc_0: component axi_crc_dma_ip_axis_crc_0_0
port map (
CLK => CLK_0_1,
M_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
RESETN => RESETN_0_1,
S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
initialValue(31 downto 0) => axis_dma_0_initialValue(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_dma_0: component axi_crc_dma_ip_axis_dma_0_0
port map (
CLK => CLK_0_1,
INTERRUPT => axis_dma_0_INTERRUPT,
M_AXIS_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0),
M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
M_AXI_ARADDR(31 downto 0) => axis_dma_0_M_AXI_ARADDR(31 downto 0),
M_AXI_ARBURST(1 downto 0) => axis_dma_0_M_AXI_ARBURST(1 downto 0),
M_AXI_ARCACHE(3 downto 0) => axis_dma_0_M_AXI_ARCACHE(3 downto 0),
M_AXI_ARID(0) => axis_dma_0_M_AXI_ARID(0),
M_AXI_ARLEN(3 downto 0) => axis_dma_0_M_AXI_ARLEN(3 downto 0),
M_AXI_ARPROT(2 downto 0) => axis_dma_0_M_AXI_ARPROT(2 downto 0),
M_AXI_ARREADY => axis_dma_0_M_AXI_ARREADY,
M_AXI_ARSIZE(2 downto 0) => axis_dma_0_M_AXI_ARSIZE(2 downto 0),
M_AXI_ARVALID => axis_dma_0_M_AXI_ARVALID,
M_AXI_AWADDR(31 downto 0) => axis_dma_0_M_AXI_AWADDR(31 downto 0),
M_AXI_AWBURST(1 downto 0) => axis_dma_0_M_AXI_AWBURST(1 downto 0),
M_AXI_AWCACHE(3 downto 0) => axis_dma_0_M_AXI_AWCACHE(3 downto 0),
M_AXI_AWID(0) => axis_dma_0_M_AXI_AWID(0),
M_AXI_AWLEN(3 downto 0) => axis_dma_0_M_AXI_AWLEN(3 downto 0),
M_AXI_AWPROT(2 downto 0) => axis_dma_0_M_AXI_AWPROT(2 downto 0),
M_AXI_AWREADY => axis_dma_0_M_AXI_AWREADY,
M_AXI_AWSIZE(2 downto 0) => axis_dma_0_M_AXI_AWSIZE(2 downto 0),
M_AXI_AWVALID => axis_dma_0_M_AXI_AWVALID,
M_AXI_BID(31 downto 0) => axis_dma_0_M_AXI_BID(31 downto 0),
M_AXI_BREADY => axis_dma_0_M_AXI_BREADY,
M_AXI_BRESP(1 downto 0) => axis_dma_0_M_AXI_BRESP(1 downto 0),
M_AXI_BVALID => axis_dma_0_M_AXI_BVALID,
M_AXI_RDATA(31 downto 0) => axis_dma_0_M_AXI_RDATA(31 downto 0),
M_AXI_RID(0) => axis_dma_0_M_AXI_RID(0),
M_AXI_RLAST => axis_dma_0_M_AXI_RLAST,
M_AXI_RREADY => axis_dma_0_M_AXI_RREADY,
M_AXI_RRESP(1 downto 0) => axis_dma_0_M_AXI_RRESP(1 downto 0),
M_AXI_RVALID => axis_dma_0_M_AXI_RVALID,
M_AXI_WDATA(31 downto 0) => axis_dma_0_M_AXI_WDATA(31 downto 0),
M_AXI_WID(31 downto 0) => axis_dma_0_M_AXI_WID(31 downto 0),
M_AXI_WLAST => axis_dma_0_M_AXI_WLAST,
M_AXI_WREADY => axis_dma_0_M_AXI_WREADY,
M_AXI_WSTRB(3 downto 0) => axis_dma_0_M_AXI_WSTRB(3 downto 0),
M_AXI_WVALID => axis_dma_0_M_AXI_WVALID,
RESETN => RESETN_0_1,
S_AXIL_ARADDR(7 downto 0) => S_AXIL_0_1_ARADDR(7 downto 0),
S_AXIL_ARREADY => S_AXIL_0_1_ARREADY,
S_AXIL_ARVALID => S_AXIL_0_1_ARVALID,
S_AXIL_AWADDR(7 downto 0) => S_AXIL_0_1_AWADDR(7 downto 0),
S_AXIL_AWREADY => S_AXIL_0_1_AWREADY,
S_AXIL_AWVALID => S_AXIL_0_1_AWVALID,
S_AXIL_BREADY => S_AXIL_0_1_BREADY,
S_AXIL_BRESP(1 downto 0) => S_AXIL_0_1_BRESP(1 downto 0),
S_AXIL_BVALID => S_AXIL_0_1_BVALID,
S_AXIL_RDATA(31 downto 0) => S_AXIL_0_1_RDATA(31 downto 0),
S_AXIL_RREADY => S_AXIL_0_1_RREADY,
S_AXIL_RRESP(1 downto 0) => S_AXIL_0_1_RRESP(1 downto 0),
S_AXIL_RVALID => S_AXIL_0_1_RVALID,
S_AXIL_WDATA(31 downto 0) => S_AXIL_0_1_WDATA(31 downto 0),
S_AXIL_WREADY => S_AXIL_0_1_WREADY,
S_AXIL_WSTRB(3 downto 0) => S_AXIL_0_1_WSTRB(3 downto 0),
S_AXIL_WVALID => S_AXIL_0_1_WVALID,
S_AXIS_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
S_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
S_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
initialValue(31 downto 0) => axis_dma_0_initialValue(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_fifo_0: component axi_crc_dma_ip_axis_fifo_0_0
port map (
M_AXIS_ACLK => CLK_0_1,
M_AXIS_ARESETN => RESETN_0_1,
M_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
M_NUM_AVAIL(7 downto 0) => NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED(7 downto 0),
S_AXIS_ACLK => CLK_0_1,
S_AXIS_ARESETN => RESETN_0_1,
S_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
S_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0)
);
axis_fifo_1: component axi_crc_dma_ip_axis_fifo_1_0
port map (
M_AXIS_ACLK => CLK_0_1,
M_AXIS_ARESETN => RESETN_0_1,
M_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
M_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
S_AXIS_ACLK => CLK_0_1,
S_AXIS_ARESETN => RESETN_0_1,
S_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0)
);
end STRUCTURE;
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml
+4 -4
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="axi_crc_dma_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739462406"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1739462406"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739462406"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739462406"/>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739483251"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1739483251"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739483251"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739483251"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Wed Feb 12 16:51:05 2025
--Date : Thu Feb 13 21:15:27 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_sim_1_wrapper.bd
--Design : axi_crc_dma_sim_1_wrapper
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml
+5 -5
View File
@@ -581,7 +581,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d5936c15</spirit:value>
<spirit:value>9:ba16d456</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -597,11 +597,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Feb 12 13:14:31 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:15:28 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d5936c15</spirit:value>
<spirit:value>9:ba16d456</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -983,7 +983,7 @@
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>REVISION_NO</spirit:name>
<spirit:displayName>Revision No</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REVISION_NO">26</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REVISION_NO">31</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
@@ -1039,7 +1039,7 @@
<spirit:parameter>
<spirit:name>REVISION_NO</spirit:name>
<spirit:displayName>Revision No</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.REVISION_NO">26</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.REVISION_NO">31</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd
+1 -1
View File
@@ -149,7 +149,7 @@ BEGIN
STIM_FILENAME => "../../axi_crc_dma_sim.mem",
HAS_FINISHED_OUT => false,
HAS_INTERRUPT_IN => true,
REVISION_NO => 26
REVISION_NO => 31
)
PORT MAP (
interrupt_in => interrupt_in,
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml
+5 -50
View File
@@ -2,55 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="axi_crc_dma_syn_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739462525"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739462525"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739462525"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739462525"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\axi_crc_dma_syn_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\axi_crc_dma_syn_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="axi_crc_dma_syn_1_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\axi_crc_dma_syn_1.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="axi_crc_dma_syn_1.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\axi_crc_dma_syn_1.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\axi_crc_dma_syn_1.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739483257"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1739483257"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739483257"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739483257"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1_ooc.xdc
-14
View File
@@ -1,14 +0,0 @@
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 10 [get_pins PS/processing_system7_0/FCLK_CLK0]
create_clock -name PS_processing_system7_0_FCLK_CLK1 -period 8 [get_pins PS/processing_system7_0/FCLK_CLK1]
create_clock -name PS_processing_system7_0_FCLK_CLK2 -period 5 [get_pins PS/processing_system7_0/FCLK_CLK2]
create_clock -name PS_processing_system7_0_FCLK_CLK3 -period 15 [get_pins PS/processing_system7_0/FCLK_CLK3]
################################################################################
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/hdl/axi_crc_dma_syn_1_wrapper.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Thu Feb 13 17:01:58 2025
--Date : Thu Feb 13 21:21:56 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_syn_1_wrapper.bd
--Design : axi_crc_dma_syn_1_wrapper
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml
+8 -8
View File
@@ -1500,7 +1500,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:05 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:11 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1518,7 +1518,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1538,7 +1538,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1566,7 +1566,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1605,7 +1605,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1625,7 +1625,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1663,7 +1663,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1683,7 +1683,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml
+9 -9
View File
@@ -1511,7 +1511,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:05 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:11 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1530,7 +1530,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1548,7 +1548,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1568,7 +1568,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1596,7 +1596,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1644,7 +1644,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1664,7 +1664,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1708,7 +1708,7 @@
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<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:09 UTC 2025</spirit:value>
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<spirit:name>outputProductCRC</spirit:name>
@@ -1728,7 +1728,7 @@
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<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:09 UTC 2025</spirit:value>
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Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0.xml
+68 -271
View File
@@ -514,7 +514,7 @@
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
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@@ -941,7 +941,7 @@
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@@ -950,7 +950,7 @@
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@@ -959,7 +959,7 @@
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@@ -1079,7 +1079,7 @@
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<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
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@@ -1161,101 +1161,6 @@
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<spirit:name>CLK</spirit:name>
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@@ -1345,8 +1245,7 @@
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@@ -1362,8 +1261,7 @@
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@@ -1425,8 +1320,7 @@
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1899,8 +1765,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1919,8 +1784,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1935,8 +1799,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1948,8 +1811,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1964,8 +1826,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1984,8 +1845,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1997,8 +1857,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2014,8 +1873,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2027,8 +1885,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2047,8 +1904,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2060,8 +1916,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2077,8 +1932,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2093,8 +1947,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2110,8 +1963,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2126,8 +1978,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2151,60 +2002,6 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axi_crc_dma_ip_wrapper:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
@@ -2221,19 +2018,19 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
@@ -2262,9 +2059,9 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
@@ -2277,9 +2074,9 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_sim_netlist.v
-1118
View File
File diff suppressed because it is too large Load Diff
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_stub.v
-82
View File
@@ -1,82 +0,0 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Thu Feb 13 17:03:23 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt2/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_stub.v
// Design : axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_crc_dma_ip_wrapper,Vivado 2023.1" *)
module axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0(CLK, INTERRUPT, M_AXI_araddr, M_AXI_arburst,
M_AXI_arcache, M_AXI_arid, M_AXI_arlen, M_AXI_arprot, M_AXI_arready, M_AXI_arsize,
M_AXI_arvalid, M_AXI_awaddr, M_AXI_awburst, M_AXI_awcache, M_AXI_awid, M_AXI_awlen,
M_AXI_awprot, M_AXI_awready, M_AXI_awsize, M_AXI_awvalid, M_AXI_bid, M_AXI_bready,
M_AXI_bresp, M_AXI_bvalid, M_AXI_rdata, M_AXI_rid, M_AXI_rlast, M_AXI_rready, M_AXI_rresp,
M_AXI_rvalid, M_AXI_wdata, M_AXI_wid, M_AXI_wlast, M_AXI_wready, M_AXI_wstrb, M_AXI_wvalid,
RESETN, S_AXIL_araddr, S_AXIL_arready, S_AXIL_arvalid, S_AXIL_awaddr, S_AXIL_awready,
S_AXIL_awvalid, S_AXIL_bready, S_AXIL_bresp, S_AXIL_bvalid, S_AXIL_rdata, S_AXIL_rready,
S_AXIL_rresp, S_AXIL_rvalid, S_AXIL_wdata, S_AXIL_wready, S_AXIL_wstrb, S_AXIL_wvalid)
/* synthesis syn_black_box black_box_pad_pin="CLK,INTERRUPT,M_AXI_araddr[31:0],M_AXI_arburst[1:0],M_AXI_arcache[3:0],M_AXI_arid[0:0],M_AXI_arlen[3:0],M_AXI_arprot[2:0],M_AXI_arready,M_AXI_arsize[2:0],M_AXI_arvalid,M_AXI_awaddr[31:0],M_AXI_awburst[1:0],M_AXI_awcache[3:0],M_AXI_awid[0:0],M_AXI_awlen[3:0],M_AXI_awprot[2:0],M_AXI_awready,M_AXI_awsize[2:0],M_AXI_awvalid,M_AXI_bid[31:0],M_AXI_bready,M_AXI_bresp[1:0],M_AXI_bvalid,M_AXI_rdata[31:0],M_AXI_rid[0:0],M_AXI_rlast,M_AXI_rready,M_AXI_rresp[1:0],M_AXI_rvalid,M_AXI_wdata[31:0],M_AXI_wid[31:0],M_AXI_wlast,M_AXI_wready,M_AXI_wstrb[3:0],M_AXI_wvalid,RESETN,S_AXIL_araddr[7:0],S_AXIL_arready,S_AXIL_arvalid,S_AXIL_awaddr[7:0],S_AXIL_awready,S_AXIL_awvalid,S_AXIL_bready,S_AXIL_bresp[1:0],S_AXIL_bvalid,S_AXIL_rdata[31:0],S_AXIL_rready,S_AXIL_rresp[1:0],S_AXIL_rvalid,S_AXIL_wdata[31:0],S_AXIL_wready,S_AXIL_wstrb[3:0],S_AXIL_wvalid" */;
input CLK;
output INTERRUPT;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [0:0]M_AXI_arid;
output [3:0]M_AXI_arlen;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [0:0]M_AXI_awid;
output [3:0]M_AXI_awlen;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [31:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input [0:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output [31:0]M_AXI_wid;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input RESETN;
input [7:0]S_AXIL_araddr;
output S_AXIL_arready;
input S_AXIL_arvalid;
input [7:0]S_AXIL_awaddr;
output S_AXIL_awready;
input S_AXIL_awvalid;
input S_AXIL_bready;
output [1:0]S_AXIL_bresp;
output S_AXIL_bvalid;
output [31:0]S_AXIL_rdata;
input S_AXIL_rready;
output [1:0]S_AXIL_rresp;
output S_AXIL_rvalid;
input [31:0]S_AXIL_wdata;
output S_AXIL_wready;
input [3:0]S_AXIL_wstrb;
input S_AXIL_wvalid;
endmodule
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0/sim/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0.vhd
-297
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@@ -1,297 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axi_crc_dma_ip_wrapper:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0 IS
PORT (
CLK : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
M_AXI_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_arlen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_arready : IN STD_LOGIC;
M_AXI_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_arvalid : OUT STD_LOGIC;
M_AXI_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_awlen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_awready : IN STD_LOGIC;
M_AXI_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_awvalid : OUT STD_LOGIC;
M_AXI_bid : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_bready : OUT STD_LOGIC;
M_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_bvalid : IN STD_LOGIC;
M_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_rlast : IN STD_LOGIC;
M_AXI_rready : OUT STD_LOGIC;
M_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_rvalid : IN STD_LOGIC;
M_AXI_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_wid : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_wlast : OUT STD_LOGIC;
M_AXI_wready : IN STD_LOGIC;
M_AXI_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_wvalid : OUT STD_LOGIC;
RESETN : IN STD_LOGIC;
S_AXIL_araddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_arready : OUT STD_LOGIC;
S_AXIL_arvalid : IN STD_LOGIC;
S_AXIL_awaddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_awready : OUT STD_LOGIC;
S_AXIL_awvalid : IN STD_LOGIC;
S_AXIL_bready : IN STD_LOGIC;
S_AXIL_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_bvalid : OUT STD_LOGIC;
S_AXIL_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_rready : IN STD_LOGIC;
S_AXIL_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_rvalid : OUT STD_LOGIC;
S_AXIL_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_wready : OUT STD_LOGIC;
S_AXIL_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_wvalid : IN STD_LOGIC
);
END axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0;
ARCHITECTURE axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch OF axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_crc_dma_ip_wrapper IS
PORT (
CLK : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
M_AXI_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_arlen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_arready : IN STD_LOGIC;
M_AXI_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_arvalid : OUT STD_LOGIC;
M_AXI_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_awlen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_awready : IN STD_LOGIC;
M_AXI_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_awvalid : OUT STD_LOGIC;
M_AXI_bid : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_bready : OUT STD_LOGIC;
M_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_bvalid : IN STD_LOGIC;
M_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_rlast : IN STD_LOGIC;
M_AXI_rready : OUT STD_LOGIC;
M_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_rvalid : IN STD_LOGIC;
M_AXI_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_wid : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_wlast : OUT STD_LOGIC;
M_AXI_wready : IN STD_LOGIC;
M_AXI_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_wvalid : OUT STD_LOGIC;
RESETN : IN STD_LOGIC;
S_AXIL_araddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_arready : OUT STD_LOGIC;
S_AXIL_arvalid : IN STD_LOGIC;
S_AXIL_awaddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_awready : OUT STD_LOGIC;
S_AXIL_awvalid : IN STD_LOGIC;
S_AXIL_bready : IN STD_LOGIC;
S_AXIL_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_bvalid : OUT STD_LOGIC;
S_AXIL_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_rready : IN STD_LOGIC;
S_AXIL_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_rvalid : OUT STD_LOGIC;
S_AXIL_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_wready : OUT STD_LOGIC;
S_AXIL_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_wvalid : IN STD_LOGIC
);
END COMPONENT axi_crc_dma_ip_wrapper;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_araddr: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH" &
"READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_araddr: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ" &
"_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
BEGIN
U0 : axi_crc_dma_ip_wrapper
PORT MAP (
CLK => CLK,
INTERRUPT => INTERRUPT,
M_AXI_araddr => M_AXI_araddr,
M_AXI_arburst => M_AXI_arburst,
M_AXI_arcache => M_AXI_arcache,
M_AXI_arid => M_AXI_arid,
M_AXI_arlen => M_AXI_arlen,
M_AXI_arprot => M_AXI_arprot,
M_AXI_arready => M_AXI_arready,
M_AXI_arsize => M_AXI_arsize,
M_AXI_arvalid => M_AXI_arvalid,
M_AXI_awaddr => M_AXI_awaddr,
M_AXI_awburst => M_AXI_awburst,
M_AXI_awcache => M_AXI_awcache,
M_AXI_awid => M_AXI_awid,
M_AXI_awlen => M_AXI_awlen,
M_AXI_awprot => M_AXI_awprot,
M_AXI_awready => M_AXI_awready,
M_AXI_awsize => M_AXI_awsize,
M_AXI_awvalid => M_AXI_awvalid,
M_AXI_bid => M_AXI_bid,
M_AXI_bready => M_AXI_bready,
M_AXI_bresp => M_AXI_bresp,
M_AXI_bvalid => M_AXI_bvalid,
M_AXI_rdata => M_AXI_rdata,
M_AXI_rid => M_AXI_rid,
M_AXI_rlast => M_AXI_rlast,
M_AXI_rready => M_AXI_rready,
M_AXI_rresp => M_AXI_rresp,
M_AXI_rvalid => M_AXI_rvalid,
M_AXI_wdata => M_AXI_wdata,
M_AXI_wid => M_AXI_wid,
M_AXI_wlast => M_AXI_wlast,
M_AXI_wready => M_AXI_wready,
M_AXI_wstrb => M_AXI_wstrb,
M_AXI_wvalid => M_AXI_wvalid,
RESETN => RESETN,
S_AXIL_araddr => S_AXIL_araddr,
S_AXIL_arready => S_AXIL_arready,
S_AXIL_arvalid => S_AXIL_arvalid,
S_AXIL_awaddr => S_AXIL_awaddr,
S_AXIL_awready => S_AXIL_awready,
S_AXIL_awvalid => S_AXIL_awvalid,
S_AXIL_bready => S_AXIL_bready,
S_AXIL_bresp => S_AXIL_bresp,
S_AXIL_bvalid => S_AXIL_bvalid,
S_AXIL_rdata => S_AXIL_rdata,
S_AXIL_rready => S_AXIL_rready,
S_AXIL_rresp => S_AXIL_rresp,
S_AXIL_rvalid => S_AXIL_rvalid,
S_AXIL_wdata => S_AXIL_wdata,
S_AXIL_wready => S_AXIL_wready,
S_AXIL_wstrb => S_AXIL_wstrb,
S_AXIL_wvalid => S_AXIL_wvalid
);
END axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch;
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0/synth/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axi_crc_dma_ip_wrapper:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0 IS
PORT (
CLK : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
M_AXI_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_arlen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_arready : IN STD_LOGIC;
M_AXI_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_arvalid : OUT STD_LOGIC;
M_AXI_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_awlen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_awready : IN STD_LOGIC;
M_AXI_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_awvalid : OUT STD_LOGIC;
M_AXI_bid : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_bready : OUT STD_LOGIC;
M_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_bvalid : IN STD_LOGIC;
M_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_rlast : IN STD_LOGIC;
M_AXI_rready : OUT STD_LOGIC;
M_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_rvalid : IN STD_LOGIC;
M_AXI_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_wid : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_wlast : OUT STD_LOGIC;
M_AXI_wready : IN STD_LOGIC;
M_AXI_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_wvalid : OUT STD_LOGIC;
RESETN : IN STD_LOGIC;
S_AXIL_araddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_arready : OUT STD_LOGIC;
S_AXIL_arvalid : IN STD_LOGIC;
S_AXIL_awaddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_awready : OUT STD_LOGIC;
S_AXIL_awvalid : IN STD_LOGIC;
S_AXIL_bready : IN STD_LOGIC;
S_AXIL_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_bvalid : OUT STD_LOGIC;
S_AXIL_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_rready : IN STD_LOGIC;
S_AXIL_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_rvalid : OUT STD_LOGIC;
S_AXIL_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_wready : OUT STD_LOGIC;
S_AXIL_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_wvalid : IN STD_LOGIC
);
END axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0;
ARCHITECTURE axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch OF axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_crc_dma_ip_wrapper IS
PORT (
CLK : IN STD_LOGIC;
INTERRUPT : OUT STD_LOGIC;
M_AXI_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_arlen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_arready : IN STD_LOGIC;
M_AXI_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_arvalid : OUT STD_LOGIC;
M_AXI_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_awlen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_awready : IN STD_LOGIC;
M_AXI_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_awvalid : OUT STD_LOGIC;
M_AXI_bid : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_bready : OUT STD_LOGIC;
M_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_bvalid : IN STD_LOGIC;
M_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_rlast : IN STD_LOGIC;
M_AXI_rready : OUT STD_LOGIC;
M_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_rvalid : IN STD_LOGIC;
M_AXI_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_wid : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_wlast : OUT STD_LOGIC;
M_AXI_wready : IN STD_LOGIC;
M_AXI_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_wvalid : OUT STD_LOGIC;
RESETN : IN STD_LOGIC;
S_AXIL_araddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_arready : OUT STD_LOGIC;
S_AXIL_arvalid : IN STD_LOGIC;
S_AXIL_awaddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_awready : OUT STD_LOGIC;
S_AXIL_awvalid : IN STD_LOGIC;
S_AXIL_bready : IN STD_LOGIC;
S_AXIL_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_bvalid : OUT STD_LOGIC;
S_AXIL_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_rready : IN STD_LOGIC;
S_AXIL_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_rvalid : OUT STD_LOGIC;
S_AXIL_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_wready : OUT STD_LOGIC;
S_AXIL_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_wvalid : IN STD_LOGIC
);
END COMPONENT axi_crc_dma_ip_wrapper;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch: ARCHITECTURE IS "axi_crc_dma_ip_wrapper,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch : ARCHITECTURE IS "axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0,axi_crc_dma_ip_wrapper,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch: ARCHITECTURE IS "axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0,axi_crc_dma_ip_wrapper,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axi_crc_dma_ip_wrapper,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch: ARCHITECTURE IS "module_ref";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_araddr: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH" &
"READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_araddr: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ" &
"_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
BEGIN
U0 : axi_crc_dma_ip_wrapper
PORT MAP (
CLK => CLK,
INTERRUPT => INTERRUPT,
M_AXI_araddr => M_AXI_araddr,
M_AXI_arburst => M_AXI_arburst,
M_AXI_arcache => M_AXI_arcache,
M_AXI_arid => M_AXI_arid,
M_AXI_arlen => M_AXI_arlen,
M_AXI_arprot => M_AXI_arprot,
M_AXI_arready => M_AXI_arready,
M_AXI_arsize => M_AXI_arsize,
M_AXI_arvalid => M_AXI_arvalid,
M_AXI_awaddr => M_AXI_awaddr,
M_AXI_awburst => M_AXI_awburst,
M_AXI_awcache => M_AXI_awcache,
M_AXI_awid => M_AXI_awid,
M_AXI_awlen => M_AXI_awlen,
M_AXI_awprot => M_AXI_awprot,
M_AXI_awready => M_AXI_awready,
M_AXI_awsize => M_AXI_awsize,
M_AXI_awvalid => M_AXI_awvalid,
M_AXI_bid => M_AXI_bid,
M_AXI_bready => M_AXI_bready,
M_AXI_bresp => M_AXI_bresp,
M_AXI_bvalid => M_AXI_bvalid,
M_AXI_rdata => M_AXI_rdata,
M_AXI_rid => M_AXI_rid,
M_AXI_rlast => M_AXI_rlast,
M_AXI_rready => M_AXI_rready,
M_AXI_rresp => M_AXI_rresp,
M_AXI_rvalid => M_AXI_rvalid,
M_AXI_wdata => M_AXI_wdata,
M_AXI_wid => M_AXI_wid,
M_AXI_wlast => M_AXI_wlast,
M_AXI_wready => M_AXI_wready,
M_AXI_wstrb => M_AXI_wstrb,
M_AXI_wvalid => M_AXI_wvalid,
RESETN => RESETN,
S_AXIL_araddr => S_AXIL_araddr,
S_AXIL_arready => S_AXIL_arready,
S_AXIL_arvalid => S_AXIL_arvalid,
S_AXIL_awaddr => S_AXIL_awaddr,
S_AXIL_awready => S_AXIL_awready,
S_AXIL_awvalid => S_AXIL_awvalid,
S_AXIL_bready => S_AXIL_bready,
S_AXIL_bresp => S_AXIL_bresp,
S_AXIL_bvalid => S_AXIL_bvalid,
S_AXIL_rdata => S_AXIL_rdata,
S_AXIL_rready => S_AXIL_rready,
S_AXIL_rresp => S_AXIL_rresp,
S_AXIL_rvalid => S_AXIL_rvalid,
S_AXIL_wdata => S_AXIL_wdata,
S_AXIL_wready => S_AXIL_wready,
S_AXIL_wstrb => S_AXIL_wstrb,
S_AXIL_wvalid => S_AXIL_wvalid
);
END axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_arch;
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/axi_crc_dma_syn_1_system_ila_0_2.xml
+5 -5
View File
@@ -1179,7 +1179,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:01:58 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:21:58 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1197,7 +1197,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 15:55:54 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 19:30:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1233,7 +1233,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:17 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:23 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1252,7 +1252,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:01:58 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:21:58 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1305,7 +1305,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:01:59 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:21:58 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/axi_crc_dma_syn_1_system_ila_0_2_sim_netlist.v
+87761 -87761
View File
File diff suppressed because it is too large Load Diff
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/bd_e484.bxml
+4 -4
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="bd_e484" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739462524"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739462524"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739462524"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739462524"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739478128"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739478128"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739478128"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739478128"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\bd_e484.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_0/bd_e484_ila_lib_0.xml
+4 -4
View File
@@ -1046,7 +1046,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:01:59 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:00 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1065,7 +1065,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:00 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:01 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1096,7 +1096,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:00 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:00 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:00 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:00 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_1/bd_e484_g_inst_0.xml
+4 -4
View File
@@ -31172,7 +31172,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:04 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31192,7 +31192,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:04 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31212,7 +31212,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:04 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31232,7 +31232,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:04 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_10/bd_e484_slot_1_w_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_11/bd_e484_slot_1_b_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_12/bd_e484_slot_1_ar_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_13/bd_e484_slot_1_r_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_2/bd_e484_slot_0_apc_0.xml
+4 -4
View File
@@ -1276,7 +1276,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:05 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1296,7 +1296,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:05 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1319,7 +1319,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:05 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1339,7 +1339,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:05 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_3/bd_e484_slot_1_apc_0.xml
+4 -4
View File
@@ -1276,7 +1276,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:05 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1296,7 +1296,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1319,7 +1319,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:05 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1339,7 +1339,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_4/bd_e484_slot_0_aw_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_5/bd_e484_slot_0_w_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_6/bd_e484_slot_0_b_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_7/bd_e484_slot_0_ar_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_8/bd_e484_slot_0_r_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/bd_0/ip/ip_9/bd_e484_slot_1_aw_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
<spirit:value>Thu Feb 13 20:22:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/sim/axi_crc_dma_syn_1.vhd
-2655
View File
File diff suppressed because it is too large Load Diff
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/synth/axi_crc_dma_syn_1.vhd
-2655
View File
File diff suppressed because it is too large Load Diff
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/mref/axi_crc_dma_ip_wrapper/component.xml
+3 -3
View File
@@ -537,7 +537,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>0df542c6</spirit:value>
<spirit:value>ad42eba3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -550,7 +550,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>0df542c6</spirit:value>
<spirit:value>ad42eba3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1491,7 +1491,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-02-13T16:00:08Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2025-02-13T21:47:34Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/mref/axi_crc_dma_ip_wrapper/xgui/axi_crc_dma_ip_wrapper_v1_0.tcl
+10 -10
View File
@@ -1,10 +1,10 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml
+3 -3
View File
@@ -617,7 +617,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>e9142791</spirit:value>
<spirit:value>4eac77e0</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -630,7 +630,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>e9142791</spirit:value>
<spirit:value>4eac77e0</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1861,7 +1861,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-02-13T15:55:11Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2025-02-13T21:47:39Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl
+85 -85
View File
@@ -1,85 +1,85 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "FIFO_AWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "IDWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "MAX_BURSTLEN" -parent ${Page_0}
ipgui::add_param $IPINST -name "polynomial_default" -parent ${Page_0}
}
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
# Procedure called to validate DWIDTH
return true
}
proc update_PARAM_VALUE.FIFO_AWIDTH { PARAM_VALUE.FIFO_AWIDTH } {
# Procedure called to update FIFO_AWIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FIFO_AWIDTH { PARAM_VALUE.FIFO_AWIDTH } {
# Procedure called to validate FIFO_AWIDTH
return true
}
proc update_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } {
# Procedure called to update IDWIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } {
# Procedure called to validate IDWIDTH
return true
}
proc update_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } {
# Procedure called to update MAX_BURSTLEN when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } {
# Procedure called to validate MAX_BURSTLEN
return true
}
proc update_PARAM_VALUE.polynomial_default { PARAM_VALUE.polynomial_default } {
# Procedure called to update polynomial_default when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.polynomial_default { PARAM_VALUE.polynomial_default } {
# Procedure called to validate polynomial_default
return true
}
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
}
proc update_MODELPARAM_VALUE.IDWIDTH { MODELPARAM_VALUE.IDWIDTH PARAM_VALUE.IDWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IDWIDTH}] ${MODELPARAM_VALUE.IDWIDTH}
}
proc update_MODELPARAM_VALUE.MAX_BURSTLEN { MODELPARAM_VALUE.MAX_BURSTLEN PARAM_VALUE.MAX_BURSTLEN } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.MAX_BURSTLEN}] ${MODELPARAM_VALUE.MAX_BURSTLEN}
}
proc update_MODELPARAM_VALUE.FIFO_AWIDTH { MODELPARAM_VALUE.FIFO_AWIDTH PARAM_VALUE.FIFO_AWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FIFO_AWIDTH}] ${MODELPARAM_VALUE.FIFO_AWIDTH}
}
proc update_MODELPARAM_VALUE.polynomial_default { MODELPARAM_VALUE.polynomial_default PARAM_VALUE.polynomial_default } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.polynomial_default}] ${MODELPARAM_VALUE.polynomial_default}
}
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "FIFO_AWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "IDWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "MAX_BURSTLEN" -parent ${Page_0}
ipgui::add_param $IPINST -name "polynomial_default" -parent ${Page_0}
}
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
# Procedure called to validate DWIDTH
return true
}
proc update_PARAM_VALUE.FIFO_AWIDTH { PARAM_VALUE.FIFO_AWIDTH } {
# Procedure called to update FIFO_AWIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FIFO_AWIDTH { PARAM_VALUE.FIFO_AWIDTH } {
# Procedure called to validate FIFO_AWIDTH
return true
}
proc update_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } {
# Procedure called to update IDWIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } {
# Procedure called to validate IDWIDTH
return true
}
proc update_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } {
# Procedure called to update MAX_BURSTLEN when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } {
# Procedure called to validate MAX_BURSTLEN
return true
}
proc update_PARAM_VALUE.polynomial_default { PARAM_VALUE.polynomial_default } {
# Procedure called to update polynomial_default when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.polynomial_default { PARAM_VALUE.polynomial_default } {
# Procedure called to validate polynomial_default
return true
}
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
}
proc update_MODELPARAM_VALUE.IDWIDTH { MODELPARAM_VALUE.IDWIDTH PARAM_VALUE.IDWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IDWIDTH}] ${MODELPARAM_VALUE.IDWIDTH}
}
proc update_MODELPARAM_VALUE.MAX_BURSTLEN { MODELPARAM_VALUE.MAX_BURSTLEN PARAM_VALUE.MAX_BURSTLEN } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.MAX_BURSTLEN}] ${MODELPARAM_VALUE.MAX_BURSTLEN}
}
proc update_MODELPARAM_VALUE.FIFO_AWIDTH { MODELPARAM_VALUE.FIFO_AWIDTH PARAM_VALUE.FIFO_AWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FIFO_AWIDTH}] ${MODELPARAM_VALUE.FIFO_AWIDTH}
}
proc update_MODELPARAM_VALUE.polynomial_default { MODELPARAM_VALUE.polynomial_default PARAM_VALUE.polynomial_default } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.polynomial_default}] ${MODELPARAM_VALUE.polynomial_default}
}
Hardware/axi_crc_dma/axi_crc_dma.srcs/axi_crc_dma/imports/Hardware/aci_crc_dma/axi_crc_dma_sim_1_wrapper_behav.wcfg
+21 -4
View File
@@ -11,13 +11,13 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0.000 ns"></ZoomStartTime>
<ZoomEndTime time="1,000.001 ns"></ZoomEndTime>
<Cursor1Time time="1,000.000 ns"></Cursor1Time>
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
<ZoomEndTime time="10.000001 us"></ZoomEndTime>
<Cursor1Time time="10.000000 us"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="309"></NameColumnWidth>
<ValueColumnWidth column_width="150"></ValueColumnWidth>
<ValueColumnWidth column_width="145"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="13" />
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma_ip_wrapp_0/U0/CLK" type="logic">
@@ -35,6 +35,7 @@
<wvobject fp_name="group469" type="group">
<obj_property name="label">AXIL Register</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma_ip_wrapp_0/U0/axi_crc_dma_ip_i/axis_dma_0/U0/run_reg" type="logic">
<obj_property name="ElementShortName">run_reg</obj_property>
<obj_property name="ObjectShortName">run_reg</obj_property>
@@ -55,6 +56,22 @@
<obj_property name="ElementShortName">interrupt_reset</obj_property>
<obj_property name="ObjectShortName">interrupt_reset</obj_property>
</wvobject>
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma_ip_wrapp_0/U0/axi_crc_dma_ip_i/axis_dma_0/U0/read_address_reg" type="array">
<obj_property name="ElementShortName">read_address_reg[31:0]</obj_property>
<obj_property name="ObjectShortName">read_address_reg[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma_ip_wrapp_0/U0/axi_crc_dma_ip_i/axis_dma_0/U0/write_address_reg" type="array">
<obj_property name="ElementShortName">write_address_reg[31:0]</obj_property>
<obj_property name="ObjectShortName">write_address_reg[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma_ip_wrapp_0/U0/axi_crc_dma_ip_i/axis_dma_0/U0/packet_size_reg" type="array">
<obj_property name="ElementShortName">packet_size_reg[15:0]</obj_property>
<obj_property name="ObjectShortName">packet_size_reg[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma_ip_wrapp_0/U0/axi_crc_dma_ip_i/axis_dma_0/U0/packet_number_reg" type="array">
<obj_property name="ElementShortName">packet_number_reg[15:0]</obj_property>
<obj_property name="ObjectShortName">packet_number_reg[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma_ip_wrapp_0/U0/axi_crc_dma_ip_i/axis_dma_0/U0/initialValue" type="array">
<obj_property name="ElementShortName">initialValue[31:0]</obj_property>
<obj_property name="ObjectShortName">initialValue[31:0]</obj_property>
Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip.bd
+1549 -1636
View File
File diff suppressed because it is too large Load Diff
Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0.xci
+9 -9
View File
@@ -133,7 +133,7 @@
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
@@ -159,7 +159,7 @@
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
@@ -201,7 +201,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -276,11 +276,11 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
@@ -325,7 +325,7 @@
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_ip/ui/bd_de245c66.ui
+2 -2
View File
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.923399",
"Default View_TopLeft":"-241,-127",
"Default View_ScaleFactor":"1.00235",
"Default View_TopLeft":"-97,-32",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd
+933 -933
View File
File diff suppressed because it is too large Load Diff
Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci
+2 -2
View File
@@ -12,13 +12,13 @@
"Component_Name": [ { "value": "axi_crc_dma_sim_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ],
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"REVISION_NO": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
"REVISION_NO": [ { "value": "31", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"STIM_FILENAME": [ { "value": "../../axi_crc_dma_sim.mem", "resolve_type": "generated", "usage": "all" } ],
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"REVISION_NO": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ]
"REVISION_NO": [ { "value": "31", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui
+2 -2
View File
@@ -1,8 +1,8 @@
{
"ActiveEmotionalView":"Default View",
"Default View_Layers":"/axi_crc_dma_ip_wrapp_0_INTERRUPT:true|",
"Default View_ScaleFactor":"1.71064",
"Default View_TopLeft":"11,-109",
"Default View_ScaleFactor":"1.25",
"Default View_TopLeft":"-150,-126",
"Display-PortTypeInterrupt":"true",
"Display-PortTypeOthers":"true",
"ExpandedHierarchyInLayout":"",
Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bd
+3477 -3514
View File
File diff suppressed because it is too large Load Diff
Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0.xci
+9 -9
View File
@@ -100,7 +100,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -123,7 +123,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -175,7 +175,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -198,9 +198,9 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
@@ -244,10 +244,10 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
@@ -261,7 +261,7 @@
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
"PortWidth": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"INTERRUPT": [ { "physical_name": "INTERRUPT" } ]
Hardware/axi_crc_dma/axi_crc_dma.srcs/sources_1/bd/axi_crc_dma_syn_1/ui/bd_a79714db.ui
+1 -1
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@@ -1,7 +1,7 @@
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"Display-PortTypeOthers":"true",
Hardware/axi_crc_dma/axi_crc_dma.xpr
+400 -480
View File
@@ -1,480 +1,400 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.1 (64-bit) -->
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Config>
<Option Name="TopModule" Val="axi_crc_dma_syn_1_processing_system7_0_0"/>
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<Config>
<Option Name="TopModule" Val="axi_crc_dma_ip_axis_crc_0_0"/>
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<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
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</Run>
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<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
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<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
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<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
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<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
Hardware/axi_crc_dma/axi_crc_dma_sim.mem
+2 -2
View File
@@ -1,7 +1,7 @@
0000000000000000000000000000100000000001
0010000000000000000000000000000000001111
0010000000000000000011111110010000001111
0000000000000000000000000000110000000001
0011000000000000000000000000000000001111
0011000000000000000011111110010000001111
0000000000000000000000000001000000000001
0000000000000000000000000000111100001111
0000000000000000000000000001010000000001
Hardware/axi_crc_dma/axi_crc_dma_sim.stm
+3 -3
View File
@@ -1,6 +1,6 @@
wal 0x08 0x20000000 # Read Address
wal 0x0C 0x30000000 # Write Address
wal 0x10 15 # Packet Size
wal 0x08 0x20000FE4 # Read Address
wal 0x0C 0x30000FE4 # Write Address
wal 0x10 15 # Packet Size
wal 0x14 9 # Packet Number
wal 0x18 0xF4ACFB13 # Polynomial
wal 0x1c 0xFFFFFFFF # Inital Value
Hardware/axis_dma.vhd
+35 -15
View File
@@ -289,6 +289,8 @@ begin
variable packet_data_cnt : unsigned(15 downto 0); -- Anzahl der verbleibenden Worte beim aktuellen Packet Minus 1
variable data_cnt : unsigned(31 downto 0); -- Anzahl der insgesamt verbleibenden Worte Minus 1
variable read_addr_cnt : unsigned(31 downto 0); -- Zaehler fuer Adresse fuer AXI-Lesevorgaenge
variable burst_len : unsigned( 4 downto 0); -- Burstlaenge
variable bend : unsigned( 4 downto 0); -- Hilfsvariable zu Bestimmung der Burstlaenge
begin
wait until rising_edge(CLK);
@@ -297,6 +299,8 @@ begin
packet_data_cnt := (others=>'0');
data_cnt := (others=>'0');
read_addr_cnt := (others=>'0');
burst_len := (others=>'0');
bend := (others=>'0');
M_AXI_ARVALID <= '0';
M_AXI_ARADDR <= (others=>'0');
@@ -321,12 +325,20 @@ begin
-- Burstlaenge setzen
if (data_cnt+1) >= MAX_BURSTLEN then
M_AXI_ARLEN <= std_logic_vector(to_unsigned(MAX_BURSTLEN-1, 4));
read_addr_cnt := read_addr_cnt + to_unsigned(4*MAX_BURSTLEN, 32); -- Adresse inkrementieren
burst_len := to_unsigned(MAX_BURSTLEN-1,5);
else
M_AXI_ARLEN <= std_logic_vector(data_cnt(3 downto 0));
burst_len := '0' & data_cnt(3 downto 0);
end if;
bend := "0" & read_addr_cnt(5 downto 2) + burst_len;
if read_addr_cnt(11 downto 6) = "111111" and bend(4) = '1' then -- 4k boundary crossing?
burst_len := '0' & (not (read_addr_cnt(5 downto 2)));
end if;
M_AXI_ARLEN <= std_logic_vector(burst_len(3 downto 0));
read_addr_cnt := read_addr_cnt + 4 * (burst_len+1);
read_state <= WAIT_REQ_ACCEPT;
end if;
@@ -415,13 +427,19 @@ begin
M_AXI_WID <= (others=>'0');
process
variable burst_data_cnt : integer range 0 to MAX_BURSTLEN; -- Zaehler fuer aktuellen Burst
variable data_cnt : unsigned(31 downto 0); -- Zaehler fuer noch zu schreibende Worte
variable write_addr : unsigned(31 downto 0); -- Zaehler fuer Schreibadresse
variable burst_data_cnt : unsigned( 4 downto 0); -- Zaehler fuer aktuellen Burst
variable data_cnt : unsigned(31 downto 0); -- Zaehler fuer noch zu schreibende Worte
variable write_addr : unsigned(31 downto 0); -- Zaehler fuer Schreibadresse
variable bend : unsigned( 4 downto 0); -- Hilfsvariable zu Bestimmung der Burstlaenge
begin
wait until rising_edge(CLK);
if RESETN = '0' then
burst_data_cnt := (others=>'0');
data_cnt := (others=>'0');
write_addr := (others=>'0');
bend := (others=>'0');
M_AXI_AWVALID <= '0';
M_AXI_AWADDR <= (others=>'0');
M_AXI_AWLEN <= (others=>'0');
@@ -429,10 +447,6 @@ begin
run_reg_clear <= '0';
burst_data_cnt := 0;
data_cnt := (others=>'0');
write_addr := (others=>'0');
write_state <= IDLE;
else
case write_state is
@@ -454,14 +468,20 @@ begin
-- Burstlaenge setzen
if unsigned(S_AXIS_NUM_AVAIL) >= MAX_BURSTLEN then
burst_data_cnt := MAX_BURSTLEN - 1;
M_AXI_AWLEN <= std_logic_vector(to_unsigned(MAX_BURSTLEN-1, 4));
write_addr := write_addr + to_unsigned(4*MAX_BURSTLEN, 32); -- increment address
burst_data_cnt := to_unsigned(MAX_BURSTLEN-1,5);
else
M_AXI_AWLEN <= std_logic_vector(data_cnt(3 downto 0));
burst_data_cnt := to_integer(data_cnt);
burst_data_cnt := '0' & data_cnt(3 downto 0);
end if;
bend := "0" & write_addr(5 downto 2) + burst_data_cnt;
if write_addr(11 downto 6) = "111111" and bend(4) = '1' then -- 4k boundary crossing?
burst_data_cnt := '0' & unsigned(not (write_addr(5 downto 2)));
end if;
M_AXI_AWLEN <= std_logic_vector(burst_data_cnt(3 downto 0));
write_addr := write_addr + 4 * (burst_data_cnt+1);
write_state <= WAIT_REQ_ACCEPT;
end if;
Software/CRC_DMA.cpp
+77 -42
View File
@@ -16,12 +16,13 @@
#include "axi_crc_dma.h"
#include "gip.h"
//#define test 0
#define PACKET_SIZE 200
#define NUMBER_PACKETS 5
// #define DEBUG
#define DATA_SIZE ((PACKET_SIZE)*(NUMBER_PACKETS))
#define TEST_RUNS 10
#define MAX_PACKET_SIZE 10000
#define MAX_NUMBER_PACKETS 25
// Berechnen einer 32 Bit CRC-Pruefsumme mit allen Parametern
uint32_t calcCRC32(
@@ -37,6 +38,15 @@ uint32_t calcCRC32(
int main(int argc, char** argv)
{
int testRuns;
if (argc < 2) {
testRuns = TEST_RUNS;
}
else {
testRuns = atoi(argv[1]);
}
// some established CRC32 Parameter sets. Source: https://reveng.sourceforge.io/crc-catalogue/ (13.02.2025)
const CrcParameterSet CRC32_AIXM = {
.Polynomial = 0x814141ab,
@@ -55,9 +65,9 @@ int main(int argc, char** argv)
};
const CrcParameterSet CRC32_ISCSI = {
.Polynomial = 0x1edc6f41 ,
.InitalValue = 0xFFFFFFFF ,
.FinalXOR = 0xFFFFFFFF ,
.Polynomial = 0x1edc6f41,
.InitalValue = 0xFFFFFFFF,
.FinalXOR = 0xFFFFFFFF,
.InputReflected = true,
.OutputReflected = true
};
@@ -70,7 +80,18 @@ int main(int argc, char** argv)
.OutputReflected = false
};
CrcParameterSet CrcSets[4] = {CRC32_AIXM, CRC32_ISO_HDLC, CRC32_ISCSI, CRC32_CD_ROM_EDC};
const CrcParameterSet CRC32_BZIP2 = {
.Polynomial = 0x04c11db7,
.InitalValue = 0xFFFFFFFF,
.FinalXOR = 0xFFFFFFFF,
.InputReflected = false,
.OutputReflected = false
};
CrcParameterSet CrcSets[5] = {CRC32_AIXM, CRC32_ISO_HDLC, CRC32_ISCSI, CRC32_CD_ROM_EDC, CRC32_BZIP2};
// Fuer Erzeugung "zufaelliger" Daten
srand(time(NULL));
// UIO & pointers
int fdCRC = open("/dev/uio0", O_RDWR);
@@ -81,26 +102,34 @@ int main(int argc, char** argv)
// Physische Adressen anlegen
uint32_t uio16PhysBase = 0x30000000; // UIO16 physical Baseaddress
uint32_t* pDataPhy = (uint32_t*) uio16PhysBase;
uint32_t* pDataDestPhy = pDataPhy + DATA_SIZE;
printf("Programm startet\n\n");
// Speicher fuer die Ergebnisse der CRC Berechnungen durch Hardware und Software
uint32_t crc_sw[MAX_NUMBER_PACKETS];
uint32_t crc_hw[MAX_NUMBER_PACKETS];
for (int CrcSetI = 0; CrcSetI < 4; CrcSetI++) {
CrcParameterSet paraSet = CrcSets[CrcSetI];
bool allTestrunsOK = true;
// Die Software ist in mehrere Testlaufe unterteilt
// Jeder Testdurchlauf erzeugt eine zufaellige Anzahl Pakete und eine zufaellige Paketgroesse
for (int TestRun = 1; TestRun <= testRuns; TestRun++) {
CrcParameterSet paraSet = CrcSets[TestRun % 5];
// Paketgroesse und Paketanzahl erzeugen
uint16_t packet_size = (uint16_t) (rand() % MAX_PACKET_SIZE) + 1;
uint16_t number_packets = (uint16_t) (rand() % MAX_NUMBER_PACKETS) + 1;
// Mehrdimensionale Arrays deklarieren und mit virtuellen Adressen initialisieren
uint32_t (*data)[PACKET_SIZE] = (uint32_t (*)[PACKET_SIZE]) pMem;
uint32_t (*DataDest)[PACKET_SIZE+1] = (uint32_t (*)[PACKET_SIZE+1]) (pMem + DATA_SIZE);
uint32_t (*data)[packet_size] = (uint32_t (*)[packet_size]) pMem;
uint32_t (*DataDest)[packet_size+1] = (uint32_t (*)[packet_size+1]) (pMem + packet_size*number_packets);
// Speicher der Ergebnisse der CRC Berechnungen durch Hardware und Software
uint32_t crc_sw[NUMBER_PACKETS];
uint32_t crc_hw[NUMBER_PACKETS];
// Ausgabe
printf("------------- Starten von Testdurchlauf %i -------------\n\n", TestRun);
printf("Paketgroesse: %i\tPaketanzahl: %i\n\n", packet_size, number_packets);
// Testdaten erzeugen
printf("Testdaten erzeugen\n\n");
srand(time(NULL));
for (int packet = 0; packet < NUMBER_PACKETS; packet++) {
for (int word = 0; word < PACKET_SIZE; word++) {
for (int packet = 0; packet < number_packets; packet++) {
for (int word = 0; word < packet_size; word++) {
data[packet][word] = (uint32_t) rand();
}
}
@@ -108,9 +137,9 @@ int main(int argc, char** argv)
// axi_crc_dam Komponete parametrieren
CRC->Control |= (1<<1); // INT aktivieren
CRC->ReadAddress = (uint32_t) pDataPhy;
CRC->WriteAddress = (uint32_t) pDataDestPhy;
CRC->PacketSize = PACKET_SIZE - 1;
CRC->NumberPackets = NUMBER_PACKETS - 1;
CRC->WriteAddress = (uint32_t) (pDataPhy + number_packets * packet_size);
CRC->PacketSize = packet_size - 1;
CRC->NumberPackets = number_packets - 1;
CRC_DMA_set_parameters(CRC, &paraSet);
// Interrupt zurücksetzen und aktivieren
@@ -124,9 +153,9 @@ int main(int argc, char** argv)
// CRC Berechnung in Software durchfuehren
printf("CRC-Berechnung in Software durchfuehren\n\n");
for (int p = 0; p < NUMBER_PACKETS; p++) {
for (int p = 0; p < number_packets; p++) {
crc_sw[p] = calcCRC32((uint8_t*) (&data[p][0]),
PACKET_SIZE*4,
packet_size*4,
paraSet.Polynomial,
paraSet.InitalValue,
paraSet.FinalXOR,
@@ -134,9 +163,8 @@ int main(int argc, char** argv)
paraSet.OutputReflected ? 1 : 0
);
printf("Packet %i:\t0x%08x\n", p, crc_sw[p]);
// printf("Packet %i:\t0x%08x\n", p, crc_sw[p]);
}
printf("\n");
// Auf INT warten
printf("Auf Interrupt warten...\n");
@@ -147,19 +175,19 @@ int main(int argc, char** argv)
printf("Interrupt erhalten\n");
// Hardwareergebnis in Array ablegen
for (int p = 0; p < NUMBER_PACKETS; p++) {
crc_hw[p] = DataDest[p][PACKET_SIZE];
for (int p = 0; p < number_packets; p++) {
crc_hw[p] = DataDest[p][packet_size];
}
#ifdef test
#ifdef DEBUG
// data und DataDest komplett ausgeben
printf("\ndata\tDataDest:\n");
for (int p = 0; p < NUMBER_PACKETS; p++) {
for (int w = 0; w < PACKET_SIZE+1; w++) {
for (int p = 0; p < number_packets; p++) {
for (int w = 0; w < packet_size+1; w++) {
// dataDest ausgeben
if (w < PACKET_SIZE) {
if (w < packet_size) {
printf("0x%08x: 0x%08x\t0x%08x: 0x%08x\n", &DataDest[p][w], DataDest[p][w], &data[p][w], data[p][w]);
} else {
printf("0x%08x: 0x%08x\n", &DataDest[p][w], DataDest[p][w]);
@@ -172,15 +200,15 @@ int main(int argc, char** argv)
// Daten und Ergebnisse vergleichen
unsigned int wrongWords = 0; // Zaehler fuer Anzahl der fehlerhaften Worte im (Ziel-)Speicher
printf("Daten Ergebnisse vergleichen\n\n");
printf("Daten und Ergebnisse vergleichen\n\n");
bool allPaketsOK = true;
for (int p = 0; p < NUMBER_PACKETS; p++) {
for (int p = 0; p < number_packets; p++) {
bool dataOK = true;
bool crcOK = true;
printf("Paket %i:\t", p);
for (int w = 0; w < PACKET_SIZE; w++) {
for (int w = 0; w < packet_size; w++) {
// Daten vergleichen
if (data[p][w] != DataDest[p][w]) {
dataOK = false;
@@ -207,13 +235,20 @@ int main(int argc, char** argv)
}
}
if (allPaketsOK) {printf("Alle Pakete OK\n\n");}
printf("Alle Ergebnisse verglichen\n");
double percentageWrong = (double) wrongWords / (DATA_SIZE + NUMBER_PACKETS);
printf("%f Prozent der geschriebenen Worte sind fehlerhaft!\n", percentageWrong);
if (allPaketsOK) {
printf("Alle Pakete OK\nTestdurchlauf erfolgreich abgeschlossen!\n\n");
} else {
allTestrunsOK = false;
printf("Ein oder mehrere Pakete nicht OK.\n");
double percentageWrong = (double) wrongWords / (number_packets*packet_size + number_packets);
printf("%f Prozent der geschriebenen Worte sind fehlerhaft!\n\n", percentageWrong);
}
}
if (allTestrunsOK) {
printf("Alle Testdurchlaeufe erfolgreich abgeschlossen!\n");
} else {
printf("Ein oder mehrere Testdurchlaufe sind fehlerhaft!\n");
}
return 0;
Support/stm2mem/axi_crc_dma_sim.mem
-24
View File
@@ -1,24 +0,0 @@
0000000000000000000000000000100000000001
0010000000000000000000000000000000001111
0000000000000000000000000000110000000001
0011000000000000000000000000000000001111
0000000000000000000000000001000000000001
0000000000000000000000000000111100001111
0000000000000000000000000001010000000001
0000000000000000000000000000100100001111
0000000000000000000000000001100000000001
1111010010101100111110110001001100001111
0000000000000000000000000001110000000001
1111111111111111111111111111111100001111
0000000000000000000000000010000000000001
1111111111111111111111111111111100001111
0000000000000000000000000010010000000001
0000000000000000000000000000001100001111
0000000000000000000000000000000000000001
0000000000000000000000000000001100001111
0000000000000000000000000000000000000110
0000000000000000000000000000010000000001
0000000000000000000000000000000100001111
0000000000000000000000000000000000000001
0000000000000000000000000000001100001111
0000000000000000000000000000000000000000
Support/stm2mem/axi_crc_dma_sim.stm
-12
View File
@@ -1,12 +0,0 @@
wal 0x08 0x20000000 # Read Address
wal 0x0C 0x30000000 # Write Address
wal 0x10 15 # Packet Size
wal 0x14 9 # Packet Number
wal 0x18 0xF4ACFB13 # Polynomial
wal 0x1c 0xFFFFFFFF # Inital Value
wal 0x20 0xFFFFFFFF # FinalXOR
wal 0x24 0x3 # InOutReflected
wal 0 0x00000003 # Start IP with Interrupt Enabled
wfi
wal 0x04 0x1
wal 0 0x00000003