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axi_master lesen

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This commit is contained in:
Matthias Biermann
2025-01-29 20:26:07 +01:00
parent ed5cae58ea
commit 5fccf08c48
77 changed files with 76237 additions and 76564 deletions
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Hardware/axi3_slave_verif.vhd
+10 -11
View File
@@ -27,7 +27,7 @@ entity axi3_slave_verif is
S_AXI_RDATA : out std_logic_vector(DWIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector( 1 downto 0);
S_AXI_RID : out std_logic_vector(IDWIDTH-1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RLAST : out std_logic := '0';
-- AXI Write Address Channel
S_AXI_AWVALID : in std_logic;
@@ -54,12 +54,12 @@ end axi3_slave_verif;
architecture Behavioral of axi3_slave_verif is
type state_type is (IDLE, READ_RESP, WRITE_WAIT, WRITE_RESP);
signal state : state_type := IDLE;
signal burst_count : integer range 0 to MAX_BURSTLEN := 0;
signal read_addr : std_logic_vector(31 downto 0);
signal write_addr : std_logic_vector(31 downto 0);
begin
process(CLK)
variable burst_count : integer range 0 to MAX_BURSTLEN := 0;
begin
if rising_edge(CLK) then
if RESETN = '0' then
@@ -76,7 +76,7 @@ begin
when IDLE =>
S_AXI_ARREADY <= '1';
S_AXI_AWREADY <= '1';
burst_count <= 0;
burst_count := to_integer(unsigned(S_AXI_ARLEN)) + 1;
if S_AXI_ARVALID = '1' then
read_addr <= S_AXI_ARADDR;
@@ -93,18 +93,17 @@ begin
S_AXI_RVALID <= '1';
S_AXI_RDATA <= std_logic_vector(to_unsigned(burst_count, DWIDTH)); -- Dummy Daten
S_AXI_RRESP <= "00"; -- OKAY response
S_AXI_RLAST <= '0';
if burst_count = to_integer(unsigned(S_AXI_ARLEN)) then
S_AXI_RLAST <= '1';
end if;
if S_AXI_RREADY = '1' then
if burst_count < to_integer(unsigned(S_AXI_ARLEN)) then
burst_count <= burst_count + 1;
if burst_count > 0 then
if burst_count = 1 then
S_AXI_RLAST <= '1';
end if;
burst_count := burst_count - 1;
else
state <= IDLE;
S_AXI_RVALID <= '0';
S_AXI_RLAST <= '0';
state <= IDLE;
end if;
end if;
Hardware/crc_axi_control.vhd
+1 -1
View File
@@ -33,7 +33,7 @@ entity crc_axi_control is
axi_start : out std_logic;
axi_write : out std_logic;
axi_addr : out std_logic_vector(31 downto 0);
axi_size : out std_logic_vector(15 downto 0);
axi_size : out std_logic_vector(3 downto 0);
axi_idle : in std_logic;
-- Control signals for CRC component
Hardware/crc_axi_master.vhd
+49 -92
View File
@@ -17,7 +17,7 @@ entity crc_axi_master is
start : in std_logic;
write : in std_logic;
addr_axi : in std_logic_vector(DWIDTH-1 downto 0);
size : in std_logic_vector(15 downto 0);
size : in std_logic_vector(3 downto 0);
ip_idle : out std_logic;
-- Interface to BRAM
@@ -69,23 +69,13 @@ end entity;
architecture rtl of crc_axi_master is
-- for read requests
type read_fsm_state_t is (IDLE, REQ, WAIT_REQ_ACCEPT, READ_DATA);
signal state_read : read_fsm_state_t := IDLE;
type state_t is (IDLE, R_REQ, R_WAIT_REQ_ACCEPT, READ_DATA, W_REQ, W_WAIT_REQ_ACCEPT);
signal state : state_t := IDLE;
-- for write requests
type write_fsm_state_t is (IDLE, REQ, WAIT_REQ_ACCEPT);
signal state_write : write_fsm_state_t := IDLE;
signal fsm_active : std_logic := '0';
signal addr_buffer : unsigned(BRAM_AWIDTH-1 downto 0) := (others=>'0');
signal addr_mem : unsigned(31 downto 0) := (others=>'0');
signal data_cnt : unsigned(15 downto 0) := (others=>'0');
signal burst_len : unsigned(3 downto 0) := (others=>'0');
begin
ip_idle <= not fsm_active;
--------------------------------
-- AXI Read/Write Request Engine
--------------------------------
@@ -97,78 +87,6 @@ begin
M_AXI_ARID <= (others=>'0');
M_AXI_RREADY <= '1';
process
begin
wait until rising_edge(CLK);
if RESETN = '0' then
M_AXI_ARVALID <= '0';
M_AXI_ARADDR <= (others=>'0');
M_AXI_ARLEN <= (others=>'0');
state_read <= IDLE;
else
-- Default values for signals
we <= '0';
case state_read is
when IDLE =>
if fsm_active = '0' and start = '1' and write = '0' then
fsm_active <= '1';
addr_buffer <= (others=>'0');
addr_mem <= unsigned(addr_axi);
data_cnt <= unsigned(size) + 1;
state_read <= REQ;
end if;
when REQ =>
-- burst laenge setzen
if data_cnt >= MAX_BURSTLEN then
data_cnt <= data_cnt - MAX_BURSTLEN;
burst_len <= to_unsigned(MAX_BURSTLEN, 4);
else
burst_len <= data_cnt(3 downto 0) - 1;
end if;
M_AXI_ARADDR <= std_logic_vector(addr_mem);
M_AXI_ARLEN <= std_logic_vector(burst_len);
M_AXI_ARVALID <= '1';
state_read <= WAIT_REQ_ACCEPT;
when WAIT_REQ_ACCEPT =>
if M_AXI_ARREADY = '1' then
M_AXI_ARVALID <= '0';
state_read <= READ_DATA;
end if;
when READ_DATA =>
if M_AXI_RVALID = '1' then
waddr <= std_logic_vector(addr_buffer);
wdata <= M_AXI_RDATA;
we <= '1';
addr_buffer <= addr_buffer + 1;
if M_AXI_RLAST = '1' then
if data_cnt = 0 then
fsm_active <= '0';
state_read <= IDLE;
else
state_read <= REQ;
end if;
end if;
end if;
when others => null;
end case;
end if;
end process;
--------------------------------
-- AXI Write Request Engine
--------------------------------
-- static outputs
M_AXI_AWSIZE <= "010" when DWIDTH=32 else "011"; -- Data width 32/64
M_AXI_AWBURST <= "01";
M_AXI_AWPROT <= "000";
@@ -182,22 +100,61 @@ begin
begin
wait until rising_edge(CLK);
if RESETN = '1' then
if RESETN = '0' then
M_AXI_ARVALID <= '0';
M_AXI_ARADDR <= (others=>'0');
M_AXI_ARLEN <= (others=>'0');
M_AXI_WVALID <= '0';
M_AXI_AWVALID <= '0';
M_AXI_AWADDR <= (others=>'0');
M_AXI_AWLEN <= (others=>'0');
M_AXI_WLAST <= '0';
state_write <= IDLE;
else
case state_write is
when IDLE =>
if fsm_active = '0' and start = '1' and write = '1' then
state <= IDLE;
else
-- Default values for signals
we <= '0';
ip_idle <= '0';
case state is
when IDLE =>
ip_idle <= '1';
if start = '1' and write = '0' then
addr_buffer <= (others=>'0');
addr_mem <= unsigned(addr_axi);
state <= R_REQ;
end if;
when R_REQ =>
M_AXI_ARADDR <= std_logic_vector(addr_mem);
M_AXI_ARLEN <= size;
M_AXI_ARVALID <= '1';
state <= R_WAIT_REQ_ACCEPT;
when R_WAIT_REQ_ACCEPT =>
if M_AXI_ARREADY = '1' then
M_AXI_ARVALID <= '0';
state <= READ_DATA;
end if;
when READ_DATA =>
if M_AXI_RVALID = '1' then
waddr <= std_logic_vector(addr_buffer);
wdata <= M_AXI_RDATA;
we <= '1';
addr_buffer <= addr_buffer + 1;
if M_AXI_RLAST = '1' then
state <= IDLE;
end if;
end if;
when others => null;
end case;
end if;
end process;
end architecture;
Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bxml
+4 -4
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="crc_axi_master_sim" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738167767"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738167767"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738167767"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738167767"/>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738177499"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738177500"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738177499"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738177500"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\crc_axi_master_sim.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/hdl/crc_axi_master_sim_wrapper.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Wed Jan 29 17:22:47 2025
--Date : Wed Jan 29 20:04:59 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target crc_axi_master_sim_wrapper.bd
--Design : crc_axi_master_sim_wrapper
Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xml
+4 -1
View File
@@ -664,7 +664,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 16:22:47 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 18:58:01 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -908,6 +908,9 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_0_2/crc_axi_master_sim_crc_axi_master_0_2.xml
+21 -21
View File
@@ -698,7 +698,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e7c54c94</spirit:value>
<spirit:value>9:23cee625</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -714,11 +714,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 16:22:47 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:05:00 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e7c54c94</spirit:value>
<spirit:value>9:23cee625</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -793,7 +793,7 @@
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">15</spirit:left>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -1523,22 +1523,22 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
@@ -1546,13 +1546,13 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_0_2/sim/crc_axi_master_sim_crc_axi_master_0_2.vhd
+2 -2
View File
@@ -60,7 +60,7 @@ ENTITY crc_axi_master_sim_crc_axi_master_0_2 IS
start : IN STD_LOGIC;
write : IN STD_LOGIC;
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ip_idle : OUT STD_LOGIC;
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -121,7 +121,7 @@ ARCHITECTURE crc_axi_master_sim_crc_axi_master_0_2_arch OF crc_axi_master_sim_cr
start : IN STD_LOGIC;
write : IN STD_LOGIC;
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ip_idle : OUT STD_LOGIC;
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_sim_c_0_0/crc_axi_master_sim_crc_axi_master_sim_c_0_0.xml
+4 -4
View File
@@ -132,7 +132,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c50bf4c4</spirit:value>
<spirit:value>9:96c0ea84</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -148,11 +148,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 16:22:47 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 18:53:25 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c50bf4c4</spirit:value>
<spirit:value>9:96c0ea84</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -236,7 +236,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">15</spirit:left>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_sim_c_0_0/sim/crc_axi_master_sim_crc_axi_master_sim_c_0_0.vhd
+2 -2
View File
@@ -60,7 +60,7 @@ ENTITY crc_axi_master_sim_crc_axi_master_sim_c_0_0 IS
start : OUT STD_LOGIC;
write : OUT STD_LOGIC;
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
size : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
size : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_idle : IN STD_LOGIC
);
END crc_axi_master_sim_crc_axi_master_sim_c_0_0;
@@ -75,7 +75,7 @@ ARCHITECTURE crc_axi_master_sim_crc_axi_master_sim_c_0_0_arch OF crc_axi_master_
start : OUT STD_LOGIC;
write : OUT STD_LOGIC;
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
size : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
size : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_idle : IN STD_LOGIC
);
END COMPONENT crc_axi_master_sim_control;
Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/sim/crc_axi_master_sim.vhd
+39 -39
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Wed Jan 29 17:22:47 2025
--Date : Wed Jan 29 20:04:59 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target crc_axi_master_sim.bd
--Design : crc_axi_master_sim
@@ -47,10 +47,43 @@ architecture STRUCTURE of crc_axi_master_sim is
start : out STD_LOGIC;
write : out STD_LOGIC;
addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
size : out STD_LOGIC_VECTOR ( 15 downto 0 );
size : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_idle : in STD_LOGIC
);
end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
component crc_axi_master_sim_axi3_slave_verif_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_RLAST : out STD_LOGIC;
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WLAST : in STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component crc_axi_master_sim_axi3_slave_verif_0_0;
component crc_axi_master_sim_crc_axi_master_0_2 is
port (
CLK : in STD_LOGIC;
@@ -58,7 +91,7 @@ architecture STRUCTURE of crc_axi_master_sim is
start : in STD_LOGIC;
write : in STD_LOGIC;
addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
size : in STD_LOGIC_VECTOR ( 15 downto 0 );
size : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip_idle : out STD_LOGIC;
waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -102,39 +135,6 @@ architecture STRUCTURE of crc_axi_master_sim is
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component crc_axi_master_sim_crc_axi_master_0_2;
component crc_axi_master_sim_axi3_slave_verif_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_RLAST : out STD_LOGIC;
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WLAST : in STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component crc_axi_master_sim_axi3_slave_verif_0_0;
signal clk_rst_generator_0_clk : STD_LOGIC;
signal clk_rst_generator_0_rst_n : STD_LOGIC;
signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -171,7 +171,7 @@ architecture STRUCTURE of crc_axi_master_sim is
signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal crc_axi_master_0_we : STD_LOGIC;
signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 15 downto 0 );
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
signal crc_axi_master_sim_c_0_start : STD_LOGIC;
signal crc_axi_master_sim_c_0_write : STD_LOGIC;
signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -265,7 +265,7 @@ crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
re => crc_axi_master_0_re,
size(15 downto 0) => crc_axi_master_sim_c_0_size(15 downto 0),
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
start => crc_axi_master_sim_c_0_start,
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
@@ -278,7 +278,7 @@ crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
axi_idle => crc_axi_master_0_idle,
clk => clk_rst_generator_0_clk,
resetn => clk_rst_generator_0_rst_n,
size(15 downto 0) => crc_axi_master_sim_c_0_size(15 downto 0),
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
start => crc_axi_master_sim_c_0_start,
write => crc_axi_master_sim_c_0_write
);
Hardware/crc_axi_master/crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/synth/crc_axi_master_sim.vhd
+39 -39
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Wed Jan 29 17:22:47 2025
--Date : Wed Jan 29 20:04:59 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target crc_axi_master_sim.bd
--Design : crc_axi_master_sim
@@ -47,10 +47,43 @@ architecture STRUCTURE of crc_axi_master_sim is
start : out STD_LOGIC;
write : out STD_LOGIC;
addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
size : out STD_LOGIC_VECTOR ( 15 downto 0 );
size : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_idle : in STD_LOGIC
);
end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
component crc_axi_master_sim_axi3_slave_verif_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_RLAST : out STD_LOGIC;
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WLAST : in STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component crc_axi_master_sim_axi3_slave_verif_0_0;
component crc_axi_master_sim_crc_axi_master_0_2 is
port (
CLK : in STD_LOGIC;
@@ -58,7 +91,7 @@ architecture STRUCTURE of crc_axi_master_sim is
start : in STD_LOGIC;
write : in STD_LOGIC;
addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
size : in STD_LOGIC_VECTOR ( 15 downto 0 );
size : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip_idle : out STD_LOGIC;
waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -102,39 +135,6 @@ architecture STRUCTURE of crc_axi_master_sim is
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component crc_axi_master_sim_crc_axi_master_0_2;
component crc_axi_master_sim_axi3_slave_verif_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_RLAST : out STD_LOGIC;
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WLAST : in STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component crc_axi_master_sim_axi3_slave_verif_0_0;
signal clk_rst_generator_0_clk : STD_LOGIC;
signal clk_rst_generator_0_rst_n : STD_LOGIC;
signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -171,7 +171,7 @@ architecture STRUCTURE of crc_axi_master_sim is
signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal crc_axi_master_0_we : STD_LOGIC;
signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 15 downto 0 );
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
signal crc_axi_master_sim_c_0_start : STD_LOGIC;
signal crc_axi_master_sim_c_0_write : STD_LOGIC;
signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -265,7 +265,7 @@ crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
re => crc_axi_master_0_re,
size(15 downto 0) => crc_axi_master_sim_c_0_size(15 downto 0),
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
start => crc_axi_master_sim_c_0_start,
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
@@ -278,7 +278,7 @@ crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
axi_idle => crc_axi_master_0_idle,
clk => clk_rst_generator_0_clk,
resetn => clk_rst_generator_0_rst_n,
size(15 downto 0) => crc_axi_master_sim_c_0_size(15 downto 0),
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
start => crc_axi_master_sim_c_0_start,
write => crc_axi_master_sim_c_0_write
);
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/crc_axi_master_syn.bxml
+5 -50
View File
@@ -2,55 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="crc_axi_master_syn" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738165301"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738165301"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738165301"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738165301"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\crc_axi_master_syn.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\crc_axi_master_syn.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="crc_axi_master_syn_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\crc_axi_master_syn.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="crc_axi_master_syn.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\crc_axi_master_syn.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\crc_axi_master_syn.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738178750"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1738178750"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738178750"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738178750"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/crc_axi_master_syn_ooc.xdc
-14
View File
@@ -1,14 +0,0 @@
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
create_clock -name Processing_System_processing_system7_0_FCLK_CLK0 -period 10 [get_pins Processing_System/processing_system7_0/FCLK_CLK0]
create_clock -name Processing_System_processing_system7_0_FCLK_CLK1 -period 8 [get_pins Processing_System/processing_system7_0/FCLK_CLK1]
create_clock -name Processing_System_processing_system7_0_FCLK_CLK2 -period 5 [get_pins Processing_System/processing_system7_0/FCLK_CLK2]
create_clock -name Processing_System_processing_system7_0_FCLK_CLK3 -period 15 [get_pins Processing_System/processing_system7_0/FCLK_CLK3]
################################################################################
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/hdl/crc_axi_master_syn_wrapper.vhd
+92
View File
@@ -0,0 +1,92 @@
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Wed Jan 29 20:18:38 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target crc_axi_master_syn_wrapper.bd
--Design : crc_axi_master_syn_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity crc_axi_master_syn_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end crc_axi_master_syn_wrapper;
architecture STRUCTURE of crc_axi_master_syn_wrapper is
component crc_axi_master_syn is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component crc_axi_master_syn;
begin
crc_axi_master_syn_i: component crc_axi_master_syn
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_auto_us_0/crc_axi_master_syn_auto_us_0.xml
+9 -9
View File
@@ -1511,7 +1511,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:42 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:46 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1530,7 +1530,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:41 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:45 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1548,7 +1548,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:41 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:45 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1568,7 +1568,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:41 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:45 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1596,7 +1596,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:41 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:45 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1644,7 +1644,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:41 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:45 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1664,7 +1664,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:41 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:45 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1708,7 +1708,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:41 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:45 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1728,7 +1728,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:41 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:45 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_0_0/crc_axi_master_syn_crc_axi_master_0_0.xml
+27 -27
View File
@@ -698,7 +698,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7a0b1cb0</spirit:value>
<spirit:value>9:45a83f32</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -710,7 +710,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:dafcae8e</spirit:value>
<spirit:value>9:302fb0f1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -724,11 +724,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 12:12:09 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:21:32 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:dafcae8e</spirit:value>
<spirit:value>9:302fb0f1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -739,7 +739,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:dafcae8e</spirit:value>
<spirit:value>9:302fb0f1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -755,11 +755,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 12:11:02 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:44 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7a0b1cb0</spirit:value>
<spirit:value>9:45a83f32</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -775,11 +775,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 12:11:02 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:44 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:dafcae8e</spirit:value>
<spirit:value>9:302fb0f1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -859,7 +859,7 @@
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">15</spirit:left>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -1675,22 +1675,22 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
@@ -1698,13 +1698,13 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_0_0/crc_axi_master_syn_crc_axi_master_0_0_sim_netlist.v
+149 -800
View File
File diff suppressed because it is too large Load Diff
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_0_0/crc_axi_master_syn_crc_axi_master_0_0_stub.v
+3 -3
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jan 29 13:12:09 2025
// Date : Wed Jan 29 20:21:32 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_0_0/crc_axi_master_syn_crc_axi_master_0_0_stub.v
@@ -22,14 +22,14 @@ module crc_axi_master_syn_crc_axi_master_0_0(CLK, RESETN, start, write, addr_axi
M_AXI_AWADDR, M_AXI_AWLEN, M_AXI_AWSIZE, M_AXI_AWID, M_AXI_AWBURST, M_AXI_AWPROT,
M_AXI_AWCACHE, M_AXI_WREADY, M_AXI_WVALID, M_AXI_WDATA, M_AXI_WSTRB, M_AXI_WLAST, M_AXI_WID,
M_AXI_BREADY, M_AXI_BVALID, M_AXI_BID, M_AXI_BRESP)
/* synthesis syn_black_box black_box_pad_pin="RESETN,start,write,addr_axi[31:0],size[15:0],ip_idle,waddr[3:0],wdata[31:0],we,raddr[3:0],rdata[31:0],re,M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARID[0:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[0:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[0:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[31:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[31:0],M_AXI_BRESP[1:0]" */
/* synthesis syn_black_box black_box_pad_pin="RESETN,start,write,addr_axi[31:0],size[3:0],ip_idle,waddr[3:0],wdata[31:0],we,raddr[3:0],rdata[31:0],re,M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARID[0:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[0:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[0:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[31:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[31:0],M_AXI_BRESP[1:0]" */
/* synthesis syn_force_seq_prim="CLK" */;
input CLK /* synthesis syn_isclock = 1 */;
input RESETN;
input start;
input write;
input [31:0]addr_axi;
input [15:0]size;
input [3:0]size;
output ip_idle;
output [3:0]waddr;
output [31:0]wdata;
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_0_0/sim/crc_axi_master_syn_crc_axi_master_0_0.vhd
+2 -2
View File
@@ -60,7 +60,7 @@ ENTITY crc_axi_master_syn_crc_axi_master_0_0 IS
start : IN STD_LOGIC;
write : IN STD_LOGIC;
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ip_idle : OUT STD_LOGIC;
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -121,7 +121,7 @@ ARCHITECTURE crc_axi_master_syn_crc_axi_master_0_0_arch OF crc_axi_master_syn_cr
start : IN STD_LOGIC;
write : IN STD_LOGIC;
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ip_idle : OUT STD_LOGIC;
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_0_0/synth/crc_axi_master_syn_crc_axi_master_0_0.vhd
+2 -2
View File
@@ -60,7 +60,7 @@ ENTITY crc_axi_master_syn_crc_axi_master_0_0 IS
start : IN STD_LOGIC;
write : IN STD_LOGIC;
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ip_idle : OUT STD_LOGIC;
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -121,7 +121,7 @@ ARCHITECTURE crc_axi_master_syn_crc_axi_master_0_0_arch OF crc_axi_master_syn_cr
start : IN STD_LOGIC;
write : IN STD_LOGIC;
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ip_idle : OUT STD_LOGIC;
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_contr_0_0/crc_axi_master_syn_crc_axi_master_contr_0_0.xml
+12 -169
View File
@@ -85,7 +85,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -123,101 +123,6 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>crc_axi_master_control</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2d34f40a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>crc_axi_master_control</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6bf78be7</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:44:19 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6bf78be7</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6bf78be7</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>crc_axi_master_syn_crc_axi_master_contr_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:35 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2d34f40a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>crc_axi_master_syn_crc_axi_master_contr_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:35 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6bf78be7</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
@@ -226,8 +131,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -239,8 +143,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -252,8 +155,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -268,8 +170,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -284,8 +185,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -304,8 +204,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -318,14 +217,13 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">15</spirit:left>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -340,8 +238,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -355,60 +252,6 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>crc_axi_master_syn_crc_axi_master_contr_0_0.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>crc_axi_master_syn_crc_axi_master_contr_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>crc_axi_master_syn_crc_axi_master_contr_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>crc_axi_master_syn_crc_axi_master_contr_0_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>crc_axi_master_syn_crc_axi_master_contr_0_0_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/crc_axi_master_syn_crc_axi_master_contr_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/crc_axi_master_syn_crc_axi_master_contr_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:crc_axi_master_control:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
@@ -425,8 +268,8 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_contr_0_0/crc_axi_master_syn_crc_axi_master_contr_0_0_sim_netlist.v
-756
View File
@@ -1,756 +0,0 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jan 29 16:44:19 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_contr_0_0/crc_axi_master_syn_crc_axi_master_contr_0_0_sim_netlist.v
// Design : crc_axi_master_syn_crc_axi_master_contr_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "crc_axi_master_syn_crc_axi_master_contr_0_0,crc_axi_master_control,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *)
(* x_core_info = "crc_axi_master_control,Vivado 2023.1" *)
(* NotValidForBitStream *)
module crc_axi_master_syn_crc_axi_master_contr_0_0
(clk,
resetn,
finished,
start,
write,
addr,
size,
axi_idle);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 resetn RST" *) (* x_interface_parameter = "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input resetn;
output finished;
output start;
output write;
output [31:0]addr;
output [15:0]size;
input axi_idle;
wire \<const0> ;
wire [28:28]\^addr ;
wire axi_idle;
wire clk;
wire finished;
wire resetn;
wire start;
assign addr[31] = \<const0> ;
assign addr[30] = \<const0> ;
assign addr[29] = \^addr [28];
assign addr[28] = \^addr [28];
assign addr[27] = \<const0> ;
assign addr[26] = \<const0> ;
assign addr[25] = \<const0> ;
assign addr[24] = \<const0> ;
assign addr[23] = \<const0> ;
assign addr[22] = \<const0> ;
assign addr[21] = \<const0> ;
assign addr[20] = \<const0> ;
assign addr[19] = \<const0> ;
assign addr[18] = \<const0> ;
assign addr[17] = \<const0> ;
assign addr[16] = \<const0> ;
assign addr[15] = \<const0> ;
assign addr[14] = \<const0> ;
assign addr[13] = \<const0> ;
assign addr[12] = \<const0> ;
assign addr[11] = \<const0> ;
assign addr[10] = \<const0> ;
assign addr[9] = \<const0> ;
assign addr[8] = \<const0> ;
assign addr[7] = \<const0> ;
assign addr[6] = \<const0> ;
assign addr[5] = \<const0> ;
assign addr[4] = \<const0> ;
assign addr[3] = \<const0> ;
assign addr[2] = \<const0> ;
assign addr[1] = \<const0> ;
assign addr[0] = \<const0> ;
assign size[15] = \<const0> ;
assign size[14] = \<const0> ;
assign size[13] = \<const0> ;
assign size[12] = \<const0> ;
assign size[11] = \<const0> ;
assign size[10] = \<const0> ;
assign size[9] = \<const0> ;
assign size[8] = \<const0> ;
assign size[7] = \<const0> ;
assign size[6] = \<const0> ;
assign size[5] = \<const0> ;
assign size[4] = \<const0> ;
assign size[3] = \<const0> ;
assign size[2] = \^addr [28];
assign size[1] = \^addr [28];
assign size[0] = \^addr [28];
assign write = \<const0> ;
GND GND
(.G(\<const0> ));
crc_axi_master_syn_crc_axi_master_contr_0_0_crc_axi_master_control U0
(.addr(\^addr ),
.axi_idle(axi_idle),
.clk(clk),
.finished(finished),
.resetn(resetn),
.start(start));
endmodule
(* ORIG_REF_NAME = "crc_axi_master_control" *)
module crc_axi_master_syn_crc_axi_master_contr_0_0_crc_axi_master_control
(finished,
addr,
start,
resetn,
clk,
axi_idle);
output finished;
output [0:0]addr;
output start;
input resetn;
input clk;
input axi_idle;
wire \FSM_onehot_state[0]_i_1_n_0 ;
wire \FSM_onehot_state[1]_i_1_n_0 ;
wire \FSM_onehot_state[2]_i_1_n_0 ;
wire \FSM_onehot_state[2]_i_2_n_0 ;
wire \FSM_onehot_state[2]_i_3_n_0 ;
wire \FSM_onehot_state_reg_n_0_[0] ;
wire \FSM_onehot_state_reg_n_0_[1] ;
wire \FSM_onehot_state_reg_n_0_[2] ;
wire [0:0]addr;
wire \addr[29]_i_1_n_0 ;
wire axi_idle;
wire clk;
wire cnt;
wire \cnt[0]_i_10_n_0 ;
wire \cnt[0]_i_11_n_0 ;
wire \cnt[0]_i_12_n_0 ;
wire \cnt[0]_i_1_n_0 ;
wire \cnt[0]_i_4_n_0 ;
wire \cnt[0]_i_5_n_0 ;
wire \cnt[0]_i_6_n_0 ;
wire \cnt[0]_i_7_n_0 ;
wire \cnt[0]_i_8_n_0 ;
wire \cnt[0]_i_9_n_0 ;
wire [31:0]cnt_reg;
wire \cnt_reg[0]_i_3_n_0 ;
wire \cnt_reg[0]_i_3_n_1 ;
wire \cnt_reg[0]_i_3_n_2 ;
wire \cnt_reg[0]_i_3_n_3 ;
wire \cnt_reg[0]_i_3_n_4 ;
wire \cnt_reg[0]_i_3_n_5 ;
wire \cnt_reg[0]_i_3_n_6 ;
wire \cnt_reg[0]_i_3_n_7 ;
wire \cnt_reg[12]_i_1_n_0 ;
wire \cnt_reg[12]_i_1_n_1 ;
wire \cnt_reg[12]_i_1_n_2 ;
wire \cnt_reg[12]_i_1_n_3 ;
wire \cnt_reg[12]_i_1_n_4 ;
wire \cnt_reg[12]_i_1_n_5 ;
wire \cnt_reg[12]_i_1_n_6 ;
wire \cnt_reg[12]_i_1_n_7 ;
wire \cnt_reg[16]_i_1_n_0 ;
wire \cnt_reg[16]_i_1_n_1 ;
wire \cnt_reg[16]_i_1_n_2 ;
wire \cnt_reg[16]_i_1_n_3 ;
wire \cnt_reg[16]_i_1_n_4 ;
wire \cnt_reg[16]_i_1_n_5 ;
wire \cnt_reg[16]_i_1_n_6 ;
wire \cnt_reg[16]_i_1_n_7 ;
wire \cnt_reg[20]_i_1_n_0 ;
wire \cnt_reg[20]_i_1_n_1 ;
wire \cnt_reg[20]_i_1_n_2 ;
wire \cnt_reg[20]_i_1_n_3 ;
wire \cnt_reg[20]_i_1_n_4 ;
wire \cnt_reg[20]_i_1_n_5 ;
wire \cnt_reg[20]_i_1_n_6 ;
wire \cnt_reg[20]_i_1_n_7 ;
wire \cnt_reg[24]_i_1_n_0 ;
wire \cnt_reg[24]_i_1_n_1 ;
wire \cnt_reg[24]_i_1_n_2 ;
wire \cnt_reg[24]_i_1_n_3 ;
wire \cnt_reg[24]_i_1_n_4 ;
wire \cnt_reg[24]_i_1_n_5 ;
wire \cnt_reg[24]_i_1_n_6 ;
wire \cnt_reg[24]_i_1_n_7 ;
wire \cnt_reg[28]_i_1_n_1 ;
wire \cnt_reg[28]_i_1_n_2 ;
wire \cnt_reg[28]_i_1_n_3 ;
wire \cnt_reg[28]_i_1_n_4 ;
wire \cnt_reg[28]_i_1_n_5 ;
wire \cnt_reg[28]_i_1_n_6 ;
wire \cnt_reg[28]_i_1_n_7 ;
wire \cnt_reg[4]_i_1_n_0 ;
wire \cnt_reg[4]_i_1_n_1 ;
wire \cnt_reg[4]_i_1_n_2 ;
wire \cnt_reg[4]_i_1_n_3 ;
wire \cnt_reg[4]_i_1_n_4 ;
wire \cnt_reg[4]_i_1_n_5 ;
wire \cnt_reg[4]_i_1_n_6 ;
wire \cnt_reg[4]_i_1_n_7 ;
wire \cnt_reg[8]_i_1_n_0 ;
wire \cnt_reg[8]_i_1_n_1 ;
wire \cnt_reg[8]_i_1_n_2 ;
wire \cnt_reg[8]_i_1_n_3 ;
wire \cnt_reg[8]_i_1_n_4 ;
wire \cnt_reg[8]_i_1_n_5 ;
wire \cnt_reg[8]_i_1_n_6 ;
wire \cnt_reg[8]_i_1_n_7 ;
wire finished;
wire finished_i_1_n_0;
wire resetn;
wire start;
wire start_i_1_n_0;
wire [3:3]\NLW_cnt_reg[28]_i_1_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h2F))
\FSM_onehot_state[0]_i_1
(.I0(\FSM_onehot_state_reg_n_0_[0] ),
.I1(\FSM_onehot_state[2]_i_2_n_0 ),
.I2(resetn),
.O(\FSM_onehot_state[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hE200))
\FSM_onehot_state[1]_i_1
(.I0(\FSM_onehot_state_reg_n_0_[1] ),
.I1(\FSM_onehot_state[2]_i_2_n_0 ),
.I2(\FSM_onehot_state_reg_n_0_[0] ),
.I3(resetn),
.O(\FSM_onehot_state[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hE200))
\FSM_onehot_state[2]_i_1
(.I0(\FSM_onehot_state_reg_n_0_[2] ),
.I1(\FSM_onehot_state[2]_i_2_n_0 ),
.I2(\FSM_onehot_state_reg_n_0_[1] ),
.I3(resetn),
.O(\FSM_onehot_state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00010000))
\FSM_onehot_state[2]_i_2
(.I0(\cnt[0]_i_4_n_0 ),
.I1(\cnt[0]_i_5_n_0 ),
.I2(\cnt[0]_i_6_n_0 ),
.I3(\cnt[0]_i_7_n_0 ),
.I4(\FSM_onehot_state_reg_n_0_[0] ),
.I5(\FSM_onehot_state[2]_i_3_n_0 ),
.O(\FSM_onehot_state[2]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\FSM_onehot_state[2]_i_3
(.I0(axi_idle),
.I1(\FSM_onehot_state_reg_n_0_[1] ),
.O(\FSM_onehot_state[2]_i_3_n_0 ));
(* FSM_ENCODED_STATES = "startup:001,test_read:010,test_finished:100," *)
FDRE #(
.INIT(1'b1))
\FSM_onehot_state_reg[0]
(.C(clk),
.CE(1'b1),
.D(\FSM_onehot_state[0]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[0] ),
.R(1'b0));
(* FSM_ENCODED_STATES = "startup:001,test_read:010,test_finished:100," *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[1]
(.C(clk),
.CE(1'b1),
.D(\FSM_onehot_state[1]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[1] ),
.R(1'b0));
(* FSM_ENCODED_STATES = "startup:001,test_read:010,test_finished:100," *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[2]
(.C(clk),
.CE(1'b1),
.D(\FSM_onehot_state[2]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hE0))
\addr[29]_i_1
(.I0(addr),
.I1(\FSM_onehot_state_reg_n_0_[1] ),
.I2(resetn),
.O(\addr[29]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\addr_reg[29]
(.C(clk),
.CE(1'b1),
.D(\addr[29]_i_1_n_0 ),
.Q(addr),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1
(.I0(resetn),
.O(\cnt[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFFEF))
\cnt[0]_i_10
(.I0(cnt_reg[5]),
.I1(cnt_reg[4]),
.I2(cnt_reg[7]),
.I3(cnt_reg[6]),
.O(\cnt[0]_i_10_n_0 ));
LUT4 #(
.INIT(16'hFFEF))
\cnt[0]_i_11
(.I0(cnt_reg[29]),
.I1(cnt_reg[28]),
.I2(cnt_reg[30]),
.I3(cnt_reg[31]),
.O(\cnt[0]_i_11_n_0 ));
LUT4 #(
.INIT(16'hFFEF))
\cnt[0]_i_12
(.I0(cnt_reg[21]),
.I1(cnt_reg[20]),
.I2(cnt_reg[23]),
.I3(cnt_reg[22]),
.O(\cnt[0]_i_12_n_0 ));
LUT5 #(
.INIT(32'hFFFE0000))
\cnt[0]_i_2
(.I0(\cnt[0]_i_4_n_0 ),
.I1(\cnt[0]_i_5_n_0 ),
.I2(\cnt[0]_i_6_n_0 ),
.I3(\cnt[0]_i_7_n_0 ),
.I4(\FSM_onehot_state_reg_n_0_[0] ),
.O(cnt));
LUT5 #(
.INIT(32'hFFFFFFF7))
\cnt[0]_i_4
(.I0(cnt_reg[10]),
.I1(cnt_reg[11]),
.I2(cnt_reg[8]),
.I3(cnt_reg[9]),
.I4(\cnt[0]_i_9_n_0 ),
.O(\cnt[0]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\cnt[0]_i_5
(.I0(cnt_reg[2]),
.I1(cnt_reg[3]),
.I2(cnt_reg[0]),
.I3(cnt_reg[1]),
.I4(\cnt[0]_i_10_n_0 ),
.O(\cnt[0]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFFFBFF))
\cnt[0]_i_6
(.I0(cnt_reg[26]),
.I1(cnt_reg[27]),
.I2(cnt_reg[24]),
.I3(cnt_reg[25]),
.I4(\cnt[0]_i_11_n_0 ),
.O(\cnt[0]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFFFEFF))
\cnt[0]_i_7
(.I0(cnt_reg[18]),
.I1(cnt_reg[19]),
.I2(cnt_reg[17]),
.I3(cnt_reg[16]),
.I4(\cnt[0]_i_12_n_0 ),
.O(\cnt[0]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_8
(.I0(cnt_reg[0]),
.O(\cnt[0]_i_8_n_0 ));
LUT4 #(
.INIT(16'hFF7F))
\cnt[0]_i_9
(.I0(cnt_reg[13]),
.I1(cnt_reg[12]),
.I2(cnt_reg[14]),
.I3(cnt_reg[15]),
.O(\cnt[0]_i_9_n_0 ));
FDRE \cnt_reg[0]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[0]_i_3_n_7 ),
.Q(cnt_reg[0]),
.R(\cnt[0]_i_1_n_0 ));
(* ADDER_THRESHOLD = "11" *)
CARRY4 \cnt_reg[0]_i_3
(.CI(1'b0),
.CO({\cnt_reg[0]_i_3_n_0 ,\cnt_reg[0]_i_3_n_1 ,\cnt_reg[0]_i_3_n_2 ,\cnt_reg[0]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\cnt_reg[0]_i_3_n_4 ,\cnt_reg[0]_i_3_n_5 ,\cnt_reg[0]_i_3_n_6 ,\cnt_reg[0]_i_3_n_7 }),
.S({cnt_reg[3:1],\cnt[0]_i_8_n_0 }));
FDRE \cnt_reg[10]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[8]_i_1_n_5 ),
.Q(cnt_reg[10]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[11]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[8]_i_1_n_4 ),
.Q(cnt_reg[11]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[12]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[12]_i_1_n_7 ),
.Q(cnt_reg[12]),
.R(\cnt[0]_i_1_n_0 ));
(* ADDER_THRESHOLD = "11" *)
CARRY4 \cnt_reg[12]_i_1
(.CI(\cnt_reg[8]_i_1_n_0 ),
.CO({\cnt_reg[12]_i_1_n_0 ,\cnt_reg[12]_i_1_n_1 ,\cnt_reg[12]_i_1_n_2 ,\cnt_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\cnt_reg[12]_i_1_n_4 ,\cnt_reg[12]_i_1_n_5 ,\cnt_reg[12]_i_1_n_6 ,\cnt_reg[12]_i_1_n_7 }),
.S(cnt_reg[15:12]));
FDRE \cnt_reg[13]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[12]_i_1_n_6 ),
.Q(cnt_reg[13]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[14]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[12]_i_1_n_5 ),
.Q(cnt_reg[14]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[15]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[12]_i_1_n_4 ),
.Q(cnt_reg[15]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[16]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[16]_i_1_n_7 ),
.Q(cnt_reg[16]),
.R(\cnt[0]_i_1_n_0 ));
(* ADDER_THRESHOLD = "11" *)
CARRY4 \cnt_reg[16]_i_1
(.CI(\cnt_reg[12]_i_1_n_0 ),
.CO({\cnt_reg[16]_i_1_n_0 ,\cnt_reg[16]_i_1_n_1 ,\cnt_reg[16]_i_1_n_2 ,\cnt_reg[16]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\cnt_reg[16]_i_1_n_4 ,\cnt_reg[16]_i_1_n_5 ,\cnt_reg[16]_i_1_n_6 ,\cnt_reg[16]_i_1_n_7 }),
.S(cnt_reg[19:16]));
FDRE \cnt_reg[17]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[16]_i_1_n_6 ),
.Q(cnt_reg[17]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[18]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[16]_i_1_n_5 ),
.Q(cnt_reg[18]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[19]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[16]_i_1_n_4 ),
.Q(cnt_reg[19]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[1]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[0]_i_3_n_6 ),
.Q(cnt_reg[1]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[20]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[20]_i_1_n_7 ),
.Q(cnt_reg[20]),
.R(\cnt[0]_i_1_n_0 ));
(* ADDER_THRESHOLD = "11" *)
CARRY4 \cnt_reg[20]_i_1
(.CI(\cnt_reg[16]_i_1_n_0 ),
.CO({\cnt_reg[20]_i_1_n_0 ,\cnt_reg[20]_i_1_n_1 ,\cnt_reg[20]_i_1_n_2 ,\cnt_reg[20]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\cnt_reg[20]_i_1_n_4 ,\cnt_reg[20]_i_1_n_5 ,\cnt_reg[20]_i_1_n_6 ,\cnt_reg[20]_i_1_n_7 }),
.S(cnt_reg[23:20]));
FDRE \cnt_reg[21]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[20]_i_1_n_6 ),
.Q(cnt_reg[21]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[22]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[20]_i_1_n_5 ),
.Q(cnt_reg[22]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[23]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[20]_i_1_n_4 ),
.Q(cnt_reg[23]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[24]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[24]_i_1_n_7 ),
.Q(cnt_reg[24]),
.R(\cnt[0]_i_1_n_0 ));
(* ADDER_THRESHOLD = "11" *)
CARRY4 \cnt_reg[24]_i_1
(.CI(\cnt_reg[20]_i_1_n_0 ),
.CO({\cnt_reg[24]_i_1_n_0 ,\cnt_reg[24]_i_1_n_1 ,\cnt_reg[24]_i_1_n_2 ,\cnt_reg[24]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\cnt_reg[24]_i_1_n_4 ,\cnt_reg[24]_i_1_n_5 ,\cnt_reg[24]_i_1_n_6 ,\cnt_reg[24]_i_1_n_7 }),
.S(cnt_reg[27:24]));
FDRE \cnt_reg[25]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[24]_i_1_n_6 ),
.Q(cnt_reg[25]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[26]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[24]_i_1_n_5 ),
.Q(cnt_reg[26]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[27]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[24]_i_1_n_4 ),
.Q(cnt_reg[27]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[28]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[28]_i_1_n_7 ),
.Q(cnt_reg[28]),
.R(\cnt[0]_i_1_n_0 ));
(* ADDER_THRESHOLD = "11" *)
CARRY4 \cnt_reg[28]_i_1
(.CI(\cnt_reg[24]_i_1_n_0 ),
.CO({\NLW_cnt_reg[28]_i_1_CO_UNCONNECTED [3],\cnt_reg[28]_i_1_n_1 ,\cnt_reg[28]_i_1_n_2 ,\cnt_reg[28]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\cnt_reg[28]_i_1_n_4 ,\cnt_reg[28]_i_1_n_5 ,\cnt_reg[28]_i_1_n_6 ,\cnt_reg[28]_i_1_n_7 }),
.S(cnt_reg[31:28]));
FDRE \cnt_reg[29]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[28]_i_1_n_6 ),
.Q(cnt_reg[29]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[2]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[0]_i_3_n_5 ),
.Q(cnt_reg[2]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[30]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[28]_i_1_n_5 ),
.Q(cnt_reg[30]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[31]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[28]_i_1_n_4 ),
.Q(cnt_reg[31]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[3]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[0]_i_3_n_4 ),
.Q(cnt_reg[3]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[4]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[4]_i_1_n_7 ),
.Q(cnt_reg[4]),
.R(\cnt[0]_i_1_n_0 ));
(* ADDER_THRESHOLD = "11" *)
CARRY4 \cnt_reg[4]_i_1
(.CI(\cnt_reg[0]_i_3_n_0 ),
.CO({\cnt_reg[4]_i_1_n_0 ,\cnt_reg[4]_i_1_n_1 ,\cnt_reg[4]_i_1_n_2 ,\cnt_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\cnt_reg[4]_i_1_n_4 ,\cnt_reg[4]_i_1_n_5 ,\cnt_reg[4]_i_1_n_6 ,\cnt_reg[4]_i_1_n_7 }),
.S(cnt_reg[7:4]));
FDRE \cnt_reg[5]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[4]_i_1_n_6 ),
.Q(cnt_reg[5]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[6]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[4]_i_1_n_5 ),
.Q(cnt_reg[6]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[7]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[4]_i_1_n_4 ),
.Q(cnt_reg[7]),
.R(\cnt[0]_i_1_n_0 ));
FDRE \cnt_reg[8]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[8]_i_1_n_7 ),
.Q(cnt_reg[8]),
.R(\cnt[0]_i_1_n_0 ));
(* ADDER_THRESHOLD = "11" *)
CARRY4 \cnt_reg[8]_i_1
(.CI(\cnt_reg[4]_i_1_n_0 ),
.CO({\cnt_reg[8]_i_1_n_0 ,\cnt_reg[8]_i_1_n_1 ,\cnt_reg[8]_i_1_n_2 ,\cnt_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\cnt_reg[8]_i_1_n_4 ,\cnt_reg[8]_i_1_n_5 ,\cnt_reg[8]_i_1_n_6 ,\cnt_reg[8]_i_1_n_7 }),
.S(cnt_reg[11:8]));
FDRE \cnt_reg[9]
(.C(clk),
.CE(cnt),
.D(\cnt_reg[8]_i_1_n_6 ),
.Q(cnt_reg[9]),
.R(\cnt[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hF8))
finished_i_1
(.I0(\FSM_onehot_state_reg_n_0_[2] ),
.I1(resetn),
.I2(finished),
.O(finished_i_1_n_0));
FDRE #(
.INIT(1'b0))
finished_reg
(.C(clk),
.CE(1'b1),
.D(finished_i_1_n_0),
.Q(finished),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h8))
start_i_1
(.I0(\FSM_onehot_state_reg_n_0_[1] ),
.I1(resetn),
.O(start_i_1_n_0));
FDRE #(
.INIT(1'b0))
start_reg
(.C(clk),
.CE(1'b1),
.D(start_i_1_n_0),
.Q(start),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_contr_0_0/sim/crc_axi_master_syn_crc_axi_master_contr_0_0.vhd
-102
View File
@@ -1,102 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:crc_axi_master_control:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY crc_axi_master_syn_crc_axi_master_contr_0_0 IS
PORT (
clk : IN STD_LOGIC;
resetn : IN STD_LOGIC;
finished : OUT STD_LOGIC;
start : OUT STD_LOGIC;
write : OUT STD_LOGIC;
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
size : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
axi_idle : IN STD_LOGIC
);
END crc_axi_master_syn_crc_axi_master_contr_0_0;
ARCHITECTURE crc_axi_master_syn_crc_axi_master_contr_0_0_arch OF crc_axi_master_syn_crc_axi_master_contr_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT crc_axi_master_control IS
PORT (
clk : IN STD_LOGIC;
resetn : IN STD_LOGIC;
finished : OUT STD_LOGIC;
start : OUT STD_LOGIC;
write : OUT STD_LOGIC;
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
size : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
axi_idle : IN STD_LOGIC
);
END COMPONENT crc_axi_master_control;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn RST";
BEGIN
U0 : crc_axi_master_control
PORT MAP (
clk => clk,
resetn => resetn,
finished => finished,
start => start,
write => write,
addr => addr,
size => size,
axi_idle => axi_idle
);
END crc_axi_master_syn_crc_axi_master_contr_0_0_arch;
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_contr_0_0/synth/crc_axi_master_syn_crc_axi_master_contr_0_0.vhd
-110
View File
@@ -1,110 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:crc_axi_master_control:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY crc_axi_master_syn_crc_axi_master_contr_0_0 IS
PORT (
clk : IN STD_LOGIC;
resetn : IN STD_LOGIC;
finished : OUT STD_LOGIC;
start : OUT STD_LOGIC;
write : OUT STD_LOGIC;
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
size : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
axi_idle : IN STD_LOGIC
);
END crc_axi_master_syn_crc_axi_master_contr_0_0;
ARCHITECTURE crc_axi_master_syn_crc_axi_master_contr_0_0_arch OF crc_axi_master_syn_crc_axi_master_contr_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT crc_axi_master_control IS
PORT (
clk : IN STD_LOGIC;
resetn : IN STD_LOGIC;
finished : OUT STD_LOGIC;
start : OUT STD_LOGIC;
write : OUT STD_LOGIC;
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
size : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
axi_idle : IN STD_LOGIC
);
END COMPONENT crc_axi_master_control;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF crc_axi_master_syn_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "crc_axi_master_control,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF crc_axi_master_syn_crc_axi_master_contr_0_0_arch : ARCHITECTURE IS "crc_axi_master_syn_crc_axi_master_contr_0_0,crc_axi_master_control,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF crc_axi_master_syn_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "crc_axi_master_syn_crc_axi_master_contr_0_0,crc_axi_master_control,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=crc_axi_master_control,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF crc_axi_master_syn_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "module_ref";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn RST";
BEGIN
U0 : crc_axi_master_control
PORT MAP (
clk => clk,
resetn => resetn,
finished => finished,
start => start,
write => write,
addr => addr,
size => size,
axi_idle => axi_idle
);
END crc_axi_master_syn_crc_axi_master_contr_0_0_arch;
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/bd_eb4d.bd
+3 -3
View File
@@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0x2BD80240352BD7D8",
"boundary_crc": "0xF6797DED63AA5C96",
"design_src": "SBD",
"device": "xc7z020clg400-1",
"name": "bd_eb4d",
@@ -198,7 +198,7 @@
},
"probe2": {
"direction": "I",
"left": "15",
"left": "3",
"right": "0"
},
"probe3": {
@@ -438,7 +438,7 @@
"value": "0"
},
"C_PROBE2_WIDTH": {
"value": "16"
"value": "4"
},
"C_PROBE30_TYPE": {
"value": "0"
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/bd_eb4d.bxml
+4 -4
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="bd_eb4d" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738165300"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738165300"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738165300"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738165300"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738178324"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738178324"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738178324"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738178324"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\bd_eb4d.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/hdl/bd_eb4d_wrapper.vhd
+3 -3
View File
@@ -49,7 +49,7 @@ entity bd_eb4d_wrapper is
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
@@ -67,7 +67,7 @@ architecture STRUCTURE of bd_eb4d_wrapper is
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
@@ -154,7 +154,7 @@ bd_eb4d_i: component bd_eb4d
probe0(0) => probe0(0),
probe1(31 downto 0) => probe1(31 downto 0),
probe10(0) => probe10(0),
probe2(15 downto 0) => probe2(15 downto 0),
probe2(3 downto 0) => probe2(3 downto 0),
probe3(0) => probe3(0),
probe4(0) => probe4(0),
probe5(0) => probe5(0),
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_0/bd_eb4d_ila_lib_0.xci
+3 -3
View File
@@ -2052,7 +2052,7 @@
"C_PROBE5_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE4_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE3_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE2_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE2_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE1_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE0_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -3161,7 +3161,7 @@
"C_SLOT_0_AXI_BUSER_WIDTH": [ { "value": "4", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE0_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE1_WIDTH": [ { "value": "32", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE2_WIDTH": [ { "value": "16", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE2_WIDTH": [ { "value": "4", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE3_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE4_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE5_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
@@ -6274,7 +6274,7 @@
"clk": [ { "direction": "in" } ],
"probe0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"probe1": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"probe2": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"probe2": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"probe3": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"probe4": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"probe5": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_0/bd_eb4d_ila_lib_0.xml
+12 -12
View File
@@ -1046,11 +1046,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:36 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:40 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:688d694c</spirit:value>
<spirit:value>9:d0f679e6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1065,11 +1065,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:36 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:40 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:688d694c</spirit:value>
<spirit:value>9:d0f679e6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1080,7 +1080,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:688d694c</spirit:value>
<spirit:value>9:d0f679e6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1096,11 +1096,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:36 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:40 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:58b5abde</spirit:value>
<spirit:value>9:1040550d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1116,11 +1116,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:36 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:40 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:688d694c</spirit:value>
<spirit:value>9:d0f679e6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1325,7 +1325,7 @@
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PROBE2_WIDTH&apos;)) - 1)">15</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PROBE2_WIDTH&apos;)) - 1)">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -29128,7 +29128,7 @@
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_PROBE2_WIDTH</spirit:name>
<spirit:displayName>Probe2 Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_PROBE2_WIDTH" spirit:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_PROBE2_WIDTH&apos;)))" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">16</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_PROBE2_WIDTH" spirit:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_PROBE2_WIDTH&apos;)))" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">4</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_PROBE3_WIDTH</spirit:name>
@@ -69425,7 +69425,7 @@
<spirit:parameter>
<spirit:name>C_PROBE2_WIDTH</spirit:name>
<spirit:displayName>Probe2 Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE2_WIDTH" spirit:order="11100" spirit:configGroups="1 UnGrouped" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">16</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE2_WIDTH" spirit:order="11100" spirit:configGroups="1 UnGrouped" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">4</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_0/sim/bd_eb4d_ila_lib_0.vhd
+1 -1
View File
@@ -57,7 +57,7 @@ clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_0/synth/bd_eb4d_ila_lib_0.vhd
+4 -4
View File
@@ -57,7 +57,7 @@ clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -3216,7 +3216,7 @@ trig_out : OUT STD_LOGIC;
trig_out_ack : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -4248,7 +4248,7 @@ ATTRIBUTE X_CORE_INFO OF bd_eb4d_ila_lib_0_arch : ARCHITECTURE IS "ila,Vivado 20
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_eb4d_ila_lib_0_arch : ARCHITECTURE IS "bd_eb4d_ila_lib_0,ila_v6_2_13_ila,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bd_eb4d_ila_lib_0_arch : ARCHITECTURE IS "bd_eb4d_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=42,C_DATA_DEPTH=8192,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=100000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=32,C_PROBE2_WIDTH=16,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=4,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=4,C_PROBE9_WIDTH=32,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=2,C_PROBE12_WIDTH=32,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=4,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=4,C_PROBE17_WIDTH=3,C_PROBE18_WIDTH=3,C_PROBE19_WIDTH=2,C_PROBE20_WIDTH=32,C_PROBE21_WIDTH=2,C_PROBE22_WIDTH=4,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=4,C_PROBE25_WIDTH=3,C_PROBE26_WIDTH=3,C_PROBE27_WIDTH=2,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=2,C_PROBE30_WIDTH=2,C_PROBE31_WIDTH=32,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=2,C_PROBE34_WIDTH=32,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=4,C_PROBE37_WIDTH=2,C_PROBE38_WIDTH=3,C_PROBE39_WIDTH=2,C_PROBE40_WIDTH=2,C_PROBE41_WIDTH=3,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
ATTRIBUTE CORE_GENERATION_INFO OF bd_eb4d_ila_lib_0_arch : ARCHITECTURE IS "bd_eb4d_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=42,C_DATA_DEPTH=8192,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=100000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=32,C_PROBE2_WIDTH=4,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=4,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=4,C_PROBE9_WIDTH=32,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=2,C_PROBE12_WIDTH=32,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=4,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=4,C_PROBE17_WIDTH=3,C_PROBE18_WIDTH=3,C_PROBE19_WIDTH=2,C_PROBE20_WIDTH=32,C_PROBE21_WIDTH=2,C_PROBE22_WIDTH=4,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=4,C_PROBE25_WIDTH=3,C_PROBE26_WIDTH=3,C_PROBE27_WIDTH=2,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=2,C_PROBE30_WIDTH=2,C_PROBE31_WIDTH=32,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=2,C_PROBE34_WIDTH=32,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=4,C_PROBE37_WIDTH=2,C_PROBE38_WIDTH=3,C_PROBE39_WIDTH=2,C_PROBE40_WIDTH=2,C_PROBE41_WIDTH=3,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
"C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,"&
"C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,"&
"C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,"&
@@ -4320,7 +4320,7 @@ C_ILA_CLK_FREQ => 100000000,
C_PROBE0_WIDTH => 1,
C_PROBE1_WIDTH => 32,
C_PROBE2_WIDTH => 16,
C_PROBE2_WIDTH => 4,
C_PROBE3_WIDTH => 1,
C_PROBE4_WIDTH => 1,
C_PROBE5_WIDTH => 1,
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_1/bd_eb4d_g_inst_0.xml
+4 -4
View File
@@ -31172,7 +31172,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:38 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:42 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31192,7 +31192,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:42 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31212,7 +31212,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:38 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:42 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31232,7 +31232,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:42 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_2/bd_eb4d_slot_0_aw_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_3/bd_eb4d_slot_0_w_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_4/bd_eb4d_slot_0_b_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_5/bd_eb4d_slot_0_ar_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/ip/ip_6/bd_eb4d_slot_0_r_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:39 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/sim/bd_eb4d.vhd
+6 -6
View File
@@ -49,7 +49,7 @@ entity bd_eb4d is
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
@@ -60,7 +60,7 @@ entity bd_eb4d is
resetn : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of bd_eb4d : entity is "bd_eb4d,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_eb4d,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
attribute CORE_GENERATION_INFO of bd_eb4d : entity is "bd_eb4d,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_eb4d,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of bd_eb4d : entity is "crc_axi_master_syn_system_ila_0_0.hwdef";
end bd_eb4d;
@@ -71,7 +71,7 @@ architecture STRUCTURE of bd_eb4d is
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
@@ -309,7 +309,7 @@ architecture STRUCTURE of bd_eb4d is
signal probe0_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal probe10_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal probe1_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal probe2_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal probe2_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal probe3_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal probe4_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal probe5_1 : STD_LOGIC_VECTOR ( 0 to 0 );
@@ -398,7 +398,7 @@ begin
probe0_1(0) <= probe0(0);
probe10_1(0) <= probe10(0);
probe1_1(31 downto 0) <= probe1(31 downto 0);
probe2_1(15 downto 0) <= probe2(15 downto 0);
probe2_1(3 downto 0) <= probe2(3 downto 0);
probe3_1(0) <= probe3(0);
probe4_1(0) <= probe4(0);
probe5_1(0) <= probe5(0);
@@ -499,7 +499,7 @@ ila_lib: component bd_eb4d_ila_lib_0
probe17(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
probe18(2 downto 0) => net_slot_0_axi_arsize(2 downto 0),
probe19(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
probe2(15 downto 0) => probe2_1(15 downto 0),
probe2(3 downto 0) => probe2_1(3 downto 0),
probe20(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
probe21(1 downto 0) => net_slot_0_axi_awburst(1 downto 0),
probe22(3 downto 0) => net_slot_0_axi_awcache(3 downto 0),
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/bd_0/synth/bd_eb4d.vhd
+6 -6
View File
@@ -49,7 +49,7 @@ entity bd_eb4d is
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
@@ -60,7 +60,7 @@ entity bd_eb4d is
resetn : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of bd_eb4d : entity is "bd_eb4d,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_eb4d,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
attribute CORE_GENERATION_INFO of bd_eb4d : entity is "bd_eb4d,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_eb4d,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of bd_eb4d : entity is "crc_axi_master_syn_system_ila_0_0.hwdef";
end bd_eb4d;
@@ -71,7 +71,7 @@ architecture STRUCTURE of bd_eb4d is
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
@@ -309,7 +309,7 @@ architecture STRUCTURE of bd_eb4d is
signal probe0_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal probe10_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal probe1_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal probe2_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal probe2_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal probe3_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal probe4_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal probe5_1 : STD_LOGIC_VECTOR ( 0 to 0 );
@@ -398,7 +398,7 @@ begin
probe0_1(0) <= probe0(0);
probe10_1(0) <= probe10(0);
probe1_1(31 downto 0) <= probe1(31 downto 0);
probe2_1(15 downto 0) <= probe2(15 downto 0);
probe2_1(3 downto 0) <= probe2(3 downto 0);
probe3_1(0) <= probe3(0);
probe4_1(0) <= probe4(0);
probe5_1(0) <= probe5(0);
@@ -499,7 +499,7 @@ ila_lib: component bd_eb4d_ila_lib_0
probe17(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
probe18(2 downto 0) => net_slot_0_axi_arsize(2 downto 0),
probe19(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
probe2(15 downto 0) => probe2_1(15 downto 0),
probe2(3 downto 0) => probe2_1(3 downto 0),
probe20(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
probe21(1 downto 0) => net_slot_0_axi_awburst(1 downto 0),
probe22(3 downto 0) => net_slot_0_axi_awcache(3 downto 0),
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/crc_axi_master_syn_system_ila_0_0.xml
+13 -13
View File
@@ -706,11 +706,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:35 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:39 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9986923d</spirit:value>
<spirit:value>9:ac6c272e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -724,7 +724,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:14 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 15:41:31 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -760,11 +760,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:47:49 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:24:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9986923d</spirit:value>
<spirit:value>9:ac6c272e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -779,11 +779,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:35 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:39 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9986923d</spirit:value>
<spirit:value>9:ac6c272e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -796,7 +796,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:0e28d590</spirit:value>
<spirit:value>9:b817298a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -816,11 +816,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:35 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:39 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:0e28d590</spirit:value>
<spirit:value>9:b817298a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -840,11 +840,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 15:41:35 UTC 2025</spirit:value>
<spirit:value>Wed Jan 29 19:18:39 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9986923d</spirit:value>
<spirit:value>9:ac6c272e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -908,7 +908,7 @@
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">15</spirit:left>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/crc_axi_master_syn_system_ila_0_0_sim_netlist.v
+68442 -70163
View File
File diff suppressed because one or more lines are too long
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/crc_axi_master_syn_system_ila_0_0_stub.v
+3 -3
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jan 29 16:47:43 2025
// Date : Wed Jan 29 20:24:03 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/crc_axi_master_syn_system_ila_0_0_stub.v
@@ -25,12 +25,12 @@ module crc_axi_master_syn_system_ila_0_0(clk, probe0, probe1, probe2, probe3, pr
SLOT_0_AXI_arcache, SLOT_0_AXI_arprot, SLOT_0_AXI_arvalid, SLOT_0_AXI_arready,
SLOT_0_AXI_rid, SLOT_0_AXI_rdata, SLOT_0_AXI_rresp, SLOT_0_AXI_rlast, SLOT_0_AXI_rvalid,
SLOT_0_AXI_rready, resetn)
/* synthesis syn_black_box black_box_pad_pin="probe0[0:0],probe1[31:0],probe2[15:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[3:0],probe7[0:0],probe8[3:0],probe9[31:0],probe10[0:0],SLOT_0_AXI_awid[0:0],SLOT_0_AXI_awaddr[31:0],SLOT_0_AXI_awlen[3:0],SLOT_0_AXI_awsize[2:0],SLOT_0_AXI_awburst[1:0],SLOT_0_AXI_awcache[3:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wid[0:0],SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wlast,SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bid[0:0],SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_arid[0:0],SLOT_0_AXI_araddr[31:0],SLOT_0_AXI_arlen[3:0],SLOT_0_AXI_arsize[2:0],SLOT_0_AXI_arburst[1:0],SLOT_0_AXI_arcache[3:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rid[0:0],SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rlast,SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,resetn" */
/* synthesis syn_black_box black_box_pad_pin="probe0[0:0],probe1[31:0],probe2[3:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[3:0],probe7[0:0],probe8[3:0],probe9[31:0],probe10[0:0],SLOT_0_AXI_awid[0:0],SLOT_0_AXI_awaddr[31:0],SLOT_0_AXI_awlen[3:0],SLOT_0_AXI_awsize[2:0],SLOT_0_AXI_awburst[1:0],SLOT_0_AXI_awcache[3:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wid[0:0],SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wlast,SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bid[0:0],SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_arid[0:0],SLOT_0_AXI_araddr[31:0],SLOT_0_AXI_arlen[3:0],SLOT_0_AXI_arsize[2:0],SLOT_0_AXI_arburst[1:0],SLOT_0_AXI_arcache[3:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rid[0:0],SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rlast,SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,resetn" */
/* synthesis syn_force_seq_prim="clk" */;
input clk /* synthesis syn_isclock = 1 */;
input [0:0]probe0;
input [31:0]probe1;
input [15:0]probe2;
input [3:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/sim/crc_axi_master_syn_system_ila_0_0.vhd
+2 -2
View File
@@ -58,7 +58,7 @@ ENTITY crc_axi_master_syn_system_ila_0_0 IS
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -113,7 +113,7 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/synth/crc_axi_master_syn_system_ila_0_0.vhd
+2 -2
View File
@@ -58,7 +58,7 @@ ENTITY crc_axi_master_syn_system_ila_0_0 IS
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -113,7 +113,7 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/sim/crc_axi_master_syn.vhd
-1728
View File
File diff suppressed because it is too large Load Diff
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/synth/crc_axi_master_syn.vhd
-1728
View File
File diff suppressed because it is too large Load Diff
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_read_generator_0_0/design_1_axi_read_generator_0_0.xml
+4
View File
@@ -1174,6 +1174,10 @@
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 19:15:56 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5f7b7a6b</spirit:value>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_read_generator_0_0/design_1_axi_read_generator_0_0_sim_netlist.v
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Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_read_generator_0_0/design_1_axi_read_generator_0_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jan 29 20:15:56 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_read_generator_0_0/design_1_axi_read_generator_0_0_stub.v
// Design : design_1_axi_read_generator_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_read_generator,Vivado 2023.1" *)
module design_1_axi_read_generator_0_0(CLK, RESETN, TRIGGER, M_AXI_ARREADY,
M_AXI_ARVALID, M_AXI_ARADDR, M_AXI_ARID, M_AXI_ARLEN, M_AXI_ARSIZE, M_AXI_ARBURST,
M_AXI_ARPROT, M_AXI_ARCACHE, M_AXI_RREADY, M_AXI_RVALID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RID,
M_AXI_RLAST, M_AXI_AWREADY, M_AXI_AWVALID, M_AXI_AWADDR, M_AXI_AWLEN, M_AXI_AWSIZE,
M_AXI_AWID, M_AXI_AWBURST, M_AXI_AWPROT, M_AXI_AWCACHE, M_AXI_WREADY, M_AXI_WVALID,
M_AXI_WDATA, M_AXI_WSTRB, M_AXI_WLAST, M_AXI_WID, M_AXI_BREADY, M_AXI_BVALID, M_AXI_BID,
M_AXI_BRESP, S_AXIL_AWADDR, S_AXIL_AWVALID, S_AXIL_AWREADY, S_AXIL_WDATA, S_AXIL_WVALID,
S_AXIL_WREADY, S_AXIL_WSTRB, S_AXIL_BVALID, S_AXIL_BREADY, S_AXIL_BRESP, S_AXIL_ARADDR,
S_AXIL_ARVALID, S_AXIL_ARREADY, S_AXIL_RDATA, S_AXIL_RVALID, S_AXIL_RREADY, S_AXIL_RRESP)
/* synthesis syn_black_box black_box_pad_pin="RESETN,TRIGGER,M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARID[3:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[3:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[3:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[3:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[3:0],M_AXI_BRESP[1:0],S_AXIL_AWADDR[14:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[14:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0]" */
/* synthesis syn_force_seq_prim="CLK" */;
input CLK /* synthesis syn_isclock = 1 */;
input RESETN;
output TRIGGER;
input M_AXI_ARREADY;
output M_AXI_ARVALID;
output [31:0]M_AXI_ARADDR;
output [3:0]M_AXI_ARID;
output [3:0]M_AXI_ARLEN;
output [2:0]M_AXI_ARSIZE;
output [1:0]M_AXI_ARBURST;
output [2:0]M_AXI_ARPROT;
output [3:0]M_AXI_ARCACHE;
output M_AXI_RREADY;
input M_AXI_RVALID;
input [31:0]M_AXI_RDATA;
input [1:0]M_AXI_RRESP;
input [3:0]M_AXI_RID;
input M_AXI_RLAST;
input M_AXI_AWREADY;
output M_AXI_AWVALID;
output [31:0]M_AXI_AWADDR;
output [3:0]M_AXI_AWLEN;
output [2:0]M_AXI_AWSIZE;
output [3:0]M_AXI_AWID;
output [1:0]M_AXI_AWBURST;
output [2:0]M_AXI_AWPROT;
output [3:0]M_AXI_AWCACHE;
input M_AXI_WREADY;
output M_AXI_WVALID;
output [31:0]M_AXI_WDATA;
output [3:0]M_AXI_WSTRB;
output M_AXI_WLAST;
output [3:0]M_AXI_WID;
output M_AXI_BREADY;
input M_AXI_BVALID;
input [3:0]M_AXI_BID;
input [1:0]M_AXI_BRESP;
input [14:0]S_AXIL_AWADDR;
input S_AXIL_AWVALID;
output S_AXIL_AWREADY;
input [31:0]S_AXIL_WDATA;
input S_AXIL_WVALID;
output S_AXIL_WREADY;
input [3:0]S_AXIL_WSTRB;
output S_AXIL_BVALID;
input S_AXIL_BREADY;
output [1:0]S_AXIL_BRESP;
input [14:0]S_AXIL_ARADDR;
input S_AXIL_ARVALID;
output S_AXIL_ARREADY;
output [31:0]S_AXIL_RDATA;
output S_AXIL_RVALID;
input S_AXIL_RREADY;
output [1:0]S_AXIL_RRESP;
endmodule
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_vip_0_0/design_1_axi_vip_0_0.xml
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<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 19:15:52 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52b70a1d</spirit:value>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_vip_0_0/design_1_axi_vip_0_0_sim_netlist.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jan 29 20:15:52 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_vip_0_0/design_1_axi_vip_0_0_sim_netlist.v
// Design : design_1_axi_vip_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_axi_vip_0_0,axi_vip_v1_1_14_top,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_vip_v1_1_14_top,Vivado 2023.1" *)
(* NotValidForBitStream *)
module design_1_axi_vip_0_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLOCK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLOCK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RESET, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [3:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [3:0]s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [3:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [3:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [3:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 4, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
wire \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
GND GND
(.G(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_vip_0_0/design_1_axi_vip_0_0_stub.v
+61
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@@ -0,0 +1,61 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jan 29 20:15:52 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_vip_0_0/design_1_axi_vip_0_0_stub.v
// Design : design_1_axi_vip_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_vip_v1_1_14_top,Vivado 2023.1" *)
module design_1_axi_vip_0_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awcache, s_axi_awprot, s_axi_awvalid,
s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready,
s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen,
s_axi_arsize, s_axi_arburst, s_axi_arcache, s_axi_arprot, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[3:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wid[3:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[3:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[3:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rid[3:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready" */;
input aclk;
input aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [3:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
endmodule
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml
+4
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@@ -612,6 +612,10 @@
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 19:15:58 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:04c44734</spirit:value>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_sim_netlist.v
+2358
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File diff suppressed because it is too large Load Diff
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_stub.v
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@@ -0,0 +1,45 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jan 29 20:15:58 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_stub.v
// Design : design_1_axil_master_with_rom_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axil_master_with_rom,Vivado 2023.1" *)
module design_1_axil_master_with_rom_0_0(M_AXIL_ACLK, M_AXIL_ARESETN, M_AXIL_ARREADY,
M_AXIL_ARVALID, M_AXIL_ARADDR, M_AXIL_ARPROT, M_AXIL_RREADY, M_AXIL_RVALID, M_AXIL_RDATA,
M_AXIL_RRESP, M_AXIL_AWREADY, M_AXIL_AWVALID, M_AXIL_AWADDR, M_AXIL_AWPROT, M_AXIL_WREADY,
M_AXIL_WVALID, M_AXIL_WDATA, M_AXIL_WSTRB, M_AXIL_BREADY, M_AXIL_BVALID, M_AXIL_BRESP)
/* synthesis syn_black_box black_box_pad_pin="M_AXIL_ARESETN,M_AXIL_ARREADY,M_AXIL_ARVALID,M_AXIL_ARADDR[31:0],M_AXIL_ARPROT[2:0],M_AXIL_RREADY,M_AXIL_RVALID,M_AXIL_RDATA[31:0],M_AXIL_RRESP[1:0],M_AXIL_AWREADY,M_AXIL_AWVALID,M_AXIL_AWADDR[31:0],M_AXIL_AWPROT[2:0],M_AXIL_WREADY,M_AXIL_WVALID,M_AXIL_WDATA[31:0],M_AXIL_WSTRB[3:0],M_AXIL_BREADY,M_AXIL_BVALID,M_AXIL_BRESP[1:0]" */
/* synthesis syn_force_seq_prim="M_AXIL_ACLK" */;
input M_AXIL_ACLK /* synthesis syn_isclock = 1 */;
input M_AXIL_ARESETN;
input M_AXIL_ARREADY;
output M_AXIL_ARVALID;
output [31:0]M_AXIL_ARADDR;
output [2:0]M_AXIL_ARPROT;
output M_AXIL_RREADY;
input M_AXIL_RVALID;
input [31:0]M_AXIL_RDATA;
input [1:0]M_AXIL_RRESP;
input M_AXIL_AWREADY;
output M_AXIL_AWVALID;
output [31:0]M_AXIL_AWADDR;
output [2:0]M_AXIL_AWPROT;
input M_AXIL_WREADY;
output M_AXIL_WVALID;
output [31:0]M_AXIL_WDATA;
output [3:0]M_AXIL_WSTRB;
output M_AXIL_BREADY;
input M_AXIL_BVALID;
input [1:0]M_AXIL_BRESP;
endmodule
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml
+4
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@@ -52,6 +52,10 @@
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Jan 29 19:15:54 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6414fffb</spirit:value>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_sim_netlist.v
+375
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@@ -0,0 +1,375 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jan 29 20:15:54 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_sim_netlist.v
// Design : design_1_clk_rst_generator_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_clk_rst_generator_0_0,clk_rst_generator,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "clk_rst_generator,Vivado 2023.1" *)
(* NotValidForBitStream *)
module design_1_clk_rst_generator_0_0
(clk_in,
rst_in,
clk,
rst_n,
stop_simulation);
input clk_in;
input rst_in;
output clk;
output rst_n;
input stop_simulation;
wire clk;
wire clk_in;
wire rst_in;
wire rst_n;
(* CLOCK_PERIOD = "8000" *)
(* HAS_CLK_INPUT = "TRUE" *)
(* HAS_RESET_INPUT = "TRUE" *)
(* HAS_STOP_INPUT = "TRUE" *)
design_1_clk_rst_generator_0_0_clk_rst_generator U0
(.clk(clk),
.clk_in(clk_in),
.rst_in(rst_in),
.rst_n(rst_n),
.stop_simulation(1'b0));
endmodule
(* CLOCK_PERIOD = "8000" *) (* HAS_CLK_INPUT = "TRUE" *) (* HAS_RESET_INPUT = "TRUE" *)
(* HAS_STOP_INPUT = "TRUE" *) (* ORIG_REF_NAME = "clk_rst_generator" *)
module design_1_clk_rst_generator_0_0_clk_rst_generator
(clk_in,
rst_in,
clk,
rst_n,
stop_simulation);
input clk_in;
input rst_in;
output clk;
output rst_n;
input stop_simulation;
wire [4:0]L;
wire clk_in;
wire [6:0]rescnt;
wire \rescnt[3]_i_5_n_0 ;
wire \rescnt[3]_i_6_n_0 ;
wire \rescnt[3]_i_7_n_0 ;
wire \rescnt[3]_i_8_n_0 ;
wire \rescnt[6]_i_4_n_0 ;
wire \rescnt[6]_i_5_n_0 ;
wire \rescnt[6]_i_6_n_0 ;
wire [6:0]rescnt_reg;
wire \rescnt_reg[3]_i_1_n_0 ;
wire \rescnt_reg[3]_i_1_n_1 ;
wire \rescnt_reg[3]_i_1_n_2 ;
wire \rescnt_reg[3]_i_1_n_3 ;
wire \rescnt_reg[6]_i_1_n_2 ;
wire \rescnt_reg[6]_i_1_n_3 ;
wire rst_in;
wire rst_in_sync;
wire rst_n;
wire rst_sig;
wire rst_sig_i_1_n_0;
wire rst_sig_i_2_n_0;
wire rst_sig_reg_n_0;
wire [3:2]\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED ;
assign clk = clk_in;
LUT2 #(
.INIT(4'hE))
\rescnt[3]_i_2
(.I0(rst_in_sync),
.I1(rescnt_reg[2]),
.O(L[2]));
LUT5 #(
.INIT(32'h00000001))
\rescnt[3]_i_3
(.I0(rescnt_reg[6]),
.I1(rescnt_reg[4]),
.I2(rst_in_sync),
.I3(rescnt_reg[5]),
.I4(rst_sig_i_2_n_0),
.O(rst_sig));
LUT2 #(
.INIT(4'hE))
\rescnt[3]_i_4
(.I0(rst_in_sync),
.I1(rescnt_reg[0]),
.O(L[0]));
LUT3 #(
.INIT(8'hF9))
\rescnt[3]_i_5
(.I0(rescnt_reg[2]),
.I1(rescnt_reg[3]),
.I2(rst_in_sync),
.O(\rescnt[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h000000000001FFFE))
\rescnt[3]_i_6
(.I0(rst_sig_i_2_n_0),
.I1(rescnt_reg[5]),
.I2(rescnt_reg[4]),
.I3(rescnt_reg[6]),
.I4(rescnt_reg[2]),
.I5(rst_in_sync),
.O(\rescnt[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000000000001FFFE))
\rescnt[3]_i_7
(.I0(rst_sig_i_2_n_0),
.I1(rescnt_reg[5]),
.I2(rescnt_reg[4]),
.I3(rescnt_reg[6]),
.I4(rescnt_reg[1]),
.I5(rst_in_sync),
.O(\rescnt[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0055005500550056))
\rescnt[3]_i_8
(.I0(rescnt_reg[0]),
.I1(rst_sig_i_2_n_0),
.I2(rescnt_reg[5]),
.I3(rst_in_sync),
.I4(rescnt_reg[4]),
.I5(rescnt_reg[6]),
.O(\rescnt[3]_i_8_n_0 ));
LUT2 #(
.INIT(4'hE))
\rescnt[6]_i_2
(.I0(rst_in_sync),
.I1(rescnt_reg[4]),
.O(L[4]));
LUT2 #(
.INIT(4'hE))
\rescnt[6]_i_3
(.I0(rst_in_sync),
.I1(rescnt_reg[3]),
.O(L[3]));
LUT3 #(
.INIT(8'hF9))
\rescnt[6]_i_4
(.I0(rescnt_reg[5]),
.I1(rescnt_reg[6]),
.I2(rst_in_sync),
.O(\rescnt[6]_i_4_n_0 ));
LUT3 #(
.INIT(8'hF9))
\rescnt[6]_i_5
(.I0(rescnt_reg[4]),
.I1(rescnt_reg[5]),
.I2(rst_in_sync),
.O(\rescnt[6]_i_5_n_0 ));
LUT3 #(
.INIT(8'hF9))
\rescnt[6]_i_6
(.I0(rescnt_reg[3]),
.I1(rescnt_reg[4]),
.I2(rst_in_sync),
.O(\rescnt[6]_i_6_n_0 ));
FDRE #(
.INIT(1'b1))
\rescnt_reg[0]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[0]),
.Q(rescnt_reg[0]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[1]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[1]),
.Q(rescnt_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[2]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[2]),
.Q(rescnt_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[3]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[3]),
.Q(rescnt_reg[3]),
.R(1'b0));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \rescnt_reg[3]_i_1
(.CI(1'b0),
.CO({\rescnt_reg[3]_i_1_n_0 ,\rescnt_reg[3]_i_1_n_1 ,\rescnt_reg[3]_i_1_n_2 ,\rescnt_reg[3]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({L[2],rst_sig,rst_sig_i_1_n_0,L[0]}),
.O(rescnt[3:0]),
.S({\rescnt[3]_i_5_n_0 ,\rescnt[3]_i_6_n_0 ,\rescnt[3]_i_7_n_0 ,\rescnt[3]_i_8_n_0 }));
FDRE #(
.INIT(1'b1))
\rescnt_reg[4]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[4]),
.Q(rescnt_reg[4]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[5]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[5]),
.Q(rescnt_reg[5]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[6]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[6]),
.Q(rescnt_reg[6]),
.R(1'b0));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \rescnt_reg[6]_i_1
(.CI(\rescnt_reg[3]_i_1_n_0 ),
.CO({\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED [3:2],\rescnt_reg[6]_i_1_n_2 ,\rescnt_reg[6]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,L[4:3]}),
.O({\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED [3],rescnt[6:4]}),
.S({1'b0,\rescnt[6]_i_4_n_0 ,\rescnt[6]_i_5_n_0 ,\rescnt[6]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
rst_in_sync_reg
(.C(clk_in),
.CE(1'b1),
.D(rst_in),
.Q(rst_in_sync),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
rst_n_INST_0
(.I0(rst_sig_reg_n_0),
.O(rst_n));
LUT5 #(
.INIT(32'hFFFFFFFE))
rst_sig_i_1
(.I0(rst_sig_i_2_n_0),
.I1(rescnt_reg[5]),
.I2(rst_in_sync),
.I3(rescnt_reg[4]),
.I4(rescnt_reg[6]),
.O(rst_sig_i_1_n_0));
LUT5 #(
.INIT(32'hFFFFFFFE))
rst_sig_i_2
(.I0(rescnt_reg[2]),
.I1(rescnt_reg[3]),
.I2(rst_in_sync),
.I3(rescnt_reg[0]),
.I4(rescnt_reg[1]),
.O(rst_sig_i_2_n_0));
FDRE #(
.INIT(1'b0))
rst_sig_reg
(.C(clk_in),
.CE(1'b1),
.D(rst_sig_i_1_n_0),
.Q(rst_sig_reg_n_0),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_contr_0_0/crc_axi_master_syn_crc_axi_master_contr_0_0_stub.v → Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_stub.v
+12 -15
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@@ -2,11 +2,11 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Jan 29 16:44:19 2025
// Date : Wed Jan 29 20:15:54 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_contr_0_0/crc_axi_master_syn_crc_axi_master_contr_0_0_stub.v
// Design : crc_axi_master_syn_crc_axi_master_contr_0_0
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_stub.v
// Design : design_1_clk_rst_generator_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
@@ -14,17 +14,14 @@
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "crc_axi_master_control,Vivado 2023.1" *)
module crc_axi_master_syn_crc_axi_master_contr_0_0(clk, resetn, finished, start, write, addr, size,
axi_idle)
/* synthesis syn_black_box black_box_pad_pin="resetn,finished,start,write,addr[31:0],size[15:0],axi_idle" */
(* x_core_info = "clk_rst_generator,Vivado 2023.1" *)
module design_1_clk_rst_generator_0_0(clk_in, rst_in, clk, rst_n, stop_simulation)
/* synthesis syn_black_box black_box_pad_pin="rst_in,rst_n,stop_simulation" */
/* synthesis syn_force_seq_prim="clk_in" */
/* synthesis syn_force_seq_prim="clk" */;
input clk /* synthesis syn_isclock = 1 */;
input resetn;
output finished;
output start;
output write;
output [31:0]addr;
output [15:0]size;
input axi_idle;
input clk_in /* synthesis syn_isclock = 1 */;
input rst_in;
output clk /* synthesis syn_isclock = 1 */;
output rst_n;
input stop_simulation;
endmodule
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/mref/axi3_slave_verif/component.xml
+6 -3
View File
@@ -305,7 +305,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>071924d0</spirit:value>
<spirit:value>8d98269c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -318,7 +318,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>071924d0</spirit:value>
<spirit:value>8d98269c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -581,6 +581,9 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
@@ -903,7 +906,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-01-29T16:20:59Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2025-01-29T18:57:52Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/mref/crc_axi_master/component.xml
+4 -4
View File
@@ -355,7 +355,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>37658bac</spirit:value>
<spirit:value>b2f7b025</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -368,7 +368,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>37658bac</spirit:value>
<spirit:value>b2f7b025</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -456,7 +456,7 @@
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">15</spirit:left>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -1231,7 +1231,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-01-29T12:10:45Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2025-01-29T19:04:49Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/mref/crc_axi_master_control/component.xml
+4 -4
View File
@@ -61,7 +61,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>055f3bd0</spirit:value>
<spirit:value>fce8410b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -74,7 +74,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>055f3bd0</spirit:value>
<spirit:value>fce8410b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -187,7 +187,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">15</spirit:left>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -257,7 +257,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-01-29T15:39:47Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2025-01-29T19:25:50Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/mref/crc_axi_master_sim_control/component.xml
+4 -4
View File
@@ -61,7 +61,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>8844eaca</spirit:value>
<spirit:value>71378371</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -74,7 +74,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>8844eaca</spirit:value>
<spirit:value>71378371</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -171,7 +171,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">15</spirit:left>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -241,7 +241,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-01-29T11:24:01Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2025-01-29T18:53:19Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bd
+287 -287
View File
@@ -14,8 +14,8 @@
"clk_rst_generator_0": "",
"crc_axi_ram_0": "",
"crc_axi_master_sim_c_0": "",
"crc_axi_master_0": "",
"axi3_slave_verif_0": ""
"axi3_slave_verif_0": "",
"crc_axi_master_0": ""
},
"components": {
"clk_rst_generator_0": {
@@ -111,7 +111,7 @@
},
"size": {
"direction": "O",
"left": "15",
"left": "3",
"right": "0"
},
"axi_idle": {
@@ -119,6 +119,285 @@
}
}
},
"axi3_slave_verif_0": {
"vlnv": "xilinx.com:module_ref:axi3_slave_verif:1.0",
"xci_name": "crc_axi_master_sim_axi3_slave_verif_0_0",
"xci_path": "ip\\crc_axi_master_sim_axi3_slave_verif_0_0\\crc_axi_master_sim_axi3_slave_verif_0_0.xci",
"inst_hier_path": "axi3_slave_verif_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "axi3_slave_verif",
"boundary_crc": "0x0"
},
"interface_ports": {
"S_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"parameters": {
"DATA_WIDTH": {
"value": "32",
"value_src": "auto"
},
"PROTOCOL": {
"value": "AXI3",
"value_src": "constant"
},
"ID_WIDTH": {
"value": "1",
"value_src": "auto"
},
"ADDR_WIDTH": {
"value": "32",
"value_src": "constant"
},
"AWUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"ARUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"WUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"RUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"BUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"READ_WRITE_MODE": {
"value": "READ_WRITE",
"value_src": "constant"
},
"HAS_BURST": {
"value": "1",
"value_src": "constant"
},
"HAS_LOCK": {
"value": "0",
"value_src": "constant"
},
"HAS_PROT": {
"value": "0",
"value_src": "constant"
},
"HAS_CACHE": {
"value": "0",
"value_src": "constant"
},
"HAS_QOS": {
"value": "0",
"value_src": "constant"
},
"HAS_REGION": {
"value": "0",
"value_src": "constant"
},
"HAS_WSTRB": {
"value": "1",
"value_src": "constant"
},
"HAS_BRESP": {
"value": "1",
"value_src": "constant"
},
"HAS_RRESP": {
"value": "1",
"value_src": "constant"
},
"SUPPORTS_NARROW_BURST": {
"value": "1",
"value_src": "auto"
},
"NUM_READ_OUTSTANDING": {
"value": "2",
"value_src": "auto"
},
"NUM_WRITE_OUTSTANDING": {
"value": "2",
"value_src": "auto"
},
"MAX_BURST_LENGTH": {
"value": "16",
"value_src": "auto"
}
},
"memory_map_ref": "S_AXI",
"port_maps": {
"AWADDR": {
"physical_name": "S_AXI_AWADDR",
"direction": "I",
"left": "31",
"right": "0"
},
"AWLEN": {
"physical_name": "S_AXI_AWLEN",
"direction": "I",
"left": "3",
"right": "0"
},
"AWSIZE": {
"physical_name": "S_AXI_AWSIZE",
"direction": "I",
"left": "2",
"right": "0"
},
"AWBURST": {
"physical_name": "S_AXI_AWBURST",
"direction": "I",
"left": "1",
"right": "0"
},
"AWVALID": {
"physical_name": "S_AXI_AWVALID",
"direction": "I"
},
"AWREADY": {
"physical_name": "S_AXI_AWREADY",
"direction": "O"
},
"WDATA": {
"physical_name": "S_AXI_WDATA",
"direction": "I",
"left": "31",
"right": "0"
},
"WSTRB": {
"physical_name": "S_AXI_WSTRB",
"direction": "I",
"left": "3",
"right": "0"
},
"WLAST": {
"physical_name": "S_AXI_WLAST",
"direction": "I"
},
"WVALID": {
"physical_name": "S_AXI_WVALID",
"direction": "I"
},
"WREADY": {
"physical_name": "S_AXI_WREADY",
"direction": "O"
},
"BRESP": {
"physical_name": "S_AXI_BRESP",
"direction": "O",
"left": "1",
"right": "0"
},
"BVALID": {
"physical_name": "S_AXI_BVALID",
"direction": "O"
},
"BREADY": {
"physical_name": "S_AXI_BREADY",
"direction": "I"
},
"ARID": {
"physical_name": "S_AXI_ARID",
"direction": "I",
"left": "0",
"right": "0"
},
"ARADDR": {
"physical_name": "S_AXI_ARADDR",
"direction": "I",
"left": "31",
"right": "0"
},
"ARLEN": {
"physical_name": "S_AXI_ARLEN",
"direction": "I",
"left": "3",
"right": "0"
},
"ARSIZE": {
"physical_name": "S_AXI_ARSIZE",
"direction": "I",
"left": "2",
"right": "0"
},
"ARBURST": {
"physical_name": "S_AXI_ARBURST",
"direction": "I",
"left": "1",
"right": "0"
},
"ARVALID": {
"physical_name": "S_AXI_ARVALID",
"direction": "I"
},
"ARREADY": {
"physical_name": "S_AXI_ARREADY",
"direction": "O"
},
"RID": {
"physical_name": "S_AXI_RID",
"direction": "O",
"left": "0",
"right": "0"
},
"RDATA": {
"physical_name": "S_AXI_RDATA",
"direction": "O",
"left": "31",
"right": "0"
},
"RRESP": {
"physical_name": "S_AXI_RRESP",
"direction": "O",
"left": "1",
"right": "0"
},
"RLAST": {
"physical_name": "S_AXI_RLAST",
"direction": "O"
},
"RVALID": {
"physical_name": "S_AXI_RVALID",
"direction": "O"
},
"RREADY": {
"physical_name": "S_AXI_RREADY",
"direction": "I"
}
}
}
},
"ports": {
"CLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "RESETN",
"value_src": "constant"
}
}
},
"RESETN": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
}
}
},
"crc_axi_master_0": {
"vlnv": "xilinx.com:module_ref:crc_axi_master:1.0",
"xci_name": "crc_axi_master_sim_crc_axi_master_0_2",
@@ -456,7 +735,7 @@
},
"size": {
"direction": "I",
"left": "15",
"left": "3",
"right": "0"
},
"ip_idle": {
@@ -497,285 +776,6 @@
}
}
}
},
"axi3_slave_verif_0": {
"vlnv": "xilinx.com:module_ref:axi3_slave_verif:1.0",
"xci_name": "crc_axi_master_sim_axi3_slave_verif_0_0",
"xci_path": "ip\\crc_axi_master_sim_axi3_slave_verif_0_0\\crc_axi_master_sim_axi3_slave_verif_0_0.xci",
"inst_hier_path": "axi3_slave_verif_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "axi3_slave_verif",
"boundary_crc": "0x0"
},
"interface_ports": {
"S_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"parameters": {
"DATA_WIDTH": {
"value": "32",
"value_src": "auto"
},
"PROTOCOL": {
"value": "AXI3",
"value_src": "constant"
},
"ID_WIDTH": {
"value": "1",
"value_src": "auto"
},
"ADDR_WIDTH": {
"value": "32",
"value_src": "constant"
},
"AWUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"ARUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"WUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"RUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"BUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"READ_WRITE_MODE": {
"value": "READ_WRITE",
"value_src": "constant"
},
"HAS_BURST": {
"value": "1",
"value_src": "constant"
},
"HAS_LOCK": {
"value": "0",
"value_src": "constant"
},
"HAS_PROT": {
"value": "0",
"value_src": "constant"
},
"HAS_CACHE": {
"value": "0",
"value_src": "constant"
},
"HAS_QOS": {
"value": "0",
"value_src": "constant"
},
"HAS_REGION": {
"value": "0",
"value_src": "constant"
},
"HAS_WSTRB": {
"value": "1",
"value_src": "constant"
},
"HAS_BRESP": {
"value": "1",
"value_src": "constant"
},
"HAS_RRESP": {
"value": "1",
"value_src": "constant"
},
"SUPPORTS_NARROW_BURST": {
"value": "1",
"value_src": "auto"
},
"NUM_READ_OUTSTANDING": {
"value": "2",
"value_src": "auto"
},
"NUM_WRITE_OUTSTANDING": {
"value": "2",
"value_src": "auto"
},
"MAX_BURST_LENGTH": {
"value": "16",
"value_src": "auto"
}
},
"memory_map_ref": "S_AXI",
"port_maps": {
"AWADDR": {
"physical_name": "S_AXI_AWADDR",
"direction": "I",
"left": "31",
"right": "0"
},
"AWLEN": {
"physical_name": "S_AXI_AWLEN",
"direction": "I",
"left": "3",
"right": "0"
},
"AWSIZE": {
"physical_name": "S_AXI_AWSIZE",
"direction": "I",
"left": "2",
"right": "0"
},
"AWBURST": {
"physical_name": "S_AXI_AWBURST",
"direction": "I",
"left": "1",
"right": "0"
},
"AWVALID": {
"physical_name": "S_AXI_AWVALID",
"direction": "I"
},
"AWREADY": {
"physical_name": "S_AXI_AWREADY",
"direction": "O"
},
"WDATA": {
"physical_name": "S_AXI_WDATA",
"direction": "I",
"left": "31",
"right": "0"
},
"WSTRB": {
"physical_name": "S_AXI_WSTRB",
"direction": "I",
"left": "3",
"right": "0"
},
"WLAST": {
"physical_name": "S_AXI_WLAST",
"direction": "I"
},
"WVALID": {
"physical_name": "S_AXI_WVALID",
"direction": "I"
},
"WREADY": {
"physical_name": "S_AXI_WREADY",
"direction": "O"
},
"BRESP": {
"physical_name": "S_AXI_BRESP",
"direction": "O",
"left": "1",
"right": "0"
},
"BVALID": {
"physical_name": "S_AXI_BVALID",
"direction": "O"
},
"BREADY": {
"physical_name": "S_AXI_BREADY",
"direction": "I"
},
"ARID": {
"physical_name": "S_AXI_ARID",
"direction": "I",
"left": "0",
"right": "0"
},
"ARADDR": {
"physical_name": "S_AXI_ARADDR",
"direction": "I",
"left": "31",
"right": "0"
},
"ARLEN": {
"physical_name": "S_AXI_ARLEN",
"direction": "I",
"left": "3",
"right": "0"
},
"ARSIZE": {
"physical_name": "S_AXI_ARSIZE",
"direction": "I",
"left": "2",
"right": "0"
},
"ARBURST": {
"physical_name": "S_AXI_ARBURST",
"direction": "I",
"left": "1",
"right": "0"
},
"ARVALID": {
"physical_name": "S_AXI_ARVALID",
"direction": "I"
},
"ARREADY": {
"physical_name": "S_AXI_ARREADY",
"direction": "O"
},
"RID": {
"physical_name": "S_AXI_RID",
"direction": "O",
"left": "0",
"right": "0"
},
"RDATA": {
"physical_name": "S_AXI_RDATA",
"direction": "O",
"left": "31",
"right": "0"
},
"RRESP": {
"physical_name": "S_AXI_RRESP",
"direction": "O",
"left": "1",
"right": "0"
},
"RLAST": {
"physical_name": "S_AXI_RLAST",
"direction": "O"
},
"RVALID": {
"physical_name": "S_AXI_RVALID",
"direction": "O"
},
"RREADY": {
"physical_name": "S_AXI_RREADY",
"direction": "I"
}
}
}
},
"ports": {
"CLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "RESETN",
"value_src": "constant"
}
}
},
"RESETN": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
}
}
}
},
"interface_nets": {
@@ -792,16 +792,16 @@
"clk_rst_generator_0/clk",
"crc_axi_ram_0/clk",
"crc_axi_master_sim_c_0/clk",
"crc_axi_master_0/CLK",
"axi3_slave_verif_0/CLK"
"axi3_slave_verif_0/CLK",
"crc_axi_master_0/CLK"
]
},
"clk_rst_generator_0_rst_n": {
"ports": [
"clk_rst_generator_0/rst_n",
"crc_axi_master_sim_c_0/resetn",
"crc_axi_master_0/RESETN",
"axi3_slave_verif_0/RESETN"
"axi3_slave_verif_0/RESETN",
"crc_axi_master_0/RESETN"
]
},
"crc_axi_master_0_idle": {
Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi3_slave_verif_0_0/crc_axi_master_sim_axi3_slave_verif_0_0.xci
+1 -1
View File
@@ -58,7 +58,7 @@
"S_AXI_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"S_AXI_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
"S_AXI_RID": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
"S_AXI_RLAST": [ { "direction": "out" } ],
"S_AXI_RLAST": [ { "direction": "out", "driver_value": "0x0" } ],
"S_AXI_AWVALID": [ { "direction": "in", "driver_value": "0" } ],
"S_AXI_AWREADY": [ { "direction": "out", "driver_value": "0x0" } ],
"S_AXI_AWADDR": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_0_2/crc_axi_master_sim_crc_axi_master_0_2.xci
+18 -18
View File
@@ -51,7 +51,7 @@
"start": [ { "direction": "in" } ],
"write": [ { "direction": "in" } ],
"addr_axi": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
"size": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
"size": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
"ip_idle": [ { "direction": "out" } ],
"waddr": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
"wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
@@ -102,25 +102,25 @@
"address_space_ref": "M_AXI",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_sim_c_0_0/crc_axi_master_sim_crc_axi_master_sim_c_0_0.xci
+1 -1
View File
@@ -41,7 +41,7 @@
"start": [ { "direction": "out", "driver_value": "0x0" } ],
"write": [ { "direction": "out", "driver_value": "0x0" } ],
"addr": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"size": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"size": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"axi_idle": [ { "direction": "in" } ]
},
"interfaces": {
Hardware/crc_axi_master/crc_axi_master.srcs/crc_axi_master/bd/crc_axi_master_sim/ui/bd_384b0fb2.ui
+16 -15
View File
@@ -1,30 +1,31 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.22266",
"Default View_TopLeft":"71,-249",
"Default View_ScaleFactor":"1.98622",
"Default View_TopLeft":"97,173",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 90 -y 160 -defaultsOSRD
preplace inst crc_axi_ram_0 -pg 1 -lvl 2 -x 400 -y 420 -defaultsOSRD
preplace inst crc_axi_master_sim_c_0 -pg 1 -lvl 2 -x 400 -y 170 -defaultsOSRD
preplace inst crc_axi_master_0 -pg 1 -lvl 3 -x 750 -y 0 -defaultsOSRD
preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 1040 -y 10 -defaultsOSRD
preplace netloc clk_rst_generator_0_clk 1 1 2 200 -60 N
preplace netloc clk_rst_generator_0_rst_n 1 1 2 210 -40 N
preplace netloc crc_axi_master_0_idle 1 1 3 230 -120 NJ -120 880
preplace netloc crc_axi_master_0_raddr 1 1 3 220 40 540J 120 890
preplace netloc crc_axi_master_0_re 1 1 3 240 50 600J 130 880
preplace netloc crc_axi_master_0_waddr 1 1 3 250 60 580J 140 920
preplace netloc crc_axi_master_0_wdata 1 1 3 270 80 550J 160 910
preplace netloc crc_axi_master_0_we 1 1 3 260 70 570J 150 900
preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 1070 -y 10 -defaultsOSRD
preplace inst crc_axi_master_0 -pg 1 -lvl 3 -x 760 -y 0 -defaultsOSRD
preplace netloc clk_rst_generator_0_clk 1 1 3 200 10 530 -120 950
preplace netloc clk_rst_generator_0_rst_n 1 1 3 210 30 630 120 950
preplace netloc crc_axi_master_0_idle 1 1 3 250 60 580J 130 920
preplace netloc crc_axi_master_0_raddr 1 1 3 220 40 600J 140 900
preplace netloc crc_axi_master_0_re 1 1 3 240 50 570J 150 890
preplace netloc crc_axi_master_0_waddr 1 1 3 260 70 550J 160 930
preplace netloc crc_axi_master_0_wdata 1 1 3 230 -130 NJ -130 890
preplace netloc crc_axi_master_0_we 1 1 3 270 80 530J 170 910
preplace netloc crc_axi_master_sim_c_0_addr 1 2 1 590 20n
preplace netloc crc_axi_master_sim_c_0_size 1 2 1 610 40n
preplace netloc crc_axi_master_sim_c_0_start 1 2 1 560 -20n
preplace netloc crc_axi_master_sim_c_0_write 1 2 1 530 0n
preplace netloc crc_axi_master_sim_c_0_write 1 2 1 540 0n
preplace netloc crc_axi_ram_0_rdata 1 2 1 620 60n
levelinfo -pg 1 -20 90 400 750 1040 1130
pagesize -pg 1 -db -bbox -sgen -20 -130 1280 530
preplace netloc crc_axi_master_0_M_AXI 1 3 1 940 -60n
levelinfo -pg 1 -20 90 400 760 1070 1170
pagesize -pg 1 -db -bbox -sgen -20 -150 1280 530
"
}
0
Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/crc_axi_master_syn.bd
+3 -12
View File
@@ -7,8 +7,7 @@
"name": "crc_axi_master_syn",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2023.1",
"validated": "true"
"tool_version": "2023.1"
},
"design_tree": {
"system_ila_0": "",
@@ -2144,7 +2143,7 @@
},
"size": {
"direction": "I",
"left": "15",
"left": "3",
"right": "0"
},
"ip_idle": {
@@ -2204,14 +2203,6 @@
"ASSOCIATED_RESET": {
"value": "resetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "user_prop"
},
"CLK_DOMAIN": {
"value": "crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0",
"value_src": "default_prop"
}
}
},
@@ -2241,7 +2232,7 @@
},
"size": {
"direction": "O",
"left": "15",
"left": "3",
"right": "0"
},
"axi_idle": {
Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_0_0/crc_axi_master_syn_crc_axi_master_0_0.xci
+18 -18
View File
@@ -51,7 +51,7 @@
"start": [ { "direction": "in" } ],
"write": [ { "direction": "in" } ],
"addr_axi": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
"size": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
"size": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
"ip_idle": [ { "direction": "out" } ],
"waddr": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
"wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
@@ -102,25 +102,25 @@
"address_space_ref": "M_AXI",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_contr_0_0/crc_axi_master_syn_crc_axi_master_contr_0_0.xci
+3 -3
View File
@@ -42,7 +42,7 @@
"start": [ { "direction": "out", "driver_value": "0x0" } ],
"write": [ { "direction": "out", "driver_value": "0x0" } ],
"addr": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"size": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"size": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"axi_idle": [ { "direction": "in" } ]
},
"interfaces": {
@@ -64,10 +64,10 @@
"mode": "slave",
"parameters": {
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/crc_axi_master_syn_system_ila_0_0.xci
+1 -1
View File
@@ -3867,7 +3867,7 @@
"clk": [ { "direction": "in" } ],
"probe0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"probe1": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"probe2": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"probe2": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"probe3": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"probe4": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"probe5": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
Hardware/crc_axi_master/crc_axi_master.srcs/sources_1/bd/crc_axi_master_syn/ui/bd_21362b23.ui
+14 -14
View File
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"3.07786",
"Default View_TopLeft":"428,114",
"Default View_ScaleFactor":"1.40656",
"Default View_TopLeft":"10,-63",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
@@ -11,24 +11,24 @@ preplace inst system_ila_0 -pg 1 -lvl 3 -x 840 -y 140 -defaultsOSRD
preplace inst Processing_System -pg 1 -lvl 3 -x 840 -y 400 -defaultsOSRD
preplace inst crc_axi_master_0 -pg 1 -lvl 2 -x 460 -y 340 -defaultsOSRD
preplace inst crc_axi_master_contr_0 -pg 1 -lvl 1 -x 150 -y 120 -defaultsOSRD
preplace netloc crc_axi_master_0_ip_idle 1 0 3 40 220 NJ 220 610
preplace netloc crc_axi_master_0_ip_idle 1 0 3 40 220 NJ 220 590
preplace netloc crc_axi_master_contr_0_addr 1 1 2 310 70 NJ
preplace netloc crc_axi_master_contr_0_size 1 1 2 320 90 NJ
preplace netloc crc_axi_master_contr_0_start 1 1 2 330 110 NJ
preplace netloc crc_axi_master_contr_0_write 1 1 2 300 130 NJ
preplace netloc finished 1 1 2 N 80 640J
preplace netloc processing_system7_0_FCLK_CLK0 1 0 4 30 230 290 460 630 490 980
preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 4 20 240 280 470 680 480 970
preplace netloc wdata 1 2 1 670 250n
preplace netloc waddr 1 2 1 640 230n
preplace netloc we 1 2 1 690 270n
preplace netloc re 1 2 1 620 210n
preplace netloc raddr 1 2 1 660 190n
preplace netloc crc_axi_master_0_M_AXI 1 2 1 650 10n
preplace netloc finished 1 1 2 N 80 610J
preplace netloc processing_system7_0_FCLK_CLK0 1 0 4 30 230 290 460 680 480 980
preplace netloc raddr 1 2 1 620 170n
preplace netloc re 1 2 1 600 190n
preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 4 20 240 280 470 710 490 970
preplace netloc waddr 1 2 1 610 210n
preplace netloc wdata 1 2 1 690 230n
preplace netloc we 1 2 1 700 250n
preplace netloc crc_axi_master_0_M_AXI 1 2 1 670 10n
preplace netloc processing_system7_0_DDR 1 3 1 970J 310n
preplace netloc processing_system7_0_FIXED_IO 1 3 1 980J 340n
levelinfo -pg 1 0 150 460 840 1000
pagesize -pg 1 -db -bbox -sgen 0 -50 1110 500
levelinfo -pg 1 -10 150 460 840 1000
pagesize -pg 1 -db -bbox -sgen -10 -50 1110 500
"
}
{
Hardware/crc_axi_master/crc_axi_master.xpr
+122 -162
View File
@@ -61,20 +61,20 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="zybo-z7-20"/>
<Option Name="WTXSimLaunchSim" Val="59"/>
<Option Name="WTXSimLaunchSim" Val="77"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="27"/>
<Option Name="WTModelSimExportSim" Val="27"/>
<Option Name="WTQuestaExportSim" Val="27"/>
<Option Name="WTXSimExportSim" Val="44"/>
<Option Name="WTModelSimExportSim" Val="44"/>
<Option Name="WTQuestaExportSim" Val="44"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="27"/>
<Option Name="WTRivieraExportSim" Val="27"/>
<Option Name="WTActivehdlExportSim" Val="27"/>
<Option Name="WTVcsExportSim" Val="44"/>
<Option Name="WTRivieraExportSim" Val="44"/>
<Option Name="WTActivehdlExportSim" Val="44"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -92,8 +92,45 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../crc_axi_master.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../crc_axi_master_control.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/crc_axi_master_syn/crc_axi_master_syn.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_crc_axi_master_0_0/crc_axi_master_syn_crc_axi_master_0_0.xci">
<Proxy FileSetName="crc_axi_master_syn_crc_axi_master_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_system_ila_0_0/crc_axi_master_syn_system_ila_0_0.xci">
<Proxy FileSetName="crc_axi_master_syn_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_rst_ps7_0_100M_0/crc_axi_master_syn_rst_ps7_0_100M_0.xci">
<Proxy FileSetName="crc_axi_master_syn_rst_ps7_0_100M_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xci">
<Proxy FileSetName="crc_axi_master_syn_processing_system7_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/crc_axi_master_syn/hdl/crc_axi_master_syn_wrapper.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -104,55 +141,20 @@
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci">
<Proxy FileSetName="design_1_axil_master_with_rom_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci">
<Proxy FileSetName="design_1_clk_rst_generator_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_vip_0_0/design_1_axi_vip_0_0.xci">
<Proxy FileSetName="design_1_axi_vip_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci">
<Proxy FileSetName="design_1_clk_rst_generator_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../crc_axi_master_control.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../crc_axi_master.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/crc_axi_master_syn/crc_axi_master_syn.bd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_system_ila_0_0/crc_axi_master_syn_system_ila_0_0.xci">
<Proxy FileSetName="crc_axi_master_syn_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_crc_axi_master_contr_0_0/crc_axi_master_syn_crc_axi_master_contr_0_0.xci">
<Proxy FileSetName="crc_axi_master_syn_crc_axi_master_contr_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xci">
<Proxy FileSetName="crc_axi_master_syn_processing_system7_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_rst_ps7_0_100M_0/crc_axi_master_syn_rst_ps7_0_100M_0.xci">
<Proxy FileSetName="crc_axi_master_syn_rst_ps7_0_100M_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_crc_axi_master_0_0/crc_axi_master_syn_crc_axi_master_0_0.xci">
<Proxy FileSetName="crc_axi_master_syn_crc_axi_master_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PPRDIR/../crc_axi_master_sim_control.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
@@ -176,8 +178,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="design_1_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TopModule" Val="crc_axi_master_syn_wrapper"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -300,21 +301,15 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="crc_axi_master_syn_crc_axi_master_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/crc_axi_master_syn_crc_axi_master_0_0" RelGenDir="$PGENDIR/crc_axi_master_syn_crc_axi_master_0_0">
<Config>
<Option Name="TopModule" Val="crc_axi_master_syn_crc_axi_master_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="crc_axi_master_syn_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/crc_axi_master_syn_system_ila_0_0" RelGenDir="$PGENDIR/crc_axi_master_syn_system_ila_0_0">
<Config>
<Option Name="TopModule" Val="crc_axi_master_syn_system_ila_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="crc_axi_master_syn_crc_axi_master_contr_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/crc_axi_master_syn_crc_axi_master_contr_0_0" RelGenDir="$PGENDIR/crc_axi_master_syn_crc_axi_master_contr_0_0">
<FileSet Name="crc_axi_master_syn_crc_axi_master_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/crc_axi_master_syn_crc_axi_master_0_0" RelGenDir="$PGENDIR/crc_axi_master_syn_crc_axi_master_0_0">
<Config>
<Option Name="TopModule" Val="crc_axi_master_syn_crc_axi_master_contr_0_0"/>
<Option Name="TopModule" Val="crc_axi_master_syn_crc_axi_master_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
@@ -340,9 +335,7 @@
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/crc_axi_master_syn_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -350,38 +343,42 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_clk_rst_generator_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_rst_generator_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_rst_generator_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_synth_1">
<Run Id="design_1_clk_rst_generator_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_rst_generator_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_rst_generator_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clk_rst_generator_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_axi_vip_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_vip_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axi_vip_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_vip_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_vip_0_0_synth_1">
<Run Id="design_1_axi_vip_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_vip_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axi_vip_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_vip_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_vip_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_vip_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_axi_read_generator_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_read_generator_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axi_read_generator_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_read_generator_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_read_generator_0_0_synth_1">
<Run Id="design_1_axi_read_generator_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_read_generator_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axi_read_generator_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_read_generator_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_read_generator_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_read_generator_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_axil_master_with_rom_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axil_master_with_rom_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axil_master_with_rom_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_synth_1">
<Run Id="design_1_axil_master_with_rom_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axil_master_with_rom_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axil_master_with_rom_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axil_master_with_rom_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
@@ -406,7 +403,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="crc_axi_master_syn_crc_axi_master_0_0_synth_1" Type="Ft3:Synth" SrcSet="crc_axi_master_syn_crc_axi_master_0_0" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_crc_axi_master_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/crc_axi_master_syn_crc_axi_master_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_0_0_synth_1">
<Run Id="crc_axi_master_syn_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="crc_axi_master_syn_system_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/crc_axi_master_syn_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
@@ -416,42 +413,16 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="crc_axi_master_syn_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="crc_axi_master_syn_system_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/crc_axi_master_syn_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="crc_axi_master_syn_crc_axi_master_contr_0_0_synth_1" Type="Ft3:Synth" SrcSet="crc_axi_master_syn_crc_axi_master_contr_0_0" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_crc_axi_master_contr_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/crc_axi_master_syn_crc_axi_master_contr_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_contr_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_contr_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="synth_1_copy_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/crc_axi_master_syn_wrapper.dcp" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1/synth_1_copy_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1_copy_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023" CtrlBit="true">
<ReportConfig DisplayName="synthesis_report" Name="synth_1_copy_1_synth_synthesis_report_0" Spec="" RunStep="synth_design">
<ReportConfig DisplayName="synthesis_report" Name="synth_1_copy_1_synth_synthesis_report_0" Spec="" RunStep="synth_design" ReportFile="design_1_wrapper.vds">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Utilization - Synth Design" Name="synth_1_copy_1_synth_report_utilization_0" Spec="report_utilization" RunStep="synth_design" Version="1" Minor="0">
<ReportConfig DisplayName="Utilization - Synth Design" Name="synth_1_copy_1_synth_report_utilization_0" Spec="report_utilization" RunStep="synth_design" ReportFile="design_1_wrapper_utilization_synth.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
</ReportConfig>
@@ -459,11 +430,21 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="crc_axi_master_syn_crc_axi_master_0_0_synth_1" Type="Ft3:Synth" SrcSet="crc_axi_master_syn_crc_axi_master_0_0" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_crc_axi_master_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/crc_axi_master_syn_crc_axi_master_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -581,7 +562,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="crc_axi_master_syn_crc_axi_master_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_crc_axi_master_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="crc_axi_master_syn_crc_axi_master_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_0_0_impl_1">
<Run Id="crc_axi_master_syn_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="crc_axi_master_syn_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
@@ -598,49 +579,9 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="crc_axi_master_syn_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="crc_axi_master_syn_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="crc_axi_master_syn_crc_axi_master_contr_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_crc_axi_master_contr_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="crc_axi_master_syn_crc_axi_master_contr_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_contr_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_contr_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1_copy_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -652,124 +593,143 @@
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023" CtrlBit="true">
<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="design_1_wrapper_timing_summary_init.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" Version="1" Minor="0">
<ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" ReportFile="design_1_wrapper_drc_opted.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_1_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_1_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" ReportFile="design_1_wrapper_timing_summary_opted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="design_1_wrapper_timing_summary_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_1_place_report_io_0" Spec="report_io" RunStep="place_design" Version="1" Minor="0">
<ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_1_place_report_io_0" Spec="report_io" RunStep="place_design" ReportFile="design_1_wrapper_io_placed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_1_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" Version="1" Minor="0">
<ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_1_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" ReportFile="design_1_wrapper_utilization_placed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_1_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" Version="1" Minor="0">
<ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_1_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" ReportFile="design_1_wrapper_control_sets_placed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="verbose" Type="" Value="true"/>
</ReportConfig>
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="design_1_wrapper_incremental_reuse_pre_placed.rpt.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="design_1_wrapper_incremental_reuse_placed.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="design_1_wrapper_timing_summary_placed.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="design_1_wrapper_timing_summary_postplace_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="design_1_wrapper_timing_summary_physopted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_route_implementation_log_0" Spec="" RunStep="route_design">
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_route_implementation_log_0" Spec="" RunStep="route_design" ReportFile="design_1_wrapper.vdi">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_1_route_report_drc_0" Spec="report_drc" RunStep="route_design" Version="1" Minor="0">
<ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_1_route_report_drc_0" Spec="report_drc" RunStep="route_design" ReportFile="design_1_wrapper_drc_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_1_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" Version="1" Minor="0">
<ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_1_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" ReportFile="design_1_wrapper_methodology_drc_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_1_route_report_power_0" Spec="report_power" RunStep="route_design" Version="1" Minor="0">
<ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_1_route_report_power_0" Spec="report_power" RunStep="route_design" ReportFile="design_1_wrapper_power_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_1_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" Version="1" Minor="0">
<ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_1_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" ReportFile="design_1_wrapper_route_status.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_1_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" Version="1" Minor="0">
<ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_1_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" ReportFile="design_1_wrapper_timing_summary_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_1_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" Version="1" Minor="0">
<ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_1_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" ReportFile="design_1_wrapper_incremental_reuse_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_1_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" Version="1" Minor="0">
<ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_1_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" ReportFile="design_1_wrapper_clock_utilization_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_1_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" Version="1" Minor="1">
<ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_1_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" ReportFile="design_1_wrapper_bus_skew_routed.rpt" Version="1" Minor="1">
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" Version="1" Minor="0">
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="design_1_wrapper_timing_summary_postroute_physopted.rpt" Version="1" Minor="0">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" Version="1" Minor="1">
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="design_1_wrapper_bus_skew_postroute_physopted.rpt" Version="1" Minor="1">
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="report_webtalk" Name="impl_1_copy_1_bitstream_report_webtalk_0" Spec="" RunStep="write_bitstream">
<ReportConfig DisplayName="report_webtalk" Name="impl_1_copy_1_bitstream_report_webtalk_0" Spec="" RunStep="write_bitstream" ReportFile="usage_statistics_webtalk.html">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream">
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream" ReportFile="design_1_wrapper.vdi">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
</ReportStrategy>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="crc_axi_master_syn_crc_axi_master_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_crc_axi_master_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="crc_axi_master_syn_crc_axi_master_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_crc_axi_master_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
Hardware/crc_axi_master/crc_axi_master_sim_wrapper_behav.wcfg
+55 -25
View File
@@ -11,15 +11,15 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="1,334.744 ns"></ZoomStartTime>
<ZoomEndTime time="1,353.583 ns"></ZoomEndTime>
<Cursor1Time time="1,366.598 ns"></Cursor1Time>
<ZoomStartTime time="1,597.000 ns"></ZoomStartTime>
<ZoomEndTime time="1,651.266 ns"></ZoomEndTime>
<Cursor1Time time="1,390.091 ns"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="366"></NameColumnWidth>
<ValueColumnWidth column_width="175"></ValueColumnWidth>
<NameColumnWidth column_width="379"></NameColumnWidth>
<ValueColumnWidth column_width="149"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="17" />
<WVObjectSize size="24" />
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/clk_rst_generator_0_clk" type="logic">
<obj_property name="ElementShortName">clk_rst_generator_0_clk</obj_property>
<obj_property name="ObjectShortName">clk_rst_generator_0_clk</obj_property>
@@ -45,13 +45,18 @@
<obj_property name="ObjectShortName">addr[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_sim_c_0/size" type="array">
<obj_property name="ElementShortName">size[15:0]</obj_property>
<obj_property name="ObjectShortName">size[15:0]</obj_property>
<obj_property name="ElementShortName">size[3:0]</obj_property>
<obj_property name="ObjectShortName">size[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider1578">
<obj_property name="label">crc_axi_master</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/ip_idle" type="logic">
<obj_property name="ElementShortName">ip_idle</obj_property>
<obj_property name="ObjectShortName">ip_idle</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/M_AXI" type="protoinst">
<obj_property name="children_use_element_short_name">true</obj_property>
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
@@ -66,17 +71,13 @@
<obj_property name="ObjectShortName">M_AXI</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/U0/state_read" type="other">
<obj_property name="ElementShortName">state_read</obj_property>
<obj_property name="ObjectShortName">state_read</obj_property>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/M_AXI_ARLEN" type="array">
<obj_property name="ElementShortName">M_AXI_ARLEN[3:0]</obj_property>
<obj_property name="ObjectShortName">M_AXI_ARLEN[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/U0/state_write" type="other">
<obj_property name="ElementShortName">state_write</obj_property>
<obj_property name="ObjectShortName">state_write</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/U0/fsm_active" type="logic">
<obj_property name="ElementShortName">fsm_active</obj_property>
<obj_property name="ObjectShortName">fsm_active</obj_property>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/U0/state" type="other">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/U0/addr_buffer" type="array">
<obj_property name="ElementShortName">addr_buffer[3:0]</obj_property>
@@ -86,16 +87,45 @@
<obj_property name="ElementShortName">addr_mem[31:0]</obj_property>
<obj_property name="ObjectShortName">addr_mem[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/U0/data_cnt" type="array">
<obj_property name="ElementShortName">data_cnt[15:0]</obj_property>
<obj_property name="ObjectShortName">data_cnt[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/U0/burst_len" type="array">
<obj_property name="ElementShortName">burst_len[3:0]</obj_property>
<obj_property name="ObjectShortName">burst_len[3:0]</obj_property>
<wvobject type="divider" fp_name="divider622">
<obj_property name="label">AXI Verify</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/axi3_slave_verif_0/U0/state" type="other">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider571">
<obj_property name="label">Block RAM</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/we" type="logic">
<obj_property name="ElementShortName">we</obj_property>
<obj_property name="ObjectShortName">we</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/waddr" type="array">
<obj_property name="ElementShortName">waddr[3:0]</obj_property>
<obj_property name="ObjectShortName">waddr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/wdata" type="array">
<obj_property name="ElementShortName">wdata[31:0]</obj_property>
<obj_property name="ObjectShortName">wdata[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/re" type="logic">
<obj_property name="ElementShortName">re</obj_property>
<obj_property name="ObjectShortName">re</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/raddr" type="array">
<obj_property name="ElementShortName">raddr[3:0]</obj_property>
<obj_property name="ObjectShortName">raddr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/rdata" type="array">
<obj_property name="ElementShortName">rdata[31:0]</obj_property>
<obj_property name="ObjectShortName">rdata[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_ram_0/U0/mem" type="array">
<obj_property name="ElementShortName">mem[0:15][31:0]</obj_property>
<obj_property name="ObjectShortName">mem[0:15][31:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
</wave_config>
Hardware/crc_axi_master_control.vhd
+23 -7
View File
@@ -12,13 +12,13 @@ entity crc_axi_master_control is
start : out std_logic := '0';
write : out std_logic := '0';
addr : out std_logic_vector(31 downto 0) := (others=>'0');
size : out std_logic_vector(15 downto 0) := (others=>'0');
size : out std_logic_vector( 3 downto 0) := (others=>'0');
axi_idle : in std_logic
);
end entity;
architecture rtl of crc_axi_master_control is
type state_t is (STARTUP, TEST_READ, TEST_FINISHED);
type state_t is (STARTUP, TEST_1_READ, TEST_1_FINISHED, TEST_2_READ, TEST_2_FINISHED);
signal state : state_t := STARTUP;
begin
process
@@ -39,21 +39,37 @@ begin
case state is
when STARTUP =>
if cnt = 1250000000 then
state <= TEST_READ;
cnt := (others=>'0');
state <= TEST_1_READ;
else
cnt := cnt + 1;
end if;
when TEST_READ =>
when TEST_1_READ =>
start <= '1';
write <= '0';
addr <= x"30000000"; -- frei verfuegbarer SDRAM Speicher
size <= std_logic_vector(to_unsigned(7, 16));
size <= std_logic_vector(to_unsigned(15, 4));
if axi_idle = '1' then
state <= TEST_FINISHED;
state <= TEST_1_FINISHED;
end if;
when TEST_1_FINISHED =>
if cnt = 100 then
state <= TEST_2_READ;
cnt := (others=>'0');
else
cnt := cnt + 1;
end if;
when TEST_2_READ =>
start <= '1';
write <= '0';
addr <= x"30000040"; -- frei verfuegbarer SDRAM Speicher
size <= std_logic_vector(to_unsigned(5, 4));
when TEST_FINISHED => finished <= '1';
if axi_idle = '1' then
state <= TEST_2_FINISHED;
end if;
when TEST_2_FINISHED => finished <= '1';
when others => null;
end case;
end if;
Hardware/crc_axi_master_sim_control.vhd
+25 -4
View File
@@ -10,7 +10,7 @@ entity crc_axi_master_sim_control is
start : out std_logic := '0';
write : out std_logic := '0';
addr : out std_logic_vector(31 downto 0) := (others=>'0');
size : out std_logic_vector(15 downto 0) := (others=>'0');
size : out std_logic_vector( 3 downto 0) := (others=>'0');
axi_idle : in std_logic
);
end entity;
@@ -27,16 +27,37 @@ begin
end loop;
-- Lesevorgang testen
report "TESTE LESEVORGANG";
report "TESTE LESEVORGANG MIT WORTANZAHL = 1";
start <= '1';
write <= '0';
addr <= x"44A00000"; -- frei verfuegbarer SDRAM Speicher
size <= std_logic_vector(to_unsigned(8, 16));
size <= std_logic_vector(to_unsigned(0, 4));
for i in 1 to 1 loop
wait until rising_edge(clk);
start <= '0';
wait until rising_edge(axi_idle);
for i in 1 to 10 loop
wait until rising_edge(clk);
end loop;
report "TESTELESEVORGANG MIT WORTANZAHL = 16";
size <= std_logic_vector(to_unsigned(15, 4));
start <= '1';
wait until rising_edge(clk);
start <= '0';
wait until rising_edge(axi_idle);
report "TESTELESEVORGANG MIT WORTANZAHL = 10";
size <= std_logic_vector(to_unsigned(9, 4));
start <= '1';
wait until rising_edge(clk);
start <= '0';
wait until rising_edge(axi_idle);