crc_aci_master fertig
This commit is contained in:
Matthias Biermann
+26
-28
@@ -7,7 +7,7 @@ entity crc_axi_master is
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DWIDTH : positive := 32;
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IDWIDTH : positive := 1;
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MAX_BURSTLEN : positive := 16;
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BRAM_AWIDTH : positive := 4
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LUTRAM_AWIDTH : positive := 4
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);
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port (
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CLK : in std_logic;
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@@ -20,11 +20,11 @@ entity crc_axi_master is
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size : in std_logic_vector(3 downto 0);
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ip_idle : out std_logic;
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-- Interface to BRAM
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waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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-- Interface to LUTRAM
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waddr : out std_logic_vector(LUTRAM_AWIDTH-1 downto 0);
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wdata : out std_logic_vector(DWIDTH-1 downto 0);
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we : out std_logic;
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raddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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raddr : out std_logic_vector(LUTRAM_AWIDTH-1 downto 0);
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rdata : in std_logic_vector(DWIDTH-1 downto 0);
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re : out std_logic;
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@@ -72,11 +72,9 @@ architecture rtl of crc_axi_master is
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type state_t is (IDLE, R_REQ, R_WAIT_REQ_ACCEPT, READ_DATA, W_REQ, W_WAIT_REQ_ACCEPT, GET_FIRST_WORD, WRITE_DATA);
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signal state : state_t := IDLE;
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signal addr_buffer : unsigned(BRAM_AWIDTH-1 downto 0) := (others=>'0');
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signal addr_LUTRAM : unsigned(LUTRAM_AWIDTH-1 downto 0) := (others=>'0');
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signal addr_mem : unsigned(31 downto 0) := (others=>'0');
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signal wait_for_end_of_burst : std_logic := '0';
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begin
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--------------------------------
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-- AXI Read/Write Request Engine
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@@ -85,21 +83,27 @@ begin
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M_AXI_ARSIZE <= "010" when DWIDTH=32 else "011"; -- Data width 32/64
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M_AXI_ARBURST <= "01";
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M_AXI_ARPROT <= "000";
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M_AXI_ARCACHE <= "1111";
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M_AXI_ARCACHE <= "0000";
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M_AXI_ARID <= (others=>'0');
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M_AXI_RREADY <= '1';
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M_AXI_AWSIZE <= "010" when DWIDTH=32 else "011"; -- Data width 32/64
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M_AXI_AWBURST <= "01";
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M_AXI_AWPROT <= "000";
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M_AXI_AWCACHE <= "1111";
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M_AXI_AWCACHE <= "0000";
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M_AXI_BREADY <= '1';
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M_AXI_WSTRB <= (others=>'1');
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M_AXI_AWID <= (others=>'0');
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M_AXI_WID <= (others=>'0');
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M_AXI_WDATA <= rdata;
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raddr <= std_logic_vector(addr_buffer);
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-- Interface to LUT Ram
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M_AXI_WDATA <= rdata;
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raddr <= std_logic_vector(addr_LUTRAM);
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re <= '1' when (state = WRITE_DATA) else '0';
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waddr <= std_logic_vector(addr_LUTRAM);
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wdata <= M_AXI_RDATA;
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we <= M_AXI_RVALID;
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process
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variable data_cnt : integer range 0 to MAX_BURSTLEN := 0;
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@@ -119,19 +123,15 @@ begin
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state <= IDLE;
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else
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-- Default values for signals
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we <= '0';
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ip_idle <= '0';
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case state is
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when IDLE =>
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ip_idle <= '1';
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if start = '1' then
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addr_buffer <= (others=>'0');
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addr_LUTRAM <= (others=>'0');
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addr_mem <= unsigned(addr_axi);
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data_cnt := to_integer(unsigned(size))+1;
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ip_idle <= '0';
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if write = '0' then
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state <= R_REQ;
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else
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@@ -154,14 +154,11 @@ begin
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when READ_DATA =>
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if M_AXI_RVALID = '1' then
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waddr <= std_logic_vector(addr_buffer);
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wdata <= M_AXI_RDATA;
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we <= '1';
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addr_buffer <= addr_buffer + 1;
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addr_LUTRAM <= addr_LUTRAM + 1;
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if M_AXI_RLAST = '1' then
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state <= IDLE;
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ip_idle <= '1';
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state <= IDLE;
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end if;
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end if;
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@@ -179,17 +176,17 @@ begin
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if data_cnt = 1 then
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M_AXI_WLAST <= '1';
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end if;
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M_AXI_WVALID <= '1';
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-- re <= '1';
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state <= WRITE_DATA;
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end if;
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when WRITE_DATA =>
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M_AXI_WVALID <= '1';
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re <= '1';
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if M_AXI_WREADY = '1' then
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-- get next word from Block RAM
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data_cnt := data_cnt - 1;
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addr_buffer <= addr_buffer + 1;
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addr_LUTRAM <= addr_LUTRAM + 1;
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if data_cnt = 1 then
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M_AXI_WLAST <= '1';
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@@ -198,7 +195,8 @@ begin
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if data_cnt = 0 then
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M_AXI_WLAST <= '0';
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M_AXI_WVALID <= '0';
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re <= '0';
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-- re <= '0';
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ip_idle <= '1';
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state <= IDLE;
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end if;
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+50
-5
@@ -2,10 +2,55 @@
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<Root MajorVersion="0" MinorVersion="40">
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<CompositeFile CompositeFileTopName="crc_axi_master_sim" CanBeSetAsTop="true" CanDisplayChildGraph="true">
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<Description>Composite Fileset</Description>
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<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738275787"/>
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<Generation Name="SIMULATION" State="RESET" Timestamp="1738275787"/>
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<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738275787"/>
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<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738275787"/>
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<FileCollection Name="SOURCES" Type="SOURCES"/>
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<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738284380"/>
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<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738284380"/>
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<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738284380"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738284380"/>
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<FileCollection Name="SOURCES" Type="SOURCES">
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<File Name="synth\crc_axi_master_sim.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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<Library Name="xil_defaultlib"/>
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<UsedIn Val="SYNTHESIS"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="sim\crc_axi_master_sim.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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<UsedIn Val="SIMULATION"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="crc_axi_master_sim_ooc.xdc" Type="XDC">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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<UsedIn Val="SYNTHESIS"/>
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<UsedIn Val="IMPLEMENTATION"/>
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<UsedIn Val="OUT_OF_CONTEXT"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="hw_handoff\crc_axi_master_sim.hwh" Type="HwHandoff">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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<Library Name="xil_defaultlib"/>
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<UsedIn Val="HW_HANDOFF"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="crc_axi_master_sim.bda">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="HW_HANDOFF"/>
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||||
<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="synth\crc_axi_master_sim.hwdef">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="HW_HANDOFF"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="sim\crc_axi_master_sim.protoinst">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="SIMULATION"/>
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||||
<ProcessingOrder Val="NORMAL"/>
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</File>
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</FileCollection>
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</CompositeFile>
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</Root>
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+10
@@ -0,0 +1,10 @@
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################################################################################
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# This XDC is used only for OOC mode of synthesis, implementation
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# This constraints file contains default clock frequencies to be used during
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# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
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# This constraints file is not used in normal top-down synthesis (default flow
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# of Vivado)
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################################################################################
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################################################################################
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+1
-1
@@ -2,7 +2,7 @@
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--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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--Date : Thu Jan 30 22:59:13 2025
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--Date : Fri Jan 31 01:46:20 2025
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--Host : BiermannSurface running 64-bit major release (build 9200)
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--Command : generate_target crc_axi_master_sim_wrapper.bd
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--Design : crc_axi_master_sim_wrapper
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+99
-55
@@ -689,6 +689,40 @@
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</spirit:addressSpace>
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</spirit:addressSpaces>
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||||
<spirit:model>
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||||
<spirit:views>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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||||
<spirit:displayName>Simulation</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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||||
<spirit:modelName>crc_axi_master</spirit:modelName>
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||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:cf9c9909</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_sim_crc_axi_master_0_2</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 00:46:20 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:cf9c9909</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
@@ -697,7 +731,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -709,7 +743,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -721,7 +755,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -733,7 +767,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -749,7 +783,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -765,7 +799,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -777,7 +811,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -787,13 +821,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.BRAM_AWIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.LUTRAM_AWIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -809,7 +843,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -821,7 +855,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -831,13 +865,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.BRAM_AWIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.LUTRAM_AWIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -853,7 +887,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -865,7 +899,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -877,7 +911,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -892,7 +926,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -911,7 +945,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -927,7 +961,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -943,7 +977,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -959,7 +993,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -975,7 +1009,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -991,7 +1025,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1007,7 +1041,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1019,7 +1053,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1031,7 +1065,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1050,7 +1084,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1069,7 +1103,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1088,7 +1122,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1103,7 +1137,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1118,7 +1152,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1133,7 +1167,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1152,7 +1186,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1168,7 +1202,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1184,7 +1218,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1200,7 +1234,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1216,7 +1250,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1232,7 +1266,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1248,7 +1282,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1260,7 +1294,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1275,7 +1309,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1294,7 +1328,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1310,7 +1344,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1322,7 +1356,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1338,7 +1372,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1350,7 +1384,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1362,7 +1396,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1381,7 +1415,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1400,7 +1434,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1426,9 +1460,9 @@
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BRAM_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Bram Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BRAM_AWIDTH" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
<spirit:name>LUTRAM_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Lutram Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LUTRAM_AWIDTH" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
@@ -1439,6 +1473,16 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/crc_axi_master_sim_crc_axi_master_0_2.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_master:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
@@ -1457,9 +1501,9 @@
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BRAM_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Bram Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BRAM_AWIDTH" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
<spirit:name>LUTRAM_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Lutram Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LUTRAM_AWIDTH" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
|
||||
+2
-2
@@ -113,7 +113,7 @@ ARCHITECTURE crc_axi_master_sim_crc_axi_master_0_2_arch OF crc_axi_master_sim_cr
|
||||
DWIDTH : INTEGER;
|
||||
IDWIDTH : INTEGER;
|
||||
MAX_BURSTLEN : INTEGER;
|
||||
BRAM_AWIDTH : INTEGER
|
||||
LUTRAM_AWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
@@ -213,7 +213,7 @@ BEGIN
|
||||
DWIDTH => 32,
|
||||
IDWIDTH => 1,
|
||||
MAX_BURSTLEN => 16,
|
||||
BRAM_AWIDTH => 4
|
||||
LUTRAM_AWIDTH => 4
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
|
||||
+3
-116
@@ -4,98 +4,6 @@
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>crc_axi_master_sim_crc_axi_ram_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
@@ -106,7 +14,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a61066fb</spirit:value>
|
||||
<spirit:value>9:12c42963</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -122,28 +30,16 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 21:38:36 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:33:13 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a61066fb</spirit:value>
|
||||
<spirit:value>9:12c42963</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>waddr</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -278,15 +174,6 @@
|
||||
<xilinx:displayName>crc_axi_ram_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
-7
@@ -55,7 +55,6 @@ USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_sim_crc_axi_ram_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
waddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : IN STD_LOGIC;
|
||||
@@ -74,7 +73,6 @@ ARCHITECTURE crc_axi_master_sim_crc_axi_ram_0_0_arch OF crc_axi_master_sim_crc_a
|
||||
DATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
waddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : IN STD_LOGIC;
|
||||
@@ -83,10 +81,6 @@ ARCHITECTURE crc_axi_master_sim_crc_axi_ram_0_0_arch OF crc_axi_master_sim_crc_a
|
||||
re : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT crc_axi_ram;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
BEGIN
|
||||
U0 : crc_axi_ram
|
||||
GENERIC MAP (
|
||||
@@ -94,7 +88,6 @@ BEGIN
|
||||
DATA_WIDTH => 32
|
||||
)
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
waddr => waddr,
|
||||
wdata => wdata,
|
||||
we => we,
|
||||
|
||||
+293
@@ -0,0 +1,293 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Fri Jan 31 01:46:20 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target crc_axi_master_sim.bd
|
||||
--Design : crc_axi_master_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_axi_master_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of crc_axi_master_sim : entity is "crc_axi_master_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=4,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of crc_axi_master_sim : entity is "crc_axi_master_sim.hwdef";
|
||||
end crc_axi_master_sim;
|
||||
|
||||
architecture STRUCTURE of crc_axi_master_sim is
|
||||
component crc_axi_master_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_clk_rst_generator_0_0;
|
||||
component crc_axi_master_sim_axi3_slave_verif_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_RLAST : out STD_LOGIC;
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WLAST : in STD_LOGIC;
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_axi3_slave_verif_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_sim_c_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
start : out STD_LOGIC;
|
||||
write : out STD_LOGIC;
|
||||
addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
axi_idle : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
|
||||
component crc_axi_master_sim_crc_axi_ram_0_0 is
|
||||
port (
|
||||
waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : in STD_LOGIC;
|
||||
raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_ram_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_0_2 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
start : in STD_LOGIC;
|
||||
write : in STD_LOGIC;
|
||||
addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
ip_idle : out STD_LOGIC;
|
||||
waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : out STD_LOGIC;
|
||||
raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : out STD_LOGIC;
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_0_2;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_idle : STD_LOGIC;
|
||||
signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_re : STD_LOGIC;
|
||||
signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_we : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_start : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_write : STD_LOGIC;
|
||||
signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
begin
|
||||
axi3_slave_verif_0: component crc_axi_master_sim_axi3_slave_verif_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
S_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
S_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
S_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
S_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
S_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
S_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
S_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
S_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
S_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
S_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
S_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
S_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
S_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
S_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
S_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
S_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
S_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
S_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
S_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
S_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
S_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
S_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
S_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
S_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
S_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
S_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID
|
||||
);
|
||||
clk_rst_generator_0: component crc_axi_master_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_AWID(0) => NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED(0),
|
||||
M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
|
||||
M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_WID(31 downto 0) => NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED(31 downto 0),
|
||||
M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
addr_axi(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
ip_idle => crc_axi_master_0_idle,
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
|
||||
port map (
|
||||
addr(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
axi_idle => crc_axi_master_0_idle,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n,
|
||||
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_ram_0: component crc_axi_master_sim_crc_axi_ram_0_0
|
||||
port map (
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we
|
||||
);
|
||||
end STRUCTURE;
|
||||
+293
@@ -0,0 +1,293 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Fri Jan 31 01:46:20 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target crc_axi_master_sim.bd
|
||||
--Design : crc_axi_master_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_axi_master_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of crc_axi_master_sim : entity is "crc_axi_master_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=4,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of crc_axi_master_sim : entity is "crc_axi_master_sim.hwdef";
|
||||
end crc_axi_master_sim;
|
||||
|
||||
architecture STRUCTURE of crc_axi_master_sim is
|
||||
component crc_axi_master_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_clk_rst_generator_0_0;
|
||||
component crc_axi_master_sim_axi3_slave_verif_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_RLAST : out STD_LOGIC;
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WLAST : in STD_LOGIC;
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_axi3_slave_verif_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_sim_c_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
start : out STD_LOGIC;
|
||||
write : out STD_LOGIC;
|
||||
addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
axi_idle : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
|
||||
component crc_axi_master_sim_crc_axi_ram_0_0 is
|
||||
port (
|
||||
waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : in STD_LOGIC;
|
||||
raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_ram_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_0_2 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
start : in STD_LOGIC;
|
||||
write : in STD_LOGIC;
|
||||
addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
ip_idle : out STD_LOGIC;
|
||||
waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : out STD_LOGIC;
|
||||
raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : out STD_LOGIC;
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_0_2;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_idle : STD_LOGIC;
|
||||
signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_re : STD_LOGIC;
|
||||
signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_we : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_start : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_write : STD_LOGIC;
|
||||
signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
begin
|
||||
axi3_slave_verif_0: component crc_axi_master_sim_axi3_slave_verif_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
S_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
S_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
S_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
S_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
S_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
S_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
S_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
S_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
S_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
S_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
S_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
S_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
S_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
S_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
S_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
S_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
S_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
S_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
S_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
S_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
S_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
S_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
S_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
S_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
S_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
S_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID
|
||||
);
|
||||
clk_rst_generator_0: component crc_axi_master_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_AWID(0) => NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED(0),
|
||||
M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
|
||||
M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_WID(31 downto 0) => NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED(31 downto 0),
|
||||
M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
addr_axi(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
ip_idle => crc_axi_master_0_idle,
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
|
||||
port map (
|
||||
addr(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
axi_idle => crc_axi_master_0_idle,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n,
|
||||
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_ram_0: component crc_axi_master_sim_crc_axi_ram_0_0
|
||||
port map (
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we
|
||||
);
|
||||
end STRUCTURE;
|
||||
+5
-50
@@ -2,55 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="crc_axi_master_syn" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738275832"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738275832"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738275832"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738275832"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\crc_axi_master_syn.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\crc_axi_master_syn.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="crc_axi_master_syn_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\crc_axi_master_syn.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="crc_axi_master_syn.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\crc_axi_master_syn.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\crc_axi_master_syn.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738284371"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1738284371"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738284371"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738284371"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
-14
@@ -1,14 +0,0 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name Processing_System_processing_system7_0_FCLK_CLK0 -period 10 [get_pins Processing_System/processing_system7_0/FCLK_CLK0]
|
||||
create_clock -name Processing_System_processing_system7_0_FCLK_CLK1 -period 8 [get_pins Processing_System/processing_system7_0/FCLK_CLK1]
|
||||
create_clock -name Processing_System_processing_system7_0_FCLK_CLK2 -period 5 [get_pins Processing_System/processing_system7_0/FCLK_CLK2]
|
||||
create_clock -name Processing_System_processing_system7_0_FCLK_CLK3 -period 15 [get_pins Processing_System/processing_system7_0/FCLK_CLK3]
|
||||
|
||||
################################################################################
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Thu Jan 30 23:23:23 2025
|
||||
--Date : Fri Jan 31 01:17:54 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target crc_axi_master_syn_wrapper.bd
|
||||
--Design : crc_axi_master_syn_wrapper
|
||||
|
||||
+9
-9
@@ -1511,7 +1511,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:52 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:24 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1530,7 +1530,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:24 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1548,7 +1548,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:23 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1568,7 +1568,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:23 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1596,7 +1596,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:23 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1644,7 +1644,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:23 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1664,7 +1664,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:23 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1708,7 +1708,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:23 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1728,7 +1728,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:23 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+61
-257
@@ -514,7 +514,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -652,7 +652,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -689,101 +689,6 @@
|
||||
</spirit:addressSpace>
|
||||
</spirit:addressSpaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_master</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:45a83f32</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_master</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:302fb0f1</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:24:59 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:302fb0f1</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:302fb0f1</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_syn_crc_axi_master_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:45a83f32</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_syn_crc_axi_master_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:302fb0f1</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
@@ -792,8 +697,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -805,8 +709,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -818,8 +721,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -831,8 +733,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -848,8 +749,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -865,8 +765,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -878,8 +777,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -889,14 +787,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.BRAM_AWIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.LUTRAM_AWIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -912,8 +809,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -925,8 +821,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -936,14 +831,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.BRAM_AWIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.LUTRAM_AWIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -959,8 +853,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -972,8 +865,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -985,8 +877,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1001,8 +892,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1021,8 +911,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1038,8 +927,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1055,8 +943,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1072,8 +959,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1089,8 +975,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1106,8 +991,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1123,8 +1007,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1136,8 +1019,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1149,8 +1031,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1169,8 +1050,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1189,8 +1069,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1209,8 +1088,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1225,8 +1103,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1241,8 +1118,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1257,8 +1133,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1277,8 +1152,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1294,8 +1168,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1311,8 +1184,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1328,8 +1200,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1345,8 +1216,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1362,8 +1232,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1379,8 +1248,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1392,8 +1260,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1408,8 +1275,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1428,8 +1294,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1445,8 +1310,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1458,8 +1322,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1475,8 +1338,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1488,8 +1350,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1501,8 +1362,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1521,8 +1381,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1541,8 +1400,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1568,9 +1426,9 @@
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BRAM_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Bram Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BRAM_AWIDTH" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
<spirit:name>LUTRAM_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Lutram Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LUTRAM_AWIDTH" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
@@ -1581,60 +1439,6 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_master_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_master_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_master_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_master_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_master_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/crc_axi_master_syn_crc_axi_master_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/crc_axi_master_syn_crc_axi_master_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_master:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
@@ -1653,9 +1457,9 @@
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BRAM_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Bram Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BRAM_AWIDTH" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
<spirit:name>LUTRAM_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Lutram Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LUTRAM_AWIDTH" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
@@ -1671,17 +1475,17 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
|
||||
+1
-1
@@ -158,7 +158,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 13:57:25 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:24 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+6
-275
@@ -4,208 +4,8 @@
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_ram_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_ram</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:35cda32e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_ram</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:80ec1d90</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:04:42 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:80ec1d90</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:80ec1d90</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_syn_crc_axi_ram_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:03:24 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:35cda32e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_syn_crc_axi_ram_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:03:24 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:80ec1d90</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>waddr</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -217,8 +17,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -234,8 +33,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -247,8 +45,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -264,8 +61,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -281,8 +77,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -294,8 +89,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -314,60 +108,6 @@
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_ram_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_ram_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_ram_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_ram_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_crc_axi_ram_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/crc_axi_master_syn_crc_axi_ram_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/crc_axi_master_syn_crc_axi_ram_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_ram:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
@@ -390,15 +130,6 @@
|
||||
<xilinx:displayName>crc_axi_ram_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
+3
-3
@@ -20,12 +20,12 @@
|
||||
create_clock -name clk_fpga_1 -period "8" [get_pins "PS7_i/FCLKCLK[1]"]
|
||||
set_input_jitter clk_fpga_1 0.24
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_2 -period "5" [get_pins "PS7_i/FCLKCLK[2]"]
|
||||
set_input_jitter clk_fpga_2 0.15
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_3 -period "14.999" [get_pins "PS7_i/FCLKCLK[3]"]
|
||||
set_input_jitter clk_fpga_3 0.44997
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_2 -period "5" [get_pins "PS7_i/FCLKCLK[2]"]
|
||||
set_input_jitter clk_fpga_2 0.15
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
|
||||
set_input_jitter clk_fpga_0 0.3
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
|
||||
+22
-22
@@ -9107,7 +9107,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK0_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">1e+08</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK0_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">100000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
@@ -9199,7 +9199,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK1.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK1_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">1.25e+08</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK1.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK1_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">125000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
@@ -9291,7 +9291,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK2.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK2_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">2e+08</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK2.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK2_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">200000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
@@ -9383,7 +9383,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK3.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK3_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">6.66667e+07</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK3.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK3_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">66666672</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
@@ -15203,7 +15203,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:434e4ede</spirit:value>
|
||||
<spirit:value>9:b2f64a09</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -15218,11 +15218,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:49 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c13cbf3f</spirit:value>
|
||||
<spirit:value>9:f261cab5</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
@@ -15241,11 +15241,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:49 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:434e4ede</spirit:value>
|
||||
<spirit:value>9:b2f64a09</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -15260,11 +15260,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:23 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c13cbf3f</spirit:value>
|
||||
<spirit:value>9:f261cab5</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
@@ -15283,11 +15283,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:20 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:7c5f388e</spirit:value>
|
||||
<spirit:value>9:c80f341c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -15301,11 +15301,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:25:06 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:19:45 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:7c5f388e</spirit:value>
|
||||
<spirit:value>9:c80f341c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -15316,7 +15316,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:7c5f388e</spirit:value>
|
||||
<spirit:value>9:c80f341c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -15332,11 +15332,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:49 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6b7819ce</spirit:value>
|
||||
<spirit:value>9:02f083cc</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
@@ -15356,11 +15356,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:49 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:21 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6b7819ce</spirit:value>
|
||||
<spirit:value>9:02f083cc</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
@@ -15380,11 +15380,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:20 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:7c5f388e</spirit:value>
|
||||
<spirit:value>9:c80f341c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
|
||||
+5
-5
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Jan 30 23:25:06 2025
|
||||
// Date : Fri Jan 31 01:19:45 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0_sim_netlist.v
|
||||
@@ -140,10 +140,10 @@ module crc_axi_master_syn_processing_system7_0_0
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WDATA" *) input [63:0]S_AXI_ACP_WDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WSTRB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 5, ARUSER_WIDTH 5, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [7:0]S_AXI_ACP_WSTRB;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) input [0:0]IRQ_F2P;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 1.25e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *) output FCLK_CLK1;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 2e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *) output FCLK_CLK2;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 6.66667e+07, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) output FCLK_CLK3;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *) output FCLK_CLK1;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *) output FCLK_CLK2;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) output FCLK_CLK3;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Jan 30 23:25:06 2025
|
||||
// Date : Fri Jan 31 01:19:45 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0_stub.v
|
||||
|
||||
+4
-4
@@ -234,16 +234,16 @@ input wire [7 : 0] S_AXI_ACP_WSTRB;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
|
||||
input wire [0 : 0] IRQ_F2P;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
|
||||
output wire FCLK_CLK0;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 1.25e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *)
|
||||
output wire FCLK_CLK1;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 2e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *)
|
||||
output wire FCLK_CLK2;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 6.66667e+07, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *)
|
||||
output wire FCLK_CLK3;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
|
||||
+13
-13
@@ -398,7 +398,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Jan 29 12:04:24 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:18:24 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -764,18 +764,6 @@
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_rst_ps7_0_100M_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_rst_ps7_0_100M_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_rst_ps7_0_100M_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
@@ -790,6 +778,18 @@
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_rst_ps7_0_100M_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_rst_ps7_0_100M_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
|
||||
|
||||
+60
-65
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jan 29 13:04:24 2025
|
||||
// Date : Wed Jan 29 13:04:23 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_rst_ps7_0_100M_0/crc_axi_master_syn_rst_ps7_0_100M_0_sim_netlist.v
|
||||
// Command : write_verilog -force -mode funcsim -rename_top crc_axi_master_syn_rst_ps7_0_100M_0 -prefix
|
||||
// crc_axi_master_syn_rst_ps7_0_100M_0_ crc_axi_master_syn_rst_ps7_0_100M_0_sim_netlist.v
|
||||
// Design : crc_axi_master_syn_rst_ps7_0_100M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
@@ -13,64 +13,6 @@
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "crc_axi_master_syn_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module crc_axi_master_syn_rst_ps7_0_100M_0
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
crc_axi_master_syn_rst_ps7_0_100M_0_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module crc_axi_master_syn_rst_ps7_0_100M_0_cdc_sync
|
||||
(lpf_asr_reg,
|
||||
scndry_out,
|
||||
@@ -266,7 +208,63 @@ module crc_axi_master_syn_rst_ps7_0_100M_0_cdc_sync_0
|
||||
.O(lpf_exr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "lpf" *)
|
||||
(* CHECK_LICENSE_TYPE = "crc_axi_master_syn_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module crc_axi_master_syn_rst_ps7_0_100M_0
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
crc_axi_master_syn_rst_ps7_0_100M_0_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
module crc_axi_master_syn_rst_ps7_0_100M_0_lpf
|
||||
(lpf_int,
|
||||
slowest_sync_clk,
|
||||
@@ -421,7 +419,6 @@ endmodule
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
|
||||
(* ORIG_REF_NAME = "proc_sys_reset" *)
|
||||
module crc_axi_master_syn_rst_ps7_0_100M_0_proc_sys_reset
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
@@ -538,7 +535,6 @@ module crc_axi_master_syn_rst_ps7_0_100M_0_proc_sys_reset
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "sequence_psr" *)
|
||||
module crc_axi_master_syn_rst_ps7_0_100M_0_sequence_psr
|
||||
(MB_out,
|
||||
Bsr_out,
|
||||
@@ -779,7 +775,6 @@ module crc_axi_master_syn_rst_ps7_0_100M_0_sequence_psr
|
||||
.R(lpf_int));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "upcnt_n" *)
|
||||
module crc_axi_master_syn_rst_ps7_0_100M_0_upcnt_n
|
||||
(Q,
|
||||
seq_clr,
|
||||
|
||||
+3
-3
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jan 29 13:04:24 2025
|
||||
// Date : Wed Jan 29 13:04:23 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_rst_ps7_0_100M_0/crc_axi_master_syn_rst_ps7_0_100M_0_stub.v
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top crc_axi_master_syn_rst_ps7_0_100M_0 -prefix
|
||||
// crc_axi_master_syn_rst_ps7_0_100M_0_ crc_axi_master_syn_rst_ps7_0_100M_0_stub.v
|
||||
// Design : crc_axi_master_syn_rst_ps7_0_100M_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
|
||||
+108
-9
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0xF6797DED63AA5C96",
|
||||
"boundary_crc": "0xBC5528FC0E362936",
|
||||
"design_src": "SBD",
|
||||
"device": "xc7z020clg400-1",
|
||||
"name": "bd_eb4d",
|
||||
@@ -14,6 +14,7 @@
|
||||
"design_tree": {
|
||||
"ila_lib": "",
|
||||
"g_inst": "",
|
||||
"slot_0_apc": "",
|
||||
"slot_0_aw": "",
|
||||
"slot_0_w": "",
|
||||
"slot_0_b": "",
|
||||
@@ -288,7 +289,7 @@
|
||||
"value": "Native"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "42"
|
||||
"value": "44"
|
||||
},
|
||||
"C_PROBE0_MU_CNT": {
|
||||
"value": "1"
|
||||
@@ -521,6 +522,18 @@
|
||||
"C_PROBE41_WIDTH": {
|
||||
"value": "3"
|
||||
},
|
||||
"C_PROBE42_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE42_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE43_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE43_WIDTH": {
|
||||
"value": "160"
|
||||
},
|
||||
"C_PROBE4_MU_CNT": {
|
||||
"value": "1"
|
||||
},
|
||||
@@ -690,16 +703,87 @@
|
||||
}
|
||||
}
|
||||
},
|
||||
"slot_0_apc": {
|
||||
"vlnv": "xilinx.com:ip:axi_protocol_checker:2.0",
|
||||
"xci_name": "bd_eb4d_slot_0_apc_0",
|
||||
"xci_path": "ip\\ip_2\\bd_eb4d_slot_0_apc_0.xci",
|
||||
"inst_hier_path": "slot_0_apc",
|
||||
"parameters": {
|
||||
"ADDR_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"ARUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"AWUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"BUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"DATA_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"ENABLE_MARK_DEBUG": {
|
||||
"value": "0"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"MAX_AR_WAITS": {
|
||||
"value": "0"
|
||||
},
|
||||
"MAX_AW_WAITS": {
|
||||
"value": "0"
|
||||
},
|
||||
"MAX_B_WAITS": {
|
||||
"value": "0"
|
||||
},
|
||||
"MAX_CONTINUOUS_RTRANSFERS_WAITS": {
|
||||
"value": "0"
|
||||
},
|
||||
"MAX_CONTINUOUS_WTRANSFERS_WAITS": {
|
||||
"value": "0"
|
||||
},
|
||||
"MAX_RD_BURSTS": {
|
||||
"value": "2"
|
||||
},
|
||||
"MAX_R_WAITS": {
|
||||
"value": "0"
|
||||
},
|
||||
"MAX_WLAST_TO_AWVALID_WAITS": {
|
||||
"value": "0"
|
||||
},
|
||||
"MAX_WRITE_TO_BVALID_WAITS": {
|
||||
"value": "0"
|
||||
},
|
||||
"MAX_WR_BURSTS": {
|
||||
"value": "2"
|
||||
},
|
||||
"MAX_W_WAITS": {
|
||||
"value": "0"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI3"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"slot_0_aw": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_eb4d_slot_0_aw_0",
|
||||
"xci_path": "ip\\ip_2\\bd_eb4d_slot_0_aw_0.xci",
|
||||
"xci_path": "ip\\ip_3\\bd_eb4d_slot_0_aw_0.xci",
|
||||
"inst_hier_path": "slot_0_aw"
|
||||
},
|
||||
"slot_0_w": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_eb4d_slot_0_w_0",
|
||||
"xci_path": "ip\\ip_3\\bd_eb4d_slot_0_w_0.xci",
|
||||
"xci_path": "ip\\ip_4\\bd_eb4d_slot_0_w_0.xci",
|
||||
"inst_hier_path": "slot_0_w",
|
||||
"parameters": {
|
||||
"NUM_PORTS": {
|
||||
@@ -710,19 +794,19 @@
|
||||
"slot_0_b": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_eb4d_slot_0_b_0",
|
||||
"xci_path": "ip\\ip_4\\bd_eb4d_slot_0_b_0.xci",
|
||||
"xci_path": "ip\\ip_5\\bd_eb4d_slot_0_b_0.xci",
|
||||
"inst_hier_path": "slot_0_b"
|
||||
},
|
||||
"slot_0_ar": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_eb4d_slot_0_ar_0",
|
||||
"xci_path": "ip\\ip_5\\bd_eb4d_slot_0_ar_0.xci",
|
||||
"xci_path": "ip\\ip_6\\bd_eb4d_slot_0_ar_0.xci",
|
||||
"inst_hier_path": "slot_0_ar"
|
||||
},
|
||||
"slot_0_r": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_eb4d_slot_0_r_0",
|
||||
"xci_path": "ip\\ip_6\\bd_eb4d_slot_0_r_0.xci",
|
||||
"xci_path": "ip\\ip_7\\bd_eb4d_slot_0_r_0.xci",
|
||||
"inst_hier_path": "slot_0_r",
|
||||
"parameters": {
|
||||
"NUM_PORTS": {
|
||||
@@ -735,7 +819,8 @@
|
||||
"Conn": {
|
||||
"interface_ports": [
|
||||
"SLOT_0_AXI",
|
||||
"g_inst/slot_0_axi"
|
||||
"g_inst/slot_0_axi",
|
||||
"slot_0_apc/PC_AXI"
|
||||
]
|
||||
}
|
||||
},
|
||||
@@ -744,9 +829,22 @@
|
||||
"ports": [
|
||||
"clk",
|
||||
"ila_lib/clk",
|
||||
"slot_0_apc/aclk",
|
||||
"g_inst/aclk"
|
||||
]
|
||||
},
|
||||
"net_slot_0_apc_pc_asserted": {
|
||||
"ports": [
|
||||
"slot_0_apc/pc_asserted",
|
||||
"ila_lib/probe42"
|
||||
]
|
||||
},
|
||||
"net_slot_0_apc_pc_status": {
|
||||
"ports": [
|
||||
"slot_0_apc/pc_status",
|
||||
"ila_lib/probe43"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_ar_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_ar_cnt",
|
||||
@@ -1074,7 +1172,8 @@
|
||||
"resetn_1": {
|
||||
"ports": [
|
||||
"resetn",
|
||||
"g_inst/aresetn"
|
||||
"g_inst/aresetn",
|
||||
"slot_0_apc/aresetn"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
||||
+10
-10
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_eb4d" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738275807"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738275807"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738275807"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738275807"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738282678"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738282678"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738282678"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738282678"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_eb4d.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
@@ -19,12 +19,6 @@
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_eb4d.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="bd_eb4d_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
@@ -45,6 +39,12 @@
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_eb4d.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
+13
-1
@@ -16,7 +16,9 @@ entity bd_eb4d_wrapper is
|
||||
SLOT_0_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_0_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
@@ -25,7 +27,9 @@ entity bd_eb4d_wrapper is
|
||||
SLOT_0_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_0_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
@@ -110,7 +114,11 @@ architecture STRUCTURE of bd_eb4d_wrapper is
|
||||
SLOT_0_AXI_wlast : in STD_LOGIC;
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||
);
|
||||
end component bd_eb4d;
|
||||
begin
|
||||
@@ -121,7 +129,9 @@ bd_eb4d_i: component bd_eb4d
|
||||
SLOT_0_AXI_arcache(3 downto 0) => SLOT_0_AXI_arcache(3 downto 0),
|
||||
SLOT_0_AXI_arid(0) => SLOT_0_AXI_arid(0),
|
||||
SLOT_0_AXI_arlen(3 downto 0) => SLOT_0_AXI_arlen(3 downto 0),
|
||||
SLOT_0_AXI_arlock(1 downto 0) => SLOT_0_AXI_arlock(1 downto 0),
|
||||
SLOT_0_AXI_arprot(2 downto 0) => SLOT_0_AXI_arprot(2 downto 0),
|
||||
SLOT_0_AXI_arqos(3 downto 0) => SLOT_0_AXI_arqos(3 downto 0),
|
||||
SLOT_0_AXI_arready => SLOT_0_AXI_arready,
|
||||
SLOT_0_AXI_arsize(2 downto 0) => SLOT_0_AXI_arsize(2 downto 0),
|
||||
SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
|
||||
@@ -130,7 +140,9 @@ bd_eb4d_i: component bd_eb4d
|
||||
SLOT_0_AXI_awcache(3 downto 0) => SLOT_0_AXI_awcache(3 downto 0),
|
||||
SLOT_0_AXI_awid(0) => SLOT_0_AXI_awid(0),
|
||||
SLOT_0_AXI_awlen(3 downto 0) => SLOT_0_AXI_awlen(3 downto 0),
|
||||
SLOT_0_AXI_awlock(1 downto 0) => SLOT_0_AXI_awlock(1 downto 0),
|
||||
SLOT_0_AXI_awprot(2 downto 0) => SLOT_0_AXI_awprot(2 downto 0),
|
||||
SLOT_0_AXI_awqos(3 downto 0) => SLOT_0_AXI_awqos(3 downto 0),
|
||||
SLOT_0_AXI_awready => SLOT_0_AXI_awready,
|
||||
SLOT_0_AXI_awsize(2 downto 0) => SLOT_0_AXI_awsize(2 downto 0),
|
||||
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
|
||||
|
||||
+11
-9
@@ -988,8 +988,8 @@
|
||||
"C_PROBE46_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE45_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE44_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE43_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE42_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE43_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE42_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE41_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE40_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE39_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -2011,8 +2011,8 @@
|
||||
"C_PROBE46_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE45_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE44_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE43_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE42_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE43_WIDTH": [ { "value": "160", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE42_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE41_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE40_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE39_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -2056,7 +2056,7 @@
|
||||
"C_PROBE1_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE0_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_DEPTH": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OF_PROBES": [ { "value": "42", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OF_PROBES": [ { "value": "44", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "bd_eb4d_ila_lib_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -3135,7 +3135,7 @@
|
||||
"C_SLOT_0_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_ILA_AXI_MON": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OF_PROBES": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OF_PROBES": [ { "value": "44", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MAJOR_VERSION": [ { "value": "2023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MINOR_VERSION": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -3157,7 +3157,7 @@
|
||||
"C_SLOT_0_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_RUSER_WIDTH": [ { "value": "3", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_AWUSER_WIDTH": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_WUSER_WIDTH": [ { "value": "160", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_BUSER_WIDTH": [ { "value": "4", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE0_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE1_WIDTH": [ { "value": "32", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
@@ -3202,7 +3202,7 @@
|
||||
"C_PROBE40_WIDTH": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE41_WIDTH": [ { "value": "3", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE42_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE43_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE43_WIDTH": [ { "value": "160", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE44_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE45_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE46_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
@@ -6313,7 +6313,9 @@
|
||||
"probe38": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe39": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe40": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe41": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ]
|
||||
"probe41": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe42": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe43": [ { "direction": "in", "size_left": "159", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"signal_clock": {
|
||||
|
||||
+21
-17
@@ -1046,11 +1046,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:24 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:55 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d0f679e6</spirit:value>
|
||||
<spirit:value>9:9f4498ec</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1065,11 +1065,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:24 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:55 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d0f679e6</spirit:value>
|
||||
<spirit:value>9:9f4498ec</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1080,7 +1080,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d0f679e6</spirit:value>
|
||||
<spirit:value>9:9f4498ec</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1096,11 +1096,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:24 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:55 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1040550d</spirit:value>
|
||||
<spirit:value>9:b94eff1a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1116,11 +1116,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:24 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:55 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d0f679e6</spirit:value>
|
||||
<spirit:value>9:9f4498ec</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -2422,7 +2422,7 @@
|
||||
<xilinx:portInfo>
|
||||
<xilinx:bufferType>BUF</xilinx:bufferType>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.probe42" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_PROBES')) > 42) and (spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_ILA_AXI_MON')) = 0)) or ((((spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_ILA_AXI_MON')) = 1) and (spirit:decode(id('MODELPARAM_VALUE.C_NUM_MONITOR_SLOTS')) > 0)) and (spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL')) != 'AXI4LITE') and ( spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL')) != 'AXI4S'))))">false</xilinx:isEnabled>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.probe42" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_PROBES')) > 42) and (spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_ILA_AXI_MON')) = 0)) or ((((spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_ILA_AXI_MON')) = 1) and (spirit:decode(id('MODELPARAM_VALUE.C_NUM_MONITOR_SLOTS')) > 0)) and (spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL')) != 'AXI4LITE') and ( spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL')) != 'AXI4S'))))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
@@ -2432,7 +2432,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_WUSER_WIDTH')) - 1)">0</spirit:left>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_WUSER_WIDTH')) - 1)">159</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -2449,7 +2449,7 @@
|
||||
<xilinx:portInfo>
|
||||
<xilinx:bufferType>BUF</xilinx:bufferType>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.probe43" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_PROBES')) > 43) and (spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_ILA_AXI_MON')) = 0)) or (((spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_ILA_AXI_MON')) = 1) and (spirit:decode(id('MODELPARAM_VALUE.C_NUM_MONITOR_SLOTS')) > 0)) and (spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL')) != 'AXI4LITE') and ( spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL')) != 'AXI4S')))">false</xilinx:isEnabled>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.probe43" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_PROBES')) > 43) and (spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_ILA_AXI_MON')) = 0)) or (((spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_ILA_AXI_MON')) = 1) and (spirit:decode(id('MODELPARAM_VALUE.C_NUM_MONITOR_SLOTS')) > 0)) and (spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL')) != 'AXI4LITE') and ( spirit:decode(id('MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL')) != 'AXI4S')))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
@@ -28993,7 +28993,7 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_OF_PROBES</spirit:name>
|
||||
<spirit:displayName>Number of Probes</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OF_PROBES" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">42</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OF_PROBES" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">44</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_DATA_DEPTH</spirit:name>
|
||||
@@ -29108,7 +29108,7 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_SLOT_0_AXI_WUSER_WIDTH</spirit:name>
|
||||
<spirit:displayName>C Slot 0 Axi WUSER Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_SLOT_0_AXI_WUSER_WIDTH" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_SLOT_0_AXI_WUSER_WIDTH" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">160</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_SLOT_0_AXI_BUSER_WIDTH</spirit:name>
|
||||
@@ -29333,7 +29333,7 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_PROBE43_WIDTH</spirit:name>
|
||||
<spirit:displayName>Probe43 Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_PROBE43_WIDTH" spirit:dependency="(spirit:decode(id('PARAM_VALUE.C_PROBE43_WIDTH')))" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_PROBE43_WIDTH" spirit:dependency="(spirit:decode(id('PARAM_VALUE.C_PROBE43_WIDTH')))" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">160</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_PROBE44_WIDTH</spirit:name>
|
||||
@@ -68933,7 +68933,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_PROBE43_WIDTH</spirit:name>
|
||||
<spirit:displayName>Probe43 Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE43_WIDTH" spirit:order="15200" spirit:configGroups="1 UnGrouped" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE43_WIDTH" spirit:order="15200" spirit:configGroups="1 UnGrouped" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">160</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
@@ -69473,7 +69473,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_OF_PROBES</spirit:name>
|
||||
<spirit:displayName>Number of Probes</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_OF_PROBES" spirit:order="10700" spirit:configGroups="1 UnGrouped" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">42</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_OF_PROBES" spirit:order="10700" spirit:configGroups="1 UnGrouped" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">44</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
@@ -74986,6 +74986,10 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE40_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE41_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE41_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE42_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE42_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE43_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE43_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE4_MU_CNT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE4_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE4_WIDTH" xilinx:valueSource="user"/>
|
||||
|
||||
+3
-1
@@ -96,7 +96,9 @@ probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe38 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe39 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
|
||||
probe41 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(159 DOWNTO 0)
|
||||
);
|
||||
END bd_eb4d_ila_lib_0;
|
||||
|
||||
|
||||
+12
-10
@@ -96,7 +96,9 @@ probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe38 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe39 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
|
||||
probe41 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(159 DOWNTO 0)
|
||||
);
|
||||
END bd_eb4d_ila_lib_0;
|
||||
|
||||
@@ -3257,7 +3259,7 @@ probe39 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
|
||||
probe44 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe45 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe46 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -4248,7 +4250,7 @@ ATTRIBUTE X_CORE_INFO OF bd_eb4d_ila_lib_0_arch : ARCHITECTURE IS "ila,Vivado 20
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_eb4d_ila_lib_0_arch : ARCHITECTURE IS "bd_eb4d_ila_lib_0,ila_v6_2_13_ila,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF bd_eb4d_ila_lib_0_arch : ARCHITECTURE IS "bd_eb4d_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=42,C_DATA_DEPTH=8192,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=100000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=32,C_PROBE2_WIDTH=4,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=4,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=4,C_PROBE9_WIDTH=32,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=2,C_PROBE12_WIDTH=32,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=4,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=4,C_PROBE17_WIDTH=3,C_PROBE18_WIDTH=3,C_PROBE19_WIDTH=2,C_PROBE20_WIDTH=32,C_PROBE21_WIDTH=2,C_PROBE22_WIDTH=4,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=4,C_PROBE25_WIDTH=3,C_PROBE26_WIDTH=3,C_PROBE27_WIDTH=2,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=2,C_PROBE30_WIDTH=2,C_PROBE31_WIDTH=32,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=2,C_PROBE34_WIDTH=32,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=4,C_PROBE37_WIDTH=2,C_PROBE38_WIDTH=3,C_PROBE39_WIDTH=2,C_PROBE40_WIDTH=2,C_PROBE41_WIDTH=3,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF bd_eb4d_ila_lib_0_arch : ARCHITECTURE IS "bd_eb4d_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=44,C_DATA_DEPTH=8192,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=100000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=32,C_PROBE2_WIDTH=4,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=4,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=4,C_PROBE9_WIDTH=32,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=2,C_PROBE12_WIDTH=32,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=4,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=4,C_PROBE17_WIDTH=3,C_PROBE18_WIDTH=3,C_PROBE19_WIDTH=2,C_PROBE20_WIDTH=32,C_PROBE21_WIDTH=2,C_PROBE22_WIDTH=4,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=4,C_PROBE25_WIDTH=3,C_PROBE26_WIDTH=3,C_PROBE27_WIDTH=2,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=2,C_PROBE30_WIDTH=2,C_PROBE31_WIDTH=32,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=2,C_PROBE34_WIDTH=32,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=4,C_PROBE37_WIDTH=2,C_PROBE38_WIDTH=3,C_PROBE39_WIDTH=2,C_PROBE40_WIDTH=2,C_PROBE41_WIDTH=3,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=160,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
|
||||
"C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,"&
|
||||
"C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,"&
|
||||
"C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,"&
|
||||
@@ -4269,7 +4271,7 @@ ATTRIBUTE CORE_GENERATION_INFO OF bd_eb4d_ila_lib_0_arch : ARCHITECTURE IS "bd_e
|
||||
"C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,"&
|
||||
"C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,"&
|
||||
"C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,"&
|
||||
"C_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=0,C_PROBE12_TYPE=0,C_PROBE13_TYPE=0,C_PROBE14_TYPE=0,C_PROBE15_TYPE=0,C_PROBE16_TYPE=0,C_PROBE17_TYPE=0,C_PROBE18_TYPE=0,C_PROBE19_TYPE=0,C_PROBE20_TYPE=0,C_PROBE21_TYPE=0,C_PROBE22_TYPE=0,C_PROBE23_TYPE=0,C_PROBE24_TYPE=0,C_PROBE25_TYPE=0,C_PROBE26_TYPE=0,C_PROBE27_TYPE=0,C_PROBE28_TYPE=0,C_PROBE29_TYPE=0,C_PROBE30_TYPE=0,C_PROBE31_TYPE=0,C_PROBE32_TYPE=0,C_PROBE33_TYPE=0,C_PROBE34_TYPE=0,C_PROBE35_TYPE=0,C_PROBE36_TYPE=0,C_PROBE37_TYPE=0,C_PROBE38_TYPE=0,C_PROBE39_TYPE=0,C_PROBE40_TYPE=0,C_PROBE41_TYPE=0,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,"&
|
||||
"C_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=0,C_PROBE12_TYPE=0,C_PROBE13_TYPE=0,C_PROBE14_TYPE=0,C_PROBE15_TYPE=0,C_PROBE16_TYPE=0,C_PROBE17_TYPE=0,C_PROBE18_TYPE=0,C_PROBE19_TYPE=0,C_PROBE20_TYPE=0,C_PROBE21_TYPE=0,C_PROBE22_TYPE=0,C_PROBE23_TYPE=0,C_PROBE24_TYPE=0,C_PROBE25_TYPE=0,C_PROBE26_TYPE=0,C_PROBE27_TYPE=0,C_PROBE28_TYPE=0,C_PROBE29_TYPE=0,C_PROBE30_TYPE=0,C_PROBE31_TYPE=0,C_PROBE32_TYPE=0,C_PROBE33_TYPE=0,C_PROBE34_TYPE=0,C_PROBE35_TYPE=0,C_PROBE36_TYPE=0,C_PROBE37_TYPE=0,C_PROBE38_TYPE=0,C_PROBE39_TYPE=0,C_PROBE40_TYPE=0,C_PROBE41_TYPE=0,C_PROBE42_TYPE=0,C_PROBE43_TYPE=0,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,"&
|
||||
"C_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,"&
|
||||
"C_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_PROBE248_TYPE=1,C_PROBE249_TYPE=1,C_PROBE250_TYPE=1,C_PROBE251_TYPE=1,C_PROBE252_TYPE=1,C_PROBE253_TYPE=1,C_PROBE254_TYPE=1,C_PROBE255_TYPE=1,C_PROBE256_TYPE=1,C_PROBE257_TYPE=1,C_PROBE258_TYPE=1,C_PROBE259_TYPE=1,C_PROBE260_TYPE=1,C_PROBE261_TYPE=1,C_PROBE262_TYPE=1,C_PROBE263_TYPE=1,C_PROBE264_TYPE=1,C_PROBE265_TYPE=1,C_PROBE266_TYPE=1,C_PROBE267_TYPE=1,C_PROBE268_TYPE=1,C_PROBE269_TYPE=1,C_PROBE270_TYPE=1,C_PROBE271_TYPE=1,C_PROBE272_TYPE=1,C_PROBE273_TYPE=1,C_PROBE274_TYPE=1,C_PROBE275_TYPE=1,C_PROBE276_TYPE=1,C_PROBE277_TYPE=1,C_PROBE278_TYPE=1,C_PROBE279_TYPE=1,C_PROBE280_TYPE=1,C_PROBE281_TYPE=1,C_PROBE282_TYPE=1,C_PROBE283_TYPE=1,C_PROBE284_TYPE=1,C_PROBE285_TYPE=1,C_PROBE286_TYPE=1,C_PROBE287_TYPE=1,C_PROBE288_TYPE=1,C_PROBE289_TYPE=1,C_PROBE290_TYPE=1,C_PROBE291_TYPE=1,C_PROBE292_TYPE=1,C_PROBE293_TYPE=1,C_PROBE294_TYPE=1,C_PROBE295_TYPE=1,C_PROBE296_TYPE=1,C_PROBE297_TYPE=1,C_PROBE298_TYPE=1,C_PROBE299_TYPE=1,C_PROBE300_TYPE=1,C_PROBE301_TYPE=1,C_PROBE302_TYPE=1,C_PROBE303_TYPE=1,C_PROBE304_TYPE=1,C_PROBE305_TYPE=1,"&
|
||||
"C_PROBE306_TYPE=1,C_PROBE307_TYPE=1,C_PROBE308_TYPE=1,C_PROBE309_TYPE=1,C_PROBE310_TYPE=1,C_PROBE311_TYPE=1,C_PROBE312_TYPE=1,C_PROBE313_TYPE=1,C_PROBE314_TYPE=1,C_PROBE315_TYPE=1,C_PROBE316_TYPE=1,C_PROBE317_TYPE=1,C_PROBE318_TYPE=1,C_PROBE319_TYPE=1,C_PROBE320_TYPE=1,C_PROBE321_TYPE=1,C_PROBE322_TYPE=1,C_PROBE323_TYPE=1,C_PROBE324_TYPE=1,C_PROBE325_TYPE=1,C_PROBE326_TYPE=1,C_PROBE327_TYPE=1,C_PROBE328_TYPE=1,C_PROBE329_TYPE=1,C_PROBE330_TYPE=1,C_PROBE331_TYPE=1,C_PROBE332_TYPE=1,C_PROBE333_TYPE=1,C_PROBE334_TYPE=1,C_PROBE335_TYPE=1,C_PROBE336_TYPE=1,C_PROBE337_TYPE=1,C_PROBE338_TYPE=1,C_PROBE339_TYPE=1,C_PROBE340_TYPE=1,C_PROBE341_TYPE=1,C_PROBE342_TYPE=1,C_PROBE343_TYPE=1,C_PROBE344_TYPE=1,C_PROBE345_TYPE=1,C_PROBE346_TYPE=1,C_PROBE347_TYPE=1,C_PROBE348_TYPE=1,C_PROBE349_TYPE=1,C_PROBE350_TYPE=1,C_PROBE351_TYPE=1,C_PROBE352_TYPE=1,C_PROBE353_TYPE=1,C_PROBE354_TYPE=1,C_PROBE355_TYPE=1,C_PROBE356_TYPE=1,C_PROBE357_TYPE=1,C_PROBE358_TYPE=1,C_PROBE359_TYPE=1,C_PROBE360_TYPE=1,C_PROBE361_TYPE=1,C_PROBE362_TYPE=1,C_PROBE363_TYPE=1,C_PROBE364_TYPE=1,C_PROBE365_TYPE=1,C_PROBE366_TYPE=1,C_PROBE367_TYPE=1,C_PROBE368_TYPE=1,C_PROBE369_TYPE=1,C_PROBE370_TYPE=1,C_PROBE371_TYPE=1,C_PROBE372_TYPE=1,C_PROBE373_TYPE=1,C_PROBE374_TYPE=1,C_PROBE375_TYPE=1,C_PROBE376_TYPE=1,C_PROBE377_TYPE=1,C_PROBE378_TYPE=1,C_PROBE379_TYPE=1,C_PROBE380_TYPE=1,C_PROBE381_TYPE=1,C_PROBE382_TYPE=1,C_PROBE383_TYPE=1,C_PROBE384_TYPE=1,C_PROBE385_TYPE=1,C_PROBE386_TYPE=1,C_PROBE387_TYPE=1,C_PROBE388_TYPE=1,C_PROBE389_TYPE=1,C_PROBE390_TYPE=1,C_PROBE391_TYPE=1,C_PROBE392_TYPE=1,C_PROBE393_TYPE=1,C_PROBE394_TYPE=1,C_PROBE395_TYPE=1,C_PROBE396_TYPE=1,C_PROBE397_TYPE=1,C_PROBE398_TYPE=1,C_PROBE399_TYPE=1,C_PROBE400_TYPE=1,C_PROBE401_TYPE=1,C_PROBE402_TYPE=1,C_PROBE403_TYPE=1,C_PROBE404_TYPE=1,C_PROBE405_TYPE=1,"&
|
||||
@@ -4295,7 +4297,7 @@ C_CORE_INFO2 => 0,
|
||||
C_CAPTURE_TYPE => 0,
|
||||
C_MU_TYPE => 0,
|
||||
C_TC_TYPE => 0,
|
||||
C_NUM_OF_PROBES => 42,
|
||||
C_NUM_OF_PROBES => 44,
|
||||
C_DATA_DEPTH => 8192,
|
||||
C_MAJOR_VERSION => 2023,
|
||||
C_MINOR_VERSION => 1,
|
||||
@@ -4361,7 +4363,7 @@ C_PROBE39_WIDTH => 2,
|
||||
C_PROBE40_WIDTH => 2,
|
||||
C_PROBE41_WIDTH => 3,
|
||||
C_PROBE42_WIDTH => 1,
|
||||
C_PROBE43_WIDTH => 1,
|
||||
C_PROBE43_WIDTH => 160,
|
||||
C_PROBE44_WIDTH => 1,
|
||||
C_PROBE45_WIDTH => 1,
|
||||
C_PROBE46_WIDTH => 1,
|
||||
@@ -6408,8 +6410,8 @@ C_PROBE38_TYPE => 0,
|
||||
C_PROBE39_TYPE => 0,
|
||||
C_PROBE40_TYPE => 0,
|
||||
C_PROBE41_TYPE => 0,
|
||||
C_PROBE42_TYPE => 1,
|
||||
C_PROBE43_TYPE => 1,
|
||||
C_PROBE42_TYPE => 0,
|
||||
C_PROBE43_TYPE => 0,
|
||||
C_PROBE44_TYPE => 1,
|
||||
C_PROBE45_TYPE => 1,
|
||||
C_PROBE46_TYPE => 1,
|
||||
@@ -7441,8 +7443,8 @@ probe38 => probe38,
|
||||
probe39 => probe39,
|
||||
probe40 => probe40,
|
||||
probe41 => probe41,
|
||||
probe42 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
probe43 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
probe42 => probe42,
|
||||
probe43 => probe43,
|
||||
probe44 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
probe45 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
probe46 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
|
||||
+4
-4
@@ -31172,7 +31172,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31192,7 +31192,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31212,7 +31212,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31232,7 +31232,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+340
@@ -0,0 +1,340 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_eb4d_slot_0_apc_0",
|
||||
"cell_name": "slot_0_apc",
|
||||
"component_reference": "xilinx.com:ip:axi_protocol_checker:2.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_RD_BURSTS": [ { "value": "2", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_WR_BURSTS": [ { "value": "2", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_SYSTEM_RESET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_AW_WAITS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_AR_WAITS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_W_WAITS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_R_WAITS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_B_WAITS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"MAX_WLAST_TO_AWVALID_WAITS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"MAX_CONTINUOUS_RTRANSFERS_WAITS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MESSAGE_LEVEL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"PC_MASTER_SIDE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_CONTROL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_MARK_DEBUG": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CHK_ERR_RESP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
},
|
||||
"model_parameters": {
|
||||
"C_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_MAXRBURSTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_MAXWBURSTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_EXMON_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_AW_MAXWAITS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_AR_MAXWAITS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_W_MAXWAITS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_R_MAXWAITS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_B_MAXWAITS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_MAX_CONTINUOUS_RTRANSFERS_WAITS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_MAX_CONTINUOUS_WTRANSFERS_WAITS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_MAX_WLAST_TO_AWVALID_WAITS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_MAX_WRITE_TO_BVALID_WAITS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_LIGHT_WEIGHT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_MASTER_SIDE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_MESSAGE_LEVEL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_SUPPORTS_NARROW_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_MAX_BURST_LENGTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_HAS_SYSTEM_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_CONTROL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PC_STATUS_WIDTH": [ { "value": "160", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHK_ERR_RESP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MARK_DEBUG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"pc_status": [ { "direction": "out", "size_left": "159", "size_right": "0" } ],
|
||||
"pc_asserted": [ { "direction": "out" } ],
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"pc_axi_awid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"pc_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
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|
||||
"pc_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"pc_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"pc_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"pc_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"pc_axi_arready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"pc_axi_rid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"pc_axi_rlast": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"pc_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"pc_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"pc_axi_rvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"pc_axi_rready": [ { "direction": "in", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"PC_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "monitor",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "pc_axi_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "pc_axi_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "pc_axi_arcache" } ],
|
||||
"ARID": [ { "physical_name": "pc_axi_arid" } ],
|
||||
"ARLEN": [ { "physical_name": "pc_axi_arlen" } ],
|
||||
"ARLOCK": [ { "physical_name": "pc_axi_arlock" } ],
|
||||
"ARPROT": [ { "physical_name": "pc_axi_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "pc_axi_arqos" } ],
|
||||
"ARREADY": [ { "physical_name": "pc_axi_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "pc_axi_arsize" } ],
|
||||
"ARVALID": [ { "physical_name": "pc_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "pc_axi_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "pc_axi_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "pc_axi_awcache" } ],
|
||||
"AWID": [ { "physical_name": "pc_axi_awid" } ],
|
||||
"AWLEN": [ { "physical_name": "pc_axi_awlen" } ],
|
||||
"AWLOCK": [ { "physical_name": "pc_axi_awlock" } ],
|
||||
"AWPROT": [ { "physical_name": "pc_axi_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "pc_axi_awqos" } ],
|
||||
"AWREADY": [ { "physical_name": "pc_axi_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "pc_axi_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "pc_axi_awvalid" } ],
|
||||
"BID": [ { "physical_name": "pc_axi_bid" } ],
|
||||
"BREADY": [ { "physical_name": "pc_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "pc_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "pc_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "pc_axi_rdata" } ],
|
||||
"RID": [ { "physical_name": "pc_axi_rid" } ],
|
||||
"RLAST": [ { "physical_name": "pc_axi_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "pc_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "pc_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "pc_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "pc_axi_wdata" } ],
|
||||
"WID": [ { "physical_name": "pc_axi_wid" } ],
|
||||
"WLAST": [ { "physical_name": "pc_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "pc_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "pc_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "pc_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:PC_AXI", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4k",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-only",
|
||||
"registers": {
|
||||
"PC_asserted": {
|
||||
"address_offset": "0x000",
|
||||
"size": 1,
|
||||
"display_name": "PC_asserted",
|
||||
"description": "PC_asserted",
|
||||
"access": "read-only"
|
||||
},
|
||||
"Current_PC[31:0]": {
|
||||
"address_offset": "0x100",
|
||||
"size": 1,
|
||||
"display_name": "Current_PC[31:0]",
|
||||
"description": "Current value of pc_status[31:0]",
|
||||
"access": "read-only"
|
||||
},
|
||||
"Current_PC[63:32]": {
|
||||
"address_offset": "0x104",
|
||||
"size": 1,
|
||||
"display_name": "Current_PC[63:32]",
|
||||
"description": "Current value of pc_status[63:32]",
|
||||
"access": "read-only"
|
||||
},
|
||||
"Current_PC[95:64]": {
|
||||
"address_offset": "0x108",
|
||||
"size": 1,
|
||||
"display_name": "Current_PC[95:64]",
|
||||
"description": "Current value of pc_status[95:64]",
|
||||
"access": "read-only"
|
||||
},
|
||||
"Current_PC[127:96]": {
|
||||
"address_offset": "0x10C",
|
||||
"size": 1,
|
||||
"display_name": "Current_PC[127:96]",
|
||||
"description": "Current value of pc_status[127:96]",
|
||||
"access": "read-only"
|
||||
},
|
||||
"Snapshot_PC[31:0]": {
|
||||
"address_offset": "0x200",
|
||||
"size": 1,
|
||||
"display_name": "Snapshot_PC[31:0]",
|
||||
"description": "First event value of pc_status[31:0]",
|
||||
"access": "read-only"
|
||||
},
|
||||
"Snapshot_PC[63:32]": {
|
||||
"address_offset": "0x204",
|
||||
"size": 1,
|
||||
"display_name": "Snapshot_PC[63:32]",
|
||||
"description": "First event value of pc_status[63:32]",
|
||||
"access": "read-only"
|
||||
},
|
||||
"Snapshot_PC[95:64]": {
|
||||
"address_offset": "0x208",
|
||||
"size": 1,
|
||||
"display_name": "Snapshot_PC[95:64]",
|
||||
"description": "First event value of pc_status[95:64]",
|
||||
"access": "read-only"
|
||||
},
|
||||
"Snapshot_PC[127:96]": {
|
||||
"address_offset": "0x20C",
|
||||
"size": 1,
|
||||
"display_name": "Snapshot_PC[127:96]",
|
||||
"description": "First event value of pc_status[127:96]",
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+3308
File diff suppressed because it is too large
Load Diff
+280
@@ -0,0 +1,280 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_checker:2.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_eb4d_slot_0_apc_0 (
|
||||
pc_status,
|
||||
pc_asserted,
|
||||
aclk,
|
||||
aresetn,
|
||||
pc_axi_awid,
|
||||
pc_axi_awaddr,
|
||||
pc_axi_awlen,
|
||||
pc_axi_awsize,
|
||||
pc_axi_awburst,
|
||||
pc_axi_awlock,
|
||||
pc_axi_awcache,
|
||||
pc_axi_awprot,
|
||||
pc_axi_awqos,
|
||||
pc_axi_awvalid,
|
||||
pc_axi_awready,
|
||||
pc_axi_wid,
|
||||
pc_axi_wlast,
|
||||
pc_axi_wdata,
|
||||
pc_axi_wstrb,
|
||||
pc_axi_wvalid,
|
||||
pc_axi_wready,
|
||||
pc_axi_bid,
|
||||
pc_axi_bresp,
|
||||
pc_axi_bvalid,
|
||||
pc_axi_bready,
|
||||
pc_axi_arid,
|
||||
pc_axi_araddr,
|
||||
pc_axi_arlen,
|
||||
pc_axi_arsize,
|
||||
pc_axi_arburst,
|
||||
pc_axi_arlock,
|
||||
pc_axi_arcache,
|
||||
pc_axi_arprot,
|
||||
pc_axi_arqos,
|
||||
pc_axi_arvalid,
|
||||
pc_axi_arready,
|
||||
pc_axi_rid,
|
||||
pc_axi_rlast,
|
||||
pc_axi_rdata,
|
||||
pc_axi_rresp,
|
||||
pc_axi_rvalid,
|
||||
pc_axi_rready
|
||||
);
|
||||
|
||||
output wire [159 : 0] pc_status;
|
||||
output wire pc_asserted;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWID" *)
|
||||
input wire [0 : 0] pc_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWADDR" *)
|
||||
input wire [31 : 0] pc_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWLEN" *)
|
||||
input wire [3 : 0] pc_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWSIZE" *)
|
||||
input wire [2 : 0] pc_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWBURST" *)
|
||||
input wire [1 : 0] pc_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWLOCK" *)
|
||||
input wire [1 : 0] pc_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWCACHE" *)
|
||||
input wire [3 : 0] pc_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWPROT" *)
|
||||
input wire [2 : 0] pc_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWQOS" *)
|
||||
input wire [3 : 0] pc_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWVALID" *)
|
||||
input wire pc_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWREADY" *)
|
||||
input wire pc_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WID" *)
|
||||
input wire [0 : 0] pc_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WLAST" *)
|
||||
input wire pc_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WDATA" *)
|
||||
input wire [31 : 0] pc_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WSTRB" *)
|
||||
input wire [3 : 0] pc_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WVALID" *)
|
||||
input wire pc_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WREADY" *)
|
||||
input wire pc_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI BID" *)
|
||||
input wire [0 : 0] pc_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI BRESP" *)
|
||||
input wire [1 : 0] pc_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI BVALID" *)
|
||||
input wire pc_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI BREADY" *)
|
||||
input wire pc_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARID" *)
|
||||
input wire [0 : 0] pc_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARADDR" *)
|
||||
input wire [31 : 0] pc_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARLEN" *)
|
||||
input wire [3 : 0] pc_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARSIZE" *)
|
||||
input wire [2 : 0] pc_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARBURST" *)
|
||||
input wire [1 : 0] pc_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARLOCK" *)
|
||||
input wire [1 : 0] pc_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARCACHE" *)
|
||||
input wire [3 : 0] pc_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARPROT" *)
|
||||
input wire [2 : 0] pc_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARQOS" *)
|
||||
input wire [3 : 0] pc_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARVALID" *)
|
||||
input wire pc_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARREADY" *)
|
||||
input wire pc_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RID" *)
|
||||
input wire [0 : 0] pc_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RLAST" *)
|
||||
input wire pc_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RDATA" *)
|
||||
input wire [31 : 0] pc_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RRESP" *)
|
||||
input wire [1 : 0] pc_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RVALID" *)
|
||||
input wire pc_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, NUM_READ_\
|
||||
THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RREADY" *)
|
||||
input wire pc_axi_rready;
|
||||
|
||||
axi_protocol_checker_v2_0_14_top #(
|
||||
.C_AXI_PROTOCOL(1),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_HAS_WSTRB(1),
|
||||
.C_PC_MAXRBURSTS(2),
|
||||
.C_PC_MAXWBURSTS(2),
|
||||
.C_PC_EXMON_WIDTH(0),
|
||||
.C_PC_AW_MAXWAITS(0),
|
||||
.C_PC_AR_MAXWAITS(0),
|
||||
.C_PC_W_MAXWAITS(0),
|
||||
.C_PC_R_MAXWAITS(0),
|
||||
.C_PC_B_MAXWAITS(0),
|
||||
.C_PC_MAX_CONTINUOUS_RTRANSFERS_WAITS(0),
|
||||
.C_PC_MAX_CONTINUOUS_WTRANSFERS_WAITS(0),
|
||||
.C_PC_MAX_WLAST_TO_AWVALID_WAITS(0),
|
||||
.C_PC_MAX_WRITE_TO_BVALID_WAITS(0),
|
||||
.C_PC_LIGHT_WEIGHT(0),
|
||||
.C_PC_MASTER_SIDE(0),
|
||||
.C_PC_MESSAGE_LEVEL(2),
|
||||
.C_PC_SUPPORTS_NARROW_BURST(1),
|
||||
.C_PC_MAX_BURST_LENGTH(16),
|
||||
.C_PC_HAS_SYSTEM_RESET(0),
|
||||
.C_ENABLE_CONTROL(0),
|
||||
.C_PC_STATUS_WIDTH(160),
|
||||
.C_CHK_ERR_RESP(0),
|
||||
.C_ENABLE_MARK_DEBUG(0)
|
||||
) inst (
|
||||
.pc_status(pc_status),
|
||||
.pc_asserted(pc_asserted),
|
||||
.system_resetn(1'D1),
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.pc_axi_awid(pc_axi_awid),
|
||||
.pc_axi_awaddr(pc_axi_awaddr),
|
||||
.pc_axi_awlen(pc_axi_awlen),
|
||||
.pc_axi_awsize(pc_axi_awsize),
|
||||
.pc_axi_awburst(pc_axi_awburst),
|
||||
.pc_axi_awlock(pc_axi_awlock),
|
||||
.pc_axi_awcache(pc_axi_awcache),
|
||||
.pc_axi_awprot(pc_axi_awprot),
|
||||
.pc_axi_awqos(pc_axi_awqos),
|
||||
.pc_axi_awregion(4'D0),
|
||||
.pc_axi_awuser(1'H0),
|
||||
.pc_axi_awvalid(pc_axi_awvalid),
|
||||
.pc_axi_awready(pc_axi_awready),
|
||||
.pc_axi_wid(pc_axi_wid),
|
||||
.pc_axi_wlast(pc_axi_wlast),
|
||||
.pc_axi_wdata(pc_axi_wdata),
|
||||
.pc_axi_wstrb(pc_axi_wstrb),
|
||||
.pc_axi_wuser(1'H0),
|
||||
.pc_axi_wvalid(pc_axi_wvalid),
|
||||
.pc_axi_wready(pc_axi_wready),
|
||||
.pc_axi_bid(pc_axi_bid),
|
||||
.pc_axi_bresp(pc_axi_bresp),
|
||||
.pc_axi_buser(1'H0),
|
||||
.pc_axi_bvalid(pc_axi_bvalid),
|
||||
.pc_axi_bready(pc_axi_bready),
|
||||
.pc_axi_arid(pc_axi_arid),
|
||||
.pc_axi_araddr(pc_axi_araddr),
|
||||
.pc_axi_arlen(pc_axi_arlen),
|
||||
.pc_axi_arsize(pc_axi_arsize),
|
||||
.pc_axi_arburst(pc_axi_arburst),
|
||||
.pc_axi_arlock(pc_axi_arlock),
|
||||
.pc_axi_arcache(pc_axi_arcache),
|
||||
.pc_axi_arprot(pc_axi_arprot),
|
||||
.pc_axi_arqos(pc_axi_arqos),
|
||||
.pc_axi_arregion(4'D0),
|
||||
.pc_axi_aruser(1'H0),
|
||||
.pc_axi_arvalid(pc_axi_arvalid),
|
||||
.pc_axi_arready(pc_axi_arready),
|
||||
.pc_axi_rid(pc_axi_rid),
|
||||
.pc_axi_rlast(pc_axi_rlast),
|
||||
.pc_axi_rdata(pc_axi_rdata),
|
||||
.pc_axi_rresp(pc_axi_rresp),
|
||||
.pc_axi_ruser(1'H0),
|
||||
.pc_axi_rvalid(pc_axi_rvalid),
|
||||
.pc_axi_rready(pc_axi_rready),
|
||||
.s_axi_araddr(10'D0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0)
|
||||
);
|
||||
endmodule
|
||||
+282
@@ -0,0 +1,282 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_checker:2.0
|
||||
// IP Revision: 14
|
||||
|
||||
(* X_CORE_INFO = "axi_protocol_checker_v2_0_14_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_eb4d_slot_0_apc_0,axi_protocol_checker_v2_0_14_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_eb4d_slot_0_apc_0,axi_protocol_checker_v2_0_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_checker,x_ipVersion=2.0,x_ipCoreRevision=14,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_AXI_PROTOCOL=1,C_AXI_ID_WIDTH=1,C_AXI_DATA_WIDTH=32,C_AXI_ADDR_WIDTH=32,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_HAS_WSTRB=1,C_PC_MAXRBURSTS=2,C_PC_MAXWBURSTS=2,C_PC_EXMON_WIDTH=0,C_PC_AW_MAXWAITS=0,C_PC_AR_MAXW\
|
||||
AITS=0,C_PC_W_MAXWAITS=0,C_PC_R_MAXWAITS=0,C_PC_B_MAXWAITS=0,C_PC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_PC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_PC_MAX_WLAST_TO_AWVALID_WAITS=0,C_PC_MAX_WRITE_TO_BVALID_WAITS=0,C_PC_LIGHT_WEIGHT=0,C_PC_MASTER_SIDE=0,C_PC_MESSAGE_LEVEL=2,C_PC_SUPPORTS_NARROW_BURST=1,C_PC_MAX_BURST_LENGTH=16,C_PC_HAS_SYSTEM_RESET=0,C_ENABLE_CONTROL=0,C_PC_STATUS_WIDTH=160,C_CHK_ERR_RESP=0,C_ENABLE_MARK_DEBUG=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_eb4d_slot_0_apc_0 (
|
||||
pc_status,
|
||||
pc_asserted,
|
||||
aclk,
|
||||
aresetn,
|
||||
pc_axi_awid,
|
||||
pc_axi_awaddr,
|
||||
pc_axi_awlen,
|
||||
pc_axi_awsize,
|
||||
pc_axi_awburst,
|
||||
pc_axi_awlock,
|
||||
pc_axi_awcache,
|
||||
pc_axi_awprot,
|
||||
pc_axi_awqos,
|
||||
pc_axi_awvalid,
|
||||
pc_axi_awready,
|
||||
pc_axi_wid,
|
||||
pc_axi_wlast,
|
||||
pc_axi_wdata,
|
||||
pc_axi_wstrb,
|
||||
pc_axi_wvalid,
|
||||
pc_axi_wready,
|
||||
pc_axi_bid,
|
||||
pc_axi_bresp,
|
||||
pc_axi_bvalid,
|
||||
pc_axi_bready,
|
||||
pc_axi_arid,
|
||||
pc_axi_araddr,
|
||||
pc_axi_arlen,
|
||||
pc_axi_arsize,
|
||||
pc_axi_arburst,
|
||||
pc_axi_arlock,
|
||||
pc_axi_arcache,
|
||||
pc_axi_arprot,
|
||||
pc_axi_arqos,
|
||||
pc_axi_arvalid,
|
||||
pc_axi_arready,
|
||||
pc_axi_rid,
|
||||
pc_axi_rlast,
|
||||
pc_axi_rdata,
|
||||
pc_axi_rresp,
|
||||
pc_axi_rvalid,
|
||||
pc_axi_rready
|
||||
);
|
||||
|
||||
output wire [159 : 0] pc_status;
|
||||
output wire pc_asserted;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWID" *)
|
||||
input wire [0 : 0] pc_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWADDR" *)
|
||||
input wire [31 : 0] pc_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWLEN" *)
|
||||
input wire [3 : 0] pc_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWSIZE" *)
|
||||
input wire [2 : 0] pc_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWBURST" *)
|
||||
input wire [1 : 0] pc_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWLOCK" *)
|
||||
input wire [1 : 0] pc_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWCACHE" *)
|
||||
input wire [3 : 0] pc_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWPROT" *)
|
||||
input wire [2 : 0] pc_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWQOS" *)
|
||||
input wire [3 : 0] pc_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWVALID" *)
|
||||
input wire pc_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI AWREADY" *)
|
||||
input wire pc_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WID" *)
|
||||
input wire [0 : 0] pc_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WLAST" *)
|
||||
input wire pc_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WDATA" *)
|
||||
input wire [31 : 0] pc_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WSTRB" *)
|
||||
input wire [3 : 0] pc_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WVALID" *)
|
||||
input wire pc_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI WREADY" *)
|
||||
input wire pc_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI BID" *)
|
||||
input wire [0 : 0] pc_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI BRESP" *)
|
||||
input wire [1 : 0] pc_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI BVALID" *)
|
||||
input wire pc_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI BREADY" *)
|
||||
input wire pc_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARID" *)
|
||||
input wire [0 : 0] pc_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARADDR" *)
|
||||
input wire [31 : 0] pc_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARLEN" *)
|
||||
input wire [3 : 0] pc_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARSIZE" *)
|
||||
input wire [2 : 0] pc_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARBURST" *)
|
||||
input wire [1 : 0] pc_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARLOCK" *)
|
||||
input wire [1 : 0] pc_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARCACHE" *)
|
||||
input wire [3 : 0] pc_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARPROT" *)
|
||||
input wire [2 : 0] pc_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARQOS" *)
|
||||
input wire [3 : 0] pc_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARVALID" *)
|
||||
input wire pc_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI ARREADY" *)
|
||||
input wire pc_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RID" *)
|
||||
input wire [0 : 0] pc_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RLAST" *)
|
||||
input wire pc_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RDATA" *)
|
||||
input wire [31 : 0] pc_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RRESP" *)
|
||||
input wire [1 : 0] pc_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RVALID" *)
|
||||
input wire pc_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, NUM_READ_\
|
||||
THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RREADY" *)
|
||||
input wire pc_axi_rready;
|
||||
|
||||
axi_protocol_checker_v2_0_14_top #(
|
||||
.C_AXI_PROTOCOL(1),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_HAS_WSTRB(1),
|
||||
.C_PC_MAXRBURSTS(2),
|
||||
.C_PC_MAXWBURSTS(2),
|
||||
.C_PC_EXMON_WIDTH(0),
|
||||
.C_PC_AW_MAXWAITS(0),
|
||||
.C_PC_AR_MAXWAITS(0),
|
||||
.C_PC_W_MAXWAITS(0),
|
||||
.C_PC_R_MAXWAITS(0),
|
||||
.C_PC_B_MAXWAITS(0),
|
||||
.C_PC_MAX_CONTINUOUS_RTRANSFERS_WAITS(0),
|
||||
.C_PC_MAX_CONTINUOUS_WTRANSFERS_WAITS(0),
|
||||
.C_PC_MAX_WLAST_TO_AWVALID_WAITS(0),
|
||||
.C_PC_MAX_WRITE_TO_BVALID_WAITS(0),
|
||||
.C_PC_LIGHT_WEIGHT(0),
|
||||
.C_PC_MASTER_SIDE(0),
|
||||
.C_PC_MESSAGE_LEVEL(2),
|
||||
.C_PC_SUPPORTS_NARROW_BURST(1),
|
||||
.C_PC_MAX_BURST_LENGTH(16),
|
||||
.C_PC_HAS_SYSTEM_RESET(0),
|
||||
.C_ENABLE_CONTROL(0),
|
||||
.C_PC_STATUS_WIDTH(160),
|
||||
.C_CHK_ERR_RESP(0),
|
||||
.C_ENABLE_MARK_DEBUG(0)
|
||||
) inst (
|
||||
.pc_status(pc_status),
|
||||
.pc_asserted(pc_asserted),
|
||||
.system_resetn(1'D1),
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.pc_axi_awid(pc_axi_awid),
|
||||
.pc_axi_awaddr(pc_axi_awaddr),
|
||||
.pc_axi_awlen(pc_axi_awlen),
|
||||
.pc_axi_awsize(pc_axi_awsize),
|
||||
.pc_axi_awburst(pc_axi_awburst),
|
||||
.pc_axi_awlock(pc_axi_awlock),
|
||||
.pc_axi_awcache(pc_axi_awcache),
|
||||
.pc_axi_awprot(pc_axi_awprot),
|
||||
.pc_axi_awqos(pc_axi_awqos),
|
||||
.pc_axi_awregion(4'D0),
|
||||
.pc_axi_awuser(1'H0),
|
||||
.pc_axi_awvalid(pc_axi_awvalid),
|
||||
.pc_axi_awready(pc_axi_awready),
|
||||
.pc_axi_wid(pc_axi_wid),
|
||||
.pc_axi_wlast(pc_axi_wlast),
|
||||
.pc_axi_wdata(pc_axi_wdata),
|
||||
.pc_axi_wstrb(pc_axi_wstrb),
|
||||
.pc_axi_wuser(1'H0),
|
||||
.pc_axi_wvalid(pc_axi_wvalid),
|
||||
.pc_axi_wready(pc_axi_wready),
|
||||
.pc_axi_bid(pc_axi_bid),
|
||||
.pc_axi_bresp(pc_axi_bresp),
|
||||
.pc_axi_buser(1'H0),
|
||||
.pc_axi_bvalid(pc_axi_bvalid),
|
||||
.pc_axi_bready(pc_axi_bready),
|
||||
.pc_axi_arid(pc_axi_arid),
|
||||
.pc_axi_araddr(pc_axi_araddr),
|
||||
.pc_axi_arlen(pc_axi_arlen),
|
||||
.pc_axi_arsize(pc_axi_arsize),
|
||||
.pc_axi_arburst(pc_axi_arburst),
|
||||
.pc_axi_arlock(pc_axi_arlock),
|
||||
.pc_axi_arcache(pc_axi_arcache),
|
||||
.pc_axi_arprot(pc_axi_arprot),
|
||||
.pc_axi_arqos(pc_axi_arqos),
|
||||
.pc_axi_arregion(4'D0),
|
||||
.pc_axi_aruser(1'H0),
|
||||
.pc_axi_arvalid(pc_axi_arvalid),
|
||||
.pc_axi_arready(pc_axi_arready),
|
||||
.pc_axi_rid(pc_axi_rid),
|
||||
.pc_axi_rlast(pc_axi_rlast),
|
||||
.pc_axi_rdata(pc_axi_rdata),
|
||||
.pc_axi_rresp(pc_axi_rresp),
|
||||
.pc_axi_ruser(1'H0),
|
||||
.pc_axi_rvalid(pc_axi_rvalid),
|
||||
.pc_axi_rready(pc_axi_rready),
|
||||
.s_axi_araddr(10'D0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0)
|
||||
);
|
||||
endmodule
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:26 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
+115
-2
@@ -16,7 +16,9 @@ entity bd_eb4d is
|
||||
SLOT_0_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_0_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
@@ -25,7 +27,9 @@ entity bd_eb4d is
|
||||
SLOT_0_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_0_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
@@ -60,7 +64,7 @@ entity bd_eb4d is
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of bd_eb4d : entity is "bd_eb4d,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_eb4d,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
|
||||
attribute CORE_GENERATION_INFO of bd_eb4d : entity is "bd_eb4d,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_eb4d,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=8,numReposBlks=8,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of bd_eb4d : entity is "crc_axi_master_syn_system_ila_0_0.hwdef";
|
||||
end bd_eb4d;
|
||||
@@ -110,7 +114,9 @@ architecture STRUCTURE of bd_eb4d is
|
||||
probe38 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 2 downto 0 )
|
||||
probe41 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 159 downto 0 )
|
||||
);
|
||||
end component bd_eb4d_ila_lib_0;
|
||||
component bd_eb4d_g_inst_0 is
|
||||
@@ -191,6 +197,52 @@ architecture STRUCTURE of bd_eb4d is
|
||||
m_slot_0_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component bd_eb4d_g_inst_0;
|
||||
component bd_eb4d_slot_0_apc_0 is
|
||||
port (
|
||||
pc_status : out STD_LOGIC_VECTOR ( 159 downto 0 );
|
||||
pc_asserted : out STD_LOGIC;
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
pc_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
pc_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
pc_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
pc_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_awvalid : in STD_LOGIC;
|
||||
pc_axi_awready : in STD_LOGIC;
|
||||
pc_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_wlast : in STD_LOGIC;
|
||||
pc_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
pc_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_wvalid : in STD_LOGIC;
|
||||
pc_axi_wready : in STD_LOGIC;
|
||||
pc_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_bvalid : in STD_LOGIC;
|
||||
pc_axi_bready : in STD_LOGIC;
|
||||
pc_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
pc_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
pc_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
pc_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_arvalid : in STD_LOGIC;
|
||||
pc_axi_arready : in STD_LOGIC;
|
||||
pc_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_rlast : in STD_LOGIC;
|
||||
pc_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
pc_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_rvalid : in STD_LOGIC;
|
||||
pc_axi_rready : in STD_LOGIC
|
||||
);
|
||||
end component bd_eb4d_slot_0_apc_0;
|
||||
component bd_eb4d_slot_0_aw_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
@@ -233,7 +285,9 @@ architecture STRUCTURE of bd_eb4d is
|
||||
signal Conn_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal Conn_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_ARREADY : STD_LOGIC;
|
||||
signal Conn_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_ARVALID : STD_LOGIC;
|
||||
@@ -242,7 +296,9 @@ architecture STRUCTURE of bd_eb4d is
|
||||
signal Conn_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal Conn_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_AWREADY : STD_LOGIC;
|
||||
signal Conn_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_AWVALID : STD_LOGIC;
|
||||
@@ -263,6 +319,8 @@ architecture STRUCTURE of bd_eb4d is
|
||||
signal Conn_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_WVALID : STD_LOGIC;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal net_slot_0_apc_pc_asserted : STD_LOGIC;
|
||||
signal net_slot_0_apc_pc_status : STD_LOGIC_VECTOR ( 159 downto 0 );
|
||||
signal net_slot_0_axi_ar_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_ar_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
@@ -342,14 +400,18 @@ architecture STRUCTURE of bd_eb4d is
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARCACHE";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARLEN";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARLOCK";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARQOS";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARSIZE";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWBURST";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWCACHE";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWLEN";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWLOCK";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWQOS";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWSIZE";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
|
||||
@@ -365,7 +427,9 @@ begin
|
||||
Conn_ARCACHE(3 downto 0) <= SLOT_0_AXI_arcache(3 downto 0);
|
||||
Conn_ARID(0) <= SLOT_0_AXI_arid(0);
|
||||
Conn_ARLEN(3 downto 0) <= SLOT_0_AXI_arlen(3 downto 0);
|
||||
Conn_ARLOCK(1 downto 0) <= SLOT_0_AXI_arlock(1 downto 0);
|
||||
Conn_ARPROT(2 downto 0) <= SLOT_0_AXI_arprot(2 downto 0);
|
||||
Conn_ARQOS(3 downto 0) <= SLOT_0_AXI_arqos(3 downto 0);
|
||||
Conn_ARREADY <= SLOT_0_AXI_arready;
|
||||
Conn_ARSIZE(2 downto 0) <= SLOT_0_AXI_arsize(2 downto 0);
|
||||
Conn_ARVALID <= SLOT_0_AXI_arvalid;
|
||||
@@ -374,7 +438,9 @@ begin
|
||||
Conn_AWCACHE(3 downto 0) <= SLOT_0_AXI_awcache(3 downto 0);
|
||||
Conn_AWID(0) <= SLOT_0_AXI_awid(0);
|
||||
Conn_AWLEN(3 downto 0) <= SLOT_0_AXI_awlen(3 downto 0);
|
||||
Conn_AWLOCK(1 downto 0) <= SLOT_0_AXI_awlock(1 downto 0);
|
||||
Conn_AWPROT(2 downto 0) <= SLOT_0_AXI_awprot(2 downto 0);
|
||||
Conn_AWQOS(3 downto 0) <= SLOT_0_AXI_awqos(3 downto 0);
|
||||
Conn_AWREADY <= SLOT_0_AXI_awready;
|
||||
Conn_AWSIZE(2 downto 0) <= SLOT_0_AXI_awsize(2 downto 0);
|
||||
Conn_AWVALID <= SLOT_0_AXI_awvalid;
|
||||
@@ -524,12 +590,59 @@ ila_lib: component bd_eb4d_ila_lib_0
|
||||
probe4(0) => probe4_1(0),
|
||||
probe40(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
|
||||
probe41(2 downto 0) => net_slot_0_axi_r_ctrl(2 downto 0),
|
||||
probe42(0) => net_slot_0_apc_pc_asserted,
|
||||
probe43(159 downto 0) => net_slot_0_apc_pc_status(159 downto 0),
|
||||
probe5(0) => probe5_1(0),
|
||||
probe6(3 downto 0) => probe6_1(3 downto 0),
|
||||
probe7(0) => probe7_1(0),
|
||||
probe8(3 downto 0) => probe8_1(3 downto 0),
|
||||
probe9(31 downto 0) => probe9_1(31 downto 0)
|
||||
);
|
||||
slot_0_apc: component bd_eb4d_slot_0_apc_0
|
||||
port map (
|
||||
aclk => clk_1,
|
||||
aresetn => resetn_1,
|
||||
pc_asserted => net_slot_0_apc_pc_asserted,
|
||||
pc_axi_araddr(31 downto 0) => Conn_ARADDR(31 downto 0),
|
||||
pc_axi_arburst(1 downto 0) => Conn_ARBURST(1 downto 0),
|
||||
pc_axi_arcache(3 downto 0) => Conn_ARCACHE(3 downto 0),
|
||||
pc_axi_arid(0) => Conn_ARID(0),
|
||||
pc_axi_arlen(3 downto 0) => Conn_ARLEN(3 downto 0),
|
||||
pc_axi_arlock(1 downto 0) => Conn_ARLOCK(1 downto 0),
|
||||
pc_axi_arprot(2 downto 0) => Conn_ARPROT(2 downto 0),
|
||||
pc_axi_arqos(3 downto 0) => Conn_ARQOS(3 downto 0),
|
||||
pc_axi_arready => Conn_ARREADY,
|
||||
pc_axi_arsize(2 downto 0) => Conn_ARSIZE(2 downto 0),
|
||||
pc_axi_arvalid => Conn_ARVALID,
|
||||
pc_axi_awaddr(31 downto 0) => Conn_AWADDR(31 downto 0),
|
||||
pc_axi_awburst(1 downto 0) => Conn_AWBURST(1 downto 0),
|
||||
pc_axi_awcache(3 downto 0) => Conn_AWCACHE(3 downto 0),
|
||||
pc_axi_awid(0) => Conn_AWID(0),
|
||||
pc_axi_awlen(3 downto 0) => Conn_AWLEN(3 downto 0),
|
||||
pc_axi_awlock(1 downto 0) => Conn_AWLOCK(1 downto 0),
|
||||
pc_axi_awprot(2 downto 0) => Conn_AWPROT(2 downto 0),
|
||||
pc_axi_awqos(3 downto 0) => Conn_AWQOS(3 downto 0),
|
||||
pc_axi_awready => Conn_AWREADY,
|
||||
pc_axi_awsize(2 downto 0) => Conn_AWSIZE(2 downto 0),
|
||||
pc_axi_awvalid => Conn_AWVALID,
|
||||
pc_axi_bid(0) => Conn_BID(0),
|
||||
pc_axi_bready => Conn_BREADY,
|
||||
pc_axi_bresp(1 downto 0) => Conn_BRESP(1 downto 0),
|
||||
pc_axi_bvalid => Conn_BVALID,
|
||||
pc_axi_rdata(31 downto 0) => Conn_RDATA(31 downto 0),
|
||||
pc_axi_rid(0) => Conn_RID(0),
|
||||
pc_axi_rlast => Conn_RLAST,
|
||||
pc_axi_rready => Conn_RREADY,
|
||||
pc_axi_rresp(1 downto 0) => Conn_RRESP(1 downto 0),
|
||||
pc_axi_rvalid => Conn_RVALID,
|
||||
pc_axi_wdata(31 downto 0) => Conn_WDATA(31 downto 0),
|
||||
pc_axi_wid(0) => Conn_WID(0),
|
||||
pc_axi_wlast => Conn_WLAST,
|
||||
pc_axi_wready => Conn_WREADY,
|
||||
pc_axi_wstrb(3 downto 0) => Conn_WSTRB(3 downto 0),
|
||||
pc_axi_wvalid => Conn_WVALID,
|
||||
pc_status(159 downto 0) => net_slot_0_apc_pc_status(159 downto 0)
|
||||
);
|
||||
slot_0_ar: component bd_eb4d_slot_0_ar_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_arvalid,
|
||||
|
||||
+115
-2
@@ -16,7 +16,9 @@ entity bd_eb4d is
|
||||
SLOT_0_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_0_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
@@ -25,7 +27,9 @@ entity bd_eb4d is
|
||||
SLOT_0_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_0_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
@@ -60,7 +64,7 @@ entity bd_eb4d is
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of bd_eb4d : entity is "bd_eb4d,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_eb4d,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
|
||||
attribute CORE_GENERATION_INFO of bd_eb4d : entity is "bd_eb4d,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_eb4d,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=8,numReposBlks=8,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of bd_eb4d : entity is "crc_axi_master_syn_system_ila_0_0.hwdef";
|
||||
end bd_eb4d;
|
||||
@@ -110,7 +114,9 @@ architecture STRUCTURE of bd_eb4d is
|
||||
probe38 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 2 downto 0 )
|
||||
probe41 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 159 downto 0 )
|
||||
);
|
||||
end component bd_eb4d_ila_lib_0;
|
||||
component bd_eb4d_g_inst_0 is
|
||||
@@ -191,6 +197,52 @@ architecture STRUCTURE of bd_eb4d is
|
||||
m_slot_0_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component bd_eb4d_g_inst_0;
|
||||
component bd_eb4d_slot_0_apc_0 is
|
||||
port (
|
||||
pc_status : out STD_LOGIC_VECTOR ( 159 downto 0 );
|
||||
pc_asserted : out STD_LOGIC;
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
pc_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
pc_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
pc_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
pc_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_awvalid : in STD_LOGIC;
|
||||
pc_axi_awready : in STD_LOGIC;
|
||||
pc_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_wlast : in STD_LOGIC;
|
||||
pc_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
pc_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_wvalid : in STD_LOGIC;
|
||||
pc_axi_wready : in STD_LOGIC;
|
||||
pc_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_bvalid : in STD_LOGIC;
|
||||
pc_axi_bready : in STD_LOGIC;
|
||||
pc_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
pc_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
pc_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
pc_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pc_axi_arvalid : in STD_LOGIC;
|
||||
pc_axi_arready : in STD_LOGIC;
|
||||
pc_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
pc_axi_rlast : in STD_LOGIC;
|
||||
pc_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
pc_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
pc_axi_rvalid : in STD_LOGIC;
|
||||
pc_axi_rready : in STD_LOGIC
|
||||
);
|
||||
end component bd_eb4d_slot_0_apc_0;
|
||||
component bd_eb4d_slot_0_aw_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
@@ -233,7 +285,9 @@ architecture STRUCTURE of bd_eb4d is
|
||||
signal Conn_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal Conn_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_ARREADY : STD_LOGIC;
|
||||
signal Conn_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_ARVALID : STD_LOGIC;
|
||||
@@ -242,7 +296,9 @@ architecture STRUCTURE of bd_eb4d is
|
||||
signal Conn_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal Conn_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_AWREADY : STD_LOGIC;
|
||||
signal Conn_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_AWVALID : STD_LOGIC;
|
||||
@@ -263,6 +319,8 @@ architecture STRUCTURE of bd_eb4d is
|
||||
signal Conn_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_WVALID : STD_LOGIC;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal net_slot_0_apc_pc_asserted : STD_LOGIC;
|
||||
signal net_slot_0_apc_pc_status : STD_LOGIC_VECTOR ( 159 downto 0 );
|
||||
signal net_slot_0_axi_ar_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_ar_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
@@ -342,14 +400,18 @@ architecture STRUCTURE of bd_eb4d is
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARCACHE";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARLEN";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARLOCK";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARQOS";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARSIZE";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWBURST";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWCACHE";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWLEN";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWLOCK";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWQOS";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWSIZE";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
|
||||
@@ -365,7 +427,9 @@ begin
|
||||
Conn_ARCACHE(3 downto 0) <= SLOT_0_AXI_arcache(3 downto 0);
|
||||
Conn_ARID(0) <= SLOT_0_AXI_arid(0);
|
||||
Conn_ARLEN(3 downto 0) <= SLOT_0_AXI_arlen(3 downto 0);
|
||||
Conn_ARLOCK(1 downto 0) <= SLOT_0_AXI_arlock(1 downto 0);
|
||||
Conn_ARPROT(2 downto 0) <= SLOT_0_AXI_arprot(2 downto 0);
|
||||
Conn_ARQOS(3 downto 0) <= SLOT_0_AXI_arqos(3 downto 0);
|
||||
Conn_ARREADY <= SLOT_0_AXI_arready;
|
||||
Conn_ARSIZE(2 downto 0) <= SLOT_0_AXI_arsize(2 downto 0);
|
||||
Conn_ARVALID <= SLOT_0_AXI_arvalid;
|
||||
@@ -374,7 +438,9 @@ begin
|
||||
Conn_AWCACHE(3 downto 0) <= SLOT_0_AXI_awcache(3 downto 0);
|
||||
Conn_AWID(0) <= SLOT_0_AXI_awid(0);
|
||||
Conn_AWLEN(3 downto 0) <= SLOT_0_AXI_awlen(3 downto 0);
|
||||
Conn_AWLOCK(1 downto 0) <= SLOT_0_AXI_awlock(1 downto 0);
|
||||
Conn_AWPROT(2 downto 0) <= SLOT_0_AXI_awprot(2 downto 0);
|
||||
Conn_AWQOS(3 downto 0) <= SLOT_0_AXI_awqos(3 downto 0);
|
||||
Conn_AWREADY <= SLOT_0_AXI_awready;
|
||||
Conn_AWSIZE(2 downto 0) <= SLOT_0_AXI_awsize(2 downto 0);
|
||||
Conn_AWVALID <= SLOT_0_AXI_awvalid;
|
||||
@@ -524,12 +590,59 @@ ila_lib: component bd_eb4d_ila_lib_0
|
||||
probe4(0) => probe4_1(0),
|
||||
probe40(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
|
||||
probe41(2 downto 0) => net_slot_0_axi_r_ctrl(2 downto 0),
|
||||
probe42(0) => net_slot_0_apc_pc_asserted,
|
||||
probe43(159 downto 0) => net_slot_0_apc_pc_status(159 downto 0),
|
||||
probe5(0) => probe5_1(0),
|
||||
probe6(3 downto 0) => probe6_1(3 downto 0),
|
||||
probe7(0) => probe7_1(0),
|
||||
probe8(3 downto 0) => probe8_1(3 downto 0),
|
||||
probe9(31 downto 0) => probe9_1(31 downto 0)
|
||||
);
|
||||
slot_0_apc: component bd_eb4d_slot_0_apc_0
|
||||
port map (
|
||||
aclk => clk_1,
|
||||
aresetn => resetn_1,
|
||||
pc_asserted => net_slot_0_apc_pc_asserted,
|
||||
pc_axi_araddr(31 downto 0) => Conn_ARADDR(31 downto 0),
|
||||
pc_axi_arburst(1 downto 0) => Conn_ARBURST(1 downto 0),
|
||||
pc_axi_arcache(3 downto 0) => Conn_ARCACHE(3 downto 0),
|
||||
pc_axi_arid(0) => Conn_ARID(0),
|
||||
pc_axi_arlen(3 downto 0) => Conn_ARLEN(3 downto 0),
|
||||
pc_axi_arlock(1 downto 0) => Conn_ARLOCK(1 downto 0),
|
||||
pc_axi_arprot(2 downto 0) => Conn_ARPROT(2 downto 0),
|
||||
pc_axi_arqos(3 downto 0) => Conn_ARQOS(3 downto 0),
|
||||
pc_axi_arready => Conn_ARREADY,
|
||||
pc_axi_arsize(2 downto 0) => Conn_ARSIZE(2 downto 0),
|
||||
pc_axi_arvalid => Conn_ARVALID,
|
||||
pc_axi_awaddr(31 downto 0) => Conn_AWADDR(31 downto 0),
|
||||
pc_axi_awburst(1 downto 0) => Conn_AWBURST(1 downto 0),
|
||||
pc_axi_awcache(3 downto 0) => Conn_AWCACHE(3 downto 0),
|
||||
pc_axi_awid(0) => Conn_AWID(0),
|
||||
pc_axi_awlen(3 downto 0) => Conn_AWLEN(3 downto 0),
|
||||
pc_axi_awlock(1 downto 0) => Conn_AWLOCK(1 downto 0),
|
||||
pc_axi_awprot(2 downto 0) => Conn_AWPROT(2 downto 0),
|
||||
pc_axi_awqos(3 downto 0) => Conn_AWQOS(3 downto 0),
|
||||
pc_axi_awready => Conn_AWREADY,
|
||||
pc_axi_awsize(2 downto 0) => Conn_AWSIZE(2 downto 0),
|
||||
pc_axi_awvalid => Conn_AWVALID,
|
||||
pc_axi_bid(0) => Conn_BID(0),
|
||||
pc_axi_bready => Conn_BREADY,
|
||||
pc_axi_bresp(1 downto 0) => Conn_BRESP(1 downto 0),
|
||||
pc_axi_bvalid => Conn_BVALID,
|
||||
pc_axi_rdata(31 downto 0) => Conn_RDATA(31 downto 0),
|
||||
pc_axi_rid(0) => Conn_RID(0),
|
||||
pc_axi_rlast => Conn_RLAST,
|
||||
pc_axi_rready => Conn_RREADY,
|
||||
pc_axi_rresp(1 downto 0) => Conn_RRESP(1 downto 0),
|
||||
pc_axi_rvalid => Conn_RVALID,
|
||||
pc_axi_wdata(31 downto 0) => Conn_WDATA(31 downto 0),
|
||||
pc_axi_wid(0) => Conn_WID(0),
|
||||
pc_axi_wlast => Conn_WLAST,
|
||||
pc_axi_wready => Conn_WREADY,
|
||||
pc_axi_wstrb(3 downto 0) => Conn_WSTRB(3 downto 0),
|
||||
pc_axi_wvalid => Conn_WVALID,
|
||||
pc_status(159 downto 0) => net_slot_0_apc_pc_status(159 downto 0)
|
||||
);
|
||||
slot_0_ar: component bd_eb4d_slot_0_ar_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_arvalid,
|
||||
|
||||
+138
-17
@@ -177,6 +177,14 @@
|
||||
<spirit:name>SLOT_0_AXI_awburst</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWLOCK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXI_awlock</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWCACHE</spirit:name>
|
||||
@@ -193,6 +201,14 @@
|
||||
<spirit:name>SLOT_0_AXI_awprot</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWQOS</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXI_awqos</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWVALID</spirit:name>
|
||||
@@ -329,6 +345,14 @@
|
||||
<spirit:name>SLOT_0_AXI_arburst</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARLOCK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXI_arlock</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARCACHE</spirit:name>
|
||||
@@ -345,6 +369,14 @@
|
||||
<spirit:name>SLOT_0_AXI_arprot</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARQOS</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXI_arqos</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARVALID</spirit:name>
|
||||
@@ -706,11 +738,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:23 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:54 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ac6c272e</spirit:value>
|
||||
<spirit:value>9:42fffda7</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -724,11 +756,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:03:19 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:37 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:94672c98</spirit:value>
|
||||
<spirit:value>9:15681c1f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -742,11 +774,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Jan 29 15:40:58 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:22 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4e700f09</spirit:value>
|
||||
<spirit:value>9:8660f532</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -760,11 +792,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:24:01 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:22:12 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ac6c272e</spirit:value>
|
||||
<spirit:value>9:42fffda7</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -779,11 +811,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:23 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:54 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ac6c272e</spirit:value>
|
||||
<spirit:value>9:42fffda7</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -796,7 +828,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:b817298a</spirit:value>
|
||||
<spirit:value>9:29378921</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -812,11 +848,15 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Jan 29 19:18:39 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:54 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:b817298a</spirit:value>
|
||||
<spirit:value>9:29378921</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -832,11 +872,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:23:23 UTC 2025</spirit:value>
|
||||
<spirit:value>Fri Jan 31 00:17:54 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ac6c272e</spirit:value>
|
||||
<spirit:value>9:42fffda7</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1175,6 +1215,26 @@
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXI_awlock</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXI_awcache</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -1215,6 +1275,26 @@
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXI_awqos</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXI_awvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -1527,6 +1607,26 @@
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXI_arlock</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXI_arcache</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -1567,6 +1667,26 @@
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXI_arqos</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXI_arvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -3533,7 +3653,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_SLOT_0_APC_STS_EN</spirit:name>
|
||||
<spirit:displayName>Slot 0 APC STS MON </spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SLOT_0_APC_STS_EN" spirit:choiceRef="choice_pairs_d116085a" spirit:order="2.103804e+08">0</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SLOT_0_APC_STS_EN" spirit:choiceRef="choice_pairs_d116085a" spirit:order="2.103804e+08">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
@@ -3725,7 +3845,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_SLOT_0_APC_EN</spirit:name>
|
||||
<spirit:displayName>Slot 0 APC EN</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SLOT_0_APC_EN" spirit:choiceRef="choice_pairs_d116085a" spirit:order="2.103801e+08">0</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SLOT_0_APC_EN" spirit:choiceRef="choice_pairs_d116085a" spirit:order="2.103801e+08">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
@@ -37244,6 +37364,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE8_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE9_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_APC_EN" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_APC_STS_EN" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_AXIS_TDATA_WIDTH" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_AXIS_TDEST_WIDTH" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_AXIS_TID_WIDTH" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+103823
-68628
File diff suppressed because one or more lines are too long
+15
-10
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jan 29 20:23:54 2025
|
||||
// Date : Fri Jan 31 01:22:07 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top crc_axi_master_syn_system_ila_0_0 -prefix
|
||||
// crc_axi_master_syn_system_ila_0_0_ crc_axi_master_syn_system_ila_0_0_stub.v
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_system_ila_0_0/crc_axi_master_syn_system_ila_0_0_stub.v
|
||||
// Design : crc_axi_master_syn_system_ila_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
@@ -17,15 +17,16 @@
|
||||
(* x_core_info = "bd_eb4d,Vivado 2023.1" *)
|
||||
module crc_axi_master_syn_system_ila_0_0(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, SLOT_0_AXI_awid, SLOT_0_AXI_awaddr, SLOT_0_AXI_awlen,
|
||||
SLOT_0_AXI_awsize, SLOT_0_AXI_awburst, SLOT_0_AXI_awcache, SLOT_0_AXI_awprot,
|
||||
SLOT_0_AXI_awvalid, SLOT_0_AXI_awready, SLOT_0_AXI_wid, SLOT_0_AXI_wdata,
|
||||
SLOT_0_AXI_wstrb, SLOT_0_AXI_wlast, SLOT_0_AXI_wvalid, SLOT_0_AXI_wready, SLOT_0_AXI_bid,
|
||||
SLOT_0_AXI_bresp, SLOT_0_AXI_bvalid, SLOT_0_AXI_bready, SLOT_0_AXI_arid,
|
||||
SLOT_0_AXI_araddr, SLOT_0_AXI_arlen, SLOT_0_AXI_arsize, SLOT_0_AXI_arburst,
|
||||
SLOT_0_AXI_arcache, SLOT_0_AXI_arprot, SLOT_0_AXI_arvalid, SLOT_0_AXI_arready,
|
||||
SLOT_0_AXI_awsize, SLOT_0_AXI_awburst, SLOT_0_AXI_awlock, SLOT_0_AXI_awcache,
|
||||
SLOT_0_AXI_awprot, SLOT_0_AXI_awqos, SLOT_0_AXI_awvalid, SLOT_0_AXI_awready,
|
||||
SLOT_0_AXI_wid, SLOT_0_AXI_wdata, SLOT_0_AXI_wstrb, SLOT_0_AXI_wlast, SLOT_0_AXI_wvalid,
|
||||
SLOT_0_AXI_wready, SLOT_0_AXI_bid, SLOT_0_AXI_bresp, SLOT_0_AXI_bvalid,
|
||||
SLOT_0_AXI_bready, SLOT_0_AXI_arid, SLOT_0_AXI_araddr, SLOT_0_AXI_arlen,
|
||||
SLOT_0_AXI_arsize, SLOT_0_AXI_arburst, SLOT_0_AXI_arlock, SLOT_0_AXI_arcache,
|
||||
SLOT_0_AXI_arprot, SLOT_0_AXI_arqos, SLOT_0_AXI_arvalid, SLOT_0_AXI_arready,
|
||||
SLOT_0_AXI_rid, SLOT_0_AXI_rdata, SLOT_0_AXI_rresp, SLOT_0_AXI_rlast, SLOT_0_AXI_rvalid,
|
||||
SLOT_0_AXI_rready, resetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[0:0],probe1[31:0],probe2[3:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[3:0],probe7[0:0],probe8[3:0],probe9[31:0],probe10[0:0],SLOT_0_AXI_awid[0:0],SLOT_0_AXI_awaddr[31:0],SLOT_0_AXI_awlen[3:0],SLOT_0_AXI_awsize[2:0],SLOT_0_AXI_awburst[1:0],SLOT_0_AXI_awcache[3:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wid[0:0],SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wlast,SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bid[0:0],SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_arid[0:0],SLOT_0_AXI_araddr[31:0],SLOT_0_AXI_arlen[3:0],SLOT_0_AXI_arsize[2:0],SLOT_0_AXI_arburst[1:0],SLOT_0_AXI_arcache[3:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rid[0:0],SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rlast,SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,resetn" */
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[0:0],probe1[31:0],probe2[3:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[3:0],probe7[0:0],probe8[3:0],probe9[31:0],probe10[0:0],SLOT_0_AXI_awid[0:0],SLOT_0_AXI_awaddr[31:0],SLOT_0_AXI_awlen[3:0],SLOT_0_AXI_awsize[2:0],SLOT_0_AXI_awburst[1:0],SLOT_0_AXI_awlock[1:0],SLOT_0_AXI_awcache[3:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awqos[3:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wid[0:0],SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wlast,SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bid[0:0],SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_arid[0:0],SLOT_0_AXI_araddr[31:0],SLOT_0_AXI_arlen[3:0],SLOT_0_AXI_arsize[2:0],SLOT_0_AXI_arburst[1:0],SLOT_0_AXI_arlock[1:0],SLOT_0_AXI_arcache[3:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arqos[3:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rid[0:0],SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rlast,SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,resetn" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [0:0]probe0;
|
||||
@@ -44,8 +45,10 @@ module crc_axi_master_syn_system_ila_0_0(clk, probe0, probe1, probe2, probe3, pr
|
||||
input [3:0]SLOT_0_AXI_awlen;
|
||||
input [2:0]SLOT_0_AXI_awsize;
|
||||
input [1:0]SLOT_0_AXI_awburst;
|
||||
input [1:0]SLOT_0_AXI_awlock;
|
||||
input [3:0]SLOT_0_AXI_awcache;
|
||||
input [2:0]SLOT_0_AXI_awprot;
|
||||
input [3:0]SLOT_0_AXI_awqos;
|
||||
input SLOT_0_AXI_awvalid;
|
||||
input SLOT_0_AXI_awready;
|
||||
input [0:0]SLOT_0_AXI_wid;
|
||||
@@ -63,8 +66,10 @@ module crc_axi_master_syn_system_ila_0_0(clk, probe0, probe1, probe2, probe3, pr
|
||||
input [3:0]SLOT_0_AXI_arlen;
|
||||
input [2:0]SLOT_0_AXI_arsize;
|
||||
input [1:0]SLOT_0_AXI_arburst;
|
||||
input [1:0]SLOT_0_AXI_arlock;
|
||||
input [3:0]SLOT_0_AXI_arcache;
|
||||
input [2:0]SLOT_0_AXI_arprot;
|
||||
input [3:0]SLOT_0_AXI_arqos;
|
||||
input SLOT_0_AXI_arvalid;
|
||||
input SLOT_0_AXI_arready;
|
||||
input [0:0]SLOT_0_AXI_rid;
|
||||
|
||||
+16
@@ -72,8 +72,10 @@ ENTITY crc_axi_master_syn_system_ila_0_0 IS
|
||||
SLOT_0_AXI_awlen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -91,8 +93,10 @@ ENTITY crc_axi_master_syn_system_ila_0_0 IS
|
||||
SLOT_0_AXI_arlen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_arready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -127,8 +131,10 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
|
||||
SLOT_0_AXI_awlen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -146,8 +152,10 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
|
||||
SLOT_0_AXI_arlen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_arready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -166,7 +174,9 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arqos: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARQOS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
|
||||
@@ -177,7 +187,9 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
|
||||
"EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awqos: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWQOS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
|
||||
@@ -221,8 +233,10 @@ BEGIN
|
||||
SLOT_0_AXI_awlen => SLOT_0_AXI_awlen,
|
||||
SLOT_0_AXI_awsize => SLOT_0_AXI_awsize,
|
||||
SLOT_0_AXI_awburst => SLOT_0_AXI_awburst,
|
||||
SLOT_0_AXI_awlock => SLOT_0_AXI_awlock,
|
||||
SLOT_0_AXI_awcache => SLOT_0_AXI_awcache,
|
||||
SLOT_0_AXI_awprot => SLOT_0_AXI_awprot,
|
||||
SLOT_0_AXI_awqos => SLOT_0_AXI_awqos,
|
||||
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
|
||||
SLOT_0_AXI_awready => SLOT_0_AXI_awready,
|
||||
SLOT_0_AXI_wid => SLOT_0_AXI_wid,
|
||||
@@ -240,8 +254,10 @@ BEGIN
|
||||
SLOT_0_AXI_arlen => SLOT_0_AXI_arlen,
|
||||
SLOT_0_AXI_arsize => SLOT_0_AXI_arsize,
|
||||
SLOT_0_AXI_arburst => SLOT_0_AXI_arburst,
|
||||
SLOT_0_AXI_arlock => SLOT_0_AXI_arlock,
|
||||
SLOT_0_AXI_arcache => SLOT_0_AXI_arcache,
|
||||
SLOT_0_AXI_arprot => SLOT_0_AXI_arprot,
|
||||
SLOT_0_AXI_arqos => SLOT_0_AXI_arqos,
|
||||
SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
|
||||
SLOT_0_AXI_arready => SLOT_0_AXI_arready,
|
||||
SLOT_0_AXI_rid => SLOT_0_AXI_rid,
|
||||
|
||||
+18
-2
@@ -72,8 +72,10 @@ ENTITY crc_axi_master_syn_system_ila_0_0 IS
|
||||
SLOT_0_AXI_awlen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -91,8 +93,10 @@ ENTITY crc_axi_master_syn_system_ila_0_0 IS
|
||||
SLOT_0_AXI_arlen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_arready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -127,8 +131,10 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
|
||||
SLOT_0_AXI_awlen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -146,8 +152,10 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
|
||||
SLOT_0_AXI_arlen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_arvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_arready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -167,8 +175,8 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF crc_axi_master_syn_system_ila_0_0_arch: ARCHITECTURE IS "crc_axi_master_syn_system_ila_0_0,bd_eb4d,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=system_ila,x_ipVersion=1.1,x_ipCoreRevision=14,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_SLOT=0,C_SLOT_15_TYPE=0,C_SLOT_14_TYPE=0,C_SLOT_13_TYPE=0,C_SLOT_12_TYPE=0,C_SLOT_11_TYPE=0,C_SLOT_10_TYPE=0,C_SLOT_9_TYPE=0,C_SLOT_8_TYPE=0,C_SLOT_7_TYPE=0,C_SLOT_6_TYPE=0,C_SLOT_5_TYPE=0,C_SLOT_4_TYPE=0,C_SLOT_3_TYPE=0,C_SLOT_2_TYPE=0,C_SLOT_1_TYPE=0,C_SLOT_" &
|
||||
"0_TYPE=0,C_SLOT_0_MAX_RD_BURSTS=2,C_SLOT_0_MAX_WR_BURSTS=2,C_SLOT_1_MAX_RD_BURSTS=2,C_SLOT_1_MAX_WR_BURSTS=2,C_SLOT_2_MAX_RD_BURSTS=2,C_SLOT_2_MAX_WR_BURSTS=2,C_SLOT_3_MAX_RD_BURSTS=2,C_SLOT_3_MAX_WR_BURSTS=2,C_SLOT_4_MAX_RD_BURSTS=2,C_SLOT_4_MAX_WR_BURSTS=2,C_SLOT_5_MAX_RD_BURSTS=2,C_SLOT_5_MAX_WR_BURSTS=2,C_SLOT_6_MAX_RD_BURSTS=2,C_SLOT_6_MAX_WR_BURSTS=2,C_SLOT_7_MAX_RD_BURSTS=2,C_SLOT_7_MAX_WR_BURSTS=2,C_SLOT_8_MAX_RD_BURSTS=2,C_SLOT_8_MAX_WR_BURSTS=2,C_SLOT_9_MAX_RD_BURSTS=2,C_SLOT_9_MAX_WR_" &
|
||||
"BURSTS=2,C_SLOT_10_MAX_RD_BURSTS=2,C_SLOT_10_MAX_WR_BURSTS=2,C_SLOT_11_MAX_RD_BURSTS=2,C_SLOT_11_MAX_WR_BURSTS=2,C_SLOT_12_MAX_RD_BURSTS=2,C_SLOT_12_MAX_WR_BURSTS=2,C_SLOT_13_MAX_RD_BURSTS=2,C_SLOT_13_MAX_WR_BURSTS=2,C_SLOT_14_MAX_RD_BURSTS=2,C_SLOT_14_MAX_WR_BURSTS=2,C_SLOT_15_MAX_RD_BURSTS=2,C_SLOT_15_MAX_WR_BURSTS=2,C_SLOT_0_TXN_CNTR_EN=1,C_SLOT_1_TXN_CNTR_EN=1,C_SLOT_2_TXN_CNTR_EN=1,C_SLOT_3_TXN_CNTR_EN=1,C_SLOT_4_TXN_CNTR_EN=1,C_SLOT_5_TXN_CNTR_EN=1,C_SLOT_6_TXN_CNTR_EN=1,C_SLOT_7_TXN_CNTR_" &
|
||||
"EN=1,C_SLOT_8_TXN_CNTR_EN=1,C_SLOT_9_TXN_CNTR_EN=1,C_SLOT_10_TXN_CNTR_EN=1,C_SLOT_11_TXN_CNTR_EN=1,C_SLOT_12_TXN_CNTR_EN=1,C_SLOT_13_TXN_CNTR_EN=1,C_SLOT_14_TXN_CNTR_EN=1,C_SLOT_15_TXN_CNTR_EN=1,C_SLOT_0_APC_STS_EN=0,C_SLOT_1_APC_STS_EN=0,C_SLOT_2_APC_STS_EN=0,C_SLOT_3_APC_STS_EN=0,C_SLOT_4_APC_STS_EN=0,C_SLOT_5_APC_STS_EN=0,C_SLOT_6_APC_STS_EN=0,C_SLOT_7_APC_STS_EN=0,C_SLOT_8_APC_STS_EN=0,C_SLOT_9_APC_STS_EN=0,C_SLOT_10_APC_STS_EN=0,C_SLOT_11_APC_STS_EN=0,C_SLOT_12_APC_STS_EN=0,C_SLOT_13_APC_ST" &
|
||||
"S_EN=0,C_SLOT_14_APC_STS_EN=0,C_SLOT_15_APC_STS_EN=0,C_SLOT_0_APC_EN=0,C_SLOT_1_APC_EN=0,C_SLOT_2_APC_EN=0,C_SLOT_3_APC_EN=0,C_SLOT_4_APC_EN=0,C_SLOT_5_APC_EN=0,C_SLOT_6_APC_EN=0,C_SLOT_7_APC_EN=0,C_SLOT_8_APC_EN=0,C_SLOT_9_APC_EN=0,C_SLOT_10_APC_EN=0,C_SLOT_11_APC_EN=0,C_SLOT_12_APC_EN=0,C_SLOT_13_APC_EN=0,C_SLOT_14_APC_EN=0,C_SLOT_15_APC_EN=0,C_SLOT_0_APC_MAX_AW_WAITS=0,C_SLOT_0_APC_MAX_AR_WAITS=0,C_SLOT_0_APC_MAX_W_WAITS=0,C_SLOT_0_APC_MAX_B_WAITS=0,C_SLOT_0_APC_MAX_R_WAITS=0,C_SLOT_0_APC_MAX" &
|
||||
"EN=1,C_SLOT_8_TXN_CNTR_EN=1,C_SLOT_9_TXN_CNTR_EN=1,C_SLOT_10_TXN_CNTR_EN=1,C_SLOT_11_TXN_CNTR_EN=1,C_SLOT_12_TXN_CNTR_EN=1,C_SLOT_13_TXN_CNTR_EN=1,C_SLOT_14_TXN_CNTR_EN=1,C_SLOT_15_TXN_CNTR_EN=1,C_SLOT_0_APC_STS_EN=1,C_SLOT_1_APC_STS_EN=0,C_SLOT_2_APC_STS_EN=0,C_SLOT_3_APC_STS_EN=0,C_SLOT_4_APC_STS_EN=0,C_SLOT_5_APC_STS_EN=0,C_SLOT_6_APC_STS_EN=0,C_SLOT_7_APC_STS_EN=0,C_SLOT_8_APC_STS_EN=0,C_SLOT_9_APC_STS_EN=0,C_SLOT_10_APC_STS_EN=0,C_SLOT_11_APC_STS_EN=0,C_SLOT_12_APC_STS_EN=0,C_SLOT_13_APC_ST" &
|
||||
"S_EN=0,C_SLOT_14_APC_STS_EN=0,C_SLOT_15_APC_STS_EN=0,C_SLOT_0_APC_EN=1,C_SLOT_1_APC_EN=0,C_SLOT_2_APC_EN=0,C_SLOT_3_APC_EN=0,C_SLOT_4_APC_EN=0,C_SLOT_5_APC_EN=0,C_SLOT_6_APC_EN=0,C_SLOT_7_APC_EN=0,C_SLOT_8_APC_EN=0,C_SLOT_9_APC_EN=0,C_SLOT_10_APC_EN=0,C_SLOT_11_APC_EN=0,C_SLOT_12_APC_EN=0,C_SLOT_13_APC_EN=0,C_SLOT_14_APC_EN=0,C_SLOT_15_APC_EN=0,C_SLOT_0_APC_MAX_AW_WAITS=0,C_SLOT_0_APC_MAX_AR_WAITS=0,C_SLOT_0_APC_MAX_W_WAITS=0,C_SLOT_0_APC_MAX_B_WAITS=0,C_SLOT_0_APC_MAX_R_WAITS=0,C_SLOT_0_APC_MAX" &
|
||||
"_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_0_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_0_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_0_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_AW_WAITS=0,C_SLOT_1_APC_MAX_AR_WAITS=0,C_SLOT_1_APC_MAX_W_WAITS=0,C_SLOT_1_APC_MAX_B_WAITS=0,C_SLOT_1_APC_MAX_R_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_1_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_AW_WAITS" &
|
||||
"=0,C_SLOT_2_APC_MAX_AR_WAITS=0,C_SLOT_2_APC_MAX_W_WAITS=0,C_SLOT_2_APC_MAX_B_WAITS=0,C_SLOT_2_APC_MAX_R_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_2_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_AW_WAITS=0,C_SLOT_3_APC_MAX_AR_WAITS=0,C_SLOT_3_APC_MAX_W_WAITS=0,C_SLOT_3_APC_MAX_B_WAITS=0,C_SLOT_3_APC_MAX_R_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_WLAST_TO_A" &
|
||||
"WVALID_WAITS=0,C_SLOT_3_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_AW_WAITS=0,C_SLOT_4_APC_MAX_AR_WAITS=0,C_SLOT_4_APC_MAX_W_WAITS=0,C_SLOT_4_APC_MAX_B_WAITS=0,C_SLOT_4_APC_MAX_R_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_4_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_5_APC_MAX_AW_WAITS=0,C_SLOT_5_APC_MAX_AR_WAITS=0,C_SLOT_5_APC_MAX_W_WAITS=0," &
|
||||
@@ -331,7 +339,9 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arqos: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARQOS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
|
||||
@@ -342,7 +352,9 @@ ARCHITECTURE crc_axi_master_syn_system_ila_0_0_arch OF crc_axi_master_syn_system
|
||||
"EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awqos: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWQOS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
|
||||
@@ -386,8 +398,10 @@ BEGIN
|
||||
SLOT_0_AXI_awlen => SLOT_0_AXI_awlen,
|
||||
SLOT_0_AXI_awsize => SLOT_0_AXI_awsize,
|
||||
SLOT_0_AXI_awburst => SLOT_0_AXI_awburst,
|
||||
SLOT_0_AXI_awlock => SLOT_0_AXI_awlock,
|
||||
SLOT_0_AXI_awcache => SLOT_0_AXI_awcache,
|
||||
SLOT_0_AXI_awprot => SLOT_0_AXI_awprot,
|
||||
SLOT_0_AXI_awqos => SLOT_0_AXI_awqos,
|
||||
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
|
||||
SLOT_0_AXI_awready => SLOT_0_AXI_awready,
|
||||
SLOT_0_AXI_wid => SLOT_0_AXI_wid,
|
||||
@@ -405,8 +419,10 @@ BEGIN
|
||||
SLOT_0_AXI_arlen => SLOT_0_AXI_arlen,
|
||||
SLOT_0_AXI_arsize => SLOT_0_AXI_arsize,
|
||||
SLOT_0_AXI_arburst => SLOT_0_AXI_arburst,
|
||||
SLOT_0_AXI_arlock => SLOT_0_AXI_arlock,
|
||||
SLOT_0_AXI_arcache => SLOT_0_AXI_arcache,
|
||||
SLOT_0_AXI_arprot => SLOT_0_AXI_arprot,
|
||||
SLOT_0_AXI_arqos => SLOT_0_AXI_arqos,
|
||||
SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
|
||||
SLOT_0_AXI_arready => SLOT_0_AXI_arready,
|
||||
SLOT_0_AXI_rid => SLOT_0_AXI_rid,
|
||||
|
||||
+6751
File diff suppressed because it is too large
Load Diff
+3735
File diff suppressed because it is too large
Load Diff
+56
@@ -0,0 +1,56 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="crc_axi_master_syn_HP_Port" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738284525"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738284525"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738284525"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738284525"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\crc_axi_master_syn_HP_Port.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\crc_axi_master_syn_HP_Port.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="crc_axi_master_syn_HP_Port_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\crc_axi_master_syn_HP_Port.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="crc_axi_master_syn_HP_Port.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\crc_axi_master_syn_HP_Port.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\crc_axi_master_syn_HP_Port.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 10 [get_pins PS/processing_system7_0/FCLK_CLK0]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK1 -period 8 [get_pins PS/processing_system7_0/FCLK_CLK1]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK2 -period 5 [get_pins PS/processing_system7_0/FCLK_CLK2]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK3 -period 15 [get_pins PS/processing_system7_0/FCLK_CLK3]
|
||||
|
||||
################################################################################
|
||||
+92
@@ -0,0 +1,92 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Fri Jan 31 01:48:41 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target crc_axi_master_syn_HP_Port_wrapper.bd
|
||||
--Design : crc_axi_master_syn_HP_Port_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_axi_master_syn_HP_Port_wrapper is
|
||||
port (
|
||||
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
DDR_cas_n : inout STD_LOGIC;
|
||||
DDR_ck_n : inout STD_LOGIC;
|
||||
DDR_ck_p : inout STD_LOGIC;
|
||||
DDR_cke : inout STD_LOGIC;
|
||||
DDR_cs_n : inout STD_LOGIC;
|
||||
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_odt : inout STD_LOGIC;
|
||||
DDR_ras_n : inout STD_LOGIC;
|
||||
DDR_reset_n : inout STD_LOGIC;
|
||||
DDR_we_n : inout STD_LOGIC;
|
||||
FIXED_IO_ddr_vrn : inout STD_LOGIC;
|
||||
FIXED_IO_ddr_vrp : inout STD_LOGIC;
|
||||
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
FIXED_IO_ps_clk : inout STD_LOGIC;
|
||||
FIXED_IO_ps_porb : inout STD_LOGIC;
|
||||
FIXED_IO_ps_srstb : inout STD_LOGIC
|
||||
);
|
||||
end crc_axi_master_syn_HP_Port_wrapper;
|
||||
|
||||
architecture STRUCTURE of crc_axi_master_syn_HP_Port_wrapper is
|
||||
component crc_axi_master_syn_HP_Port is
|
||||
port (
|
||||
DDR_cas_n : inout STD_LOGIC;
|
||||
DDR_cke : inout STD_LOGIC;
|
||||
DDR_ck_n : inout STD_LOGIC;
|
||||
DDR_ck_p : inout STD_LOGIC;
|
||||
DDR_cs_n : inout STD_LOGIC;
|
||||
DDR_reset_n : inout STD_LOGIC;
|
||||
DDR_odt : inout STD_LOGIC;
|
||||
DDR_ras_n : inout STD_LOGIC;
|
||||
DDR_we_n : inout STD_LOGIC;
|
||||
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
FIXED_IO_ddr_vrn : inout STD_LOGIC;
|
||||
FIXED_IO_ddr_vrp : inout STD_LOGIC;
|
||||
FIXED_IO_ps_srstb : inout STD_LOGIC;
|
||||
FIXED_IO_ps_clk : inout STD_LOGIC;
|
||||
FIXED_IO_ps_porb : inout STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_syn_HP_Port;
|
||||
begin
|
||||
crc_axi_master_syn_HP_Port_i: component crc_axi_master_syn_HP_Port
|
||||
port map (
|
||||
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
|
||||
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
|
||||
DDR_cas_n => DDR_cas_n,
|
||||
DDR_ck_n => DDR_ck_n,
|
||||
DDR_ck_p => DDR_ck_p,
|
||||
DDR_cke => DDR_cke,
|
||||
DDR_cs_n => DDR_cs_n,
|
||||
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
|
||||
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
|
||||
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
|
||||
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
|
||||
DDR_odt => DDR_odt,
|
||||
DDR_ras_n => DDR_ras_n,
|
||||
DDR_reset_n => DDR_reset_n,
|
||||
DDR_we_n => DDR_we_n,
|
||||
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
|
||||
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
|
||||
);
|
||||
end STRUCTURE;
|
||||
+1644
File diff suppressed because it is too large
Load Diff
+1715
File diff suppressed because it is too large
Load Diff
+323
-560
File diff suppressed because it is too large
Load Diff
+4
-4
@@ -2,11 +2,11 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Jan 30 23:24:59 2025
|
||||
// Date : Fri Jan 31 01:49:53 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_master_0_0/crc_axi_master_syn_crc_axi_master_0_0_stub.v
|
||||
// Design : crc_axi_master_syn_crc_axi_master_0_0
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.v
|
||||
// Design : crc_axi_master_syn_HP_Port_crc_axi_master_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
@@ -15,7 +15,7 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "crc_axi_master,Vivado 2023.1" *)
|
||||
module crc_axi_master_syn_crc_axi_master_0_0(CLK, RESETN, start, write, addr_axi, size, ip_idle,
|
||||
module crc_axi_master_syn_HP_Port_crc_axi_master_0_0(CLK, RESETN, start, write, addr_axi, size, ip_idle,
|
||||
waddr, wdata, we, raddr, rdata, re, M_AXI_ARREADY, M_AXI_ARVALID, M_AXI_ARADDR, M_AXI_ARID,
|
||||
M_AXI_ARLEN, M_AXI_ARSIZE, M_AXI_ARBURST, M_AXI_ARPROT, M_AXI_ARCACHE, M_AXI_RREADY,
|
||||
M_AXI_RVALID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RID, M_AXI_RLAST, M_AXI_AWREADY, M_AXI_AWVALID,
|
||||
+10
-10
@@ -53,7 +53,7 @@ LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_syn_crc_axi_master_0_0 IS
|
||||
ENTITY crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
@@ -103,17 +103,17 @@ ENTITY crc_axi_master_syn_crc_axi_master_0_0 IS
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END crc_axi_master_syn_crc_axi_master_0_0;
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_syn_crc_axi_master_0_0_arch OF crc_axi_master_syn_crc_axi_master_0_0 IS
|
||||
ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_crc_axi_master_0_0_arch: ARCHITECTURE IS "yes";
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_master IS
|
||||
GENERIC (
|
||||
DWIDTH : INTEGER;
|
||||
IDWIDTH : INTEGER;
|
||||
MAX_BURSTLEN : INTEGER;
|
||||
BRAM_AWIDTH : INTEGER
|
||||
LUTRAM_AWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
@@ -167,7 +167,7 @@ ARCHITECTURE crc_axi_master_syn_crc_axi_master_0_0_arch OF crc_axi_master_syn_cr
|
||||
END COMPONENT crc_axi_master;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
@@ -175,8 +175,8 @@ ARCHITECTURE crc_axi_master_syn_crc_axi_master_0_0_arch OF crc_axi_master_syn_cr
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, NUM_READ_T" &
|
||||
"HREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, NU" &
|
||||
"M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
@@ -213,7 +213,7 @@ BEGIN
|
||||
DWIDTH => 32,
|
||||
IDWIDTH => 1,
|
||||
MAX_BURSTLEN => 16,
|
||||
BRAM_AWIDTH => 4
|
||||
LUTRAM_AWIDTH => 4
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
@@ -264,4 +264,4 @@ BEGIN
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP
|
||||
);
|
||||
END crc_axi_master_syn_crc_axi_master_0_0_arch;
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch;
|
||||
+14
-14
@@ -53,7 +53,7 @@ LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_syn_crc_axi_master_0_0 IS
|
||||
ENTITY crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
@@ -103,17 +103,17 @@ ENTITY crc_axi_master_syn_crc_axi_master_0_0 IS
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END crc_axi_master_syn_crc_axi_master_0_0;
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_syn_crc_axi_master_0_0_arch OF crc_axi_master_syn_crc_axi_master_0_0 IS
|
||||
ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_crc_axi_master_0_0_arch: ARCHITECTURE IS "yes";
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_master IS
|
||||
GENERIC (
|
||||
DWIDTH : INTEGER;
|
||||
IDWIDTH : INTEGER;
|
||||
MAX_BURSTLEN : INTEGER;
|
||||
BRAM_AWIDTH : INTEGER
|
||||
LUTRAM_AWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
@@ -166,16 +166,16 @@ ARCHITECTURE crc_axi_master_syn_crc_axi_master_0_0_arch OF crc_axi_master_syn_cr
|
||||
);
|
||||
END COMPONENT crc_axi_master;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF crc_axi_master_syn_crc_axi_master_0_0_arch: ARCHITECTURE IS "crc_axi_master,Vivado 2023.1";
|
||||
ATTRIBUTE X_CORE_INFO OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "crc_axi_master,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF crc_axi_master_syn_crc_axi_master_0_0_arch : ARCHITECTURE IS "crc_axi_master_syn_crc_axi_master_0_0,crc_axi_master,{}";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch : ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_master_0_0,crc_axi_master,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF crc_axi_master_syn_crc_axi_master_0_0_arch: ARCHITECTURE IS "crc_axi_master_syn_crc_axi_master_0_0,crc_axi_master,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=crc_axi_master,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DWIDTH=32,IDWIDTH=1,MAX_BURSTLEN=16,BRAM_AWIDTH=4}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_master_0_0,crc_axi_master,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=crc_axi_master,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DWIDTH=32,IDWIDTH=1,MAX_BURSTLEN=16,LUTRAM_AWIDTH=4}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF crc_axi_master_syn_crc_axi_master_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
@@ -183,8 +183,8 @@ ARCHITECTURE crc_axi_master_syn_crc_axi_master_0_0_arch OF crc_axi_master_syn_cr
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, NUM_READ_T" &
|
||||
"HREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, NU" &
|
||||
"M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
@@ -221,7 +221,7 @@ BEGIN
|
||||
DWIDTH => 32,
|
||||
IDWIDTH => 1,
|
||||
MAX_BURSTLEN => 16,
|
||||
BRAM_AWIDTH => 4
|
||||
LUTRAM_AWIDTH => 4
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
@@ -272,4 +272,4 @@ BEGIN
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP
|
||||
);
|
||||
END crc_axi_master_syn_crc_axi_master_0_0_arch;
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch;
|
||||
+439
@@ -0,0 +1,439 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_master_control</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:804d679a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_master_control</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a33be952</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:52:52 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a33be952</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a33be952</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:52:47 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:804d679a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Jan 30 22:52:47 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a33be952</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>finished</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>start</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>write</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>addr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>size</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>axi_idle</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_master_control:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>crc_axi_master_control_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+1511
File diff suppressed because it is too large
Load Diff
+30
@@ -0,0 +1,30 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Jan 29 21:32:40 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0 -prefix
|
||||
// crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_ crc_axi_master_syn_crc_axi_master_contr_0_0_stub.v
|
||||
// Design : crc_axi_master_syn_crc_axi_master_contr_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "crc_axi_master_control,Vivado 2023.1" *)
|
||||
module crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0(clk, resetn, finished, start, write, addr, size,
|
||||
axi_idle)
|
||||
/* synthesis syn_black_box black_box_pad_pin="resetn,finished,start,write,addr[31:0],size[3:0],axi_idle" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input resetn;
|
||||
output finished;
|
||||
output start;
|
||||
output write;
|
||||
output [31:0]addr;
|
||||
output [3:0]size;
|
||||
input axi_idle;
|
||||
endmodule
|
||||
+102
@@ -0,0 +1,102 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:crc_axi_master_control:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
finished : OUT STD_LOGIC;
|
||||
start : OUT STD_LOGIC;
|
||||
write : OUT STD_LOGIC;
|
||||
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_idle : IN STD_LOGIC
|
||||
);
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_master_control IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
finished : OUT STD_LOGIC;
|
||||
start : OUT STD_LOGIC;
|
||||
write : OUT STD_LOGIC;
|
||||
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_idle : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT crc_axi_master_control;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn RST";
|
||||
BEGIN
|
||||
U0 : crc_axi_master_control
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
resetn => resetn,
|
||||
finished => finished,
|
||||
start => start,
|
||||
write => write,
|
||||
addr => addr,
|
||||
size => size,
|
||||
axi_idle => axi_idle
|
||||
);
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch;
|
||||
+110
@@ -0,0 +1,110 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:crc_axi_master_control:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
finished : OUT STD_LOGIC;
|
||||
start : OUT STD_LOGIC;
|
||||
write : OUT STD_LOGIC;
|
||||
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_idle : IN STD_LOGIC
|
||||
);
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_master_control IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
finished : OUT STD_LOGIC;
|
||||
start : OUT STD_LOGIC;
|
||||
write : OUT STD_LOGIC;
|
||||
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_idle : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT crc_axi_master_control;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "crc_axi_master_control,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch : ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0,crc_axi_master_control,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0,crc_axi_master_control,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=crc_axi_master_control,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn RST";
|
||||
BEGIN
|
||||
U0 : crc_axi_master_control
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
resetn => resetn,
|
||||
finished => finished,
|
||||
start => start,
|
||||
write => write,
|
||||
addr => addr,
|
||||
size => size,
|
||||
axi_idle => axi_idle
|
||||
);
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_contr_0_0_arch;
|
||||
+293
@@ -0,0 +1,293 @@
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<spirit:displayName>Data Width</spirit:displayName>
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<spirit:name>Component_Name</spirit:name>
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<xilinx:definitionSource>module_ref</xilinx:definitionSource>
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<xilinx:coreRevision>1</xilinx:coreRevision>
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+9
-12
@@ -2,29 +2,27 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Jan 30 23:04:42 2025
|
||||
// Date : Fri Jan 31 00:54:03 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_ram_0_0/crc_axi_master_syn_crc_axi_ram_0_0_sim_netlist.v
|
||||
// Design : crc_axi_master_syn_crc_axi_ram_0_0
|
||||
// Command : write_verilog -force -mode funcsim -rename_top crc_axi_master_syn_HP_Port_crc_axi_ram_0_0 -prefix
|
||||
// crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_ crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_sim_netlist.v
|
||||
// Design : crc_axi_master_syn_HP_Port_crc_axi_ram_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "crc_axi_master_syn_crc_axi_ram_0_0,crc_axi_ram,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *)
|
||||
(* CHECK_LICENSE_TYPE = "crc_axi_master_syn_HP_Port_crc_axi_ram_0_0,crc_axi_ram,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *)
|
||||
(* x_core_info = "crc_axi_ram,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module crc_axi_master_syn_crc_axi_ram_0_0
|
||||
(clk,
|
||||
waddr,
|
||||
module crc_axi_master_syn_HP_Port_crc_axi_ram_0_0
|
||||
(waddr,
|
||||
wdata,
|
||||
we,
|
||||
raddr,
|
||||
rdata,
|
||||
re);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input clk;
|
||||
input [3:0]waddr;
|
||||
input [31:0]wdata;
|
||||
input we;
|
||||
@@ -39,7 +37,7 @@ module crc_axi_master_syn_crc_axi_ram_0_0
|
||||
wire [31:0]wdata;
|
||||
wire we;
|
||||
|
||||
crc_axi_master_syn_crc_axi_ram_0_0_crc_axi_ram U0
|
||||
crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_crc_axi_ram U0
|
||||
(.raddr(raddr),
|
||||
.rdata(rdata),
|
||||
.re(re),
|
||||
@@ -48,8 +46,7 @@ module crc_axi_master_syn_crc_axi_ram_0_0
|
||||
.we(we));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "crc_axi_ram" *)
|
||||
module crc_axi_master_syn_crc_axi_ram_0_0_crc_axi_ram
|
||||
module crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_crc_axi_ram
|
||||
(rdata,
|
||||
re,
|
||||
wdata,
|
||||
+6
-7
@@ -2,11 +2,11 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Jan 30 23:04:42 2025
|
||||
// Date : Fri Jan 31 00:54:03 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn/ip/crc_axi_master_syn_crc_axi_ram_0_0/crc_axi_master_syn_crc_axi_ram_0_0_stub.v
|
||||
// Design : crc_axi_master_syn_crc_axi_ram_0_0
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top crc_axi_master_syn_HP_Port_crc_axi_ram_0_0 -prefix
|
||||
// crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_ crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_stub.v
|
||||
// Design : crc_axi_master_syn_HP_Port_crc_axi_ram_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
@@ -15,10 +15,9 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "crc_axi_ram,Vivado 2023.1" *)
|
||||
module crc_axi_master_syn_crc_axi_ram_0_0(clk, waddr, wdata, we, raddr, rdata, re)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,waddr[3:0],wdata[31:0],we,raddr[3:0],rdata[31:0]" */
|
||||
module crc_axi_master_syn_HP_Port_crc_axi_ram_0_0(waddr, wdata, we, raddr, rdata, re)
|
||||
/* synthesis syn_black_box black_box_pad_pin="waddr[3:0],wdata[31:0],we,raddr[3:0],rdata[31:0]" */
|
||||
/* synthesis syn_force_seq_prim="re" */;
|
||||
input clk;
|
||||
input [3:0]waddr;
|
||||
input [31:0]wdata;
|
||||
input we;
|
||||
+5
-12
@@ -53,9 +53,8 @@ LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_syn_crc_axi_ram_0_0 IS
|
||||
ENTITY crc_axi_master_syn_HP_Port_crc_axi_ram_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
waddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : IN STD_LOGIC;
|
||||
@@ -63,18 +62,17 @@ ENTITY crc_axi_master_syn_crc_axi_ram_0_0 IS
|
||||
rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : IN STD_LOGIC
|
||||
);
|
||||
END crc_axi_master_syn_crc_axi_ram_0_0;
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_ram_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_syn_crc_axi_ram_0_0_arch OF crc_axi_master_syn_crc_axi_ram_0_0 IS
|
||||
ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_ram_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_crc_axi_ram_0_0_arch: ARCHITECTURE IS "yes";
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_ram IS
|
||||
GENERIC (
|
||||
AW : INTEGER;
|
||||
DATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
waddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : IN STD_LOGIC;
|
||||
@@ -83,10 +81,6 @@ ARCHITECTURE crc_axi_master_syn_crc_axi_ram_0_0_arch OF crc_axi_master_syn_crc_a
|
||||
re : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT crc_axi_ram;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
BEGIN
|
||||
U0 : crc_axi_ram
|
||||
GENERIC MAP (
|
||||
@@ -94,7 +88,6 @@ BEGIN
|
||||
DATA_WIDTH => 32
|
||||
)
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
waddr => waddr,
|
||||
wdata => wdata,
|
||||
we => we,
|
||||
@@ -102,4 +95,4 @@ BEGIN
|
||||
rdata => rdata,
|
||||
re => re
|
||||
);
|
||||
END crc_axi_master_syn_crc_axi_ram_0_0_arch;
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch;
|
||||
+9
-16
@@ -53,9 +53,8 @@ LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_syn_crc_axi_ram_0_0 IS
|
||||
ENTITY crc_axi_master_syn_HP_Port_crc_axi_ram_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
waddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : IN STD_LOGIC;
|
||||
@@ -63,18 +62,17 @@ ENTITY crc_axi_master_syn_crc_axi_ram_0_0 IS
|
||||
rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : IN STD_LOGIC
|
||||
);
|
||||
END crc_axi_master_syn_crc_axi_ram_0_0;
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_ram_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_syn_crc_axi_ram_0_0_arch OF crc_axi_master_syn_crc_axi_ram_0_0 IS
|
||||
ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_ram_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_crc_axi_ram_0_0_arch: ARCHITECTURE IS "yes";
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_ram IS
|
||||
GENERIC (
|
||||
AW : INTEGER;
|
||||
DATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
waddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : IN STD_LOGIC;
|
||||
@@ -84,17 +82,13 @@ ARCHITECTURE crc_axi_master_syn_crc_axi_ram_0_0_arch OF crc_axi_master_syn_crc_a
|
||||
);
|
||||
END COMPONENT crc_axi_ram;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF crc_axi_master_syn_crc_axi_ram_0_0_arch: ARCHITECTURE IS "crc_axi_ram,Vivado 2023.1";
|
||||
ATTRIBUTE X_CORE_INFO OF crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch: ARCHITECTURE IS "crc_axi_ram,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF crc_axi_master_syn_crc_axi_ram_0_0_arch : ARCHITECTURE IS "crc_axi_master_syn_crc_axi_ram_0_0,crc_axi_ram,{}";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch : ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_ram_0_0,crc_axi_ram,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF crc_axi_master_syn_crc_axi_ram_0_0_arch: ARCHITECTURE IS "crc_axi_master_syn_crc_axi_ram_0_0,crc_axi_ram,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=crc_axi_ram,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,AW=4,DATA_WIDTH=32}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch: ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_ram_0_0,crc_axi_ram,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=crc_axi_ram,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,AW=4,DATA_WIDTH=32}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF crc_axi_master_syn_crc_axi_ram_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
BEGIN
|
||||
U0 : crc_axi_ram
|
||||
GENERIC MAP (
|
||||
@@ -102,7 +96,6 @@ BEGIN
|
||||
DATA_WIDTH => 32
|
||||
)
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
waddr => waddr,
|
||||
wdata => wdata,
|
||||
we => we,
|
||||
@@ -110,4 +103,4 @@ BEGIN
|
||||
rdata => rdata,
|
||||
re => re
|
||||
);
|
||||
END crc_axi_master_syn_crc_axi_ram_0_0_arch;
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_ram_0_0_arch;
|
||||
+710
@@ -0,0 +1,710 @@
|
||||
############################################################################
|
||||
##
|
||||
## Xilinx, Inc. 2006 www.xilinx.com
|
||||
############################################################################
|
||||
## File name : ps7_constraints.xdc
|
||||
##
|
||||
## Details : Constraints file
|
||||
## FPGA family: zynq
|
||||
## FPGA: xc7z020clg400-1
|
||||
## Device Size: xc7z020
|
||||
## Package: clg400
|
||||
## Speedgrade: -1
|
||||
##
|
||||
##
|
||||
############################################################################
|
||||
############################################################################
|
||||
############################################################################
|
||||
# Clock constraints #
|
||||
############################################################################
|
||||
create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
|
||||
set_input_jitter clk_fpga_0 0.3
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_1 -period "8" [get_pins "PS7_i/FCLKCLK[1]"]
|
||||
set_input_jitter clk_fpga_1 0.24
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_2 -period "5" [get_pins "PS7_i/FCLKCLK[2]"]
|
||||
set_input_jitter clk_fpga_2 0.15
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_3 -period "14.999" [get_pins "PS7_i/FCLKCLK[3]"]
|
||||
set_input_jitter clk_fpga_3 0.44997
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
|
||||
|
||||
############################################################################
|
||||
# I/O STANDARDS and Location Constraints #
|
||||
############################################################################
|
||||
|
||||
# Enet 0 / mdio / MIO[53]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
|
||||
set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
|
||||
set_property slew "slow" [get_ports "MIO[53]"]
|
||||
set_property drive "8" [get_ports "MIO[53]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[53]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
|
||||
# Enet 0 / mdc / MIO[52]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
|
||||
set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
|
||||
set_property slew "slow" [get_ports "MIO[52]"]
|
||||
set_property drive "8" [get_ports "MIO[52]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[52]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
|
||||
# GPIO / gpio[51] / MIO[51]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
|
||||
set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
|
||||
set_property slew "slow" [get_ports "MIO[51]"]
|
||||
set_property drive "8" [get_ports "MIO[51]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[51]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
|
||||
# GPIO / gpio[50] / MIO[50]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
|
||||
set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
|
||||
set_property slew "slow" [get_ports "MIO[50]"]
|
||||
set_property drive "8" [get_ports "MIO[50]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[50]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
|
||||
# UART 1 / rx / MIO[49]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
|
||||
set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
|
||||
set_property slew "slow" [get_ports "MIO[49]"]
|
||||
set_property drive "8" [get_ports "MIO[49]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[49]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
|
||||
# UART 1 / tx / MIO[48]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
|
||||
set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
|
||||
set_property slew "slow" [get_ports "MIO[48]"]
|
||||
set_property drive "8" [get_ports "MIO[48]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[48]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
|
||||
# SD 0 / cd / MIO[47]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
|
||||
set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
|
||||
set_property slew "slow" [get_ports "MIO[47]"]
|
||||
set_property drive "8" [get_ports "MIO[47]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[47]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
|
||||
# USB Reset / reset / MIO[46]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
|
||||
set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
|
||||
set_property slew "slow" [get_ports "MIO[46]"]
|
||||
set_property drive "8" [get_ports "MIO[46]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[46]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[46]"]
|
||||
# SD 0 / data[3] / MIO[45]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
|
||||
set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
|
||||
set_property slew "slow" [get_ports "MIO[45]"]
|
||||
set_property drive "8" [get_ports "MIO[45]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[45]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
|
||||
# SD 0 / data[2] / MIO[44]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
|
||||
set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
|
||||
set_property slew "slow" [get_ports "MIO[44]"]
|
||||
set_property drive "8" [get_ports "MIO[44]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[44]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
|
||||
# SD 0 / data[1] / MIO[43]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
|
||||
set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
|
||||
set_property slew "slow" [get_ports "MIO[43]"]
|
||||
set_property drive "8" [get_ports "MIO[43]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[43]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
|
||||
# SD 0 / data[0] / MIO[42]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
|
||||
set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
|
||||
set_property slew "slow" [get_ports "MIO[42]"]
|
||||
set_property drive "8" [get_ports "MIO[42]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[42]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
|
||||
# SD 0 / cmd / MIO[41]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
|
||||
set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
|
||||
set_property slew "slow" [get_ports "MIO[41]"]
|
||||
set_property drive "8" [get_ports "MIO[41]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[41]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
|
||||
# SD 0 / clk / MIO[40]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
|
||||
set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
|
||||
set_property slew "slow" [get_ports "MIO[40]"]
|
||||
set_property drive "8" [get_ports "MIO[40]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[40]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
|
||||
# USB 0 / data[7] / MIO[39]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
|
||||
set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
|
||||
set_property slew "fast" [get_ports "MIO[39]"]
|
||||
set_property drive "8" [get_ports "MIO[39]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[39]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
|
||||
# USB 0 / data[6] / MIO[38]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
|
||||
set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
|
||||
set_property slew "fast" [get_ports "MIO[38]"]
|
||||
set_property drive "8" [get_ports "MIO[38]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[38]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
|
||||
# USB 0 / data[5] / MIO[37]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
|
||||
set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
|
||||
set_property slew "fast" [get_ports "MIO[37]"]
|
||||
set_property drive "8" [get_ports "MIO[37]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[37]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
|
||||
# USB 0 / clk / MIO[36]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
|
||||
set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
|
||||
set_property slew "fast" [get_ports "MIO[36]"]
|
||||
set_property drive "8" [get_ports "MIO[36]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[36]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
|
||||
# USB 0 / data[3] / MIO[35]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
|
||||
set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
|
||||
set_property slew "fast" [get_ports "MIO[35]"]
|
||||
set_property drive "8" [get_ports "MIO[35]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[35]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
|
||||
# USB 0 / data[2] / MIO[34]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
|
||||
set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
|
||||
set_property slew "fast" [get_ports "MIO[34]"]
|
||||
set_property drive "8" [get_ports "MIO[34]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[34]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
|
||||
# USB 0 / data[1] / MIO[33]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
|
||||
set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
|
||||
set_property slew "fast" [get_ports "MIO[33]"]
|
||||
set_property drive "8" [get_ports "MIO[33]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[33]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
|
||||
# USB 0 / data[0] / MIO[32]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
|
||||
set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
|
||||
set_property slew "fast" [get_ports "MIO[32]"]
|
||||
set_property drive "8" [get_ports "MIO[32]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[32]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
|
||||
# USB 0 / nxt / MIO[31]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
|
||||
set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
|
||||
set_property slew "fast" [get_ports "MIO[31]"]
|
||||
set_property drive "8" [get_ports "MIO[31]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[31]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
|
||||
# USB 0 / stp / MIO[30]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
|
||||
set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
|
||||
set_property slew "fast" [get_ports "MIO[30]"]
|
||||
set_property drive "8" [get_ports "MIO[30]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[30]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
|
||||
# USB 0 / dir / MIO[29]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
|
||||
set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
|
||||
set_property slew "fast" [get_ports "MIO[29]"]
|
||||
set_property drive "8" [get_ports "MIO[29]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[29]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
|
||||
# USB 0 / data[4] / MIO[28]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
|
||||
set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
|
||||
set_property slew "fast" [get_ports "MIO[28]"]
|
||||
set_property drive "8" [get_ports "MIO[28]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
|
||||
# Enet 0 / rx_ctl / MIO[27]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
|
||||
set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
|
||||
set_property slew "fast" [get_ports "MIO[27]"]
|
||||
set_property drive "8" [get_ports "MIO[27]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[27]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
|
||||
# Enet 0 / rxd[3] / MIO[26]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
|
||||
set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
|
||||
set_property slew "fast" [get_ports "MIO[26]"]
|
||||
set_property drive "8" [get_ports "MIO[26]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[26]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
|
||||
# Enet 0 / rxd[2] / MIO[25]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
|
||||
set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
|
||||
set_property slew "fast" [get_ports "MIO[25]"]
|
||||
set_property drive "8" [get_ports "MIO[25]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[25]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
|
||||
# Enet 0 / rxd[1] / MIO[24]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
|
||||
set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
|
||||
set_property slew "fast" [get_ports "MIO[24]"]
|
||||
set_property drive "8" [get_ports "MIO[24]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[24]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
|
||||
# Enet 0 / rxd[0] / MIO[23]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
|
||||
set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
|
||||
set_property slew "fast" [get_ports "MIO[23]"]
|
||||
set_property drive "8" [get_ports "MIO[23]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[23]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
|
||||
# Enet 0 / rx_clk / MIO[22]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
|
||||
set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
|
||||
set_property slew "fast" [get_ports "MIO[22]"]
|
||||
set_property drive "8" [get_ports "MIO[22]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[22]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
|
||||
# Enet 0 / tx_ctl / MIO[21]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
|
||||
set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
|
||||
set_property slew "fast" [get_ports "MIO[21]"]
|
||||
set_property drive "8" [get_ports "MIO[21]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[21]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
|
||||
# Enet 0 / txd[3] / MIO[20]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
|
||||
set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
|
||||
set_property slew "fast" [get_ports "MIO[20]"]
|
||||
set_property drive "8" [get_ports "MIO[20]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[20]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
|
||||
# Enet 0 / txd[2] / MIO[19]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
|
||||
set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
|
||||
set_property slew "fast" [get_ports "MIO[19]"]
|
||||
set_property drive "8" [get_ports "MIO[19]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[19]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
|
||||
# Enet 0 / txd[1] / MIO[18]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
|
||||
set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
|
||||
set_property slew "fast" [get_ports "MIO[18]"]
|
||||
set_property drive "8" [get_ports "MIO[18]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[18]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
|
||||
# Enet 0 / txd[0] / MIO[17]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
|
||||
set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
|
||||
set_property slew "fast" [get_ports "MIO[17]"]
|
||||
set_property drive "8" [get_ports "MIO[17]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[17]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
|
||||
# Enet 0 / tx_clk / MIO[16]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
|
||||
set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
|
||||
set_property slew "fast" [get_ports "MIO[16]"]
|
||||
set_property drive "8" [get_ports "MIO[16]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[16]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
|
||||
# I2C 0 / sda / MIO[15]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
|
||||
set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
|
||||
set_property slew "slow" [get_ports "MIO[15]"]
|
||||
set_property drive "8" [get_ports "MIO[15]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
|
||||
# I2C 0 / scl / MIO[14]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
|
||||
set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
|
||||
set_property slew "slow" [get_ports "MIO[14]"]
|
||||
set_property drive "8" [get_ports "MIO[14]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
|
||||
# I2C 1 / sda / MIO[13]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
|
||||
set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
|
||||
set_property slew "slow" [get_ports "MIO[13]"]
|
||||
set_property drive "8" [get_ports "MIO[13]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
|
||||
# I2C 1 / scl / MIO[12]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
|
||||
set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
|
||||
set_property slew "slow" [get_ports "MIO[12]"]
|
||||
set_property drive "8" [get_ports "MIO[12]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
|
||||
# UART 0 / tx / MIO[11]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
|
||||
set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
|
||||
set_property slew "slow" [get_ports "MIO[11]"]
|
||||
set_property drive "8" [get_ports "MIO[11]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[11]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[11]"]
|
||||
# UART 0 / rx / MIO[10]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
|
||||
set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
|
||||
set_property slew "slow" [get_ports "MIO[10]"]
|
||||
set_property drive "8" [get_ports "MIO[10]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[10]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[10]"]
|
||||
# GPIO / gpio[9] / MIO[9]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
|
||||
set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
|
||||
set_property slew "slow" [get_ports "MIO[9]"]
|
||||
set_property drive "8" [get_ports "MIO[9]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
|
||||
# Quad SPI Flash / qspi_fbclk / MIO[8]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
|
||||
set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
|
||||
set_property slew "slow" [get_ports "MIO[8]"]
|
||||
set_property drive "8" [get_ports "MIO[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
|
||||
# GPIO / gpio[7] / MIO[7]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
|
||||
set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
|
||||
set_property slew "slow" [get_ports "MIO[7]"]
|
||||
set_property drive "8" [get_ports "MIO[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
|
||||
# Quad SPI Flash / qspi0_sclk / MIO[6]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
|
||||
set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
|
||||
set_property slew "slow" [get_ports "MIO[6]"]
|
||||
set_property drive "8" [get_ports "MIO[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
|
||||
# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
|
||||
set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
|
||||
set_property slew "slow" [get_ports "MIO[5]"]
|
||||
set_property drive "8" [get_ports "MIO[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
|
||||
# Quad SPI Flash / qspi0_io[2] / MIO[4]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
|
||||
set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
|
||||
set_property slew "slow" [get_ports "MIO[4]"]
|
||||
set_property drive "8" [get_ports "MIO[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
|
||||
# Quad SPI Flash / qspi0_io[1] / MIO[3]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
|
||||
set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
|
||||
set_property slew "slow" [get_ports "MIO[3]"]
|
||||
set_property drive "8" [get_ports "MIO[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
|
||||
# Quad SPI Flash / qspi0_io[0] / MIO[2]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
|
||||
set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
|
||||
set_property slew "slow" [get_ports "MIO[2]"]
|
||||
set_property drive "8" [get_ports "MIO[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
|
||||
# Quad SPI Flash / qspi0_ss_b / MIO[1]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
|
||||
set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
|
||||
set_property slew "slow" [get_ports "MIO[1]"]
|
||||
set_property drive "8" [get_ports "MIO[1]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
|
||||
# GPIO / gpio[0] / MIO[0]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
|
||||
set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
|
||||
set_property slew "slow" [get_ports "MIO[0]"]
|
||||
set_property drive "8" [get_ports "MIO[0]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRP"]
|
||||
set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRP"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRN"]
|
||||
set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRN"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_WEB"]
|
||||
set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
|
||||
set_property slew "SLOW" [get_ports "DDR_WEB"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_RAS_n"]
|
||||
set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_RAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_ODT"]
|
||||
set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
|
||||
set_property slew "SLOW" [get_ports "DDR_ODT"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_DRSTB"]
|
||||
set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
|
||||
set_property slew "FAST" [get_ports "DDR_DRSTB"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[3]"]
|
||||
set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[2]"]
|
||||
set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[1]"]
|
||||
set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[0]"]
|
||||
set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[9]"]
|
||||
set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[8]"]
|
||||
set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[7]"]
|
||||
set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[6]"]
|
||||
set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[5]"]
|
||||
set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[4]"]
|
||||
set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[3]"]
|
||||
set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[31]"]
|
||||
set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[30]"]
|
||||
set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[2]"]
|
||||
set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[29]"]
|
||||
set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[28]"]
|
||||
set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[27]"]
|
||||
set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[26]"]
|
||||
set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[25]"]
|
||||
set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[24]"]
|
||||
set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[23]"]
|
||||
set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[22]"]
|
||||
set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[21]"]
|
||||
set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[20]"]
|
||||
set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[1]"]
|
||||
set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[19]"]
|
||||
set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[18]"]
|
||||
set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[17]"]
|
||||
set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[16]"]
|
||||
set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[15]"]
|
||||
set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[14]"]
|
||||
set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[13]"]
|
||||
set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[12]"]
|
||||
set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[11]"]
|
||||
set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[10]"]
|
||||
set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[0]"]
|
||||
set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[3]"]
|
||||
set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[2]"]
|
||||
set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[1]"]
|
||||
set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[0]"]
|
||||
set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_CS_n"]
|
||||
set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_CKE"]
|
||||
set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CKE"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
|
||||
set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk"]
|
||||
set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
|
||||
set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk_n"]
|
||||
set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk_n"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_CAS_n"]
|
||||
set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[9]"]
|
||||
set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[8]"]
|
||||
set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[7]"]
|
||||
set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[6]"]
|
||||
set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[5]"]
|
||||
set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[4]"]
|
||||
set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[3]"]
|
||||
set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[2]"]
|
||||
set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[1]"]
|
||||
set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[14]"]
|
||||
set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[13]"]
|
||||
set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[12]"]
|
||||
set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[11]"]
|
||||
set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[10]"]
|
||||
set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[0]"]
|
||||
set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
|
||||
set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
|
||||
set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
|
||||
set_property slew "fast" [get_ports "PS_PORB"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
|
||||
set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
|
||||
set_property slew "fast" [get_ports "PS_SRSTB"]
|
||||
set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
|
||||
set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
|
||||
set_property slew "fast" [get_ports "PS_CLK"]
|
||||
|
||||
+41293
File diff suppressed because it is too large
Load Diff
+6593
File diff suppressed because it is too large
Load Diff
+119
@@ -0,0 +1,119 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Thu Jan 30 23:53:57 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_processing_system7_0_0/crc_axi_master_syn_HP_Port_processing_system7_0_0_stub.v
|
||||
// Design : crc_axi_master_syn_HP_Port_processing_system7_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2023.1" *)
|
||||
module crc_axi_master_syn_HP_Port_processing_system7_0_0(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
|
||||
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
|
||||
S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST,
|
||||
S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID,
|
||||
S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT,
|
||||
S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID,
|
||||
S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST,
|
||||
S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK,
|
||||
S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE,
|
||||
S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR,
|
||||
S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN,
|
||||
S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA,
|
||||
S_AXI_HP0_WSTRB, IRQ_F2P, FCLK_CLK0, FCLK_CLK1, FCLK_CLK2, FCLK_CLK3, FCLK_RESET0_N, MIO,
|
||||
DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB,
|
||||
DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK,
|
||||
PS_PORB)
|
||||
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[31:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[31:0],S_AXI_HP0_WSTRB[3:0],IRQ_F2P[0:0],FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */
|
||||
/* synthesis syn_force_seq_prim="S_AXI_HP0_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK0" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK1" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK2" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK3" */;
|
||||
input SDIO0_WP;
|
||||
output TTC0_WAVE0_OUT;
|
||||
output TTC0_WAVE1_OUT;
|
||||
output TTC0_WAVE2_OUT;
|
||||
output [1:0]USB0_PORT_INDCTL;
|
||||
output USB0_VBUS_PWRSELECT;
|
||||
input USB0_VBUS_PWRFAULT;
|
||||
output S_AXI_HP0_ARREADY;
|
||||
output S_AXI_HP0_AWREADY;
|
||||
output S_AXI_HP0_BVALID;
|
||||
output S_AXI_HP0_RLAST;
|
||||
output S_AXI_HP0_RVALID;
|
||||
output S_AXI_HP0_WREADY;
|
||||
output [1:0]S_AXI_HP0_BRESP;
|
||||
output [1:0]S_AXI_HP0_RRESP;
|
||||
output [5:0]S_AXI_HP0_BID;
|
||||
output [5:0]S_AXI_HP0_RID;
|
||||
output [31:0]S_AXI_HP0_RDATA;
|
||||
output [7:0]S_AXI_HP0_RCOUNT;
|
||||
output [7:0]S_AXI_HP0_WCOUNT;
|
||||
output [2:0]S_AXI_HP0_RACOUNT;
|
||||
output [5:0]S_AXI_HP0_WACOUNT;
|
||||
input S_AXI_HP0_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input S_AXI_HP0_ARVALID;
|
||||
input S_AXI_HP0_AWVALID;
|
||||
input S_AXI_HP0_BREADY;
|
||||
input S_AXI_HP0_RDISSUECAP1_EN;
|
||||
input S_AXI_HP0_RREADY;
|
||||
input S_AXI_HP0_WLAST;
|
||||
input S_AXI_HP0_WRISSUECAP1_EN;
|
||||
input S_AXI_HP0_WVALID;
|
||||
input [1:0]S_AXI_HP0_ARBURST;
|
||||
input [1:0]S_AXI_HP0_ARLOCK;
|
||||
input [2:0]S_AXI_HP0_ARSIZE;
|
||||
input [1:0]S_AXI_HP0_AWBURST;
|
||||
input [1:0]S_AXI_HP0_AWLOCK;
|
||||
input [2:0]S_AXI_HP0_AWSIZE;
|
||||
input [2:0]S_AXI_HP0_ARPROT;
|
||||
input [2:0]S_AXI_HP0_AWPROT;
|
||||
input [31:0]S_AXI_HP0_ARADDR;
|
||||
input [31:0]S_AXI_HP0_AWADDR;
|
||||
input [3:0]S_AXI_HP0_ARCACHE;
|
||||
input [3:0]S_AXI_HP0_ARLEN;
|
||||
input [3:0]S_AXI_HP0_ARQOS;
|
||||
input [3:0]S_AXI_HP0_AWCACHE;
|
||||
input [3:0]S_AXI_HP0_AWLEN;
|
||||
input [3:0]S_AXI_HP0_AWQOS;
|
||||
input [5:0]S_AXI_HP0_ARID;
|
||||
input [5:0]S_AXI_HP0_AWID;
|
||||
input [5:0]S_AXI_HP0_WID;
|
||||
input [31:0]S_AXI_HP0_WDATA;
|
||||
input [3:0]S_AXI_HP0_WSTRB;
|
||||
input [0:0]IRQ_F2P;
|
||||
output FCLK_CLK0 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_CLK1 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_CLK2 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_CLK3 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_RESET0_N;
|
||||
inout [53:0]MIO;
|
||||
inout DDR_CAS_n;
|
||||
inout DDR_CKE;
|
||||
inout DDR_Clk_n;
|
||||
inout DDR_Clk;
|
||||
inout DDR_CS_n;
|
||||
inout DDR_DRSTB;
|
||||
inout DDR_ODT;
|
||||
inout DDR_RAS_n;
|
||||
inout DDR_WEB;
|
||||
inout [2:0]DDR_BankAddr;
|
||||
inout [14:0]DDR_Addr;
|
||||
inout DDR_VRN;
|
||||
inout DDR_VRP;
|
||||
inout [3:0]DDR_DM;
|
||||
inout [31:0]DDR_DQ;
|
||||
inout [3:0]DDR_DQS_n;
|
||||
inout [3:0]DDR_DQS;
|
||||
inout PS_SRSTB;
|
||||
inout PS_CLK;
|
||||
inout PS_PORB;
|
||||
endmodule
|
||||
+3934
File diff suppressed because it is too large
Load Diff
+12628
File diff suppressed because it is too large
Load Diff
+117
@@ -0,0 +1,117 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 125000000
|
||||
#define FPGA2_FREQ 200000000
|
||||
#define FPGA3_FREQ 66666672
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+859
@@ -0,0 +1,859 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF8000180 0x03F03F30 0x00200400
|
||||
mask_write 0XF8000190 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100F00
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00026C00
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00028800
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF8006158 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF800615C 0x000FFFFF 0x0000007C
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000073
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F0
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F7
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000BC
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000B3
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001640
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00001304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00001304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00001304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F0037
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||
mask_write 0XE0000034 0x000000FF 0x00000006
|
||||
mask_write 0XE0000018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0000000 0x000001FF 0x00000017
|
||||
mask_write 0XE0000004 0x000003FF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A244 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
mask_write 0XE000A248 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8008000 0x00000001 0x00000001
|
||||
mask_write 0XF8008014 0x00000001 0x00000001
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF8000180 0x03F03F30 0x00200400
|
||||
mask_write 0XF8000190 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100F00
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00026C00
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00028800
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF8006158 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF800615C 0x000FFFFF 0x0000007C
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000073
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F0
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F7
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000BC
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000B3
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001640
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00001304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00001304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00001304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F0037
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE0000034 0x000000FF 0x00000006
|
||||
mask_write 0XE0000018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0000000 0x000001FF 0x00000017
|
||||
mask_write 0XE0000004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A244 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
mask_write 0XE000A248 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8008000 0x00000001 0x00000001
|
||||
mask_write 0XF8008014 0x00000001 0x00000001
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF8000180 0x03F03F30 0x00200400
|
||||
mask_write 0XF8000190 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100F00
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00026C00
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00028800
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF8006158 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF800615C 0x000FFFFF 0x0000007C
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000073
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F0
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F7
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000BC
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000B3
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001640
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00001304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00001304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00001304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F0037
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE0000034 0x000000FF 0x00000006
|
||||
mask_write 0XE0000018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0000000 0x000001FF 0x00000017
|
||||
mask_write 0XE0000004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A244 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
mask_write 0XE000A248 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8008000 0x00000001 0x00000001
|
||||
mask_write 0XF8008014 0x00000001 0x00000001
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 667000000
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
+12641
File diff suppressed because it is too large
Load Diff
+131
@@ -0,0 +1,131 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 <Xilinx Inc.>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init_gpl.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 125000000
|
||||
#define FPGA2_FREQ 200000000
|
||||
#define FPGA3_FREQ 66666672
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+643
@@ -0,0 +1,643 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
|
||||
<designInfo version="1.0" >
|
||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
||||
<PARAMETERS >
|
||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="667" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
|
||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
|
||||
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
|
||||
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
|
||||
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
|
||||
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="4" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="125" />
|
||||
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="65" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
|
||||
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="MIO 14 .. 15" />
|
||||
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="MIO 12 .. 13" />
|
||||
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
|
||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 47" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="20" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="32" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 10 .. 11" />
|
||||
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.221" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.222" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.217" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.244" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="22.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="105.056" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="27.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="66.904" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="22.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="89.1715" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="29.4" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="113.63" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="-0.050" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="-0.044" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="-0.035" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="-0.100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="22.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="98.503" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="27.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="68.5855" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="22.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="90.295" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="29.4" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="103.977" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3 (Low Voltage)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="MIO 46" />
|
||||
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
|
||||
</PARAMETERS>
|
||||
<BUSINTERFACES >
|
||||
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="1" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
</BUSINTERFACES>
|
||||
<CLOCKOUTS >
|
||||
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="100.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="125.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="200.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="66.666672" />
|
||||
</CLOCKOUTS>
|
||||
</MODULE>
|
||||
</designInfo>
|
||||
+665
@@ -0,0 +1,665 @@
|
||||
#ifndef IP_CRC_AXI_MASTER_SYN_HP_PORT_PROCESSING_SYSTEM7_0_0_H_
|
||||
#define IP_CRC_AXI_MASTER_SYN_HP_PORT_PROCESSING_SYSTEM7_0_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "crc_axi_master_syn_HP_Port_processing_system7_0_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport crc_axi_master_syn_HP_Port_processing_system7_0_0 : public crc_axi_master_syn_HP_Port_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_syn_HP_Port_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_syn_HP_Port_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport crc_axi_master_syn_HP_Port_processing_system7_0_0 : public crc_axi_master_syn_HP_Port_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_syn_HP_Port_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_syn_HP_Port_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_inout< bool > DDR_CAS_n;
|
||||
sc_core::sc_inout< bool > DDR_CKE;
|
||||
sc_core::sc_inout< bool > DDR_Clk_n;
|
||||
sc_core::sc_inout< bool > DDR_Clk;
|
||||
sc_core::sc_inout< bool > DDR_CS_n;
|
||||
sc_core::sc_inout< bool > DDR_DRSTB;
|
||||
sc_core::sc_inout< bool > DDR_ODT;
|
||||
sc_core::sc_inout< bool > DDR_RAS_n;
|
||||
sc_core::sc_inout< bool > DDR_WEB;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_inout< bool > DDR_VRN;
|
||||
sc_core::sc_inout< bool > DDR_VRP;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_inout< bool > PS_SRSTB;
|
||||
sc_core::sc_inout< bool > PS_CLK;
|
||||
sc_core::sc_inout< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport crc_axi_master_syn_HP_Port_processing_system7_0_0 : public crc_axi_master_syn_HP_Port_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_syn_HP_Port_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_syn_HP_Port_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport crc_axi_master_syn_HP_Port_processing_system7_0_0 : public crc_axi_master_syn_HP_Port_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_syn_HP_Port_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_syn_HP_Port_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport crc_axi_master_syn_HP_Port_processing_system7_0_0 : public crc_axi_master_syn_HP_Port_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_syn_HP_Port_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_syn_HP_Port_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_CRC_AXI_MASTER_SYN_HP_PORT_PROCESSING_SYSTEM7_0_0_H_
|
||||
+1198
File diff suppressed because it is too large
Load Diff
+612
@@ -0,0 +1,612 @@
|
||||
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module crc_axi_master_syn_HP_Port_processing_system7_0_0 (
|
||||
SDIO0_WP,
|
||||
TTC0_WAVE0_OUT,
|
||||
TTC0_WAVE1_OUT,
|
||||
TTC0_WAVE2_OUT,
|
||||
USB0_PORT_INDCTL,
|
||||
USB0_VBUS_PWRSELECT,
|
||||
USB0_VBUS_PWRFAULT,
|
||||
S_AXI_HP0_ARREADY,
|
||||
S_AXI_HP0_AWREADY,
|
||||
S_AXI_HP0_BVALID,
|
||||
S_AXI_HP0_RLAST,
|
||||
S_AXI_HP0_RVALID,
|
||||
S_AXI_HP0_WREADY,
|
||||
S_AXI_HP0_BRESP,
|
||||
S_AXI_HP0_RRESP,
|
||||
S_AXI_HP0_BID,
|
||||
S_AXI_HP0_RID,
|
||||
S_AXI_HP0_RDATA,
|
||||
S_AXI_HP0_RCOUNT,
|
||||
S_AXI_HP0_WCOUNT,
|
||||
S_AXI_HP0_RACOUNT,
|
||||
S_AXI_HP0_WACOUNT,
|
||||
S_AXI_HP0_ACLK,
|
||||
S_AXI_HP0_ARVALID,
|
||||
S_AXI_HP0_AWVALID,
|
||||
S_AXI_HP0_BREADY,
|
||||
S_AXI_HP0_RDISSUECAP1_EN,
|
||||
S_AXI_HP0_RREADY,
|
||||
S_AXI_HP0_WLAST,
|
||||
S_AXI_HP0_WRISSUECAP1_EN,
|
||||
S_AXI_HP0_WVALID,
|
||||
S_AXI_HP0_ARBURST,
|
||||
S_AXI_HP0_ARLOCK,
|
||||
S_AXI_HP0_ARSIZE,
|
||||
S_AXI_HP0_AWBURST,
|
||||
S_AXI_HP0_AWLOCK,
|
||||
S_AXI_HP0_AWSIZE,
|
||||
S_AXI_HP0_ARPROT,
|
||||
S_AXI_HP0_AWPROT,
|
||||
S_AXI_HP0_ARADDR,
|
||||
S_AXI_HP0_AWADDR,
|
||||
S_AXI_HP0_ARCACHE,
|
||||
S_AXI_HP0_ARLEN,
|
||||
S_AXI_HP0_ARQOS,
|
||||
S_AXI_HP0_AWCACHE,
|
||||
S_AXI_HP0_AWLEN,
|
||||
S_AXI_HP0_AWQOS,
|
||||
S_AXI_HP0_ARID,
|
||||
S_AXI_HP0_AWID,
|
||||
S_AXI_HP0_WID,
|
||||
S_AXI_HP0_WDATA,
|
||||
S_AXI_HP0_WSTRB,
|
||||
IRQ_F2P,
|
||||
FCLK_CLK0,
|
||||
FCLK_CLK1,
|
||||
FCLK_CLK2,
|
||||
FCLK_CLK3,
|
||||
FCLK_RESET0_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
input SDIO0_WP;
|
||||
output TTC0_WAVE0_OUT;
|
||||
output TTC0_WAVE1_OUT;
|
||||
output TTC0_WAVE2_OUT;
|
||||
output [1 : 0] USB0_PORT_INDCTL;
|
||||
output USB0_VBUS_PWRSELECT;
|
||||
input USB0_VBUS_PWRFAULT;
|
||||
output S_AXI_HP0_ARREADY;
|
||||
output S_AXI_HP0_AWREADY;
|
||||
output S_AXI_HP0_BVALID;
|
||||
output S_AXI_HP0_RLAST;
|
||||
output S_AXI_HP0_RVALID;
|
||||
output S_AXI_HP0_WREADY;
|
||||
output [1 : 0] S_AXI_HP0_BRESP;
|
||||
output [1 : 0] S_AXI_HP0_RRESP;
|
||||
output [5 : 0] S_AXI_HP0_BID;
|
||||
output [5 : 0] S_AXI_HP0_RID;
|
||||
output [31 : 0] S_AXI_HP0_RDATA;
|
||||
output [7 : 0] S_AXI_HP0_RCOUNT;
|
||||
output [7 : 0] S_AXI_HP0_WCOUNT;
|
||||
output [2 : 0] S_AXI_HP0_RACOUNT;
|
||||
output [5 : 0] S_AXI_HP0_WACOUNT;
|
||||
input S_AXI_HP0_ACLK;
|
||||
input S_AXI_HP0_ARVALID;
|
||||
input S_AXI_HP0_AWVALID;
|
||||
input S_AXI_HP0_BREADY;
|
||||
input S_AXI_HP0_RDISSUECAP1_EN;
|
||||
input S_AXI_HP0_RREADY;
|
||||
input S_AXI_HP0_WLAST;
|
||||
input S_AXI_HP0_WRISSUECAP1_EN;
|
||||
input S_AXI_HP0_WVALID;
|
||||
input [1 : 0] S_AXI_HP0_ARBURST;
|
||||
input [1 : 0] S_AXI_HP0_ARLOCK;
|
||||
input [2 : 0] S_AXI_HP0_ARSIZE;
|
||||
input [1 : 0] S_AXI_HP0_AWBURST;
|
||||
input [1 : 0] S_AXI_HP0_AWLOCK;
|
||||
input [2 : 0] S_AXI_HP0_AWSIZE;
|
||||
input [2 : 0] S_AXI_HP0_ARPROT;
|
||||
input [2 : 0] S_AXI_HP0_AWPROT;
|
||||
input [31 : 0] S_AXI_HP0_ARADDR;
|
||||
input [31 : 0] S_AXI_HP0_AWADDR;
|
||||
input [3 : 0] S_AXI_HP0_ARCACHE;
|
||||
input [3 : 0] S_AXI_HP0_ARLEN;
|
||||
input [3 : 0] S_AXI_HP0_ARQOS;
|
||||
input [3 : 0] S_AXI_HP0_AWCACHE;
|
||||
input [3 : 0] S_AXI_HP0_AWLEN;
|
||||
input [3 : 0] S_AXI_HP0_AWQOS;
|
||||
input [5 : 0] S_AXI_HP0_ARID;
|
||||
input [5 : 0] S_AXI_HP0_AWID;
|
||||
input [5 : 0] S_AXI_HP0_WID;
|
||||
input [31 : 0] S_AXI_HP0_WDATA;
|
||||
input [3 : 0] S_AXI_HP0_WSTRB;
|
||||
input [0 : 0] IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_CLK1;
|
||||
output FCLK_CLK2;
|
||||
output FCLK_CLK3;
|
||||
output FCLK_RESET0_N;
|
||||
input [53 : 0] MIO;
|
||||
input DDR_CAS_n;
|
||||
input DDR_CKE;
|
||||
input DDR_Clk_n;
|
||||
input DDR_Clk;
|
||||
input DDR_CS_n;
|
||||
input DDR_DRSTB;
|
||||
input DDR_ODT;
|
||||
input DDR_RAS_n;
|
||||
input DDR_WEB;
|
||||
input [2 : 0] DDR_BankAddr;
|
||||
input [14 : 0] DDR_Addr;
|
||||
input DDR_VRN;
|
||||
input DDR_VRP;
|
||||
input [3 : 0] DDR_DM;
|
||||
input [31 : 0] DDR_DQ;
|
||||
input [3 : 0] DDR_DQS_n;
|
||||
input [3 : 0] DDR_DQS;
|
||||
input PS_SRSTB;
|
||||
input PS_CLK;
|
||||
input PS_PORB;
|
||||
|
||||
processing_system7_vip_v1_0_16 #(
|
||||
.C_USE_M_AXI_GP0(0),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_ACP(0),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(1),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(32),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_HIGH_OCM_EN(0),
|
||||
.C_FCLK_CLK0_FREQ(100.0),
|
||||
.C_FCLK_CLK1_FREQ(125.0),
|
||||
.C_FCLK_CLK2_FREQ(200.0),
|
||||
.C_FCLK_CLK3_FREQ(66.666672),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
|
||||
) inst (
|
||||
.M_AXI_GP0_ARVALID(),
|
||||
.M_AXI_GP0_AWVALID(),
|
||||
.M_AXI_GP0_BREADY(),
|
||||
.M_AXI_GP0_RREADY(),
|
||||
.M_AXI_GP0_WLAST(),
|
||||
.M_AXI_GP0_WVALID(),
|
||||
.M_AXI_GP0_ARID(),
|
||||
.M_AXI_GP0_AWID(),
|
||||
.M_AXI_GP0_WID(),
|
||||
.M_AXI_GP0_ARBURST(),
|
||||
.M_AXI_GP0_ARLOCK(),
|
||||
.M_AXI_GP0_ARSIZE(),
|
||||
.M_AXI_GP0_AWBURST(),
|
||||
.M_AXI_GP0_AWLOCK(),
|
||||
.M_AXI_GP0_AWSIZE(),
|
||||
.M_AXI_GP0_ARPROT(),
|
||||
.M_AXI_GP0_AWPROT(),
|
||||
.M_AXI_GP0_ARADDR(),
|
||||
.M_AXI_GP0_AWADDR(),
|
||||
.M_AXI_GP0_WDATA(),
|
||||
.M_AXI_GP0_ARCACHE(),
|
||||
.M_AXI_GP0_ARLEN(),
|
||||
.M_AXI_GP0_ARQOS(),
|
||||
.M_AXI_GP0_AWCACHE(),
|
||||
.M_AXI_GP0_AWLEN(),
|
||||
.M_AXI_GP0_AWQOS(),
|
||||
.M_AXI_GP0_WSTRB(),
|
||||
.M_AXI_GP0_ACLK(1'B0),
|
||||
.M_AXI_GP0_ARREADY(1'B0),
|
||||
.M_AXI_GP0_AWREADY(1'B0),
|
||||
.M_AXI_GP0_BVALID(1'B0),
|
||||
.M_AXI_GP0_RLAST(1'B0),
|
||||
.M_AXI_GP0_RVALID(1'B0),
|
||||
.M_AXI_GP0_WREADY(1'B0),
|
||||
.M_AXI_GP0_BID(12'B0),
|
||||
.M_AXI_GP0_RID(12'B0),
|
||||
.M_AXI_GP0_BRESP(2'B0),
|
||||
.M_AXI_GP0_RRESP(2'B0),
|
||||
.M_AXI_GP0_RDATA(32'B0),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(),
|
||||
.S_AXI_ACP_AWREADY(),
|
||||
.S_AXI_ACP_BVALID(),
|
||||
.S_AXI_ACP_RLAST(),
|
||||
.S_AXI_ACP_RVALID(),
|
||||
.S_AXI_ACP_WREADY(),
|
||||
.S_AXI_ACP_BRESP(),
|
||||
.S_AXI_ACP_RRESP(),
|
||||
.S_AXI_ACP_BID(),
|
||||
.S_AXI_ACP_RID(),
|
||||
.S_AXI_ACP_RDATA(),
|
||||
.S_AXI_ACP_ACLK(1'B0),
|
||||
.S_AXI_ACP_ARVALID(1'B0),
|
||||
.S_AXI_ACP_AWVALID(1'B0),
|
||||
.S_AXI_ACP_BREADY(1'B0),
|
||||
.S_AXI_ACP_RREADY(1'B0),
|
||||
.S_AXI_ACP_WLAST(1'B0),
|
||||
.S_AXI_ACP_WVALID(1'B0),
|
||||
.S_AXI_ACP_ARID(3'B0),
|
||||
.S_AXI_ACP_ARPROT(3'B0),
|
||||
.S_AXI_ACP_AWID(3'B0),
|
||||
.S_AXI_ACP_AWPROT(3'B0),
|
||||
.S_AXI_ACP_WID(3'B0),
|
||||
.S_AXI_ACP_ARADDR(32'B0),
|
||||
.S_AXI_ACP_AWADDR(32'B0),
|
||||
.S_AXI_ACP_ARCACHE(4'B0),
|
||||
.S_AXI_ACP_ARLEN(4'B0),
|
||||
.S_AXI_ACP_ARQOS(4'B0),
|
||||
.S_AXI_ACP_AWCACHE(4'B0),
|
||||
.S_AXI_ACP_AWLEN(4'B0),
|
||||
.S_AXI_ACP_AWQOS(4'B0),
|
||||
.S_AXI_ACP_ARBURST(2'B0),
|
||||
.S_AXI_ACP_ARLOCK(2'B0),
|
||||
.S_AXI_ACP_ARSIZE(3'B0),
|
||||
.S_AXI_ACP_AWBURST(2'B0),
|
||||
.S_AXI_ACP_AWLOCK(2'B0),
|
||||
.S_AXI_ACP_AWSIZE(3'B0),
|
||||
.S_AXI_ACP_ARUSER(5'B0),
|
||||
.S_AXI_ACP_AWUSER(5'B0),
|
||||
.S_AXI_ACP_WDATA(64'B0),
|
||||
.S_AXI_ACP_WSTRB(8'B0),
|
||||
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
|
||||
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
|
||||
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
|
||||
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
|
||||
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
|
||||
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
|
||||
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
|
||||
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
|
||||
.S_AXI_HP0_BID(S_AXI_HP0_BID),
|
||||
.S_AXI_HP0_RID(S_AXI_HP0_RID),
|
||||
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
|
||||
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
|
||||
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
|
||||
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
|
||||
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
|
||||
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
|
||||
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
|
||||
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
|
||||
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
|
||||
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
|
||||
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
|
||||
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
|
||||
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
|
||||
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
|
||||
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
|
||||
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
|
||||
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
|
||||
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
|
||||
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
|
||||
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
|
||||
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
|
||||
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
|
||||
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
|
||||
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
|
||||
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
|
||||
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
|
||||
.S_AXI_HP0_WID(S_AXI_HP0_WID),
|
||||
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
|
||||
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
|
||||
.FCLK_CLK1(FCLK_CLK1),
|
||||
|
||||
.FCLK_CLK2(FCLK_CLK2),
|
||||
|
||||
.FCLK_CLK3(FCLK_CLK3),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(),
|
||||
.FCLK_RESET2_N(),
|
||||
.FCLK_RESET3_N(),
|
||||
.IRQ_F2P(IRQ_F2P),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
#ifndef IP_CRC_AXI_MASTER_SYN_HP_PORT_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
#define IP_CRC_AXI_MASTER_SYN_HP_PORT_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class processing_system7_v5_5_tlm;
|
||||
|
||||
class DllExport crc_axi_master_syn_HP_Port_processing_system7_0_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_syn_HP_Port_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_syn_HP_Port_processing_system7_0_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
processing_system7_v5_5_tlm* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
crc_axi_master_syn_HP_Port_processing_system7_0_0_sc(const crc_axi_master_syn_HP_Port_processing_system7_0_0_sc&);
|
||||
const crc_axi_master_syn_HP_Port_processing_system7_0_0_sc& operator=(const crc_axi_master_syn_HP_Port_processing_system7_0_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_CRC_AXI_MASTER_SYN_HP_PORT_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user